From c6ee05eddb26ce1877da9977a77b5aba7aa0b86b Mon Sep 17 00:00:00 2001 From: Stefan Lankes Date: Sun, 21 Feb 2016 11:28:09 +0100 Subject: [PATCH] add debug messages of the configuration of MTRR and PAT --- hermit/arch/x86/include/asm/processor.h | 18 ++++++++++++++++ hermit/arch/x86/kernel/processor.c | 28 +++++++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/hermit/arch/x86/include/asm/processor.h b/hermit/arch/x86/include/asm/processor.h index 37fbb1357..2e38d43ab 100644 --- a/hermit/arch/x86/include/asm/processor.h +++ b/hermit/arch/x86/include/asm/processor.h @@ -201,6 +201,20 @@ extern "C" { #define MSR_IA32_FEATURE_CONTROL 0x0000003a #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 #define MSR_IA32_PERF_STATUS 0x00000198 +#define MSR_IA32_CR_PAT 0x00000277 +#define MSR_MTRRdefType 0x000002ff + +#define MSR_MTRRfix64K_00000 0x00000250 +#define MSR_MTRRfix16K_80000 0x00000258 +#define MSR_MTRRfix16K_A0000 0x00000259 +#define MSR_MTRRfix4K_C0000 0x00000268 +#define MSR_MTRRfix4K_C8000 0x00000269 +#define MSR_MTRRfix4K_D0000 0x0000026a +#define MSR_MTRRfix4K_D8000 0x0000026b +#define MSR_MTRRfix4K_E0000 0x0000026c +#define MSR_MTRRfix4K_E8000 0x0000026d +#define MSR_MTRRfix4K_F0000 0x0000026e +#define MSR_MTRRfix4K_F8000 0x0000026f // MSR EFER bits #define EFER_SCE (1 << 0) @@ -243,6 +257,10 @@ inline static uint32_t has_sse(void) { return (cpu_info.feature1 & CPU_FEATURE_SSE); } +inline static uint32_t has_pat(void) { + return (cpu_info.feature1 & CPU_FEATURE_PAT); +} + inline static uint32_t has_sse2(void) { return (cpu_info.feature1 & CPU_FEATURE_SSE2); } diff --git a/hermit/arch/x86/kernel/processor.c b/hermit/arch/x86/kernel/processor.c index 3222fea01..6e95b422b 100644 --- a/hermit/arch/x86/kernel/processor.c +++ b/hermit/arch/x86/kernel/processor.c @@ -423,10 +423,38 @@ int cpu_detection(void) { kprintf("CR0 0x%llx, CR4 0x%llx\n", read_cr0(), read_cr4()); kprintf("size of xsave_t: %d\n", sizeof(xsave_t)); if (has_msr()) { + uint64_t msr; + kprintf("IA32_MISC_ENABLE 0x%llx\n", rdmsr(MSR_IA32_MISC_ENABLE)); kprintf("IA32_FEATURE_CONTROL 0x%llx\n", rdmsr(MSR_IA32_FEATURE_CONTROL)); //kprintf("IA32_ENERGY_PERF_BIAS 0x%llx\n", rdmsr(MSR_IA32_ENERGY_PERF_BIAS)); //kprintf("IA32_PERF_STATUS 0x%llx\n", rdmsr(MSR_IA32_PERF_STATUS)); + if (has_pat()) { + msr = rdmsr(MSR_IA32_CR_PAT); + + kprintf("MSR_IA32_CR_PAT 0x%llx\n", msr); + kprintf("PAT use per default %s\n", (msr & 0xF) == 0x6 ? "writeback." : "NO writeback!"); + } + + msr = rdmsr(MSR_MTRRdefType); + kprintf("MTRR is %s.\n", (msr & (1 << 11)) ? "enabled" : "disabled"); + kprintf("Fixed-range MTRR is %s.\n", (msr & (1 << 10)) ? "enabled" : "disabled"); + kprintf("MTRR used per default %s\n", (msr & 0xFF) == 0x6 ? "writeback." : "NO writeback!"); +#if 0 + if (msr & (1 << 10)) { + kprintf("MSR_MTRRfix64K_00000 0x%llx\n", rdmsr(MSR_MTRRfix64K_00000)); + kprintf("MSR_MTRRfix16K_80000 0x%llx\n", rdmsr(MSR_MTRRfix16K_80000)); + kprintf("MSR_MTRRfix16K_A0000 0x%llx\n", rdmsr(MSR_MTRRfix16K_A0000)); + kprintf("MSR_MTRRfix4K_C0000 0x%llx\n", rdmsr(MSR_MTRRfix4K_C0000)); + kprintf("MSR_MTRRfix4K_C8000 0x%llx\n", rdmsr(MSR_MTRRfix4K_C8000)); + kprintf("MSR_MTRRfix4K_D0000 0x%llx\n", rdmsr(MSR_MTRRfix4K_D0000)); + kprintf("MSR_MTRRfix4K_D8000 0x%llx\n", rdmsr(MSR_MTRRfix4K_D8000)); + kprintf("MSR_MTRRfix4K_E0000 0x%llx\n", rdmsr(MSR_MTRRfix4K_E0000)); + kprintf("MSR_MTRRfix4K_E8000 0x%llx\n", rdmsr(MSR_MTRRfix4K_E8000)); + kprintf("MSR_MTRRfix4K_F0000 0x%llx\n", rdmsr(MSR_MTRRfix4K_F0000)); + kprintf("MSR_MTRRfix4K_F8000 0x%llx\n", rdmsr(MSR_MTRRfix4K_F8000)); + } +#endif } }