mirror of
https://github.com/hermitcore/libhermit.git
synced 2025-03-09 00:00:03 +01:00
enable the support of dynamic ticks
- a dynamic oneshoot timer is used to wakeup the system instead of a periodic timer
This commit is contained in:
Stefan Lankes
parent
088b496baf
commit
cacd070d24
14 changed files with 142 additions and 114 deletions
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@ -151,6 +151,7 @@ include/hermit/config.inc: include/hermit/config.h
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@awk '/^#define MAX_CORES/{ print "%define MAX_CORES", $$3 }' include/hermit/config.h >> include/hermit/config.inc
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@awk '/^#define KERNEL_STACK_SIZE/{ print "%define KERNEL_STACK_SIZE", $$3 }' include/hermit/config.h >> include/hermit/config.inc
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@awk '/^#define VIDEO_MEM_ADDR/{ print "%define VIDEO_MEM_ADDR", $$3 }' include/hermit/config.h >> include/hermit/config.inc
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@awk '/^#define DYNAMIC_TICKS/{ print "%define DYNAMIC_TICKS", $$3 }' include/hermit/config.h >> include/hermit/config.inc
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%.o : %.asm include/hermit/config.inc
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@echo [ASM] $@
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@ -6,5 +6,4 @@ TODO list
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* prioririty handling in the Pthread library is still missing
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* use gs register to accelerate the access to newlib's reentrant structure
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* revise TLB shoot down
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* revise and check tickless support (the tickless support is currently not tested)
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* revise of the mmnif driver
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@ -55,9 +55,9 @@ extern "C" {
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/// LVT Timer Register
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#define APIC_LVT_T 0x0320
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/// LVT Thermal Sensor Register
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#define APIC_LVT_TSR 0x0330
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#define APIC_LVT_TSR 0x0330
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/// LVT Performance Monitoring Counters Register
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#define APIC_LVT_PMC 0x0340
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#define APIC_LVT_PMC 0x0340
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/// LVT LINT0 Register
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#define APIC_LINT0 0x0350
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/// LVT LINT1 Register
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@ -168,29 +168,29 @@ typedef struct {
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struct {
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uint32_t vector : 8,
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delivery_mode : 3, /* 000: FIXED
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* 001: lowest prio
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* 111: ExtINT
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*/
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* 001: lowest prio
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* 111: ExtINT
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*/
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dest_mode : 1, /* 0: physical, 1: logical */
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delivery_status : 1,
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delivery_status : 1,
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polarity : 1,
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irr : 1,
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irr : 1,
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trigger : 1, /* 0: edge, 1: level */
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mask : 1, /* 0: enabled, 1: disabled */
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__reserved_2 : 15;
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__reserved_2 : 15;
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} bitfield;
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uint32_t whole;
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} lower;
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union {
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struct {
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uint32_t __reserved_1 : 24,
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physical_dest : 4,
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__reserved_2 : 4;
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physical_dest : 4,
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__reserved_2 : 4;
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} physical;
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struct {
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uint32_t __reserved_1 : 24,
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logical_dest : 8;
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logical_dest : 8;
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} logical;
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uint32_t upper;
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} dest;
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@ -203,6 +203,7 @@ int apic_calibration(void);
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int apic_is_enabled(void);
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int apic_enable_timer(void);
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int apic_disable_timer(void);
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int apic_timer_deadline(uint32_t);
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int apic_send_ipi(uint64_t dest, uint8_t irq);
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int ioapic_inton(uint8_t irq, uint8_t apicid);
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int ioapic_intoff(uint8_t irq, uint8_t apicid);
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@ -73,17 +73,11 @@ int irq_uninstall_handler(unsigned int irq);
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*/
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int irq_init(void);
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/** @brief Disable the timer interrupt
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/** @brief Switch from a fix to a dynamic timer period
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*
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* @return 0 on success
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*/
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int disable_timer_irq(void);
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/** @brief Enable the timer interrupt
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*
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* @return 0 on success
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*/
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int enable_timer_irq(void);
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int enable_dynticks(void);
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#ifdef __cplusplus
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}
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@ -622,11 +622,7 @@ static inline size_t lsb(size_t i)
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/// The PAUSE instruction provides a hint to the processor that the code sequence is a spin-wait loop.
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#define PAUSE asm volatile ("pause")
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/// The HALT instruction stops the processor until the next interrupt arrives
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#ifndef CONFIG_TICKLESS
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#define HALT asm volatile ("hlt")
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#else
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#define HALT asm volatile("pause")
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#endif
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/** @brief Init several subsystems
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*
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@ -48,9 +48,6 @@
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*/
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extern const void kernel_start;
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extern void start_tickless(void);
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extern void end_tickless(void);
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#define IOAPIC_ADDR ((size_t) &kernel_start - 2*PAGE_SIZE)
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#define LAPIC_ADDR ((size_t) &kernel_start - 1*PAGE_SIZE)
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#define MAX_APIC_CORES 256
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@ -221,13 +218,28 @@ static inline uint32_t apic_lvt_entries(void)
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return 0;
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}
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int apic_timer_deadline(uint32_t t)
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{
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if (BUILTIN_EXPECT(apic_is_enabled() && icr, 1)) {
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//kprintf("timer oneshot %ld\n", t);
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// create one shot interrup
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lapic_write(APIC_DCR, 0xB); // set it to 1 clock increments
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lapic_write(APIC_LVT_T, 0x7B); // connects the timer to 123 and enables it
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lapic_write(APIC_ICR, icr*t);
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return 0;
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}
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return -EINVAL;
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}
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int apic_disable_timer(void)
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{
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if (BUILTIN_EXPECT(!apic_is_enabled(), 0))
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return -EINVAL;
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lapic_write(APIC_LVT_T, 0x10000); // disable timer interrupt
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start_tickless();
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return 0;
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}
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@ -238,7 +250,6 @@ int apic_enable_timer(void)
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lapic_write(APIC_DCR, 0xB); // set it to 1 clock increments
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lapic_write(APIC_LVT_T, 0x2007B); // connects the timer to 123 and enables it
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lapic_write(APIC_ICR, icr);
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end_tickless();
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return 0;
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}
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@ -54,7 +54,6 @@ align 4
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global boot_processor
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global cpu_online
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global possible_cpus
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global timer_ticks
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global current_boot_id
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global isle
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global possible_isles
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@ -71,7 +70,7 @@ align 4
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boot_processor dd -1
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cpu_online dd 0
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possible_cpus dd 0
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timer_ticks dq 0
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dq 0 ; reserved for future extensions
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current_boot_id dd 0
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isle dd -1
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image_size dq 0
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@ -362,12 +361,19 @@ apic_svr:
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push byte 127
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jmp common_stub
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global wakeup
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align 16
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wakeup:
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push byte 0 ; pseudo error code
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push byte 121
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jmp common_stub
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global mmnif_irq
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align 16
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mmnif_irq:
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push byte 0 ; pseudo error code
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push byte 122
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jmp common_stub
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push byte 0 ; pseudo error code
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push byte 122
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jmp common_stub
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extern irq_handler
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extern get_current_stack
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@ -413,8 +419,10 @@ isrsyscall:
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call [rax*8+syscall_table]
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push rax ; result, which we have to return
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%ifdef DYNAMIC_TICKS
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extern check_ticks
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call check_ticks
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%endif
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extern check_timers
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call check_timers
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@ -43,9 +43,9 @@
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#include <asm/io.h>
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#include <asm/apic.h>
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/*
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/*
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* These are our own ISRs that point to our special IRQ handler
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* instead of the regular 'fault_handler' function
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* instead of the regular 'fault_handler' function
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*/
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extern void irq0(void);
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extern void irq1(void);
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@ -78,6 +78,7 @@ extern void apic_lint0(void);
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extern void apic_lint1(void);
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extern void apic_error(void);
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extern void apic_svr(void);
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extern void wakeup(void);
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extern void mmnif_irq(void);
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#define MAX_HANDLERS 256
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@ -120,7 +121,7 @@ int irq_uninstall_handler(unsigned int irq)
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* actually happening. We send commands to the Programmable
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* Interrupt Controller (PICs - also called the 8259's) in
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* order to make IRQ0 to 15 be remapped to IDT entries 32 to
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* 47
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* 47
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*/
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static int irq_remap(void)
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{
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@ -138,7 +139,7 @@ static int irq_remap(void)
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return 0;
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}
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int disable_timer_irq(void)
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int enable_dynticks(void)
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{
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if (BUILTIN_EXPECT(apic_is_enabled(), 1))
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return apic_disable_timer();
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@ -146,6 +147,7 @@ int disable_timer_irq(void)
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return -EINVAL;
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}
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#if 0
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int enable_timer_irq(void)
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{
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if (BUILTIN_EXPECT(apic_is_enabled(), 1))
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@ -153,6 +155,7 @@ int enable_timer_irq(void)
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return -EINVAL;
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}
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#endif
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/** @brief Remap IRQs and install ISRs in IDT
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*
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@ -218,6 +221,8 @@ static int irq_install(void)
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idt_set_gate(113, (size_t)irq81, KERNEL_CODE_SELECTOR,
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IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
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idt_set_gate(121, (size_t)wakeup, KERNEL_CODE_SELECTOR,
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IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
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idt_set_gate(122, (size_t)mmnif_irq, KERNEL_CODE_SELECTOR,
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IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
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@ -250,10 +255,10 @@ int irq_init(void)
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* Each of the IRQ ISRs point to this function, rather than
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* the 'fault_handler' in 'isrs.c'. The IRQ Controllers need
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* to be told when you are done servicing them, so you need
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* to send them an "End of Interrupt" command. If we use the PIC
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* instead of the APIC, we have two 8259 chips: The first one
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* exists at 0x20, the second one exists at 0xA0. If the second
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* controller (an IRQ from 8 to 15) gets an interrupt, you need to
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* to send them an "End of Interrupt" command. If we use the PIC
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* instead of the APIC, we have two 8259 chips: The first one
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* exists at 0x20, the second one exists at 0xA0. If the second
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* controller (an IRQ from 8 to 15) gets an interrupt, you need to
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* acknowledge the interrupt at BOTH controllers, otherwise, you
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* only send an EOI command to the first controller. If you don't send
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* an EOI, it won't raise any more IRQs.
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@ -270,10 +275,10 @@ size_t** irq_handler(struct state *s)
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check_workqueues_in_irqhandler(s->int_no);
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/*
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/*
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* Find out if we have a custom handler to run for this
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* IRQ and then finally, run it
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*/
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* IRQ and then finally, run it
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*/
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if (BUILTIN_EXPECT(s->int_no < MAX_HANDLERS, 1)) {
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handler = irq_routines[s->int_no];
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if (handler)
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@ -36,55 +36,28 @@
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#include <asm/irqflags.h>
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#include <asm/io.h>
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/*
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/*
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* This will keep track of how many ticks the system
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* has been running for
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* has been running for
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*/
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extern volatile uint64_t timer_ticks;
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DEFINE_PER_CORE(uint64_t, timer_ticks, 0);
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extern uint32_t cpu_freq;
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extern int32_t boot_processor;
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static int8_t use_tickless = 0;
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static uint64_t last_rdtsc = 0;
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#if MAX_CORES > 1
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static spinlock_irqsave_t ticks_lock = SPINLOCK_IRQSAVE_INIT;
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#endif
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void start_tickless(void)
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{
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use_tickless = 1;
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if (has_rdtscp())
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last_rdtsc = rdtscp(NULL);
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else
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last_rdtsc = rdtsc();
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rmb();
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}
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void end_tickless(void)
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{
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use_tickless = 0;
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last_rdtsc = 0;
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}
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#ifdef DYNAMIC_TICKS
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DEFINE_PER_CORE(uint64_t, last_rdtsc, 0);
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void check_ticks(void)
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{
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if (!use_tickless)
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return;
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#if MAX_CORES > 1
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spinlock_irqsave_lock(&ticks_lock);
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#endif
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if (has_rdtscp()){
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uint64_t curr_rdtsc = rdtscp(NULL);
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uint64_t diff;
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rmb();
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diff = ((curr_rdtsc - last_rdtsc) * (uint64_t)TIMER_FREQ) / (1000000ULL*(uint64_t)get_cpu_frequency());
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diff = ((curr_rdtsc - per_core(last_rdtsc)) * (uint64_t)TIMER_FREQ) / (1000000ULL*(uint64_t)get_cpu_frequency());
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if (diff > 0) {
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timer_ticks += diff;
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last_rdtsc = curr_rdtsc;
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set_per_core(timer_ticks, per_core(timer_ticks) + diff);
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set_per_core(last_rdtsc, curr_rdtsc);
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rmb();
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}
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} else {
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@ -92,37 +65,31 @@ void check_ticks(void)
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uint64_t diff;
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rmb();
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diff = ((curr_rdtsc - last_rdtsc) * (uint64_t)TIMER_FREQ) / (1000000ULL*(uint64_t)get_cpu_frequency());
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diff = ((curr_rdtsc - per_core(last_rdtsc)) * (uint64_t)TIMER_FREQ) / (1000000ULL*(uint64_t)get_cpu_frequency());
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if (diff > 0) {
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timer_ticks += diff;
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last_rdtsc = curr_rdtsc;
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set_per_core(timer_ticks, per_core(timer_ticks) + diff);
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set_per_core(last_rdtsc, curr_rdtsc);
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rmb();
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}
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}
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#if MAX_CORES > 1
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spinlock_irqsave_unlock(&ticks_lock);
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}
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#endif
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}
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uint64_t get_clock_tick(void)
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static void wakeup_handler(struct state *s)
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{
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return timer_ticks;
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}
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/*
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/*
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* Handles the timer. In this case, it's very simple: We
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* increment the 'timer_ticks' variable every time the
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* timer fires.
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* timer fires.
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*/
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static void timer_handler(struct state *s)
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{
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#if MAX_CORES > 1
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if (CORE_ID == boot_processor)
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#ifndef DYNAMIC_TICKS
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/* Increment our 'tick counter' */
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set_per_core(timer_ticks, per_core(timer_ticks)+1);
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#endif
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/* Increment our 'tick counter' */
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timer_ticks++;
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#if 0
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/*
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@ -138,7 +105,7 @@ static void timer_handler(struct state *s)
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int timer_wait(unsigned int ticks)
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{
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uint64_t eticks = timer_ticks + ticks;
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task_t* curr_task = per_core(current_task);
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if (curr_task->status == TASK_IDLE)
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@ -173,18 +140,26 @@ int timer_wait(unsigned int ticks)
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while(rdtsc() - start < 1000000) ; \
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} while (0)
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/*
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/*
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* Sets up the system clock by installing the timer handler
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* into IRQ0
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* into IRQ0
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*/
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int timer_init(void)
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{
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/*
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/*
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* Installs 'timer_handler' for the PIC and APIC timer,
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* only one handler will be later used.
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*/
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irq_install_handler(32, timer_handler);
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irq_install_handler(123, timer_handler);
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irq_install_handler(121, wakeup_handler);
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#ifdef DYNAMIC_TICKS
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if (has_rdtscp())
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last_rdtsc = rdtscp(NULL);
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else
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last_rdtsc = rdtsc();
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#endif
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if (cpu_freq) // do we need to configure the timer?
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return 0;
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|
|
@ -48,12 +48,11 @@ extern "C" {
|
|||
|
||||
#define BYTE_ORDER LITTLE_ENDIAN
|
||||
|
||||
//#define CONFIG_TICKLESS
|
||||
#define DYNAMIC_TICKS
|
||||
|
||||
#define BUILTIN_EXPECT(exp, b) __builtin_expect((exp), (b))
|
||||
//#define BUILTIN_EXPECT(exp, b) (exp)
|
||||
#define NORETURN __attribute__((noreturn))
|
||||
#define STDCALL __attribute__((stdcall))
|
||||
|
||||
#define HAVE_ARCH_MEMSET
|
||||
#define HAVE_ARCH_MEMCPY
|
||||
|
|
|
|||
|
|
@ -230,13 +230,17 @@ void NORETURN leave_kernel_task(void);
|
|||
* */
|
||||
void check_scheduling(void);
|
||||
|
||||
#ifdef DYNAMIC_TICKS
|
||||
/** @brief check, if the tick counter has to be updated
|
||||
* */
|
||||
void check_ticks(void);
|
||||
#endif
|
||||
|
||||
static inline void check_workqueues_in_irqhandler(int irq)
|
||||
{
|
||||
#ifdef DYNAMIC_TICKS
|
||||
check_ticks();
|
||||
#endif
|
||||
check_timers();
|
||||
|
||||
if (irq < 0)
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/**
|
||||
/**
|
||||
* @author Stefan Lankes
|
||||
* @file include/hermit/time.h
|
||||
* @brief Time related functions
|
||||
|
|
@ -34,6 +34,8 @@
|
|||
#ifndef __TIME_H__
|
||||
#define __TIME_H__
|
||||
|
||||
#include <asm/apic.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
|
@ -47,7 +49,7 @@ struct tms {
|
|||
clock_t tms_cstime;
|
||||
};
|
||||
|
||||
/** @brief Initialize Timer interrupts
|
||||
/** @brief Initialize Timer interrupts
|
||||
*
|
||||
* This procedure installs IRQ handlers for timer interrupts
|
||||
*/
|
||||
|
|
@ -61,10 +63,15 @@ int timer_init(void);
|
|||
*/
|
||||
int timer_wait(unsigned int ticks);
|
||||
|
||||
DECLARE_PER_CORE(uint64_t, timer_ticks);
|
||||
|
||||
/** @brief Returns the current number of ticks.
|
||||
* @return Current number of ticks
|
||||
*/
|
||||
uint64_t get_clock_tick(void);
|
||||
static inline uint64_t get_clock_tick(void)
|
||||
{
|
||||
return per_core(timer_ticks);
|
||||
}
|
||||
|
||||
/** @brief sleep some seconds
|
||||
*
|
||||
|
|
@ -74,6 +81,8 @@ uint64_t get_clock_tick(void);
|
|||
*/
|
||||
static inline void sleep(unsigned int sec) { timer_wait(sec*TIMER_FREQ); }
|
||||
|
||||
static inline int timer_deadline(uint32_t t) { return apic_timer_deadline(t); }
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -195,8 +195,8 @@ int smp_main(void)
|
|||
{
|
||||
int32_t cpu = atomic_int32_inc(&cpu_online);
|
||||
|
||||
#ifdef CONFIG_TICKLESS
|
||||
disable_timer_irq();
|
||||
#ifdef DYNAMIC_TICKS
|
||||
enable_dynticks();
|
||||
#endif
|
||||
|
||||
/* wait for the other cpus */
|
||||
|
|
@ -324,8 +324,8 @@ int main(void)
|
|||
list_fs(fs_root, 1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TICKLESS
|
||||
disable_timer_irq();
|
||||
#ifdef DYNAMIC_TICKS
|
||||
enable_dynticks();
|
||||
#endif
|
||||
|
||||
/* wait for the other cpus */
|
||||
|
|
|
|||
|
|
@ -79,7 +79,11 @@ void check_scheduling(void)
|
|||
|
||||
uint32_t get_highest_priority(void)
|
||||
{
|
||||
return msb(readyqueues[CORE_ID].prio_bitmap);
|
||||
uint32_t prio = msb(readyqueues[CORE_ID].prio_bitmap);
|
||||
|
||||
if (prio > MAX_PRIO)
|
||||
return 0;
|
||||
return prio;
|
||||
}
|
||||
|
||||
int multitasking_init(void)
|
||||
|
|
@ -350,6 +354,9 @@ out:
|
|||
if (ret)
|
||||
kfree(stack);
|
||||
|
||||
if (core_id != CORE_ID)
|
||||
apic_send_ipi(core_id, 121);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -448,6 +455,9 @@ out:
|
|||
kfree(counter);
|
||||
}
|
||||
|
||||
if (core_id != CORE_ID)
|
||||
apic_send_ipi(core_id, 121);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -527,6 +537,12 @@ int wakeup_task(tid_t id)
|
|||
readyqueues[core_id].queue[prio-1].last = task;
|
||||
}
|
||||
spinlock_irqsave_unlock(&readyqueues[core_id].lock);
|
||||
|
||||
#ifdef DYNAMIC_TICKS
|
||||
// send IPI to be sure that the scheuler recognize the new task
|
||||
if (core_id != CORE_ID)
|
||||
apic_send_ipi(core_id, 121);
|
||||
#endif
|
||||
}
|
||||
|
||||
irq_nested_enable(flags);
|
||||
|
|
@ -636,6 +652,9 @@ int set_timer(uint64_t deadline)
|
|||
if (!tmp) {
|
||||
readyqueues[core_id].timers.first = readyqueues[core_id].timers.last = curr_task;
|
||||
curr_task->prev = curr_task->next = NULL;
|
||||
#ifdef DYNAMIC_TICKS
|
||||
timer_deadline(deadline-get_clock_tick());
|
||||
#endif
|
||||
} else {
|
||||
while(tmp && (deadline >= tmp->timeout))
|
||||
tmp = tmp->next;
|
||||
|
|
@ -655,8 +674,12 @@ int set_timer(uint64_t deadline)
|
|||
tmp->prev = curr_task;
|
||||
if (curr_task->prev)
|
||||
curr_task->prev->next = curr_task;
|
||||
if (readyqueues[core_id].timers.first == tmp)
|
||||
if (readyqueues[core_id].timers.first == tmp) {
|
||||
readyqueues[core_id].timers.first = curr_task;
|
||||
#ifdef DYNAMIC_TICKS
|
||||
timer_deadline(deadline-get_clock_tick());
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -684,10 +707,13 @@ void check_timers(void)
|
|||
|
||||
// remove timer from queue
|
||||
readyqueues[core_id].timers.first = readyqueues[core_id].timers.first->next;
|
||||
if (readyqueues[core_id].timers.first)
|
||||
if (readyqueues[core_id].timers.first) {
|
||||
readyqueues[core_id].timers.first->prev = NULL;
|
||||
else
|
||||
readyqueues[core_id].timers.last = NULL;
|
||||
#ifdef DYNAMIC_TICKS
|
||||
if (readyqueues[core_id].timers.first->timeout > get_clock_tick())
|
||||
timer_deadline(readyqueues[core_id].timers.first->timeout-current_tick);
|
||||
#endif
|
||||
} else readyqueues[core_id].timers.last = NULL;
|
||||
task->flags &= ~TASK_TIMER;
|
||||
|
||||
// wakeup task
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue