From ef01dd009d40815b9f2f05044053a82bc7c5d986 Mon Sep 17 00:00:00 2001 From: Stefan Lankes Date: Fri, 19 Feb 2016 23:33:19 +0100 Subject: [PATCH] besure that HermitCore enbales the cache --- hermit/arch/x86/include/asm/processor.h | 3 +++ hermit/arch/x86/kernel/processor.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/hermit/arch/x86/include/asm/processor.h b/hermit/arch/x86/include/asm/processor.h index cc1073e86..c5697a71e 100644 --- a/hermit/arch/x86/include/asm/processor.h +++ b/hermit/arch/x86/include/asm/processor.h @@ -196,8 +196,11 @@ extern "C" { #define MSR_XAPIC_ENABLE (1UL << 11) #define MSR_X2APIC_ENABLE (1UL << 10) + #define MSR_IA32_MISC_ENABLE 0x000001a0 #define MSR_IA32_FEATURE_CONTROL 0x0000003a +#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 +#define MSR_IA32_PERF_STATUS 0x00000198 // MSR EFER bits #define EFER_SCE (1 << 0) diff --git a/hermit/arch/x86/kernel/processor.c b/hermit/arch/x86/kernel/processor.c index c2716d5c7..3222fea01 100644 --- a/hermit/arch/x86/kernel/processor.c +++ b/hermit/arch/x86/kernel/processor.c @@ -260,6 +260,7 @@ int cpu_detection(void) { cr0 |= CR0_AM; cr0 |= CR0_NE; cr0 |= CR0_MP; + cr0 &= ~(CR0_CD|CR0_NW); write_cr0(cr0); cr4 = read_cr4(); @@ -424,6 +425,8 @@ int cpu_detection(void) { if (has_msr()) { kprintf("IA32_MISC_ENABLE 0x%llx\n", rdmsr(MSR_IA32_MISC_ENABLE)); kprintf("IA32_FEATURE_CONTROL 0x%llx\n", rdmsr(MSR_IA32_FEATURE_CONTROL)); + //kprintf("IA32_ENERGY_PERF_BIAS 0x%llx\n", rdmsr(MSR_IA32_ENERGY_PERF_BIAS)); + //kprintf("IA32_PERF_STATUS 0x%llx\n", rdmsr(MSR_IA32_PERF_STATUS)); } }