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956 lines
24 KiB
C
956 lines
24 KiB
C
/*
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* Copyright (c) 2005 Topspin Communications. All rights reserved.
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* Copyright (c) 2005 Mellanox Technologies Ltd. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <config.h>
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#include <endian.h>
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#include <stdlib.h>
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#include <pthread.h>
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#include <string.h>
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#include <util/compiler.h>
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#include "mthca.h"
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#include "doorbell.h"
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#include "wqe.h"
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enum {
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MTHCA_SEND_DOORBELL_FENCE = 1 << 5
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};
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static const uint8_t mthca_opcode[] = {
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[IBV_WR_SEND] = MTHCA_OPCODE_SEND,
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[IBV_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM,
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[IBV_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE,
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[IBV_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM,
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[IBV_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ,
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[IBV_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS,
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[IBV_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
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};
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static void *get_recv_wqe(struct mthca_qp *qp, int n)
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{
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return qp->buf.buf + (n << qp->rq.wqe_shift);
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}
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static void *get_send_wqe(struct mthca_qp *qp, int n)
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{
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return qp->buf.buf + qp->send_wqe_offset + (n << qp->sq.wqe_shift);
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}
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void mthca_init_qp_indices(struct mthca_qp *qp)
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{
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qp->sq.next_ind = 0;
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qp->sq.last_comp = qp->sq.max - 1;
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qp->sq.head = 0;
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qp->sq.tail = 0;
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qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
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qp->rq.next_ind = 0;
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qp->rq.last_comp = qp->rq.max - 1;
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qp->rq.head = 0;
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qp->rq.tail = 0;
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qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
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}
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static inline int wq_overflow(struct mthca_wq *wq, int nreq, struct mthca_cq *cq)
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{
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unsigned cur;
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cur = wq->head - wq->tail;
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if (cur + nreq < wq->max)
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return 0;
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pthread_spin_lock(&cq->lock);
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cur = wq->head - wq->tail;
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pthread_spin_unlock(&cq->lock);
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return cur + nreq >= wq->max;
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}
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int mthca_tavor_post_send(struct ibv_qp *ibqp, struct ibv_send_wr *wr,
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struct ibv_send_wr **bad_wr)
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{
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struct mthca_qp *qp = to_mqp(ibqp);
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void *wqe, *prev_wqe;
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int ind;
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int nreq;
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int ret = 0;
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int size;
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int size0 = 0;
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int i;
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uint32_t uninitialized_var(f0);
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uint32_t uninitialized_var(op0);
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pthread_spin_lock(&qp->sq.lock);
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udma_to_device_barrier();
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ind = qp->sq.next_ind;
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for (nreq = 0; wr; ++nreq, wr = wr->next) {
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if (wq_overflow(&qp->sq, nreq, to_mcq(qp->ibv_qp.send_cq))) {
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ret = -1;
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*bad_wr = wr;
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goto out;
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}
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wqe = get_send_wqe(qp, ind);
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prev_wqe = qp->sq.last;
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qp->sq.last = wqe;
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((struct mthca_next_seg *) wqe)->nda_op = 0;
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((struct mthca_next_seg *) wqe)->ee_nds = 0;
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((struct mthca_next_seg *) wqe)->flags =
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((wr->send_flags & IBV_SEND_SIGNALED) ?
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htobe32(MTHCA_NEXT_CQ_UPDATE) : 0) |
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((wr->send_flags & IBV_SEND_SOLICITED) ?
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htobe32(MTHCA_NEXT_SOLICIT) : 0) |
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htobe32(1);
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if (wr->opcode == IBV_WR_SEND_WITH_IMM ||
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wr->opcode == IBV_WR_RDMA_WRITE_WITH_IMM)
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((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
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wqe += sizeof (struct mthca_next_seg);
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size = sizeof (struct mthca_next_seg) / 16;
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switch (ibqp->qp_type) {
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case IBV_QPT_RC:
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switch (wr->opcode) {
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case IBV_WR_ATOMIC_CMP_AND_SWP:
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case IBV_WR_ATOMIC_FETCH_AND_ADD:
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((struct mthca_raddr_seg *) wqe)->raddr =
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htobe64(wr->wr.atomic.remote_addr);
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((struct mthca_raddr_seg *) wqe)->rkey =
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htobe32(wr->wr.atomic.rkey);
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((struct mthca_raddr_seg *) wqe)->reserved = 0;
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wqe += sizeof (struct mthca_raddr_seg);
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if (wr->opcode == IBV_WR_ATOMIC_CMP_AND_SWP) {
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((struct mthca_atomic_seg *) wqe)->swap_add =
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htobe64(wr->wr.atomic.swap);
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((struct mthca_atomic_seg *) wqe)->compare =
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htobe64(wr->wr.atomic.compare_add);
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} else {
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((struct mthca_atomic_seg *) wqe)->swap_add =
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htobe64(wr->wr.atomic.compare_add);
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((struct mthca_atomic_seg *) wqe)->compare = 0;
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}
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wqe += sizeof (struct mthca_atomic_seg);
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size += (sizeof (struct mthca_raddr_seg) +
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sizeof (struct mthca_atomic_seg)) / 16;
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break;
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case IBV_WR_RDMA_WRITE:
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case IBV_WR_RDMA_WRITE_WITH_IMM:
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case IBV_WR_RDMA_READ:
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((struct mthca_raddr_seg *) wqe)->raddr =
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htobe64(wr->wr.rdma.remote_addr);
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((struct mthca_raddr_seg *) wqe)->rkey =
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htobe32(wr->wr.rdma.rkey);
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((struct mthca_raddr_seg *) wqe)->reserved = 0;
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wqe += sizeof (struct mthca_raddr_seg);
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size += sizeof (struct mthca_raddr_seg) / 16;
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break;
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default:
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/* No extra segments required for sends */
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break;
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}
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break;
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case IBV_QPT_UC:
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switch (wr->opcode) {
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case IBV_WR_RDMA_WRITE:
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case IBV_WR_RDMA_WRITE_WITH_IMM:
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((struct mthca_raddr_seg *) wqe)->raddr =
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htobe64(wr->wr.rdma.remote_addr);
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((struct mthca_raddr_seg *) wqe)->rkey =
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htobe32(wr->wr.rdma.rkey);
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((struct mthca_raddr_seg *) wqe)->reserved = 0;
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wqe += sizeof (struct mthca_raddr_seg);
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size += sizeof (struct mthca_raddr_seg) / 16;
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break;
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default:
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/* No extra segments required for sends */
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break;
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}
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break;
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case IBV_QPT_UD:
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((struct mthca_tavor_ud_seg *) wqe)->lkey =
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htobe32(to_mah(wr->wr.ud.ah)->key);
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((struct mthca_tavor_ud_seg *) wqe)->av_addr =
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htobe64((uintptr_t) to_mah(wr->wr.ud.ah)->av);
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((struct mthca_tavor_ud_seg *) wqe)->dqpn =
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htobe32(wr->wr.ud.remote_qpn);
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((struct mthca_tavor_ud_seg *) wqe)->qkey =
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htobe32(wr->wr.ud.remote_qkey);
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wqe += sizeof (struct mthca_tavor_ud_seg);
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size += sizeof (struct mthca_tavor_ud_seg) / 16;
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break;
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default:
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break;
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}
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if (wr->num_sge > qp->sq.max_gs) {
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ret = -1;
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*bad_wr = wr;
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goto out;
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}
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if (wr->send_flags & IBV_SEND_INLINE) {
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if (wr->num_sge) {
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struct mthca_inline_seg *seg = wqe;
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int s = 0;
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wqe += sizeof *seg;
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for (i = 0; i < wr->num_sge; ++i) {
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struct ibv_sge *sge = &wr->sg_list[i];
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s += sge->length;
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if (s > qp->max_inline_data) {
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ret = -1;
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*bad_wr = wr;
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goto out;
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}
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memcpy(wqe, (void *) (intptr_t) sge->addr,
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sge->length);
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wqe += sge->length;
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}
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seg->byte_count = htobe32(MTHCA_INLINE_SEG | s);
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size += align(s + sizeof *seg, 16) / 16;
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}
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} else {
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struct mthca_data_seg *seg;
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for (i = 0; i < wr->num_sge; ++i) {
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seg = wqe;
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seg->byte_count = htobe32(wr->sg_list[i].length);
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seg->lkey = htobe32(wr->sg_list[i].lkey);
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seg->addr = htobe64(wr->sg_list[i].addr);
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wqe += sizeof *seg;
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}
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size += wr->num_sge * (sizeof *seg / 16);
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}
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qp->wrid[ind + qp->rq.max] = wr->wr_id;
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if (wr->opcode >= sizeof mthca_opcode / sizeof mthca_opcode[0]) {
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ret = -1;
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*bad_wr = wr;
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goto out;
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}
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((struct mthca_next_seg *) prev_wqe)->nda_op =
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htobe32(((ind << qp->sq.wqe_shift) +
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qp->send_wqe_offset) |
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mthca_opcode[wr->opcode]);
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/*
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* Make sure that nda_op is written before setting ee_nds.
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*/
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udma_ordering_write_barrier();
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((struct mthca_next_seg *) prev_wqe)->ee_nds =
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htobe32((size0 ? 0 : MTHCA_NEXT_DBD) | size |
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((wr->send_flags & IBV_SEND_FENCE) ?
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MTHCA_NEXT_FENCE : 0));
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if (!size0) {
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size0 = size;
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op0 = mthca_opcode[wr->opcode];
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f0 = wr->send_flags & IBV_SEND_FENCE ?
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MTHCA_SEND_DOORBELL_FENCE : 0;
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}
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++ind;
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if (ind >= qp->sq.max)
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ind -= qp->sq.max;
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}
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out:
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if (nreq) {
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uint32_t doorbell[2];
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doorbell[0] = ((qp->sq.next_ind << qp->sq.wqe_shift) +
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qp->send_wqe_offset) |
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f0 | op0;
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doorbell[1] = (ibqp->qp_num << 8) | size0;
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udma_to_device_barrier();
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mthca_write64(doorbell, to_mctx(ibqp->context)->uar +
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MTHCA_SEND_DOORBELL);
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}
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qp->sq.next_ind = ind;
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qp->sq.head += nreq;
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pthread_spin_unlock(&qp->sq.lock);
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return ret;
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}
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int mthca_tavor_post_recv(struct ibv_qp *ibqp, struct ibv_recv_wr *wr,
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struct ibv_recv_wr **bad_wr)
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{
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struct mthca_qp *qp = to_mqp(ibqp);
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uint32_t doorbell[2];
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int ret = 0;
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int nreq;
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int i;
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int size;
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int size0 = 0;
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int ind;
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void *wqe;
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void *prev_wqe;
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pthread_spin_lock(&qp->rq.lock);
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ind = qp->rq.next_ind;
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for (nreq = 0; wr; wr = wr->next) {
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if (wq_overflow(&qp->rq, nreq, to_mcq(qp->ibv_qp.recv_cq))) {
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ret = -1;
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*bad_wr = wr;
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goto out;
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}
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wqe = get_recv_wqe(qp, ind);
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prev_wqe = qp->rq.last;
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qp->rq.last = wqe;
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((struct mthca_next_seg *) wqe)->ee_nds =
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htobe32(MTHCA_NEXT_DBD);
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((struct mthca_next_seg *) wqe)->flags =
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htobe32(MTHCA_NEXT_CQ_UPDATE);
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wqe += sizeof (struct mthca_next_seg);
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size = sizeof (struct mthca_next_seg) / 16;
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if (wr->num_sge > qp->rq.max_gs) {
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ret = -1;
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*bad_wr = wr;
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goto out;
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}
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for (i = 0; i < wr->num_sge; ++i) {
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((struct mthca_data_seg *) wqe)->byte_count =
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htobe32(wr->sg_list[i].length);
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((struct mthca_data_seg *) wqe)->lkey =
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htobe32(wr->sg_list[i].lkey);
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((struct mthca_data_seg *) wqe)->addr =
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htobe64(wr->sg_list[i].addr);
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wqe += sizeof (struct mthca_data_seg);
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size += sizeof (struct mthca_data_seg) / 16;
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}
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qp->wrid[ind] = wr->wr_id;
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((struct mthca_next_seg *) prev_wqe)->ee_nds =
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htobe32(MTHCA_NEXT_DBD | size);
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if (!size0)
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size0 = size;
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++ind;
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if (ind >= qp->rq.max)
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ind -= qp->rq.max;
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++nreq;
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if (nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB) {
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nreq = 0;
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doorbell[0] =
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(qp->rq.next_ind << qp->rq.wqe_shift) | size0;
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doorbell[1] = ibqp->qp_num << 8;
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/*
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* Make sure that descriptors are written
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* before doorbell is rung.
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*/
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udma_to_device_barrier();
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mthca_write64(doorbell, to_mctx(ibqp->context)->uar +
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MTHCA_RECV_DOORBELL);
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qp->rq.next_ind = ind;
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qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
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size0 = 0;
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}
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}
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out:
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if (nreq) {
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doorbell[0] = (qp->rq.next_ind << qp->rq.wqe_shift) | size0;
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doorbell[1] = (ibqp->qp_num << 8) | nreq;
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/*
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* Make sure that descriptors are written before
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* doorbell is rung.
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*/
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udma_to_device_barrier();
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mthca_write64(doorbell, to_mctx(ibqp->context)->uar +
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MTHCA_RECV_DOORBELL);
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}
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qp->rq.next_ind = ind;
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qp->rq.head += nreq;
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pthread_spin_unlock(&qp->rq.lock);
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return ret;
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}
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int mthca_arbel_post_send(struct ibv_qp *ibqp, struct ibv_send_wr *wr,
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struct ibv_send_wr **bad_wr)
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{
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struct mthca_qp *qp = to_mqp(ibqp);
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uint32_t doorbell[2];
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void *wqe, *prev_wqe;
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int ind;
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int nreq;
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int ret = 0;
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int size;
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int size0 = 0;
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int i;
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uint32_t uninitialized_var(f0);
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uint32_t uninitialized_var(op0);
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pthread_spin_lock(&qp->sq.lock);
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/* XXX check that state is OK to post send */
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ind = qp->sq.head & (qp->sq.max - 1);
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for (nreq = 0; wr; ++nreq, wr = wr->next) {
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if (nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB) {
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nreq = 0;
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doorbell[0] = (MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
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((qp->sq.head & 0xffff) << 8) | f0 | op0;
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doorbell[1] = (ibqp->qp_num << 8) | size0;
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qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
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/*
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* Make sure that descriptors are written before
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* doorbell record.
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*/
|
|
udma_to_device_barrier();
|
|
*qp->sq.db = htobe32(qp->sq.head & 0xffff);
|
|
|
|
/*
|
|
* Make sure doorbell record is written before we
|
|
* write MMIO send doorbell.
|
|
*/
|
|
mmio_ordered_writes_hack();
|
|
mthca_write64(doorbell, to_mctx(ibqp->context)->uar +
|
|
MTHCA_SEND_DOORBELL);
|
|
|
|
size0 = 0;
|
|
}
|
|
|
|
if (wq_overflow(&qp->sq, nreq, to_mcq(qp->ibv_qp.send_cq))) {
|
|
ret = -1;
|
|
*bad_wr = wr;
|
|
goto out;
|
|
}
|
|
|
|
wqe = get_send_wqe(qp, ind);
|
|
prev_wqe = qp->sq.last;
|
|
qp->sq.last = wqe;
|
|
|
|
((struct mthca_next_seg *) wqe)->flags =
|
|
((wr->send_flags & IBV_SEND_SIGNALED) ?
|
|
htobe32(MTHCA_NEXT_CQ_UPDATE) : 0) |
|
|
((wr->send_flags & IBV_SEND_SOLICITED) ?
|
|
htobe32(MTHCA_NEXT_SOLICIT) : 0) |
|
|
htobe32(1);
|
|
if (wr->opcode == IBV_WR_SEND_WITH_IMM ||
|
|
wr->opcode == IBV_WR_RDMA_WRITE_WITH_IMM)
|
|
((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
|
|
|
|
wqe += sizeof (struct mthca_next_seg);
|
|
size = sizeof (struct mthca_next_seg) / 16;
|
|
|
|
switch (ibqp->qp_type) {
|
|
case IBV_QPT_RC:
|
|
switch (wr->opcode) {
|
|
case IBV_WR_ATOMIC_CMP_AND_SWP:
|
|
case IBV_WR_ATOMIC_FETCH_AND_ADD:
|
|
((struct mthca_raddr_seg *) wqe)->raddr =
|
|
htobe64(wr->wr.atomic.remote_addr);
|
|
((struct mthca_raddr_seg *) wqe)->rkey =
|
|
htobe32(wr->wr.atomic.rkey);
|
|
((struct mthca_raddr_seg *) wqe)->reserved = 0;
|
|
|
|
wqe += sizeof (struct mthca_raddr_seg);
|
|
|
|
if (wr->opcode == IBV_WR_ATOMIC_CMP_AND_SWP) {
|
|
((struct mthca_atomic_seg *) wqe)->swap_add =
|
|
htobe64(wr->wr.atomic.swap);
|
|
((struct mthca_atomic_seg *) wqe)->compare =
|
|
htobe64(wr->wr.atomic.compare_add);
|
|
} else {
|
|
((struct mthca_atomic_seg *) wqe)->swap_add =
|
|
htobe64(wr->wr.atomic.compare_add);
|
|
((struct mthca_atomic_seg *) wqe)->compare = 0;
|
|
}
|
|
|
|
wqe += sizeof (struct mthca_atomic_seg);
|
|
size += (sizeof (struct mthca_raddr_seg) +
|
|
sizeof (struct mthca_atomic_seg)) / 16;
|
|
break;
|
|
|
|
case IBV_WR_RDMA_WRITE:
|
|
case IBV_WR_RDMA_WRITE_WITH_IMM:
|
|
case IBV_WR_RDMA_READ:
|
|
((struct mthca_raddr_seg *) wqe)->raddr =
|
|
htobe64(wr->wr.rdma.remote_addr);
|
|
((struct mthca_raddr_seg *) wqe)->rkey =
|
|
htobe32(wr->wr.rdma.rkey);
|
|
((struct mthca_raddr_seg *) wqe)->reserved = 0;
|
|
wqe += sizeof (struct mthca_raddr_seg);
|
|
size += sizeof (struct mthca_raddr_seg) / 16;
|
|
break;
|
|
|
|
default:
|
|
/* No extra segments required for sends */
|
|
break;
|
|
}
|
|
|
|
break;
|
|
|
|
case IBV_QPT_UC:
|
|
switch (wr->opcode) {
|
|
case IBV_WR_RDMA_WRITE:
|
|
case IBV_WR_RDMA_WRITE_WITH_IMM:
|
|
((struct mthca_raddr_seg *) wqe)->raddr =
|
|
htobe64(wr->wr.rdma.remote_addr);
|
|
((struct mthca_raddr_seg *) wqe)->rkey =
|
|
htobe32(wr->wr.rdma.rkey);
|
|
((struct mthca_raddr_seg *) wqe)->reserved = 0;
|
|
wqe += sizeof (struct mthca_raddr_seg);
|
|
size += sizeof (struct mthca_raddr_seg) / 16;
|
|
break;
|
|
|
|
default:
|
|
/* No extra segments required for sends */
|
|
break;
|
|
}
|
|
|
|
break;
|
|
|
|
case IBV_QPT_UD:
|
|
memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
|
|
to_mah(wr->wr.ud.ah)->av, sizeof (struct mthca_av));
|
|
((struct mthca_arbel_ud_seg *) wqe)->dqpn =
|
|
htobe32(wr->wr.ud.remote_qpn);
|
|
((struct mthca_arbel_ud_seg *) wqe)->qkey =
|
|
htobe32(wr->wr.ud.remote_qkey);
|
|
|
|
wqe += sizeof (struct mthca_arbel_ud_seg);
|
|
size += sizeof (struct mthca_arbel_ud_seg) / 16;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (wr->num_sge > qp->sq.max_gs) {
|
|
ret = -1;
|
|
*bad_wr = wr;
|
|
goto out;
|
|
}
|
|
|
|
if (wr->send_flags & IBV_SEND_INLINE) {
|
|
if (wr->num_sge) {
|
|
struct mthca_inline_seg *seg = wqe;
|
|
int s = 0;
|
|
|
|
wqe += sizeof *seg;
|
|
for (i = 0; i < wr->num_sge; ++i) {
|
|
struct ibv_sge *sge = &wr->sg_list[i];
|
|
|
|
s += sge->length;
|
|
|
|
if (s > qp->max_inline_data) {
|
|
ret = -1;
|
|
*bad_wr = wr;
|
|
goto out;
|
|
}
|
|
|
|
memcpy(wqe, (void *) (uintptr_t) sge->addr,
|
|
sge->length);
|
|
wqe += sge->length;
|
|
}
|
|
|
|
seg->byte_count = htobe32(MTHCA_INLINE_SEG | s);
|
|
size += align(s + sizeof *seg, 16) / 16;
|
|
}
|
|
} else {
|
|
struct mthca_data_seg *seg;
|
|
|
|
for (i = 0; i < wr->num_sge; ++i) {
|
|
seg = wqe;
|
|
seg->byte_count = htobe32(wr->sg_list[i].length);
|
|
seg->lkey = htobe32(wr->sg_list[i].lkey);
|
|
seg->addr = htobe64(wr->sg_list[i].addr);
|
|
wqe += sizeof *seg;
|
|
}
|
|
|
|
size += wr->num_sge * (sizeof *seg / 16);
|
|
}
|
|
|
|
qp->wrid[ind + qp->rq.max] = wr->wr_id;
|
|
|
|
if (wr->opcode >= sizeof mthca_opcode / sizeof mthca_opcode[0]) {
|
|
ret = -1;
|
|
*bad_wr = wr;
|
|
goto out;
|
|
}
|
|
|
|
((struct mthca_next_seg *) prev_wqe)->nda_op =
|
|
htobe32(((ind << qp->sq.wqe_shift) +
|
|
qp->send_wqe_offset) |
|
|
mthca_opcode[wr->opcode]);
|
|
udma_ordering_write_barrier();
|
|
((struct mthca_next_seg *) prev_wqe)->ee_nds =
|
|
htobe32(MTHCA_NEXT_DBD | size |
|
|
((wr->send_flags & IBV_SEND_FENCE) ?
|
|
MTHCA_NEXT_FENCE : 0));
|
|
|
|
if (!size0) {
|
|
size0 = size;
|
|
op0 = mthca_opcode[wr->opcode];
|
|
f0 = wr->send_flags & IBV_SEND_FENCE ?
|
|
MTHCA_SEND_DOORBELL_FENCE : 0;
|
|
}
|
|
|
|
++ind;
|
|
if (ind >= qp->sq.max)
|
|
ind -= qp->sq.max;
|
|
}
|
|
|
|
out:
|
|
if (nreq) {
|
|
doorbell[0] =
|
|
(nreq << 24) | ((qp->sq.head & 0xffff) << 8) | f0 | op0;
|
|
doorbell[1] = (ibqp->qp_num << 8) | size0;
|
|
|
|
qp->sq.head += nreq;
|
|
|
|
/*
|
|
* Make sure that descriptors are written before
|
|
* doorbell record.
|
|
*/
|
|
udma_to_device_barrier();
|
|
*qp->sq.db = htobe32(qp->sq.head & 0xffff);
|
|
|
|
/*
|
|
* Make sure doorbell record is written before we
|
|
* write MMIO send doorbell.
|
|
*/
|
|
mmio_ordered_writes_hack();
|
|
mthca_write64(doorbell, to_mctx(ibqp->context)->uar +
|
|
MTHCA_SEND_DOORBELL);
|
|
}
|
|
|
|
pthread_spin_unlock(&qp->sq.lock);
|
|
return ret;
|
|
}
|
|
|
|
int mthca_arbel_post_recv(struct ibv_qp *ibqp, struct ibv_recv_wr *wr,
|
|
struct ibv_recv_wr **bad_wr)
|
|
{
|
|
struct mthca_qp *qp = to_mqp(ibqp);
|
|
int ret = 0;
|
|
int nreq;
|
|
int ind;
|
|
int i;
|
|
void *wqe;
|
|
|
|
pthread_spin_lock(&qp->rq.lock);
|
|
|
|
/* XXX check that state is OK to post receive */
|
|
|
|
ind = qp->rq.head & (qp->rq.max - 1);
|
|
|
|
for (nreq = 0; wr; ++nreq, wr = wr->next) {
|
|
if (wq_overflow(&qp->rq, nreq, to_mcq(qp->ibv_qp.recv_cq))) {
|
|
ret = -1;
|
|
*bad_wr = wr;
|
|
goto out;
|
|
}
|
|
|
|
wqe = get_recv_wqe(qp, ind);
|
|
|
|
((struct mthca_next_seg *) wqe)->flags = 0;
|
|
|
|
wqe += sizeof (struct mthca_next_seg);
|
|
|
|
if (wr->num_sge > qp->rq.max_gs) {
|
|
ret = -1;
|
|
*bad_wr = wr;
|
|
goto out;
|
|
}
|
|
|
|
for (i = 0; i < wr->num_sge; ++i) {
|
|
((struct mthca_data_seg *) wqe)->byte_count =
|
|
htobe32(wr->sg_list[i].length);
|
|
((struct mthca_data_seg *) wqe)->lkey =
|
|
htobe32(wr->sg_list[i].lkey);
|
|
((struct mthca_data_seg *) wqe)->addr =
|
|
htobe64(wr->sg_list[i].addr);
|
|
wqe += sizeof (struct mthca_data_seg);
|
|
}
|
|
|
|
if (i < qp->rq.max_gs) {
|
|
((struct mthca_data_seg *) wqe)->byte_count = 0;
|
|
((struct mthca_data_seg *) wqe)->lkey = htobe32(MTHCA_INVAL_LKEY);
|
|
((struct mthca_data_seg *) wqe)->addr = 0;
|
|
}
|
|
|
|
qp->wrid[ind] = wr->wr_id;
|
|
|
|
++ind;
|
|
if (ind >= qp->rq.max)
|
|
ind -= qp->rq.max;
|
|
}
|
|
out:
|
|
if (nreq) {
|
|
qp->rq.head += nreq;
|
|
|
|
/*
|
|
* Make sure that descriptors are written before
|
|
* doorbell record.
|
|
*/
|
|
udma_to_device_barrier();
|
|
*qp->rq.db = htobe32(qp->rq.head & 0xffff);
|
|
}
|
|
|
|
pthread_spin_unlock(&qp->rq.lock);
|
|
return ret;
|
|
}
|
|
|
|
int mthca_alloc_qp_buf(struct ibv_pd *pd, struct ibv_qp_cap *cap,
|
|
enum ibv_qp_type type, struct mthca_qp *qp)
|
|
{
|
|
int size;
|
|
int max_sq_sge;
|
|
struct mthca_next_seg *next;
|
|
int i;
|
|
|
|
qp->rq.max_gs = cap->max_recv_sge;
|
|
qp->sq.max_gs = cap->max_send_sge;
|
|
max_sq_sge = align(cap->max_inline_data + sizeof (struct mthca_inline_seg),
|
|
sizeof (struct mthca_data_seg)) / sizeof (struct mthca_data_seg);
|
|
if (max_sq_sge < cap->max_send_sge)
|
|
max_sq_sge = cap->max_send_sge;
|
|
|
|
qp->wrid = malloc((qp->rq.max + qp->sq.max) * sizeof (uint64_t));
|
|
if (!qp->wrid)
|
|
return -1;
|
|
|
|
size = sizeof (struct mthca_next_seg) +
|
|
qp->rq.max_gs * sizeof (struct mthca_data_seg);
|
|
|
|
for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
|
|
qp->rq.wqe_shift++)
|
|
; /* nothing */
|
|
|
|
size = max_sq_sge * sizeof (struct mthca_data_seg);
|
|
switch (type) {
|
|
case IBV_QPT_UD:
|
|
size += mthca_is_memfree(pd->context) ?
|
|
sizeof (struct mthca_arbel_ud_seg) :
|
|
sizeof (struct mthca_tavor_ud_seg);
|
|
break;
|
|
|
|
case IBV_QPT_UC:
|
|
size += sizeof (struct mthca_raddr_seg);
|
|
break;
|
|
|
|
case IBV_QPT_RC:
|
|
size += sizeof (struct mthca_raddr_seg);
|
|
/*
|
|
* An atomic op will require an atomic segment, a
|
|
* remote address segment and one scatter entry.
|
|
*/
|
|
if (size < (sizeof (struct mthca_atomic_seg) +
|
|
sizeof (struct mthca_raddr_seg) +
|
|
sizeof (struct mthca_data_seg)))
|
|
size = (sizeof (struct mthca_atomic_seg) +
|
|
sizeof (struct mthca_raddr_seg) +
|
|
sizeof (struct mthca_data_seg));
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Make sure that we have enough space for a bind request */
|
|
if (size < sizeof (struct mthca_bind_seg))
|
|
size = sizeof (struct mthca_bind_seg);
|
|
|
|
size += sizeof (struct mthca_next_seg);
|
|
|
|
for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
|
|
qp->sq.wqe_shift++)
|
|
; /* nothing */
|
|
|
|
qp->send_wqe_offset = align(qp->rq.max << qp->rq.wqe_shift,
|
|
1 << qp->sq.wqe_shift);
|
|
|
|
qp->buf_size = qp->send_wqe_offset + (qp->sq.max << qp->sq.wqe_shift);
|
|
|
|
if (mthca_alloc_buf(&qp->buf,
|
|
align(qp->buf_size, to_mdev(pd->context->device)->page_size),
|
|
to_mdev(pd->context->device)->page_size)) {
|
|
free(qp->wrid);
|
|
return -1;
|
|
}
|
|
|
|
memset(qp->buf.buf, 0, qp->buf_size);
|
|
|
|
if (mthca_is_memfree(pd->context)) {
|
|
struct mthca_data_seg *scatter;
|
|
__be32 sz;
|
|
|
|
sz = htobe32((sizeof (struct mthca_next_seg) +
|
|
qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16);
|
|
|
|
for (i = 0; i < qp->rq.max; ++i) {
|
|
next = get_recv_wqe(qp, i);
|
|
next->nda_op = htobe32(((i + 1) & (qp->rq.max - 1)) <<
|
|
qp->rq.wqe_shift);
|
|
next->ee_nds = sz;
|
|
|
|
for (scatter = (void *) (next + 1);
|
|
(void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
|
|
++scatter)
|
|
scatter->lkey = htobe32(MTHCA_INVAL_LKEY);
|
|
}
|
|
|
|
for (i = 0; i < qp->sq.max; ++i) {
|
|
next = get_send_wqe(qp, i);
|
|
next->nda_op = htobe32((((i + 1) & (qp->sq.max - 1)) <<
|
|
qp->sq.wqe_shift) +
|
|
qp->send_wqe_offset);
|
|
}
|
|
} else {
|
|
for (i = 0; i < qp->rq.max; ++i) {
|
|
next = get_recv_wqe(qp, i);
|
|
next->nda_op = htobe32((((i + 1) % qp->rq.max) <<
|
|
qp->rq.wqe_shift) | 1);
|
|
}
|
|
}
|
|
|
|
qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
|
|
qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct mthca_qp *mthca_find_qp(struct mthca_context *ctx, uint32_t qpn)
|
|
{
|
|
int tind = (qpn & (ctx->num_qps - 1)) >> ctx->qp_table_shift;
|
|
|
|
if (ctx->qp_table[tind].refcnt)
|
|
return ctx->qp_table[tind].table[qpn & ctx->qp_table_mask];
|
|
else
|
|
return NULL;
|
|
}
|
|
|
|
int mthca_store_qp(struct mthca_context *ctx, uint32_t qpn, struct mthca_qp *qp)
|
|
{
|
|
int tind = (qpn & (ctx->num_qps - 1)) >> ctx->qp_table_shift;
|
|
|
|
if (!ctx->qp_table[tind].refcnt) {
|
|
ctx->qp_table[tind].table = calloc(ctx->qp_table_mask + 1,
|
|
sizeof (struct mthca_qp *));
|
|
if (!ctx->qp_table[tind].table)
|
|
return -1;
|
|
}
|
|
|
|
++ctx->qp_table[tind].refcnt;
|
|
ctx->qp_table[tind].table[qpn & ctx->qp_table_mask] = qp;
|
|
return 0;
|
|
}
|
|
|
|
void mthca_clear_qp(struct mthca_context *ctx, uint32_t qpn)
|
|
{
|
|
int tind = (qpn & (ctx->num_qps - 1)) >> ctx->qp_table_shift;
|
|
|
|
if (!--ctx->qp_table[tind].refcnt)
|
|
free(ctx->qp_table[tind].table);
|
|
else
|
|
ctx->qp_table[tind].table[qpn & ctx->qp_table_mask] = NULL;
|
|
}
|
|
|
|
int mthca_free_err_wqe(struct mthca_qp *qp, int is_send,
|
|
int index, int *dbd, __be32 *new_wqe)
|
|
{
|
|
struct mthca_next_seg *next;
|
|
|
|
/*
|
|
* For SRQs, all receive WQEs generate a CQE, so we're always
|
|
* at the end of the doorbell chain.
|
|
*/
|
|
if (qp->ibv_qp.srq && !is_send) {
|
|
*new_wqe = 0;
|
|
return 0;
|
|
}
|
|
|
|
if (is_send)
|
|
next = get_send_wqe(qp, index);
|
|
else
|
|
next = get_recv_wqe(qp, index);
|
|
|
|
*dbd = !!(next->ee_nds & htobe32(MTHCA_NEXT_DBD));
|
|
if (next->ee_nds & htobe32(0x3f))
|
|
*new_wqe = (next->nda_op & htobe32(~0x3f)) |
|
|
(next->ee_nds & htobe32(0x3f));
|
|
else
|
|
*new_wqe = 0;
|
|
|
|
return 0;
|
|
}
|
|
|