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esp32c3

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This commit is contained in:
Andy Green 2021-08-26 13:33:02 +01:00
parent d4dd7cb695
commit 06e881aad6
23 changed files with 3306 additions and 9 deletions
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10
.sai.json
View file

@ -98,6 +98,11 @@
"build": "rm -rf ebuild ; mkdir ebuild; cd ebuild; cp -rp ../minimal-examples/embedded/esp32/${cpack} . ; cd ${cpack} ; . /opt/esp/esp-idf/export.sh ; ln -sf ../.. libwebsockets ; idf.py set-target esp32 && cp libwebsockets/minimal-examples/embedded/esp32/${cpack}/sdkconfig . && cp sdkconfig.h build && idf.py ${cmake} build size size-components size-files && cd build && /usr/local/bin/sai-device ${cpack} ESPPORT=0 ctest --output-on-failure",
"default": false
},
"freertos-espidf/riscv-esp32c3/gcc": {
"build": "rm -rf ebuild ; mkdir ebuild; cd ebuild; cp -rp ../minimal-examples/embedded/esp32/${cpack} . ; cd ${cpack} ; . /opt/esp/esp-idf/export.sh ; ln -sf ../.. libwebsockets ; idf.py set-target esp32c3 && cp libwebsockets/minimal-examples/embedded/esp32/${cpack}/sdkconfig . && cp sdkconfig.h build && idf.py ${cmake} build size size-components size-files && cd build && /usr/local/bin/sai-device ${cpack} ESPPORT=0 ctest --output-on-failure",
"default": false
},
"linux-fedora-32/riscv64-virt/gcc": {
"build": "mkdir build destdir;cd build;export LD_LIBRARY_PATH=../destdir/usr/local/share/libwebsockets-test-server/plugins:../destdir/usr/local/lib;export CCACHE_DISABLE=1;export SAI_CPACK=\"-G RPM\";cmake .. ${cmake} && make -j4 && rm -rf ../destdir && make -j12 DESTDIR=../destdir install && ctest -j3 --output-on-failure ${cpack}",
"default": false
@ -133,6 +138,11 @@
"cmake": "-DLWS_WITH_SYS_FAULT_INJECTION=1 -DLWS_WITH_MINIMAL_EXAMPLES=1 -DLWS_WITH_CBOR=1",
"platforms": "w10/x86_64-amd/msvc"
},
"esp32-c3": {
"cmake": "-DLWS_IPV6=0",
"cpack": "esp-c3dev",
"platforms": "none, freertos-espidf/riscv-esp32c3/gcc"
},
"esp32-heltec": {
"cmake": "-DLWS_IPV6=0",
"cpack": "esp-heltec-wb32",

2
lib/plat/freertos/esp32/drivers/netdev/wifi-esp32.c
View file

@ -309,7 +309,7 @@ _event_handler_wifi(void *arg, esp_event_base_t event_base, int32_t event_id,
lws_smd_msg_printf(ctx, LWSSMDCL_NETWORK,
"{\"type\":\"priv\",\"if\":\"%s\",\"ev\":%d}",
wnd->inst.name, event_id);
wnd->inst.name, (int)event_id);
break;
default:
return;

14
lib/plat/freertos/esp32/drivers/pwm-esp32.c
View file

@ -26,8 +26,10 @@
#include "soc/ledc_reg.h"
#include "driver/ledc.h"
#define _LEDC_HIGH_SPEED_MODE 0
static const ledc_timer_config_t tc = {
.speed_mode = LEDC_HIGH_SPEED_MODE,
.speed_mode = _LEDC_HIGH_SPEED_MODE,
.duty_resolution = LEDC_TIMER_13_BIT,
.timer_num = LEDC_TIMER_0,
.freq_hz = 5000,
@ -40,7 +42,7 @@ lws_pwm_plat_init(const struct lws_pwm_ops *lo)
ledc_channel_config_t lc = {
.duty = 8191,
.intr_type = LEDC_INTR_FADE_END,
.speed_mode = LEDC_HIGH_SPEED_MODE,
.speed_mode = _LEDC_HIGH_SPEED_MODE,
.timer_sel = LEDC_TIMER_0,
};
size_t n;
@ -51,8 +53,8 @@ lws_pwm_plat_init(const struct lws_pwm_ops *lo)
lc.channel = LEDC_CHANNEL_0 + lo->pwm_map[n].index;
lc.gpio_num = lo->pwm_map[n].gpio;
ledc_channel_config(&lc);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, lc.channel, 0);
ledc_update_duty(LEDC_HIGH_SPEED_MODE, lc.channel);
ledc_set_duty(_LEDC_HIGH_SPEED_MODE, lc.channel, 0);
ledc_update_duty(_LEDC_HIGH_SPEED_MODE, lc.channel);
}
return 0;
@ -68,9 +70,9 @@ lws_pwm_plat_intensity(const struct lws_pwm_ops *lo, _lws_plat_gpio_t gpio,
if (lo->pwm_map[n].gpio == gpio) {
if (!lo->pwm_map[n].active_level)
inten = 65535 - inten;
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0 +
ledc_set_duty(_LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0 +
lo->pwm_map[n].index, inten >> 3);
ledc_update_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0 +
ledc_update_duty(_LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0 +
lo->pwm_map[n].index);
return;
}

4
lib/system/smd/smd.c
View file

@ -346,7 +346,7 @@ lws_smd_ss_msg_printf(const char *tag, uint8_t *buf, size_t *len,
*len = LWS_SMD_SS_RX_HEADER_LEN + (unsigned int)n;
lwsl_info("%s: %s send cl 0x%x, len %u\n", __func__, tag, _class,
lwsl_info("%s: %s send cl 0x%x, len %u\n", __func__, tag, (unsigned int)_class,
(unsigned int)n);
return 0;
@ -414,7 +414,7 @@ _lws_smd_ss_rx_forward(struct lws_context *ctx, const char *tag,
}
lwsl_info("%s: %s send cl 0x%x, len %u, ts %llu\n", __func__,
tag, _class, msg->length,
tag, (unsigned int)_class, msg->length,
(unsigned long long)msg->timestamp);
return 0;

36
minimal-examples/embedded/esp32/esp-c3dev/CMakeLists.txt Normal file
View file

@ -0,0 +1,36 @@
cmake_minimum_required(VERSION 3.5)
if (ESP_PLATFORM)
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
project(lws-minimal-esp32)
enable_testing()
target_link_libraries(lws-minimal-esp32.elf websockets)
option(LWS_WITH_DRIVERS "With generic drivers for gpio, i2c, display etc" ON)
set(LWS_WITH_DRIVERS ON)
option(LWS_WITH_SECURE_STREAMS "With secure streams" ON)
set(LWS_WITH_SECURE_STREAMS ON)
option(LWS_WITH_SECURE_STREAMS_STATIC_POLICY_ONLY "static ssp" OFF)
set(LWS_WITH_SECURE_STREAMS_STATIC_POLICY_ONLY OFF)
option(LWS_WITH_LWSAC "With lwsac" ON)
set(LWS_WITH_LWSAC ON)
option(LWS_WITH_STRUCT_JSON "With lws_struct JSON" ON)
set(LWS_WITH_STRUCT_JSON ON)
option(LWS_WITH_SYS_NTPCLIENT "With ntpclient" ON)
set(LWS_WITH_SYS_NTPCLIENT ON)
add_subdirectory(libwebsockets)
add_test(NAME flashing COMMAND idf.py flash)
set_tests_properties(flashing PROPERTIES
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}
TIMEOUT 120)
add_test(NAME boot COMMAND /usr/local/bin/sai-expect)
set_tests_properties(boot PROPERTIES
DEPENDS flashing
TIMEOUT 20)
endif()

497
minimal-examples/embedded/esp32/esp-c3dev/lws-button.c Normal file
View file

@ -0,0 +1,497 @@
/*
* Generic GPIO / irq buttons
*
* Copyright (C) 2019 - 2020 Andy Green <andy@warmcat.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
* deal in the Software without restriction, including without limitation the
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include "private-lib-core.h"
typedef enum lws_button_classify_states {
LBCS_IDLE, /* nothing happening */
LBCS_MIN_DOWN_QUALIFY,
LBCS_ASSESS_DOWN_HOLD,
LBCS_UP_SETTLE1,
LBCS_WAIT_DOUBLECLICK,
LBCS_MIN_DOWN_QUALIFY2,
LBCS_WAIT_UP,
LBCS_UP_SETTLE2,
} lws_button_classify_states_t;
/*
* This is the opaque, allocated, non-const, dynamic footprint of the
* button controller
*/
typedef struct lws_button_state {
#if defined(LWS_PLAT_TIMER_TYPE)
LWS_PLAT_TIMER_TYPE timer; /* bh timer */
LWS_PLAT_TIMER_TYPE timer_mon; /* monitor timer */
#endif
const lws_button_controller_t *controller;
struct lws_context *ctx;
short mon_refcount;
lws_button_idx_t enable_bitmap;
lws_button_idx_t state_bitmap;
uint16_t mon_timer_count;
/* incremented each time the mon timer cb happens */
/* lws_button_each_t per button overallocated after this */
} lws_button_state_t;
typedef struct lws_button_each {
lws_button_state_t *bcs;
uint16_t mon_timer_comp;
uint8_t state;
/**^ lws_button_classify_states_t */
uint8_t isr_pending;
} lws_button_each_t;
#if defined(LWS_PLAT_TIMER_START)
static const lws_button_regime_t default_regime = {
.ms_min_down = 20,
.ms_min_down_longpress = 300,
.ms_up_settle = 20,
.ms_doubleclick_grace = 120,
.flags = LWSBTNRGMFLAG_CLASSIFY_DOUBLECLICK
};
#endif
/*
* This is happening in interrupt context, we have to schedule a bottom half to
* do the foreground lws_smd queueing, using, eg, a platform timer.
*
* All the buttons point here and use one timer per button controller. An
* interrupt here means, "something happened to one or more buttons"
*/
#if defined(LWS_PLAT_TIMER_START)
void
lws_button_irq_cb_t(void *arg)
{
lws_button_each_t *each = (lws_button_each_t *)arg;
each->isr_pending = 1;
LWS_PLAT_TIMER_START(each->bcs->timer);
}
#endif
/*
* This is the bottom-half scheduled via a timer set in the ISR. From here
* we are allowed to hold mutexes etc. We are coming here because any button
* interrupt arrived, we have to try to figure out which events have happened.
*/
#if defined(LWS_PLAT_TIMER_CB)
static LWS_PLAT_TIMER_CB(lws_button_bh, th)
{
lws_button_state_t *bcs = LWS_PLAT_TIMER_CB_GET_OPAQUE(th);
const lws_button_controller_t *bc = bcs->controller;
lws_button_each_t *each = (lws_button_each_t *)&bcs[1];
size_t n;
/*
* The ISR and bottom-half is shared by all the buttons. Each gpio
* IRQ has an individual opaque ptr pointing to the corresponding
* button's dynamic lws_button_each_t, the ISR marks the button's
* each->isr_pending and schedules this bottom half.
*
* So now the bh timer has fired and something to do, we need to go
* through all the buttons that have isr_pending set and service their
* state. Intermediate states should start / bump the refcount on the
* mon timer. That's refcounted so it only runs when a button down.
*/
for (n = 0; n < bc->count_buttons; n++) {
if (!each[n].isr_pending)
continue;
/*
* Hide what we're about to do from the delicate eyes of the
* IRQ controller...
*/
bc->gpio_ops->irq_mode(bc->button_map[n].gpio,
LWSGGPIO_IRQ_NONE, NULL, NULL);
each[n].isr_pending = 0;
/*
* Force the network around the switch to the
* active level briefly
*/
bc->gpio_ops->set(bc->button_map[n].gpio,
!!(bc->active_state_bitmap & (1 << n)));
bc->gpio_ops->mode(bc->button_map[n].gpio, LWSGGPIO_FL_WRITE);
if (each[n].state == LBCS_IDLE) {
/*
* If this is the first sign something happening on this
* button, make sure the monitor timer is running to
* classify it over time
*/
each[n].state = LBCS_MIN_DOWN_QUALIFY;
each[n].mon_timer_comp = bcs->mon_timer_count;
if (!bcs->mon_refcount++) {
#if defined(LWS_PLAT_TIMER_START)
// lwsl_notice("%s: starting mon timer\n", __func__);
LWS_PLAT_TIMER_START(bcs->timer_mon);
#endif
}
}
/*
* Just for a us or two inbetween here, we're driving it to the
* level we were informed by the interrupt it had enetered, to
* force to charge on the actual and parasitic network around
* the switch to a deterministic-ish state.
*
* If the switch remains in that state, well, it makes no
* difference; if it was a pre-contact and the charge on the
* network was left indeterminate, this will dispose it to act
* consistently in the short term until the pullup / pulldown
* has time to act on it or the switch comes and forces the
* network charge state itself.
*/
bc->gpio_ops->mode(bc->button_map[n].gpio, LWSGGPIO_FL_READ);
/*
* We could do a better job manipulating the irq mode according
* to the switch state. But if an interrupt comes and we have
* done that, we can't tell if it's from before or after the
* mode change... ie, we don't know what the interrupt was
* telling us. We can't trust the gpio state if we read it now
* to be related to what the irq from some time before was
* trying to tell us. So always set it back to the same mode
* and accept the limitation.
*/
bc->gpio_ops->irq_mode(bc->button_map[n].gpio,
bc->active_state_bitmap & (1 << n) ?
LWSGGPIO_IRQ_RISING :
LWSGGPIO_IRQ_FALLING,
lws_button_irq_cb_t, &each[n]);
}
}
#endif
#if defined(LWS_PLAT_TIMER_CB)
static LWS_PLAT_TIMER_CB(lws_button_mon, th)
{
lws_button_state_t *bcs = LWS_PLAT_TIMER_CB_GET_OPAQUE(th);
lws_button_each_t *each = (lws_button_each_t *)&bcs[1];
const lws_button_controller_t *bc = bcs->controller;
const lws_button_regime_t *regime;
const char *event_name;
int comp_age_ms;
char active;
size_t n;
bcs->mon_timer_count++;
for (n = 0; n < bc->count_buttons; n++) {
if (each[n].state == LBCS_IDLE)
continue;
if (bc->button_map[n].regime)
regime = bc->button_map[n].regime;
else
regime = &default_regime;
comp_age_ms = (bcs->mon_timer_count - each[n].mon_timer_comp) *
LWS_BUTTON_MON_TIMER_MS;
active = bc->gpio_ops->read(bc->button_map[n].gpio) ^
(!(bc->active_state_bitmap & (1 << n)));
// lwsl_notice("%d\n", each[n].state);
switch (each[n].state) {
case LBCS_MIN_DOWN_QUALIFY:
/*
* We're trying to figure out if the initial down event
* is a glitch, or if it meets the criteria for being
* treated as the definitive start of some kind of click
* action. To get past this, he has to be solidly down
* for the time mentioned in the applied regime (at
* least when we sample it).
*
* Significant bounce at the start will abort this try,
* but if it's really down there will be a subsequent
* solid down period... it will simply restart this flow
* from a new interrupt and pass the filter then.
*
* The "brief drive on edge" strategy considerably
* reduces inconsistencies here. But physical bounce
* will continue to be observed.
*/
if (!active) {
/* We ignore stuff for a bit after discard */
each[n].mon_timer_comp = bcs->mon_timer_count;
each[n].state = LBCS_UP_SETTLE2;
continue;
}
if (comp_age_ms >= regime->ms_min_down) {
/* We made it through the initial regime filter,
* the next step is wait and see if this down
* event evolves into a single/double click or
* we can call it as a long-click
*/
each[n].state = LBCS_ASSESS_DOWN_HOLD;
break;
}
break;
case LBCS_ASSESS_DOWN_HOLD:
/*
* How long is he going to hold it? If he holds it
* past the long-click threshold, we can call it as a
* long-click and do the up processing afterwards.
*/
if (comp_age_ms >= regime->ms_min_down_longpress) {
/* call it as a longclick */
event_name = "longclick";
each[n].state = LBCS_WAIT_UP;
goto classify;
}
if (!active) {
/*
* He didn't hold it past the long-click
* threshold... we could end up classifying it
* as either a click or a double-click then.
*
* If double-clicks are not allowed to be
* classified, then we can already classify it
* as a single-click.
*/
if (!(regime->flags & LWSBTNRGMFLAG_CLASSIFY_DOUBLECLICK))
goto classify_single;
/*
* Just wait for the up settle time then start
* looking for a second down.
*/
each[n].mon_timer_comp = bcs->mon_timer_count;
each[n].state = LBCS_UP_SETTLE1;
}
break;
case LBCS_UP_SETTLE1:
if (comp_age_ms > regime->ms_up_settle)
/*
* Just block anything for the up settle time
*/
each[n].state = LBCS_WAIT_DOUBLECLICK;
break;
case LBCS_WAIT_DOUBLECLICK:
if (active) {
/*
* He has gone down again inside the regime's
* doubleclick grace period... he's going down
* the double-click path
*/
each[n].mon_timer_comp = bcs->mon_timer_count;
each[n].state = LBCS_MIN_DOWN_QUALIFY2;
break;
}
if (comp_age_ms >= regime->ms_doubleclick_grace) {
/*
* The grace period expired, the second click
* was either not forthcoming at all, or coming
* quick enough to count: we classify it as a
* single-click
*/
goto classify_single;
}
break;
case LBCS_MIN_DOWN_QUALIFY2:
if (!active) {
classify_single:
/*
* He went up again too quickly, classify it
* as a single-click. It could be bounce in
* which case you might want to increase
* the ms_up_settle in the regime
*/
event_name = "click";
each[n].mon_timer_comp = bcs->mon_timer_count;
each[n].state = LBCS_UP_SETTLE2;
goto classify;
}
if (comp_age_ms >= regime->ms_min_down) {
/*
* It's a double-click
*/
event_name = "doubleclick";
each[n].state = LBCS_WAIT_UP;
goto classify;
}
break;
case LBCS_WAIT_UP:
if (!active) {
each[n].mon_timer_comp = bcs->mon_timer_count;
each[n].state = LBCS_UP_SETTLE2;
}
break;
case LBCS_UP_SETTLE2:
if (comp_age_ms < regime->ms_up_settle)
break;
each[n].state = LBCS_IDLE;
if (!(--bcs->mon_refcount)) {
#if defined(LWS_PLAT_TIMER_STOP)
LWS_PLAT_TIMER_STOP(bcs->timer_mon);
#endif
}
break;
}
continue;
classify:
lws_smd_msg_printf(bcs->ctx, LWSSMDCL_INTERACTION,
"{\"btn\":\"%s/%s\", \"s\":\"%s\"}",
bc->smd_bc_name,
bc->button_map[n].smd_interaction_name,
event_name);
}
}
#endif
struct lws_button_state *
lws_button_controller_create(struct lws_context *ctx,
const lws_button_controller_t *controller)
{
lws_button_state_t *bcs = lws_zalloc(sizeof(lws_button_state_t) +
(controller->count_buttons * sizeof(lws_button_each_t)),
__func__);
lws_button_each_t *each = (lws_button_each_t *)&bcs[1];
size_t n;
if (!bcs)
return NULL;
bcs->controller = controller;
bcs->ctx = ctx;
for (n = 0; n < controller->count_buttons; n++)
each[n].bcs = bcs;
#if defined(LWS_PLAT_TIMER_CREATE)
/* this only runs inbetween a gpio ISR and the bottom half */
bcs->timer = LWS_PLAT_TIMER_CREATE("bcst",
1, 0, bcs, (TimerCallbackFunction_t)lws_button_bh);
if (!bcs->timer)
return NULL;
/* this only runs when a button activity is being classified */
bcs->timer_mon = LWS_PLAT_TIMER_CREATE("bcmon", LWS_BUTTON_MON_TIMER_MS, 1, bcs,
(TimerCallbackFunction_t)lws_button_mon);
if (!bcs->timer_mon)
return NULL;
#endif
return bcs;
}
void
lws_button_controller_destroy(struct lws_button_state *bcs)
{
/* disable them all */
lws_button_enable(bcs, 0, 0);
#if defined(LWS_PLAT_TIMER_DELETE)
LWS_PLAT_TIMER_DELETE(&bcs->timer);
LWS_PLAT_TIMER_DELETE(&bcs->timer_mon);
#endif
lws_free(bcs);
}
lws_button_idx_t
lws_button_get_bit(struct lws_button_state *bcs, const char *name)
{
const lws_button_controller_t *bc = bcs->controller;
int n;
for (n = 0; n < bc->count_buttons; n++)
if (!strcmp(name, bc->button_map[n].smd_interaction_name))
return 1 << n;
return 0; /* not found */
}
void
lws_button_enable(lws_button_state_t *bcs,
lws_button_idx_t _reset, lws_button_idx_t _set)
{
lws_button_idx_t u = (bcs->enable_bitmap & (~_reset)) | _set;
const lws_button_controller_t *bc = bcs->controller;
#if defined(LWS_PLAT_TIMER_START)
lws_button_each_t *each = (lws_button_each_t *)&bcs[1];
#endif
int n;
for (n = 0; n < bcs->controller->count_buttons; n++) {
if (!(bcs->enable_bitmap & (1 << n)) && (u & (1 << n))) {
/* set as input with pullup or pulldown appropriately */
bc->gpio_ops->mode(bc->button_map[n].gpio,
LWSGGPIO_FL_READ |
((bc->active_state_bitmap & (1 << n)) ?
LWSGGPIO_FL_PULLDOWN : LWSGGPIO_FL_PULLUP));
#if defined(LWS_PLAT_TIMER_START)
/*
* This one is becoming enabled... the opaque for the
* ISR is the indvidual lws_button_each_t, they all
* point to the same ISR
*/
bc->gpio_ops->irq_mode(bc->button_map[n].gpio,
bc->active_state_bitmap & (1 << n) ?
LWSGGPIO_IRQ_RISING :
LWSGGPIO_IRQ_FALLING,
lws_button_irq_cb_t, &each[n]);
#endif
}
if ((bcs->enable_bitmap & (1 << n)) && !(u & (1 << n)))
/* this one is becoming disabled */
bc->gpio_ops->irq_mode(bc->button_map[n].gpio,
LWSGGPIO_IRQ_NONE, NULL, NULL);
}
bcs->enable_bitmap = u;
}

6
minimal-examples/embedded/esp32/esp-c3dev/main/CMakeLists.txt Normal file
View file

@ -0,0 +1,6 @@
idf_component_register(SRCS
lws-minimal-esp32.c devices.c
INCLUDE_DIRS "../libwebsockets/include;${IDF_PATH}/components/spi_flash/include;${IDF_PATH}/components/nvs_flash/include;${IDF_PATH}/components/mdns/include")
target_link_libraries(${COMPONENT_LIB} websockets)
include_directories(../build/libwebsockets)

107
minimal-examples/embedded/esp32/esp-c3dev/main/bb-i2c.c Normal file
View file

@ -0,0 +1,107 @@
/*
* lws generic bitbang i2c
*
* Written in 2010-2020 by Andy Green <andy@warmcat.com>
*
* This file is made available under the Creative Commons CC0 1.0
* Universal Public Domain Dedication.
*/
#include "bb-i2c.h"
int
lws_bb_i2c_start(lws_i2c_ops_t *octx)
{
lws_bb_i2c_t *ctx = (lws_bb_i2c_t *)octx;
ctx->gpio->set(ctx->sda, 1);
ctx->gpio->set(ctx->scl, 1);
ctx->delay();
if (!ctx->gpio->read(ctx->sda))
return 1;
ctx->gpio->set(ctx->sda, 0);
ctx->delay();
ctx->gpio->set(ctx->scl, 0);
return 0;
}
void
lws_bb_i2c_stop(lws_i2c_ops_t *octx)
{
lws_bb_i2c_t *ctx = (lws_bb_i2c_t *)octx;
ctx->gpio->set(ctx->sda, 0);
ctx->gpio->set(ctx->scl, 1);
ctx->delay();
while (!ctx->gpio->read(ctx->scl))
;
ctx->gpio->set(ctx->sda, 1);
ctx->delay();
}
int
lws_bb_i2c_write(lws_i2c_ops_t *octx, uint8_t data)
{
lws_bb_i2c_t *ctx = (lws_bb_i2c_t *)octx;
int n;
for (n = 0; n < 8; n++) {
ctx->gpio->set(ctx->sda, !!(data & (1 << 7)));
ctx->delay();
ctx->gpio->set(ctx->scl, 1);
ctx->delay();
data <<= 1;
ctx->gpio->set(ctx->scl, 0);
}
ctx->gpio->set(ctx->sda, 1);
ctx->delay();
ctx->gpio->set(ctx->scl, 1);
ctx->delay();
n = ctx->gpio->read(ctx->sda);
ctx->gpio->set(ctx->scl, 0);
ctx->delay();
return !!n; /* 0 = ACKED = OK */
}
int
lws_bb_i2c_read(lws_i2c_ops_t *octx)
{
lws_bb_i2c_t *ctx = (lws_bb_i2c_t *)octx;
int n, r = 0;
ctx->gpio->set(ctx->sda, 1);
for (n = 7; n <= 0; n--) {
ctx->gpio->set(ctx->scl, 0);
ctx->delay();
ctx->gpio->set(ctx->scl, 1);
ctx->delay();
if (ctx->gpio->read(ctx->sda))
r |= 1 << n;
}
ctx->gpio->set(ctx->scl, 0);
return r;
}
void
lws_bb_i2c_set_ack(lws_i2c_ops_t *octx, int ack)
{
lws_bb_i2c_t *ctx = (lws_bb_i2c_t *)octx;
ctx->gpio->set(ctx->scl, 0);
ctx->gpio->set(ctx->sda, !!ack);
ctx->delay();
ctx->gpio->set(ctx->scl, 1);
ctx->delay();
ctx->gpio->set(ctx->scl, 0);
ctx->delay();
ctx->gpio->set(ctx->sda, 1);
}

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minimal-examples/embedded/esp32/esp-c3dev/main/bb-i2c.h Normal file
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/*
* lws-minimal-esp32
*
* Written in 2010-2020 by Andy Green <andy@warmcat.com>
*
* This file is made available under the Creative Commons CC0 1.0
* Universal Public Domain Dedication.
*/
#include <stdint.h>
#include <stddef.h>
#include "i2c.h"
#include "gpio-esp32.h"
typedef struct lws_bb_i2c {
lws_i2c_ops_t bb_ops; /* init to lws_bb_i2c_ops */
/* implementation-specific members */
_lws_plat_gpio_t scl;
_lws_plat_gpio_t sda;
const lws_gpio_ops_t *gpio;
void (*delay)(void);
} lws_bb_i2c_t;
#define lws_bb_i2c_ops \
{ \
.start = lws_bb_i2c_start, \
.stop = lws_bb_i2c_stop, \
.write = lws_bb_i2c_write, \
.read = lws_bb_i2c_read, \
.set_ack = lws_bb_i2c_set_ack, \
}
int
lws_bb_i2c_start(lws_i2c_ops_t *octx);
void
lws_bb_i2c_stop(lws_i2c_ops_t *octx);
int
lws_bb_i2c_write(lws_i2c_ops_t *octx, uint8_t data);
int
lws_bb_i2c_read(lws_i2c_ops_t *octx);
void
lws_bb_i2c_set_ack(lws_i2c_ops_t *octx, int ack);

5
minimal-examples/embedded/esp32/esp-c3dev/main/component.mk Normal file
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#
# "main" pseudo-component makefile.
#
# (Uses default behaviour of compiling all source files in directory, adding 'include' to include path.)

187
minimal-examples/embedded/esp32/esp-c3dev/main/devices.c Normal file
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/*
* devices for ESP32 C3 dev board
*
* Written in 2010-2021 by Andy Green <andy@warmcat.com>
*
* This file is made available under the Creative Commons CC0 1.0
* Universal Public Domain Dedication.
*/
#define LWIP_PROVIDE_ERRNO 1
#define _ESP_PLATFORM_ERRNO_H_
#include <stdio.h>
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include <driver/gpio.h>
#include <libwebsockets.h>
struct lws_led_state *lls;
lws_display_state_t lds;
struct lws_button_state *bcs;
lws_netdev_instance_wifi_t *wnd;
/*
* Button controller
*/
static const lws_button_map_t bcm[] = {
{
.gpio = GPIO_NUM_0,
.smd_interaction_name = "user"
},
};
static const lws_button_controller_t bc = {
.smd_bc_name = "bc",
.gpio_ops = &lws_gpio_plat,
.button_map = &bcm[0],
.active_state_bitmap = 0,
.count_buttons = LWS_ARRAY_SIZE(bcm),
};
/*
* pwm controller
*/
static const lws_pwm_map_t pwm_map[] = {
{ .gpio = GPIO_NUM_8, .index = 0, .active_level = 1 }
};
static const lws_pwm_ops_t pwm_ops = {
lws_pwm_plat_ops,
.pwm_map = &pwm_map[0],
.count_pwm_map = LWS_ARRAY_SIZE(pwm_map)
};
#if 0
static const lws_display_ssd1306_t disp = {
.disp = {
lws_display_ssd1306_ops,
.w = 128,
.h = 64
},
.i2c = (lws_i2c_ops_t *)&li2c,
.gpio = &lws_gpio_plat,
.reset_gpio = GPIO_NUM_16,
.i2c7_address = SSD1306_I2C7_ADS1
};
#endif
/*
* led controller
*/
static const lws_led_gpio_map_t lgm[] = {
{
.name = "alert",
.gpio = GPIO_NUM_8,
.pwm_ops = &pwm_ops, /* managed by pwm */
.active_level = 1,
},
};
static const lws_led_gpio_controller_t lgc = {
.led_ops = lws_led_gpio_ops,
.gpio_ops = &lws_gpio_plat,
.led_map = &lgm[0],
.count_leds = LWS_ARRAY_SIZE(lgm)
};
/*
* Settings stored in platform nv
*/
static const lws_settings_ops_t sett = {
lws_settings_ops_plat
};
/*
* Wifi
*/
static const lws_netdev_ops_t wifi_ops = {
lws_netdev_wifi_plat_ops
};
int
init_plat_devices(struct lws_context *ctx)
{
lws_settings_instance_t *si;
lws_netdevs_t *netdevs = lws_netdevs_from_ctx(ctx);
si = lws_settings_init(&sett, (void *)"nvs");
if (!si) {
lwsl_err("%s: failed to create settings instance\n", __func__);
return 1;
}
netdevs->si = si;
#if 0
/*
* This is a temp hack to bootstrap the settings to contain the test
* AP ssid and passphrase for one time, so the settings can be stored
* while there's no UI atm
*/
{
lws_wifi_creds_t creds;
memset(&creds, 0, sizeof(creds));
lws_strncpy(creds.ssid, "xxx", sizeof(creds.ssid));
lws_strncpy(creds.passphrase, "xxx", sizeof(creds.passphrase));
lws_dll2_add_tail(&creds.list, &netdevs->owner_creds);
if (lws_netdev_credentials_settings_set(netdevs)) {
lwsl_err("%s: failed to write bootstrap creds\n",
__func__);
return 1;
}
}
#endif
/* create the wifi network device and configure it */
wnd = (lws_netdev_instance_wifi_t *)
wifi_ops.create(ctx, &wifi_ops, "wl0", NULL);
if (!wnd) {
lwsl_err("%s: failed to create wifi object\n", __func__);
return 1;
}
wnd->flags |= LNDIW_MODE_STA;
if (wifi_ops.configure(&wnd->inst, NULL)) {
lwsl_err("%s: failed to configure wifi object\n", __func__);
return 1;
}
wifi_ops.up(&wnd->inst);
esp_wifi_set_mode(WIFI_MODE_STA);
lws_netdev_wifi_scan_plat(&wnd->inst);
lls = lgc.led_ops.create(&lgc.led_ops);
if (!lls) {
lwsl_err("%s: could not create led\n", __func__);
return 1;
}
/* pwm init must go after the led controller init */
// pwm_ops.init(&pwm_ops);
bcs = lws_button_controller_create(ctx, &bc);
if (!bcs) {
lwsl_err("%s: could not create buttons\n", __func__);
return 1;
}
lws_button_enable(bcs, 0, lws_button_get_bit(bcs, "user"));
// lws_led_transition(lls, "alert", &lws_pwmseq_static_off,
// &lws_pwmseq_static_on);
lwsl_notice("%s: exiting device init\n", __func__);
return 0;
}

36
minimal-examples/embedded/esp32/esp-c3dev/main/gpio-esp32.c Normal file
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#include <driver/gpio.h>
#include "gpio-esp32.h"
static void
lws_gpio_esp32_mode_write(_lws_plat_gpio_t gpio)
{
gpio_reset_pin(gpio);
gpio_set_pull_mode(gpio, GPIO_PULLUP_ONLY);
gpio_set_direction(gpio, GPIO_MODE_INPUT_OUTPUT);
gpio_set_level(gpio, 1);
}
static void
lws_gpio_esp32_mode_read(_lws_plat_gpio_t gpio)
{
gpio_set_pull_mode(gpio, GPIO_PULLUP_ONLY);
gpio_set_direction(gpio, GPIO_MODE_INPUT);
gpio_set_level(gpio, 1);
}
static int
lws_gpio_esp32_read(_lws_plat_gpio_t gpio)
{
return gpio_get_level(gpio);
}
static void
lws_gpio_esp32_set(_lws_plat_gpio_t gpio, int val)
{
gpio_set_level(gpio, val);
}
const lws_gpio_ops_t lws_gpio_esp32 = {
.mode_write = lws_gpio_esp32_mode_write,
.mode_read = lws_gpio_esp32_mode_read,
.read = lws_gpio_esp32_read,
.set = lws_gpio_esp32_set,
};

13
minimal-examples/embedded/esp32/esp-c3dev/main/gpio-esp32.h Normal file
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/*
* lws generic gpio - esp32 platform wrapper
*
* Written in 2010-2020 by Andy Green <andy@warmcat.com>
*
* This file is made available under the Creative Commons CC0 1.0
* Universal Public Domain Dedication.
*/
typedef int _lws_plat_gpio_t;
#include "gpio.h"
extern const lws_gpio_ops_t lws_gpio_esp32;

25
minimal-examples/embedded/esp32/esp-c3dev/main/gpio.h Normal file
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/*
* lws genric gpio
*
* Written in 2010-2020 by Andy Green <andy@warmcat.com>
*
* This file is made available under the Creative Commons CC0 1.0
* Universal Public Domain Dedication.
*
* You should typedef _lws_plat_gpio_t to int or whatever before
* including this. It's better to wrap this in a platform-specific
* include that does that and then include the platform-specific
* include in your code.
*/
#if !defined(__LWS_GPIO_H__)
#define __LWS_GPIO_H__
typedef struct lws_gpio_ops {
void (*mode_write)(_lws_plat_gpio_t gpio);
void (*mode_read)(_lws_plat_gpio_t gpio);
int (*read)(_lws_plat_gpio_t gpio);
void (*set)(_lws_plat_gpio_t gpio, int val);
} lws_gpio_ops_t;
#endif

32
minimal-examples/embedded/esp32/esp-c3dev/main/i2c.c Normal file
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#include "i2c.h"
int
lws_i2c_command(lws_i2c_ops_t *ctx, uint8_t ads, uint8_t c)
{
if (ctx->start(ctx))
return 1;
if (ctx->write(ctx, ads << 1)) {
ctx->stop(ctx);
return 1;
}
ctx->write(ctx, 0);
ctx->write(ctx, c);
ctx->stop(ctx);
return 0;
}
int
lws_i2c_command_list(lws_i2c_ops_t *ctx, uint8_t ads, const uint8_t *buf, size_t len)
{
while (len--)
if (lws_i2c_command(ctx, ads, *buf++))
return 1;
return 0;
}

35
minimal-examples/embedded/esp32/esp-c3dev/main/i2c.h Normal file
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/*
* Generic i2c ops
*
* These ops always appear first in an implementation-specific
* object, so the generic ops can be cast to the implementation-
* specific object in the handlers.
*
* Written in 2010-2020 by Andy Green <andy@warmcat.com>
*
* This file is made available under the Creative Commons CC0 1.0
* Universal Public Domain Dedication.
*/
#if !defined(__LWS_I2C_H__)
#define __LWS_I2C_H__
#include <stdint.h>
#include <stddef.h>
typedef struct lws_i2c_ops {
int (*start)(struct lws_i2c_ops *ctx);
void (*stop)(struct lws_i2c_ops *ctx);
int (*write)(struct lws_i2c_ops *ctx, uint8_t data);
int (*read)(struct lws_i2c_ops *ctx);
void (*set_ack)(struct lws_i2c_ops *octx, int ack);
} lws_i2c_ops_t;
int
lws_i2c_command(lws_i2c_ops_t *ctx, uint8_t ads, uint8_t c);
int
lws_i2c_command_list(lws_i2c_ops_t *ctx, uint8_t ads, const uint8_t *buf, size_t len);
#endif

206
minimal-examples/embedded/esp32/esp-c3dev/main/lws-minimal-esp32.c Normal file
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/*
* lws-minimal-esp32
*
* Written in 2010-2020 by Andy Green <andy@warmcat.com>
*
* This file is made available under the Creative Commons CC0 1.0
* Universal Public Domain Dedication.
*
* Based on espressif Public Domain sample
*/
#define LWIP_PROVIDE_ERRNO 1
#define _ESP_PLATFORM_ERRNO_H_
#include <stdio.h>
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include <driver/gpio.h>
#include <libwebsockets.h>
struct lws_context *context;
extern struct lws_led_state *lls;
extern lws_display_state_t lds;
extern lws_netdev_instance_wifi_t *wnd;
extern int init_plat_devices(struct lws_context *);
#include "policy.h"
static uint8_t flip;
typedef struct myss {
struct lws_ss_handle *ss;
void *opaque_data;
/* ... application specific state ... */
size_t amount;
} myss_t;
static int
myss_rx(void *userobj, const uint8_t *buf, size_t len, int flags)
{
myss_t *m = (myss_t *)userobj;
lwsl_user("%s: len %d, flags: %d\n", __func__, (int)len, flags);
// lwsl_hexdump_info(buf, len);
m->amount += len;
if (flags & LWSSS_FLAG_EOM) {
/*
* If we received the whole message, for our example it means
* we are done.
*/
lwsl_notice("%s: received %u bytes\n", __func__,
(unsigned int)m->amount);
/*
* In CI, we use sai-expect to look for this
* string for success
*/
lwsl_notice("Completed: PASS\n");
}
return 0;
}
static int
myss_state(void *userobj, void *sh, lws_ss_constate_t state,
lws_ss_tx_ordinal_t ack)
{
myss_t *m = (myss_t *)userobj;
lwsl_user("%s: %s, ord 0x%x\n", __func__, lws_ss_state_name(state),
(unsigned int)ack);
switch (state) {
case LWSSSCS_CREATING:
if (lws_ss_client_connect(m->ss))
lwsl_err("%s: connection failed\n", __func__);
break;
default:
break;
}
return 0;
}
static const lws_ss_info_t ssi = {
.handle_offset = offsetof(myss_t, ss),
.opaque_user_data_offset = offsetof(myss_t, opaque_data),
.rx = myss_rx,
.state = myss_state,
.user_alloc = sizeof(myss_t),
.streamtype = "test_stream",
};
static const lws_led_sequence_def_t *seqs[] = {
&lws_pwmseq_static_on,
&lws_pwmseq_static_off,
&lws_pwmseq_sine_endless_slow,
&lws_pwmseq_sine_endless_fast,
};
static int
smd_cb(void *opaque, lws_smd_class_t _class, lws_usec_t timestamp, void *buf,
size_t len)
{
if (!lws_json_simple_strcmp(buf, len, "\"src\":", "bc/user") &&
!lws_json_simple_strcmp(buf, len, "\"event\":", "click")) {
lws_led_transition(lls, "alert", seqs[flip & 3],
&lws_pwmseq_linear_wipe);
flip++;
}
lwsl_hexdump_notice(buf, len);
if ((_class & LWSSMDCL_SYSTEM_STATE) &&
!lws_json_simple_strcmp(buf, len, "\"state\":", "OPERATIONAL")) {
/* create the secure stream */
lwsl_notice("%s: creating test secure stream\n", __func__);
if (lws_ss_create(context, 0, &ssi, NULL, NULL, NULL, NULL)) {
lwsl_err("%s: failed to create secure stream\n",
__func__);
return -1;
}
}
if (_class & LWSSMDCL_INTERACTION)
/*
* Any kind of user interaction brings the display back up and
* resets the dimming / blanking timers
*/
lws_display_state_active(&lds);
return 0;
}
void
app_main(void)
{
struct lws_context_creation_info *info;
lws_set_log_level(1024 | 7, NULL);
lws_netdev_plat_init();
lws_netdev_plat_wifi_init();
info = malloc(sizeof(*info));
if (!info)
goto spin;
memset(info, 0, sizeof(*info));
lwsl_notice("LWS test for ESP32-C3 Dev Board\n");
info->pss_policies_json = ss_policy;
info->options = LWS_SERVER_OPTION_EXPLICIT_VHOSTS |
LWS_SERVER_OPTION_DO_SSL_GLOBAL_INIT;
info->port = CONTEXT_PORT_NO_LISTEN;
info->early_smd_cb = smd_cb;
info->early_smd_class_filter = LWSSMDCL_INTERACTION |
LWSSMDCL_SYSTEM_STATE |
LWSSMDCL_NETWORK;
context = lws_create_context(info);
if (!context) {
lwsl_err("lws init failed\n");
return;
}
/*
* We don't need this after context creation... things it pointed to
* still need to exist though since the context copied the pointers.
*/
free(info);
/* devices and init are in devices.c */
if (init_plat_devices(context))
goto spin;
/* the lws event loop */
do {
taskYIELD();
} while (lws_service(context, 0) >= 0);
spin:
vTaskDelay(10);
taskYIELD();
goto spin;
}

134
minimal-examples/embedded/esp32/esp-c3dev/main/policy.h Normal file
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@ -0,0 +1,134 @@
static const char * const ss_policy =
"{"
"\"release\":" "\"01234567\","
"\"product\":" "\"myproduct\","
"\"schema-version\":" "1,"
"\"retry\": [" /* named backoff / retry strategies */
"{\"default\": {"
"\"backoff\": [" "1000,"
"2000,"
"3000,"
"5000,"
"10000"
"],"
"\"conceal\":" "25,"
"\"jitterpc\":" "20,"
"\"svalidping\":" "30,"
"\"svalidhup\":" "35"
"}}"
"],"
"\"certs\": [" /* named individual certificates in BASE64 DER */
/*
* Let's Encrypt certs for warmcat.com / libwebsockets.org
*
* We fetch the real policy from there using SS and switch to
* using that.
*/
"{\"isrg_root_x1\": \"" /* ISRG ROOT X1 */
"MIIFazCCA1OgAwIBAgIRAIIQz7DSQONZRGPgu2OCiwAwDQYJKoZIhvcNAQELBQAw"
"TzELMAkGA1UEBhMCVVMxKTAnBgNVBAoTIEludGVybmV0IFNlY3VyaXR5IFJlc2Vh"
"cmNoIEdyb3VwMRUwEwYDVQQDEwxJU1JHIFJvb3QgWDEwHhcNMTUwNjA0MTEwNDM4"
"WhcNMzUwNjA0MTEwNDM4WjBPMQswCQYDVQQGEwJVUzEpMCcGA1UEChMgSW50ZXJu"
"ZXQgU2VjdXJpdHkgUmVzZWFyY2ggR3JvdXAxFTATBgNVBAMTDElTUkcgUm9vdCBY"
"MTCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBAK3oJHP0FDfzm54rVygc"
"h77ct984kIxuPOZXoHj3dcKi/vVqbvYATyjb3miGbESTtrFj/RQSa78f0uoxmyF+"
"0TM8ukj13Xnfs7j/EvEhmkvBioZxaUpmZmyPfjxwv60pIgbz5MDmgK7iS4+3mX6U"
"A5/TR5d8mUgjU+g4rk8Kb4Mu0UlXjIB0ttov0DiNewNwIRt18jA8+o+u3dpjq+sW"
"T8KOEUt+zwvo/7V3LvSye0rgTBIlDHCNAymg4VMk7BPZ7hm/ELNKjD+Jo2FR3qyH"
"B5T0Y3HsLuJvW5iB4YlcNHlsdu87kGJ55tukmi8mxdAQ4Q7e2RCOFvu396j3x+UC"
"B5iPNgiV5+I3lg02dZ77DnKxHZu8A/lJBdiB3QW0KtZB6awBdpUKD9jf1b0SHzUv"
"KBds0pjBqAlkd25HN7rOrFleaJ1/ctaJxQZBKT5ZPt0m9STJEadao0xAH0ahmbWn"
"OlFuhjuefXKnEgV4We0+UXgVCwOPjdAvBbI+e0ocS3MFEvzG6uBQE3xDk3SzynTn"
"jh8BCNAw1FtxNrQHusEwMFxIt4I7mKZ9YIqioymCzLq9gwQbooMDQaHWBfEbwrbw"
"qHyGO0aoSCqI3Haadr8faqU9GY/rOPNk3sgrDQoo//fb4hVC1CLQJ13hef4Y53CI"
"rU7m2Ys6xt0nUW7/vGT1M0NPAgMBAAGjQjBAMA4GA1UdDwEB/wQEAwIBBjAPBgNV"
"HRMBAf8EBTADAQH/MB0GA1UdDgQWBBR5tFnme7bl5AFzgAiIyBpY9umbbjANBgkq"
"hkiG9w0BAQsFAAOCAgEAVR9YqbyyqFDQDLHYGmkgJykIrGF1XIpu+ILlaS/V9lZL"
"ubhzEFnTIZd+50xx+7LSYK05qAvqFyFWhfFQDlnrzuBZ6brJFe+GnY+EgPbk6ZGQ"
"3BebYhtF8GaV0nxvwuo77x/Py9auJ/GpsMiu/X1+mvoiBOv/2X/qkSsisRcOj/KK"
"NFtY2PwByVS5uCbMiogziUwthDyC3+6WVwW6LLv3xLfHTjuCvjHIInNzktHCgKQ5"
"ORAzI4JMPJ+GslWYHb4phowim57iaztXOoJwTdwJx4nLCgdNbOhdjsnvzqvHu7Ur"
"TkXWStAmzOVyyghqpZXjFaH3pO3JLF+l+/+sKAIuvtd7u+Nxe5AW0wdeRlN8NwdC"
"jNPElpzVmbUq4JUagEiuTDkHzsxHpFKVK7q4+63SM1N95R1NbdWhscdCb+ZAJzVc"
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"emyPxgcYxn/eR44/KJ4EBs+lVDR3veyJm+kXQ99b21/+jh5Xos1AnX5iItreGCc="
"\"},"
"{\"LEX3_isrg_root_x1\": \"" /* LE X3 signed by ISRG X1 root */
"MIIFjTCCA3WgAwIBAgIRANOxciY0IzLc9AUoUSrsnGowDQYJKoZIhvcNAQELBQAw"
"TzELMAkGA1UEBhMCVVMxKTAnBgNVBAoTIEludGVybmV0IFNlY3VyaXR5IFJlc2Vh"
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"2PGDuWx8M6DlS6qQkvHaRUo0FMd8TsSlbF0/v965qGFKhSDeQoMpYnwcmQilRh/0"
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"rUCGwbCUDI0mxadJ3Bz4WxR6fyNpBK2yAinWEsikxqEt"
"\"}"
"],"
"\"trust_stores\": [" /* named cert chains */
"{"
"\"name\": \"le_via_isrg\","
"\"stack\": ["
"\"isrg_root_x1\","
"\"LEX3_isrg_root_x1\""
"]"
"}"
"],"
"\"s\": ["
"{\"test_stream\": {"
"\"endpoint\":" "\"warmcat.com\","
"\"port\":" "443,"
"\"protocol\":" "\"h2\","
"\"http_method\":" "\"GET\","
"\"http_url\":" "\"index.html\","
"\"tls\":" "true,"
"\"opportunistic\":" "true,"
"\"retry\":" "\"default\","
"\"tls_trust_store\":" "\"le_via_isrg\""
"}},{"
/*
* "captive_portal_detect" describes
* what to do in order to check if the path to
* the Internet is being interrupted by a
* captive portal.
*/
"\"captive_portal_detect\": {"
"\"endpoint\":" "\"connectivitycheck.android.com\","
"\"http_url\":" "\"generate_204\","
"\"port\":" "80,"
"\"protocol\":" "\"h1\","
"\"http_method\":" "\"GET\","
"\"opportunistic\":" "true,"
"\"http_expect\":" "204,"
"\"http_fail_redirect\": true"
"}}"
"]}"
;

52
minimal-examples/embedded/esp32/esp-c3dev/main/ssd1306.h Normal file
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#if !defined(__LWS_SSD1306_H__)
#define __LWS_SSD1306_H__
/*
* D/C# pin on SSD1306 sets the I2C slave ads
* from these two options (7-bit address)
*/
#define SSD1306_I2C7_ADS1 0x3c
#define SSD1306_I2C7_ADS2 0x3d
enum {
SSD1306_SETLOWCOLUMN = 0x00,
SSD1306_SETHIGHCOLUMN = 0x10,
SSD1306_MEMORYMODE = 0x20,
SSD1306_COLUMNADDR = 0x21,
SSD1306_PAGEADDR = 0x22,
SSD1306_DEACTIVATE_SCROLL = 0x2e,
SSD1306_SETSTARTLINE = 0x40,
SSD1306_SETCONTRAST = 0x81,
SSD1306_CHARGEPUMP = 0x8d,
SSD1306_SEGREMAP = 0xa0,
SSD1306_SETSEGMENTREMAP = 0xa1,
SSD1306_DISPLAYALLON_RESUME = 0xa4,
SSD1306_DISPLAYALLON = 0xa5,
SSD1306_NORMALDISPLAY = 0xa6,
SSD1306_INVERTDISPLAY = 0xa7,
SSD1306_SETMULTIPLEX = 0xa8,
SSD1306_DISPLAYOFF = 0xae,
SSD1306_DISPLAYON = 0xaf,
SSD1306_COMSCANINC = 0xc0,
SSD1306_COMSCANDEC = 0xc8,
SSD1306_SETDISPLAYOFFSET = 0xd3,
SSD1306_SETDISPLAYCLOCKDIV = 0xd5,
SSD1306_SETPRECHARGE = 0xd9,
SSD1306_SETCOMPINS = 0xda,
SSD1306_SETVCOMDESELECT = 0xdb,
SSD1306_NOP = 0xe3,
SSD1306_EXTERNALVCC = 0x01,
SSD1306_SWITCHCAPVCC = 0x02,
};
#endif

5
minimal-examples/embedded/esp32/esp-c3dev/partitions.csv Normal file
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# ESP-IDF Partition Table
# Name, Type, SubType, Offset, Size, Flags
nvs, data, nvs, 0x9000, 0x6000,
phy_init, data, phy, 0xf000, 0x1000,
factory, app, factory, 0x10000, 2M,
1 # ESP-IDF Partition Table
2 # Name, Type, SubType, Offset, Size, Flags
3 nvs, data, nvs, 0x9000, 0x6000,
4 phy_init, data, phy, 0xf000, 0x1000,
5 factory, app, factory, 0x10000, 2M,

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minimal-examples/embedded/esp32/esp-c3dev/private-lib-plat-freertos.h Normal file
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/*
* libwebsockets - small server side websockets and web server implementation
*
* Copyright (C) 2010 - 2019 Andy Green <andy@warmcat.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
* deal in the Software without restriction, including without limitation the
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* Included from lib/private-lib-core.h if LWS_PLAT_FREERTOS
*/
#if !defined(LWS_ESP_PLATFORM)
#define SOMAXCONN 3
#endif
#if defined(LWS_AMAZON_RTOS)
int
open(const char *path, int oflag, ...);
#else
#include <fcntl.h>
#endif
#include <strings.h>
#include <unistd.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <sys/time.h>
#include <netdb.h>
#ifndef __cplusplus
#include <errno.h>
#endif
#include <signal.h>
#if defined(LWS_AMAZON_RTOS)
const char *
gai_strerror(int);
#else
#include <sys/socket.h>
#endif
#if defined(LWS_AMAZON_RTOS)
#include "FreeRTOS.h"
#if defined(LWS_WITH_SYS_ASYNC_DNS)
#include "FreeRTOS_IP.h"
#endif
#include "timers.h"
#include <esp_attr.h>
#else
#include "freertos/timers.h"
#include <esp_attr.h>
#include <esp_system.h>
#include <esp_task_wdt.h>
#endif
#if defined(LWS_WITH_ESP32)
#include "lwip/apps/sntp.h"
#include <errno.h>
#endif
typedef SemaphoreHandle_t lws_mutex_t;
#define lws_mutex_init(x) x = xSemaphoreCreateMutex()
#define lws_mutex_destroy(x) vSemaphoreDelete(x)
#define lws_mutex_lock(x) xSemaphoreTake(x, portMAX_DELAY)
#define lws_mutex_unlock(x) xSemaphoreGive(x)
#include <lwip/sockets.h>
#if defined(LWS_BUILTIN_GETIFADDRS)
#include "./misc/getifaddrs.h"
#endif
#define LWS_ERRNO errno
#define LWS_EAGAIN EAGAIN
#define LWS_EALREADY EALREADY
#define LWS_EINPROGRESS EINPROGRESS
#define LWS_EINTR EINTR
#define LWS_EISCONN EISCONN
#define LWS_ENOTCONN ENOTCONN
#define LWS_EWOULDBLOCK EWOULDBLOCK
#define LWS_EADDRINUSE EADDRINUSE
#define lws_set_blocking_send(wsi)
#ifndef LWS_NO_FORK
#ifdef LWS_HAVE_SYS_PRCTL_H
#include <sys/prctl.h>
#endif
#endif
#if !defined(MSG_NOSIGNAL)
#define MSG_NOSIGNAL 0
#endif
#define compatible_close(x) close(x)
#define lws_plat_socket_offset() LWIP_SOCKET_OFFSET
#define wsi_from_fd(A,B) A->lws_lookup[B - lws_plat_socket_offset()]
struct lws_context;
struct lws;
int
insert_wsi(const struct lws_context *context, struct lws *wsi);
#define delete_from_fd(A,B) A->lws_lookup[B - lws_plat_socket_offset()] = 0
#define LWS_PLAT_TIMER_TYPE TimerHandle_t
#define LWS_PLAT_TIMER_CB(name, var) void name(TimerHandle_t var)
#define LWS_PLAT_TIMER_CB_GET_OPAQUE(x) pvTimerGetTimerID(x)
#define LWS_PLAT_TIMER_CREATE(name, interval, repeat, opaque, cb) \
xTimerCreate(name, pdMS_TO_TICKS(interval) ? pdMS_TO_TICKS(interval) : 1, \
repeat ? pdTRUE : 0, opaque, cb)
#define LWS_PLAT_TIMER_DELETE(ptr) xTimerDelete(ptr, 0)
#define LWS_PLAT_TIMER_START(ptr) xTimerStart(ptr, 0)
#define LWS_PLAT_TIMER_STOP(ptr) xTimerStop(ptr, 0)

1301
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426
minimal-examples/embedded/esp32/esp-c3dev/sdkconfig.h Normal file
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/*
* Automatically generated file. DO NOT EDIT.
* Espressif IoT Development Framework (ESP-IDF) Configuration Header
*/
#pragma once
#define CONFIG_IDF_CMAKE 1
#define CONFIG_IDF_TARGET "esp32"
#define CONFIG_IDF_TARGET_ESP32 1
#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0000
#define CONFIG_SDK_TOOLPREFIX "xtensa-esp32-elf-"
#define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1
#define CONFIG_APP_BUILD_GENERATE_BINARIES 1
#define CONFIG_APP_BUILD_BOOTLOADER 1
#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1
#define CONFIG_APP_COMPILE_TIME_DATE 1
#define CONFIG_APP_RETRIEVE_LEN_ELF_SHA 16
#define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1
#define CONFIG_BOOTLOADER_LOG_LEVEL_INFO 1
#define CONFIG_BOOTLOADER_LOG_LEVEL 3
#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1
#define CONFIG_BOOTLOADER_WDT_ENABLE 1
#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000
#define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x0
#define CONFIG_ESPTOOLPY_BAUD_OTHER_VAL 115200
#define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1
#define CONFIG_ESPTOOLPY_FLASHMODE "dio"
#define CONFIG_ESPTOOLPY_FLASHFREQ_26M 1
#define CONFIG_ESPTOOLPY_FLASHFREQ "26m"
#define CONFIG_ESPTOOLPY_FLASHSIZE_2MB 1
#define CONFIG_ESPTOOLPY_FLASHSIZE "2MB"
#define CONFIG_ESPTOOLPY_FLASHSIZE_DETECT 1
#define CONFIG_ESPTOOLPY_BEFORE_RESET 1
#define CONFIG_ESPTOOLPY_BEFORE "default_reset"
#define CONFIG_ESPTOOLPY_AFTER_RESET 1
#define CONFIG_ESPTOOLPY_AFTER "hard_reset"
#define CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B 1
#define CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL 115200
#define CONFIG_ESPTOOLPY_MONITOR_BAUD 115200
#define CONFIG_PARTITION_TABLE_CUSTOM 1
#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv"
#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv"
#define CONFIG_PARTITION_TABLE_OFFSET 0x8000
#define CONFIG_PARTITION_TABLE_MD5 1
#define CONFIG_COMPILER_OPTIMIZATION_DEFAULT 1
#define CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE 1
#define CONFIG_COMPILER_STACK_CHECK_MODE_NONE 1
#define CONFIG_APPTRACE_DEST_NONE 1
#define CONFIG_APPTRACE_LOCK_ENABLE 1
#define CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF 0
#define CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF 0
#define CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF 0
#define CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF 0
#define CONFIG_BTDM_CTRL_PINNED_TO_CORE 0
#define CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF 1
#define CONFIG_BT_RESERVE_DRAM 0x0
#define CONFIG_COAP_MBEDTLS_PSK 1
#define CONFIG_COAP_LOG_DEFAULT_LEVEL 0
#define CONFIG_ADC_DISABLE_DAC 1
#define CONFIG_SPI_MASTER_ISR_IN_IRAM 1
#define CONFIG_SPI_SLAVE_ISR_IN_IRAM 1
#define CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4 1
#define CONFIG_EFUSE_MAX_BLK_LEN 192
#define CONFIG_ESP_TLS_USING_MBEDTLS 1
#define CONFIG_ESP32_REV_MIN_0 1
#define CONFIG_ESP32_REV_MIN 0
#define CONFIG_ESP32_DPORT_WORKAROUND 1
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_160 1
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 160
#define CONFIG_ESP32_TRACEMEM_RESERVE_DRAM 0x0
#define CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR 1
#define CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES 4
#define CONFIG_ESP32_ULP_COPROC_RESERVE_MEM 0
#define CONFIG_ESP32_DEBUG_OCDAWARE 1
#define CONFIG_ESP32_BROWNOUT_DET 1
#define CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_0 1
#define CONFIG_ESP32_BROWNOUT_DET_LVL 0
#define CONFIG_ESP32_REDUCE_PHY_TX_POWER 1
#define CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1 1
#define CONFIG_ESP32_RTC_CLK_SRC_INT_RC 1
#define CONFIG_ESP32_RTC_CLK_CAL_CYCLES 1024
#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000
#define CONFIG_ESP32_XTAL_FREQ_26 1
#define CONFIG_ESP32_XTAL_FREQ 26
#define CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL 5
#define CONFIG_ADC_CAL_EFUSE_TP_ENABLE 1
#define CONFIG_ADC_CAL_EFUSE_VREF_ENABLE 1
#define CONFIG_ADC_CAL_LUT_ENABLE 1
#define CONFIG_ESP_ERR_TO_NAME_LOOKUP 1
#define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32
#define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2304
#define CONFIG_ESP_MAIN_TASK_STACK_SIZE 6584
#define CONFIG_ESP_IPC_TASK_STACK_SIZE 1024
#define CONFIG_ESP_IPC_USES_CALLERS_PRIORITY 1
#define CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE 2048
#define CONFIG_ESP_CONSOLE_UART_DEFAULT 1
#define CONFIG_ESP_CONSOLE_UART_NUM 0
#define CONFIG_ESP_CONSOLE_UART_TX_GPIO 1
#define CONFIG_ESP_CONSOLE_UART_RX_GPIO 3
#define CONFIG_ESP_CONSOLE_UART_BAUDRATE 115200
#define CONFIG_ESP_INT_WDT 1
#define CONFIG_ESP_INT_WDT_TIMEOUT_MS 300
#define CONFIG_ESP_INT_WDT_CHECK_CPU1 1
#define CONFIG_ESP_TASK_WDT 1
#define CONFIG_ESP_TASK_WDT_TIMEOUT_S 5
#define CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 1
#define CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1
#define CONFIG_ETH_ENABLED 1
#define CONFIG_ETH_USE_ESP32_EMAC 1
#define CONFIG_ETH_PHY_INTERFACE_RMII 1
#define CONFIG_ETH_RMII_CLK_INPUT 1
#define CONFIG_ETH_RMII_CLK_IN_GPIO 0
#define CONFIG_ETH_DMA_BUFFER_SIZE 512
#define CONFIG_ETH_DMA_RX_BUFFER_NUM 10
#define CONFIG_ETH_DMA_TX_BUFFER_NUM 10
#define CONFIG_ETH_USE_SPI_ETHERNET 1
#define CONFIG_ESP_EVENT_POST_FROM_ISR 1
#define CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR 1
#define CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS 1
#define CONFIG_HTTPD_MAX_REQ_HDR_LEN 512
#define CONFIG_HTTPD_MAX_URI_LEN 512
#define CONFIG_HTTPD_ERR_RESP_NO_DELAY 1
#define CONFIG_HTTPD_PURGE_BUF_LEN 32
#define CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL 120
#define CONFIG_ESP_NETIF_TCPIP_LWIP 1
#define CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER 1
#define CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT 1
#define CONFIG_ESP_TIMER_TASK_STACK_SIZE 3584
#define CONFIG_ESP_TIMER_IMPL_TG0_LAC 1
#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 10
#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM 32
#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER 1
#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 1
#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32
#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1
#define CONFIG_ESP32_WIFI_TX_BA_WIN 6
#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1
#define CONFIG_ESP32_WIFI_RX_BA_WIN 6
#define CONFIG_ESP32_WIFI_NVS_ENABLED 1
#define CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0 1
#define CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN 752
#define CONFIG_ESP32_WIFI_MGMT_SBUF_NUM 32
#define CONFIG_ESP32_WIFI_IRAM_OPT 1
#define CONFIG_ESP32_WIFI_RX_IRAM_OPT 1
#define CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE 1
#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE 1
#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER 20
#define CONFIG_ESP32_PHY_MAX_TX_POWER 20
#define CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE 1
#define CONFIG_FATFS_CODEPAGE_437 1
#define CONFIG_FATFS_CODEPAGE 437
#define CONFIG_FATFS_LFN_NONE 1
#define CONFIG_FATFS_FS_LOCK 0
#define CONFIG_FATFS_TIMEOUT_MS 10000
#define CONFIG_FATFS_PER_FILE_CACHE 1
#define CONFIG_FMB_COMM_MODE_RTU_EN 1
#define CONFIG_FMB_COMM_MODE_ASCII_EN 1
#define CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND 150
#define CONFIG_FMB_MASTER_DELAY_MS_CONVERT 200
#define CONFIG_FMB_QUEUE_LENGTH 20
#define CONFIG_FMB_SERIAL_TASK_STACK_SIZE 2048
#define CONFIG_FMB_SERIAL_BUF_SIZE 256
#define CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB 8
#define CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS 1000
#define CONFIG_FMB_SERIAL_TASK_PRIO 10
#define CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT 20
#define CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE 20
#define CONFIG_FMB_CONTROLLER_STACK_SIZE 4096
#define CONFIG_FMB_EVENT_QUEUE_TIMEOUT 20
#define CONFIG_FMB_TIMER_PORT_ENABLED 1
#define CONFIG_FMB_TIMER_GROUP 0
#define CONFIG_FMB_TIMER_INDEX 0
#define CONFIG_FREERTOS_NO_AFFINITY 0x7FFFFFFF
#define CONFIG_FREERTOS_CORETIMER_0 1
#define CONFIG_FREERTOS_HZ 100
#define CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION 1
#define CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY 1
#define CONFIG_FREERTOS_INTERRUPT_BACKTRACE 1
#define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1
#define CONFIG_FREERTOS_ASSERT_FAIL_ABORT 1
#define CONFIG_FREERTOS_IDLE_TASK_STACKSIZE 1536
#define CONFIG_FREERTOS_ISR_STACKSIZE 1536
#define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16
#define CONFIG_FREERTOS_TIMER_TASK_PRIORITY 1
#define CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH 2048
#define CONFIG_FREERTOS_TIMER_QUEUE_LENGTH 10
#define CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE 0
#define CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER 1
#define CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER 1
#define CONFIG_FREERTOS_DEBUG_OCDAWARE 1
#define CONFIG_HEAP_POISONING_DISABLED 1
#define CONFIG_HEAP_TRACING_OFF 1
#define CONFIG_LOG_DEFAULT_LEVEL_INFO 1
#define CONFIG_LOG_DEFAULT_LEVEL 3
#define CONFIG_LOG_COLORS 1
#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1
#define CONFIG_LWIP_LOCAL_HOSTNAME "espressif"
#define CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES 1
#define CONFIG_LWIP_TIMERS_ONDEMAND 1
#define CONFIG_LWIP_MAX_SOCKETS 10
#define CONFIG_LWIP_SO_REUSE 1
#define CONFIG_LWIP_SO_REUSE_RXTOALL 1
#define CONFIG_LWIP_IP_FRAG 1
#define CONFIG_LWIP_ESP_GRATUITOUS_ARP 1
#define CONFIG_LWIP_GARP_TMR_INTERVAL 60
#define CONFIG_LWIP_TCPIP_RECVMBOX_SIZE 32
#define CONFIG_LWIP_DHCP_DOES_ARP_CHECK 1
#define CONFIG_LWIP_DHCPS_LEASE_UNIT 60
#define CONFIG_LWIP_DHCPS_MAX_STATION_NUM 8
#define CONFIG_LWIP_NETIF_LOOPBACK 1
#define CONFIG_LWIP_LOOPBACK_MAX_PBUFS 8
#define CONFIG_LWIP_MAX_ACTIVE_TCP 16
#define CONFIG_LWIP_MAX_LISTENING_TCP 16
#define CONFIG_LWIP_TCP_MAXRTX 12
#define CONFIG_LWIP_TCP_SYNMAXRTX 6
#define CONFIG_LWIP_TCP_MSS 1440
#define CONFIG_LWIP_TCP_TMR_INTERVAL 250
#define CONFIG_LWIP_TCP_MSL 60000
#define CONFIG_LWIP_TCP_SND_BUF_DEFAULT 5744
#define CONFIG_LWIP_TCP_WND_DEFAULT 5744
#define CONFIG_LWIP_TCP_RECVMBOX_SIZE 6
#define CONFIG_LWIP_TCP_QUEUE_OOSEQ 1
#define CONFIG_LWIP_TCP_OVERSIZE_MSS 1
#define CONFIG_LWIP_MAX_UDP_PCBS 16
#define CONFIG_LWIP_UDP_RECVMBOX_SIZE 6
#define CONFIG_LWIP_TCPIP_TASK_STACK_SIZE 3072
#define CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY 1
#define CONFIG_LWIP_TCPIP_TASK_AFFINITY 0x7FFFFFFF
#define CONFIG_LWIP_MAX_RAW_PCBS 16
#define CONFIG_LWIP_DHCP_MAX_NTP_SERVERS 1
#define CONFIG_LWIP_SNTP_UPDATE_DELAY 3600000
#define CONFIG_LWIP_ESP_LWIP_ASSERT 1
#define CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC 1
#define CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN 1
#define CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN 16384
#define CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN 4096
#define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE 1
#define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL 1
#define CONFIG_MBEDTLS_HARDWARE_AES 1
#define CONFIG_MBEDTLS_HARDWARE_MPI 1
#define CONFIG_MBEDTLS_HARDWARE_SHA 1
#define CONFIG_MBEDTLS_HAVE_TIME 1
#define CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT 1
#define CONFIG_MBEDTLS_TLS_SERVER 1
#define CONFIG_MBEDTLS_TLS_CLIENT 1
#define CONFIG_MBEDTLS_TLS_ENABLED 1
#define CONFIG_MBEDTLS_PSK_MODES 1
#define CONFIG_MBEDTLS_KEY_EXCHANGE_PSK 1
#define CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_PSK 1
#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK 1
#define CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_PSK 1
#define CONFIG_MBEDTLS_KEY_EXCHANGE_RSA 1
#define CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA 1
#define CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE 1
#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA 1
#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA 1
#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA 1
#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA 1
#define CONFIG_MBEDTLS_SSL_RENEGOTIATION 1
#define CONFIG_MBEDTLS_SSL_PROTO_TLS1 1
#define CONFIG_MBEDTLS_SSL_PROTO_TLS1_1 1
#define CONFIG_MBEDTLS_SSL_PROTO_TLS1_2 1
#define CONFIG_MBEDTLS_SSL_PROTO_DTLS 1
#define CONFIG_MBEDTLS_SSL_ALPN 1
#define CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS 1
#define CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS 1
#define CONFIG_MBEDTLS_AES_C 1
#define CONFIG_MBEDTLS_RC4_DISABLED 1
#define CONFIG_MBEDTLS_CCM_C 1
#define CONFIG_MBEDTLS_GCM_C 1
#define CONFIG_MBEDTLS_PEM_PARSE_C 1
#define CONFIG_MBEDTLS_PEM_WRITE_C 1
#define CONFIG_MBEDTLS_X509_CRL_PARSE_C 1
#define CONFIG_MBEDTLS_X509_CSR_PARSE_C 1
#define CONFIG_MBEDTLS_ECP_C 1
#define CONFIG_MBEDTLS_ECDH_C 1
#define CONFIG_MBEDTLS_ECDSA_C 1
#define CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED 1
#define CONFIG_MBEDTLS_ECP_NIST_OPTIM 1
#define CONFIG_MDNS_MAX_SERVICES 10
#define CONFIG_MDNS_TASK_PRIORITY 1
#define CONFIG_MDNS_TASK_AFFINITY_CPU0 1
#define CONFIG_MDNS_TASK_AFFINITY 0x0
#define CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS 2000
#define CONFIG_MDNS_TIMER_PERIOD_MS 100
#define CONFIG_MQTT_PROTOCOL_311 1
#define CONFIG_MQTT_TRANSPORT_SSL 1
#define CONFIG_MQTT_TRANSPORT_WEBSOCKET 1
#define CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE 1
#define CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF 1
#define CONFIG_NEWLIB_STDIN_LINE_ENDING_CR 1
#define CONFIG_OPENSSL_ASSERT_EXIT 1
#define CONFIG_PTHREAD_TASK_PRIO_DEFAULT 5
#define CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT 3072
#define CONFIG_PTHREAD_STACK_MIN 768
#define CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY 1
#define CONFIG_PTHREAD_TASK_CORE_DEFAULT -1
#define CONFIG_PTHREAD_TASK_NAME_DEFAULT "pthread"
#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
#define CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS 1
#define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1
#define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20
#define CONFIG_SPI_FLASH_ERASE_YIELD_TICKS 1
#define CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1
#define CONFIG_SPIFFS_MAX_PARTITIONS 3
#define CONFIG_SPIFFS_CACHE 1
#define CONFIG_SPIFFS_CACHE_WR 1
#define CONFIG_SPIFFS_PAGE_CHECK 1
#define CONFIG_SPIFFS_GC_MAX_RUNS 10
#define CONFIG_SPIFFS_PAGE_SIZE 256
#define CONFIG_SPIFFS_OBJ_NAME_LEN 32
#define CONFIG_SPIFFS_USE_MAGIC 1
#define CONFIG_SPIFFS_USE_MAGIC_LENGTH 1
#define CONFIG_SPIFFS_META_LENGTH 4
#define CONFIG_SPIFFS_USE_MTIME 1
#define CONFIG_USB_DESC_CUSTOM_VID 0x1234
#define CONFIG_USB_DESC_CUSTOM_PID 0x5678
#define CONFIG_UNITY_ENABLE_FLOAT 1
#define CONFIG_UNITY_ENABLE_DOUBLE 1
#define CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER 1
#define CONFIG_VFS_SUPPORT_IO 1
#define CONFIG_VFS_SUPPORT_DIR 1
#define CONFIG_VFS_SUPPORT_SELECT 1
#define CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT 1
#define CONFIG_VFS_SUPPORT_TERMIOS 1
#define CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS 1
#define CONFIG_VFS_SEMIHOSTFS_HOST_PATH_MAX_LEN 128
#define CONFIG_WL_SECTOR_SIZE_4096 1
#define CONFIG_WL_SECTOR_SIZE 4096
#define CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES 16
#define CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT 30
#define CONFIG_WPA_MBEDTLS_CRYPTO 1
/* List of deprecated options */
#define CONFIG_ADC2_DISABLE_DAC CONFIG_ADC_DISABLE_DAC
#define CONFIG_BROWNOUT_DET CONFIG_ESP32_BROWNOUT_DET
#define CONFIG_BROWNOUT_DET_LVL_SEL_0 CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_0
#define CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEFAULT
#define CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE
#define CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT
#define CONFIG_CONSOLE_UART_RX_GPIO CONFIG_ESP_CONSOLE_UART_RX_GPIO
#define CONFIG_CONSOLE_UART_TX_GPIO CONFIG_ESP_CONSOLE_UART_TX_GPIO
#define CONFIG_ESP32S2_PANIC_PRINT_REBOOT CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT
#define CONFIG_ESP32_APPTRACE_DEST_NONE CONFIG_APPTRACE_DEST_NONE
#define CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY
#define CONFIG_ESP32_PANIC_PRINT_REBOOT CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT
#define CONFIG_ESP32_PTHREAD_STACK_MIN CONFIG_PTHREAD_STACK_MIN
#define CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT CONFIG_PTHREAD_TASK_NAME_DEFAULT
#define CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT CONFIG_PTHREAD_TASK_PRIO_DEFAULT
#define CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT
#define CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC CONFIG_ESP32_RTC_CLK_SRC_INT_RC
#define CONFIG_ESP_GRATUITOUS_ARP CONFIG_LWIP_ESP_GRATUITOUS_ARP
#define CONFIG_FLASHMODE_DIO CONFIG_ESPTOOLPY_FLASHMODE_DIO
#define CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
#define CONFIG_GARP_TMR_INTERVAL CONFIG_LWIP_GARP_TMR_INTERVAL
#define CONFIG_INT_WDT CONFIG_ESP_INT_WDT
#define CONFIG_INT_WDT_CHECK_CPU1 CONFIG_ESP_INT_WDT_CHECK_CPU1
#define CONFIG_INT_WDT_TIMEOUT_MS CONFIG_ESP_INT_WDT_TIMEOUT_MS
#define CONFIG_IPC_TASK_STACK_SIZE CONFIG_ESP_IPC_TASK_STACK_SIZE
#define CONFIG_LOG_BOOTLOADER_LEVEL_INFO CONFIG_BOOTLOADER_LOG_LEVEL_INFO
#define CONFIG_MAIN_TASK_STACK_SIZE CONFIG_ESP_MAIN_TASK_STACK_SIZE
#define CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE
#define CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT
#define CONFIG_MB_CONTROLLER_STACK_SIZE CONFIG_FMB_CONTROLLER_STACK_SIZE
#define CONFIG_MB_EVENT_QUEUE_TIMEOUT CONFIG_FMB_EVENT_QUEUE_TIMEOUT
#define CONFIG_MB_MASTER_DELAY_MS_CONVERT CONFIG_FMB_MASTER_DELAY_MS_CONVERT
#define CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND
#define CONFIG_MB_QUEUE_LENGTH CONFIG_FMB_QUEUE_LENGTH
#define CONFIG_MB_SERIAL_BUF_SIZE CONFIG_FMB_SERIAL_BUF_SIZE
#define CONFIG_MB_SERIAL_TASK_PRIO CONFIG_FMB_SERIAL_TASK_PRIO
#define CONFIG_MB_SERIAL_TASK_STACK_SIZE CONFIG_FMB_SERIAL_TASK_STACK_SIZE
#define CONFIG_MB_TIMER_GROUP CONFIG_FMB_TIMER_GROUP
#define CONFIG_MB_TIMER_INDEX CONFIG_FMB_TIMER_INDEX
#define CONFIG_MB_TIMER_PORT_ENABLED CONFIG_FMB_TIMER_PORT_ENABLED
#define CONFIG_MONITOR_BAUD_115200B CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B
#define CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE
#define CONFIG_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEFAULT
#define CONFIG_POST_EVENTS_FROM_IRAM_ISR CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR
#define CONFIG_POST_EVENTS_FROM_ISR CONFIG_ESP_EVENT_POST_FROM_ISR
#define CONFIG_REDUCE_PHY_TX_POWER CONFIG_ESP32_REDUCE_PHY_TX_POWER
#define CONFIG_SEMIHOSTFS_HOST_PATH_MAX_LEN CONFIG_VFS_SEMIHOSTFS_HOST_PATH_MAX_LEN
#define CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS
#define CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS
#define CONFIG_STACK_CHECK_NONE CONFIG_COMPILER_STACK_CHECK_MODE_NONE
#define CONFIG_SUPPORT_TERMIOS CONFIG_VFS_SUPPORT_TERMIOS
#define CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT
#define CONFIG_SYSTEM_EVENT_QUEUE_SIZE CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE
#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE
#define CONFIG_TASK_WDT CONFIG_ESP_TASK_WDT
#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
#define CONFIG_TASK_WDT_TIMEOUT_S CONFIG_ESP_TASK_WDT_TIMEOUT_S
#define CONFIG_TCPIP_RECVMBOX_SIZE CONFIG_LWIP_TCPIP_RECVMBOX_SIZE
#define CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY
#define CONFIG_TCPIP_TASK_STACK_SIZE CONFIG_LWIP_TCPIP_TASK_STACK_SIZE
#define CONFIG_TCP_MAXRTX CONFIG_LWIP_TCP_MAXRTX
#define CONFIG_TCP_MSL CONFIG_LWIP_TCP_MSL
#define CONFIG_TCP_MSS CONFIG_LWIP_TCP_MSS
#define CONFIG_TCP_OVERSIZE_MSS CONFIG_LWIP_TCP_OVERSIZE_MSS
#define CONFIG_TCP_QUEUE_OOSEQ CONFIG_LWIP_TCP_QUEUE_OOSEQ
#define CONFIG_TCP_RECVMBOX_SIZE CONFIG_LWIP_TCP_RECVMBOX_SIZE
#define CONFIG_TCP_SND_BUF_DEFAULT CONFIG_LWIP_TCP_SND_BUF_DEFAULT
#define CONFIG_TCP_SYNMAXRTX CONFIG_LWIP_TCP_SYNMAXRTX
#define CONFIG_TCP_WND_DEFAULT CONFIG_LWIP_TCP_WND_DEFAULT
#define CONFIG_TIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH
#define CONFIG_TIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY
#define CONFIG_TIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH
#define CONFIG_TIMER_TASK_STACK_SIZE CONFIG_ESP_TIMER_TASK_STACK_SIZE
#define CONFIG_TOOLPREFIX CONFIG_SDK_TOOLPREFIX
#define CONFIG_UDP_RECVMBOX_SIZE CONFIG_LWIP_UDP_RECVMBOX_SIZE