From 2761badd0f190c56d14341ef2531613bea91e263 Mon Sep 17 00:00:00 2001
From: Andy Green <andy@warmcat.com>
Date: Wed, 6 Oct 2021 11:43:06 +0100
Subject: [PATCH] minimal: ss: embedded: RT595S ACM transport
Adds an example for NXP RT595S eval board, using serialized SS over CDC /
ACM USB composite device, one ttyACM for logs and the other for the SSS
link.
---
include/libwebsockets.h | 4 +-
.../lws-secure-streams-serialization.h | 1 +
lib/core-net/transport-mux-common.c | 5 +-
.../serialized/client/sspc-transport.c | 2 +-
.../embedded/rt595/hello_world/CMakeLists.txt | 159 +
.../embedded/rt595/hello_world/README.md | 275 +
.../rt595/hello_world/hello_world_v3_8.xml | 164 +
.../embedded/rt595/hello_world/libwebsockets | 1 +
.../project/.settings/language.settings.xml | 25 +
.../hello_world/project/CMSIS/cmsis_armcc.h | 894 +
.../project/CMSIS/cmsis_armclang.h | 1444 +
.../project/CMSIS/cmsis_armclang_ltm.h | 1891 +
.../project/CMSIS/cmsis_compiler.h | 283 +
.../hello_world/project/CMSIS/cmsis_gcc.h | 2168 +
.../hello_world/project/CMSIS/cmsis_iccarm.h | 964 +
.../hello_world/project/CMSIS/cmsis_version.h | 39 +
.../hello_world/project/CMSIS/core_cm33.h | 2910 +
.../hello_world/project/CMSIS/mpu_armv8.h | 346 +
.../hello_world/project/CMSIS/tz_context.h | 70 +
.../hello_world/project/Debug/MIMXRT595S.xml | 5 +
.../project/Debug/MIMXRT595S_part.xml | 2 +
.../project/Debug/crt_infolist.dtd | 279 +
...ev_composite_cdc_vcom_cdc_vcom_bm_Debug.ld | 233 +
...site_cdc_vcom_cdc_vcom_bm_Debug_library.ld | 17 +
...osite_cdc_vcom_cdc_vcom_bm_Debug_memory.ld | 32 +
..._cdc_vcom_cdc_vcom_bm_LinkServer_Debug.swd | 2 +
.../rt595/hello_world/project/Debug/makefile | 64 +
.../rt595/hello_world/project/board/board.c | 622 +
.../rt595/hello_world/project/board/board.h | 281 +
.../hello_world/project/board/clock_config.c | 246 +
.../hello_world/project/board/clock_config.h | 67 +
.../rt595/hello_world/project/board/pin_mux.c | 108 +
.../rt595/hello_world/project/board/pin_mux.h | 64 +
.../lists/fsl_component_generic_list.c | 493 +
.../lists/fsl_component_generic_list.h | 201 +
.../component/osa/fsl_os_abstraction.h | 906 +
.../component/osa/fsl_os_abstraction_bm.c | 1346 +
.../component/osa/fsl_os_abstraction_bm.h | 72 +
.../component/osa/fsl_os_abstraction_config.h | 44 +
.../project/component/uart/fsl_adapter_uart.h | 834 +
.../component/uart/fsl_adapter_usart.c | 1086 +
.../project/device/MIMXRT595S_cm33.h | 56136 ++++++++++++++++
.../project/device/MIMXRT595S_cm33_features.h | 627 +
.../project/device/fsl_device_registers.h | 44 +
.../project/device/system_MIMXRT595S_cm33.c | 232 +
.../project/device/system_MIMXRT595S_cm33.h | 124 +
.../hello_world/project/drivers/fsl_cache.c | 372 +
.../hello_world/project/drivers/fsl_cache.h | 267 +
.../hello_world/project/drivers/fsl_clock.c | 1845 +
.../hello_world/project/drivers/fsl_clock.h | 1540 +
.../hello_world/project/drivers/fsl_common.c | 83 +
.../hello_world/project/drivers/fsl_common.h | 293 +
.../project/drivers/fsl_common_arm.c | 233 +
.../project/drivers/fsl_common_arm.h | 660 +
.../project/drivers/fsl_flexcomm.c | 412 +
.../project/drivers/fsl_flexcomm.h | 64 +
.../hello_world/project/drivers/fsl_flexspi.c | 1157 +
.../hello_world/project/drivers/fsl_flexspi.h | 864 +
.../hello_world/project/drivers/fsl_gpio.c | 317 +
.../hello_world/project/drivers/fsl_gpio.h | 364 +
.../hello_world/project/drivers/fsl_iap.c | 222 +
.../hello_world/project/drivers/fsl_iap.h | 727 +
.../hello_world/project/drivers/fsl_iopctl.h | 116 +
.../hello_world/project/drivers/fsl_power.c | 1226 +
.../hello_world/project/drivers/fsl_power.h | 584 +
.../hello_world/project/drivers/fsl_reset.c | 164 +
.../hello_world/project/drivers/fsl_reset.h | 290 +
.../hello_world/project/drivers/fsl_usart.c | 1160 +
.../hello_world/project/drivers/fsl_usart.h | 866 +
...c_vcom_cdc_vcom_bm LinkServer Debug.launch | 95 +
.../project/flash_config/flash_config.c | 79 +
.../project/flash_config/flash_config.h | 101 +
.../hello_world/project/source/composite.c | 379 +
.../hello_world/project/source/composite.h | 87 +
.../project/source/semihost_hardfault.c | 98 +
.../project/source/sspc/binance-ss.c | 223 +
.../hello_world/project/source/sspc/get-ss.c | 71 +
.../hello_world/project/source/sspc/helpers.c | 151 +
.../hello_world/project/source/sspc/main.c | 130 +
.../hello_world/project/source/sspc/private.h | 51 +
.../hello_world/project/source/sspc/system.c | 277 +
.../project/source/sspc/transport-serial.c | 178 +
.../hello_world/project/source/sys/time.h | 0
.../hello_world/project/source/sys/types.h | 0
.../rt595/hello_world/project/source/unistd.h | 0
.../project/source/usb_device_config.h | 157 +
.../project/source/usb_device_descriptor.c | 814 +
.../project/source/usb_device_descriptor.h | 244 +
.../hello_world/project/source/virtual_com.c | 485 +
.../hello_world/project/source/virtual_com.h | 86 +
.../project/startup/startup_mimxrt595s_cm33.c | 856 +
.../usb/device/class/cdc/usb_device_cdc_acm.c | 931 +
.../usb/device/class/cdc/usb_device_cdc_acm.h | 270 +
.../usb/device/class/usb_device_class.c | 595 +
.../usb/device/class/usb_device_class.h | 439 +
.../project/usb/device/include/usb_device.h | 660 +
.../source/lpcip3511/usb_device_lpcip3511.c | 2567 +
.../source/lpcip3511/usb_device_lpcip3511.h | 318 +
.../usb/device/source/usb_device_ch9.c | 1135 +
.../usb/device/source/usb_device_ch9.h | 79 +
.../usb/device/source/usb_device_dci.c | 1399 +
.../usb/device/source/usb_device_dci.h | 170 +
.../inf/cdc.cat | Bin 0 -> 10093 bytes
.../inf/fsl_ucwxp.inf | 109 +
.../hello_world/project/usb/include/usb.h | 134 +
.../project/usb/include/usb_misc.h | 502 +
.../project/usb/include/usb_spec.h | 299 +
.../hello_world/project/usb/phy/usb_phy.c | 278 +
.../hello_world/project/usb/phy/usb_phy.h | 105 +
.../project/utilities/fsl_assert.c | 50 +
.../project/utilities/fsl_debug_console.c | 1877 +
.../project/utilities/fsl_debug_console.h | 224 +
112 files changed, 106337 insertions(+), 4 deletions(-)
create mode 100644 minimal-examples/embedded/rt595/hello_world/CMakeLists.txt
create mode 100644 minimal-examples/embedded/rt595/hello_world/README.md
create mode 100644 minimal-examples/embedded/rt595/hello_world/hello_world_v3_8.xml
create mode 120000 minimal-examples/embedded/rt595/hello_world/libwebsockets
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/.settings/language.settings.xml
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_armcc.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_armclang.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_armclang_ltm.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_compiler.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_gcc.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_iccarm.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_version.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/CMSIS/core_cm33.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/CMSIS/mpu_armv8.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/CMSIS/tz_context.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/Debug/MIMXRT595S.xml
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/Debug/MIMXRT595S_part.xml
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/Debug/crt_infolist.dtd
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug.ld
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug_library.ld
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug_memory.ld
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_LinkServer_Debug.swd
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/Debug/makefile
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/board/board.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/board/board.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/board/clock_config.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/board/clock_config.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/board/pin_mux.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/board/pin_mux.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/component/lists/fsl_component_generic_list.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/component/lists/fsl_component_generic_list.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction_bm.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction_bm.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction_config.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/component/uart/fsl_adapter_uart.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/component/uart/fsl_adapter_usart.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/device/MIMXRT595S_cm33.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/device/MIMXRT595S_cm33_features.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/device/fsl_device_registers.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/device/system_MIMXRT595S_cm33.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/device/system_MIMXRT595S_cm33.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_cache.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_cache.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_clock.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_clock.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common_arm.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common_arm.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexcomm.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexcomm.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexspi.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexspi.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_gpio.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_gpio.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_iap.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_iap.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_iopctl.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_power.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_power.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_reset.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_reset.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_usart.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_usart.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm LinkServer Debug.launch
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/flash_config/flash_config.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/flash_config/flash_config.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/composite.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/composite.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/semihost_hardfault.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/sspc/binance-ss.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/sspc/get-ss.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/sspc/helpers.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/sspc/main.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/sspc/private.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/sspc/system.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/sspc/transport-serial.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/sys/time.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/sys/types.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/unistd.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/usb_device_config.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/usb_device_descriptor.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/usb_device_descriptor.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/virtual_com.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/source/virtual_com.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/startup/startup_mimxrt595s_cm33.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/device/class/cdc/usb_device_cdc_acm.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/device/class/cdc/usb_device_cdc_acm.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/device/class/usb_device_class.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/device/class/usb_device_class.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/device/include/usb_device.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/device/source/lpcip3511/usb_device_lpcip3511.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/device/source/lpcip3511/usb_device_lpcip3511.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_ch9.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_ch9.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_dci.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_dci.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/example/usb_device_composite_cdc_vcom_cdc_vcom/inf/cdc.cat
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/example/usb_device_composite_cdc_vcom_cdc_vcom/inf/fsl_ucwxp.inf
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/include/usb.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/include/usb_misc.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/include/usb_spec.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/phy/usb_phy.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/usb/phy/usb_phy.h
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/utilities/fsl_assert.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/utilities/fsl_debug_console.c
create mode 100644 minimal-examples/embedded/rt595/hello_world/project/utilities/fsl_debug_console.h
diff --git a/include/libwebsockets.h b/include/libwebsockets.h
index 411587c08..1f437f456 100644
--- a/include/libwebsockets.h
+++ b/include/libwebsockets.h
@@ -38,7 +38,7 @@ extern "C" {
#include "lws_config.h"
-#ifdef LWS_HAVE_SYS_TYPES_H
+#if defined(LWS_HAVE_SYS_TYPES_H) && !defined(LWS_PLAT_BAREMETAL)
#include <sys/types.h>
#endif
@@ -145,6 +145,7 @@ typedef int suseconds_t;
#else /* NOT WIN32 */
#include <unistd.h>
+
#if defined(LWS_HAVE_SYS_CAPABILITY_H) && defined(LWS_HAVE_LIBCAP)
#include <sys/capability.h>
#endif
@@ -209,6 +210,7 @@ typedef int suseconds_t;
#endif /* not shared */
#define LWS_WARN_DEPRECATED __attribute__ ((deprecated))
+#undef printf
#define LWS_FORMAT(string_index) __attribute__ ((format(printf, string_index, string_index+1)))
#else /* not GNUC */
diff --git a/include/libwebsockets/lws-secure-streams-serialization.h b/include/libwebsockets/lws-secure-streams-serialization.h
index 911553779..acaec82db 100644
--- a/include/libwebsockets/lws-secure-streams-serialization.h
+++ b/include/libwebsockets/lws-secure-streams-serialization.h
@@ -527,6 +527,7 @@ typedef struct lws_transport_mux {
uint64_t us_ping_in;
uint64_t us_ping_out;
uint64_t us_unixtime_peer;
+ uint64_t us_unixtime_peer_loc;
uint64_t mp_time;
uint64_t mp_time1;
enum lwstmc_parser mp_state;
diff --git a/lib/core-net/transport-mux-common.c b/lib/core-net/transport-mux-common.c
index 5844a32b3..5911135e7 100644
--- a/lib/core-net/transport-mux-common.c
+++ b/lib/core-net/transport-mux-common.c
@@ -167,7 +167,7 @@ sul_ping_cb(lws_sorted_usec_list_t *sul)
sul_ping_cb, 2 * LWS_US_PER_SEC);
}
-#if defined(PICO_SDK_PATH)
+#if defined(PICO_SDK_PATH) || defined(LWS_PLAT_BAREMETAL)
#if 0
struct stv {
uint32_t tv_sec;
@@ -623,7 +623,8 @@ lws_transport_mux_rx_parse(lws_transport_mux_t *tm,
lwsl_user("%s: got PONGACK: ustime %llu\n",
__func__,
(unsigned long long)tm->mp_time);
- tm->us_unixtime_peer = tm->mp_time - get_us_timeofday();
+ tm->us_unixtime_peer = tm->mp_time;
+ tm->us_unixtime_peer_loc = (uint64_t)lws_now_usecs();
tm->mp_state = LWSTMCPAR_CMD;
lws_transport_set_link(tm, LWSTM_OPERATIONAL);
lws_sul_cancel(&tm->sul_ping);
diff --git a/lib/secure-streams/serialized/client/sspc-transport.c b/lib/secure-streams/serialized/client/sspc-transport.c
index a689b8974..f19e429cd 100644
--- a/lib/secure-streams/serialized/client/sspc-transport.c
+++ b/lib/secure-streams/serialized/client/sspc-transport.c
@@ -280,7 +280,7 @@ lws_sspc_txp_tx(lws_sspc_handle_t *h, size_t metadata_limit)
lws_ser_wu16be(s + 1, (uint16_t)txl);
/* SSSv1: add protocol version byte (initially 1) */
*(s + 3) = (uint8_t)LWS_SSS_CLIENT_PROTOCOL_VERSION;
-#if defined(WIN32)
+#if defined(WIN32) || defined(LWS_PLAT_BAREMETAL)
lws_ser_wu32be(s + 4, (uint32_t)0);
#else
lws_ser_wu32be(s + 4, (uint32_t)getpid());
diff --git a/minimal-examples/embedded/rt595/hello_world/CMakeLists.txt b/minimal-examples/embedded/rt595/hello_world/CMakeLists.txt
new file mode 100644
index 000000000..c33186cb9
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/CMakeLists.txt
@@ -0,0 +1,159 @@
+cmake_minimum_required(VERSION 3.13)
+
+set(TOOLCHAIN_PATH "/usr/local/mcuxpressoide-11.4.1_6260/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.4.0.202103011116/tools/bin/arm-none-eabi")
+
+set(CMAKE_C_COMPILER "${TOOLCHAIN_PATH}-gcc")
+set(CMAKE_CXX_COMPILER "${TOOLCHAIN_PATH}-g++")
+
+#
+# We set up the general build flags first so everything built the same.
+#
+# We build libwebsockets.a, with LWS_ONLY_SSPC and LWS_PLAT_BAREMETAL etc.
+#
+# Then we build project/ with LWS_SS_USE_SSPC and link him to our libwebsockets.a
+
+
+set(CMAKE_SYSTEM_NAME Generic)
+set(CMAKE_SYSTEM_PROCESSOR arm)
+set(CMAKE_CROSSCOMPILING 1)
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -specs=redlib.specs -fno-common -g3 -mcpu=cortex-m33 -ffunction-sections -fdata-sections -ffreestanding -fno-builtin -fmerge-constants -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -D__NEWLIB__ -nostdlib -Xlinker --gc-sections" )
+set(CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS}")
+#SET(CMAKE_FIND_ROOT_PATH ${TOOLCHAIN_DIR}/${TARGET_TRIPLET} ${EXTRA_FIND_PATH})
+SET(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
+SET(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
+SET(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
+
+project(rt500-hello C)
+add_link_options( -ffreestanding -nostdlib -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -Xlinker --gc-sections -L ${PROJECT_SOURCE_DIR}/project/Debug -T evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug.ld )
+
+
+set(LWS_WITH_SSL 0 CACHE BOOL a)
+set(LWS_WITH_TLS 0 CACHE BOOL b)
+set(LWS_WITH_SHARED 0 CACHE BOOL c)
+set(LWS_PLAT_BAREMETAL 1 CACHE BOOL d)
+set(LWS_WITH_NETWORK 0 CACHE BOOL e)
+set(LWS_ONLY_SSPC 1 CACHE BOOL f) # remove everything except SSPC pieces from library build
+
+include_directories(${PROJECT_SOURCE_DIR}/project/source)
+add_compile_definitions(
+ __REDLIB__
+ uid_t=int
+ gid_t=int
+ CPU_MIMXRT595SFFOC
+ CPU_MIMXRT595SFFOC_cm33
+ _DEBUG=1
+ BOOT_HEADER_ENABLE=1
+ CPU_MIMXRT595SEVKA=1
+ MCUXPRESSO_SDK
+ CR_INTEGER_PRINTF
+ PRINTF_FLOAT_ENABLE=0
+ __MCUXPRESSO
+ __USE_CMSIS
+ CPU_MIMXRT595SFAWC_cm33
+ SERIAL_PORT_TYPE_UART
+ ssize_t=long
+ )
+
+
+# build lws as part of this
+add_subdirectory(libwebsockets)
+
+add_executable(${PROJECT_NAME}
+ project/utilities/fsl_assert.c
+ project/utilities/fsl_debug_console.c
+ project/usb/phy/usb_phy.c
+ project/usb/device/source/lpcip3511/usb_device_lpcip3511.c
+ project/usb/device/source/usb_device_ch9.c
+ project/usb/device/source/usb_device_dci.c
+ project/usb/device/class/cdc/usb_device_cdc_acm.c
+ project/usb/device/class/usb_device_class.c
+ project/startup/startup_mimxrt595s_cm33.c
+ project/source/sspc/binance-ss.c
+ project/source/sspc/get-ss.c
+ project/source/sspc/helpers.c
+ project/source/sspc/main.c
+ project/source/sspc/system.c
+ project/source/sspc/transport-serial.c
+ project/source/composite.c
+ project/source/semihost_hardfault.c
+ project/source/usb_device_descriptor.c
+ project/source/virtual_com.c
+ project/flash_config/flash_config.c
+ project/drivers/fsl_cache.c
+ project/drivers/fsl_clock.c
+ project/drivers/fsl_common.c
+ project/drivers/fsl_common_arm.c
+ project/drivers/fsl_flexcomm.c
+ project/drivers/fsl_flexspi.c
+ project/drivers/fsl_gpio.c
+ project/drivers/fsl_iap.c
+ project/drivers/fsl_power.c
+ project/drivers/fsl_reset.c
+ project/drivers/fsl_usart.c
+ project/device/system_MIMXRT595S_cm33.c
+ project/component/uart/fsl_adapter_usart.c
+ project/component/osa/fsl_os_abstraction_bm.c
+ project/component/lists/fsl_component_generic_list.c
+ project/board/board.c
+ project/board/clock_config.c
+ project/board/pin_mux.c
+ )
+
+
+target_compile_definitions(${PROJECT_NAME} PUBLIC
+ __REDLIB__
+ uid_t=int
+ gid_t=int
+ STANDALONE=1
+ CPU_MIMXRT595SFFOC
+ CPU_MIMXRT595SFFOC_cm33
+ _DEBUG=1
+ BOOT_HEADER_ENABLE=1
+ FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1
+ USB_STACK_BM
+ CPU_MIMXRT595SEVKA=1
+ USB_STACK_USE_DEDICATED_RAM=1
+ FSL_OSA_BM_TASK_ENABLE=0
+ FSL_OSA_BM_TIMER_CONFIG=0
+ SDK_DEBUGCONSOLE=1
+ MCUXPRESSO_SDK
+ CR_INTEGER_PRINTF
+ PRINTF_FLOAT_ENABLE=0
+ __MCUXPRESSO
+ __USE_CMSIS
+ CPU_MIMXRT595SFAWC_cm33
+ SERIAL_PORT_TYPE_UART
+ LWS_SS_USE_SSPC)
+
+target_include_directories(${PROJECT_NAME} PRIVATE
+ project/board
+ project/devices/MIMXRT595S/drivers
+ project/devices/MIMXRT595S/
+ project/CMSIS/Core/Include
+ project/devices/MIMXRT595S/utilities/debug_console
+ project/component/lists
+ project/component/serial_manager
+ project/component/uart
+ project/component/osa
+ project/CMSIS
+ project/device
+ project/drivers
+ project/usb/include
+ project/usb/phy
+ project/usb/device/source
+ project/usb/device/class
+ project/usb/device/class/cdc
+ project/usb/device/source/lpcip3511
+ project/usb/device/include
+ project/source
+ project/source/sspc
+ project/utilities
+ # lws_config.h generated into here
+ ${PROJECT_BINARY_DIR}/libwebsockets
+ # source includes will do for everything else
+ libwebsockets/include )
+
+set_target_properties(${PROJECT_NAME} PROPERTIES SUFFIX ".axf")
+target_link_libraries(${PROJECT_NAME} websockets)
+
+
diff --git a/minimal-examples/embedded/rt595/hello_world/README.md b/minimal-examples/embedded/rt595/hello_world/README.md
new file mode 100644
index 000000000..d6bcf1289
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/README.md
@@ -0,0 +1,275 @@
+# SS example for RT595S Eval Board
+
+## Overview
+
+This example uses serialized Secure Streams to run the binance example and a
+simple get example stream on the RT595S eval board, via an SS proxy over the
+UART / CDC ACM link, with no networking available at the RT595S.
+
+It operates over a composite CDC ACM (ie, serial port) USB device link to a
+host PC, one CDC channel is used to show logs from the RT595S and the second is
+used to pass serialized SS to the SS proxy to make it work.
+
+It shows live information from binance, and every 5s does a get from
+libwebsockets.org and dumps the start and end of each chunk, demonstrating
+multiple streams working simultaneously over a single ACM link.
+
+## Setting up
+
+1) Set SW7 boot mode `1: OFF, 2: OFF, 3: ON`
+
+2) Hook J40 Micro USB B to Host PC -- this is the flashing tool connection
+ and appears as `/dev/ttyACM0`
+
+3) Hook J38 Micro USB B to Host PC -- this is the user USB connection we will
+ be controlling with this example, after it is flashed and running, it will
+ appear as `/dev/ttyACM1` and `2`
+
+4) Build lws on the host PC with `-DLWS_WITH_MINIMAL_EXAMPLES=1` and
+ `-DLWS_WITH_SECURE_STREAMS_PROXY_API=1`, it should produce an example in
+ the build dir `./bin/lws-minimal-ssproxy-custom-transport-uart`
+
+## Building
+
+First edit the `TOOLCHAIN_PATH` at the top of CMakeLists.txt in this dir to
+point to the NXP toolchain
+
+A typical path is like
+
+```
+set(TOOLCHAIN_PATH "/usr/local/mcuxpressoide-11.4.1_6260/ide/plugins/com.nxp.mcuxpresso.tools.linux_11.4.0.202103011116/tools/bin/arm-none-eabi")
+```
+
+Then build this example in a build dir
+
+```
+$ mkdir build <<<=== the subdir build is mandatory
+$ cd build
+$ cmake .. && make
+```
+
+...that builds a tiny libwebsockets.a and produces the `rt500-hello.axf`
+selfcontained elf already linked to the library.
+
+## Flashing the RT595S eval board
+
+To flash the board, run the commandline flasher that is part of mcuxpresso IDE,
+its path is like this
+
+```
+$ /usr/local/mcuxpressoide-11.4.1_6260/ide/plugins/com.nxp.mcuxpresso.tools.bin.linux_11.4.0.202109131312/binaries/crt_emu_cm_redlink
+ -flash-load-exec rt500-hello.axf \
+ -vendor=NXP \
+ -flash-driver=MIMXRT500_SFDP_MXIC_OSPI.cfx \
+ -p MIMXRT595S \
+ -x ../project/Debug
+```
+
+This will look like
+
+```
+Ns: MCUXpresso IDE RedlinkMulti Driver v11.4 (Sep 13 2021 15:09:55 - crt_emu_cm_redlink build 16)
+Wc(03). No cache support.
+Nc: Found chip XML file in ../project/Debug/MIMXRT595S.xml
+Nc: Reconnected to existing LinkServer process.
+Nc: Probe Firmware: LPC-LINK2 CMSIS-DAP V5.361 (NXP Semiconductors)
+Nc: Serial Number: FRAQBQAR
+Nc: VID:PID: 1FC9:0090
+Nc: USB Path: /dev/hidraw7
+Nc: Using memory from core 0 after searching for a good core
+Pc: ( 30) Emulator Connected
+Nc: processor is in secure mode
+Pc: ( 40) Debug Halt
+Pc: ( 50) CPU ID
+Nc: debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0
+Nc: processor type = Cortex-M33 (CPU ID 00000D21) on DAP AP 0
+Nc: number of h/w breakpoints = 8
+Nc: number of flash patches = 0
+Nc: number of h/w watchpoints = 4
+Nc: Probe(0): Connected&Reset. DpID: 6BA02477. CpuID: 00000D21. Info: <None>
+Nc: Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.
+Ns: Content of CoreSight Debug ROM(s):
+Nc: RBASE E00FE000: CID B105100D PID 0000095000 ROM (type 0x1)
+Nc: ROM 1 E00FF000: CID B105100D PID 04000BB4C9 ROM (type 0x1)
+Nc: ROM 2 E000E000: CID B105900D PID 04000BBD21 CSt ARM ARMv8-M type 0x0 Misc - Undefined
+Nc: ROM 2 E0001000: CID B105900D PID 04000BBD21 CSt ARM DWTv2 type 0x0 Misc - Undefined
+Nc: ROM 2 E0002000: CID B105900D PID 04000BBD21 CSt ARM FPBv2 type 0x0 Misc - Undefined
+Nc: ROM 2 E0000000: CID B105900D PID 04000BBD21 CSt ARM ITMv2 type 0x43 Trace Source - Bus
+Nc: ROM 2 E0041000: CID B105900D PID 04002BBD21 CSt ARM ETMv4.0 type 0x13 Trace Source - Core
+Nc: ROM 2 E0042000: CID B105900D PID 04000BBD21 CSt ARM CTIv2 type 0x14 Debug Control - Trigger, e.g. ECT
+Nc: ROM 1 E0040000: CID B105900D PID 04000BBD21 CSt type 0x11 Trace Sink - TPIU
+Nc: NXP: MIMXRT595S
+Nc: DAP stride is 1024 bytes (256 words)
+Nc: Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MIMXRT500_SFDP_MXIC_OSPI.cfx
+Nc: Image 'iMXRT500_SFDP_MXIC_OSPI Sep 14 2021 15:07:17'
+Nc: Opening flash driver MIMXRT500_SFDP_MXIC_OSPI.cfx
+Nc: Sending VECTRESET to run flash driver
+Nc: Flash variant 'JEDEC_FlexSPI_Device' detected (64MB = 1024*64K at 0x8000000)
+Nc: Closing flash driver MIMXRT500_SFDP_MXIC_OSPI.cfx
+Nt: Loading 'rt500-hello.axf' ELF 0x08000000 len 0x17F90
+Nc: Opening flash driver MIMXRT500_SFDP_MXIC_OSPI.cfx (already resident)
+Nc: Sending VECTRESET to run flash driver
+Nc: Flash variant 'JEDEC_FlexSPI_Device' detected (64MB = 1024*64K at 0x8000000)
+Nc: Sectors written: 2, unchanged: 0, total: 2
+Nc: Closing flash driver MIMXRT500_SFDP_MXIC_OSPI.cfx
+Nt: Loaded 0x17F90 bytes in 1094ms (about 89kB/s)
+Nt: Reset target (system)
+Nc: Starting execution using system reset
+Nc: processor is in non-secure mode
+Nc: state - running or following reset request - re-read of state failed - rc Nn(05). Wire ACK Fault in DAP access
+Xw:
+```
+
+... the last bit is normal, the cpu is reset and running the flashed code.
+
+## Connecting a logging console
+
+You should be able to open a terminal emulator on the host PC to `/dev/ttyACM1`,
+the baud rate and other serial details are ignored, so 115200/8/N/1 is fine.
+The log shows the logging of the firmware running on the RT595S, initially
+something like
+
+```
+17227078: (null): sul_ping_cb: no PONG came
+19227106: (null): sul_ping_cb: issuing ping
+21227133: (null): sul_ping_cb: no PONG came
+23227160: (null): sul_ping_cb: issuing ping
+25227186: (null): sul_ping_cb: no PONG came
+27227214: (null): sul_ping_cb: issuing ping
+29227240: (null): sul_ping_cb: no PONG came
+```
+
+since there is no SS proxy for it to link up to yet.
+
+If you run on the host PC from the lws build dir
+
+```
+$ ./bin/lws-minimal-ssproxy-custom-transport-uart -i /dev/ttyACM2
+```
+
+then after a second or two the RT595 firmware and the SS proxy should link up
+over ttyACM2, and start updating the bitcoin information and dumping the GET
+every 5s. That looks like this kind of thing
+
+```
+155228906: (null): sul_ping_cb: issuing ping
+157228932: (null): sul_ping_cb: no PONG came
+157633108: lws_sspc_create: txp path txp_inside_sspc -> txpmuxc
+157633235: (null): lws_transport_mux_retry_connect
+157633286: (null): lws_transport_path_client_dump: lws_transport_mux_retry_connect: MUX: 0x852ec, IN: ops=txp_inside_sspc, priv=0x853f8, ONW: ops=txpmuxc, priv=0x0
+157633333: (null): lws_transport_mux_retry_connect: transport not operational
+157633375: binance_state: LWSSSCS_UPSTREAM_LINK_RETRY (18), ord 0x0
+157633444: lws_sspc_create: txp path txp_inside_sspc -> txpmuxc
+157633481: (null): lws_transport_mux_retry_connect
+157633530: (null): lws_transport_path_client_dump: lws_transport_mux_retry_connect: MUX: 0x852ec, IN: ops=txp_inside_sspc, priv=0x876d4, ONW: ops=txpmuxc, priv=0x0
+157633579: (null): lws_transport_mux_retry_connect: transport not operational
+157633616: get_state: LWSSSCS_UPSTREAM_LINK_RETRY (18), ord 0x0
+157633685: (null): lws_transport_mux_rx_parse: got PING
+157633779: (null): lws_transport_mux_pending: send RESET_TRANSPORT
+157633824: (null): lws_transport_mux_pending: issuing PING
+157633864: (null): lws_transport_mux_pending: issuing PONG
+157633924: (null): lws_transport_path_client_dump: cpath: MUX: 0x0, IN: ops=txpmuxc, priv=0x852ec (IsTM), ONW: ops=txpserial, priv=0x0
+157633966: (null): txp_serial_write: writing 27
+157634016: (null): lws_transport_mux_rx_parse: PONG payload mismatch 0xab4fba 0x9654d3d
+157634180: (null): lws_transport_mux_rx_parse: got PONG
+157634213: (null): lws_transport_mux_rx_parse: got PONGACK: ustime 1635076485985673
+157634252: (null): lws_transport_set_link: ******* transport mux link is UP
+157634305: (null): lws_transport_mux_pending: issuing PONGACK
+157634370: (null): lws_transport_path_client_dump: cpath: MUX: 0x0, IN: ops=txpmuxc, priv=0x852ec (IsTM), ONW: ops=txpserial, priv=0x0
+157634414: (null): txp_serial_write: writing 9
+158633431: (null): lws_transport_mux_retry_connect
+158633480: (null): lws_transport_path_client_dump: lws_transport_mux_retry_connect: MUX: 0x852ec, IN: ops=txp_inside_sspc, priv=0x853f8, ONW: ops=txpmuxc, priv=0x0
+158633537: (null): lws_transport_mux_retry_connect: added channel
+158633618: (null): lws_transport_path_client_dump: cpath: MUX: 0x0, IN: ops=txpmuxc, priv=0x852ec (IsTM), ONW: ops=txpserial, priv=0x0
+158633659: (null): txp_serial_write: writing 2
+158633689: (null): lws_transport_mux_retry_connect
+158633737: (null): lws_transport_path_client_dump: lws_transport_mux_retry_connect: MUX: 0x852ec, IN: ops=txp_inside_sspc, priv=0x876d4, ONW: ops=txpmuxc, priv=0x0
+158633788: (null): lws_transport_mux_retry_connect: added channel
+158633890: (null): lws_transport_path_client_dump: cpath: MUX: 0x0, IN: ops=txpmuxc, priv=0x852ec (IsTM), ONW: ops=txpserial, priv=0x0
+158633931: (null): txp_serial_write: writing 2
+158634079: (null): lws_transport_mux_rx_parse: ch 255 fully open
+158634112: ltm_ch_opens: 0
+158634143: lws_sspc_txp_connect_disposition: CONNECTED (binance), txpmuxc
+158634213: (null): lws_transport_mux_write: 19
+158634249: (null): txp_serial_write: writing 23
+158634292: (null): lws_transport_mux_rx_parse: ch 254 fully open
+158634330: ltm_ch_opens: 0
+158634358: lws_sspc_txp_connect_disposition: CONNECTED (mintest-lws), txpmuxc
+158634456: (null): lws_transport_mux_write: 23
+158634484: (null): txp_serial_write: writing 27
+158634845: lws_ss_serialize_state_transition: LPCSCLI_WAITING_CREATE_RESULT -> LPCSCLI_LOCAL_CONNECTED
+158634896: lws_ss_check_next_state_sspc: (unset) -> LWSSSCS_CREATING
+158634933: binance_state: LWSSSCS_CREATING (1), ord 0x0
+158635016: lws_sspc_txp_tx: (local_conn) onward connect
+158635062: (null): lws_transport_mux_write: 3
+158635089: (null): txp_serial_write: writing 7
+158635144: lws_ss_check_next_state_sspc: LWSSSCS_CREATING -> LWSSSCS_CONNECTING
+158635191: binance_state: LWSSSCS_CONNECTING (6), ord 0x0
+158635303: lws_ss_serialize_state_transition: LPCSCLI_WAITING_CREATE_RESULT -> LPCSCLI_LOCAL_CONNECTED
+158635345: lws_ss_check_next_state_sspc: (unset) -> LWSSSCS_CREATING
+158635381: get_state: LWSSSCS_CREATING (1), ord 0x0
+158635467: lws_sspc_txp_tx: (local_conn) onward connect
+158635503: (null): lws_transport_mux_write: 3
+158635530: (null): txp_serial_write: writing 7
+158635816: lws_ss_check_next_state_sspc: LWSSSCS_CREATING -> LWSSSCS_CONNECTING
+158635853: get_state: LWSSSCS_CONNECTING (6), ord 0x0
+159693591: lws_sspc_deserialize_parse: CONNECTED binance
+159693623: lws_ss_serialize_state_transition: LPCSCLI_LOCAL_CONNECTED -> LPCSCLI_OPERATIONAL
+159693665: lws_ss_check_next_state_sspc: LWSSSCS_CONNECTING -> LWSSSCS_CONNECTED
+159693701: binance_state: LWSSSCS_CONNECTED (5), ord 0x0
+160693746: (null): sul_hz_cb: price: min: 6031470¢, max: 6032348¢, avg: 6031713¢, (31 prices/s)
+160693801: (null): sul_hz_cb: elatency: min: 136ms, max: 361ms, avg: 206ms, (31 msg/s, 72 KiBytes/s SS RX)
+161693748: (null): sul_hz_cb: price: min: 6028681¢, max: 6032500¢, avg: 6030043¢, (30 prices/s)
+161693801: (null): sul_hz_cb: elatency: min: 136ms, max: 175ms, avg: 144ms, (30 msg/s, 126 KiBytes/s SS RX)
+162693751: (null): sul_hz_cb: price: min: 5968822¢, max: 6029283¢, avg: 6026034¢, (30 prices/s)
+162693812: (null): sul_hz_cb: elatency: min: 135ms, max: 173ms, avg: 142ms, (30 msg/s, 123 KiBytes/s SS RX)
+162800988: get_rx: RX 5, flags 0x43
+162801104: (null): 0000: 7B 22 70 65 65 00 00 00 00 00 00 F4 3C A8 9B AA {"pee.......<...
+162801135: (null):
+162801221: lws_sspc_deserialize_parse: CONNECTED mintest-lws
+162801254: lws_ss_serialize_state_transition: LPCSCLI_LOCAL_CONNECTED -> LPCSCLI_OPERATIONAL
+162801297: lws_ss_check_next_state_sspc: LWSSSCS_CONNECTING -> LWSSSCS_CONNECTED
+162801335: get_state: LWSSSCS_CONNECTED (5), ord 0x0
+162802084: get_rx: RX 1520, flags 0x1
+162802194: (null): 0000: 3C 21 44 4F 43 54 59 50 45 20 68 74 6D 6C 3E 0A <!DOCTYPE html>.
+162802226: (null):
+162802318: (null): 0000: 3C 6C 69 3E 38 30 20 6D 69 6E 69 6D 61 6C 20 65 <li>80 minimal e
+162802352: (null):
+162802731: get_rx: RX 1520, flags 0x0
+162802840: (null): 0000: 78 61 6D 70 6C 65 73 3A 20 3C 61 20 68 72 65 66 xamples: <a href
+162802872: (null):
+162802964: (null): 0000: AD 98 3C 2F 74 64 3E 3C 74 64 20 63 6C 61 73 73 ..</td><td class
+162802998: (null):
+162803403: get_rx: RX 1520, flags 0x0
+162803512: (null): 0000: 3D 22 67 22 3E E2 AD 98 3C 2F 74 64 3E 3C 2F 74 ="g">...</td></t
+162803544: (null):
+162803636: (null): 0000: 77 65 62 73 6F 63 6B 65 74 73 2F 74 72 65 65 2F websockets/tree/
+162803670: (null):
+162804105: get_rx: RX 1520, flags 0x0
+162804215: (null): 0000: 6C 69 62 2F 65 76 65 6E 74 2D 6C 69 62 73 22 20 lib/event-libs"
+162804247: (null):
+162804339: (null): 0000: 31 36 20 69 62 22 3E 0A 20 20 20 20 20 3C 68 31 16 ib">. <h1
+162804373: (null):
+162804708: get_rx: RX 1277, flags 0x0
+162804818: (null): 0000: 3E 51 41 3C 2F 68 31 3E 0A 20 20 20 20 20 20 4C >QA</h1>. L
+162804849: (null):
+162804941: (null): 0000: 3C 2F 62 6F 64 79 3E 0A 3C 2F 68 74 6D 6C 3E 0A </body>.</html>.
+162804975: (null):
+162805084: get_rx: RX 0, flags 0x2
+162805120: lws_ss_check_next_state_sspc: LWSSSCS_CONNECTED -> LWSSSCS_QOS_ACK_REMOTE
+162805160: get_state: LWSSSCS_QOS_ACK_REMOTE (10), ord 0x0
+162805198: lws_ss_serialize_state_transition: LPCSCLI_OPERATIONAL -> LPCSCLI_LOCAL_CONNECTED
+162805239: lws_ss_check_next_state_sspc: LWSSSCS_QOS_ACK_REMOTE -> LWSSSCS_DISCONNECTED
+162805276: get_state: LWSSSCS_DISCONNECTED (2), ord 0x0
+163635428: (null): lws_sspc_request_tx: state 8, conn_req_state 0
+163635484: lws_sspc_txp_tx: (local_conn) onward connect
+163635527: (null): lws_transport_mux_write: 3
+163635555: (null): txp_serial_write: writing 7
+163636075: lws_ss_check_next_state_sspc: LWSSSCS_DISCONNECTED -> LWSSSCS_CONNECTING
+163636114: get_state: LWSSSCS_CONNECTING (6), ord 0x0
+163693754: (null): sul_hz_cb: price: min: 6025722¢, max: 6026388¢, avg: 6026199¢, (31 prices/s)
+163693805: (null): sul_hz_cb: elatency: min: 134ms, max: 170ms, avg: 139ms, (31 msg/s, 72 KiBytes/s SS RX)
+164693759: (null): sul_hz_cb: price: min: 6025359¢, max: 6026340¢, avg: 6025954¢, (30 prices/s)
+164693810: (null): sul_hz_cb: elatency: min: 135ms, max: 143ms, avg: 137ms, (30 msg/s, 93 KiBytes/s SS RX)
+...
+```
diff --git a/minimal-examples/embedded/rt595/hello_world/hello_world_v3_8.xml b/minimal-examples/embedded/rt595/hello_world/hello_world_v3_8.xml
new file mode 100644
index 000000000..26a54add8
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/hello_world_v3_8.xml
@@ -0,0 +1,164 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
+ <externalDefinitions>
+ <definition extID="cm33_MIMXRT595S"/>
+ <definition extID="platform.drivers.common.MIMXRT595S"/>
+ <definition extID="platform.drivers.clock.MIMXRT595S"/>
+ <definition extID="platform.drivers.power.MIMXRT595S"/>
+ <definition extID="platform.drivers.reset.MIMXRT595S"/>
+ <definition extID="device.MIMXRT595S_CMSIS.MIMXRT595S"/>
+ <definition extID="utility.debug_console.MIMXRT595S"/>
+ <definition extID="platform.utilities.assert.MIMXRT595S"/>
+ <definition extID="component.usart_adapter.MIMXRT595S"/>
+ <definition extID="platform.drivers.flexspi.MIMXRT595S"/>
+ <definition extID="platform.drivers.cache_cache64.MIMXRT595S"/>
+ <definition extID="component.serial_manager.MIMXRT595S"/>
+ <definition extID="component.lists.MIMXRT595S"/>
+ <definition extID="component.serial_manager_uart.MIMXRT595S"/>
+ <definition extID="platform.drivers.flexcomm_usart.MIMXRT595S"/>
+ <definition extID="platform.drivers.flash_config.MIMXRT595S"/>
+ <definition extID="device.MIMXRT595S_startup.MIMXRT595S"/>
+ <definition extID="platform.drivers.flexcomm.MIMXRT595S"/>
+ <definition extID="platform.drivers.lpc_iopctl.MIMXRT595S"/>
+ <definition extID="platform.drivers.lpc_gpio.MIMXRT595S"/>
+ <definition extID="CMSIS_Include_core_cm.MIMXRT595S"/>
+ <definition extID="platform.utilities.misc_utilities.MIMXRT595S"/>
+ <definition extID="platform.drivers.iap.MIMXRT595S"/>
+ <definition extID="iar"/>
+ <definition extID="mdk"/>
+ <definition extID="armgcc"/>
+ <definition extID="mcuxpresso"/>
+ <definition extID="com.nxp.mcuxpresso"/>
+ <definition extID="com.crt.advproject.config.exe.debug"/>
+ <definition extID="com.crt.advproject.config.exe.release"/>
+ </externalDefinitions>
+ <example id="evkmimxrt595_hello_world" name="hello_world" device_core="cm33_MIMXRT595S" dependency="platform.drivers.common.MIMXRT595S platform.drivers.clock.MIMXRT595S platform.drivers.power.MIMXRT595S platform.drivers.reset.MIMXRT595S device.MIMXRT595S_CMSIS.MIMXRT595S utility.debug_console.MIMXRT595S platform.utilities.assert.MIMXRT595S component.usart_adapter.MIMXRT595S platform.drivers.flexspi.MIMXRT595S platform.drivers.cache_cache64.MIMXRT595S component.serial_manager.MIMXRT595S component.lists.MIMXRT595S component.serial_manager_uart.MIMXRT595S platform.drivers.flexcomm_usart.MIMXRT595S platform.drivers.flash_config.MIMXRT595S device.MIMXRT595S_startup.MIMXRT595S platform.drivers.flexcomm.MIMXRT595S platform.drivers.lpc_iopctl.MIMXRT595S platform.drivers.lpc_gpio.MIMXRT595S CMSIS_Include_core_cm.MIMXRT595S platform.utilities.misc_utilities.MIMXRT595S platform.drivers.iap.MIMXRT595S" category="demo_apps">
+ <projects>
+ <project type="com.crt.advproject.projecttype.exe" nature="org.eclipse.cdt.core.cnature"/>
+ </projects>
+ <memory>
+ <memoryBlock id="QSPI_FLASH_MIMXRT595S" name="QSPI_FLASH" addr="08000000" size="04000000" type="ExtFlash" access="RO"/>
+ <memoryBlock id="SRAM_MIMXRT595S" name="SRAM" addr="20080000" size="00280000" type="RAM" access="RW"/>
+ <memoryBlock id="USB_RAM_MIMXRT595S" name="USB_RAM" addr="40140000" size="00004000" type="RAM" access="RW"/>
+ </memory>
+ <toolchainSettings>
+ <toolchainSetting id_refs="com.nxp.mcuxpresso">
+ <option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
+ <value>CPU_MIMXRT595SFFOC_cm33</value>
+ <value>BOOT_HEADER_ENABLE=1</value>
+ <value>FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1</value>
+ <value>SERIAL_PORT_TYPE_UART=1</value>
+ <value>MCUXPRESSO_SDK</value>
+ </option>
+ <option id="com.crt.advproject.gas.fpu" type="enum">
+ <value>com.crt.advproject.gas.fpu.fpv5sp.hard</value>
+ </option>
+ <option id="com.crt.advproject.gcc.fpu" type="enum">
+ <value>com.crt.advproject.gcc.fpu.fpv5sp.hard</value>
+ </option>
+ <option id="gnu.c.compiler.option.optimization.flags" type="string">
+ <value>-fno-common</value>
+ </option>
+ <option id="com.crt.advproject.c.misc.dialect" type="enum">
+ <value>com.crt.advproject.misc.dialect.gnu99</value>
+ </option>
+ <option id="gnu.c.compiler.option.misc.other" type="string">
+ <value>-mcpu=cortex-m33 -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
+ </option>
+ <option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
+ <value>false</value>
+ </option>
+ <option id="com.crt.advproject.link.fpu" type="enum">
+ <value>com.crt.advproject.link.fpu.fpv5sp.hard</value>
+ </option>
+ <option id="gnu.c.link.option.nostdlibs" type="boolean">
+ <value>true</value>
+ </option>
+ </toolchainSetting>
+ </toolchainSettings>
+ <debug_configurations>
+ <debug_configuration id_refs="com.crt.advproject.config.exe.debug com.crt.advproject.config.exe.release">
+ <drivers>
+ <driver id_refs="QSPI_FLASH_MIMXRT595S">
+ <driverBinary path="devices/MIMXRT595S/mcuxpresso" project_relative_path="binary" type="binary">
+ <files mask="MIMXRT500_SFDP_MXIC_OSPI.cfx"/>
+ </driverBinary>
+ </driver>
+ </drivers>
+ </debug_configuration>
+ </debug_configurations>
+ <include_paths>
+ <include_path path="boards/evkmimxrt595/demo_apps/hello_world" project_relative_path="board" type="c_include"/>
+ <include_path path="boards/evkmimxrt595/demo_apps/hello_world" project_relative_path="evkmimxrt595/demo_apps/hello_world" type="c_include"/>
+ </include_paths>
+ <source path="boards/evkmimxrt595/demo_apps/hello_world/iar" project_relative_path="./" type="workspace" toolchain="iar">
+ <files mask="hello_world.ewd"/>
+ <files mask="hello_world.ewp"/>
+ <files mask="hello_world.eww"/>
+ </source>
+ <source path="boards/evkmimxrt595/demo_apps/hello_world/mdk" project_relative_path="./" type="workspace" toolchain="mdk">
+ <files mask="hello_world.uvoptx"/>
+ <files mask="hello_world.uvprojx"/>
+ <files mask="JLinkSettings.ini"/>
+ <files mask="hello_world.uvmpw"/>
+ </source>
+ <source path="boards/evkmimxrt595/demo_apps/hello_world/armgcc" project_relative_path="./" type="workspace" toolchain="armgcc">
+ <files mask="build_all.bat"/>
+ <files mask="build_all.sh"/>
+ <files mask="clean.bat"/>
+ <files mask="clean.sh"/>
+ <files mask="CMakeLists.txt"/>
+ <files mask="flags.cmake"/>
+ <files mask="config.cmake"/>
+ <files mask="build_debug.bat"/>
+ <files mask="build_debug.sh"/>
+ <files mask="build_release.bat"/>
+ <files mask="build_release.sh"/>
+ <files mask="build_flash_debug.bat"/>
+ <files mask="build_flash_debug.sh"/>
+ <files mask="build_flash_release.bat"/>
+ <files mask="build_flash_release.sh"/>
+ </source>
+ <source path="boards/evkmimxrt595/demo_apps/hello_world" project_relative_path="source" type="src">
+ <files mask="hello_world.c"/>
+ </source>
+ <source path="boards/evkmimxrt595/demo_apps/hello_world" project_relative_path="board" type="src">
+ <files mask="pin_mux.c"/>
+ </source>
+ <source path="boards/evkmimxrt595/demo_apps/hello_world" project_relative_path="board" type="c_include">
+ <files mask="pin_mux.h"/>
+ </source>
+ <source path="boards/evkmimxrt595/demo_apps/hello_world" project_relative_path="." type="other">
+ <files mask="hello_world.mex" hidden="true"/>
+ </source>
+ <source path="boards/evkmimxrt595/demo_apps/hello_world" project_relative_path="evkmimxrt595/demo_apps/hello_world" type="binary">
+ <files mask="hello_world.bin" hidden="true"/>
+ </source>
+ <source path="boards/evkmimxrt595/demo_apps/hello_world" project_relative_path="board" type="src">
+ <files mask="board.c"/>
+ <files mask="clock_config.c"/>
+ </source>
+ <source path="boards/evkmimxrt595/demo_apps/hello_world" project_relative_path="board" type="c_include">
+ <files mask="board.h"/>
+ <files mask="clock_config.h"/>
+ </source>
+ <source path="boards/evkmimxrt595/demo_apps/hello_world" project_relative_path="doc" type="doc" toolchain="iar mdk mcuxpresso armgcc">
+ <files mask="readme.txt"/>
+ </source>
+ <source path="boards/evkmimxrt595/demo_apps/hello_world/iar" project_relative_path="MIMXRT595S/iar" type="linker" toolchain="iar">
+ <files mask="MIMXRT595Sxxxx_cm33_ram.icf"/>
+ <files mask="MIMXRT595Sxxxx_cm33_flash.icf"/>
+ </source>
+ <source path="boards/evkmimxrt595/demo_apps/hello_world/mdk" project_relative_path="MIMXRT595S/arm" type="linker" toolchain="mdk">
+ <files mask="MIMXRT595Sxxxx_cm33_ram.scf"/>
+ <files mask="MIMXRT595Sxxxx_cm33_flash.scf"/>
+ </source>
+ <source path="boards/evkmimxrt595/demo_apps/hello_world/armgcc" project_relative_path="MIMXRT595S/gcc" type="linker" toolchain="armgcc">
+ <files mask="MIMXRT595Sxxxx_cm33_ram.ld"/>
+ <files mask="MIMXRT595Sxxxx_cm33_flash.ld"/>
+ </source>
+ <source path="boards/evkmimxrt595/demo_apps/hello_world/mdk" project_relative_path="generator/templates/mdk/app_evkmimxrt595" type="configuration" toolchain="mdk">
+ <files mask="flashdebug.ini"/>
+ </source>
+ </example>
+</ksdk:examples>
diff --git a/minimal-examples/embedded/rt595/hello_world/libwebsockets b/minimal-examples/embedded/rt595/hello_world/libwebsockets
new file mode 120000
index 000000000..c866b8687
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/libwebsockets
@@ -0,0 +1 @@
+../../../..
\ No newline at end of file
diff --git a/minimal-examples/embedded/rt595/hello_world/project/.settings/language.settings.xml b/minimal-examples/embedded/rt595/hello_world/project/.settings/language.settings.xml
new file mode 100644
index 000000000..826f637fc
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+ <configuration id="com.crt.advproject.config.exe.debug.1881597443" name="Debug">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="com.crt.advproject.GCCBuildCommandParser" keep-relative-paths="false" name="MCU GCC Build Output Parser" parameter="(arm-none-eabi-gcc)|(arm-none-eabi-[gc]\+\+)|(gcc)|([gc]\+\+)|(clang)" prefer-non-shared="true"/>
+ <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="153932990861307738" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ </extension>
+ </configuration>
+ <configuration id="com.crt.advproject.config.exe.release.930801483" name="Release">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider copy-of="extension" id="com.crt.advproject.GCCBuildCommandParser"/>
+ <provider class="com.crt.advproject.specs.MCUGCCBuiltinSpecsDetector" console="false" env-hash="195095928804160250" id="com.crt.advproject.GCCBuildSpecCompilerParser" keep-relative-paths="false" name="MCU GCC Built-in Compiler Parser" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ </extension>
+ </configuration>
+</project>
\ No newline at end of file
diff --git a/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_armcc.h b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_armcc.h
new file mode 100644
index 000000000..59f173ac7
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_armcc.h
@@ -0,0 +1,894 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.1.0
+ * @date 08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __ARM_FEATURE_DSP 1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __memory_changed()
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_armclang.h b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_armclang.h
new file mode 100644
index 000000000..e917f357a
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_armclang.h
@@ -0,0 +1,1444 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.2.0
+ * @date 08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define __SADD8 __builtin_arm_sadd8
+#define __QADD8 __builtin_arm_qadd8
+#define __SHADD8 __builtin_arm_shadd8
+#define __UADD8 __builtin_arm_uadd8
+#define __UQADD8 __builtin_arm_uqadd8
+#define __UHADD8 __builtin_arm_uhadd8
+#define __SSUB8 __builtin_arm_ssub8
+#define __QSUB8 __builtin_arm_qsub8
+#define __SHSUB8 __builtin_arm_shsub8
+#define __USUB8 __builtin_arm_usub8
+#define __UQSUB8 __builtin_arm_uqsub8
+#define __UHSUB8 __builtin_arm_uhsub8
+#define __SADD16 __builtin_arm_sadd16
+#define __QADD16 __builtin_arm_qadd16
+#define __SHADD16 __builtin_arm_shadd16
+#define __UADD16 __builtin_arm_uadd16
+#define __UQADD16 __builtin_arm_uqadd16
+#define __UHADD16 __builtin_arm_uhadd16
+#define __SSUB16 __builtin_arm_ssub16
+#define __QSUB16 __builtin_arm_qsub16
+#define __SHSUB16 __builtin_arm_shsub16
+#define __USUB16 __builtin_arm_usub16
+#define __UQSUB16 __builtin_arm_uqsub16
+#define __UHSUB16 __builtin_arm_uhsub16
+#define __SASX __builtin_arm_sasx
+#define __QASX __builtin_arm_qasx
+#define __SHASX __builtin_arm_shasx
+#define __UASX __builtin_arm_uasx
+#define __UQASX __builtin_arm_uqasx
+#define __UHASX __builtin_arm_uhasx
+#define __SSAX __builtin_arm_ssax
+#define __QSAX __builtin_arm_qsax
+#define __SHSAX __builtin_arm_shsax
+#define __USAX __builtin_arm_usax
+#define __UQSAX __builtin_arm_uqsax
+#define __UHSAX __builtin_arm_uhsax
+#define __USAD8 __builtin_arm_usad8
+#define __USADA8 __builtin_arm_usada8
+#define __SSAT16 __builtin_arm_ssat16
+#define __USAT16 __builtin_arm_usat16
+#define __UXTB16 __builtin_arm_uxtb16
+#define __UXTAB16 __builtin_arm_uxtab16
+#define __SXTB16 __builtin_arm_sxtb16
+#define __SXTAB16 __builtin_arm_sxtab16
+#define __SMUAD __builtin_arm_smuad
+#define __SMUADX __builtin_arm_smuadx
+#define __SMLAD __builtin_arm_smlad
+#define __SMLADX __builtin_arm_smladx
+#define __SMLALD __builtin_arm_smlald
+#define __SMLALDX __builtin_arm_smlaldx
+#define __SMUSD __builtin_arm_smusd
+#define __SMUSDX __builtin_arm_smusdx
+#define __SMLSD __builtin_arm_smlsd
+#define __SMLSDX __builtin_arm_smlsdx
+#define __SMLSLD __builtin_arm_smlsld
+#define __SMLSLDX __builtin_arm_smlsldx
+#define __SEL __builtin_arm_sel
+#define __QADD __builtin_arm_qadd
+#define __QSUB __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_armclang_ltm.h b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_armclang_ltm.h
new file mode 100644
index 000000000..feec32405
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_armclang_ltm.h
@@ -0,0 +1,1891 @@
+/**************************************************************************//**
+ * @file cmsis_armclang_ltm.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V1.2.0
+ * @date 08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_compiler.h b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_compiler.h
new file mode 100644
index 000000000..adbf296f1
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_compiler.h
@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.1.0
+ * @date 09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+ #include "cmsis_armclang_ltm.h"
+
+ /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include <cmsis_ccs.h>
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #define __RESTRICT __restrict
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_gcc.h b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_gcc.h
new file mode 100644
index 000000000..3ddcc58b6
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_gcc.h
@@ -0,0 +1,2168 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.2.0
+ * @date 08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+ \brief Initializes data and bss sections
+ \details This default implementations initialized all data and additional bss
+ sections relying on .copy.table and .zero.table specified properly
+ in the used linker script.
+
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+ extern void _start(void) __NO_RETURN;
+
+ typedef struct {
+ uint32_t const* src;
+ uint32_t* dest;
+ uint32_t wlen;
+ } __copy_table_t;
+
+ typedef struct {
+ uint32_t* dest;
+ uint32_t wlen;
+ } __zero_table_t;
+
+ extern const __copy_table_t __copy_table_start__;
+ extern const __copy_table_t __copy_table_end__;
+ extern const __zero_table_t __zero_table_start__;
+ extern const __zero_table_t __zero_table_end__;
+
+ for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+ for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ pTable->dest[i] = pTable->src[i];
+ }
+ }
+
+ for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+ for(uint32_t i=0u; i<pTable->wlen; ++i) {
+ pTable->dest[i] = 0u;
+ }
+ }
+
+ _start();
+}
+
+#define __PROGRAM_START __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_iccarm.h b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_iccarm.h
new file mode 100644
index 000000000..12d68fd9a
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_iccarm.h
@@ -0,0 +1,964 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.1.0
+ * @date 08. May 2019
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #if __ICCARM_V8
+ #define __RESTRICT __restrict
+ #else
+ /* Needs IAR language extensions */
+ #define __RESTRICT restrict
+ #endif
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include <intrinsics.h>
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_version.h b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_version.h
new file mode 100644
index 000000000..f2e274662
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.3
+ * @date 24. June 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/minimal-examples/embedded/rt595/hello_world/project/CMSIS/core_cm33.h b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/core_cm33.h
new file mode 100644
index 000000000..7fed59a88
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/core_cm33.h
@@ -0,0 +1,2910 @@
+/**************************************************************************//**
+ * @file core_cm33.h
+ * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version V5.1.0
+ * @date 12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M33
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (33U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined (__TARGET_FPU_VFP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined (__ARM_FP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined (__ARMVFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined (__TI_VFP_SUPPORT__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined (__FPU_VFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM33_REV
+ #define __CM33_REV 0x0000U
+ #warning "__CM33_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/CMSIS/mpu_armv8.h b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/mpu_armv8.h
new file mode 100644
index 000000000..0041d4dc6
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/mpu_armv8.h
@@ -0,0 +1,346 @@
+/******************************************************************************
+ * @file mpu_armv8.h
+ * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version V5.1.0
+ * @date 08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+ (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable */
+#define ARM_MPU_SH_NON (0U)
+
+/** \brief Normal memory outer shareable */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+ ((BASE & MPU_RBAR_BASE_Msk) | \
+ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+ ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; /*!< Region Base Address Register value */
+ uint32_t RLAR; /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+ const uint8_t reg = idx / 4U;
+ const uint32_t pos = ((idx % 4U) * 8U);
+ const uint32_t mask = 0xFFU << pos;
+
+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+ return; // invalid index
+ }
+
+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+ mpu->RNR = rnr;
+ mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ mpu->RNR = rnr;
+ mpu->RBAR = rbar;
+ mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ if (cnt == 1U) {
+ mpu->RNR = rnr;
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+ } else {
+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+
+ mpu->RNR = rnrBase;
+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+ table += c;
+ cnt -= c;
+ rnrOffset = 0U;
+ rnrBase += MPU_TYPE_RALIASES;
+ mpu->RNR = rnrBase;
+ }
+
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/minimal-examples/embedded/rt595/hello_world/project/CMSIS/tz_context.h b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/tz_context.h
new file mode 100644
index 000000000..0d09749f3
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/CMSIS/tz_context.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file tz_context.h
+ * @brief Context Management for Armv8-M TrustZone
+ * @version V1.0.1
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+
+#include <stdint.h>
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in] module identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0 no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif // TZ_CONTEXT_H
diff --git a/minimal-examples/embedded/rt595/hello_world/project/Debug/MIMXRT595S.xml b/minimal-examples/embedded/rt595/hello_world/project/Debug/MIMXRT595S.xml
new file mode 100644
index 000000000..f64795c61
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/Debug/MIMXRT595S.xml
@@ -0,0 +1,5 @@
+<directory>
+ <chips chipVendor='NXP' >
+ <chip name='MIMXRT595S' xml_file='MIMXRT595S_part.xml' />
+ </chips>
+</directory>
diff --git a/minimal-examples/embedded/rt595/hello_world/project/Debug/MIMXRT595S_part.xml b/minimal-examples/embedded/rt595/hello_world/project/Debug/MIMXRT595S_part.xml
new file mode 100644
index 000000000..1858f06fc
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/Debug/MIMXRT595S_part.xml
@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<infoList vendor="NXP">
<info chip="MIMXRT595S" name="MIMXRT595S">
<chip>
<name>MIMXRT595S</name>
<family>MIMXRT500</family>
<vendor>NXP</vendor>
<memory can_program="true" id="Flash" is_ro="true" size="0" type="Flash"/>
<memory id="RAM" size="5120" type="RAM"/>
<memoryInstance derived_from="Flash" driver="MIMXRT500_SFDP_MXIC_OSPI.cfx" id="QSPI_FLASH" location="0x8000000" size="0x800000"/>
<memoryInstance derived_from="RAM" id="SRAM" location="0x80000" size="0x280000"/>
<memoryInstance derived_from="RAM" id="USB_RAM" location="0x40140000" size="0x4000"/>
</chip>
<processor>
<name gcc_name="cortex-m33">Cortex-M33</name>
<family>Cortex-M</family>
</processor>
</info>
</infoList>
diff --git a/minimal-examples/embedded/rt595/hello_world/project/Debug/crt_infolist.dtd b/minimal-examples/embedded/rt595/hello_world/project/Debug/crt_infolist.dtd
new file mode 100644
index 000000000..396f96230
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/Debug/crt_infolist.dtd
@@ -0,0 +1,279 @@
+<!-- DTD file for infoList/info blocks. These define boards, chips,
+ and RTOSes/app-structures. Note that the files themselves may
+ use many includes to build up the information, but only one
+ DTD is used for all of it. -->
+<!ELEMENT infoList (info*)><!ATTLIST infoList
+ vendor CDATA #IMPLIED>
+ <!-- An info is defined as a container for a whole debuggable
+ target. This can be a board+chip, chip only, or one of those
+ with an rtos or app structure. The info has a name, which
+ is the name the user will use to select it when running
+ tools (e.g. stub, targ, etc); normally, this is a compacted
+ form of the chip name or board name (e.g. LPC2124, LMEV811,
+ etc.) The chip name must be specified and uses the standard
+ naming convention established by CRT. The proc is optional
+ and is the processor family (e.g. ARM7 or Cortex-M). The
+ match_ID is a number that has a local meaning. It is used
+ to auto-detect chips and boards when a register can be
+ looked up based on some knowledge (e.g. vendor, family of
+ chips, etc). match_ID may be a comma-separated list where
+ a chip may have multiple IDs -->
+ <!ELEMENT info (chip?,link*,processor?,emulator?)> <!ATTLIST info
+ name ID #REQUIRED
+ chip CDATA #REQUIRED
+ proc CDATA #IMPLIED
+ stub CDATA #IMPLIED
+ match_ID CDATA #IMPLIED>
+ <!-- Chip defines the details of the chip itself, including
+ memory, reset rules, vendor information, peripheral
+ information, and programming for flash. The determined
+ attribute is not used in the file, but is used when this
+ data is emitted by a tool live. -->
+ <!ELEMENT chip (vendor?|name?|reset?|clock?|memory*|
+ memoryInstance*|prog_flash*|peripheralInstance*)> <!ATTLIST chip
+ determined (detected|specified|installation) #IMPLIED>
+ <!-- Vendor provides the vendor name for the chip. This is the
+ full name and not the 3 letter short name. -->
+ <!ELEMENT vendor (#PCDATA)>
+ <!-- Name provides a more accurate version of the chip name
+ for display to a user. Version is the internal version
+ number if known. -->
+ <!ELEMENT name (#PCDATA)> <!ATTLIST name
+ ver NMTOKENS #IMPLIED>
+ <!-- Family is the chip family this belongs to. This usually
+ means "x" used for the last few digits/characters of the
+ name. How broad a family is depends on the vendor. So,
+ "2xxx" may be used for a big family in some cases and
+ "21xx" may be for medium sized family, and "213x" may be
+ used for a narrow family. The notion of family is usually
+ based on mostly shared peripherals and style (but not
+ size) of memory. -->
+ <!ELEMENT family (#PCDATA)>
+ <!-- Reset provides information on what happens when
+ the user requests a reset of the target (including
+ after a full load of a target app). This includes
+ board level reset, system reset (peripherals), and
+ core/cpu reset. Fake means that the tool will
+ write the correct values into registers. Real
+ means that the device will truly reset itself (within
+ any limits of debuggability. -->
+ <!ELEMENT reset EMPTY> <!ATTLIST reset
+ board (none|real|fake) "none"
+ sys (none|real|fake) "none"
+ core (none|real|fake) "fake">
+ <!-- Clock provides information on the chip's clocking
+ mechanism, including external osc/crystal and
+ PLL mechanism. The freq attr is not normally
+ provided in the file form (but may be pushed down
+ from a board definition), and so is used when a
+ tool provides this information. The freqency is
+ expressed in MHz and may have a "." in it as well
+ as end with MHz. Is_accurate is true when the
+ clock speed can be accurately determined; if not,
+ it must come from the board definition or the user
+ if needed for flash. Changeable indicates if the
+ clock speed can be changed dynamically, such as
+ programming a PLL -->
+ <!ELEMENT clock EMPTY> <!ATTLIST clock
+ freq NMTOKENS #IMPLIED
+ is_accurate (true|false) #IMPLIED
+ changeable (true|false) #IMPLIED>
+ <!-- Memory is used to define all memory types on the chip.
+ This includes ROM, Flash, RAM, external memory
+ (if known or knowable), and peripheral memory.
+ Note that the file may contain a subset of information.
+ The output from a tool will include all dynamic
+ information (determined at connect time). The
+ memory is defined with type, default size, and
+ access rules. The instances of such memory is then
+ derived from the template. This definition and
+ instance model makes it easier to define common
+ memory types, and then have instances per chip.
+ The instances provide the location and an optional
+ size override. Note that programmable Flash's
+ programming information is defined using the
+ prog_flash element. -->
+ <!ELEMENT memory (#PCDATA)> <!ATTLIST memory
+ id ID #REQUIRED
+ type (Unknown|ROM|Flash|EEPROM|ExtFlash|
+ RAM|ExtRAM|Peripheral|ExtPeripheral)
+ #REQUIRED
+ size NMTOKEN #IMPLIED
+ is_ro (true|false) #IMPLIED
+ is_wo (true|false) #IMPLIED
+ is_volatile (true|false) #IMPLIED
+ can_program (true|false) #IMPLIED>
+ <!-- MemoryInstance is an instantiation of a memory
+ type previously defined. It provides location,
+ an optional size override (required if the
+ size is not provided by the memory definition).
+ The enable indicates a test for the memory being
+ enabled (an expression from memory reads). -->
+ <!ELEMENT memoryInstance EMPTY> <!ATTLIST memoryInstance
+ id ID #REQUIRED
+ derived_from IDREF #REQUIRED
+ location NMTOKENS #REQUIRED
+ size NMTOKEN #IMPLIED
+ enable CDATA #IMPLIED>
+ <!-- Prog_flash is used to define the programming
+ rules for flash which can be programmed by the
+ tools. The flash must also be defined via the
+ memory and memoryInstance elements. The location
+ must be within a memoryInstance. For flashes
+ with variable sized blocks (sectors), there will
+ be more than one prog_flash element. For example,
+ if there are 8 2K blocks and then 2 32K blocks,
+ the 1st prog_flash will have a blocksz of 2K,
+ a size of 16K, and a location at the memoryInstance
+ start. The 2nd prog_flash will have a blocksz of 32K,
+ a size of 64K, and a location at 16K beyond the
+ memoryInstance start. The prog_flash elements must
+ be in address order.
+ The locked attr is true if the area is not writable
+ by programming. This is for pre-locked rather than
+ detectable dynamically locked.
+ The rules for self_erase, readwhileprog, and
+ progwithcode are not normally in the file, since
+ this information is understood by the flash algo
+ code (which is code). The algoName attr is an optional
+ algorithm name for chip families and boards with
+ more than one flash type. The maxPrgBuff attr is
+ optional and only used when RAM is needed for the
+ flash programming. It gives a reduced RAM buff size if
+ this device has a smaller max copy size than normal. -->
+ <!ELEMENT prog_flash (#PCDATA)> <!ATTLIST prog_flash
+ location NMTOKENS #REQUIRED
+ size NMTOKEN #REQUIRED
+ blocksz NMTOKEN #REQUIRED
+ wordsz NMTOKEN #REQUIRED
+ locked (true|false) #IMPLIED
+ self_erase (true|false) #IMPLIED
+ readwhileprog (true|false) #IMPLIED
+ progwithcode (true|false) #IMPLIED
+ algoName NMTOKEN #IMPLIED
+ maxPrgBuff NMTOKEN #IMPLIED>
+ <!-- PeripheralInstance defines the instantiation of
+ peripherals defined in a separate file (see link
+ element). Instances define the location and what
+ the instance is derived from. The tool output form
+ may also include enables for cases where the
+ peripheral can be validated as enabled or disabled
+ on the chip using a register; this is the same form
+ as peripheral enable in crt_peripheral_defs.dtd.
+ The determined attribute is not normally set in a file,
+ but is used for output. It indicates where the
+ peripheralInstance came from (what file, if any) and
+ if a static conclusion (vs. determined after
+ a connect). -->
+ <!ELEMENT peripheralInstance EMPTY> <!ATTLIST peripheralInstance
+ id ID #REQUIRED
+ derived_from IDREF #REQUIRED
+ location CDATA #REQUIRED
+ enable CDATA #IMPLIED
+ determined (defFile|infoFile|Dynamic) "infoFile">
+
+ <!-- The link element is used to point to a peripheral definition
+ file (or a set of them). It contains a file reference,
+ which may be relative to this file or a full URI. The
+ type reference may currently only be "simple". The show
+ reference may currently only be "embed". -->
+ <!ELEMENT link EMPTY> <!ATTLIST link
+ href CDATA #REQUIRED
+ type (simple) "simple"
+ show (embed) "embed">
+ <!-- The processor element is an output only element. That is,
+ it is not in a file, but emitted by tools. The determined
+ attribute indicates how the tool knows details about
+ the processor (such as version). -->
+ <!ELEMENT processor (name,family,regFormat*)> <!ATTLIST processor
+ determined (detected|specified|installation) #IMPLIED>
+ <!-- Name is the processors specific name (within a family)
+ and attributes define extra information of known. The
+ meaning of revision and ID is specific to each processor.
+ But, ARM processors use the r1p1 style format for rev. -->
+ <!ELEMENT name (#PCDATA)> <!ATTLIST name
+ rev NMTOKENS #IMPLIED
+ ID CDATA #IMPLIED
+ gcc_name CDATA #IMPLIED>
+ <!-- Family defines the processor family that the processor
+ is a member of. -->
+ <!ELEMENT family (#PCDATA)>
+ <!-- regFormat is used for processor specific registers that use
+ an unsual format. If not specified here, it is assumed that
+ the format will be hex and 32-bits. This allows for regs with
+ their own enumeration as well as bit-packed, such as flags.
+ Note that id is the name of the register when accessing
+ as a register (if missing, then cannot be written through
+ this interface), and name is the name it will show as when
+ formatted. Special is a marker for special registers or display
+ lines, such as PSR, PSR as text (bits expanded), Fault info,
+ and Cycle counter. -->
+ <!ELEMENT regFormat (field)> <!ATTLIST regFormat
+ id CDATA #IMPLIED
+ name CDATA #IMPLIED
+ gdb_name CDATA #IMPLIED
+ special (PSR|PSR_TEXT|FAULT|FAULT_TEXT|CYCLE) #IMPLIED
+ description CDATA #IMPLIED>
+ <!-- fieldFormat is used to give the bit breakout of the
+ register. If type is toggle, then it has two value
+ states. If the type is enum, then it is only given
+ as an enum. If the type is mixed, then it is given as
+ a value and an enum. If toggle, then on and off are
+ defined with the strings that represent them. Offset
+ is a bit in [] or a range in []. Optionally, enumList is
+ given as a comma separated list of enum constants, if
+ enum or mixed. -->
+ <!ELEMENT fieldFormat EMPTY> <!ATTLIST fieldFormat
+ id CDATA #IMPLIED
+ type (toggle|enum|mixed|value) #IMPLIED
+ offset CDATA #REQUIRED
+ on CDATA #IMPLIED
+ off CDATA #IMPLIED
+ enumList CDATA #IMPLIED
+ description CDATA #IMPLIED>
+
+ <!-- The emulator element is an output only element. That is,
+ it is not in a file, but emitted by tools. The attribute
+ indicates what "wire type" it uses (including simulator
+ or software connection). The rest of the details are in
+ sub-elements. -->
+ <!ELEMENT emulator (vendor,name,description,instance,speed)><!ATTLIST emulator
+ type (SWD|JTAG|Monitor|Simulator|Agent) #IMPLIED>
+ <!-- vendor may be inaccurate if more than one emulator
+ uses the same protocol, for example. The vendor name
+ may reflect on the software driver and not the emulator
+ probe vendor. It may be "Unknown" if not determined. -->
+ <!ELEMENT vendor (#PCDATA)>
+ <!-- name is normally the name of the software package that
+ supports the emulator. It may be a fully descriptive
+ name, rather than a trade name. -->
+ <!ELEMENT name (#PCDATA)>
+ <!-- description is normally info on the target if known, else
+ not provided. For example, name of emulator or board. -->
+ <!ELEMENT description (#PCDATA)>
+ <!-- instance reflects the choice from a list, if more
+ than one emulator is available. For USB emulators,
+ it will give the selected one and its USB name. A
+ TCP/IP one would give the port and hostname. -->
+ <!ELEMENT instance (#PCDATA)><!ATTLIST instance
+ index CDATA #IMPLIED>
+ <!-- Speed provides the current wire speed (if meaningful)
+ for the emulator. It also indicates the fastest and
+ slowest speeds possible, all in KHz. Note that speed
+ may be a bit misleading if the emulator driver uses
+ wire delays to get speeds between two wire rates. Run
+ speed is used when the target memory can be accessed
+ while the target runs (it often has to be slower).
+ Determined indicates how the speed was selected.-->
+ <!ELEMENT speed (#PCDATA)><!ATTLIST speed
+ fastestKHz CDATA #REQUIRED
+ slowestKHz CDATA #REQUIRED
+ step CDATA #IMPLIED
+ speed CDATA #REQUIRED
+ delay NMTOKEN #IMPLIED
+ run_speed CDATA #IMPLIED
+ run_delay NMTOKEN #IMPLIED
+ run_speedKHz NMTOKEN #IMPLIED
+ determined (test|setting|stored) "test">
+
+
diff --git a/minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug.ld b/minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug.ld
new file mode 100644
index 000000000..8c90f8afa
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug.ld
@@ -0,0 +1,233 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2021
+ * Generated linker script file for MIMXRT595S
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.4.1 [Build 6260] [2021-09-15] on Oct 24, 2021, 10:02:43 AM
+ */
+
+INCLUDE "evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug_library.ld"
+INCLUDE "evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug_memory.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+ /* Image Vector Table and Boot Data for booting from external flash */
+ .boot_hdr : ALIGN(4)
+ {
+ FILL(0x00)
+ __boot_hdr_start__ = ABSOLUTE(.) ;
+ . = 0x400 ;
+ __flash_conf_hdr_start__ = ABSOLUTE(.) ;
+ KEEP(*(.flash_conf))
+ __flash_conf_hdr_end__ = ABSOLUTE(.) ;
+ . = 0x1000 ;
+ __boot_hdr_end__ = ABSOLUTE(.) ;
+ } >QSPI_FLASH
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+ *(.after_vectors*)
+
+ } > QSPI_FLASH
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+ } > QSPI_FLASH
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > QSPI_FLASH
+
+ .ARM.exidx : ALIGN(4)
+ {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > QSPI_FLASH
+
+ _etext = .;
+
+
+ /* USB_RAM */
+ .m_usb_data (NOLOAD) :
+ {
+ *(m_usb_global)
+ } > USB_RAM AT> USB_RAM
+ /* DATA section for USB_RAM */
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ PROVIDE(__start_data_USB_RAM = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$USB_RAM)
+ *(.data.$RAM2)
+ *(.data.$USB_RAM)
+ *(.data.$RAM2.*)
+ *(.data.$USB_RAM.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ PROVIDE(__end_data_USB_RAM = .) ;
+ } > USB_RAM AT>QSPI_FLASH
+
+ /* MAIN DATA SECTION */
+ .uninit_RESERVED (NOLOAD) : ALIGN(4)
+ {
+ _start_uninit_RESERVED = .;
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > SRAM AT> SRAM
+
+ /* Main DATA section (SRAM) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ PROVIDE(__start_data_RAM = .) ;
+ PROVIDE(__start_data_SRAM = .) ;
+ *(vtable)
+ *(.ramfunc*)
+ KEEP(*(CodeQuickAccess))
+ KEEP(*(DataQuickAccess))
+ *(RamFunction)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ PROVIDE(__end_data_RAM = .) ;
+ PROVIDE(__end_data_SRAM = .) ;
+ } > SRAM AT>QSPI_FLASH
+
+ /* BSS section for USB_RAM */
+ .bss_RAM2 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM2 = .) ;
+ PROVIDE(__start_bss_USB_RAM = .) ;
+ *(.bss.$RAM2)
+ *(.bss.$USB_RAM)
+ *(.bss.$RAM2.*)
+ *(.bss.$USB_RAM.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM2 = .) ;
+ PROVIDE(__end_bss_USB_RAM = .) ;
+ } > USB_RAM AT> USB_RAM
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ PROVIDE(__start_bss_RAM = .) ;
+ PROVIDE(__start_bss_SRAM = .) ;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(__end_bss_RAM = .) ;
+ PROVIDE(__end_bss_SRAM = .) ;
+ PROVIDE(end = .);
+ } > SRAM AT> SRAM
+
+ /* NOINIT section for USB_RAM */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_noinit_RAM2 = .) ;
+ PROVIDE(__start_noinit_USB_RAM = .) ;
+ *(.noinit.$RAM2)
+ *(.noinit.$USB_RAM)
+ *(.noinit.$RAM2.*)
+ *(.noinit.$USB_RAM.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_noinit_RAM2 = .) ;
+ PROVIDE(__end_noinit_USB_RAM = .) ;
+ } > USB_RAM AT> USB_RAM
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ PROVIDE(__start_noinit_RAM = .) ;
+ PROVIDE(__start_noinit_SRAM = .) ;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ PROVIDE(__end_noinit_RAM = .) ;
+ PROVIDE(__end_noinit_SRAM = .) ;
+ } > SRAM AT> SRAM
+
+ /* Reserve and place Heap within memory map */
+ _HeapSize = 0x20000;
+ .heap : ALIGN(4)
+ {
+ _pvHeapStart = .;
+ . += _HeapSize;
+ . = ALIGN(4);
+ _pvHeapLimit = .;
+ } > SRAM
+
+ _StackSize = 0x1000;
+ /* Reserve space in memory for Stack */
+ .heap2stackfill :
+ {
+ . += _StackSize;
+ } > SRAM
+ /* Locate actual Stack in memory map */
+ .stack ORIGIN(SRAM) + LENGTH(SRAM) - _StackSize - 0: ALIGN(4)
+ {
+ _vStackBase = .;
+ . = ALIGN(4);
+ _vStackTop = . + _StackSize;
+ } > SRAM
+
+ /* Provide basic symbols giving location and size of main text
+ * block, including initial values of RW data sections. Note that
+ * these will need extending to give a complete picture with
+ * complex images (e.g multiple Flash banks).
+ */
+ _image_start = LOADADDR(.text);
+ _image_end = LOADADDR(.data) + SIZEOF(.data);
+ _image_size = _image_end - _image_start;
+
+ /* Provide symbols for MIMXRT500 parts for startup code to use
+ * to set image to be plain load image or XIP.
+ * Config : Plain load image = false
+ */
+ __imghdr_loadaddress = LOADADDR(.text);
+ __imghdr_imagetype = 0;
+}
\ No newline at end of file
diff --git a/minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug_library.ld b/minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug_library.ld
new file mode 100644
index 000000000..9cb468e9a
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug_library.ld
@@ -0,0 +1,17 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2021
+ * Generated linker script file for MIMXRT595S
+ * Created from library.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.4.1 [Build 6260] [2021-09-15] on Oct 24, 2021, 10:02:43 AM
+ */
+
+GROUP (
+ "libcr_nohost_nf.a"
+ "libcr_c.a"
+ "libcr_eabihelpers.a"
+ "libgcc.a"
+)
diff --git a/minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug_memory.ld b/minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug_memory.ld
new file mode 100644
index 000000000..555686b36
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug_memory.ld
@@ -0,0 +1,32 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2021
+ * Generated linker script file for MIMXRT595S
+ * Created from memory.ldt by FMCreateLinkMemory
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.4.1 [Build 6260] [2021-09-15] on Oct 24, 2021, 10:02:43 AM
+ */
+
+MEMORY
+{
+ /* Define each memory region */
+ QSPI_FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 0x800000 /* 8M bytes (alias Flash) */
+ SRAM (rwx) : ORIGIN = 0x80000, LENGTH = 0x280000 /* 2560K bytes (alias RAM) */
+ USB_RAM (rwx) : ORIGIN = 0x40140000, LENGTH = 0x4000 /* 16K bytes (alias RAM2) */
+}
+
+ /* Define a symbol for the top of each memory region */
+ __base_QSPI_FLASH = 0x8000000 ; /* QSPI_FLASH */
+ __base_Flash = 0x8000000 ; /* Flash */
+ __top_QSPI_FLASH = 0x8000000 + 0x800000 ; /* 8M bytes */
+ __top_Flash = 0x8000000 + 0x800000 ; /* 8M bytes */
+ __base_SRAM = 0x80000 ; /* SRAM */
+ __base_RAM = 0x80000 ; /* RAM */
+ __top_SRAM = 0x80000 + 0x280000 ; /* 2560K bytes */
+ __top_RAM = 0x80000 + 0x280000 ; /* 2560K bytes */
+ __base_USB_RAM = 0x40140000 ; /* USB_RAM */
+ __base_RAM2 = 0x40140000 ; /* RAM2 */
+ __top_USB_RAM = 0x40140000 + 0x4000 ; /* 16K bytes */
+ __top_RAM2 = 0x40140000 + 0x4000 ; /* 16K bytes */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_LinkServer_Debug.swd b/minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_LinkServer_Debug.swd
new file mode 100644
index 000000000..9388f9386
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_LinkServer_Debug.swd
@@ -0,0 +1,2 @@
+1 Devices Found:
+0. ID: 0x6BA02477 IR Length: 4*
diff --git a/minimal-examples/embedded/rt595/hello_world/project/Debug/makefile b/minimal-examples/embedded/rt595/hello_world/project/Debug/makefile
new file mode 100644
index 000000000..9ac2a3ca8
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/Debug/makefile
@@ -0,0 +1,64 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include utilities/subdir.mk
+-include usb/phy/subdir.mk
+-include usb/device/source/lpcip3511/subdir.mk
+-include usb/device/source/subdir.mk
+-include usb/device/class/cdc/subdir.mk
+-include usb/device/class/subdir.mk
+-include startup/subdir.mk
+-include source/sspc/subdir.mk
+-include source/subdir.mk
+-include flash_config/subdir.mk
+-include drivers/subdir.mk
+-include device/subdir.mk
+-include component/uart/subdir.mk
+-include component/osa/subdir.mk
+-include component/lists/subdir.mk
+-include board/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables
+
+# All Target
+all: evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm.axf
+
+# Tool invocations
+evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm.axf: $(OBJS) $(USER_OBJS)
+ @echo 'Building target: $@'
+ @echo 'Invoking: MCU Linker'
+ arm-none-eabi-gcc -nostdlib -L"/home/agreen/Documents/MCUXpresso_11.4.1_6260/workspace/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm/source" -Xlinker -Map="evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm.map" -Xlinker --gc-sections -Xlinker -print-memory-usage -Xlinker --sort-section=alignment -Xlinker --cref -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -T evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm_Debug.ld -o "evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm.axf" $(OBJS) $(USER_OBJS) $(LIBS)
+ @echo 'Finished building target: $@'
+ @echo ' '
+ $(MAKE) --no-print-directory post-build
+
+# Other Targets
+clean:
+ -$(RM) $(EXECUTABLES)$(OBJS)$(C_DEPS) evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm.axf
+ -@echo ' '
+
+post-build:
+ -@echo 'Performing post-build steps'
+ -arm-none-eabi-size "evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm.axf"; # arm-none-eabi-objcopy -v -O binary "evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm.axf" "evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm.bin" ; # checksum -p MIMXRT595S -d "evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm.bin";
+ -@echo ' '
+
+.PHONY: all clean dependents post-build
+
+-include ../makefile.targets
diff --git a/minimal-examples/embedded/rt595/hello_world/project/board/board.c b/minimal-examples/embedded/rt595/hello_world/project/board/board.c
new file mode 100644
index 000000000..eb13a7951
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/board/board.c
@@ -0,0 +1,622 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_clock.h"
+#include "fsl_flexspi.h"
+#include "fsl_cache.h"
+#include "fsl_power.h"
+#include "clock_config.h"
+#include "board.h"
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_i2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+#if defined BOARD_USE_CODEC
+#include "fsl_i3c.h"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_FLEXSPI_DLL_LOCK_RETRY (10)
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal);
+static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal);
+static status_t flexspi_hyper_ram_reset(FLEXSPI_Type *base);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq;
+
+ /* attach FRG0 clock to FLEXCOMM0 (debug console) */
+ CLOCK_SetFRGClock(BOARD_DEBUG_UART_FRG_CLK);
+ CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+ uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal)
+{
+ flexspi_transfer_t flashXfer;
+ status_t status;
+
+ /* Write data */
+ flashXfer.deviceAddress = regAddr;
+ flashXfer.port = kFLEXSPI_PortA1;
+ flashXfer.cmdType = kFLEXSPI_Write;
+ flashXfer.SeqNumber = 1;
+ flashXfer.seqIndex = 3;
+ flashXfer.data = mrVal;
+ flashXfer.dataSize = 1;
+
+ status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+ return status;
+}
+
+static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal)
+{
+ flexspi_transfer_t flashXfer;
+ status_t status;
+
+ /* Read data */
+ flashXfer.deviceAddress = regAddr;
+ flashXfer.port = kFLEXSPI_PortA1;
+ flashXfer.cmdType = kFLEXSPI_Read;
+ flashXfer.SeqNumber = 1;
+ flashXfer.seqIndex = 2;
+ flashXfer.data = mrVal;
+ flashXfer.dataSize = 2;
+
+ status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+ return status;
+}
+
+static status_t flexspi_hyper_ram_reset(FLEXSPI_Type *base)
+{
+ flexspi_transfer_t flashXfer;
+ status_t status;
+
+ /* Write data */
+ flashXfer.deviceAddress = 0x0U;
+ flashXfer.port = kFLEXSPI_PortA1;
+ flashXfer.cmdType = kFLEXSPI_Command;
+ flashXfer.SeqNumber = 1;
+ flashXfer.seqIndex = 4;
+
+ status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+ if (status == kStatus_Success)
+ {
+ /* for loop of 50000 is about 1ms (@200 MHz CPU) */
+ for (uint32_t i = 2000000U; i > 0; i--)
+ {
+ __NOP();
+ }
+ }
+ return status;
+}
+
+/* Initialize psram. */
+status_t BOARD_InitPsRam(void)
+{
+ flexspi_device_config_t deviceconfig = {
+ .flexspiRootClk = 396000000, /* 396MHZ SPI serial clock, DDR serial clock 198M */
+ .isSck2Enabled = false,
+ .flashSize = 0x2000, /* 64Mb/KByte */
+ .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
+ .CSInterval = 5,
+ .CSHoldTime = 3,
+ .CSSetupTime = 3,
+ .dataValidTime = 1,
+ .columnspace = 0,
+ .enableWordAddress = false,
+ .AWRSeqIndex = 1,
+ .AWRSeqNumber = 1,
+ .ARDSeqIndex = 0,
+ .ARDSeqNumber = 1,
+ .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
+ .AHBWriteWaitInterval = 0,
+ .enableWriteMask = true,
+ };
+
+ uint32_t customLUT[64] = {
+ /* Read Data */
+ [0] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
+ [1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07, kFLEXSPI_Command_READ_DDR,
+ kFLEXSPI_8PAD, 0x04),
+
+ /* Write Data */
+ [4] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
+ [5] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07, kFLEXSPI_Command_WRITE_DDR,
+ kFLEXSPI_8PAD, 0x04),
+
+ /* Read Register */
+ [8] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x40, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
+ [9] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07, kFLEXSPI_Command_READ_DDR,
+ kFLEXSPI_8PAD, 0x04),
+
+ /* Write Register */
+ [12] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xC0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
+ [13] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x08, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD,
+ 0x00),
+
+ /* reset */
+ [16] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xFF, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_8PAD, 0x03),
+
+ };
+
+ uint32_t mr0mr1[1];
+ uint32_t mr4mr8[1];
+ uint32_t mr0Val[1];
+ uint32_t mr4Val[1];
+ uint32_t mr8Val[1];
+ flexspi_config_t config;
+ cache64_config_t cacheCfg;
+ status_t status = kStatus_Success;
+
+ POWER_DisablePD(kPDRUNCFG_APD_FLEXSPI1_SRAM);
+ POWER_DisablePD(kPDRUNCFG_PPD_FLEXSPI1_SRAM);
+ POWER_ApplyPD();
+
+ CLOCK_AttachClk(kAUX0_PLL_to_FLEXSPI1_CLK);
+ CLOCK_SetClkDiv(kCLOCK_DivFlexspi1Clk, 1);
+
+ RESET_PeripheralReset(kFLEXSPI1_RST_SHIFT_RSTn);
+#if (defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Need to explicitly enable FlexSPI1 clock in mpi_loader_extram_loader case.
+ * In that case, FlexSPI driver need to be used before data sections copy. So
+ * global variables are forbidden with FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL=1.
+ */
+ CLOCK_EnableClock(kCLOCK_Flexspi1);
+#endif
+
+ /* As cache depends on FlexSPI power and clock, cache must be initialized after FlexSPI power/clock is set */
+ CACHE64_GetDefaultConfig(&cacheCfg);
+ CACHE64_Init(CACHE64_POLSEL1, &cacheCfg);
+#if BOARD_ENABLE_PSRAM_CACHE
+ CACHE64_EnableWriteBuffer(CACHE64_CTRL1, true);
+ CACHE64_EnableCache(CACHE64_CTRL1);
+#endif
+
+ /* Get FLEXSPI default settings and configure the flexspi. */
+ FLEXSPI_GetDefaultConfig(&config);
+
+ /* Init FLEXSPI. */
+ config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
+ /*Set AHB buffer size for reading data through AHB bus. */
+ config.ahbConfig.enableAHBPrefetch = true;
+ config.ahbConfig.enableAHBBufferable = true;
+ config.ahbConfig.enableAHBCachable = true;
+ config.ahbConfig.enableReadAddressOpt = true;
+ for (uint8_t i = 1; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1; i++)
+ {
+ config.ahbConfig.buffer[i].bufferSize = 0;
+ }
+ /* FlexSPI1 has total 2KB RX buffer.
+ * Set GPU/Display master to use AHB Rx Buffer0.
+ */
+ config.ahbConfig.buffer[0].masterIndex = 11; /* GPU/Display */
+ config.ahbConfig.buffer[0].bufferSize = 1024; /* Allocate 1KB bytes for GPU/Display */
+ config.ahbConfig.buffer[0].enablePrefetch = true;
+ config.ahbConfig.buffer[0].priority = 7; /* Set GPU/Display to highest priority. */
+ /* All other masters use last buffer with 1KB bytes. */
+ config.ahbConfig.buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1].bufferSize = 1024;
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
+ config.enableCombination = true;
+#endif
+ FLEXSPI_Init(BOARD_FLEXSPI_PSRAM, &config);
+
+ /* Configure flash settings according to serial flash feature. */
+ FLEXSPI_SetFlashConfig(BOARD_FLEXSPI_PSRAM, &deviceconfig, kFLEXSPI_PortA1);
+
+ /* Update LUT table. */
+ FLEXSPI_UpdateLUT(BOARD_FLEXSPI_PSRAM, 0, customLUT, ARRAY_SIZE(customLUT));
+
+ /* Do software reset. */
+ FLEXSPI_SoftwareReset(BOARD_FLEXSPI_PSRAM);
+
+ /* Reset hyper ram. */
+ status = flexspi_hyper_ram_reset(BOARD_FLEXSPI_PSRAM);
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ status = flexspi_hyper_ram_get_mcr(BOARD_FLEXSPI_PSRAM, 0x0, mr0mr1);
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ status = flexspi_hyper_ram_get_mcr(BOARD_FLEXSPI_PSRAM, 0x4, mr4mr8);
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ /* Enable RBX, burst length set to 1K. - MR8 */
+ mr8Val[0] = (mr4mr8[0] & 0xFF00U) >> 8U;
+ mr8Val[0] = mr8Val[0] | 0x0F;
+ status = flexspi_hyper_ram_write_mcr(BOARD_FLEXSPI_PSRAM, 0x8, mr8Val);
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ /* Set LC code to 0x04(LC=7, maximum frequency 200M) - MR0. */
+ mr0Val[0] = mr0mr1[0] & 0x00FFU;
+ mr0Val[0] = (mr0Val[0] & ~0x3CU) | (4U << 2U);
+ status = flexspi_hyper_ram_write_mcr(BOARD_FLEXSPI_PSRAM, 0x0, mr0Val);
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ /* Set WLC code to 0x01(WLC=7, maximum frequency 200M) - MR4. */
+ mr4Val[0] = mr4mr8[0] & 0x00FFU;
+ mr4Val[0] = (mr4Val[0] & ~0xE0U) | (1U << 5U);
+ status = flexspi_hyper_ram_write_mcr(BOARD_FLEXSPI_PSRAM, 0x4, mr4Val);
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ return status;
+}
+
+void BOARD_DeinitFlash(FLEXSPI_Type *base)
+{
+ /* Enable FLEXSPI clock again */
+ CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK;
+
+ /* Enable FLEXSPI module */
+ base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+
+ /* Wait until FLEXSPI is not busy */
+ while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
+ {
+ }
+ /* Disable module during the reset procedure */
+ base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
+}
+
+void BOARD_InitFlash(FLEXSPI_Type *base)
+{
+ uint32_t status;
+ uint32_t lastStatus;
+ uint32_t retry;
+
+ /* If serial root clock is >= 100 MHz, DLLEN set to 1, OVRDEN set to 0, then SLVDLYTARGET setting of 0x0 is
+ * recommended. */
+ base->DLLCR[0] = 0x1U;
+
+ /* Enable FLEXSPI module */
+ base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+
+ base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
+ while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
+ {
+ }
+
+ /* Need to wait DLL locked if DLL enabled */
+ if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK))
+ {
+ lastStatus = base->STS2;
+ retry = BOARD_FLEXSPI_DLL_LOCK_RETRY;
+ /* Wait slave delay line locked and slave reference delay line locked. */
+ do
+ {
+ status = base->STS2;
+ if ((status & (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) ==
+ (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK))
+ {
+ /* Locked */
+ retry = 100;
+ break;
+ }
+ else if (status == lastStatus)
+ {
+ /* Same delay cell number in calibration */
+ retry--;
+ }
+ else
+ {
+ retry = BOARD_FLEXSPI_DLL_LOCK_RETRY;
+ lastStatus = status;
+ }
+ } while (retry > 0);
+ /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
+ for (; retry > 0U; retry--)
+ {
+ __NOP();
+ }
+ }
+}
+
+/* BOARD_SetFlexspiClock run in RAM used to configure FlexSPI clock source and divider when XIP. */
+void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint32_t src, uint32_t divider)
+{
+ if (base == FLEXSPI0)
+ {
+ if ((CLKCTL0->FLEXSPI0FCLKSEL != CLKCTL0_FLEXSPI0FCLKSEL_SEL(src)) ||
+ ((CLKCTL0->FLEXSPI0FCLKDIV & CLKCTL0_FLEXSPI0FCLKDIV_DIV_MASK) != (divider - 1)))
+ {
+ /* Always deinit FLEXSPI and init FLEXSPI for the flash to make sure the flash works correctly after the
+ FLEXSPI root clock changed as the default FLEXSPI configuration may does not work for the new root clock
+ frequency. */
+ BOARD_DeinitFlash(base);
+
+ /* Disable clock before changing clock source */
+ CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_MASK;
+ /* Update flexspi clock. */
+ CLKCTL0->FLEXSPI0FCLKSEL = CLKCTL0_FLEXSPI0FCLKSEL_SEL(src);
+ CLKCTL0->FLEXSPI0FCLKDIV |= CLKCTL0_FLEXSPI0FCLKDIV_RESET_MASK; /* Reset the divider counter */
+ CLKCTL0->FLEXSPI0FCLKDIV = CLKCTL0_FLEXSPI0FCLKDIV_DIV(divider - 1);
+ while ((CLKCTL0->FLEXSPI0FCLKDIV) & CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG_MASK)
+ {
+ }
+ /* Enable FLEXSPI clock again */
+ CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK;
+
+ BOARD_InitFlash(base);
+ }
+ }
+ else if (base == FLEXSPI1)
+ {
+ if ((CLKCTL0->FLEXSPI1FCLKSEL != CLKCTL0_FLEXSPI1FCLKSEL_SEL(src)) ||
+ ((CLKCTL0->FLEXSPI1FCLKDIV & CLKCTL0_FLEXSPI1FCLKDIV_DIV_MASK) != (divider - 1)))
+ {
+ /* Always deinit FLEXSPI and init FLEXSPI for the flash to make sure the flash works correctly after the
+ FLEXSPI root clock changed as the default FLEXSPI configuration may does not work for the new root clock
+ frequency. */
+ BOARD_DeinitFlash(base);
+
+ /* Disable clock before changing clock source */
+ CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_MASK;
+ /* Update flexspi clock. */
+ CLKCTL0->FLEXSPI1FCLKSEL = CLKCTL0_FLEXSPI1FCLKSEL_SEL(src);
+ CLKCTL0->FLEXSPI1FCLKDIV |= CLKCTL0_FLEXSPI1FCLKDIV_RESET_MASK; /* Reset the divider counter */
+ CLKCTL0->FLEXSPI1FCLKDIV = CLKCTL0_FLEXSPI1FCLKDIV_DIV(divider - 1);
+ while ((CLKCTL0->FLEXSPI1FCLKDIV) & CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG_MASK)
+ {
+ }
+ /* Enable FLEXSPI clock again */
+ CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK;
+
+ BOARD_InitFlash(base);
+ }
+ }
+ else
+ {
+ return;
+ }
+}
+
+/* This function is used to change FlexSPI clock to a stable source before clock sources(Such as PLL and Main clock)
+ * updating in case XIP(execute code on FLEXSPI memory.) */
+void BOARD_FlexspiClockSafeConfig(void)
+{
+ /* Move FLEXSPI clock source from main clock to FRO192M / 2 to avoid instruction/data fetch issue in XIP when
+ * updating PLL and main clock.
+ */
+ BOARD_SetFlexspiClock(FLEXSPI0, 3U, 2U);
+}
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
+{
+ i2c_master_config_t i2cConfig = {0};
+
+ I2C_MasterGetDefaultConfig(&i2cConfig);
+ I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_I2C_Send(I2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *txBuff,
+ uint8_t txBuffSize)
+{
+ i2c_master_transfer_t masterXfer;
+
+ /* Prepare transfer structure. */
+ masterXfer.slaveAddress = deviceAddress;
+ masterXfer.direction = kI2C_Write;
+ masterXfer.subaddress = subAddress;
+ masterXfer.subaddressSize = subaddressSize;
+ masterXfer.data = txBuff;
+ masterXfer.dataSize = txBuffSize;
+ masterXfer.flags = kI2C_TransferDefaultFlag;
+
+ return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+status_t BOARD_I2C_Receive(I2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *rxBuff,
+ uint8_t rxBuffSize)
+{
+ i2c_master_transfer_t masterXfer;
+
+ /* Prepare transfer structure. */
+ masterXfer.slaveAddress = deviceAddress;
+ masterXfer.subaddress = subAddress;
+ masterXfer.subaddressSize = subaddressSize;
+ masterXfer.data = rxBuff;
+ masterXfer.dataSize = rxBuffSize;
+ masterXfer.direction = kI2C_Read;
+ masterXfer.flags = kI2C_TransferDefaultFlag;
+
+ return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+#endif
+
+#if defined BOARD_USE_CODEC
+void BOARD_I3C_Init(I3C_Type *base, uint32_t clkSrc_Hz)
+{
+ i3c_master_config_t i3cConfig;
+
+ I3C_MasterGetDefaultConfig(&i3cConfig);
+ I3C_MasterInit(base, &i3cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_I3C_Send(I3C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *txBuff,
+ uint8_t txBuffSize)
+{
+ i3c_master_transfer_t masterXfer;
+
+ /* Prepare transfer structure. */
+ masterXfer.slaveAddress = deviceAddress;
+ masterXfer.direction = kI3C_Write;
+ masterXfer.busType = kI3C_TypeI2C;
+ masterXfer.subaddress = subAddress;
+ masterXfer.subaddressSize = subaddressSize;
+ masterXfer.data = txBuff;
+ masterXfer.dataSize = txBuffSize;
+ masterXfer.flags = kI3C_TransferDefaultFlag;
+ masterXfer.busType = kI3C_TypeI2C;
+
+ return I3C_MasterTransferBlocking(base, &masterXfer);
+}
+
+status_t BOARD_I3C_Receive(I3C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *rxBuff,
+ uint8_t rxBuffSize)
+{
+ i3c_master_transfer_t masterXfer;
+
+ /* Prepare transfer structure. */
+ masterXfer.slaveAddress = deviceAddress;
+ masterXfer.subaddress = subAddress;
+ masterXfer.subaddressSize = subaddressSize;
+ masterXfer.data = rxBuff;
+ masterXfer.dataSize = rxBuffSize;
+ masterXfer.direction = kI3C_Read;
+ masterXfer.busType = kI3C_TypeI2C;
+ masterXfer.flags = kI3C_TransferDefaultFlag;
+ masterXfer.busType = kI3C_TypeI2C;
+
+ return I3C_MasterTransferBlocking(base, &masterXfer);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+#if BOARD_I3C_CODEC
+ BOARD_I3C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+#else
+ BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+#endif
+}
+
+status_t BOARD_Codec_I2C_Send(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+#if BOARD_I3C_CODEC
+ return BOARD_I3C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+#else
+ return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+#endif
+ txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+#if BOARD_I3C_CODEC
+ return BOARD_I3C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+#else
+ return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+#endif
+}
+#endif
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_PMIC_I2C_Init(void)
+{
+ BOARD_I2C_Init(BOARD_PMIC_I2C_BASEADDR, BOARD_PMIC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_PMIC_I2C_Send(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+ return BOARD_I2C_Send(BOARD_PMIC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+ txBuffSize);
+}
+
+status_t BOARD_PMIC_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_I2C_Receive(BOARD_PMIC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_MIPIPanelTouch_I2C_Init(void)
+{
+ BOARD_I2C_Init(BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR, BOARD_MIPI_PANEL_TOUCH_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_MIPIPanelTouch_I2C_Send(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+ return BOARD_I2C_Send(BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize,
+ (uint8_t *)txBuff, txBuffSize);
+}
+
+status_t BOARD_MIPIPanelTouch_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_I2C_Receive(BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
+ rxBuffSize);
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+ BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint32_t txBuff)
+{
+ uint8_t data = (uint8_t)txBuff;
+ return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+ return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/board/board.h b/minimal-examples/embedded/rt595/hello_world/project/board/board.h
new file mode 100644
index 000000000..387f4fb86
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/board/board.h
@@ -0,0 +1,281 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_reset.h"
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "EVK-MIMXRT595"
+#define BOARD_I3C_CODEC (1)
+
+/*! @brief The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0
+#define BOARD_DEBUG_UART_INSTANCE 0U
+#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetFlexcommClkFreq(0)
+#define BOARD_DEBUG_UART_FRG_CLK \
+ (&(const clock_frg_clk_config_t){0U, kCLOCK_FrgPllDiv, 255U, 0U}) /*!< Select FRG0 mux as frg_pll */
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRG_to_FLEXCOMM0
+#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler
+#define BOARD_UART_IRQ FLEXCOMM0_IRQn
+
+#if BOARD_I3C_CODEC
+#define BOARD_CODEC_I2C_BASEADDR I3C0
+#define BOARD_CODEC_I2C_INSTANCE 0
+#define BOARD_CODEC_I2C_CLOCK_FREQ CLOCK_GetI3cClkFreq()
+#else
+#define BOARD_CODEC_I2C_BASEADDR I2C4
+#define BOARD_CODEC_I2C_INSTANCE 4
+#define BOARD_CODEC_I2C_CLOCK_FREQ CLOCK_GetFlexcommClkFreq(4)
+#endif
+
+#define BOARD_FLEXSPI_PSRAM FLEXSPI1
+#ifndef BOARD_ENABLE_PSRAM_CACHE
+#define BOARD_ENABLE_PSRAM_CACHE 1
+#endif
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+/* PCA9420 */
+#define BOARD_PMIC_I2C_BASEADDR I2C15
+#define BOARD_PMIC_I2C_CLOCK_FREQ CLOCK_GetFlexcommClkFreq(15)
+
+/* Accelerometer */
+#define BOARD_ACCEL_I2C_BASEADDR I2C4
+#define BOARD_ACCEL_I2C_ADDR 0x1E
+#define BOARD_ACCEL_I2C_CLOCK_FREQ CLOCK_GetFlexcommClkFreq(4)
+
+/* Board led color mapping */
+#define LOGIC_LED_ON 1U
+#define LOGIC_LED_OFF 0U
+
+#ifndef BOARD_LED_RED_GPIO
+#define BOARD_LED_RED_GPIO GPIO
+#endif
+#define BOARD_LED_RED_GPIO_PORT 0U
+#ifndef BOARD_LED_RED_GPIO_PIN
+#define BOARD_LED_RED_GPIO_PIN 14U
+#endif
+
+#ifndef BOARD_LED_GREEN_GPIO
+#define BOARD_LED_GREEN_GPIO GPIO
+#endif
+#define BOARD_LED_GREEN_GPIO_PORT 1U
+#ifndef BOARD_LED_GREEN_GPIO_PIN
+#define BOARD_LED_GREEN_GPIO_PIN 0U
+#endif
+#ifndef BOARD_LED_BLUE_GPIO
+#define BOARD_LED_BLUE_GPIO GPIO
+#endif
+#define BOARD_LED_BLUE_GPIO_PORT 3U
+#ifndef BOARD_LED_BLUE_GPIO_PIN
+#define BOARD_LED_BLUE_GPIO_PIN 17U
+#endif
+
+#ifndef BOARD_FLASH_RESET_GPIO
+#define BOARD_FLASH_RESET_GPIO GPIO
+#endif
+#ifndef BOARD_FLASH_RESET_GPIO_PORT
+#define BOARD_FLASH_RESET_GPIO_PORT 4U
+#endif
+#ifndef BOARD_FLASH_RESET_GPIO_PIN
+#define BOARD_FLASH_RESET_GPIO_PIN 5U
+#endif
+
+#define LED_RED_INIT(output) \
+ GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_RED */
+#define LED_RED_ON() \
+ GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+ 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */
+#define LED_RED_OFF() \
+ GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+ 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */
+#define LED_RED_TOGGLE() \
+ GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
+ 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */
+
+#define LED_GREEN_INIT(output) \
+ GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_GREEN */
+#define LED_GREEN_ON() \
+ GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+ 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */
+#define LED_GREEN_OFF() \
+ GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+ 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */
+#define LED_GREEN_TOGGLE() \
+ GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
+ 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */
+
+#define LED_BLUE_INIT(output) \
+ GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_BLUE */
+#define LED_BLUE_ON() \
+ GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+ 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */
+#define LED_BLUE_OFF() \
+ GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+ 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */
+#define LED_BLUE_TOGGLE() \
+ GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
+ 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */
+
+/* Board SW PIN */
+#ifndef BOARD_SW1_GPIO
+#define BOARD_SW1_GPIO GPIO
+#endif
+#define BOARD_SW1_GPIO_PORT 0U
+#ifndef BOARD_SW1_GPIO_PIN
+#define BOARD_SW1_GPIO_PIN 25U
+#endif
+
+#ifndef BOARD_SW2_GPIO
+#define BOARD_SW2_GPIO GPIO
+#endif
+#define BOARD_SW2_GPIO_PORT 0U
+#ifndef BOARD_SW2_GPIO_PIN
+#define BOARD_SW2_GPIO_PIN 10U
+#endif
+
+/* USB PHY condfiguration */
+#define BOARD_USB_PHY_D_CAL (0x0CU)
+#define BOARD_USB_PHY_TXCAL45DP (0x06U)
+#define BOARD_USB_PHY_TXCAL45DM (0x06U)
+
+#define BOARD_FLASH_SIZE (0x4000000U)
+
+/* SSD1963 (TFT_PROTO_5) panel. */
+/* RST pin. */
+#define BOARD_SSD1963_RST_PORT 5
+#define BOARD_SSD1963_RST_PIN 0
+/* CS pin. */
+#define BOARD_SSD1963_CS_PORT 5
+#define BOARD_SSD1963_CS_PIN 1
+/* D/C pin, also named RS pin. */
+#define BOARD_SSD1963_RS_PORT 4
+#define BOARD_SSD1963_RS_PIN 31
+/* Touch panel. */
+#define BOARD_SSD1963_TOUCH_I2C_BASEADDR I2C4
+#define BOARD_SSD1963_TOUCH_I2C_CLOCK_FREQ CLOCK_GetFlexcommClkFreq(4)
+
+/* MIPI panel. */
+/* RST pin. */
+#define BOARD_MIPI_RST_PORT 3
+#define BOARD_MIPI_RST_PIN 21
+/* POWER pin .*/
+#define BOARD_MIPI_POWER_PORT 3
+#define BOARD_MIPI_POWER_PIN 15
+/* Backlight pin. */
+#define BOARD_MIPI_BL_PORT 0
+#define BOARD_MIPI_BL_PIN 12
+/* TE pin. */
+#define BOARD_MIPI_TE_PORT 3
+#define BOARD_MIPI_TE_PIN 18
+
+/* Touch panel. */
+#define BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR I2C4
+#define BOARD_MIPI_PANEL_TOUCH_I2C_CLOCK_FREQ CLOCK_GetFlexcommClkFreq(4)
+#define BOARD_MIPI_PANEL_TOUCH_RST_PORT 4
+#define BOARD_MIPI_PANEL_TOUCH_RST_PIN 4
+#define BOARD_MIPI_PANEL_TOUCH_INT_PORT 3
+#define BOARD_MIPI_PANEL_TOUCH_INT_PIN 19
+
+#define BOARD_BT_UART_INSTANCE 12
+#define BOARD_BT_UART_BAUDRATE 3000000
+#define BOARD_BT_UART_CLK_FREQ CLOCK_GetFlexcommClkFreq(12U)
+#define BOARD_BT_UART_FRG_CLK \
+ (&(const clock_frg_clk_config_t){12, kCLOCK_FrgMainClk, 255, 12}) /*!< Select FRG0 mux as frg_pll */
+#define BOARD_BT_UART_CLK_ATTACH kFRG_to_FLEXCOMM12
+#define BOARD_BT_UART_RST kFC12_RST_SHIFT_RSTn
+#define BOARD_BT_UART_IRQ FLEXCOMM12_IRQn
+#define BOARD_BT_UART_IRQ_HANDLER FLEXCOMM12_IRQHandler
+#define BOARD_BT_UART_CLKSRC kCLOCK_Flexcomm12
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+status_t BOARD_InitPsRam(void);
+void BOARD_FlexspiClockSafeConfig(void);
+AT_QUICKACCESS_SECTION_CODE(void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint32_t src, uint32_t divider));
+AT_QUICKACCESS_SECTION_CODE(void BOARD_DeinitFlash(FLEXSPI_Type *base));
+AT_QUICKACCESS_SECTION_CODE(void BOARD_InitFlash(FLEXSPI_Type *base));
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
+status_t BOARD_I2C_Send(I2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *txBuff,
+ uint8_t txBuffSize);
+status_t BOARD_I2C_Receive(I2C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *rxBuff,
+ uint8_t rxBuffSize);
+
+void BOARD_PMIC_I2C_Init(void);
+status_t BOARD_PMIC_I2C_Send(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_PMIC_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+
+void BOARD_MIPIPanelTouch_I2C_Init(void);
+status_t BOARD_MIPIPanelTouch_I2C_Send(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_MIPIPanelTouch_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+
+void BOARD_Accel_I2C_Init(void);
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint32_t txBuff);
+status_t BOARD_Accel_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+#if defined BOARD_USE_CODEC
+void BOARD_I3C_Init(I3C_Type *base, uint32_t clkSrc_Hz);
+status_t BOARD_I3C_Send(I3C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *txBuff,
+ uint8_t txBuffSize);
+status_t BOARD_I3C_Receive(I3C_Type *base,
+ uint8_t deviceAddress,
+ uint32_t subAddress,
+ uint8_t subaddressSize,
+ uint8_t *rxBuff,
+ uint8_t rxBuffSize);
+void BOARD_Codec_I2C_Init(void);
+status_t BOARD_Codec_I2C_Send(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_Codec_I2C_Receive(
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/board/clock_config.c b/minimal-examples/embedded/rt595/hello_world/project/board/clock_config.c
new file mode 100644
index 000000000..314c033db
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/board/clock_config.c
@@ -0,0 +1,246 @@
+/*
+ * Copyright 2019-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up all selectors to provide selected clocks.
+ *
+ * 3. Set up all dividers.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: MIMXRT595S
+package_id: MIMXRT595SFFOC
+mcu_data: ksdk2_0
+processor_version: 0.8.1
+board: MIMXRT595-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : BOARD_FlexspiClockSafeConfig
+ * Description : FLEXSPI clock source safe configuration weak function.
+ * Called before clock source(Such as PLL, Main clock) configuration.
+ * Note : Users need override this function to change FLEXSPI clock source to stable source when executing
+ * code on FLEXSPI memory(XIP). If XIP, the function should runs in RAM and move the FLEXSPI clock
+ *source to an stable clock to avoid instruction/data fetch issue during clock updating.
+ *END**************************************************************************/
+__attribute__((weak)) void BOARD_FlexspiClockSafeConfig(void)
+{
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : BOARD_SetFlexspiClock
+ * Description : This function should be overridden if executing code on FLEXSPI memory(XIP).
+ * To Change FLEXSPI clock, should move to run from RAM and then configure FLEXSPI clock source.
+ * After the clock is changed and stable, move back to run on FLEXSPI.
+ * Param base : FLEXSPI peripheral base address.
+ * Param src : FLEXSPI clock source.
+ * Param divider : FLEXSPI clock divider.
+ *END**************************************************************************/
+__attribute__((weak)) void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint32_t src, uint32_t divider)
+{
+ if (FLEXSPI0 == base)
+ {
+ CLKCTL0->FLEXSPI0FCLKSEL = CLKCTL0_FLEXSPI0FCLKSEL_SEL(src);
+ CLKCTL0->FLEXSPI0FCLKDIV |= CLKCTL0_FLEXSPI0FCLKDIV_RESET_MASK; /* Reset the divider counter */
+ CLKCTL0->FLEXSPI0FCLKDIV = CLKCTL0_FLEXSPI0FCLKDIV_DIV(divider - 1);
+ while ((CLKCTL0->FLEXSPI0FCLKDIV) & CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG_MASK)
+ {
+ }
+ }
+ else if (FLEXSPI1 == base)
+ {
+ CLKCTL0->FLEXSPI1FCLKSEL = CLKCTL0_FLEXSPI1FCLKSEL_SEL(src);
+ CLKCTL0->FLEXSPI1FCLKDIV |= CLKCTL0_FLEXSPI1FCLKDIV_RESET_MASK; /* Reset the divider counter */
+ CLKCTL0->FLEXSPI1FCLKDIV = CLKCTL0_FLEXSPI1FCLKDIV_DIV(divider - 1);
+ while ((CLKCTL0->FLEXSPI1FCLKDIV) & CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG_MASK)
+ {
+ }
+ }
+ else
+ {
+ return;
+ }
+}
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: CLKOUT_clock.outFreq, value: 960 kHz}
+- {id: FLEXSPI0_clock.outFreq, value: 198 MHz}
+- {id: LPOSC1M_clock.outFreq, value: 1 MHz}
+- {id: OSTIMER_clock.outFreq, value: 1 MHz}
+- {id: SYSTICK_clock.outFreq, value: 198 MHz}
+- {id: System_clock.outFreq, value: 198 MHz}
+- {id: TRACE_clock.outFreq, value: 198 MHz}
+- {id: USBPHY_clock.outFreq, value: 99 MHz}
+- {id: WAKE_32K_clock.outFreq, value: 976.5625 Hz}
+settings:
+- {id: AUDIOPLL0_PFD0_CLK_GATE, value: Enabled}
+- {id: CLKCTL.A32KHZWAKECLKDIV.scale, value: '32', locked: true}
+- {id: CLKCTL.AUDIOPLL0CLKSEL.sel, value: CLKCTL.OSC_CLKSEL}
+- {id: CLKCTL.AUDIOPLL0_PFD0_DIV.scale, value: '26', locked: true}
+- {id: CLKCTL.AUDIOPLLCLKDIV.scale, value: '15', locked: true}
+- {id: CLKCTL.AUDIO_PLL0_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CLKCTL.CLKOUTFCLKDIV.scale, value: '100', locked: true}
+- {id: CLKCTL.CLKOUTSEL0.sel, value: CLKCTL.FRO_DIV2_EN}
+- {id: CLKCTL.CLKOUTSEL1.sel, value: CLKCTL.CLKOUTSEL0}
+- {id: CLKCTL.DMIC0FCLKDIV.scale, value: '1', locked: true}
+- {id: CLKCTL.DSPCPUCLKDIV.scale, value: '1', locked: true}
+- {id: CLKCTL.FLEXSPI0FCLKDIV.scale, value: '2', locked: true}
+- {id: CLKCTL.FLEXSPI0FCLKSEL.sel, value: CLKCTL.MAINCLKSELB}
+- {id: CLKCTL.FRGPLLCLKDIV.scale, value: '11', locked: true}
+- {id: CLKCTL.I3C01FCLKSDIV.scale, value: '1', locked: true}
+- {id: CLKCTL.MAINCLKSELB.sel, value: CLKCTL.MAINPLLCLKDIV}
+- {id: CLKCTL.PFC0DIV.scale, value: '2', locked: true}
+- {id: CLKCTL.PFC1DIV.scale, value: '4', locked: true}
+- {id: CLKCTL.PLL0.denom, value: '1', locked: true}
+- {id: CLKCTL.PLL0.div, value: '22', locked: true}
+- {id: CLKCTL.PLL0.num, value: '0'}
+- {id: CLKCTL.PLL0_PFD0_DIV.scale, value: '24', locked: true}
+- {id: CLKCTL.PLL0_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CLKCTL.PLL0_PFD2_DIV.scale, value: '24', locked: true}
+- {id: CLKCTL.PLL0_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CLKCTL.PLL1.denom, value: '27000', locked: true}
+- {id: CLKCTL.PLL1.div, value: '22', locked: true}
+- {id: CLKCTL.PLL1.num, value: '5040', locked: true}
+- {id: CLKCTL.SYSCPUAHBCLKDIV.scale, value: '2', locked: true}
+- {id: CLKCTL.SYSPLL0CLKSEL.sel, value: CLKCTL.OSC_CLKSEL}
+- {id: CLKCTL.SYSTICKFCLKDIV.scale, value: '2', locked: true}
+- {id: CLKCTL.SYSTICKFCLKSEL.sel, value: CLKCTL.SYSTICKFCLKDIV}
+- {id: FRO_DIV16_EN_CFG, value: Enabled}
+- {id: FRO_DIV1_EN_CFG, value: Enabled}
+- {id: FRO_DIV2_EN_CFG, value: Enabled}
+- {id: FRO_DIV4_EN_CFG, value: Enabled}
+- {id: FRO_DIV8_EN_CFG, value: Enabled}
+- {id: PLL0_PFD0_CLK_GATE, value: Enabled}
+- {id: PLL0_PFD2_CLK_GATE, value: Enabled}
+- {id: SYSCTL_PDRUNCFG_AUDIOPLL_CFG, value: 'No'}
+- {id: SYSCTL_PDRUNCFG_SYSPLL_CFG, value: 'No'}
+- {id: SYSCTL_PDRUNCFG_SYSXTAL_CFG, value: Power_up}
+- {id: XTAL_LP_Enable, value: LowPowerMode}
+sources:
+- {id: CLKCTL.XTAL.outFreq, value: 24 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t g_sysPllConfig_BOARD_BootClockRUN = {
+ .sys_pll_src = kCLOCK_SysPllXtalIn, /* OSC clock */
+ .numerator = 0, /* Numerator of the SYSPLL0 fractional loop divider is 0 */
+ .denominator = 1, /* Denominator of the SYSPLL0 fractional loop divider is 1 */
+ .sys_pll_mult = kCLOCK_SysPllMult22 /* Divide by 22 */
+};
+const clock_audio_pll_config_t g_audioPllConfig_BOARD_BootClockRUN = {
+ .audio_pll_src = kCLOCK_AudioPllXtalIn, /* OSC clock */
+ .numerator = 5040, /* Numerator of the Audio PLL fractional loop divider is 0 */
+ .denominator = 27000, /* Denominator of the Audio PLL fractional loop divider is 1 */
+ .audio_pll_mult = kCLOCK_AudioPllMult22 /* Divide by 22 */
+};
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* Configure LPOSC 1M */
+ POWER_DisablePD(kPDRUNCFG_PD_LPOSC); /* Power on LPOSC (1MHz) */
+ CLOCK_EnableLpOscClk(); /* Wait until LPOSC stable */
+
+ /* Configure FRO clock source */
+ POWER_DisablePD(kPDRUNCFG_PD_FFRO); /* Power on FRO (192MHz or 96MHz) */
+ /* FRO_DIV1 is always enabled and used as Main clock during PLL update. */
+ CLOCK_EnableFroClk(kCLOCK_FroAllOutEn); /* Enable all FRO outputs */
+
+ /* Call function BOARD_FlexspiClockSafeConfig() to move FlexSPI clock to a stable clock source to avoid
+ instruction/data fetch issue when updating PLL and Main clock if XIP(execute code on FLEXSPI memory). */
+ BOARD_FlexspiClockSafeConfig();
+
+ /* Let CPU run on FRO with divider 2 for safe switching. */
+ CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2);
+ CLOCK_AttachClk(kFRO_DIV1_to_MAIN_CLK);
+
+ /* Configure SYSOSC clock source. */
+ POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL); /* Power on SYSXTAL */
+ POWER_UpdateOscSettlingTime(BOARD_SYSOSC_SETTLING_US); /* Updated XTAL oscillator settling time */
+ CLOCK_EnableSysOscClk(true, true, BOARD_SYSOSC_SETTLING_US); /* Enable system OSC */
+ CLOCK_SetXtalFreq(BOARD_XTAL_SYS_CLK_HZ); /* Sets external XTAL OSC freq */
+
+ /* Configure SysPLL0 clock source. */
+ CLOCK_InitSysPll(&g_sysPllConfig_BOARD_BootClockRUN);
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 24); /* Enable MAIN PLL clock */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); /* Enable AUX0 PLL clock */
+
+ /* Configure Audio PLL clock source. */
+ CLOCK_InitAudioPll(&g_audioPllConfig_BOARD_BootClockRUN);
+ CLOCK_InitAudioPfd(kCLOCK_Pfd0, 26); /* Enable Audio PLL clock */
+
+ CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); /* Set SYSCPUAHBCLKDIV divider to value 2 */
+
+ /* Set up clock selectors - Attach clocks to the peripheries. */
+ CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); /* Switch MAIN_CLK to MAIN_PLL */
+ CLOCK_AttachClk(kMAIN_CLK_DIV_to_SYSTICK_CLK); /* Switch SYSTICK_CLK to MAIN_CLK_DIV */
+ CLOCK_AttachClk(kFRO_DIV2_to_CLKOUT); /* Switch CLKOUT to FRO_DIV2 */
+
+ /* Set up dividers. */
+ CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); /* Set AUDIOPLLCLKDIV divider to value 15 */
+ CLOCK_SetClkDiv(kCLOCK_DivPLLFRGClk, 11U); /* Set FRGPLLCLKDIV divider to value 11 */
+ CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 2U); /* Set SYSTICKFCLKDIV divider to value 2 */
+ CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U); /* Set PFC0DIV divider to value 2 */
+ CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 4U); /* Set PFC1DIV divider to value 4 */
+ CLOCK_SetClkDiv(kCLOCK_DivClockOut, 100U); /* Set CLKOUTFCLKDIV divider to value 100 */
+
+ /* Call function BOARD_SetFlexspiClock() to set user configured clock source/divider for FlexSPI. */
+ BOARD_SetFlexspiClock(FLEXSPI0, 0U, 2U);
+
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+
+ /* Set main clock to FRO as deep sleep clock by default. */
+ POWER_SetDeepSleepClock(kDeepSleepClk_Fro);
+}
diff --git a/minimal-examples/embedded/rt595/hello_world/project/board/clock_config.h b/minimal-examples/embedded/rt595/hello_world/project/board/clock_config.h
new file mode 100644
index 000000000..94ea12ca8
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/board/clock_config.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2019-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_SYSOSC_SETTLING_US 220U /*!< Board System oscillator settling time in us */
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
+#define BOARD_XTAL_SYS_CLK_HZ 24000000U /*!< Board xtal frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 198000000U /*!< Core clock frequency: 198000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/board/pin_mux.c b/minimal-examples/embedded/rt595/hello_world/project/board/pin_mux.c
new file mode 100644
index 000000000..313f11614
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/board/pin_mux.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMXRT595S
+package_id: MIMXRT595SFFOC
+mcu_data: ksdk2_0
+processor_version: 0.9.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_iopctl.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'}
+- pin_list:
+ - {pin_num: H16, peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_2/FC0_RXD_SDA_MOSI_DATA/CTIMER0_MAT2/I2S_BRIDGE_DATA_IN/SEC_PIO0_2, ibena: enabled}
+ - {pin_num: G16, peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_1/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT1/I2S_BRIDGE_WS_IN/SEC_PIO0_1}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 */
+void BOARD_InitPins(void)
+{
+
+ const uint32_t port0_pin1_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
+ IOPCTL_PIO_FUNC1 |
+ /* Disable pull-up / pull-down function */
+ IOPCTL_PIO_PUPD_DI |
+ /* Enable pull-down function */
+ IOPCTL_PIO_PULLDOWN_EN |
+ /* Disable input buffer function */
+ IOPCTL_PIO_INBUF_DI |
+ /* Normal mode */
+ IOPCTL_PIO_SLEW_RATE_NORMAL |
+ /* Normal drive */
+ IOPCTL_PIO_FULLDRIVE_DI |
+ /* Analog mux is disabled */
+ IOPCTL_PIO_ANAMUX_DI |
+ /* Pseudo Output Drain is disabled */
+ IOPCTL_PIO_PSEDRAIN_DI |
+ /* Input function is not inverted */
+ IOPCTL_PIO_INV_DI);
+ /* PORT0 PIN1 (coords: G16) is configured as FC0_TXD_SCL_MISO_WS */
+ IOPCTL_PinMuxSet(IOPCTL, 0U, 1U, port0_pin1_config);
+
+ const uint32_t port0_pin2_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
+ IOPCTL_PIO_FUNC1 |
+ /* Disable pull-up / pull-down function */
+ IOPCTL_PIO_PUPD_DI |
+ /* Enable pull-down function */
+ IOPCTL_PIO_PULLDOWN_EN |
+ /* Enables input buffer function */
+ IOPCTL_PIO_INBUF_EN |
+ /* Normal mode */
+ IOPCTL_PIO_SLEW_RATE_NORMAL |
+ /* Normal drive */
+ IOPCTL_PIO_FULLDRIVE_DI |
+ /* Analog mux is disabled */
+ IOPCTL_PIO_ANAMUX_DI |
+ /* Pseudo Output Drain is disabled */
+ IOPCTL_PIO_PSEDRAIN_DI |
+ /* Input function is not inverted */
+ IOPCTL_PIO_INV_DI);
+ /* PORT0 PIN2 (coords: H16) is configured as FC0_RXD_SDA_MOSI_DATA */
+ IOPCTL_PinMuxSet(IOPCTL, 0U, 2U, port0_pin2_config);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/minimal-examples/embedded/rt595/hello_world/project/board/pin_mux.h b/minimal-examples/embedded/rt595/hello_world/project/board/pin_mux.h
new file mode 100644
index 000000000..902e65f0e
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/board/pin_mux.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define IOPCTL_PIO_ANAMUX_DI 0x00u /*!<@brief Analog mux is disabled */
+#define IOPCTL_PIO_FULLDRIVE_DI 0x00u /*!<@brief Normal drive */
+#define IOPCTL_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */
+#define IOPCTL_PIO_INBUF_DI 0x00u /*!<@brief Disable input buffer function */
+#define IOPCTL_PIO_INBUF_EN 0x40u /*!<@brief Enables input buffer function */
+#define IOPCTL_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
+#define IOPCTL_PIO_PSEDRAIN_DI 0x00u /*!<@brief Pseudo Output Drain is disabled */
+#define IOPCTL_PIO_PULLDOWN_EN 0x00u /*!<@brief Enable pull-down function */
+#define IOPCTL_PIO_PUPD_DI 0x00u /*!<@brief Disable pull-up / pull-down function */
+#define IOPCTL_PIO_SLEW_RATE_NORMAL 0x00u /*!<@brief Normal mode */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/minimal-examples/embedded/rt595/hello_world/project/component/lists/fsl_component_generic_list.c b/minimal-examples/embedded/rt595/hello_world/project/component/lists/fsl_component_generic_list.c
new file mode 100644
index 000000000..6184631f7
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/component/lists/fsl_component_generic_list.c
@@ -0,0 +1,493 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Include
+*************************************************************************************
+********************************************************************************** */
+#include "fsl_component_generic_list.h"
+
+#if defined(OSA_USED)
+#include "fsl_os_abstraction.h"
+#if (defined(USE_RTOS) && (USE_RTOS > 0U))
+#define LIST_ENTER_CRITICAL() \
+ OSA_SR_ALLOC(); \
+ OSA_ENTER_CRITICAL()
+#define LIST_EXIT_CRITICAL() OSA_EXIT_CRITICAL()
+#else
+#define LIST_ENTER_CRITICAL()
+#define LIST_EXIT_CRITICAL()
+#endif
+#else
+#define LIST_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ();
+#define LIST_EXIT_CRITICAL() EnableGlobalIRQ(regPrimask);
+#endif
+
+static list_status_t LIST_Error_Check(list_handle_t list, list_element_handle_t newElement)
+{
+ list_status_t listStatus = kLIST_Ok;
+#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U))
+ list_element_handle_t element = list->head;
+#endif
+ if ((list->max != 0U) && (list->max == list->size))
+ {
+ listStatus = kLIST_Full; /*List is full*/
+ }
+#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U))
+ else
+ {
+ while (element != NULL) /*Scan list*/
+ {
+ /* Determine if element is duplicated */
+ if (element == newElement)
+ {
+ listStatus = kLIST_DuplicateError;
+ break;
+ }
+ element = element->next;
+ }
+ }
+#endif
+ return listStatus;
+}
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public functions
+*************************************************************************************
+********************************************************************************** */
+/*! *********************************************************************************
+ * \brief Initialises the list descriptor.
+ *
+ * \param[in] list - LIST_ handle to init.
+ * max - Maximum number of elements in list. 0 for unlimited.
+ *
+ * \return void.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+void LIST_Init(list_handle_t list, uint32_t max)
+{
+ list->head = NULL;
+ list->tail = NULL;
+ list->max = (uint16_t)max;
+ list->size = 0;
+}
+
+/*! *********************************************************************************
+ * \brief Gets the list that contains the given element.
+ *
+ * \param[in] element - Handle of the element.
+ *
+ * \return NULL if element is orphan.
+ * Handle of the list the element is inserted into.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_handle_t LIST_GetList(list_element_handle_t element)
+{
+ return element->list;
+}
+
+/*! *********************************************************************************
+ * \brief Links element to the tail of the list.
+ *
+ * \param[in] list - ID of list to insert into.
+ * element - element to add
+ *
+ * \return kLIST_Full if list is full.
+ * kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element)
+{
+ LIST_ENTER_CRITICAL();
+ list_status_t listStatus = kLIST_Ok;
+
+ listStatus = LIST_Error_Check(list, element);
+ if (listStatus == kLIST_Ok) /* Avoiding list status error */
+ {
+ if (list->size == 0U)
+ {
+ list->head = element;
+ }
+ else
+ {
+ list->tail->next = element;
+ }
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#else
+ element->prev = list->tail;
+#endif
+ element->list = list;
+ element->next = NULL;
+ list->tail = element;
+ list->size++;
+ }
+
+ LIST_EXIT_CRITICAL();
+ return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief Links element to the head of the list.
+ *
+ * \param[in] list - ID of list to insert into.
+ * element - element to add
+ *
+ * \return kLIST_Full if list is full.
+ * kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element)
+{
+ LIST_ENTER_CRITICAL();
+ list_status_t listStatus = kLIST_Ok;
+
+ listStatus = LIST_Error_Check(list, element);
+ if (listStatus == kLIST_Ok) /* Avoiding list status error */
+ {
+ /* Links element to the head of the list */
+ if (list->size == 0U)
+ {
+ list->tail = element;
+ }
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#else
+ else
+ {
+ list->head->prev = element;
+ }
+ element->prev = NULL;
+#endif
+ element->list = list;
+ element->next = list->head;
+ list->head = element;
+ list->size++;
+ }
+
+ LIST_EXIT_CRITICAL();
+ return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief Unlinks element from the head of the list.
+ *
+ * \param[in] list - ID of list to remove from.
+ *
+ * \return NULL if list is empty.
+ * ID of removed element(pointer) if removal was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_RemoveHead(list_handle_t list)
+{
+ list_element_handle_t element;
+
+ LIST_ENTER_CRITICAL();
+
+ if ((NULL == list) || (list->size == 0U))
+ {
+ element = NULL; /*LIST_ is empty*/
+ }
+ else
+ {
+ element = list->head;
+ list->size--;
+ if (list->size == 0U)
+ {
+ list->tail = NULL;
+ }
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#else
+ else
+ {
+ element->next->prev = NULL;
+ }
+#endif
+ element->list = NULL;
+ list->head = element->next; /*Is NULL if element is head*/
+ }
+
+ LIST_EXIT_CRITICAL();
+ return element;
+}
+
+/*! *********************************************************************************
+ * \brief Gets head element ID.
+ *
+ * \param[in] list - ID of list.
+ *
+ * \return NULL if list is empty.
+ * ID of head element if list is not empty.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetHead(list_handle_t list)
+{
+ return list->head;
+}
+
+/*! *********************************************************************************
+ * \brief Gets next element ID.
+ *
+ * \param[in] element - ID of the element.
+ *
+ * \return NULL if element is tail.
+ * ID of next element if exists.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetNext(list_element_handle_t element)
+{
+ return element->next;
+}
+
+/*! *********************************************************************************
+ * \brief Gets previous element ID.
+ *
+ * \param[in] element - ID of the element.
+ *
+ * \return NULL if element is head.
+ * ID of previous element if exists.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetPrev(list_element_handle_t element)
+{
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+ return NULL;
+#else
+ return element->prev;
+#endif
+}
+
+/*! *********************************************************************************
+ * \brief Unlinks an element from its list.
+ *
+ * \param[in] element - ID of the element to remove.
+ *
+ * \return kLIST_OrphanElement if element is not part of any list.
+ * kLIST_Ok if removal was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_RemoveElement(list_element_handle_t element)
+{
+ list_status_t listStatus = kLIST_Ok;
+ LIST_ENTER_CRITICAL();
+
+ if (element->list == NULL)
+ {
+ listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/
+ }
+ else
+ {
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+ list_element_handle_t element_list = element->list->head;
+ while (NULL != element_list)
+ {
+ if (element->list->head == element)
+ {
+ element->list->head = element_list->next;
+ break;
+ }
+ if (element_list->next == element)
+ {
+ element_list->next = element->next;
+ break;
+ }
+ element_list = element_list->next;
+ }
+#else
+ if (element->prev == NULL) /*Element is head or solo*/
+ {
+ element->list->head = element->next; /*is null if solo*/
+ }
+ if (element->next == NULL) /*Element is tail or solo*/
+ {
+ element->list->tail = element->prev; /*is null if solo*/
+ }
+ if (element->prev != NULL) /*Element is not head*/
+ {
+ element->prev->next = element->next;
+ }
+ if (element->next != NULL) /*Element is not tail*/
+ {
+ element->next->prev = element->prev;
+ }
+#endif
+ element->list->size--;
+ element->list = NULL;
+ }
+
+ LIST_EXIT_CRITICAL();
+ return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief Links an element in the previous position relative to a given member
+ * of a list.
+ *
+ * \param[in] element - ID of a member of a list.
+ * newElement - new element to insert before the given member.
+ *
+ * \return kLIST_OrphanElement if element is not part of any list.
+ * kLIST_Full if list is full.
+ * kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement)
+{
+ list_status_t listStatus = kLIST_Ok;
+ LIST_ENTER_CRITICAL();
+
+ if (element->list == NULL)
+ {
+ listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/
+ }
+ else
+ {
+ listStatus = LIST_Error_Check(element->list, newElement);
+ if (listStatus == kLIST_Ok)
+ {
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+ list_element_handle_t element_list = element->list->head;
+ while (NULL != element_list)
+ {
+ if ((element_list->next == element) || (element_list == element))
+ {
+ if (element_list == element)
+ {
+ element->list->head = newElement;
+ }
+ else
+ {
+ element_list->next = newElement;
+ }
+ newElement->list = element->list;
+ newElement->next = element;
+ element->list->size++;
+ break;
+ }
+ element_list = element_list->next;
+ }
+
+#else
+ if (element->prev == NULL) /*Element is list head*/
+ {
+ element->list->head = newElement;
+ }
+ else
+ {
+ element->prev->next = newElement;
+ }
+ newElement->list = element->list;
+ element->list->size++;
+ newElement->next = element;
+ newElement->prev = element->prev;
+ element->prev = newElement;
+#endif
+ }
+ }
+
+ LIST_EXIT_CRITICAL();
+ return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief Gets the current size of a list.
+ *
+ * \param[in] list - ID of the list.
+ *
+ * \return Current size of the list.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+uint32_t LIST_GetSize(list_handle_t list)
+{
+ return list->size;
+}
+
+/*! *********************************************************************************
+ * \brief Gets the number of free places in the list.
+ *
+ * \param[in] list - ID of the list.
+ *
+ * \return Available size of the list.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+uint32_t LIST_GetAvailableSize(list_handle_t list)
+{
+ return ((uint32_t)list->max - (uint32_t)list->size); /*Gets the number of free places in the list*/
+}
diff --git a/minimal-examples/embedded/rt595/hello_world/project/component/lists/fsl_component_generic_list.h b/minimal-examples/embedded/rt595/hello_world/project/component/lists/fsl_component_generic_list.h
new file mode 100644
index 000000000..312aa8a96
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/component/lists/fsl_component_generic_list.h
@@ -0,0 +1,201 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _GENERIC_LIST_H_
+#define _GENERIC_LIST_H_
+
+#include "fsl_common.h"
+/*!
+ * @addtogroup GenericList
+ * @{
+ */
+
+/**********************************************************************************
+ * Include
+ ***********************************************************************************/
+
+/**********************************************************************************
+ * Public macro definitions
+ ***********************************************************************************/
+/*! @brief Definition to determine whether use list light. */
+#ifndef GENERIC_LIST_LIGHT
+#define GENERIC_LIST_LIGHT (1)
+#endif
+
+/*! @brief Definition to determine whether enable list duplicated checking. */
+#ifndef GENERIC_LIST_DUPLICATED_CHECKING
+#define GENERIC_LIST_DUPLICATED_CHECKING (0)
+#endif
+
+/**********************************************************************************
+ * Public type definitions
+ ***********************************************************************************/
+/*! @brief The list status */
+typedef enum _list_status
+{
+ kLIST_Ok = kStatus_Success, /*!< Success */
+ kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */
+ kLIST_Full = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */
+ kLIST_Empty = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */
+ kLIST_OrphanElement = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */
+ kLIST_NotSupport = MAKE_STATUS(kStatusGroup_LIST, 5), /*!< Not Support */
+} list_status_t;
+
+/*! @brief The list structure*/
+typedef struct list_label
+{
+ struct list_element_tag *head; /*!< list head */
+ struct list_element_tag *tail; /*!< list tail */
+ uint16_t size; /*!< list size */
+ uint16_t max; /*!< list max number of elements */
+} list_label_t, *list_handle_t;
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+/*! @brief The list element*/
+typedef struct list_element_tag
+{
+ struct list_element_tag *next; /*!< next list element */
+ struct list_label *list; /*!< pointer to the list */
+} list_element_t, *list_element_handle_t;
+#else
+/*! @brief The list element*/
+typedef struct list_element_tag
+{
+ struct list_element_tag *next; /*!< next list element */
+ struct list_element_tag *prev; /*!< previous list element */
+ struct list_label *list; /*!< pointer to the list */
+} list_element_t, *list_element_handle_t;
+#endif
+/**********************************************************************************
+ * Public prototypes
+ ***********************************************************************************/
+/**********************************************************************************
+ * API
+ **********************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+/*!
+ * @brief Initialize the list.
+ *
+ * This function initialize the list.
+ *
+ * @param list - List handle to initialize.
+ * @param max - Maximum number of elements in list. 0 for unlimited.
+ */
+void LIST_Init(list_handle_t list, uint32_t max);
+
+/*!
+ * @brief Gets the list that contains the given element.
+ *
+ *
+ * @param element - Handle of the element.
+ * @retval NULL if element is orphan, Handle of the list the element is inserted into.
+ */
+list_handle_t LIST_GetList(list_element_handle_t element);
+
+/*!
+ * @brief Links element to the head of the list.
+ *
+ * @param list - Handle of the list.
+ * @param element - Handle of the element.
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
+ */
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element);
+
+/*!
+ * @brief Links element to the tail of the list.
+ *
+ * @param list - Handle of the list.
+ * @param element - Handle of the element.
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
+ */
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element);
+
+/*!
+ * @brief Unlinks element from the head of the list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_RemoveHead(list_handle_t list);
+
+/*!
+ * @brief Gets head element handle.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetHead(list_handle_t list);
+
+/*!
+ * @brief Gets next element handle for given element handle.
+ *
+ * @param element - Handle of the element.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetNext(list_element_handle_t element);
+
+/*!
+ * @brief Gets previous element handle for given element handle.
+ *
+ * @param element - Handle of the element.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetPrev(list_element_handle_t element);
+
+/*!
+ * @brief Unlinks an element from its list.
+ *
+ * @param element - Handle of the element.
+ *
+ * @retval kLIST_OrphanElement if element is not part of any list.
+ * @retval kLIST_Ok if removal was successful.
+ */
+list_status_t LIST_RemoveElement(list_element_handle_t element);
+
+/*!
+ * @brief Links an element in the previous position relative to a given member of a list.
+ *
+ * @param element - Handle of the element.
+ * @param newElement - New element to insert before the given member.
+ *
+ * @retval kLIST_OrphanElement if element is not part of any list.
+ * @retval kLIST_Ok if removal was successful.
+ */
+list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement);
+
+/*!
+ * @brief Gets the current size of a list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval Current size of the list.
+ */
+uint32_t LIST_GetSize(list_handle_t list);
+
+/*!
+ * @brief Gets the number of free places in the list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval Available size of the list.
+ */
+uint32_t LIST_GetAvailableSize(list_handle_t list);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @}*/
+#endif /*_GENERIC_LIST_H_*/
diff --git a/minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction.h b/minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction.h
new file mode 100644
index 000000000..9f4fe4d8e
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction.h
@@ -0,0 +1,906 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_OS_ABSTRACTION_H_
+#define _FSL_OS_ABSTRACTION_H_
+
+#include "fsl_common.h"
+#include "fsl_os_abstraction_config.h"
+#include "fsl_component_generic_list.h"
+
+/*!
+ * @addtogroup osa_adapter
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Type for the Task Priority*/
+typedef uint16_t osa_task_priority_t;
+/*! @brief Type for a task handler */
+typedef void *osa_task_handle_t;
+/*! @brief Type for the parameter to be passed to the task at its creation */
+typedef void *osa_task_param_t;
+/*! @brief Type for task pointer. Task prototype declaration */
+typedef void (*osa_task_ptr_t)(osa_task_param_t task_param);
+/*! @brief Type for the semaphore handler */
+typedef void *osa_semaphore_handle_t;
+/*! @brief Type for the mutex handler */
+typedef void *osa_mutex_handle_t;
+/*! @brief Type for the event handler */
+typedef void *osa_event_handle_t;
+/*! @brief Type for an event flags group, bit 32 is reserved. */
+typedef uint32_t osa_event_flags_t;
+/*! @brief Message definition. */
+typedef void *osa_msg_handle_t;
+/*! @brief Type for the message queue handler */
+typedef void *osa_msgq_handle_t;
+/*! @brief Type for the Timer handler */
+typedef void *osa_timer_handle_t;
+/*! @brief Type for the Timer callback function pointer. */
+typedef void (*osa_timer_fct_ptr_t)(void const *argument);
+/*! @brief Thread Definition structure contains startup information of a thread.*/
+typedef struct osa_task_def_tag
+{
+ osa_task_ptr_t pthread; /*!< start address of thread function*/
+ uint32_t tpriority; /*!< initial thread priority*/
+ uint32_t instances; /*!< maximum number of instances of that thread function*/
+ uint32_t stacksize; /*!< stack size requirements in bytes; 0 is default stack size*/
+ uint32_t *tstack; /*!< stack pointer*/
+ void *tlink; /*!< link pointer*/
+ uint8_t *tname; /*!< name pointer*/
+ uint8_t useFloat; /*!< is use float*/
+} osa_task_def_t;
+/*! @brief Thread Link Definition structure .*/
+typedef struct osa_thread_link_tag
+{
+ uint8_t link[12]; /*!< link*/
+ osa_task_handle_t osThreadId; /*!< thread id*/
+ osa_task_def_t *osThreadDefHandle; /*!< pointer of thread define handle*/
+ uint32_t *osThreadStackHandle; /*!< pointer of thread stack handle*/
+} osa_thread_link_t, *osa_thread_link_handle_t;
+
+/*! @brief Definition structure contains timer parameters.*/
+typedef struct osa_time_def_tag
+{
+ osa_timer_fct_ptr_t pfCallback; /* < start address of a timer function */
+ void *argument; /* < argument of a timer function */
+} osa_time_def_t;
+
+/*! @brief Type for the timer definition*/
+typedef enum _osa_timer
+{
+ KOSA_TimerOnce = 0, /*!< one-shot timer*/
+ KOSA_TimerPeriodic = 1 /*!< repeating timer*/
+} osa_timer_t;
+
+/*! @brief Defines the return status of OSA's functions */
+typedef enum _osa_status
+{
+ KOSA_StatusSuccess = kStatus_Success, /*!< Success */
+ KOSA_StatusError = MAKE_STATUS(kStatusGroup_OSA, 1), /*!< Failed */
+ KOSA_StatusTimeout = MAKE_STATUS(kStatusGroup_OSA, 2), /*!< Timeout occurs while waiting */
+ KOSA_StatusIdle = MAKE_STATUS(kStatusGroup_OSA, 3), /*!< Used for bare metal only, the wait object is not ready
+ and timeout still not occur */
+} osa_status_t;
+
+#ifdef USE_RTOS
+#undef USE_RTOS
+#endif
+
+#if defined(SDK_OS_MQX)
+#define USE_RTOS (1)
+#elif defined(SDK_OS_FREE_RTOS)
+#define USE_RTOS (1)
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#define OSA_TASK_HANDLE_SIZE (12U)
+#else
+#define OSA_TASK_HANDLE_SIZE (16U)
+#endif
+#define OSA_EVENT_HANDLE_SIZE (8U)
+#define OSA_SEM_HANDLE_SIZE (4U)
+#define OSA_MUTEX_HANDLE_SIZE (4U)
+#define OSA_MSGQ_HANDLE_SIZE (4U)
+#define OSA_MSG_HANDLE_SIZE (0U)
+#elif defined(SDK_OS_UCOSII)
+#define USE_RTOS (1)
+#elif defined(SDK_OS_UCOSIII)
+#define USE_RTOS (1)
+#elif defined(FSL_RTOS_THREADX)
+#define USE_RTOS (1)
+#else
+#define USE_RTOS (0)
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#define OSA_TASK_HANDLE_SIZE (24U)
+#else
+#define OSA_TASK_HANDLE_SIZE (28U)
+#endif
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+#define OSA_EVENT_HANDLE_SIZE (20U)
+#else
+#define OSA_EVENT_HANDLE_SIZE (16U)
+#endif /* FSL_OSA_TASK_ENABLE */
+#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U))
+#define OSA_SEM_HANDLE_SIZE (12U)
+#define OSA_MUTEX_HANDLE_SIZE (12U)
+#else
+#define OSA_SEM_HANDLE_SIZE (4U)
+#define OSA_MUTEX_HANDLE_SIZE (4U)
+#endif
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+#define OSA_MSGQ_HANDLE_SIZE (32U)
+#else
+#define OSA_MSGQ_HANDLE_SIZE (28U)
+#endif /* FSL_OSA_TASK_ENABLE */
+#define OSA_MSG_HANDLE_SIZE (4U)
+#endif
+
+/*! @brief Priority setting for OSA. */
+#ifndef OSA_PRIORITY_IDLE
+#define OSA_PRIORITY_IDLE (6)
+#endif
+
+#ifndef OSA_PRIORITY_LOW
+#define OSA_PRIORITY_LOW (5)
+#endif
+
+#ifndef OSA_PRIORITY_BELOW_NORMAL
+#define OSA_PRIORITY_BELOW_NORMAL (4)
+#endif
+
+#ifndef OSA_PRIORITY_NORMAL
+#define OSA_PRIORITY_NORMAL (3)
+#endif
+
+#ifndef OSA_PRIORITY_ABOVE_NORMAL
+#define OSA_PRIORITY_ABOVE_NORMAL (2)
+#endif
+
+#ifndef OSA_PRIORITY_HIGH
+#define OSA_PRIORITY_HIGH (1)
+#endif
+
+#ifndef OSA_PRIORITY_REAL_TIME
+#define OSA_PRIORITY_REAL_TIME (0)
+#endif
+
+#ifndef OSA_TASK_PRIORITY_MAX
+#define OSA_TASK_PRIORITY_MAX (0)
+#endif
+
+#ifndef OSA_TASK_PRIORITY_MIN
+#define OSA_TASK_PRIORITY_MIN (15)
+#endif
+
+#define SIZE_IN_UINT32_UNITS(size) (((size) + sizeof(uint32_t) - 1) / sizeof(uint32_t))
+
+/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
+#define osaWaitNone_c ((uint32_t)(0))
+#define osaWaitForever_c ((uint32_t)(-1))
+#define osaEventFlagsAll_c ((osa_event_flags_t)(0x00FFFFFF))
+#define osThreadStackArray(name) osThread_##name##_stack
+#define osThreadStackDef(name, stacksize, instances) \
+ const uint32_t osThreadStackArray(name)[SIZE_IN_UINT32_UNITS(stacksize) * (instances)];
+
+/* ==== Thread Management ==== */
+
+/* Create a Thread Definition with function, priority, and stack requirements.
+ * \param name name of the thread function.
+ * \param priority initial priority of the thread function.
+ * \param instances number of possible thread instances.
+ * \param stackSz stack size (in bytes) requirements for the thread function.
+ * \param useFloat
+ */
+#if defined(SDK_OS_MQX)
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
+ osa_thread_link_t osThreadLink_##name[instances] = {0}; \
+ osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \
+ (name), (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \
+ (uint8_t *)#name, (useFloat)}
+#elif defined(SDK_OS_UCOSII)
+#if gTaskMultipleInstancesManagement_c
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
+ osa_thread_link_t osThreadLink_##name[instances] = {0}; \
+ osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \
+ (name), (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \
+ (uint8_t *)#name, (useFloat)}
+#else
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
+ osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \
+ (name), (priority), (instances), (stackSz), osThreadStackArray(name), NULL, (uint8_t *)#name, (useFloat)}
+#endif
+#elif defined(FSL_RTOS_THREADX)
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
+ uint32_t s_stackBuffer##name[(stackSz + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]; \
+ static const osa_task_def_t os_thread_def_##name = { \
+ (name), (priority), (instances), (stackSz), s_stackBuffer##name, NULL, (uint8_t *)#name, (useFloat)}
+#else
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
+ const osa_task_def_t os_thread_def_##name = {(name), (priority), (instances), (stackSz), \
+ NULL, NULL, (uint8_t *)#name, (useFloat)}
+#endif
+/* Access a Thread defintion.
+ * \param name name of the thread definition object.
+ */
+#define OSA_TASK(name) (const osa_task_def_t *)&os_thread_def_##name
+
+#define OSA_TASK_PROTO(name) extern osa_task_def_t os_thread_def_##name
+/* ==== Timer Management ====
+ * Define a Timer object.
+ * \param name name of the timer object.
+ * \param function name of the timer call back function.
+ */
+
+#define OSA_TIMER_DEF(name, function) osa_time_def_t os_timer_def_##name = {(function), NULL}
+
+/* Access a Timer definition.
+ * \param name name of the timer object.
+ */
+#define OSA_TIMER(name) &os_timer_def_##name
+
+/* ==== Buffer Definition ==== */
+
+/*!
+ * @brief Defines the semaphore handle
+ *
+ * This macro is used to define a 4 byte aligned semaphore handle.
+ * Then use "(osa_semaphore_handle_t)name" to get the semaphore handle.
+ *
+ * The macro should be global and could be optional. You could also define semaphore handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ * @endcode
+ *
+ * @param name The name string of the semaphore handle.
+ */
+#define OSA_SEMAPHORE_HANDLE_DEFINE(name) \
+ uint32_t name[(OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+/*!
+ * @brief Defines the mutex handle
+ *
+ * This macro is used to define a 4 byte aligned mutex handle.
+ * Then use "(osa_mutex_handle_t)name" to get the mutex handle.
+ *
+ * The macro should be global and could be optional. You could also define mutex handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * OSA_MUTEX_HANDLE_DEFINE(mutexHandle);
+ * @endcode
+ *
+ * @param name The name string of the mutex handle.
+ */
+#define OSA_MUTEX_HANDLE_DEFINE(name) uint32_t name[(OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+/*!
+ * @brief Defines the event handle
+ *
+ * This macro is used to define a 4 byte aligned event handle.
+ * Then use "(osa_event_handle_t)name" to get the event handle.
+ *
+ * The macro should be global and could be optional. You could also define event handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * OSA_EVENT_HANDLE_DEFINE(eventHandle);
+ * @endcode
+ *
+ * @param name The name string of the event handle.
+ */
+#define OSA_EVENT_HANDLE_DEFINE(name) uint32_t name[(OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+/*!
+ * @brief Defines the message queue handle
+ *
+ * This macro is used to define a 4 byte aligned message queue handle.
+ * Then use "(osa_msgq_handle_t)name" to get the message queue handle.
+ *
+ * The macro should be global and could be optional. You could also define message queue handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * OSA_MSGQ_HANDLE_DEFINE(msgqHandle, 3, sizeof(msgStruct));
+ * @endcode
+ *
+ * @param name The name string of the message queue handle.
+ * @param numberOfMsgs Number of messages.
+ * @param msgSize Message size.
+ *
+ */
+#if defined(SDK_OS_FREE_RTOS)
+/*< Macro For FREE_RTOS*/
+#define OSA_MSGQ_HANDLE_DEFINE(name, numberOfMsgs, msgSize) \
+ uint32_t name[(OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+#else
+/*< Macro For BARE_MATEL*/
+#define OSA_MSGQ_HANDLE_DEFINE(name, numberOfMsgs, msgSize) \
+ uint32_t name[((OSA_MSGQ_HANDLE_SIZE + numberOfMsgs * msgSize) + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+#endif
+
+/*!
+ * @brief Defines the TASK handle
+ *
+ * This macro is used to define a 4 byte aligned TASK handle.
+ * Then use "(osa_task_handle_t)name" to get the TASK handle.
+ *
+ * The macro should be global and could be optional. You could also define TASK handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * OSA_TASK_HANDLE_DEFINE(taskHandle);
+ * @endcode
+ *
+ * @param name The name string of the TASK handle.
+ */
+#define OSA_TASK_HANDLE_DEFINE(name) uint32_t name[(OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+#if defined(SDK_OS_FREE_RTOS)
+#include "fsl_os_abstraction_free_rtos.h"
+#elif defined(FSL_RTOS_THREADX)
+#include "fsl_os_abstraction_threadx.h"
+#else
+#include "fsl_os_abstraction_bm.h"
+#endif
+
+extern const uint8_t gUseRtos_c;
+
+/*
+ * alloc the temporary memory to store the status
+ */
+#define OSA_SR_ALLOC() uint32_t osaCurrentSr;
+/*
+ * Enter critical mode
+ */
+#define OSA_ENTER_CRITICAL() OSA_EnterCritical(&osaCurrentSr)
+/*
+ * Exit critical mode and retore the previous mode
+ */
+#define OSA_EXIT_CRITICAL() OSA_ExitCritical(osaCurrentSr)
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Reserves the requested amount of memory in bytes.
+ *
+ * The function is used to reserve the requested amount of memory in bytes and initializes it to 0.
+ *
+ * @param length Amount of bytes to reserve.
+ *
+ * @return Pointer to the reserved memory. NULL if memory can't be allocated.
+ */
+void *OSA_MemoryAllocate(uint32_t length);
+
+/*!
+ * @brief Frees the memory previously reserved.
+ *
+ * The function is used to free the memory block previously reserved.
+ *
+ * @param p Pointer to the start of the memory block previously reserved.
+ *
+ */
+void OSA_MemoryFree(void *p);
+
+/*!
+ * @brief Enter critical with nesting mode.
+ *
+ * @param sr Store current status and return to caller.
+ */
+void OSA_EnterCritical(uint32_t *sr);
+
+/*!
+ * @brief Exit critical with nesting mode.
+ *
+ * @param sr Previous status to restore.
+ */
+void OSA_ExitCritical(uint32_t sr);
+
+/*!
+ * @name Task management
+ * @{
+ */
+
+/*!
+ * @brief Initialize OSA.
+ *
+ * This function is used to setup the basic services.
+ *
+ * Example below shows how to use this API to create the task handle.
+ * @code
+ * OSA_Init();
+ * @endcode
+ */
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+void OSA_Init(void);
+#endif
+
+/*!
+ * @brief Start OSA schedule.
+ *
+ * This function is used to start OSA scheduler.
+ *
+ * Example below shows how to use this API to start osa schedule.
+ * @code
+ * OSA_Start();
+ * @endcode
+ */
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+void OSA_Start(void);
+#endif
+
+/*!
+ * @brief Creates a task.
+ *
+ * This function is used to create task based on the resources defined
+ * by the macro OSA_TASK_DEFINE.
+ *
+ * Example below shows how to use this API to create the task handle.
+ * @code
+ * OSA_TASK_HANDLE_DEFINE(taskHandle);
+ * OSA_TASK_DEFINE( Job1, OSA_PRIORITY_HIGH, 1, 800, 0);
+ * OSA_TaskCreate((osa_task_handle_t)taskHandle, OSA_TASK(Job1), (osa_task_param_t)NULL);
+ * @endcode
+ *
+ * @param taskHandle Pointer to a memory space of size OSA_TASK_HANDLE_SIZE allocated by the caller, task handle.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_TASK_HANDLE_DEFINE(taskHandle);
+ * or
+ * uint32_t taskHandle[((OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param thread_def pointer to theosa_task_def_t structure which defines the task.
+ * @param task_param Pointer to be passed to the task when it is created.
+ * @retval KOSA_StatusSuccess The task is successfully created.
+ * @retval KOSA_StatusError The task can not be created.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle,
+ const osa_task_def_t *thread_def,
+ osa_task_param_t task_param);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Gets the handler of active task.
+ *
+ * @return Handler to current active task.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_task_handle_t OSA_TaskGetCurrentHandle(void);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Puts the active task to the end of scheduler's queue.
+ *
+ * When a task calls this function, it gives up the CPU and puts itself to the
+ * end of a task ready list.
+ *
+ * @retval KOSA_StatusSuccess The function is called successfully.
+ * @retval KOSA_StatusError Error occurs with this function.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskYield(void);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Gets the priority of a task.
+ *
+ * @param taskHandle The handler of the task whose priority is received.
+ *
+ * @return Task's priority.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Sets the priority of a task.
+ *
+ * @param taskHandle The handler of the task whose priority is set.
+ * @param taskPriority The priority to set.
+ *
+ * @retval KOSA_StatusSuccess Task's priority is set successfully.
+ * @retval KOSA_StatusError Task's priority can not be set.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Destroys a previously created task.
+ *
+ * @param taskHandle The handler of the task to destroy.
+ *
+ * @retval KOSA_StatusSuccess The task was successfully destroyed.
+ * @retval KOSA_StatusError Task destruction failed or invalid parameter.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Creates a semaphore with a given value.
+ *
+ * This function creates a semaphore and sets the value to the parameter
+ * initValue.
+ *
+ * Example below shows how to use this API to create the semaphore handle.
+ * @code
+ * OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ * OSA_SemaphoreCreate((osa_semaphore_handle_t)semaphoreHandle, 0xff);
+ * @endcode
+ *
+ * @param semaphoreHandle Pointer to a memory space of size OSA_SEM_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ * or
+ * uint32_t semaphoreHandle[((OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param initValue Initial value the semaphore will be set to.
+ *
+ * @retval KOSA_StatusSuccess the new semaphore if the semaphore is created successfully.
+ * @retval KOSA_StatusError if the semaphore can not be created.
+ */
+osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue);
+
+/*!
+ * @brief Destroys a previously created semaphore.
+ *
+ * @param semaphoreHandle The semaphore handle.
+ * The macro SEMAPHORE_HANDLE_BUFFER_GET is used to get the semaphore buffer pointer,
+ * and should not be used before the macro SEMAPHORE_HANDLE_BUFFER_DEFINE is used.
+ *
+ * @retval KOSA_StatusSuccess The semaphore is successfully destroyed.
+ * @retval KOSA_StatusError The semaphore can not be destroyed.
+ */
+osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle);
+
+/*!
+ * @brief Pending a semaphore with timeout.
+ *
+ * This function checks the semaphore's counting value. If it is positive,
+ * decreases it and returns KOSA_StatusSuccess. Otherwise, a timeout is used
+ * to wait.
+ *
+ * @param semaphoreHandle The semaphore handle.
+ * @param millisec The maximum number of milliseconds to wait if semaphore is not
+ * positive. Pass osaWaitForever_c to wait indefinitely, pass 0
+ * will return KOSA_StatusTimeout immediately.
+ *
+ * @retval KOSA_StatusSuccess The semaphore is received.
+ * @retval KOSA_StatusTimeout The semaphore is not received within the specified 'timeout'.
+ * @retval KOSA_StatusError An incorrect parameter was passed.
+ */
+osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec);
+
+/*!
+ * @brief Signals for someone waiting on the semaphore to wake up.
+ *
+ * Wakes up one task that is waiting on the semaphore. If no task is waiting, increases
+ * the semaphore's counting value.
+ *
+ * @param semaphoreHandle The semaphore handle to signal.
+ *
+ * @retval KOSA_StatusSuccess The semaphore is successfully signaled.
+ * @retval KOSA_StatusError The object can not be signaled or invalid parameter.
+ *
+ */
+osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle);
+
+/*!
+ * @brief Create an unlocked mutex.
+ *
+ * This function creates a non-recursive mutex and sets it to unlocked status.
+ *
+ * Example below shows how to use this API to create the mutex handle.
+ * @code
+ * OSA_MUTEX_HANDLE_DEFINE(mutexHandle);
+ * OSA_MutexCreate((osa_mutex_handle_t)mutexHandle);
+ * @endcode
+ *
+ * @param mutexHandle Pointer to a memory space of size OSA_MUTEX_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_MUTEX_HANDLE_DEFINE(mutexHandle);
+ * or
+ * uint32_t mutexHandle[((OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @retval KOSA_StatusSuccess the new mutex if the mutex is created successfully.
+ * @retval KOSA_StatusError if the mutex can not be created.
+ */
+osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle);
+
+/*!
+ * @brief Waits for a mutex and locks it.
+ *
+ * This function checks the mutex's status. If it is unlocked, locks it and returns the
+ * KOSA_StatusSuccess. Otherwise, waits for a timeout in milliseconds to lock.
+ *
+ * @param mutexHandle The mutex handle.
+ * @param millisec The maximum number of milliseconds to wait for the mutex.
+ * If the mutex is locked, Pass the value osaWaitForever_c will
+ * wait indefinitely, pass 0 will return KOSA_StatusTimeout
+ * immediately.
+ *
+ * @retval KOSA_StatusSuccess The mutex is locked successfully.
+ * @retval KOSA_StatusTimeout Timeout occurred.
+ * @retval KOSA_StatusError Incorrect parameter was passed.
+ *
+ * @note This is non-recursive mutex, a task can not try to lock the mutex it has locked.
+ */
+osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec);
+
+/*!
+ * @brief Unlocks a previously locked mutex.
+ *
+ * @param mutexHandle The mutex handle.
+ *
+ * @retval KOSA_StatusSuccess The mutex is successfully unlocked.
+ * @retval KOSA_StatusError The mutex can not be unlocked or invalid parameter.
+ */
+osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle);
+
+/*!
+ * @brief Destroys a previously created mutex.
+ *
+ * @param mutexHandle The mutex handle.
+ *
+ * @retval KOSA_StatusSuccess The mutex is successfully destroyed.
+ * @retval KOSA_StatusError The mutex can not be destroyed.
+ *
+ */
+osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle);
+
+/*!
+ * @brief Initializes an event object with all flags cleared.
+ *
+ * This function creates an event object and set its clear mode. If autoClear
+ * is 1, when a task gets the event flags, these flags will be
+ * cleared automatically. Otherwise these flags must
+ * be cleared manually.
+ *
+ * Example below shows how to use this API to create the event handle.
+ * @code
+ * OSA_EVENT_HANDLE_DEFINE(eventHandle);
+ * OSA_EventCreate((osa_event_handle_t)eventHandle, 0);
+ * @endcode
+ *
+ * @param eventHandle Pointer to a memory space of size OSA_EVENT_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_EVENT_HANDLE_DEFINE(eventHandle);
+ * or
+ * uint32_t eventHandle[((OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param autoClear 1 The event is auto-clear.
+ * 0 The event manual-clear
+ * @retval KOSA_StatusSuccess the new event if the event is created successfully.
+ * @retval KOSA_StatusError if the event can not be created.
+ */
+osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear);
+
+/*!
+ * @brief Sets one or more event flags.
+ *
+ * Sets specified flags of an event object.
+ *
+ * @param eventHandle The event handle.
+ * @param flagsToSet Flags to be set.
+ *
+ * @retval KOSA_StatusSuccess The flags were successfully set.
+ * @retval KOSA_StatusError An incorrect parameter was passed.
+ */
+osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet);
+
+/*!
+ * @brief Clears one or more flags.
+ *
+ * Clears specified flags of an event object.
+ *
+ * @param eventHandle The event handle.
+ * @param flagsToClear Flags to be clear.
+ *
+ * @retval KOSA_StatusSuccess The flags were successfully cleared.
+ * @retval KOSA_StatusError An incorrect parameter was passed.
+ */
+osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear);
+
+/*!
+ * @brief Get event's flags.
+ *
+ * Get specified flags of an event object.
+ *
+ * @param eventHandle The event handle.
+ * The macro EVENT_HANDLE_BUFFER_GET is used to get the event buffer pointer,
+ * and should not be used before the macro EVENT_HANDLE_BUFFER_DEFINE is used.
+ * @param flagsMask The flags user want to get are specified by this parameter.
+ * @param pFlagsOfEvent The event flags are obtained by this parameter.
+ *
+ * @retval KOSA_StatusSuccess The event flags were successfully got.
+ * @retval KOSA_StatusError An incorrect parameter was passed.
+ */
+osa_status_t OSA_EventGet(osa_event_handle_t eventHandle,
+ osa_event_flags_t flagsMask,
+ osa_event_flags_t *pFlagsOfEvent);
+
+/*!
+ * @brief Waits for specified event flags to be set.
+ *
+ * This function waits for a combination of flags to be set in an event object.
+ * Applications can wait for any/all bits to be set. Also this function could
+ * obtain the flags who wakeup the waiting task.
+ *
+ * @param eventHandle The event handle.
+ * @param flagsToWait Flags that to wait.
+ * @param waitAll Wait all flags or any flag to be set.
+ * @param millisec The maximum number of milliseconds to wait for the event.
+ * If the wait condition is not met, pass osaWaitForever_c will
+ * wait indefinitely, pass 0 will return KOSA_StatusTimeout
+ * immediately.
+ * @param pSetFlags Flags that wakeup the waiting task are obtained by this parameter.
+ *
+ * @retval KOSA_StatusSuccess The wait condition met and function returns successfully.
+ * @retval KOSA_StatusTimeout Has not met wait condition within timeout.
+ * @retval KOSA_StatusError An incorrect parameter was passed.
+
+ *
+ * @note Please pay attention to the flags bit width, FreeRTOS uses the most
+ * significant 8 bis as control bits, so do not wait these bits while using
+ * FreeRTOS.
+ *
+ */
+osa_status_t OSA_EventWait(osa_event_handle_t eventHandle,
+ osa_event_flags_t flagsToWait,
+ uint8_t waitAll,
+ uint32_t millisec,
+ osa_event_flags_t *pSetFlags);
+
+/*!
+ * @brief Destroys a previously created event object.
+ *
+ * @param eventHandle The event handle.
+ *
+ * @retval KOSA_StatusSuccess The event is successfully destroyed.
+ * @retval KOSA_StatusError Event destruction failed.
+ */
+osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle);
+
+/*!
+ * @brief Initializes a message queue.
+ *
+ * This function allocates memory for and initializes a message queue. Message queue elements are hardcoded as void*.
+ *
+ * Example below shows how to use this API to create the massage queue handle.
+ * @code
+ * OSA_MSGQ_HANDLE_DEFINE(msgqHandle);
+ * OSA_MsgQCreate((osa_msgq_handle_t)msgqHandle, 5U, sizeof(msg));
+ * @endcode
+ *
+ * @param msgqHandle Pointer to a memory space of size #(OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize) on bare-matel
+ * and #(OSA_MSGQ_HANDLE_SIZE) on FreeRTOS allocated by the caller, message queue handle.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_MSGQ_HANDLE_DEFINE(msgqHandle);
+ * or
+ * For bm: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * For freertos: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param msgNo :number of messages the message queue should accommodate.
+ * @param msgSize :size of a single message structure.
+ *
+ * @retval KOSA_StatusSuccess Message queue successfully Create.
+ * @retval KOSA_StatusError Message queue create failure.
+ */
+osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize);
+
+/*!
+ * @brief Puts a message at the end of the queue.
+ *
+ * This function puts a message to the end of the message queue. If the queue
+ * is full, this function returns the KOSA_StatusError;
+ *
+ * @param msgqHandle Message Queue handler.
+ * @param pMessage Pointer to the message to be put into the queue.
+ *
+ * @retval KOSA_StatusSuccess Message successfully put into the queue.
+ * @retval KOSA_StatusError The queue was full or an invalid parameter was passed.
+ */
+osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage);
+
+/*!
+ * @brief Reads and remove a message at the head of the queue.
+ *
+ * This function gets a message from the head of the message queue. If the
+ * queue is empty, timeout is used to wait.
+ *
+ * @param msgqHandle Message Queue handler.
+ * @param pMessage Pointer to a memory to save the message.
+ * @param millisec The number of milliseconds to wait for a message. If the
+ * queue is empty, pass osaWaitForever_c will wait indefinitely,
+ * pass 0 will return KOSA_StatusTimeout immediately.
+ *
+ * @retval KOSA_StatusSuccess Message successfully obtained from the queue.
+ * @retval KOSA_StatusTimeout The queue remains empty after timeout.
+ * @retval KOSA_StatusError Invalid parameter.
+ */
+osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec);
+
+/*!
+ * @brief Get the available message
+ *
+ * This function is used to get the available message.
+ *
+ * @param msgqHandle Message Queue handler.
+ *
+ * @return Available message count
+ */
+int OSA_MsgQAvailableMsgs(osa_msgq_handle_t msgqHandle);
+
+/*!
+ * @brief Destroys a previously created queue.
+ *
+ * @param msgqHandle Message Queue handler.
+ *
+ * @retval KOSA_StatusSuccess The queue was successfully destroyed.
+ * @retval KOSA_StatusError Message queue destruction failed.
+ */
+osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle);
+
+/*!
+ * @brief Enable all interrupts.
+ */
+void OSA_InterruptEnable(void);
+
+/*!
+ * @brief Disable all interrupts.
+ */
+void OSA_InterruptDisable(void);
+
+/*!
+ * @brief Enable all interrupts using PRIMASK.
+ */
+void OSA_EnableIRQGlobal(void);
+
+/*!
+ * @brief Disable all interrupts using PRIMASK.
+ */
+void OSA_DisableIRQGlobal(void);
+
+/*!
+ * @brief Delays execution for a number of milliseconds.
+ *
+ * @param millisec The time in milliseconds to wait.
+ */
+void OSA_TimeDelay(uint32_t millisec);
+
+/*!
+ * @brief This function gets current time in milliseconds.
+ *
+ * @retval current time in milliseconds
+ */
+uint32_t OSA_TimeGetMsec(void);
+
+/*!
+ * @brief Installs the interrupt handler.
+ *
+ * @param IRQNumber IRQ number of the interrupt.
+ * @param handler The interrupt handler to install.
+ */
+void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void));
+
+/*! @}*/
+#ifdef __cplusplus
+}
+#endif
+/*! @}*/
+#endif
diff --git a/minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction_bm.c b/minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction_bm.c
new file mode 100644
index 000000000..007cb55a0
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction_bm.c
@@ -0,0 +1,1346 @@
+/*!
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ *
+ *
+ * This is the source file for the OS Abstraction layer for MQXLite.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Include
+*************************************************************************************
+********************************************************************************** */
+#include "fsl_component_generic_list.h"
+#include "fsl_os_abstraction.h"
+#include "fsl_os_abstraction_bm.h"
+#include <string.h>
+
+/*! *********************************************************************************
+*************************************************************************************
+* Private macros
+*************************************************************************************
+********************************************************************************** */
+
+/* Weak function. */
+#if defined(__GNUC__)
+#define __WEAK_FUNC __attribute__((weak))
+#elif defined(__ICCARM__)
+#define __WEAK_FUNC __weak
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#define __WEAK_FUNC __attribute__((weak))
+#endif
+
+#ifdef DEBUG_ASSERT
+#define OS_ASSERT(condition) \
+ if (!(condition)) \
+ while (1) \
+ ;
+#else
+#define OS_ASSERT(condition) (void)(condition);
+#endif
+
+/************************************************************************************
+*************************************************************************************
+* Private type definitions
+*************************************************************************************
+************************************************************************************/
+
+/*! @brief Type for an semaphore */
+typedef struct Semaphore
+{
+#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U))
+ uint32_t time_start; /*!< The time to start timeout */
+ uint32_t timeout; /*!< Timeout to wait in milliseconds */
+#endif
+ volatile uint8_t isWaiting; /*!< Is any task waiting for a timeout on this object */
+ volatile uint8_t semCount; /*!< The count value of the object */
+
+} semaphore_t;
+
+/*! @brief Type for a mutex */
+typedef struct Mutex
+{
+#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U))
+ uint32_t time_start; /*!< The time to start timeout */
+ uint32_t timeout; /*!< Timeout to wait in milliseconds */
+#endif
+ volatile uint8_t isWaiting; /*!< Is any task waiting for a timeout on this mutex */
+ volatile uint8_t isLocked; /*!< Is the object locked or not */
+} mutex_t;
+
+#define gIdleTaskPriority_c ((task_priority_t)0)
+#define gInvalidTaskPriority_c ((task_priority_t)-1)
+
+/*! @brief Type for a task handler, returned by the OSA_TaskCreate function */
+typedef void (*task_t)(task_param_t param);
+/*! @brief Task control block for bare metal. */
+typedef struct TaskControlBlock
+{
+ list_element_t link;
+ osa_task_ptr_t p_func; /*!< Task's entry */
+ osa_task_priority_t priority; /*!< Task's priority */
+ osa_task_param_t param; /*!< Task's parameter */
+ uint8_t haveToRun; /*!< Task was signaled */
+} task_control_block_t;
+
+/*! @brief Type for a task pointer */
+typedef task_control_block_t *task_handler_t;
+
+/*! @brief Type for a task stack */
+typedef uint32_t task_stack_t;
+
+/*! @brief Type for an event object */
+typedef struct Event
+{
+ uint32_t time_start; /*!< The time to start timeout */
+ uint32_t timeout; /*!< Timeout to wait in milliseconds */
+ volatile event_flags_t flags; /*!< The flags status */
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+ task_handler_t waitingTask; /*!< Handler to the waiting task */
+#endif
+ uint8_t autoClear; /*!< Auto clear or manual clear */
+ volatile uint8_t isWaiting; /*!< Is any task waiting for a timeout on this event */
+} event_t;
+
+/*! @brief Type for a message queue */
+typedef struct MsgQueue
+{
+ volatile uint8_t isWaiting; /*!< Is any task waiting for a timeout */
+ uint32_t time_start; /*!< The time to start timeout */
+ uint32_t timeout; /*!< Timeout to wait in milliseconds */
+ uint32_t size; /*!< The size(byte) of a single message */
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+ task_handler_t waitingTask; /*!< Handler to the waiting task */
+#endif
+ uint8_t *queueMem; /*!< Points to the queue memory */
+ uint16_t number; /*!< The number of messages in the queue */
+ uint16_t max; /*!< The max number of queue messages */
+ uint16_t head; /*!< Index of the next message to be read */
+ uint16_t tail; /*!< Index of the next place to write to */
+} msg_queue_t;
+
+/*! @brief Type for a message queue handler */
+typedef msg_queue_t *msg_queue_handler_t;
+
+/*! @brief State structure for bm osa manager. */
+typedef struct _osa_state
+{
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+ list_label_t taskList;
+ task_handler_t curTaskHandler;
+#endif
+ volatile uint32_t interruptDisableCount;
+ volatile uint32_t tickCounter;
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+#if (defined(FSL_OSA_MAIN_FUNC_ENABLE) && (FSL_OSA_MAIN_FUNC_ENABLE > 0U))
+ OSA_TASK_HANDLE_DEFINE(mainTaskHandle);
+#endif
+#endif
+} osa_state_t;
+
+/*! *********************************************************************************
+*************************************************************************************
+* Private prototypes
+*************************************************************************************
+********************************************************************************** */
+__WEAK_FUNC void main_task(osa_task_param_t arg);
+__WEAK_FUNC void main_task(osa_task_param_t arg)
+{
+}
+__WEAK_FUNC void OSA_TimeInit(void);
+__WEAK_FUNC uint32_t OSA_TimeDiff(uint32_t time_start, uint32_t time_end);
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public memory declarations
+*************************************************************************************
+********************************************************************************** */
+const uint8_t gUseRtos_c = USE_RTOS; /* USE_RTOS = 0 for BareMetal and 1 for OS */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Private memory declarations
+*************************************************************************************
+********************************************************************************** */
+static osa_state_t s_osaState;
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public functions
+*************************************************************************************
+********************************************************************************** */
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MemoryAllocate
+ * Description : Reserves the requested amount of memory in bytes.
+ *
+ *END**************************************************************************/
+void *OSA_MemoryAllocate(uint32_t length)
+{
+ void *p = (void *)malloc(length);
+
+ if (NULL != p)
+ {
+ (void)memset(p, 0, length);
+ }
+
+ return p;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MemoryFree
+ * Description : Frees the memory previously reserved.
+ *
+ *END**************************************************************************/
+void OSA_MemoryFree(void *p)
+{
+ free(p);
+}
+
+void OSA_EnterCritical(uint32_t *sr)
+{
+ *sr = DisableGlobalIRQ();
+}
+
+void OSA_ExitCritical(uint32_t sr)
+{
+ EnableGlobalIRQ(sr);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EnableIRQGlobal
+ * Description : Disable system interrupt.
+ *
+ *END**************************************************************************/
+void OSA_EnableIRQGlobal(void)
+{
+ if (s_osaState.interruptDisableCount > 0U)
+ {
+ s_osaState.interruptDisableCount--;
+
+ if (0U == s_osaState.interruptDisableCount)
+ {
+ __enable_irq();
+ }
+ /* call core API to enable the global interrupt*/
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_DisableIRQGlobal
+ * Description : Disable system interrupt
+ * This function will disable the global interrupt by calling the core API
+ *
+ *END**************************************************************************/
+void OSA_DisableIRQGlobal(void)
+{
+ /* call core API to disable the global interrupt*/
+ __disable_irq();
+
+ /* update counter*/
+ s_osaState.interruptDisableCount++;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskGetCurrentHandle
+ * Description : This function is used to get current active task's handler.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_task_handle_t OSA_TaskGetCurrentHandle(void)
+{
+ return (osa_task_handle_t)s_osaState.curTaskHandler;
+}
+#endif
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EXT_TaskYield
+ * Description : When a task calls this function, it will give up CPU and put
+ * itself to the tail of ready list.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskYield(void)
+{
+ return KOSA_StatusSuccess;
+}
+#endif
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskGetPriority
+ * Description : This function returns task's priority by task handler.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle)
+{
+ assert(taskHandle);
+ task_handler_t handler = (task_handler_t)taskHandle;
+ return handler->priority;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskSetPriority
+ * Description : This function sets task's priority by task handler.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority)
+{
+ assert(taskHandle);
+ list_element_handle_t list_element;
+ task_control_block_t *tcb = NULL;
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+ task_control_block_t *preTcb = NULL;
+#endif
+ task_control_block_t *ptaskStruct = (task_control_block_t *)taskHandle;
+ uint32_t regPrimask;
+
+ ptaskStruct->priority = taskPriority;
+ (void)LIST_RemoveElement(&ptaskStruct->link);
+ /* Insert task control block into the task list. */
+ list_element = LIST_GetHead(&s_osaState.taskList);
+ while (NULL != list_element)
+ {
+ tcb = (task_control_block_t *)(void *)list_element;
+ if (ptaskStruct->priority <= tcb->priority)
+ {
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+ if (preTcb == NULL)
+ {
+ (&tcb->link)->list->head = (struct list_element_tag *)(void *)ptaskStruct;
+ }
+ else
+ {
+ (&preTcb->link)->next = (struct list_element_tag *)(void *)ptaskStruct;
+ }
+ (&ptaskStruct->link)->list = (&tcb->link)->list;
+ (&ptaskStruct->link)->next = (struct list_element_tag *)(void *)tcb;
+ (&ptaskStruct->link)->list->size++;
+#else
+ (void)LIST_AddPrevElement(&tcb->link, &ptaskStruct->link);
+#endif
+ break;
+ }
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+ preTcb = tcb;
+#endif
+ list_element = LIST_GetNext(list_element);
+ }
+ if (ptaskStruct->priority > tcb->priority)
+ {
+ OSA_EnterCritical(®Primask);
+ (void)LIST_AddTail(&s_osaState.taskList, (list_element_handle_t)(void *)&(ptaskStruct->link));
+ OSA_ExitCritical(regPrimask);
+ }
+
+ return KOSA_StatusSuccess;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskCreate
+ * Description : This function is used to create a task and make it ready.
+ * Param[in] : threadDef - Definition of the thread.
+ * task_param - Parameter to pass to the new thread.
+ * Return Thread handle of the new thread, or NULL if failed.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, const osa_task_def_t *thread_def, osa_task_param_t task_param)
+{
+ list_element_handle_t list_element;
+
+ task_control_block_t *tcb = NULL;
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+ task_control_block_t *preTcb = NULL;
+#endif
+ list_status_t listStatus;
+
+ task_control_block_t *ptaskStruct = (task_control_block_t *)taskHandle;
+ uint32_t regPrimask;
+ assert(sizeof(task_control_block_t) == OSA_TASK_HANDLE_SIZE);
+ assert(taskHandle);
+
+ ptaskStruct->p_func = thread_def->pthread;
+ ptaskStruct->haveToRun = 1U;
+ ptaskStruct->priority = (uint16_t)PRIORITY_OSA_TO_RTOS(thread_def->tpriority);
+ ptaskStruct->param = task_param;
+
+ list_element = LIST_GetHead(&s_osaState.taskList);
+ while (NULL != list_element)
+ {
+ tcb = (task_control_block_t *)(void *)list_element;
+ if (ptaskStruct->priority <= tcb->priority)
+ {
+ OSA_EnterCritical(®Primask);
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+ if (preTcb == NULL)
+ {
+ (&tcb->link)->list->head = (struct list_element_tag *)(void *)ptaskStruct;
+ }
+ else
+ {
+ (&preTcb->link)->next = (struct list_element_tag *)(void *)ptaskStruct;
+ }
+ (&ptaskStruct->link)->list = (&tcb->link)->list;
+ (&ptaskStruct->link)->next = (struct list_element_tag *)(void *)tcb;
+ (&ptaskStruct->link)->list->size++;
+ OSA_ExitCritical(regPrimask);
+ return KOSA_StatusSuccess;
+#else
+ listStatus = LIST_AddPrevElement(&tcb->link, &ptaskStruct->link);
+ OSA_ExitCritical(regPrimask);
+ if (listStatus == (list_status_t)kLIST_DuplicateError)
+ {
+ return KOSA_StatusError;
+ }
+ break;
+#endif
+ }
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+ preTcb = tcb;
+#endif
+ list_element = LIST_GetNext(list_element);
+ }
+
+ if ((NULL == tcb) || (ptaskStruct->priority > tcb->priority))
+ {
+ OSA_EnterCritical(®Primask);
+ listStatus = LIST_AddTail(&s_osaState.taskList, (list_element_handle_t)(void *)&(ptaskStruct->link));
+ (void)listStatus;
+ assert(listStatus == kLIST_Ok);
+ OSA_ExitCritical(regPrimask);
+ }
+
+ return KOSA_StatusSuccess;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskDestroy
+ * Description : This function destroy a task.
+ * Param[in] :taskHandle - Thread handle.
+ * Return KOSA_StatusSuccess if the task is destroied, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle)
+{
+ uint32_t regPrimask;
+ assert(taskHandle);
+
+ OSA_EnterCritical(®Primask);
+ (void)LIST_RemoveElement(taskHandle);
+ OSA_ExitCritical(regPrimask);
+ return KOSA_StatusSuccess;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TimeInit
+ * Description : This function initializes the timer used in BM OSA, the
+ * functions such as OSA_TimeDelay, OSA_TimeGetMsec, and the timeout are all
+ * based on this timer.
+ *
+ *END**************************************************************************/
+__WEAK_FUNC void OSA_TimeInit(void)
+{
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+ SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk);
+ SysTick->LOAD = (uint32_t)(SystemCoreClock / 1000U - 1U);
+ SysTick->VAL = 0;
+ SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_CLKSOURCE_Msk;
+#endif
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TimeDiff
+ * Description : This function gets the difference between two time stamp,
+ * time overflow is considered.
+ *
+ *END**************************************************************************/
+__WEAK_FUNC uint32_t OSA_TimeDiff(uint32_t time_start, uint32_t time_end)
+{
+ if (time_end >= time_start)
+ {
+ return time_end - time_start;
+ }
+ else
+ {
+ return FSL_OSA_TIME_RANGE - time_start + time_end + 1UL;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA__TimeDelay
+ * Description : This function is used to suspend the active thread for the given number of milliseconds.
+ *
+ *END**************************************************************************/
+void OSA_TimeDelay(uint32_t millisec)
+{
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+ uint32_t currTime, timeStart;
+
+ timeStart = OSA_TimeGetMsec();
+
+ do
+ {
+ currTime = OSA_TimeGetMsec(); /* Get current time stamp */
+ } while (millisec >= OSA_TimeDiff(timeStart, currTime));
+#endif
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TimeGetMsec
+ * Description : This function gets current time in milliseconds.
+ *
+ *END**************************************************************************/
+__WEAK_FUNC uint32_t OSA_TimeGetMsec(void)
+{
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+ return s_osaState.tickCounter;
+#else
+ return 0;
+#endif
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphoreCreate
+ * Description : This function is used to create a semaphore.
+ * Return : Semaphore handle of the new semaphore, or NULL if failed.
+ *
+ *END**************************************************************************/
+
+osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue)
+{
+ semaphore_t *pSemStruct = (semaphore_t *)semaphoreHandle;
+ assert(sizeof(semaphore_t) <= OSA_SEM_HANDLE_SIZE);
+ assert(semaphoreHandle);
+
+ pSemStruct->semCount = (uint8_t)initValue;
+ pSemStruct->isWaiting = 0U;
+#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U))
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+
+ pSemStruct->time_start = 0U;
+ pSemStruct->timeout = 0U;
+#endif
+#endif
+ return KOSA_StatusSuccess;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphoreDestroy
+ * Description : This function is used to destroy a semaphore.
+ * Return : KOSA_StatusSuccess if the semaphore is destroyed successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle)
+{
+ assert(semaphoreHandle);
+ semaphore_t *pSemStruct = (semaphore_t *)semaphoreHandle;
+
+ /* Destroy semaphoreHandle's data */
+ (void)memset(pSemStruct, 0, sizeof(semaphore_t));
+
+ return KOSA_StatusSuccess;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphoreWait
+ * Description : This function checks the semaphore's counting value, if it is
+ * positive, decreases it and returns KOSA_StatusSuccess, otherwise, timeout
+ * will be used for wait. The parameter timeout indicates how long should wait
+ * in milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will
+ * return KOSA_StatusTimeout immediately if semaphore is not positive.
+ * This function returns KOSA_StatusSuccess if the semaphore is received, returns
+ * KOSA_StatusTimeout if the semaphore is not received within the specified
+ * 'timeout', returns KOSA_StatusError if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec)
+{
+ semaphore_t *pSemStruct = (semaphore_t *)semaphoreHandle;
+ uint32_t regPrimask;
+ assert(semaphoreHandle);
+#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U))
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+ uint32_t currentTime;
+#endif
+#endif
+ /* Check the sem count first. Deal with timeout only if not already set */
+
+ if (0U != pSemStruct->semCount)
+ {
+ OSA_EnterCritical(®Primask);
+ pSemStruct->semCount--;
+ pSemStruct->isWaiting = 0U;
+ OSA_ExitCritical(regPrimask);
+ return KOSA_StatusSuccess;
+ }
+ else
+ {
+ if (0U == millisec)
+ {
+ /* If timeout is 0 and semaphore is not available, return kStatus_OSA_Timeout. */
+ return KOSA_StatusTimeout;
+ }
+#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U))
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+ else if (0U != pSemStruct->isWaiting)
+ {
+ /* Check for timeout */
+ currentTime = OSA_TimeGetMsec();
+ if (pSemStruct->timeout < OSA_TimeDiff(pSemStruct->time_start, currentTime))
+ {
+ OSA_EnterCritical(®Primask);
+ pSemStruct->isWaiting = 0U;
+ OSA_ExitCritical(regPrimask);
+ return KOSA_StatusTimeout;
+ }
+ }
+ else if (millisec != osaWaitForever_c) /* If don't wait forever, start the timer */
+ {
+ /* Start the timeout counter */
+ OSA_EnterCritical(®Primask);
+ pSemStruct->isWaiting = 1U;
+ OSA_ExitCritical(regPrimask);
+ pSemStruct->time_start = OSA_TimeGetMsec();
+ pSemStruct->timeout = millisec;
+ }
+#endif
+#endif
+ else
+ {
+ ;
+ }
+ }
+
+ return KOSA_StatusIdle;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphorePost
+ * Description : This function is used to wake up one task that wating on the
+ * semaphore. If no task is waiting, increase the semaphore. The function returns
+ * KOSA_StatusSuccess if the semaphre is post successfully, otherwise returns
+ * KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle)
+{
+ semaphore_t *pSemStruct = (semaphore_t *)semaphoreHandle;
+ uint32_t regPrimask;
+ assert(semaphoreHandle);
+
+ /* The max value is 0xFF */
+ if (0xFFU == pSemStruct->semCount)
+ {
+ return KOSA_StatusError;
+ }
+ OSA_EnterCritical(®Primask);
+ ++pSemStruct->semCount;
+ OSA_ExitCritical(regPrimask);
+
+ return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexCreate
+ * Description : This function is used to create a mutex.
+ * Return : Mutex handle of the new mutex, or NULL if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle)
+{
+ mutex_t *pMutexStruct = (mutex_t *)mutexHandle;
+ assert(sizeof(mutex_t) <= OSA_MUTEX_HANDLE_SIZE);
+ assert(mutexHandle);
+
+ pMutexStruct->isLocked = 0U;
+ pMutexStruct->isWaiting = 0U;
+#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U))
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+
+ pMutexStruct->time_start = 0u;
+ pMutexStruct->timeout = 0u;
+#endif
+#endif
+ return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexLock
+ * Description : This function checks the mutex's status, if it is unlocked,
+ * lock it and returns KOSA_StatusSuccess, otherwise, wait for the mutex.
+ * MQX does not support timeout to wait for a mutex.
+ * This function returns KOSA_StatusSuccess if the mutex is obtained, returns
+ * KOSA_StatusError if any errors occur during waiting. If the mutex has been
+ * locked, pass 0 as timeout will return KOSA_StatusTimeout immediately.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec)
+{
+#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U))
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+ uint32_t currentTime;
+#endif
+#endif
+ mutex_t *pMutexStruct = (mutex_t *)mutexHandle;
+ uint32_t regPrimask;
+
+ /* Always check first. Deal with timeout only if not available. */
+ if (0U == pMutexStruct->isLocked)
+ {
+ /* Get the lock and return success */
+ OSA_EnterCritical(®Primask);
+ pMutexStruct->isLocked = 1U;
+ pMutexStruct->isWaiting = 0U;
+ OSA_ExitCritical(regPrimask);
+ return KOSA_StatusSuccess;
+ }
+ else
+ {
+ if (0U == millisec)
+ {
+ /* If timeout is 0 and mutex is not available, return kStatus_OSA_Timeout. */
+ return KOSA_StatusTimeout;
+ }
+#if (defined(FSL_OSA_BM_TIMEOUT_ENABLE) && (FSL_OSA_BM_TIMEOUT_ENABLE > 0U))
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+ else if (pMutexStruct->isWaiting != 0U)
+ {
+ /* Check for timeout */
+ currentTime = OSA_TimeGetMsec();
+ if (pMutexStruct->timeout < OSA_TimeDiff(pMutexStruct->time_start, currentTime))
+ {
+ OSA_EnterCritical(®Primask);
+ pMutexStruct->isWaiting = 0U;
+ OSA_ExitCritical(regPrimask);
+ return KOSA_StatusTimeout;
+ }
+ }
+ else if (millisec != osaWaitForever_c) /* If dont't wait forever, start timer. */
+ {
+ /* Start the timeout counter */
+ OSA_EnterCritical(®Primask);
+ pMutexStruct->isWaiting = 1U;
+ OSA_ExitCritical(regPrimask);
+ pMutexStruct->time_start = OSA_TimeGetMsec();
+ pMutexStruct->timeout = millisec;
+ }
+#endif
+#endif
+ else
+ {
+ ;
+ }
+ }
+
+ return KOSA_StatusIdle;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexUnlock
+ * Description : This function is used to unlock a mutex.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle)
+{
+ mutex_t *pMutexStruct = (mutex_t *)mutexHandle;
+ uint32_t regPrimask;
+ assert(mutexHandle);
+
+ OSA_EnterCritical(®Primask);
+ pMutexStruct->isLocked = 0U;
+ OSA_ExitCritical(regPrimask);
+ return KOSA_StatusSuccess;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexDestroy
+ * Description : This function is used to destroy a mutex.
+ * Return : KOSA_StatusSuccess if the lock object is destroyed successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle)
+{
+ assert(mutexHandle);
+ mutex_t *pMutexStruct = (mutex_t *)mutexHandle;
+
+ /* Destory mutexHandle's data */
+ (void)memset(pMutexStruct, 0, sizeof(mutex_t));
+
+ return KOSA_StatusSuccess;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventCreate
+ * Description : This function is used to create a event object.
+ * Return : Event handle of the new event, or NULL if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear)
+{
+ event_t *pEventStruct = eventHandle;
+ assert(sizeof(event_t) == OSA_EVENT_HANDLE_SIZE);
+ assert(eventHandle);
+
+ pEventStruct->isWaiting = 0U;
+ pEventStruct->flags = 0;
+ pEventStruct->autoClear = autoClear;
+ pEventStruct->time_start = 0u;
+ pEventStruct->timeout = 0u;
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+ pEventStruct->waitingTask = NULL;
+#endif
+ return KOSA_StatusSuccess;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventSet
+ * Description : Set one or more event flags of an event object.
+ * Return : KOSA_StatusSuccess if set successfully, KOSA_StatusError if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet)
+{
+ event_t *pEventStruct;
+ uint32_t regPrimask;
+ pEventStruct = (event_t *)eventHandle;
+ /* Set flags ensuring atomic operation */
+ OSA_EnterCritical(®Primask);
+ pEventStruct->flags |= flagsToSet;
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+ if (pEventStruct->waitingTask != NULL)
+ {
+ pEventStruct->waitingTask->haveToRun = 1U;
+ }
+#endif
+ OSA_ExitCritical(regPrimask);
+
+ return KOSA_StatusSuccess;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventClear
+ * Description : Clear one or more event flags of an event object.
+ * Return :KOSA_StatusSuccess if clear successfully, KOSA_StatusError if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear)
+{
+ event_t *pEventStruct;
+ uint32_t regPrimask;
+ pEventStruct = (event_t *)eventHandle;
+ /* Clear flags ensuring atomic operation */
+ OSA_EnterCritical(®Primask);
+ pEventStruct->flags &= ~flagsToClear;
+ if (0U != pEventStruct->flags)
+ {
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+ if (NULL != pEventStruct->waitingTask)
+ {
+ pEventStruct->waitingTask->haveToRun = 1U;
+ }
+#endif
+ }
+ OSA_ExitCritical(regPrimask);
+
+ return KOSA_StatusSuccess;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventGet
+ * Description : This function is used to get event's flags that specified by prameter
+ * flagsMask, and the flags (user specified) are obatianed by parameter pFlagsOfEvent. So
+ * you should pass the parameter 0xffffffff to specify you want to get all.
+ * Return :KOSA_StatusSuccess if event flags were successfully got, KOSA_StatusError if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventGet(osa_event_handle_t eventHandle, osa_event_flags_t flagsMask, osa_event_flags_t *pFlagsOfEvent)
+{
+ event_t *pEventStruct;
+ pEventStruct = (event_t *)eventHandle;
+ OSA_SR_ALLOC();
+
+ if (NULL == pFlagsOfEvent)
+ {
+ return KOSA_StatusError;
+ }
+
+ OSA_ENTER_CRITICAL();
+ *pFlagsOfEvent = pEventStruct->flags & flagsMask;
+ OSA_EXIT_CRITICAL();
+
+ return KOSA_StatusSuccess;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventWait
+ * Description : This function checks the event's status, if it meets the wait
+ * condition, return KOSA_StatusSuccess, otherwise, timeout will be used for
+ * wait. The parameter timeout indicates how long should wait in milliseconds.
+ * Pass osaWaitForever_c to wait indefinitely, pass 0 will return the value
+ * KOSA_StatusTimeout immediately if wait condition is not met. The event flags
+ * will be cleared if the event is auto clear mode. Flags that wakeup waiting
+ * task could be obtained from the parameter setFlags.
+ * This function returns KOSA_StatusSuccess if wait condition is met, returns
+ * KOSA_StatusTimeout if wait condition is not met within the specified
+ * 'timeout', returns KOSA_StatusError if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventWait(osa_event_handle_t eventHandle,
+ osa_event_flags_t flagsToWait,
+ uint8_t waitAll,
+ uint32_t millisec,
+ osa_event_flags_t *pSetFlags)
+{
+ event_t *pEventStruct;
+ uint32_t regPrimask;
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+ uint32_t currentTime;
+#endif
+ osa_status_t retVal = KOSA_StatusIdle;
+ if (NULL == pSetFlags)
+ {
+ return KOSA_StatusError;
+ }
+
+ pEventStruct = (event_t *)eventHandle;
+
+ OSA_EnterCritical(®Primask);
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+#if (TASK_MAX_NUM > 0)
+ pEventStruct->waitingTask = OSA_TaskGetCurrentHandle();
+#endif
+#endif
+
+ *pSetFlags = pEventStruct->flags & flagsToWait;
+
+ /* Check the event flag first, if does not meet wait condition, deal with timeout. */
+ if (((0U == waitAll) && (0U != *pSetFlags)) || (*pSetFlags == flagsToWait))
+ {
+ pEventStruct->isWaiting = 0U;
+ if (1U == pEventStruct->autoClear)
+ {
+ pEventStruct->flags &= ~flagsToWait;
+ }
+ retVal = KOSA_StatusSuccess;
+ }
+ else
+ {
+ if (0U == millisec)
+ {
+ /* If timeout is 0 and wait condition is not met, return kStatus_OSA_Timeout. */
+ retVal = KOSA_StatusTimeout;
+ }
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+ else if (0U != pEventStruct->isWaiting)
+ {
+ /* Check for timeout */
+ currentTime = OSA_TimeGetMsec();
+ if (pEventStruct->timeout < OSA_TimeDiff(pEventStruct->time_start, currentTime))
+ {
+ pEventStruct->isWaiting = 0U;
+ retVal = KOSA_StatusTimeout;
+ }
+ }
+ else if (millisec != osaWaitForever_c) /* If no timeout, don't start the timer */
+ {
+ /* Start the timeout counter */
+ pEventStruct->isWaiting = 1U;
+ pEventStruct->time_start = OSA_TimeGetMsec();
+ pEventStruct->timeout = millisec;
+ }
+#endif
+ else
+ {
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+ pEventStruct->waitingTask->haveToRun = 0U;
+#endif
+ }
+ }
+
+ OSA_ExitCritical(regPrimask);
+
+ return retVal;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventDestroy
+ * Description : This function is used to destroy a event object. Return
+ * KOSA_StatusSuccess if the event object is destroyed successfully, otherwise
+ * return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle)
+{
+ assert(eventHandle);
+ event_t *pEventStruct = (event_t *)eventHandle;
+
+ /* Destroy eventHandle's data */
+ (void)memset(pEventStruct, 0, sizeof(event_t));
+
+ return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQCreate
+ * Description : This function is used to create a message queue.
+ * Return : the handle to the message queue if create successfully, otherwise
+ * return NULL.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize)
+{
+ msg_queue_t *pMsgQStruct = msgqHandle;
+ assert(sizeof(msg_queue_t) == OSA_MSGQ_HANDLE_SIZE);
+ assert(msgqHandle);
+
+ pMsgQStruct->max = (uint16_t)msgNo;
+ pMsgQStruct->number = 0;
+ pMsgQStruct->head = 0;
+ pMsgQStruct->tail = 0;
+ pMsgQStruct->size = msgSize;
+ pMsgQStruct->queueMem = (uint8_t *)((uint8_t *)msgqHandle + sizeof(msg_queue_t));
+ return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQPut
+ * Description : This function is used to put a message to a message queue.
+ * Return : KOSA_StatusSuccess if the message is put successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage)
+{
+ assert(msgqHandle);
+ msg_queue_t *pQueue;
+ osa_status_t status = KOSA_StatusSuccess;
+ uint32_t regPrimask;
+
+ uint8_t *pMsgArray;
+
+ pQueue = (msg_queue_t *)msgqHandle;
+
+ if (NULL == pQueue->queueMem)
+ {
+ return KOSA_StatusError;
+ }
+
+ OSA_EnterCritical(®Primask);
+ if (pQueue->number >= pQueue->max)
+ {
+ status = KOSA_StatusError;
+ }
+ else
+ {
+ pMsgArray = &pQueue->queueMem[pQueue->tail];
+ for (uint32_t i = 0; i < pQueue->size; i++)
+ {
+ pMsgArray[i] = *((uint8_t *)pMessage + i);
+ }
+
+ pQueue->number++;
+ pQueue->tail += (uint16_t)pQueue->size;
+
+ if (pQueue->tail >= (pQueue->max * pQueue->size))
+ {
+ pQueue->tail = 0;
+ }
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+ if (NULL != pQueue->waitingTask)
+ {
+ pQueue->waitingTask->haveToRun = 1U;
+ }
+#endif
+ }
+ OSA_ExitCritical(regPrimask);
+ return status;
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQGet
+ * Description : This function checks the queue's status, if it is not empty,
+ * get message from it and return KOSA_StatusSuccess, otherwise, timeout will
+ * be used for wait. The parameter timeout indicates how long should wait in
+ * milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will return
+ * KOSA_StatusTimeout immediately if queue is empty.
+ * This function returns KOSA_StatusSuccess if message is got successfully,
+ * returns KOSA_StatusTimeout if message queue is empty within the specified
+ * 'timeout', returns KOSA_StatusError if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec)
+{
+ assert(msgqHandle);
+ msg_queue_t *pQueue;
+ osa_status_t status = KOSA_StatusSuccess;
+ uint32_t regPrimask;
+
+ uint8_t *pMsgArray;
+
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+ uint32_t currentTime;
+#endif
+
+ pQueue = (msg_queue_t *)msgqHandle;
+
+ if (NULL == pQueue->queueMem)
+ {
+ return KOSA_StatusError;
+ }
+
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+ pQueue->waitingTask = OSA_TaskGetCurrentHandle();
+#endif
+
+ OSA_EnterCritical(®Primask);
+ if (0U != pQueue->number)
+ {
+ pMsgArray = (uint8_t *)pMessage;
+ for (uint32_t i = 0; i < pQueue->size; i++)
+ {
+ pMsgArray[i] = pQueue->queueMem[pQueue->head + i];
+ }
+
+ pQueue->number--;
+ pQueue->head += (uint16_t)pQueue->size;
+ pQueue->isWaiting = 0U;
+
+ if (pQueue->head >= (pQueue->max * pQueue->size))
+ {
+ pQueue->head = 0;
+ }
+ status = KOSA_StatusSuccess;
+ }
+ else
+ {
+ if (0U == millisec)
+ {
+ /* If timeout is 0 and wait condition is not met, return kStatus_OSA_Timeout. */
+ status = KOSA_StatusTimeout;
+ }
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+ else if (0U != pQueue->isWaiting)
+ {
+ /* Check for timeout */
+ status = KOSA_StatusIdle; /* Before a timeout, the status should be idle. */
+ currentTime = OSA_TimeGetMsec();
+ if (pQueue->timeout < OSA_TimeDiff(pQueue->time_start, currentTime))
+ {
+ pQueue->isWaiting = 0U;
+ status = KOSA_StatusTimeout;
+ }
+ }
+ else if (millisec != osaWaitForever_c) /* If no timeout, don't start the timer */
+ {
+ /* Start the timeout counter */
+ pQueue->isWaiting = 1U;
+ pQueue->time_start = OSA_TimeGetMsec();
+ pQueue->timeout = millisec;
+ status = KOSA_StatusIdle;
+ }
+#endif
+ else
+ {
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+ pQueue->waitingTask->haveToRun = 0U;
+#endif
+ status = KOSA_StatusIdle;
+ }
+ }
+ OSA_ExitCritical(regPrimask);
+
+ return status;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQAvailableMsgs
+ * Description : This function is used to get the available message.
+ * Return : Available message count
+ *
+ *END**************************************************************************/
+int OSA_MsgQAvailableMsgs(osa_msgq_handle_t msgqHandle)
+{
+ assert(msgqHandle);
+ msg_queue_t *pQueue = (msg_queue_t *)msgqHandle;
+
+ return (int)pQueue->number;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EXT_MsgQDestroy
+ * Description : This function is used to destroy the message queue.
+ * Return : KOSA_StatusSuccess if the message queue is destroyed successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle)
+{
+ assert(msgqHandle);
+ msg_queue_t *pQueue = (msg_queue_t *)msgqHandle;
+
+ /* Destory msgqHandle's data */
+ /* OSA_MsgQGet() & OSA_MsgQPut() will check queueMem, if NULL will return an error. */
+ (void)memset(pQueue, 0, sizeof(msg_queue_t));
+
+ return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_InterruptEnable
+ * Description : self explanatory.
+ *
+ *END**************************************************************************/
+void OSA_InterruptEnable(void)
+{
+ OSA_EnableIRQGlobal();
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_InterruptDisable
+ * Description : self explanatory.
+ *
+ *END**************************************************************************/
+void OSA_InterruptDisable(void)
+{
+ OSA_DisableIRQGlobal();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_InstallIntHandler
+ * Description : This function is used to install interrupt handler.
+ *
+ *END**************************************************************************/
+void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void))
+{
+#if defined(__IAR_SYSTEMS_ICC__)
+ _Pragma("diag_suppress = Pm138")
+#endif
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+ (void) InstallIRQHandler((IRQn_Type)IRQNumber, (uint32_t) * (uint32_t *)&handler);
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+#if defined(__IAR_SYSTEMS_ICC__)
+ _Pragma("diag_remark = PM138")
+#endif
+}
+
+/*! *********************************************************************************
+*************************************************************************************
+* Private functions
+*************************************************************************************
+********************************************************************************** */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+#if (defined(FSL_OSA_MAIN_FUNC_ENABLE) && (FSL_OSA_MAIN_FUNC_ENABLE > 0U))
+static OSA_TASK_DEFINE(main_task, gMainThreadPriority_c, 1, gMainThreadStackSize_c, 0);
+
+void main(void)
+{
+ OSA_Init();
+
+ /* Initialize MCU clock */
+ extern void BOARD_InitHardware(void);
+ BOARD_InitHardware();
+
+ (void)OSA_TaskCreate((osa_task_handle_t)s_osaState.mainTaskHandle, OSA_TASK(main_task), NULL);
+
+ OSA_Start();
+}
+#endif /*(defined(FSL_OSA_MAIN_FUNC_ENABLE) && (FSL_OSA_MAIN_FUNC_ENABLE > 0U))*/
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_Init
+ * Description : This function is used to setup the basic services, it should
+ * be called first in function main.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+void OSA_Init(void)
+{
+ LIST_Init((&s_osaState.taskList), 0);
+ s_osaState.curTaskHandler = NULL;
+ s_osaState.interruptDisableCount = 0U;
+ s_osaState.tickCounter = 0U;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_Start
+ * Description : This function is used to start RTOS scheduler.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+void OSA_Start(void)
+{
+ list_element_handle_t list_element;
+ task_control_block_t *tcb;
+
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+ OSA_TimeInit();
+#endif
+
+ while (true)
+ {
+ list_element = LIST_GetHead(&s_osaState.taskList);
+ while (NULL != list_element)
+ {
+ tcb = (task_control_block_t *)(void *)list_element;
+ s_osaState.curTaskHandler = (osa_task_handle_t)tcb;
+ if (0U != tcb->haveToRun)
+ {
+ if (NULL != tcb->p_func)
+ {
+ tcb->p_func(tcb->param);
+ }
+ list_element = LIST_GetHead(&s_osaState.taskList);
+ }
+ else
+ {
+ list_element = LIST_GetNext(list_element);
+ }
+ }
+ }
+}
+
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : SysTick_Handler
+ * Description : This ISR of the SYSTICK timer.
+ *
+ *END**************************************************************************/
+#if (FSL_OSA_BM_TIMER_CONFIG != FSL_OSA_BM_TIMER_NONE)
+void SysTick_Handler(void);
+void SysTick_Handler(void)
+{
+ s_osaState.tickCounter++;
+}
+#endif
diff --git a/minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction_bm.h b/minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction_bm.h
new file mode 100644
index 000000000..84a5bd17a
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction_bm.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#if !defined(__FSL_OS_ABSTRACTION_BM_H__)
+#define __FSL_OS_ABSTRACTION_BM_H__
+
+/*!
+ * @addtogroup os_abstraction_bm
+ * @{
+ */
+
+/*******************************************************************************
+ * Declarations
+ ******************************************************************************/
+/*! @brief Bare Metal does not use timer. */
+#ifndef FSL_OSA_BM_TIMER_NONE
+#define FSL_OSA_BM_TIMER_NONE 0U
+#endif
+
+/*! @brief Bare Metal uses SYSTICK as timer. */
+#ifndef FSL_OSA_BM_TIMER_SYSTICK
+#define FSL_OSA_BM_TIMER_SYSTICK 1U
+#endif
+
+/*! @brief Configure what timer is used in Bare Metal. */
+#ifndef FSL_OSA_BM_TIMER_CONFIG
+#define FSL_OSA_BM_TIMER_CONFIG FSL_OSA_BM_TIMER_NONE
+#endif
+
+/*! @brief Type for task parameter */
+typedef void *task_param_t;
+
+/*! @brief Type for an event flags group, bit 32 is reserved */
+typedef uint32_t event_flags_t;
+
+/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
+#define OSA_WAIT_FOREVER 0xFFFFFFFFU
+
+/*! @brief How many tasks can the bare metal support. */
+#ifndef TASK_MAX_NUM
+#define TASK_MAX_NUM 7
+#endif
+
+/*! @brief OSA's time range in millisecond, OSA time wraps if exceeds this value. */
+#define FSL_OSA_TIME_RANGE 0xFFFFFFFFU
+
+/*! @brief The default interrupt handler installed in vector table. */
+#define OSA_DEFAULT_INT_HANDLER ((osa_int_handler_t)(&DefaultISR))
+
+/*! @brief The default interrupt handler installed in vector table. */
+extern void DefaultISR(void);
+
+/*!
+ * @name Thread management
+ * @{
+ */
+
+/*!
+ * @brief To provide unified priority for upper layer, OSA layer makes conversation.
+ */
+#define PRIORITY_OSA_TO_RTOS(osa_prio) (osa_prio)
+#define PRIORITY_RTOS_TO_OSA(rtos_prio) (rtos_prio)
+
+/*! @}*/
+/*! @}*/
+#endif /* __FSL_OS_ABSTRACTION_BM_H__ */
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction_config.h b/minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction_config.h
new file mode 100644
index 000000000..7996d93dd
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/component/osa/fsl_os_abstraction_config.h
@@ -0,0 +1,44 @@
+/*!
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_OS_ABSTRACTION_CONFIG_H_
+#define _FSL_OS_ABSTRACTION_CONFIG_H_
+
+#ifndef gMainThreadStackSize_c
+#define gMainThreadStackSize_c 1024
+#endif
+
+#ifndef gMainThreadPriority_c
+#define gMainThreadPriority_c 7
+#endif
+
+#ifndef gTaskMultipleInstancesManagement_c
+#define gTaskMultipleInstancesManagement_c 0
+#endif
+
+/*! @brief Definition to determine whether enable OSA's TASK module. */
+#ifndef OSA_USED
+#ifndef FSL_OSA_TASK_ENABLE
+#define FSL_OSA_TASK_ENABLE 0U
+#endif
+#else
+#if defined(FSL_OSA_TASK_ENABLE)
+#undef FSL_OSA_TASK_ENABLE
+#endif
+#define FSL_OSA_TASK_ENABLE 1U
+#endif /* OSA_USED */
+
+#ifndef FSL_OSA_MAIN_FUNC_ENABLE
+#define FSL_OSA_MAIN_FUNC_ENABLE 1U
+#endif
+
+#ifndef FSL_OSA_BM_TIMEOUT_ENABLE
+#define FSL_OSA_BM_TIMEOUT_ENABLE 0U
+#endif
+
+#endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/component/uart/fsl_adapter_uart.h b/minimal-examples/embedded/rt595/hello_world/project/component/uart/fsl_adapter_uart.h
new file mode 100644
index 000000000..2e432aea8
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/component/uart/fsl_adapter_uart.h
@@ -0,0 +1,834 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HAL_UART_ADAPTER_H__
+#define __HAL_UART_ADAPTER_H__
+
+#include "fsl_common.h"
+#if defined(SDK_OS_FREE_RTOS)
+#include "FreeRTOS.h"
+#endif
+
+/*!
+ * @addtogroup UART_Adapter
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#define UART_ADAPTER_NON_BLOCKING_MODE (1U)
+#else
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
+#define UART_ADAPTER_NON_BLOCKING_MODE (0U)
+#else
+#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE
+#endif
+#endif
+
+#if defined(__GIC_PRIO_BITS)
+#ifndef HAL_UART_ISR_PRIORITY
+#define HAL_UART_ISR_PRIORITY (25U)
+#endif
+#else
+#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#ifndef HAL_UART_ISR_PRIORITY
+#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#endif
+#else
+/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc.
+ * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum
+ * priority is 3 (2^2 - 1). So, the default value is 3.
+ */
+#ifndef HAL_UART_ISR_PRIORITY
+#define HAL_UART_ISR_PRIORITY (3U)
+#endif
+#endif
+#endif
+
+#ifndef HAL_UART_ADAPTER_LOWPOWER
+#define HAL_UART_ADAPTER_LOWPOWER (0U)
+#endif /* HAL_UART_ADAPTER_LOWPOWER */
+
+#ifndef HAL_UART_ADAPTER_FIFO
+#define HAL_UART_ADAPTER_FIFO (0U)
+#endif /* HAL_UART_ADAPTER_FIFO */
+
+#ifndef HAL_UART_DMA_ENABLE
+#define HAL_UART_DMA_ENABLE (0U)
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*! @brief Enable or disable master SPI DMA adapter int mode (1 - enable, 0 - disable) */
+#ifndef HAL_UART_DMA_INIT_ENABLE
+#define HAL_UART_DMA_INIT_ENABLE (0U)
+#endif /* HAL_SPI_MASTER_DMA_INIT_ENABLE */
+
+/*! @brief Definition of uart dma adapter software idleline detection timeout value in ms. */
+#ifndef HAL_UART_DMA_IDLELINE_TIMEOUT
+#define HAL_UART_DMA_IDLELINE_TIMEOUT (1U)
+#endif /* HAL_UART_DMA_IDLELINE_TIMEOUT */
+
+/*! @brief Definition of uart adapter handle size. */
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+#define HAL_UART_HANDLE_SIZE (92U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4)
+#define HAL_UART_BLOCK_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4)
+#else
+#define HAL_UART_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4)
+#endif
+
+/*! @brief Definition of uart dma adapter handle size. */
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
+#define HAL_UART_DMA_HANDLE_SIZE (124U)
+#elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
+#define HAL_UART_DMA_HANDLE_SIZE (140U)
+#else
+#error This SOC does not have DMA or EDMA available!
+#endif
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*!
+ * @brief Defines the uart handle
+ *
+ * This macro is used to define a 4 byte aligned uart handle.
+ * Then use "(hal_uart_handle_t)name" to get the uart handle.
+ *
+ * The macro should be global and could be optional. You could also define uart handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * UART_HANDLE_DEFINE(uartHandle);
+ * @endcode
+ *
+ * @param name The name string of the uart handle.
+ */
+#define UART_HANDLE_DEFINE(name) uint32_t name[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+#define UART_DMA_HANDLE_DEFINE(name) \
+ uint32_t name[((HAL_UART_DMA_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+#endif
+
+/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */
+#ifndef HAL_UART_TRANSFER_MODE
+#define HAL_UART_TRANSFER_MODE (0U)
+#endif
+
+/*! @brief The handle of uart adapter. */
+typedef void *hal_uart_handle_t;
+
+/*! @brief The handle of uart dma adapter. */
+typedef void *hal_uart_dma_handle_t;
+
+/*! @brief UART status */
+typedef enum _hal_uart_status
+{
+ kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */
+ kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */
+ kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */
+ kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */
+ kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */
+ kStatus_HAL_UartBaudrateNotSupport =
+ MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */
+ kStatus_HAL_UartProtocolError = MAKE_STATUS(
+ kStatusGroup_HAL_UART,
+ 6), /*!< Error occurs for Noise, Framing, Parity, etc.
+ For transactional transfer, The up layer needs to abort the transfer and then starts again */
+ kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */
+} hal_uart_status_t;
+
+/*! @brief UART parity mode. */
+typedef enum _hal_uart_parity_mode
+{
+ kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */
+ kHAL_UartParityEven = 0x2U, /*!< Parity even enabled */
+ kHAL_UartParityOdd = 0x3U, /*!< Parity odd enabled */
+} hal_uart_parity_mode_t;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*! @brief UART Block Mode. */
+typedef enum _hal_uart_block_mode
+{
+ kHAL_UartNonBlockMode = 0x0U, /*!< Uart NonBlock Mode */
+ kHAL_UartBlockMode = 0x1U, /*!< Uart Block Mode */
+} hal_uart_block_mode_t;
+#endif /* UART_ADAPTER_NON_BLOCKING_MODE */
+
+/*! @brief UART stop bit count. */
+typedef enum _hal_uart_stop_bit_count
+{
+ kHAL_UartOneStopBit = 0U, /*!< One stop bit */
+ kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */
+} hal_uart_stop_bit_count_t;
+
+/*! @brief UART configuration structure. */
+typedef struct _hal_uart_config
+{
+ uint32_t srcClock_Hz; /*!< Source clock */
+ uint32_t baudRate_Bps; /*!< Baud rate */
+ hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
+ hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
+ uint8_t enableRx; /*!< Enable RX */
+ uint8_t enableTx; /*!< Enable TX */
+ uint8_t enableRxRTS; /*!< Enable RX RTS */
+ uint8_t enableTxCTS; /*!< Enable TX CTS */
+ uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the
+ SOC corresponding RM.
+ Invalid instance value will cause initialization failure. */
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ hal_uart_block_mode_t mode; /*!< Uart block mode */
+#endif /* UART_ADAPTER_NON_BLOCKING_MODE */
+#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
+ uint8_t txFifoWatermark;
+ uint8_t rxFifoWatermark;
+#endif
+} hal_uart_config_t;
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+/*! @brief UART DMA status */
+typedef enum _hal_uart_dma_status
+{
+ kStatus_HAL_UartDmaSuccess = 0U,
+ kStatus_HAL_UartDmaRxIdle = (1U << 1U),
+ kStatus_HAL_UartDmaRxBusy = (1U << 2U),
+ kStatus_HAL_UartDmaTxIdle = (1U << 3U),
+ kStatus_HAL_UartDmaTxBusy = (1U << 4U),
+ kStatus_HAL_UartDmaIdleline = (1U << 5U),
+ kStatus_HAL_UartDmaError = (1U << 6U),
+} hal_uart_dma_status_t;
+
+typedef struct _dma_mux_configure_t
+{
+ union
+ {
+ struct
+ {
+ uint8_t dma_mux_instance;
+ uint32_t rx_request;
+ uint32_t tx_request;
+ } dma_dmamux_configure;
+ };
+} dma_mux_configure_t;
+typedef struct _dma_channel_mux_configure_t
+{
+ union
+ {
+ struct
+ {
+ uint32_t dma_rx_channel_mux;
+ uint32_t dma_tx_channel_mux;
+ } dma_dmamux_configure;
+ };
+} dma_channel_mux_configure_t;
+
+typedef struct _hal_uart_dma_config_t
+{
+ uint8_t uart_instance;
+ uint8_t dma_instance;
+ uint8_t rx_channel;
+ uint8_t tx_channel;
+ void *dma_mux_configure;
+ void *dma_channel_mux_configure;
+} hal_uart_dma_config_t;
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*! @brief UART transfer callback function. */
+typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam);
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+typedef struct _dma_callback_msg
+{
+ hal_uart_dma_status_t status;
+ uint8_t *data;
+ uint32_t dataSize;
+} hal_dma_callback_msg_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*hal_uart_dma_transfer_callback_t)(hal_uart_dma_handle_t handle,
+ hal_dma_callback_msg_t *msg,
+ void *callbackParam);
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*! @brief UART transfer structure. */
+typedef struct _hal_uart_transfer
+{
+ uint8_t *data; /*!< The buffer of data to be transfer.*/
+ size_t dataSize; /*!< The byte count to be transfer. */
+} hal_uart_transfer_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a UART instance with the UART handle and the user configuration structure.
+ *
+ * This function configures the UART module with user-defined settings. The user can configure the configuration
+ * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by
+ * the caller. Example below shows how to use this API to configure the UART.
+ * @code
+ * UART_HANDLE_DEFINE(g_UartHandle);
+ * hal_uart_config_t config;
+ * config.srcClock_Hz = 48000000;
+ * config.baudRate_Bps = 115200U;
+ * config.parityMode = kHAL_UartParityDisabled;
+ * config.stopBitCount = kHAL_UartOneStopBit;
+ * config.enableRx = 1;
+ * config.enableTx = 1;
+ * config.enableRxRTS = 0;
+ * config.enableTxCTS = 0;
+ * config.instance = 0;
+ * HAL_UartInit((hal_uart_handle_t)g_UartHandle, &config);
+ * @endcode
+ *
+ * @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #UART_HANDLE_DEFINE(handle);
+ * or
+ * uint32_t handle[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param config Pointer to user-defined configuration structure.
+ * @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_HAL_UartSuccess UART initialization succeed
+ */
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *config);
+
+/*!
+ * @brief Deinitializes a UART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the UART clock.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess UART de-initialization succeed
+ */
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle);
+
+/*! @}*/
+
+/*!
+ * @name Blocking bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Reads RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data, and reads data from the RX register.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function HAL_UartTransferReceiveNonBlocking
+ * cannot be used at the same time.
+ * And, the function HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_HAL_UartError An error occurred while receiving data.
+ * @retval kStatus_HAL_UartParityError A parity error occurred while receiving data.
+ * @retval kStatus_HAL_UartSuccess Successfully received all data.
+ */
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @note The function #HAL_UartSendBlocking and the function HAL_UartTransferSendNonBlocking
+ * cannot be used at the same time.
+ * And, the function HAL_UartTransferAbortSend cannot be used to abort the transmission of this function.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully sent all data.
+ */
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length);
+
+/*! @}*/
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+/*!
+ * @name Transactional
+ * @note The transactional API and the functional API cannot be used at the same time. The macro
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
+ * @{
+ */
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART module.
+ * When any status of the UART changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.
+ */
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART driver.
+ * When the new data arrives, the receive request is serviced first.
+ * When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param transfer UART transfer structure, see #hal_uart_transfer_t.
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param transfer UART transfer structure. See #hal_uart_transfer_t.
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of
+ * the function #HAL_UartReceiveBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the receiving.
+ */
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data sending.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of
+ * the function #HAL_UartSendBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle);
+
+/*! @}*/
+
+#else
+
+/*!
+ * @name Functional API with non-blocking mode.
+ * @note The functional API and the transactional API cannot be used at the same time. The macro
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
+ * @{
+ */
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART module.
+ * When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.
+ */
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART adapter.
+ * When the new data arrives, the receive request is serviced first.
+ * When all data is received, the UART adapter notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of
+ * the function #HAL_UartReceiveBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the receiving.
+ */
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data sending.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @note The function #HAL_UartAbortSend cannot be used to abort the transmission of
+ * the function #HAL_UartSendBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle);
+
+/*! @}*/
+
+#endif
+#endif
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+
+/*!
+ * @brief Initializes a UART dma instance with the UART dma handle and the user configuration structure.
+ *
+ * This function configures the UART dma module with user-defined settings. The user can configure the configuration
+ * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_DMA_HANDLE_SIZE allocated
+ * by the caller. Example below shows how to use this API to configure the UART.
+ * @code
+ *
+ * Init TimerManager, only used in UART without Idleline interrupt
+ * timer_config_t timerConfig;
+ * timerConfig.srcClock_Hz = 16000000;
+ * timerConfig.instance = 0;
+ * TM_Init(&timerConfig);
+ *
+ * Init the DMA module
+ * DMA_Init(DMA0);
+ *
+ * Define a uart dma handle
+ * UART_HANDLE_DEFINE(g_uartHandle);
+ * UART_DMA_HANDLE_DEFINE(g_UartDmaHandle);
+ *
+ * Configure uart settings
+ * hal_uart_config_t uartConfig;
+ * uartConfig.srcClock_Hz = 48000000;
+ * uartConfig.baudRate_Bps = 115200;
+ * uartConfig.parityMode = kHAL_UartParityDisabled;
+ * uartConfig.stopBitCount = kHAL_UartOneStopBit;
+ * uartConfig.enableRx = 1;
+ * uartConfig.enableTx = 1;
+ * uartConfig.enableRxRTS = 0;
+ * uartConfig.enableTxCTS = 0;
+ * uartConfig.instance = 0;
+ *
+ * Init uart
+ * HAL_UartInit((hal_uart_handle_t *)g_uartHandle, &uartConfig);
+ *
+ * Configure uart dma settings
+ * hal_uart_dma_config_t dmaConfig;
+ * dmaConfig.uart_instance = 0;
+ * dmaConfig.dma_instance = 0;
+ * dmaConfig.rx_channel = 0;
+ * dmaConfig.tx_channel = 1;
+ *
+ * Init uart dma
+ * HAL_UartDMAInit((hal_uart_handle_t *)g_uartHandle, (hal_uart_dma_handle_t *)g_uartDmaHandle, &dmaConfig);
+ * @endcode
+ *
+ * @param handle UART handle pointer.
+ * @param dmaHandle Pointer to point to a memory space of size #HAL_UART_DMA_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #UART_DMA_HANDLE_DEFINE(handle);
+ * or
+ * uint32_t handle[((HAL_UART_DMA_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param dmaConfig Pointer to user-defined configuration structure.
+ * @retval kStatus_HAL_UartDmaError UART dma initialization failed.
+ * @retval kStatus_HAL_UartDmaSuccess UART dma initialization succeed.
+ */
+hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle,
+ hal_uart_dma_handle_t dmaHandle,
+ hal_uart_dma_config_t *dmaConfig);
+
+/*!
+ * @brief Deinitializes a UART DMA instance.
+ *
+ * This function will abort uart dma receive/send transfer and deinitialize UART.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartDmaSuccess UART DMA de-initialization succeed
+ */
+hal_uart_dma_status_t HAL_UartDMADeinit(hal_uart_handle_t handle);
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART DMA module.
+ * When any status of the UART DMA changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartDmaSuccess Successfully install the callback.
+ */
+hal_uart_dma_status_t HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle,
+ hal_uart_dma_transfer_callback_t callback,
+ void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an dma method.
+ *
+ * This function receives data using an dma method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART DMA driver.
+ * When all data is received, the UART DMA adapter notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_HAL_UartDmaRxIdle.
+ *
+ * When an idleline is detected, the UART DMA adapter notifies the upper layer through a callback function,
+ * and passes the status parameter @ref kStatus_HAL_UartDmaIdleline. For the UARTs without hardware idleline
+ * interrupt(like usart), it will use a software idleline detection method with the help of TimerManager.
+ *
+ * When the soc support cache, uplayer should do cache maintain operations for transfer buffer before call this API.
+ *
+ * @param handle UART handle pointer.
+ * @param data data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @param receiveAll Idleline interrupt will not end transfer process if set true.
+ * @retval kStatus_HAL_UartDmaSuccess Successfully start the data receive.
+ * @retval kStatus_HAL_UartDmaRxBusy Previous receive request is not finished.
+ */
+hal_uart_dma_status_t HAL_UartDMATransferReceive(hal_uart_handle_t handle,
+ uint8_t *data,
+ size_t length,
+ bool receiveAll);
+
+/*!
+ * @brief Transmits a buffer of data using an dma method.
+ *
+ * This function sends data using an dma method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register by DMA, the UART DMA driver calls the callback
+ * function and passes the @ref kStatus_HAL_UartDmaTxIdle as status parameter.
+ *
+ * When the soc support cache, uplayer should do cache maintain operations for transfer buffer before call this API.
+ *
+ * @param handle UART handle pointer.
+ * @param data data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartDmaSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartDmaTxBusy Previous send request is not finished.
+ */
+hal_uart_dma_status_t HAL_UartDMATransferSend(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param reCount Receive bytes count.
+ * @retval kStatus_HAL_UartDmaError An error occurred.
+ * @retval kStatus_HAL_UartDmaSuccess Get successfully through the parameter \p reCount.
+ */
+hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the DMA method.
+ *
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_HAL_UartDmaError An error occurred.
+ * @retval kStatus_HAL_UartDmaSuccess Get successfully through the parameter \p seCount.
+ */
+hal_uart_dma_status_t HAL_UartDMAGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
+
+/*!
+ * @brief Aborts the DMA-driven data receiving.
+ *
+ * This function aborts the DMA-driven data receiving.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartDmaSuccess Get successfully abort the receiving.
+ */
+hal_uart_dma_status_t HAL_UartDMAAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the DMA-driven data sending.
+ *
+ * This function aborts the DMA-driven data sending.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_dma_status_t HAL_UartDMAAbortSend(hal_uart_handle_t handle);
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*!
+ * @brief Prepares to enter low power consumption.
+ *
+ * This function is used to prepare to enter low power consumption.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess Successful operation.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle);
+
+/*!
+ * @brief Restores from low power consumption.
+ *
+ * This function is used to restore from low power consumption.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess Successful operation.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle);
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*!
+ * @brief UART IRQ handle function.
+ *
+ * This function handles the UART transmit and receive IRQ request.
+ *
+ * @param handle UART handle pointer.
+ */
+void HAL_UartIsrFunction(hal_uart_handle_t handle);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @}*/
+#endif /* __HAL_UART_ADAPTER_H__ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/component/uart/fsl_adapter_usart.c b/minimal-examples/embedded/rt595/hello_world/project/component/uart/fsl_adapter_usart.c
new file mode 100644
index 000000000..4261752b8
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/component/uart/fsl_adapter_usart.c
@@ -0,0 +1,1086 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_usart.h"
+#include "fsl_flexcomm.h"
+
+#include "fsl_adapter_uart.h"
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+#include "fsl_component_timer_manager.h"
+#include "fsl_usart_dma.h"
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+/*! @brief uart RX state structure. */
+typedef struct _hal_uart_dma_receive_state
+{
+ uint8_t *volatile buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+ volatile uint32_t timeout;
+ volatile bool receiveAll;
+} hal_uart_dma_receive_state_t;
+
+/*! @brief uart TX state structure. */
+typedef struct _hal_uart_dma_send_state
+{
+ uint8_t *volatile buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+ volatile uint32_t timeout;
+} hal_uart_dma_send_state_t;
+
+typedef struct _hal_uart_dma_state
+{
+ struct _hal_uart_dma_state *next;
+ uint8_t instance; /* USART instance */
+ hal_uart_dma_transfer_callback_t dma_callback;
+ void *dma_callback_param;
+ usart_dma_handle_t dmaHandle;
+ dma_handle_t txDmaHandle;
+ dma_handle_t rxDmaHandle;
+ hal_uart_dma_receive_state_t dma_rx;
+ hal_uart_dma_send_state_t dma_tx;
+} hal_uart_dma_state_t;
+
+typedef struct _uart_dma_list
+{
+ TIMER_MANAGER_HANDLE_DEFINE(timerManagerHandle);
+ hal_uart_dma_state_t *dma_list;
+ volatile int8_t activeCount;
+} hal_uart_dma_list_t;
+
+static hal_uart_dma_list_t s_dmaHandleList;
+#endif /* HAL_UART_DMA_ENABLE */
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*! @brief uart RX state structure. */
+typedef struct _hal_uart_receive_state
+{
+ volatile uint8_t *buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+} hal_uart_receive_state_t;
+
+/*! @brief uart TX state structure. */
+typedef struct _hal_uart_send_state
+{
+ volatile uint8_t *buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+} hal_uart_send_state_t;
+#endif
+/*! @brief uart state structure. */
+typedef struct _hal_uart_state
+{
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ hal_uart_transfer_callback_t callback;
+ void *callbackParam;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ usart_handle_t hardwareHandle;
+#endif
+ hal_uart_receive_state_t rx;
+ hal_uart_send_state_t tx;
+#endif
+ uint8_t instance;
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+ hal_uart_dma_state_t *dmaHandle;
+#endif /* HAL_UART_DMA_ENABLE */
+} hal_uart_state_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static USART_Type *const s_UsartAdapterBase[] = USART_BASE_PTRS;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+/* Array of USART IRQ number. */
+static const IRQn_Type s_UsartIRQ[] = USART_IRQS;
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if ((defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) || \
+ (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)))
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+ hal_uart_status_t uartStatus = kStatus_HAL_UartError;
+ switch (status)
+ {
+ case kStatus_Success:
+ uartStatus = kStatus_HAL_UartSuccess;
+ break;
+ case kStatus_USART_TxBusy:
+ uartStatus = kStatus_HAL_UartTxBusy;
+ break;
+ case kStatus_USART_RxBusy:
+ uartStatus = kStatus_HAL_UartRxBusy;
+ break;
+ case kStatus_USART_TxIdle:
+ uartStatus = kStatus_HAL_UartTxIdle;
+ break;
+ case kStatus_USART_RxIdle:
+ uartStatus = kStatus_HAL_UartRxIdle;
+ break;
+ case kStatus_USART_BaudrateNotSupport:
+ uartStatus = kStatus_HAL_UartBaudrateNotSupport;
+ break;
+ case kStatus_USART_NoiseError:
+ case kStatus_USART_FramingError:
+ case kStatus_USART_ParityError:
+ uartStatus = kStatus_HAL_UartProtocolError;
+ break;
+ default:
+ /* This comments for MISRA C-2012 Rule 16.4 */
+ break;
+ }
+ return uartStatus;
+}
+#else
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+ if (kStatus_Success == status)
+ {
+ return kStatus_HAL_UartSuccess;
+ }
+ else
+ {
+ return kStatus_HAL_UartError;
+ }
+}
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+static void HAL_UartCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_status_t uartStatus = HAL_UartGetStatus(status);
+ assert(callbackParam);
+
+ uartHandle = (hal_uart_state_t *)callbackParam;
+
+ if (kStatus_HAL_UartProtocolError == uartStatus)
+ {
+ if (0U != uartHandle->hardwareHandle.rxDataSize)
+ {
+ uartStatus = kStatus_HAL_UartError;
+ }
+ }
+
+ if (NULL != uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam);
+ }
+}
+
+#else
+static void HAL_UartInterruptHandle(USART_Type *base, void *handle)
+{
+ hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle;
+ uint32_t status;
+ uint8_t instance;
+
+ if (NULL == uartHandle)
+ {
+ return;
+ }
+ instance = uartHandle->instance;
+
+ status = USART_GetStatusFlags(s_UsartAdapterBase[instance]);
+
+ /* Receive data register full */
+ if ((0U != (USART_FIFOSTAT_RXNOTEMPTY_MASK & status)) &&
+ (0U != (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_RXLVL_MASK)))
+ {
+ if (NULL != uartHandle->rx.buffer)
+ {
+ uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = USART_ReadByte(s_UsartAdapterBase[instance]);
+ if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[instance],
+ USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
+ uartHandle->rx.buffer = NULL;
+ if (NULL != uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam);
+ }
+ }
+ }
+ }
+
+ /* Send data register empty and the interrupt is enabled. */
+ if ((0U != (USART_FIFOSTAT_TXNOTFULL_MASK & status)) &&
+ (0U != (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_TXLVL_MASK)))
+ {
+ if (NULL != uartHandle->tx.buffer)
+ {
+ USART_WriteByte(s_UsartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]);
+ if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[instance], USART_FIFOINTENCLR_TXLVL_MASK);
+ uartHandle->tx.buffer = NULL;
+ if (NULL != uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam);
+ }
+ }
+ }
+ }
+
+#if 1
+ USART_ClearStatusFlags(s_UsartAdapterBase[instance], status);
+#endif
+}
+
+static void HAL_UartInterruptHandle_Wapper(void *base, void *handle)
+{
+ HAL_UartInterruptHandle((USART_Type *)base, handle);
+}
+#endif
+
+#endif
+
+static hal_uart_status_t HAL_UartInitCommon(hal_uart_handle_t handle, const hal_uart_config_t *config)
+{
+ usart_config_t usartConfig;
+ status_t status;
+
+ assert(handle);
+ assert(config);
+ assert(config->instance < (sizeof(s_UsartAdapterBase) / sizeof(USART_Type *)));
+ assert(s_UsartAdapterBase[config->instance]);
+ assert(HAL_UART_HANDLE_SIZE >= sizeof(hal_uart_state_t));
+
+ USART_GetDefaultConfig(&usartConfig);
+ usartConfig.baudRate_Bps = config->baudRate_Bps;
+
+ if ((0U != config->enableRxRTS) || (0U != config->enableTxCTS))
+ {
+ usartConfig.enableHardwareFlowControl = true;
+ }
+
+ if (kHAL_UartParityEven == config->parityMode)
+ {
+ usartConfig.parityMode = kUSART_ParityEven;
+ }
+ else if (kHAL_UartParityOdd == config->parityMode)
+ {
+ usartConfig.parityMode = kUSART_ParityOdd;
+ }
+ else
+ {
+ usartConfig.parityMode = kUSART_ParityDisabled;
+ }
+
+ if (kHAL_UartTwoStopBit == config->stopBitCount)
+ {
+ usartConfig.stopBitCount = kUSART_TwoStopBit;
+ }
+ else
+ {
+ usartConfig.stopBitCount = kUSART_OneStopBit;
+ }
+ usartConfig.enableRx = (bool)config->enableRx;
+ usartConfig.enableTx = (bool)config->enableTx;
+ usartConfig.txWatermark = kUSART_TxFifo0;
+ usartConfig.rxWatermark = kUSART_RxFifo1;
+
+ status = USART_Init(s_UsartAdapterBase[config->instance], &usartConfig, config->srcClock_Hz);
+
+ if (kStatus_Success != status)
+ {
+ return HAL_UartGetStatus(status);
+ }
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *config)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_status_t status;
+
+ /* Init serial port */
+ status = HAL_UartInitCommon(handle, config);
+ if (kStatus_HAL_UartSuccess != status)
+ {
+ return status;
+ }
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartHandle->instance = config->instance;
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+ uartHandle->dmaHandle = NULL;
+#endif /* HAL_UART_DMA_ENABLE */
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ USART_TransferCreateHandle(s_UsartAdapterBase[config->instance], &uartHandle->hardwareHandle,
+ (usart_transfer_callback_t)HAL_UartCallback, handle);
+#else
+ /* Enable interrupt in NVIC. */
+ FLEXCOMM_SetIRQHandler(s_UsartAdapterBase[config->instance], HAL_UartInterruptHandle_Wapper, handle);
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[config->instance], HAL_UART_ISR_PRIORITY);
+ (void)EnableIRQ(s_UsartIRQ[config->instance]);
+#endif
+
+#endif
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ USART_Deinit(s_UsartAdapterBase[uartHandle->instance]);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(data);
+ assert(length);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ if (NULL != uartHandle->rx.buffer)
+ {
+ return kStatus_HAL_UartRxBusy;
+ }
+#endif
+
+ status = USART_ReadBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ if (NULL != uartHandle->tx.buffer)
+ {
+ return kStatus_HAL_UartTxBusy;
+ }
+#endif
+
+ (void)USART_WriteBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle)
+{
+ assert(handle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle)
+{
+ assert(handle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ uartHandle->callbackParam = callbackParam;
+ uartHandle->callback = callback;
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(transfer);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = USART_TransferReceiveNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+ (usart_transfer_t *)transfer, NULL);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(transfer);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = USART_TransferSendNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+ (usart_transfer_t *)transfer);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(count);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status =
+ USART_TransferGetReceiveCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(count);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = USART_TransferGetSendCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ USART_TransferAbortReceive(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ USART_TransferAbortSend(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#else
+
+/* None transactional API with non-blocking mode. */
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ uartHandle->callbackParam = callbackParam;
+ uartHandle->callback = callback;
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->rx.buffer)
+ {
+ return kStatus_HAL_UartRxBusy;
+ }
+
+ uartHandle->rx.bufferLength = length;
+ uartHandle->rx.bufferSofar = 0;
+ uartHandle->rx.buffer = data;
+ USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK);
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->tx.buffer)
+ {
+ return kStatus_HAL_UartTxBusy;
+ }
+ uartHandle->tx.bufferLength = length;
+ uartHandle->tx.bufferSofar = 0;
+ uartHandle->tx.buffer = (volatile uint8_t *)data;
+ USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_TXLVL_MASK);
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(reCount);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->rx.buffer)
+ {
+ *reCount = uartHandle->rx.bufferSofar;
+ return kStatus_HAL_UartSuccess;
+ }
+ return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(seCount);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->tx.buffer)
+ {
+ *seCount = uartHandle->tx.bufferSofar;
+ return kStatus_HAL_UartSuccess;
+ }
+ return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->rx.buffer)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance],
+ USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
+ uartHandle->rx.buffer = NULL;
+ }
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->tx.buffer)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENCLR_TXLVL_MASK);
+ uartHandle->tx.buffer = NULL;
+ }
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#endif
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+ DisableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+ USART_TransferHandleIRQ(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+#if 0
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+ EnableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+}
+
+#else
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+ DisableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+ HAL_UartInterruptHandle(s_UsartAdapterBase[uartHandle->instance], (void *)uartHandle);
+#if 0
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+ EnableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+}
+
+#endif
+
+#endif
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+static void USART_DMACallbacks(USART_Type *base, usart_dma_handle_t *handle, status_t status, void *userData)
+{
+ hal_uart_dma_state_t *uartDmaHandle;
+ hal_uart_status_t uartStatus = HAL_UartGetStatus(status);
+ hal_dma_callback_msg_t msg;
+ assert(handle);
+
+ uartDmaHandle = (hal_uart_dma_state_t *)userData;
+
+ if (NULL != uartDmaHandle->dma_callback)
+ {
+ if (kStatus_HAL_UartTxIdle == uartStatus)
+ {
+ msg.status = kStatus_HAL_UartDmaTxIdle;
+ msg.data = uartDmaHandle->dma_tx.buffer;
+ msg.dataSize = uartDmaHandle->dma_tx.bufferLength;
+ uartDmaHandle->dma_tx.buffer = NULL;
+ }
+ else if (kStatus_HAL_UartRxIdle == uartStatus)
+ {
+ msg.status = kStatus_HAL_UartDmaRxIdle;
+ msg.data = uartDmaHandle->dma_rx.buffer;
+ msg.dataSize = uartDmaHandle->dma_rx.bufferLength;
+ uartDmaHandle->dma_rx.buffer = NULL;
+ }
+
+ uartDmaHandle->dma_callback(uartDmaHandle, &msg, uartDmaHandle->dma_callback_param);
+ }
+}
+
+static void TimeoutTimer_Callbcak(void *param)
+{
+ hal_uart_dma_list_t *uartDmaHandleList;
+ hal_uart_dma_state_t *uartDmaHandle;
+ hal_dma_callback_msg_t msg;
+ uint32_t newReceived = 0U;
+
+ uartDmaHandleList = &s_dmaHandleList;
+ uartDmaHandle = uartDmaHandleList->dma_list;
+
+ while (NULL != uartDmaHandle)
+ {
+ if ((NULL != uartDmaHandle->dma_rx.buffer) && (false == uartDmaHandle->dma_rx.receiveAll))
+ {
+ /* HAL_UartDMAGetReceiveCount(uartDmaHandle, &msg.dataSize); */
+ USART_TransferGetReceiveCountDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle,
+ &msg.dataSize);
+ newReceived = msg.dataSize - uartDmaHandle->dma_rx.bufferSofar;
+ uartDmaHandle->dma_rx.bufferSofar = msg.dataSize;
+
+ /* 1, If it is in idle state. */
+ if ((0U == newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar))
+ {
+ uartDmaHandle->dma_rx.timeout++;
+ if (uartDmaHandle->dma_rx.timeout >= HAL_UART_DMA_IDLELINE_TIMEOUT)
+ {
+ /* HAL_UartDMAAbortReceive(uartDmaHandle); */
+ USART_TransferAbortReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance],
+ &uartDmaHandle->dmaHandle);
+ msg.data = uartDmaHandle->dma_rx.buffer;
+ msg.status = kStatus_HAL_UartDmaIdleline;
+ uartDmaHandle->dma_rx.buffer = NULL;
+ uartDmaHandle->dma_callback(uartDmaHandle, &msg, uartDmaHandle->dma_callback_param);
+ }
+ }
+ /* 2, If got new data again. */
+ if ((0U < newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar))
+ {
+ uartDmaHandle->dma_rx.timeout = 0U;
+ }
+ }
+
+ uartDmaHandle = uartDmaHandle->next;
+ }
+}
+
+hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle,
+ hal_uart_dma_handle_t dmaHandle,
+ hal_uart_dma_config_t *dmaConfig)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+
+ assert(handle);
+ assert(dmaHandle);
+
+ /* DMA init process. */
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = (hal_uart_dma_state_t *)dmaHandle;
+
+ uartHandle->dmaHandle = uartDmaHandle;
+
+ uartDmaHandle->instance = dmaConfig->uart_instance;
+
+ DMA_Type *dmaBases[] = DMA_BASE_PTRS;
+ DMA_EnableChannel(dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel);
+ DMA_EnableChannel(dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel);
+
+ DMA_CreateHandle(&uartDmaHandle->txDmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel);
+ DMA_CreateHandle(&uartDmaHandle->rxDmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel);
+
+ /* Timeout timer init. */
+ if (0U == s_dmaHandleList.activeCount)
+ {
+ s_dmaHandleList.dma_list = uartDmaHandle;
+ uartDmaHandle->next = NULL;
+ s_dmaHandleList.activeCount++;
+
+ timer_status_t timerStatus;
+ timerStatus = TM_Open((timer_handle_t)s_dmaHandleList.timerManagerHandle);
+ assert(kStatus_TimerSuccess == timerStatus);
+
+ timerStatus =
+ TM_InstallCallback((timer_handle_t)s_dmaHandleList.timerManagerHandle, TimeoutTimer_Callbcak, NULL);
+ assert(kStatus_TimerSuccess == timerStatus);
+
+ (void)TM_Start((timer_handle_t)s_dmaHandleList.timerManagerHandle, (uint8_t)kTimerModeIntervalTimer, 1);
+
+ (void)timerStatus;
+ }
+ else
+ {
+ uartDmaHandle->next = s_dmaHandleList.dma_list;
+ s_dmaHandleList.dma_list = uartDmaHandle;
+ }
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMADeinit(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+ hal_uart_dma_state_t *prev;
+ hal_uart_dma_state_t *curr;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = uartHandle->dmaHandle;
+
+ uartHandle->dmaHandle = NULL;
+
+ assert(uartDmaHandle);
+
+ /* Abort rx/tx */
+ /* Here we should not abort before create transfer handle. */
+ if (NULL != uartDmaHandle->dmaHandle.txDmaHandle)
+ {
+ USART_TransferAbortSendDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle);
+ }
+ if (NULL != uartDmaHandle->dmaHandle.rxDmaHandle)
+ {
+ USART_TransferAbortReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle);
+ }
+
+ /* Disable rx/tx channels */
+ /* Here we should not disable before create transfer handle. */
+ if (NULL != uartDmaHandle->dmaHandle.txDmaHandle)
+ {
+ DMA_DisableChannel(uartDmaHandle->txDmaHandle.base, uartDmaHandle->txDmaHandle.channel);
+ }
+ if (NULL != uartDmaHandle->dmaHandle.rxDmaHandle)
+ {
+ DMA_DisableChannel(uartDmaHandle->rxDmaHandle.base, uartDmaHandle->rxDmaHandle.channel);
+ }
+
+ /* Remove handle from list */
+ prev = NULL;
+ curr = s_dmaHandleList.dma_list;
+ while (curr != NULL)
+ {
+ if (curr == uartDmaHandle)
+ {
+ /* 1, if it is the first one */
+ if (prev == NULL)
+ {
+ s_dmaHandleList.dma_list = curr->next;
+ }
+ /* 2, if it is the last one */
+ else if (curr->next == NULL)
+ {
+ prev->next = NULL;
+ }
+ /* 3, if it is in the middle */
+ else
+ {
+ prev->next = curr->next;
+ }
+ break;
+ }
+
+ prev = curr;
+ curr = curr->next;
+ }
+
+ /* Reset all handle data. */
+ (void)memset(uartDmaHandle, 0, sizeof(hal_uart_dma_state_t));
+
+ s_dmaHandleList.activeCount = (s_dmaHandleList.activeCount > 0) ? (s_dmaHandleList.activeCount - 1) : 0;
+ if (0 == s_dmaHandleList.activeCount)
+ {
+ (void)TM_Close((timer_handle_t)s_dmaHandleList.timerManagerHandle);
+ }
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle,
+ hal_uart_dma_transfer_callback_t callback,
+ void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = uartHandle->dmaHandle;
+
+ assert(uartDmaHandle);
+
+ uartDmaHandle->dma_callback = callback;
+ uartDmaHandle->dma_callback_param = callbackParam;
+
+ USART_TransferCreateHandleDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle,
+ USART_DMACallbacks, uartDmaHandle, &uartDmaHandle->txDmaHandle,
+ &uartDmaHandle->rxDmaHandle);
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMATransferReceive(hal_uart_handle_t handle,
+ uint8_t *data,
+ size_t length,
+ bool receiveAll)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+ usart_transfer_t xfer;
+
+ assert(handle);
+ assert(data);
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = uartHandle->dmaHandle;
+
+ assert(uartDmaHandle);
+
+ if (NULL == uartDmaHandle->dma_rx.buffer)
+ {
+ uartDmaHandle->dma_rx.buffer = data;
+ uartDmaHandle->dma_rx.bufferLength = length;
+ uartDmaHandle->dma_rx.timeout = 0U;
+ uartDmaHandle->dma_rx.receiveAll = receiveAll;
+ }
+ else
+ {
+ /* Already in reading process. */
+ return kStatus_HAL_UartDmaRxBusy;
+ }
+
+ xfer.data = data;
+ xfer.dataSize = length;
+
+ USART_TransferReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle, &xfer);
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMATransferSend(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+ usart_transfer_t xfer;
+
+ assert(handle);
+ assert(data);
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = uartHandle->dmaHandle;
+
+ assert(uartDmaHandle);
+
+ if (NULL == uartDmaHandle->dma_tx.buffer)
+ {
+ uartDmaHandle->dma_tx.buffer = data;
+ uartDmaHandle->dma_tx.bufferLength = length;
+ uartDmaHandle->dma_tx.bufferSofar = 0U;
+ uartDmaHandle->dma_tx.timeout = 0U;
+ }
+ else
+ {
+ /* Already in writing process. */
+ return kStatus_HAL_UartDmaTxBusy;
+ }
+
+ xfer.data = data;
+ xfer.dataSize = length;
+
+ USART_TransferSendDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle, &xfer);
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = uartHandle->dmaHandle;
+
+ assert(uartDmaHandle);
+
+ if (kStatus_Success != USART_TransferGetReceiveCountDMA(s_UsartAdapterBase[uartDmaHandle->instance],
+ &uartDmaHandle->dmaHandle, reCount))
+ {
+ return kStatus_HAL_UartDmaError;
+ }
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMAGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)
+{
+ /* No get send count API */
+ return kStatus_HAL_UartDmaError;
+}
+
+hal_uart_dma_status_t HAL_UartDMAAbortReceive(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = uartHandle->dmaHandle;
+
+ assert(uartDmaHandle);
+
+ USART_TransferAbortReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle);
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMAAbortSend(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = uartHandle->dmaHandle;
+
+ assert(uartDmaHandle);
+
+ USART_TransferAbortSendDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle);
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+#endif /* HAL_UART_DMA_ENABLE */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/device/MIMXRT595S_cm33.h b/minimal-examples/embedded/rt595/hello_world/project/device/MIMXRT595S_cm33.h
new file mode 100644
index 000000000..943f76962
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/device/MIMXRT595S_cm33.h
@@ -0,0 +1,56136 @@
+/*
+** ###################################################################
+** Processors: MIMXRT595SFAWC_cm33
+** MIMXRT595SFFOC_cm33
+**
+** Compilers: GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** Keil ARM C/C++ Compiler
+** MCUXpresso Compiler
+**
+** Reference manual: iMXRT500RM Rev.0, 01/2021
+** Version: rev. 5.0, 2020-08-27
+** Build: b210222
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MIMXRT595S_cm33
+**
+** Copyright 1997-2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2021 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2019-04-19)
+** Initial version.
+** - rev. 2.0 (2019-07-22)
+** Base on rev 0.7 RM.
+** - rev. 3.0 (2020-03-16)
+** Base on Rev.A RM.
+** - rev. 4.0 (2020-05-18)
+** Base on Rev.B RM.
+** - rev. 5.0 (2020-08-27)
+** Base on Rev.C RM.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MIMXRT595S_cm33.h
+ * @version 5.0
+ * @date 2020-08-27
+ * @brief CMSIS Peripheral Access Layer for MIMXRT595S_cm33
+ *
+ * CMSIS Peripheral Access Layer for MIMXRT595S_cm33
+ */
+
+#ifndef _MIMXRT595S_CM33_H_
+#define _MIMXRT595S_CM33_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0500U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 90 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Auxiliary constants */
+ NotAvail_IRQn = -128, /**< Not available device specific interrupt */
+
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ WDT0_IRQn = 0, /**< Watchdog timer interrupt */
+ DMA0_IRQn = 1, /**< DMA interrupt */
+ GPIO_INTA_IRQn = 2, /**< GPIO Interrupt A */
+ GPIO_INTB_IRQn = 3, /**< GPIO Interrupt B */
+ PIN_INT0_IRQn = 4, /**< General Purpose Input/Output interrupt 0 */
+ PIN_INT1_IRQn = 5, /**< General Purpose Input/Output interrupt 1 */
+ PIN_INT2_IRQn = 6, /**< General Purpose Input/Output interrupt 2 */
+ PIN_INT3_IRQn = 7, /**< General Purpose Input/Output interrupt 3 */
+ UTICK0_IRQn = 8, /**< Micro-tick Timer */
+ MRT0_IRQn = 9, /**< Multi-Rate Timer */
+ CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
+ CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
+ SCT0_IRQn = 12, /**< SCTimer/PWM */
+ CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
+ FLEXCOMM0_IRQn = 14, /**< FlexComm interrupt */
+ FLEXCOMM1_IRQn = 15, /**< FlexComm interrupt */
+ FLEXCOMM2_IRQn = 16, /**< FlexComm interrupt */
+ FLEXCOMM3_IRQn = 17, /**< FlexComm interrupt */
+ FLEXCOMM4_IRQn = 18, /**< FlexComm interrupt */
+ FLEXCOMM5_IRQn = 19, /**< FlexComm interrupt */
+ FLEXCOMM14_IRQn = 20, /**< FlexComm interrupt. Standalone SPI */
+ FLEXCOMM15_IRQn = 21, /**< FlexComm interrupt. Standalone I2C */
+ ADC0_IRQn = 22, /**< Analog-to-Digital Converter interrupt */
+ Reserved39_IRQn = 23, /**< Reserved interrupt */
+ ACMP_IRQn = 24, /**< Analog comparator Interrupts */
+ DMIC0_IRQn = 25, /**< Digital Microphone Interface interrupt */
+ Reserved42_IRQn = 26, /**< Reserved interrupt */
+ HYPERVISOR_IRQn = 27, /**< Hypervisor interrupt */
+ SECURE_VIOLATION_IRQn = 28, /**< Secure violation interrupt */
+ HWVAD0_IRQn = 29, /**< Hardware Voice Activity Detector interrupt */
+ Reserved46_IRQn = 30, /**< Reserved interrupt */
+ RNG_IRQn = 31, /**< Random Number Generator interrupt */
+ RTC_IRQn = 32, /**< Real Time Clock Alarm interrupt OR Wakeup timer interrupt */
+ DSP_TIE_EXPSTATE1_IRQn = 33, /**< DSP interrupt */
+ MU_A_IRQn = 34, /**< Messaging Unit - Side A */
+ PIN_INT4_IRQn = 35, /**< General Purpose Input/Output interrupt 4 */
+ PIN_INT5_IRQn = 36, /**< General Purpose Input/Output interrupt 5 */
+ PIN_INT6_IRQn = 37, /**< General Purpose Input/Output interrupt 6 */
+ PIN_INT7_IRQn = 38, /**< General Purpose Input/Output interrupt 7 */
+ CTIMER2_IRQn = 39, /**< Standard counter/timer CTIMER2 */
+ CTIMER4_IRQn = 40, /**< Standard counter/timer CTIMER4 */
+ OS_EVENT_IRQn = 41, /**< Event timer M33 Wakeup/interrupt */
+ FLEXSPI0_FLEXSPI1_IRQn = 42, /**< FlexSPI0_IRQ OR FlexSPI1_IRQ */
+ FLEXCOMM6_IRQn = 43, /**< FlexComm interrupt */
+ FLEXCOMM7_IRQn = 44, /**< FlexComm interrupt */
+ USDHC0_IRQn = 45, /**< USDHC interrupt */
+ USDHC1_IRQn = 46, /**< USDHC interrupt */
+ SGPIO_INTA_IRQn = 47, /**< Secure GPIO HS interrupt 0 */
+ SGPIO_INTB_IRQn = 48, /**< Secure GPIO HS interrupt 1 */
+ I3C0_IRQn = 49, /**< Improved Inter Integrated Circuit 0 interrupt */
+ USB0_IRQn = 50, /**< USB device */
+ USB0_NEEDCLK_IRQn = 51, /**< USB Activity Wake-up Interrupt */
+ WDT1_IRQn = 52, /**< Watchdog timer 1 interrupt */
+ USB_PHYDCD_IRQn = 53, /**< USBPHY DCD interrupt */
+ DMA1_IRQn = 54, /**< DMA interrupt */
+ PUF_IRQn = 55, /**< QuidKey interrupt */
+ POWERQUAD_IRQn = 56, /**< Powerquad interrupt */
+ CASPER_IRQn = 57, /**< Caspar interrupt */
+ PMU_PMIC_IRQn = 58, /**< Power Management Control interrupt */
+ HASHCRYPT_IRQn = 59, /**< SHA interrupt */
+ FLEXCOMM8_IRQn = 60, /**< FlexComm interrupt */
+ FLEXCOMM9_IRQn = 61, /**< FlexComm interrupt */
+ FLEXCOMM10_IRQn = 62, /**< FlexComm interrupt */
+ FLEXCOMM11_IRQn = 63, /**< FlexComm interrupt */
+ FLEXCOMM12_IRQn = 64, /**< FlexComm interrupt */
+ FLEXCOMM13_IRQn = 65, /**< FlexComm interrupt */
+ FLEXCOMM16_IRQn = 66, /**< FlexComm interrupt */
+ I3C1_IRQn = 67, /**< Improved Inter Integrated Circuit 1 interrupt */
+ FLEXIO_IRQn = 68, /**< Flexible I/O interrupt */
+ LCDIF_IRQn = 69, /**< Liquid Crystal Display interface interrupt */
+ GPU_IRQn = 70, /**< Graphics Processor Unit interrupt */
+ MIPI_IRQn = 71, /**< MIPI interrupt */
+ Reserved88_IRQn = 72,
+ SDMA_IRQn = 73 /**< Smart DMA Engine Controller interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M33 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
+#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */
+#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */
+
+#include "core_cm33.h" /* Core Peripheral Access Layer */
+#include "system_MIMXRT595S_cm33.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #else
+ #pragma push
+ #pragma anon_unions
+ #endif
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
+ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
+ uint8_t RESERVED_0[8];
+ __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */
+ __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */
+ __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
+ __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
+ __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */
+ __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */
+ uint8_t RESERVED_1[12];
+ __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
+ __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */
+ uint8_t RESERVED_2[100];
+ __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
+ __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */
+ uint8_t RESERVED_3[24];
+ struct { /* offset: 0x100, array step: 0x8 */
+ __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
+ __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
+ } CMD[15];
+ uint8_t RESERVED_4[136];
+ __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
+ uint8_t RESERVED_5[240];
+ __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define ADC_VERID_RES_MASK (0x1U)
+#define ADC_VERID_RES_SHIFT (0U)
+/*! RES - Resolution
+ * 0b0..Up to 13-bit differential/12-bit single ended resolution supported.
+ * 0b1..Up to 16-bit differential/15-bit single ended resolution supported.
+ */
+#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
+#define ADC_VERID_DIFFEN_MASK (0x2U)
+#define ADC_VERID_DIFFEN_SHIFT (1U)
+/*! DIFFEN - Differential Supported
+ * 0b0..Differential operation not supported.
+ * 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
+ */
+#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
+#define ADC_VERID_MVI_MASK (0x8U)
+#define ADC_VERID_MVI_SHIFT (3U)
+/*! MVI - Multi Vref Implemented
+ * 0b0..Single voltage reference high (VREFH) input supported.
+ * 0b1..Multiple voltage reference high (VREFH) inputs supported.
+ */
+#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
+#define ADC_VERID_CSW_MASK (0x70U)
+#define ADC_VERID_CSW_SHIFT (4U)
+/*! CSW - Channel Scale Width
+ * 0b000..Channel scaling not supported.
+ * 0b001..Channel scaling supported. 1-bit CSCALE control field.
+ * 0b110..Channel scaling supported. 6-bit CSCALE control field.
+ */
+#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
+#define ADC_VERID_VR1RNGI_MASK (0x100U)
+#define ADC_VERID_VR1RNGI_SHIFT (8U)
+/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
+ * 0b0..Range control not required. CFG[VREF1RNG] is not implemented.
+ * 0b1..Range control required. CFG[VREF1RNG] is implemented.
+ */
+#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
+#define ADC_VERID_IADCKI_MASK (0x200U)
+#define ADC_VERID_IADCKI_SHIFT (9U)
+/*! IADCKI - Internal ADC Clock implemented
+ * 0b0..Internal clock source not implemented.
+ * 0b1..Internal clock source (and CFG[ADCKEN]) implemented.
+ */
+#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
+#define ADC_VERID_CALOFSI_MASK (0x400U)
+#define ADC_VERID_CALOFSI_SHIFT (10U)
+/*! CALOFSI - Calibration Function Implemented
+ * 0b0..Calibration Not Implemented.
+ * 0b1..Calibration Implemented.
+ */
+#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
+#define ADC_VERID_NUM_SEC_MASK (0x800U)
+#define ADC_VERID_NUM_SEC_SHIFT (11U)
+/*! NUM_SEC - Number of Single Ended Outputs Supported
+ * 0b0..This design supports one single ended conversion at a time.
+ * 0b1..This design supports two simultanious single ended conversions.
+ */
+#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)
+#define ADC_VERID_NUM_FIFO_MASK (0x7000U)
+#define ADC_VERID_NUM_FIFO_SHIFT (12U)
+/*! NUM_FIFO - Number of FIFOs
+ * 0b000..N/A
+ * 0b001..This design supports one result FIFO.
+ * 0b010..This design supports two result FIFOs.
+ * 0b011..This design supports three result FIFOs.
+ * 0b100..This design supports four result FIFOs.
+ */
+#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)
+#define ADC_VERID_MINOR_MASK (0xFF0000U)
+#define ADC_VERID_MINOR_SHIFT (16U)
+/*! MINOR - Minor Version Number
+ */
+#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
+#define ADC_VERID_MAJOR_MASK (0xFF000000U)
+#define ADC_VERID_MAJOR_SHIFT (24U)
+/*! MAJOR - Major Version Number
+ */
+#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
+#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
+/*! TRIG_NUM - Trigger Number
+ */
+#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
+#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
+#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
+/*! FIFOSIZE - Result FIFO Depth
+ * 0b00000001..Result FIFO depth = 1 dataword.
+ * 0b00000100..Result FIFO depth = 4 datawords.
+ * 0b00001000..Result FIFO depth = 8 datawords.
+ * 0b00010000..Result FIFO depth = 16 datawords.
+ * 0b00100000..Result FIFO depth = 32 datawords.
+ * 0b01000000..Result FIFO depth = 64 datawords.
+ */
+#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
+#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
+#define ADC_PARAM_CV_NUM_SHIFT (16U)
+/*! CV_NUM - Compare Value Number
+ */
+#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
+#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
+#define ADC_PARAM_CMD_NUM_SHIFT (24U)
+/*! CMD_NUM - Command Buffer Number
+ */
+#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
+/*! @} */
+
+/*! @name CTRL - ADC Control Register */
+/*! @{ */
+#define ADC_CTRL_ADCEN_MASK (0x1U)
+#define ADC_CTRL_ADCEN_SHIFT (0U)
+/*! ADCEN - ADC Enable
+ * 0b0..ADC is disabled.
+ * 0b1..ADC is enabled.
+ */
+#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
+#define ADC_CTRL_RST_MASK (0x2U)
+#define ADC_CTRL_RST_SHIFT (1U)
+/*! RST - Software Reset
+ * 0b0..ADC logic is not reset.
+ * 0b1..ADC logic is reset.
+ */
+#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
+#define ADC_CTRL_DOZEN_MASK (0x4U)
+#define ADC_CTRL_DOZEN_SHIFT (2U)
+/*! DOZEN - Doze Enable
+ * 0b0..ADC is enabled in Doze mode.
+ * 0b1..ADC is disabled in Doze mode.
+ */
+#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
+#define ADC_CTRL_RSTFIFO0_MASK (0x100U)
+#define ADC_CTRL_RSTFIFO0_SHIFT (8U)
+/*! RSTFIFO0 - Reset FIFO 0
+ * 0b0..No effect.
+ * 0b1..FIFO 0 is reset.
+ */
+#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)
+#define ADC_CTRL_RSTFIFO1_MASK (0x200U)
+#define ADC_CTRL_RSTFIFO1_SHIFT (9U)
+/*! RSTFIFO1 - Reset FIFO 1
+ * 0b0..No effect.
+ * 0b1..FIFO 1 is reset.
+ */
+#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK)
+/*! @} */
+
+/*! @name STAT - ADC Status Register */
+/*! @{ */
+#define ADC_STAT_RDY0_MASK (0x1U)
+#define ADC_STAT_RDY0_SHIFT (0U)
+/*! RDY0 - Result FIFO 0 Ready Flag
+ * 0b0..Result FIFO 0 data level not above watermark level.
+ * 0b1..Result FIFO 0 holding data above watermark level.
+ */
+#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)
+#define ADC_STAT_FOF0_MASK (0x2U)
+#define ADC_STAT_FOF0_SHIFT (1U)
+/*! FOF0 - Result FIFO 0 Overflow Flag
+ * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared.
+ * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
+ */
+#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)
+#define ADC_STAT_RDY1_MASK (0x4U)
+#define ADC_STAT_RDY1_SHIFT (2U)
+/*! RDY1 - Result FIFO1 Ready Flag
+ * 0b0..Result FIFO1 data level not above watermark level.
+ * 0b1..Result FIFO1 holding data above watermark level.
+ */
+#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK)
+#define ADC_STAT_FOF1_MASK (0x8U)
+#define ADC_STAT_FOF1_SHIFT (3U)
+/*! FOF1 - Result FIFO1 Overflow Flag
+ * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
+ * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
+ */
+#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK)
+#define ADC_STAT_TEXC_INT_MASK (0x100U)
+#define ADC_STAT_TEXC_INT_SHIFT (8U)
+/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception
+ * 0b0..No trigger exceptions have occurred.
+ * 0b1..A trigger exception has occurred and is pending acknowledgement.
+ */
+#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)
+#define ADC_STAT_TCOMP_INT_MASK (0x200U)
+#define ADC_STAT_TCOMP_INT_SHIFT (9U)
+/*! TCOMP_INT - Interrupt Flag For Trigger Completion
+ * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
+ * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.
+ */
+#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)
+#define ADC_STAT_ADC_ACTIVE_MASK (0x800U)
+#define ADC_STAT_ADC_ACTIVE_SHIFT (11U)
+/*! ADC_ACTIVE - ADC Active
+ * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
+ * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
+ */
+#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
+#define ADC_STAT_TRGACT_MASK (0xF0000U)
+#define ADC_STAT_TRGACT_SHIFT (16U)
+/*! TRGACT - Trigger Active
+ * 0b0000..Command (sequence) associated with Trigger 0 currently being executed.
+ * 0b0001..Command (sequence) associated with Trigger 1 currently being executed.
+ * 0b0010..Command (sequence) associated with Trigger 2 currently being executed.
+ * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed.
+ */
+#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
+#define ADC_STAT_CMDACT_MASK (0xF000000U)
+#define ADC_STAT_CMDACT_SHIFT (24U)
+/*! CMDACT - Command Active
+ * 0b0000..No command is currently in progress.
+ * 0b0001..Command 1 currently being executed.
+ * 0b0010..Command 2 currently being executed.
+ * 0b0011-0b1111..Associated command number is currently being executed.
+ */
+#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
+/*! @} */
+
+/*! @name IE - Interrupt Enable Register */
+/*! @{ */
+#define ADC_IE_FWMIE0_MASK (0x1U)
+#define ADC_IE_FWMIE0_SHIFT (0U)
+/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
+ * 0b0..FIFO 0 watermark interrupts are not enabled.
+ * 0b1..FIFO 0 watermark interrupts are enabled.
+ */
+#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)
+#define ADC_IE_FOFIE0_MASK (0x2U)
+#define ADC_IE_FOFIE0_SHIFT (1U)
+/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
+ * 0b0..FIFO 0 overflow interrupts are not enabled.
+ * 0b1..FIFO 0 overflow interrupts are enabled.
+ */
+#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)
+#define ADC_IE_FWMIE1_MASK (0x4U)
+#define ADC_IE_FWMIE1_SHIFT (2U)
+/*! FWMIE1 - FIFO1 Watermark Interrupt Enable
+ * 0b0..FIFO1 watermark interrupts are not enabled.
+ * 0b1..FIFO1 watermark interrupts are enabled.
+ */
+#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK)
+#define ADC_IE_FOFIE1_MASK (0x8U)
+#define ADC_IE_FOFIE1_SHIFT (3U)
+/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable
+ * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
+ * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
+ */
+#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK)
+#define ADC_IE_TEXC_IE_MASK (0x100U)
+#define ADC_IE_TEXC_IE_SHIFT (8U)
+/*! TEXC_IE - Trigger Exception Interrupt Enable
+ * 0b0..Trigger exception interrupts are disabled.
+ * 0b1..Trigger exception interrupts are enabled.
+ */
+#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)
+#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U)
+#define ADC_IE_TCOMP_IE_SHIFT (16U)
+/*! TCOMP_IE - Trigger Completion Interrupt Enable
+ * 0b0000000000000000..Trigger completion interrupts are disabled.
+ * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only.
+ * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only.
+ * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled.
+ * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source.
+ */
+#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
+/*! @} */
+
+/*! @name DE - DMA Enable Register */
+/*! @{ */
+#define ADC_DE_FWMDE0_MASK (0x1U)
+#define ADC_DE_FWMDE0_SHIFT (0U)
+/*! FWMDE0 - FIFO 0 Watermark DMA Enable
+ * 0b0..DMA request disabled.
+ * 0b1..DMA request enabled.
+ */
+#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)
+#define ADC_DE_FWMDE1_MASK (0x2U)
+#define ADC_DE_FWMDE1_SHIFT (1U)
+/*! FWMDE1 - FIFO1 Watermark DMA Enable
+ * 0b0..DMA request disabled.
+ * 0b1..DMA request enabled.
+ */
+#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK)
+/*! @} */
+
+/*! @name CFG - ADC Configuration Register */
+/*! @{ */
+#define ADC_CFG_TPRICTRL_MASK (0x3U)
+#define ADC_CFG_TPRICTRL_SHIFT (0U)
+/*! TPRICTRL - ADC trigger priority control
+ * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted
+ * and the new command specified by the trigger is started.
+ * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after
+ * after completing the current conversion. If averaging is enabled, the averaging loop will be completed.
+ * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.
+ * 0b10..If a higher priority trigger is received during command processing, the current command will be
+ * completed (averaging, looping, compare) before servicing the higher priority trigger.
+ * 0b11..RESERVED
+ */
+#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
+#define ADC_CFG_PWRSEL_MASK (0x30U)
+#define ADC_CFG_PWRSEL_SHIFT (4U)
+/*! PWRSEL - Power Configuration Select
+ * 0b00..Lowest power setting.
+ * 0b01..Higher power setting than 0b0.
+ * 0b10..Higher power setting than 0b1.
+ * 0b11..Highest power setting.
+ */
+#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
+#define ADC_CFG_REFSEL_MASK (0xC0U)
+#define ADC_CFG_REFSEL_SHIFT (6U)
+/*! REFSEL - Voltage Reference Selection
+ * 0b00..(Default) Option 1 setting.
+ * 0b01..Option 2 setting.
+ * 0b10..Option 3 setting.
+ * 0b11..Reserved
+ */
+#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
+#define ADC_CFG_TRES_MASK (0x100U)
+#define ADC_CFG_TRES_SHIFT (8U)
+/*! TRES - Trigger Resume Enable
+ * 0b0..Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted.
+ * 0b1..Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted.
+ */
+#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)
+#define ADC_CFG_TCMDRES_MASK (0x200U)
+#define ADC_CFG_TCMDRES_SHIFT (9U)
+/*! TCMDRES - Trigger Command Resume
+ * 0b0..Trigger sequences interrupted by a high priority trigger exception is automatically restarted.
+ * 0b1..Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception.
+ */
+#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)
+#define ADC_CFG_HPT_EXDI_MASK (0x400U)
+#define ADC_CFG_HPT_EXDI_SHIFT (10U)
+/*! HPT_EXDI - High Priority Trigger Exception Disable
+ * 0b0..High priority trigger exceptions are enabled.
+ * 0b1..High priority trigger exceptions are disabled.
+ */
+#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)
+#define ADC_CFG_PUDLY_MASK (0xFF0000U)
+#define ADC_CFG_PUDLY_SHIFT (16U)
+/*! PUDLY - Power Up Delay
+ */
+#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
+#define ADC_CFG_PWREN_MASK (0x10000000U)
+#define ADC_CFG_PWREN_SHIFT (28U)
+/*! PWREN - ADC Analog Pre-Enable
+ * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
+ * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
+ * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN
+ * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed.
+ * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be
+ * executed.
+ */
+#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
+/*! @} */
+
+/*! @name PAUSE - ADC Pause Register */
+/*! @{ */
+#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
+#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
+/*! PAUSEDLY - Pause Delay
+ */
+#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
+#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
+#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
+/*! PAUSEEN - PAUSE Option Enable
+ * 0b0..Pause operation disabled
+ * 0b1..Pause operation enabled
+ */
+#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
+/*! @} */
+
+/*! @name SWTRIG - Software Trigger Register */
+/*! @{ */
+#define ADC_SWTRIG_SWT0_MASK (0x1U)
+#define ADC_SWTRIG_SWT0_SHIFT (0U)
+/*! SWT0 - Software trigger 0 event
+ * 0b0..No trigger 0 event generated.
+ * 0b1..Trigger 0 event generated.
+ */
+#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
+#define ADC_SWTRIG_SWT1_MASK (0x2U)
+#define ADC_SWTRIG_SWT1_SHIFT (1U)
+/*! SWT1 - Software trigger 1 event
+ * 0b0..No trigger 1 event generated.
+ * 0b1..Trigger 1 event generated.
+ */
+#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
+#define ADC_SWTRIG_SWT2_MASK (0x4U)
+#define ADC_SWTRIG_SWT2_SHIFT (2U)
+/*! SWT2 - Software trigger 2 event
+ * 0b0..No trigger 2 event generated.
+ * 0b1..Trigger 2 event generated.
+ */
+#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
+#define ADC_SWTRIG_SWT3_MASK (0x8U)
+#define ADC_SWTRIG_SWT3_SHIFT (3U)
+/*! SWT3 - Software trigger 3 event
+ * 0b0..No trigger 3 event generated.
+ * 0b1..Trigger 3 event generated.
+ */
+#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
+#define ADC_SWTRIG_SWT4_MASK (0x10U)
+#define ADC_SWTRIG_SWT4_SHIFT (4U)
+/*! SWT4 - Software trigger 4 event
+ * 0b0..No trigger 4 event generated.
+ * 0b1..Trigger 4 event generated.
+ */
+#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
+#define ADC_SWTRIG_SWT5_MASK (0x20U)
+#define ADC_SWTRIG_SWT5_SHIFT (5U)
+/*! SWT5 - Software trigger 5 event
+ * 0b0..No trigger 5 event generated.
+ * 0b1..Trigger 5 event generated.
+ */
+#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
+#define ADC_SWTRIG_SWT6_MASK (0x40U)
+#define ADC_SWTRIG_SWT6_SHIFT (6U)
+/*! SWT6 - Software trigger 6 event
+ * 0b0..No trigger 6 event generated.
+ * 0b1..Trigger 6 event generated.
+ */
+#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
+#define ADC_SWTRIG_SWT7_MASK (0x80U)
+#define ADC_SWTRIG_SWT7_SHIFT (7U)
+/*! SWT7 - Software trigger 7 event
+ * 0b0..No trigger 7 event generated.
+ * 0b1..Trigger 7 event generated.
+ */
+#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
+#define ADC_SWTRIG_SWT8_MASK (0x100U)
+#define ADC_SWTRIG_SWT8_SHIFT (8U)
+/*! SWT8 - Software trigger 8 event
+ * 0b0..No trigger 8 event generated.
+ * 0b1..Trigger 8 event generated.
+ */
+#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK)
+#define ADC_SWTRIG_SWT9_MASK (0x200U)
+#define ADC_SWTRIG_SWT9_SHIFT (9U)
+/*! SWT9 - Software trigger 9 event
+ * 0b0..No trigger 9 event generated.
+ * 0b1..Trigger 9 event generated.
+ */
+#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK)
+#define ADC_SWTRIG_SWT10_MASK (0x400U)
+#define ADC_SWTRIG_SWT10_SHIFT (10U)
+/*! SWT10 - Software trigger 10 event
+ * 0b0..No trigger 10 event generated.
+ * 0b1..Trigger 10 event generated.
+ */
+#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK)
+#define ADC_SWTRIG_SWT11_MASK (0x800U)
+#define ADC_SWTRIG_SWT11_SHIFT (11U)
+/*! SWT11 - Software trigger 11 event
+ * 0b0..No trigger 11 event generated.
+ * 0b1..Trigger 11 event generated.
+ */
+#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK)
+#define ADC_SWTRIG_SWT12_MASK (0x1000U)
+#define ADC_SWTRIG_SWT12_SHIFT (12U)
+/*! SWT12 - Software trigger 12 event
+ * 0b0..No trigger 12 event generated.
+ * 0b1..Trigger 12 event generated.
+ */
+#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK)
+#define ADC_SWTRIG_SWT13_MASK (0x2000U)
+#define ADC_SWTRIG_SWT13_SHIFT (13U)
+/*! SWT13 - Software trigger 13 event
+ * 0b0..No trigger 13 event generated.
+ * 0b1..Trigger 13 event generated.
+ */
+#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK)
+#define ADC_SWTRIG_SWT14_MASK (0x4000U)
+#define ADC_SWTRIG_SWT14_SHIFT (14U)
+/*! SWT14 - Software trigger 14 event
+ * 0b0..No trigger 14 event generated.
+ * 0b1..Trigger 14 event generated.
+ */
+#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK)
+#define ADC_SWTRIG_SWT15_MASK (0x8000U)
+#define ADC_SWTRIG_SWT15_SHIFT (15U)
+/*! SWT15 - Software trigger 15 event
+ * 0b0..No trigger 15 event generated.
+ * 0b1..Trigger 15 event generated.
+ */
+#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK)
+/*! @} */
+
+/*! @name TSTAT - Trigger Status Register */
+/*! @{ */
+#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU)
+#define ADC_TSTAT_TEXC_NUM_SHIFT (0U)
+/*! TEXC_NUM - Trigger Exception Number
+ * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
+ * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception.
+ * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception.
+ * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception.
+ * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception.
+ */
+#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)
+#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U)
+#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U)
+/*! TCOMP_FLAG - Trigger Completion Flag
+ * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled.
+ * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts.
+ * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts.
+ * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts.
+ * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.
+ */
+#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
+/*! @} */
+
+/*! @name TCTRL - Trigger Control Register */
+/*! @{ */
+#define ADC_TCTRL_HTEN_MASK (0x1U)
+#define ADC_TCTRL_HTEN_SHIFT (0U)
+/*! HTEN - Trigger enable
+ * 0b0..Hardware trigger source disabled
+ * 0b1..Hardware trigger source enabled
+ */
+#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
+#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U)
+#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U)
+/*! FIFO_SEL_A - SAR Result Destination For Channel A
+ * 0b0..Result written to FIFO 0
+ * 0b1..Result written to FIFO 1
+ */
+#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK)
+#define ADC_TCTRL_TPRI_MASK (0xF00U)
+#define ADC_TCTRL_TPRI_SHIFT (8U)
+/*! TPRI - Trigger priority setting
+ * 0b0000..Set to highest priority, Level 1
+ * 0b0001-0b1110..Set to corresponding priority level
+ * 0b1111..Set to lowest priority, Level 16
+ */
+#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
+#define ADC_TCTRL_RSYNC_MASK (0x8000U)
+#define ADC_TCTRL_RSYNC_SHIFT (15U)
+/*! RSYNC - Trigger Resync
+ */
+#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)
+#define ADC_TCTRL_TDLY_MASK (0xF0000U)
+#define ADC_TCTRL_TDLY_SHIFT (16U)
+/*! TDLY - Trigger delay select
+ */
+#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
+#define ADC_TCTRL_TCMD_MASK (0xF000000U)
+#define ADC_TCTRL_TCMD_SHIFT (24U)
+/*! TCMD - Trigger command select
+ * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
+ * 0b0001..CMD1 is executed
+ * 0b0010-0b1110..Corresponding CMD is executed
+ * 0b1111..CMD15 is executed
+ */
+#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
+/*! @} */
+
+/* The count of ADC_TCTRL */
+#define ADC_TCTRL_COUNT (16U)
+
+/*! @name FCTRL - FIFO Control Register */
+/*! @{ */
+#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
+#define ADC_FCTRL_FCOUNT_SHIFT (0U)
+/*! FCOUNT - Result FIFO counter
+ */
+#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
+#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
+#define ADC_FCTRL_FWMARK_SHIFT (16U)
+/*! FWMARK - Watermark level selection
+ */
+#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
+/*! @} */
+
+/* The count of ADC_FCTRL */
+#define ADC_FCTRL_COUNT (2U)
+
+/*! @name CMDL - ADC Command Low Buffer Register */
+/*! @{ */
+#define ADC_CMDL_ADCH_MASK (0x1FU)
+#define ADC_CMDL_ADCH_SHIFT (0U)
+/*! ADCH - Input channel select
+ * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
+ * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
+ * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
+ * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
+ * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
+ * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
+ * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
+ */
+#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
+#define ADC_CMDL_ABSEL_MASK (0x20U)
+#define ADC_CMDL_ABSEL_SHIFT (5U)
+/*! ABSEL - A-side vs. B-side Select
+ * 0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
+ * 0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
+ */
+#define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
+#define ADC_CMDL_DIFF_MASK (0x40U)
+#define ADC_CMDL_DIFF_SHIFT (6U)
+/*! DIFF - Differential Mode Enable
+ * 0b0..Single-ended mode.
+ * 0b1..Differential mode.
+ */
+#define ADC_CMDL_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
+#define ADC_CMDL_CSCALE_MASK (0x2000U)
+#define ADC_CMDL_CSCALE_SHIFT (13U)
+/*! CSCALE - Channel Scale
+ * 0b0..Scale selected analog channel (Factor of 30/64)
+ * 0b1..(Default) Full scale (Factor of 1)
+ */
+#define ADC_CMDL_CSCALE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
+/*! @} */
+
+/* The count of ADC_CMDL */
+#define ADC_CMDL_COUNT (15U)
+
+/*! @name CMDH - ADC Command High Buffer Register */
+/*! @{ */
+#define ADC_CMDH_CMPEN_MASK (0x3U)
+#define ADC_CMDH_CMPEN_SHIFT (0U)
+/*! CMPEN - Compare Function Enable
+ * 0b00..Compare disabled.
+ * 0b01..Reserved
+ * 0b10..Compare enabled. Store on true.
+ * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
+ */
+#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
+#define ADC_CMDH_WAIT_TRIG_MASK (0x4U)
+#define ADC_CMDH_WAIT_TRIG_SHIFT (2U)
+/*! WAIT_TRIG - Wait for trigger assertion before execution.
+ * 0b0..This command will be automatically executed.
+ * 0b1..The active trigger must be asserted again before executing this command.
+ */
+#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)
+#define ADC_CMDH_LWI_MASK (0x80U)
+#define ADC_CMDH_LWI_SHIFT (7U)
+/*! LWI - Loop with Increment
+ * 0b0..Auto channel increment disabled
+ * 0b1..Auto channel increment enabled
+ */
+#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
+#define ADC_CMDH_STS_MASK (0x700U)
+#define ADC_CMDH_STS_SHIFT (8U)
+/*! STS - Sample Time Select
+ * 0b000..Minimum sample time of 3 ADCK cycles.
+ * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
+ * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
+ * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
+ * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
+ * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
+ * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
+ * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
+ */
+#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
+#define ADC_CMDH_AVGS_MASK (0x7000U)
+#define ADC_CMDH_AVGS_SHIFT (12U)
+/*! AVGS - Hardware Average Select
+ * 0b000..Single conversion.
+ * 0b001..2 conversions averaged.
+ * 0b010..4 conversions averaged.
+ * 0b011..8 conversions averaged.
+ * 0b100..16 conversions averaged.
+ * 0b101..32 conversions averaged.
+ * 0b110..64 conversions averaged.
+ * 0b111..128 conversions averaged.
+ */
+#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
+#define ADC_CMDH_LOOP_MASK (0xF0000U)
+#define ADC_CMDH_LOOP_SHIFT (16U)
+/*! LOOP - Loop Count Select
+ * 0b0000..Looping not enabled. Command executes 1 time.
+ * 0b0001..Loop 1 time. Command executes 2 times.
+ * 0b0010..Loop 2 times. Command executes 3 times.
+ * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
+ * 0b1111..Loop 15 times. Command executes 16 times.
+ */
+#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
+#define ADC_CMDH_NEXT_MASK (0xF000000U)
+#define ADC_CMDH_NEXT_SHIFT (24U)
+/*! NEXT - Next Command Select
+ * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
+ * trigger pending, begin command associated with lower priority trigger.
+ * 0b0001..Select CMD1 command buffer register as next command.
+ * 0b0010-0b1110..Select corresponding CMD command buffer register as next command
+ * 0b1111..Select CMD15 command buffer register as next command.
+ */
+#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
+/*! @} */
+
+/* The count of ADC_CMDH */
+#define ADC_CMDH_COUNT (15U)
+
+/*! @name CV - Compare Value Register */
+/*! @{ */
+#define ADC_CV_CVL_MASK (0xFFFFU)
+#define ADC_CV_CVL_SHIFT (0U)
+/*! CVL - Compare Value Low.
+ */
+#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
+#define ADC_CV_CVH_MASK (0xFFFF0000U)
+#define ADC_CV_CVH_SHIFT (16U)
+/*! CVH - Compare Value High.
+ */
+#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
+/*! @} */
+
+/* The count of ADC_CV */
+#define ADC_CV_COUNT (4U)
+
+/*! @name RESFIFO - ADC Data Result FIFO Register */
+/*! @{ */
+#define ADC_RESFIFO_D_MASK (0xFFFFU)
+#define ADC_RESFIFO_D_SHIFT (0U)
+/*! D - Data result
+ */
+#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
+#define ADC_RESFIFO_TSRC_MASK (0xF0000U)
+#define ADC_RESFIFO_TSRC_SHIFT (16U)
+/*! TSRC - Trigger Source
+ * 0b0000..Trigger source 0 initiated this conversion.
+ * 0b0001..Trigger source 1 initiated this conversion.
+ * 0b0010-0b1110..Corresponding trigger source initiated this conversion.
+ * 0b1111..Trigger source 15 initiated this conversion.
+ */
+#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
+#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
+#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
+/*! LOOPCNT - Loop count value
+ * 0b0000..Result is from initial conversion in command.
+ * 0b0001..Result is from second conversion in command.
+ * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
+ * 0b1111..Result is from 16th conversion in command.
+ */
+#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
+#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
+#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
+/*! CMDSRC - Command Buffer Source
+ * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
+ * prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
+ * 0b0001..CMD1 buffer used as control settings for this conversion.
+ * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
+ * 0b1111..CMD15 buffer used as control settings for this conversion.
+ */
+#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
+#define ADC_RESFIFO_VALID_MASK (0x80000000U)
+#define ADC_RESFIFO_VALID_SHIFT (31U)
+/*! VALID - FIFO entry is valid
+ * 0b0..FIFO is empty. Discard any read from RESFIFO.
+ * 0b1..FIFO record read from RESFIFO is valid.
+ */
+#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
+/*! @} */
+
+/* The count of ADC_RESFIFO */
+#define ADC_RESFIFO_COUNT (2U)
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral ADC0 base address */
+ #define ADC0_BASE (0x5013A000u)
+ /** Peripheral ADC0 base address */
+ #define ADC0_BASE_NS (0x4013A000u)
+ /** Peripheral ADC0 base pointer */
+ #define ADC0 ((ADC_Type *)ADC0_BASE)
+ /** Peripheral ADC0 base pointer */
+ #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS)
+ /** Array initializer of ADC peripheral base addresses */
+ #define ADC_BASE_ADDRS { ADC0_BASE }
+ /** Array initializer of ADC peripheral base pointers */
+ #define ADC_BASE_PTRS { ADC0 }
+ /** Array initializer of ADC peripheral base addresses */
+ #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS }
+ /** Array initializer of ADC peripheral base pointers */
+ #define ADC_BASE_PTRS_NS { ADC0_NS }
+#else
+ /** Peripheral ADC0 base address */
+ #define ADC0_BASE (0x4013A000u)
+ /** Peripheral ADC0 base pointer */
+ #define ADC0 ((ADC_Type *)ADC0_BASE)
+ /** Array initializer of ADC peripheral base addresses */
+ #define ADC_BASE_ADDRS { ADC0_BASE }
+ /** Array initializer of ADC peripheral base pointers */
+ #define ADC_BASE_PTRS { ADC0 }
+#endif
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS { ADC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- AHB_SECURE_CTRL Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer
+ * @{
+ */
+
+/** AHB_SECURE_CTRL - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[16];
+ __IO uint32_t ROM_MEM_RULE[4]; /**< Memory ROM Rule(n) Register, array offset: 0x10, array step: 0x4 */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t FLEXSPI0_REGION0_RULE[4]; /**< FLEXSPI0 Region 0 Rule(n) Register, array offset: 0x30, array step: 0x4 */
+ struct { /* offset: 0x40, array step: 0x10 */
+ __IO uint32_t FLEXSPI0_REGION_RULE0; /**< FLEXSPI0 Region 1 Rule 0 Register..FLEXSPI0 Region 4 Rule 0 Register, array offset: 0x40, array step: 0x10 */
+ uint8_t RESERVED_0[12];
+ } FLEXSPI0_REGION1_4_RULE[4];
+ uint8_t RESERVED_2[16];
+ __IO uint32_t RAM00_RULE[4]; /**< SRAM Partition 00 Rule(n) Register, array offset: 0x90, array step: 0x4 */
+ __IO uint32_t RAM01_RULE[4]; /**< SRAM Partition 01 Rule(n) Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_3[16];
+ __IO uint32_t RAM02_RULE[4]; /**< SRAM Partition 02 Rule(n) Register, array offset: 0xC0, array step: 0x4 */
+ __IO uint32_t RAM03_RULE[4]; /**< SRAM Partition 03 Rule(n) Register, array offset: 0xD0, array step: 0x4 */
+ uint8_t RESERVED_4[16];
+ __IO uint32_t RAM04_RULE[4]; /**< SRAM Partition 04 Rule(n) Register, array offset: 0xF0, array step: 0x4 */
+ __IO uint32_t RAM05_RULE[4]; /**< SRAM Partition 05 Rule(n) Register, array offset: 0x100, array step: 0x4 */
+ __IO uint32_t RAM06_RULE[4]; /**< SRAM Partition 06 Rule(n) Register, array offset: 0x110, array step: 0x4 */
+ __IO uint32_t RAM07_RULE[4]; /**< SRAM Partition 07 Rule(n) Register, array offset: 0x120, array step: 0x4 */
+ uint8_t RESERVED_5[16];
+ __IO uint32_t RAM08_RULE[4]; /**< SRAM Partition 08 Rule(n) Register, array offset: 0x140, array step: 0x4 */
+ __IO uint32_t RAM09_RULE[4]; /**< SRAM Partition 09 Rule(n) Register, array offset: 0x150, array step: 0x4 */
+ __IO uint32_t RAM10_RULE[4]; /**< SRAM Partition 10 Rule(n) Register, array offset: 0x160, array step: 0x4 */
+ __IO uint32_t RAM11_RULE[4]; /**< SRAM Partition 11 Rule(n) Register, array offset: 0x170, array step: 0x4 */
+ uint8_t RESERVED_6[16];
+ __IO uint32_t RAM12_RULE[4]; /**< SRAM Partition 12 Rule(n) Register, array offset: 0x190, array step: 0x4 */
+ __IO uint32_t RAM13_RULE[4]; /**< SRAM Partition 13 Rule(n) Register, array offset: 0x1A0, array step: 0x4 */
+ __IO uint32_t RAM14_RULE[4]; /**< SRAM Partition 14 Rule(n) Register, array offset: 0x1B0, array step: 0x4 */
+ __IO uint32_t RAM15_RULE[4]; /**< SRAM Partition 15 Rule(n) Register, array offset: 0x1C0, array step: 0x4 */
+ uint8_t RESERVED_7[16];
+ __IO uint32_t RAM16_RULE[4]; /**< SRAM Partition 16 Rule(n) Register, array offset: 0x1E0, array step: 0x4 */
+ __IO uint32_t RAM17_RULE[4]; /**< SRAM Partition 17 Rule(n) Register, array offset: 0x1F0, array step: 0x4 */
+ __IO uint32_t RAM18_RULE[4]; /**< SRAM Partition 18 Rule(n) Register, array offset: 0x200, array step: 0x4 */
+ __IO uint32_t RAM19_RULE[4]; /**< SRAM Partition 19 Rule(n) Register, array offset: 0x210, array step: 0x4 */
+ uint8_t RESERVED_8[16];
+ __IO uint32_t RAM20_RULE[4]; /**< SRAM Partition 20 Rule(n) Register, array offset: 0x230, array step: 0x4 */
+ __IO uint32_t RAM21_RULE[4]; /**< SRAM Partition 21 Rule(n) Register, array offset: 0x240, array step: 0x4 */
+ __IO uint32_t RAM22_RULE[4]; /**< SRAM Partition 22 Rule(n) Register, array offset: 0x250, array step: 0x4 */
+ __IO uint32_t RAM23_RULE[4]; /**< SRAM Partition 23 Rule(n) Register, array offset: 0x260, array step: 0x4 */
+ uint8_t RESERVED_9[16];
+ __IO uint32_t RAM24_RULE[4]; /**< SRAM Partition 24 Rule(n) Register, array offset: 0x280, array step: 0x4 */
+ __IO uint32_t RAM25_RULE[4]; /**< SRAM Partition 25 Rule(n) Register, array offset: 0x290, array step: 0x4 */
+ __IO uint32_t RAM26_RULE[4]; /**< SRAM Partition 26 Rule(n) Register, array offset: 0x2A0, array step: 0x4 */
+ __IO uint32_t RAM27_RULE[4]; /**< SRAM Partition 27 Rule(n) Register, array offset: 0x2B0, array step: 0x4 */
+ uint8_t RESERVED_10[16];
+ __IO uint32_t RAM28_RULE[4]; /**< SRAM Partition 28 Rule(n) Register, array offset: 0x2D0, array step: 0x4 */
+ __IO uint32_t RAM29_RULE[4]; /**< SRAM Partition 29 Rule(n) Register, array offset: 0x2E0, array step: 0x4 */
+ __IO uint32_t RAM30_RULE[4]; /**< SRAM Partition 30 Rule(n) Register, array offset: 0x2F0, array step: 0x4 */
+ __IO uint32_t RAM31_RULE[4]; /**< SRAM Partition 31 Rule(n) Register, array offset: 0x300, array step: 0x4 */
+ uint8_t RESERVED_11[16];
+ __IO uint32_t SDMA_RAM_RULE[4]; /**< Smart DMA (SDMA) RAM Rule(n) Register, array offset: 0x320, array step: 0x4 */
+ uint8_t RESERVED_12[16];
+ __IO uint32_t FLEXSPI1_REGION0_RULE[4]; /**< FlexSPI1 Region 0 Rule(n) Register, array offset: 0x340, array step: 0x4 */
+ struct { /* offset: 0x350, array step: 0x10 */
+ __IO uint32_t FLEXSPI1_REGION_RULE0; /**< FlexSPI1 Region 1 Rule 0 Register..FlexSPI1 Region 4 Rule 0 Register, array offset: 0x350, array step: 0x10 */
+ uint8_t RESERVED_0[12];
+ } FLEXSPI1_REGIONN_RULE0[4];
+ uint8_t RESERVED_13[16];
+ __IO uint32_t APB_BRIDGE_PER0_RULE0; /**< APB Bridge Peripheral 0 Rule 0 Register, offset: 0x3A0 */
+ __IO uint32_t APB_BRIDGE_PER0_RULE1; /**< APB Bridge Peripheral 0 Rule 1 Register, offset: 0x3A4 */
+ uint8_t RESERVED_14[4];
+ __IO uint32_t APB_BRIDGE_PER0_RULE3; /**< APB Bridge Peripheral 0 Rule 3 Register, offset: 0x3AC */
+ __IO uint32_t APB_BRIDGE_PER1_RULE0; /**< APB Bridge Peripheral 1 Rule 0 Register, offset: 0x3B0 */
+ __IO uint32_t APB_BRIDGE_PER1_RULE1; /**< APB Bridge Peripheral 1 Rule 1 Register, offset: 0x3B4 */
+ __IO uint32_t APB_BRIDGE_PER1_RULE2; /**< APB Bridge Peripheral 1 Rule 2 Register, offset: 0x3B8 */
+ __IO uint32_t APB_BRIDGE_PER1_RULE3; /**< APB Bridge Peripheral 1 Rule 3 Register, offset: 0x3BC */
+ __IO uint32_t AHB_PERIPH0_SLAVE_RULE0; /**< AHB Peripheral 0 Slave Rule 0 Register, offset: 0x3C0 */
+ uint8_t RESERVED_15[12];
+ __IO uint32_t AIPS_BRIDGE0_PER_RULE0; /**< AIPS Bridge Peripheral 0 Rule 0 Register, offset: 0x3D0 */
+ uint8_t RESERVED_16[12];
+ __IO uint32_t AHB_PERIPH1_SLAVE_RULE0; /**< AHB Peripheral 1 Slave Rule 0 Register, offset: 0x3E0 */
+ __IO uint32_t AHB_PERIPH1_SLAVE_RULE1; /**< AHB Peripheral 1 Slave Rule 1 Register, offset: 0x3E4 */
+ uint8_t RESERVED_17[24];
+ __IO uint32_t AIPS_BRIDGE1_PER_RULE0; /**< AIPS Bridge Peripheral 1 Rule 0 Register, offset: 0x400 */
+ __IO uint32_t AIPS_BRIDGE1_PER_RULE1; /**< AIPS Bridge Peripheral 1 Rule 1 Register, offset: 0x404 */
+ uint8_t RESERVED_18[8];
+ __IO uint32_t AHB_PERIPH2_SLAVE_RULE0; /**< AHB Peripheral 2 Slave Rule 0 Register, offset: 0x410 */
+ uint8_t RESERVED_19[12];
+ __IO uint32_t AHB_SECURE_CTRL_PERIPH_RULE0; /**< AHB Secure Control Peripheral Rule 0 Register, offset: 0x420 */
+ uint8_t RESERVED_20[12];
+ __IO uint32_t AHB_PERIPH3_SLAVE_RULE0; /**< AHB Peripheral 3 Slave Rule 0 Register, offset: 0x430 */
+ __IO uint32_t AHB_PERIPH3_SLAVE_RULE1; /**< AHB Peripheral 3 Slave Rule 1 Register, offset: 0x434 */
+ uint8_t RESERVED_21[2504];
+ __I uint32_t SEC_VIO_ADDR[18]; /**< Security Violation Address(n) Register, array offset: 0xE00, array step: 0x4 */
+ uint8_t RESERVED_22[56];
+ __I uint32_t SEC_VIO_MISC_INFO[18]; /**< Security Violation Miscellaneous Information at Address(n) Register, array offset: 0xE80, array step: 0x4 */
+ uint8_t RESERVED_23[56];
+ __IO uint32_t SEC_VIO_INFO_VALID; /**< Security Violation Info Validity for Address(n) Register, offset: 0xF00 */
+ uint8_t RESERVED_24[124];
+ __IO uint32_t SEC_GPIO_MASK0; /**< GPIO Mask for Port 0 Register, offset: 0xF80 */
+ __IO uint32_t SEC_GPIO_MASK1; /**< GPIO Mask for Port 1 Register, offset: 0xF84 */
+ __IO uint32_t SEC_GPIO_MASK2; /**< GPIO Mask for Port 2 Register, offset: 0xF88 */
+ uint8_t RESERVED_25[20];
+ __IO uint32_t DSP_INT_MASK0; /**< Secure Interrupt Mask for DSP Register, offset: 0xFA0 */
+ uint8_t RESERVED_26[24];
+ __IO uint32_t SEC_MASK_LOCK; /**< Secure Mask Lock Register, offset: 0xFBC */
+ uint8_t RESERVED_27[16];
+ __IO uint32_t MASTER_SEC_LEVEL; /**< Master Secure Level Register, offset: 0xFD0 */
+ __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< Master Secure Level Register, offset: 0xFD4 */
+ uint8_t RESERVED_28[20];
+ __IO uint32_t CM33_LOCK_REG; /**< Miscellaneous CPU0 Control Signals Register, offset: 0xFEC */
+ uint8_t RESERVED_29[8];
+ __IO uint32_t MISC_CTRL_DP_REG; /**< Secure Control Duplicate Register, offset: 0xFF8 */
+ __IO uint32_t MISC_CTRL_REG; /**< Secure Control Register, offset: 0xFFC */
+} AHB_SECURE_CTRL_Type;
+
+/* ----------------------------------------------------------------------------
+ -- AHB_SECURE_CTRL Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks
+ * @{
+ */
+
+/*! @name ROM_MEM_RULE - Memory ROM Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_ROM_MEM_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_ROM_MEM_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_ROM_MEM_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_ROM_MEM_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_ROM_MEM_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_ROM_MEM_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_ROM_MEM_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_ROM_MEM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_ROM_MEM_RULE */
+#define AHB_SECURE_CTRL_ROM_MEM_RULE_COUNT (4U)
+
+/*! @name FLEXSPI0_REGION0_RULE - FLEXSPI0 Region 0 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION0_RULE_COUNT (4U)
+
+/*! @name FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0 - FLEXSPI0 Region 1 Rule 0 Register..FLEXSPI0 Region 4 Rule 0 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE0_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE0_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE1_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE1_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE2_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE2_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE3_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_RULE3_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0 */
+#define AHB_SECURE_CTRL_FLEXSPI0_REGION1_4_RULE_FLEXSPI0_REGION_RULE0_COUNT (4U)
+
+/*! @name RAM00_RULE - SRAM Partition 00 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM00_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM00_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM00_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM00_RULE */
+#define AHB_SECURE_CTRL_RAM00_RULE_COUNT (4U)
+
+/*! @name RAM01_RULE - SRAM Partition 01 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM01_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM01_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM01_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM01_RULE */
+#define AHB_SECURE_CTRL_RAM01_RULE_COUNT (4U)
+
+/*! @name RAM02_RULE - SRAM Partition 02 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM02_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM02_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM02_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM02_RULE */
+#define AHB_SECURE_CTRL_RAM02_RULE_COUNT (4U)
+
+/*! @name RAM03_RULE - SRAM Partition 03 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM03_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM03_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM03_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM03_RULE */
+#define AHB_SECURE_CTRL_RAM03_RULE_COUNT (4U)
+
+/*! @name RAM04_RULE - SRAM Partition 04 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM04_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM04_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM04_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM04_RULE */
+#define AHB_SECURE_CTRL_RAM04_RULE_COUNT (4U)
+
+/*! @name RAM05_RULE - SRAM Partition 05 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM05_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM05_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM05_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM05_RULE */
+#define AHB_SECURE_CTRL_RAM05_RULE_COUNT (4U)
+
+/*! @name RAM06_RULE - SRAM Partition 06 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM06_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM06_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM06_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM06_RULE */
+#define AHB_SECURE_CTRL_RAM06_RULE_COUNT (4U)
+
+/*! @name RAM07_RULE - SRAM Partition 07 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM07_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM07_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM07_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM07_RULE */
+#define AHB_SECURE_CTRL_RAM07_RULE_COUNT (4U)
+
+/*! @name RAM08_RULE - SRAM Partition 08 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM08_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM08_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM08_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM08_RULE */
+#define AHB_SECURE_CTRL_RAM08_RULE_COUNT (4U)
+
+/*! @name RAM09_RULE - SRAM Partition 09 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM09_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM09_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM09_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM09_RULE */
+#define AHB_SECURE_CTRL_RAM09_RULE_COUNT (4U)
+
+/*! @name RAM10_RULE - SRAM Partition 10 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM10_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM10_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM10_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM10_RULE */
+#define AHB_SECURE_CTRL_RAM10_RULE_COUNT (4U)
+
+/*! @name RAM11_RULE - SRAM Partition 11 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM11_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM11_RULE */
+#define AHB_SECURE_CTRL_RAM11_RULE_COUNT (4U)
+
+/*! @name RAM12_RULE - SRAM Partition 12 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM12_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM12_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM12_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM12_RULE */
+#define AHB_SECURE_CTRL_RAM12_RULE_COUNT (4U)
+
+/*! @name RAM13_RULE - SRAM Partition 13 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM13_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM13_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM13_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM13_RULE */
+#define AHB_SECURE_CTRL_RAM13_RULE_COUNT (4U)
+
+/*! @name RAM14_RULE - SRAM Partition 14 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM14_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM14_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM14_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM14_RULE */
+#define AHB_SECURE_CTRL_RAM14_RULE_COUNT (4U)
+
+/*! @name RAM15_RULE - SRAM Partition 15 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM15_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM15_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM15_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM15_RULE */
+#define AHB_SECURE_CTRL_RAM15_RULE_COUNT (4U)
+
+/*! @name RAM16_RULE - SRAM Partition 16 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM16_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM16_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM16_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM16_RULE */
+#define AHB_SECURE_CTRL_RAM16_RULE_COUNT (4U)
+
+/*! @name RAM17_RULE - SRAM Partition 17 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM17_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM17_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM17_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM17_RULE */
+#define AHB_SECURE_CTRL_RAM17_RULE_COUNT (4U)
+
+/*! @name RAM18_RULE - SRAM Partition 18 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM18_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM18_RULE */
+#define AHB_SECURE_CTRL_RAM18_RULE_COUNT (4U)
+
+/*! @name RAM19_RULE - SRAM Partition 19 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM19_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM19_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM19_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM19_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM19_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM19_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM19_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM19_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM19_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM19_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM19_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM19_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM19_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM19_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM19_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM19_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM19_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM19_RULE */
+#define AHB_SECURE_CTRL_RAM19_RULE_COUNT (4U)
+
+/*! @name RAM20_RULE - SRAM Partition 20 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM20_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM20_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM20_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM20_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM20_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM20_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM20_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM20_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM20_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM20_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM20_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM20_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM20_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM20_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM20_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM20_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM20_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM20_RULE */
+#define AHB_SECURE_CTRL_RAM20_RULE_COUNT (4U)
+
+/*! @name RAM21_RULE - SRAM Partition 21 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM21_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM21_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM21_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM21_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM21_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM21_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM21_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM21_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM21_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM21_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM21_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM21_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM21_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM21_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM21_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM21_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM21_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM21_RULE */
+#define AHB_SECURE_CTRL_RAM21_RULE_COUNT (4U)
+
+/*! @name RAM22_RULE - SRAM Partition 22 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM22_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM22_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM22_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM22_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM22_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM22_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM22_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM22_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM22_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM22_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM22_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM22_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM22_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM22_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM22_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM22_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM22_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM22_RULE */
+#define AHB_SECURE_CTRL_RAM22_RULE_COUNT (4U)
+
+/*! @name RAM23_RULE - SRAM Partition 23 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM23_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM23_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM23_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM23_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM23_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM23_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM23_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM23_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM23_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM23_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM23_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM23_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM23_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM23_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM23_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM23_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM23_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM23_RULE */
+#define AHB_SECURE_CTRL_RAM23_RULE_COUNT (4U)
+
+/*! @name RAM24_RULE - SRAM Partition 24 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM24_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM24_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM24_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM24_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM24_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM24_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM24_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM24_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM24_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM24_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM24_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM24_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM24_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM24_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM24_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM24_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM24_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM24_RULE */
+#define AHB_SECURE_CTRL_RAM24_RULE_COUNT (4U)
+
+/*! @name RAM25_RULE - SRAM Partition 25 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM25_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM25_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM25_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM25_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM25_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM25_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM25_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM25_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM25_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM25_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM25_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM25_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM25_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM25_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM25_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM25_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM25_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM25_RULE */
+#define AHB_SECURE_CTRL_RAM25_RULE_COUNT (4U)
+
+/*! @name RAM26_RULE - SRAM Partition 26 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM26_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM26_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM26_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM26_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM26_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM26_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM26_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM26_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM26_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM26_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM26_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM26_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM26_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM26_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM26_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM26_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM26_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM26_RULE */
+#define AHB_SECURE_CTRL_RAM26_RULE_COUNT (4U)
+
+/*! @name RAM27_RULE - SRAM Partition 27 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM27_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM27_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM27_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM27_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM27_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM27_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM27_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM27_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM27_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM27_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM27_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM27_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM27_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM27_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM27_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM27_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM27_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM27_RULE */
+#define AHB_SECURE_CTRL_RAM27_RULE_COUNT (4U)
+
+/*! @name RAM28_RULE - SRAM Partition 28 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM28_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM28_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM28_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM28_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM28_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM28_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM28_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM28_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM28_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM28_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM28_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM28_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM28_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM28_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM28_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM28_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM28_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM28_RULE */
+#define AHB_SECURE_CTRL_RAM28_RULE_COUNT (4U)
+
+/*! @name RAM29_RULE - SRAM Partition 29 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM29_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM29_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM29_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM29_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM29_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM29_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM29_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM29_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM29_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM29_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM29_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM29_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM29_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM29_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM29_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM29_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM29_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM29_RULE */
+#define AHB_SECURE_CTRL_RAM29_RULE_COUNT (4U)
+
+/*! @name RAM30_RULE - SRAM Partition 30 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM30_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM30_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM30_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM30_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM30_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM30_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM30_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM30_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM30_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM30_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM30_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM30_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM30_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM30_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM30_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM30_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM30_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM30_RULE */
+#define AHB_SECURE_CTRL_RAM30_RULE_COUNT (4U)
+
+/*! @name RAM31_RULE - SRAM Partition 31 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM31_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM31_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM31_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM31_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM31_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM31_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM31_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_RAM31_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM31_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM31_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM31_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM31_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM31_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_RAM31_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_RAM31_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_RAM31_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_RAM31_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_RAM31_RULE */
+#define AHB_SECURE_CTRL_RAM31_RULE_COUNT (4U)
+
+/*! @name SDMA_RAM_RULE - Smart DMA (SDMA) RAM Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SDMA_RAM_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_SDMA_RAM_RULE */
+#define AHB_SECURE_CTRL_SDMA_RAM_RULE_COUNT (4U)
+
+/*! @name FLEXSPI1_REGION0_RULE - FlexSPI1 Region 0 Rule(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE4_SHIFT (16U)
+/*! RULE4 - Rule 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE5_MASK (0x300000U)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE5_SHIFT (20U)
+/*! RULE5 - Rule 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE6_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE6_SHIFT (24U)
+/*! RULE6 - Rule 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE7_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE7_SHIFT (28U)
+/*! RULE7 - Rule 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_RULE7_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGION0_RULE_COUNT (4U)
+
+/*! @name FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0 - FlexSPI1 Region 1 Rule 0 Register..FlexSPI1 Region 4 Rule 0 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE0_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE0_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE1_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE1_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE2_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE2_MASK)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE3_SHIFT)) & AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_RULE3_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0 */
+#define AHB_SECURE_CTRL_FLEXSPI1_REGIONN_RULE0_FLEXSPI1_REGION_RULE0_COUNT (4U)
+
+/*! @name APB_BRIDGE_PER0_RULE0 - APB Bridge Peripheral 0 Rule 0 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_RSTCTL_A_MASK (0x3U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_RSTCTL_A_SHIFT (0U)
+/*! RSTCTL_A - RSTCTL_A
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_RSTCTL_A(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_RSTCTL_A_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_RSTCTL_A_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_CLKCTL_A_MASK (0x30U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_CLKCTL_A_SHIFT (4U)
+/*! CLKCTL_A - CLKCTL_A
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_CLKCTL_A(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_CLKCTL_A_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_CLKCTL_A_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_SYSCTL_A_MASK (0x300U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_SYSCTL_A_SHIFT (8U)
+/*! SYSCTL_A - SYSCTL_A
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_SYSCTL_A(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_SYSCTL_A_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_SYSCTL_A_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_PVT_MASK (0x3000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_PVT_SHIFT (12U)
+/*! PVT - PVT
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_PVT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_PVT_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_PVT_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_IOCON_MASK (0x30000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_IOCON_SHIFT (16U)
+/*! IOCON - IOCON
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_IOCON_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_IOCON_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_PUF_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_PUF_SHIFT (24U)
+/*! PUF - PUF
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_PUF(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_PUF_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE0_PUF_MASK)
+/*! @} */
+
+/*! @name APB_BRIDGE_PER0_RULE1 - APB Bridge Peripheral 0 Rule 1 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE1_WWDT0_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE1_WWDT0_SHIFT (24U)
+/*! WWDT0 - WWDT0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE1_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE1_WWDT0_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE1_WWDT0_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE1_MICRO_TICK_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE1_MICRO_TICK_SHIFT (28U)
+/*! MICRO_TICK - MICRO_TICK
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE1_MICRO_TICK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE1_MICRO_TICK_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE1_MICRO_TICK_MASK)
+/*! @} */
+
+/*! @name APB_BRIDGE_PER0_RULE3 - APB Bridge Peripheral 0 Rule 3 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE3_PROBE_IS_SYNC_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE3_PROBE_IS_SYNC_SHIFT (24U)
+/*! PROBE_IS_SYNC - PROBE_IS (SYNC)
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE3_PROBE_IS_SYNC(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE3_PROBE_IS_SYNC_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE3_PROBE_IS_SYNC_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE3_PROBE_IS_XVC_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE3_PROBE_IS_XVC_SHIFT (28U)
+/*! PROBE_IS_XVC - PROBE_IS (XVC)
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE3_PROBE_IS_XVC(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE3_PROBE_IS_XVC_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER0_RULE3_PROBE_IS_XVC_MASK)
+/*! @} */
+
+/*! @name APB_BRIDGE_PER1_RULE0 - APB Bridge Peripheral 1 Rule 0 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_RSTCTL_B_MASK (0x3U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_RSTCTL_B_SHIFT (0U)
+/*! RSTCTL_B - RSTCTL_B
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_RSTCTL_B(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_RSTCTL_B_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_RSTCTL_B_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_CLKCTL_B_MASK (0x30U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_CLKCTL_B_SHIFT (4U)
+/*! CLKCTL_B - CLKCTL_B
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_CLKCTL_B(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_CLKCTL_B_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_CLKCTL_B_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_SYSCTL_B_MASK (0x300U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_SYSCTL_B_SHIFT (8U)
+/*! SYSCTL_B - SYSCTL_B
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_SYSCTL_B(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_SYSCTL_B_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_SYSCTL_B_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_GPIO_INT_MASK (0x300000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_GPIO_INT_SHIFT (20U)
+/*! GPIO_INT - GPIO_INT
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_GPIO_INT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_GPIO_INT_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_GPIO_INT_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_PERIPHERAL_MUXES_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_PERIPHERAL_MUXES_SHIFT (24U)
+/*! PERIPHERAL_MUXES - Peripheral Muxes
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_PERIPHERAL_MUXES(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_PERIPHERAL_MUXES_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_PERIPHERAL_MUXES_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_SDMA_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_SDMA_SHIFT (28U)
+/*! SDMA - Smart DMA (SDMA)
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_SDMA(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_SDMA_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE0_SDMA_MASK)
+/*! @} */
+
+/*! @name APB_BRIDGE_PER1_RULE1 - APB Bridge Peripheral 1 Rule 1 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B0_MASK (0x3U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B0_SHIFT (0U)
+/*! CT32B0 - CT32B0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B0_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B0_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B1_MASK (0x30U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B1_SHIFT (4U)
+/*! CT32B1 - CT32B1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B1_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B1_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B2_MASK (0x300U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B2_SHIFT (8U)
+/*! CT32B2 - CT32B2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B2_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B2_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B3_SHIFT (12U)
+/*! CT32B3 - CT32B3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B3_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B3_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B4_MASK (0x30000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B4_SHIFT (16U)
+/*! CT32B4 - CT32B4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B4_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_CT32B4_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_MRT0_MASK (0x300000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_MRT0_SHIFT (20U)
+/*! MRT0 - MRT0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_MRT0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_MRT0_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_MRT0_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_WWDT1_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_WWDT1_SHIFT (24U)
+/*! WWDT1 - WWDT1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_WWDT1_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_WWDT1_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_FREQMEASURE_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_FREQMEASURE_SHIFT (28U)
+/*! FREQMEASURE - FREQMEASURE
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_FREQMEASURE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_FREQMEASURE_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE1_FREQMEASURE_MASK)
+/*! @} */
+
+/*! @name APB_BRIDGE_PER1_RULE2 - APB Bridge Peripheral 1 Rule 2 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_RTC_WAKEUP_MASK (0x3U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_RTC_WAKEUP_SHIFT (0U)
+/*! RTC_WAKEUP - RTC Wakeup
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_RTC_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_RTC_WAKEUP_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_RTC_WAKEUP_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_DSI_HOST_CONTROLLER_MASK (0x30U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_DSI_HOST_CONTROLLER_SHIFT (4U)
+/*! DSI_HOST_CONTROLLER - DSI Host Controller
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_DSI_HOST_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_DSI_HOST_CONTROLLER_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_DSI_HOST_CONTROLLER_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_FLEXIO_REGISTERS_MASK (0x300U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_FLEXIO_REGISTERS_SHIFT (8U)
+/*! FLEXIO_REGISTERS - FLEXIO Registers
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_FLEXIO_REGISTERS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_FLEXIO_REGISTERS_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_FLEXIO_REGISTERS_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_CACHE_CONTROL_0_REGS_MASK (0x3000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_CACHE_CONTROL_0_REGS_SHIFT (12U)
+/*! CACHE_CONTROL_0_REGS - Cache Control 0 Registers
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_CACHE_CONTROL_0_REGS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_CACHE_CONTROL_0_REGS_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_CACHE_CONTROL_0_REGS_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_CACHE_CONTROL_1_REGS_MASK (0x30000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_CACHE_CONTROL_1_REGS_SHIFT (16U)
+/*! CACHE_CONTROL_1_REGS - Cache Control 1 Registers
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_CACHE_CONTROL_1_REGS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_CACHE_CONTROL_1_REGS_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_CACHE_CONTROL_1_REGS_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_I3C0_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_I3C0_SHIFT (24U)
+/*! I3C0 - I3C0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_I3C0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_I3C0_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_I3C0_MASK)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_I3C1_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_I3C1_SHIFT (28U)
+/*! I3C1 - I3C1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_I3C1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_I3C1_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE2_I3C1_MASK)
+/*! @} */
+
+/*! @name APB_BRIDGE_PER1_RULE3 - APB Bridge Peripheral 1 Rule 3 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE3_MRT1_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE3_MRT1_SHIFT (28U)
+/*! MRT1 - MRT1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE3_MRT1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE3_MRT1_SHIFT)) & AHB_SECURE_CTRL_APB_BRIDGE_PER1_RULE3_MRT1_MASK)
+/*! @} */
+
+/*! @name AHB_PERIPH0_SLAVE_RULE0 - AHB Peripheral 0 Slave Rule 0 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_HSGPIO_MASK (0x3U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_HSGPIO_SHIFT (0U)
+/*! HSGPIO - HSGPIO
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_HSGPIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_HSGPIO_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_HSGPIO_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_DMA0_MASK (0x30U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_DMA0_SHIFT (4U)
+/*! DMA0 - DMA 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_DMA0_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_DMA0_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_DMA1_MASK (0x300U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_DMA1_SHIFT (8U)
+/*! DMA1 - DMA 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_DMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_DMA1_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_DMA1_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM0_MASK (0x3000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM0_SHIFT (12U)
+/*! FLEXCOMM0 - FLEXCOMM 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM0_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM0_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM1_MASK (0x30000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM1_SHIFT (16U)
+/*! FLEXCOMM1 - FLEXCOMM 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM1_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM1_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM2_MASK (0x300000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM2_SHIFT (20U)
+/*! FLEXCOMM2 - FLEXCOMM 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM2_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM2_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM3_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM3_SHIFT (24U)
+/*! FLEXCOMM3 - FLEXCOMM 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM3_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_FLEXCOMM3_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_DEBUG_MAILBOX_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_DEBUG_MAILBOX_SHIFT (28U)
+/*! DEBUG_MAILBOX - DEBUG_MAILBOX
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_DEBUG_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_DEBUG_MAILBOX_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH0_SLAVE_RULE0_DEBUG_MAILBOX_MASK)
+/*! @} */
+
+/*! @name AIPS_BRIDGE0_PER_RULE0 - AIPS Bridge Peripheral 0 Rule 0 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_MU0_MASK (0x3U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_MU0_SHIFT (0U)
+/*! MU0 - MU0 (M33 PORT)
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_MU0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_MU0_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_MU0_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_MU1_MASK (0x30U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_MU1_SHIFT (4U)
+/*! MU1 - MU1 (DSP PORT)
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_MU1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_MU1_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_MU1_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_SEMAPHORE_MASK (0x300U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_SEMAPHORE_SHIFT (8U)
+/*! SEMAPHORE - Semaphore
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_SEMAPHORE_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_SEMAPHORE_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_OS_EVENT_TIMER_M33_PORT_MASK (0x3000U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_OS_EVENT_TIMER_M33_PORT_SHIFT (12U)
+/*! OS_EVENT_TIMER_M33_PORT - OS_EVENT TIMER (M33 PORT)
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_OS_EVENT_TIMER_M33_PORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_OS_EVENT_TIMER_M33_PORT_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_OS_EVENT_TIMER_M33_PORT_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_OS_EVENT_TIMER_DSP_PORT_MASK (0x30000U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_OS_EVENT_TIMER_DSP_PORT_SHIFT (16U)
+/*! OS_EVENT_TIMER_DSP_PORT - OS_EVENT TIMER (DSP PORT)
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_OS_EVENT_TIMER_DSP_PORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_OS_EVENT_TIMER_DSP_PORT_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_OS_EVENT_TIMER_DSP_PORT_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_ROM_MASK (0x300000U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_ROM_SHIFT (20U)
+/*! ROM - ROM
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_ROM(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_ROM_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE0_PER_RULE0_ROM_MASK)
+/*! @} */
+
+/*! @name AHB_PERIPH1_SLAVE_RULE0 - AHB Peripheral 1 Slave Rule 0 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_CRC_MASK (0x3U)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_CRC_SHIFT (0U)
+/*! CRC - CRC
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_CRC(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_CRC_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_CRC_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_DMIC0_MASK (0x30U)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_DMIC0_SHIFT (4U)
+/*! DMIC0 - DMIC0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_DMIC0_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_DMIC0_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM4_MASK (0x300U)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM4_SHIFT (8U)
+/*! FLEXCOMM4 - FLEXCOMM 4
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM4_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM4_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM5_MASK (0x3000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM5_SHIFT (12U)
+/*! FLEXCOMM5 - FLEXCOMM 5
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM5_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM5_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM6_MASK (0x30000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM6_SHIFT (16U)
+/*! FLEXCOMM6 - FLEXCOMM 6
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM6_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM6_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM7_MASK (0x300000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM7_SHIFT (20U)
+/*! FLEXCOMM7 - FLEXCOMM 7
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM7_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM7_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM14_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM14_SHIFT (24U)
+/*! FLEXCOMM14 - FLEXCOMM 14
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM14(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM14_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM14_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM15_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM15_SHIFT (28U)
+/*! FLEXCOMM15 - FLEXCOMM 15
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM15(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM15_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE0_FLEXCOMM15_MASK)
+/*! @} */
+
+/*! @name AHB_PERIPH1_SLAVE_RULE1 - AHB Peripheral 1 Slave Rule 1 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE1_FLEXCOMM16_MASK (0x3U)
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE1_FLEXCOMM16_SHIFT (0U)
+/*! FLEXCOMM16 - FLEXCOMM 16
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE1_FLEXCOMM16(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE1_FLEXCOMM16_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH1_SLAVE_RULE1_FLEXCOMM16_MASK)
+/*! @} */
+
+/*! @name AIPS_BRIDGE1_PER_RULE0 - AIPS Bridge Peripheral 1 Rule 0 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_0_MASK (0x3U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_0_SHIFT (0U)
+/*! OTP_CONTROLLER_0 - OTP Controller 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_0_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_0_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_1_MASK (0x30U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_1_SHIFT (4U)
+/*! OTP_CONTROLLER_1 - OTP Controller 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_1_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_1_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_2_MASK (0x300U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_2_SHIFT (8U)
+/*! OTP_CONTROLLER_2 - OTP Controller 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_2_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_2_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_3_SHIFT (12U)
+/*! OTP_CONTROLLER_3 - OTP Controller 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_3_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_OTP_CONTROLLER_3_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_FLEXSPI0_REGISTERS_MASK (0x30000U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_FLEXSPI0_REGISTERS_SHIFT (16U)
+/*! FLEXSPI0_REGISTERS - FLEXSPI0 Registers
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_FLEXSPI0_REGISTERS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_FLEXSPI0_REGISTERS_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_FLEXSPI0_REGISTERS_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_PMC_PMU_CONTROL_MASK (0x300000U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_PMC_PMU_CONTROL_SHIFT (20U)
+/*! PMC_PMU_CONTROL - PMC (PMU CONTROL)
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_PMC_PMU_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_PMC_PMU_CONTROL_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_PMC_PMU_CONTROL_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_SDIO0_REGISTERS_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_SDIO0_REGISTERS_SHIFT (24U)
+/*! SDIO0_REGISTERS - SDIO 0 Registers
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_SDIO0_REGISTERS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_SDIO0_REGISTERS_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_SDIO0_REGISTERS_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_SDIO1_REGISTERS_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_SDIO1_REGISTERS_SHIFT (28U)
+/*! SDIO1_REGISTERS - SDIO 1 Registers
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_SDIO1_REGISTERS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_SDIO1_REGISTERS_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE0_SDIO1_REGISTERS_MASK)
+/*! @} */
+
+/*! @name AIPS_BRIDGE1_PER_RULE1 - AIPS Bridge Peripheral 1 Rule 1 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_RNG_MASK (0x3U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_RNG_SHIFT (0U)
+/*! RNG - RNG (Random Number Generator)
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_RNG(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_RNG_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_RNG_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_ACMP0_MASK (0x30U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_ACMP0_SHIFT (4U)
+/*! ACMP0 - ACMP 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_ACMP0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_ACMP0_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_ACMP0_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_ADC0_MASK (0x300U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_ADC0_SHIFT (8U)
+/*! ADC0 - ADC 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_ADC0_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_ADC0_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_HS_USB_PHY_MASK (0x3000U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_HS_USB_PHY_SHIFT (12U)
+/*! HS_USB_PHY - HS USB PHY
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_HS_USB_PHY(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_HS_USB_PHY_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_HS_USB_PHY_MASK)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_FLEXSPI1_REGISTERS_MASK (0x30000U)
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_FLEXSPI1_REGISTERS_SHIFT (16U)
+/*! FLEXSPI1_REGISTERS - FLEXSPI1 Registers
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_FLEXSPI1_REGISTERS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_FLEXSPI1_REGISTERS_SHIFT)) & AHB_SECURE_CTRL_AIPS_BRIDGE1_PER_RULE1_FLEXSPI1_REGISTERS_MASK)
+/*! @} */
+
+/*! @name AHB_PERIPH2_SLAVE_RULE0 - AHB Peripheral 2 Slave Rule 0 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_USB_HS_RAM_MASK (0x3U)
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_USB_HS_RAM_SHIFT (0U)
+/*! USB_HS_RAM - USB HS RAM
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_USB_HS_RAM(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_USB_HS_RAM_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_USB_HS_RAM_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_USB_HS_DEV_MASK (0x30U)
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_USB_HS_DEV_SHIFT (4U)
+/*! USB_HS_DEV - USB HS DEV
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_USB_HS_DEV(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_USB_HS_DEV_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_USB_HS_DEV_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_USB_HS_HOST_MASK (0x300U)
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_USB_HS_HOST_SHIFT (8U)
+/*! USB_HS_HOST - USB HS HOST
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_USB_HS_HOST(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_USB_HS_HOST_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_USB_HS_HOST_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_SCT_MASK (0x3000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_SCT_SHIFT (12U)
+/*! SCT - SCT
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_SCT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_SCT_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH2_SLAVE_RULE0_SCT_MASK)
+/*! @} */
+
+/*! @name AHB_SECURE_CTRL_PERIPH_RULE0 - AHB Secure Control Peripheral Rule 0 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE0_MASK (0x3U)
+#define AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE0_SHIFT (0U)
+/*! RULE0 - Rule 0
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE0_SHIFT)) & AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE0_MASK)
+#define AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE1_MASK (0x30U)
+#define AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE1_SHIFT (4U)
+/*! RULE1 - Rule 1
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE1_SHIFT)) & AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE1_MASK)
+#define AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE2_MASK (0x300U)
+#define AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE2_SHIFT (8U)
+/*! RULE2 - Rule 2
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE2_SHIFT)) & AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE2_MASK)
+#define AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE3_MASK (0x3000U)
+#define AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE3_SHIFT (12U)
+/*! RULE3 - Rule 3
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE3_SHIFT)) & AHB_SECURE_CTRL_AHB_SECURE_CTRL_PERIPH_RULE0_RULE3_MASK)
+/*! @} */
+
+/*! @name AHB_PERIPH3_SLAVE_RULE0 - AHB Peripheral 3 Slave Rule 0 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_POWERQUAD_MASK (0x3U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_POWERQUAD_SHIFT (0U)
+/*! POWERQUAD - POWERQUAD
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_POWERQUAD_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_POWERQUAD_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_CASPER_MASK (0x30U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_CASPER_SHIFT (4U)
+/*! CASPER - CASPER
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_CASPER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_CASPER_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_CASPER_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_CASPER_RAM_MASK (0x300U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_CASPER_RAM_SHIFT (8U)
+/*! CASPER_RAM - CASPER RAM
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_CASPER_RAM(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_CASPER_RAM_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_CASPER_RAM_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_SECURE_GPIO_MASK (0x3000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_SECURE_GPIO_SHIFT (12U)
+/*! SECURE_GPIO - Secure GPIO
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_SECURE_GPIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_SECURE_GPIO_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_SECURE_GPIO_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_HASH_MASK (0x30000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_HASH_SHIFT (16U)
+/*! HASH - HASH
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_HASH_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_HASH_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_FLEXCOMM8_MASK (0x300000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_FLEXCOMM8_SHIFT (20U)
+/*! FLEXCOMM8 - FLEXCOMM 8
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_FLEXCOMM8_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_FLEXCOMM8_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_FLEXCOMM9_MASK (0x3000000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_FLEXCOMM9_SHIFT (24U)
+/*! FLEXCOMM9 - FLEXCOMM 9
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_FLEXCOMM9_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_FLEXCOMM9_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_FLEXCOMM10_MASK (0x30000000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_FLEXCOMM10_SHIFT (28U)
+/*! FLEXCOMM10 - FLEXCOMM 10
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_FLEXCOMM10_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE0_FLEXCOMM10_MASK)
+/*! @} */
+
+/*! @name AHB_PERIPH3_SLAVE_RULE1 - AHB Peripheral 3 Slave Rule 1 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_FLEXCOMM11_MASK (0x3U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_FLEXCOMM11_SHIFT (0U)
+/*! FLEXCOMM11 - FLEXCOMM 11
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_FLEXCOMM11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_FLEXCOMM11_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_FLEXCOMM11_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_FLEXCOMM12_MASK (0x30U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_FLEXCOMM12_SHIFT (4U)
+/*! FLEXCOMM12 - FLEXCOMM 12
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_FLEXCOMM12(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_FLEXCOMM12_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_FLEXCOMM12_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_FLEXCOMM13_MASK (0x300U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_FLEXCOMM13_SHIFT (8U)
+/*! FLEXCOMM13 - FLEXCOMM 13
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_FLEXCOMM13(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_FLEXCOMM13_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_FLEXCOMM13_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_LCDIF_MASK (0x3000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_LCDIF_SHIFT (12U)
+/*! LCDIF - LCDIF
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_LCDIF_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_LCDIF_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_GPU_MASK (0x30000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_GPU_SHIFT (16U)
+/*! GPU - GPU
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_GPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_GPU_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_GPU_MASK)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_AXI_SWITCH_MASK (0x300000U)
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_AXI_SWITCH_SHIFT (20U)
+/*! AXI_SWITCH - AXI Switch
+ * 0b00..Non-secure and non-privilege user access allowed
+ * 0b01..Non-secure and privilege access allowed
+ * 0b10..Secure and non-privilege user access allowed
+ * 0b11..Secure and privilege user access allowed
+ */
+#define AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_AXI_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_AXI_SWITCH_SHIFT)) & AHB_SECURE_CTRL_AHB_PERIPH3_SLAVE_RULE1_AXI_SWITCH_MASK)
+/*! @} */
+
+/*! @name SEC_VIO_ADDR - Security Violation Address(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_MASK (0xFFFFFFFFU)
+#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_SHIFT (0U)
+/*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */
+#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (18U)
+
+/*! @name SEC_VIO_MISC_INFO - Security Violation Miscellaneous Information at Address(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U)
+/*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator
+ * 0b0..Read access
+ * 0b1..Write access
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U)
+/*! SEC_VIO_INFO_DATA_ACCESS - Security Violation Info Data Access
+ * 0b0..Code
+ * 0b1..Data
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U)
+/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - Security Violation Info Master Security Level
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U)
+/*! SEC_VIO_INFO_MASTER - Security violation master number
+ * 0b0000..M33 Code
+ * 0b0001..M33 System
+ * 0b0010..Powerquad
+ * 0b0011..DSP
+ * 0b0100..DMA0
+ * 0b0101..DMA1
+ * 0b0110..SDMA Instruction
+ * 0b0111..SDMA Data
+ * 0b1000..SDIO0
+ * 0b1001..SDIO1
+ * 0b1010..HASH
+ * 0b1011..GPU
+ * 0b1100..Reserved
+ * 0b1101..Reserved
+ * 0b1110..Reserved
+ * 0b1111..Reserved
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK)
+/*! @} */
+
+/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (18U)
+
+/*! @name SEC_VIO_INFO_VALID - Security Violation Info Validity for Address(n) Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U)
+/*! VIO_INFO_VALID0 - Violation information valid flag for AHB port 0
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U)
+/*! VIO_INFO_VALID1 - Violation information valid flag for AHB port 1
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U)
+/*! VIO_INFO_VALID2 - Violation information valid flag for AHB port 2
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U)
+/*! VIO_INFO_VALID3 - Violation information valid flag for AHB port 3
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U)
+/*! VIO_INFO_VALID4 - Violation information valid flag for AHB port 4
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U)
+/*! VIO_INFO_VALID5 - Violation information valid flag for AHB port 5
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U)
+/*! VIO_INFO_VALID6 - Violation information valid flag for AHB port 6
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U)
+/*! VIO_INFO_VALID7 - Violation information valid flag for AHB port 7
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U)
+/*! VIO_INFO_VALID8 - Violation information valid flag for AHB port 8
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U)
+/*! VIO_INFO_VALID9 - Violation information valid flag for AHB port 9
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U)
+/*! VIO_INFO_VALID10 - Violation information valid flag for AHB port 10
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U)
+/*! VIO_INFO_VALID11 - Violation information valid flag for AHB port 11
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U)
+/*! VIO_INFO_VALID12 - Violation information valid flag for AHB port 12
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK (0x2000U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT (13U)
+/*! VIO_INFO_VALID13 - Violation information valid flag for AHB port 13
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK (0x4000U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT (14U)
+/*! VIO_INFO_VALID14 - Violation information valid flag for AHB port 14
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK (0x8000U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT (15U)
+/*! VIO_INFO_VALID15 - Violation information valid flag for AHB port 15
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK (0x10000U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT (16U)
+/*! VIO_INFO_VALID16 - Violation information valid flag for AHB port 16
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK (0x20000U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT (17U)
+/*! VIO_INFO_VALID17 - Violation information valid flag for AHB port 17
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK (0x40000U)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT (18U)
+/*! VIO_INFO_VALID18 - Violation information valid flag for AHB port 18
+ * 0b0..Not valid
+ * 0b1..Valid
+ */
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK)
+/*! @} */
+
+/*! @name SEC_GPIO_MASK0 - GPIO Mask for Port 0 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U)
+/*! PIO0_PIN0_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U)
+/*! PIO0_PIN1_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U)
+/*! PIO0_PIN2_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U)
+/*! PIO0_PIN3_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U)
+/*! PIO0_PIN4_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U)
+/*! PIO0_PIN5_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U)
+/*! PIO0_PIN6_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U)
+/*! PIO0_PIN7_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U)
+/*! PIO0_PIN8_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U)
+/*! PIO0_PIN9_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U)
+/*! PIO0_PIN10_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U)
+/*! PIO0_PIN11_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U)
+/*! PIO0_PIN12_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U)
+/*! PIO0_PIN13_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U)
+/*! PIO0_PIN14_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U)
+/*! PIO0_PIN15_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U)
+/*! PIO0_PIN16_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U)
+/*! PIO0_PIN17_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U)
+/*! PIO0_PIN18_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U)
+/*! PIO0_PIN19_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U)
+/*! PIO0_PIN20_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U)
+/*! PIO0_PIN21_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U)
+/*! PIO0_PIN22_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U)
+/*! PIO0_PIN23_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U)
+/*! PIO0_PIN24_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U)
+/*! PIO0_PIN25_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U)
+/*! PIO0_PIN26_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U)
+/*! PIO0_PIN27_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U)
+/*! PIO0_PIN28_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U)
+/*! PIO0_PIN29_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U)
+/*! PIO0_PIN30_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U)
+/*! PIO0_PIN31_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK)
+/*! @} */
+
+/*! @name SEC_GPIO_MASK1 - GPIO Mask for Port 1 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U)
+/*! PIO1_PIN0_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U)
+/*! PIO1_PIN1_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U)
+/*! PIO1_PIN2_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U)
+/*! PIO1_PIN3_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U)
+/*! PIO1_PIN4_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U)
+/*! PIO1_PIN5_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U)
+/*! PIO1_PIN6_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U)
+/*! PIO1_PIN7_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U)
+/*! PIO1_PIN8_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U)
+/*! PIO1_PIN9_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U)
+/*! PIO1_PIN10_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U)
+/*! PIO1_PIN11_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U)
+/*! PIO1_PIN12_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U)
+/*! PIO1_PIN13_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U)
+/*! PIO1_PIN14_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U)
+/*! PIO1_PIN15_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U)
+/*! PIO1_PIN16_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U)
+/*! PIO1_PIN17_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U)
+/*! PIO1_PIN18_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U)
+/*! PIO1_PIN19_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U)
+/*! PIO1_PIN20_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U)
+/*! PIO1_PIN21_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U)
+/*! PIO1_PIN22_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U)
+/*! PIO1_PIN23_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U)
+/*! PIO1_PIN24_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U)
+/*! PIO1_PIN25_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U)
+/*! PIO1_PIN26_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U)
+/*! PIO1_PIN27_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U)
+/*! PIO1_PIN28_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U)
+/*! PIO1_PIN29_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U)
+/*! PIO1_PIN30_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U)
+/*! PIO1_PIN31_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK)
+/*! @} */
+
+/*! @name SEC_GPIO_MASK2 - GPIO Mask for Port 2 Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_MASK (0x1U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_SHIFT (0U)
+/*! PIO2_PIN0_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_MASK (0x2U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_SHIFT (1U)
+/*! PIO2_PIN1_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_MASK (0x4U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_SHIFT (2U)
+/*! PIO2_PIN2_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_MASK (0x8U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_SHIFT (3U)
+/*! PIO2_PIN3_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_MASK (0x10U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_SHIFT (4U)
+/*! PIO2_PIN4_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_MASK (0x20U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_SHIFT (5U)
+/*! PIO2_PIN5_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_MASK (0x40U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_SHIFT (6U)
+/*! PIO2_PIN6_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_MASK (0x80U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_SHIFT (7U)
+/*! PIO2_PIN7_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_MASK (0x100U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_SHIFT (8U)
+/*! PIO2_PIN8_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_MASK (0x200U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_SHIFT (9U)
+/*! PIO2_PIN9_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_MASK (0x400U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_SHIFT (10U)
+/*! PIO2_PIN10_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_MASK (0x800U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_SHIFT (11U)
+/*! PIO2_PIN11_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_MASK (0x1000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_SHIFT (12U)
+/*! PIO2_PIN12_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_MASK (0x2000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_SHIFT (13U)
+/*! PIO2_PIN13_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_MASK (0x4000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_SHIFT (14U)
+/*! PIO2_PIN14_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_MASK (0x8000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_SHIFT (15U)
+/*! PIO2_PIN15_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_MASK (0x10000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_SHIFT (16U)
+/*! PIO2_PIN16_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_MASK (0x20000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_SHIFT (17U)
+/*! PIO2_PIN17_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_MASK (0x40000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_SHIFT (18U)
+/*! PIO2_PIN18_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_MASK (0x80000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_SHIFT (19U)
+/*! PIO2_PIN19_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_MASK (0x100000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_SHIFT (20U)
+/*! PIO2_PIN20_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_MASK (0x200000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_SHIFT (21U)
+/*! PIO2_PIN21_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_MASK (0x400000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_SHIFT (22U)
+/*! PIO2_PIN22_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_MASK (0x800000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_SHIFT (23U)
+/*! PIO2_PIN23_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_MASK (0x1000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_SHIFT (24U)
+/*! PIO2_PIN24_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_MASK (0x2000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_SHIFT (25U)
+/*! PIO2_PIN25_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_MASK (0x4000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_SHIFT (26U)
+/*! PIO2_PIN26_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_MASK (0x8000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_SHIFT (27U)
+/*! PIO2_PIN27_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_MASK (0x10000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_SHIFT (28U)
+/*! PIO2_PIN28_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_MASK (0x20000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_SHIFT (29U)
+/*! PIO2_PIN29_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_MASK (0x40000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_SHIFT (30U)
+/*! PIO2_PIN30_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_MASK (0x80000000U)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_SHIFT (31U)
+/*! PIO2_PIN31_SEC_MASK - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_MASK)
+/*! @} */
+
+/*! @name DSP_INT_MASK0 - Secure Interrupt Mask for DSP Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT0_MASK (0x20U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT0_SHIFT (5U)
+/*! PMUX_OUT0 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT0_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT0_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT1_MASK (0x40U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT1_SHIFT (6U)
+/*! PMUX_OUT1 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT1_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT1_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT2_MASK (0x80U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT2_SHIFT (7U)
+/*! PMUX_OUT2 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT2_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT2_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT3_MASK (0x100U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT3_SHIFT (8U)
+/*! PMUX_OUT3 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT3_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT3_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT4_MASK (0x200U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT4_SHIFT (9U)
+/*! PMUX_OUT4 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT4_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT4_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT5_MASK (0x400U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT5_SHIFT (10U)
+/*! PMUX_OUT5 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT5_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT5_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT6_MASK (0x800U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT6_SHIFT (11U)
+/*! PMUX_OUT6 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT6_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT6_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT7_MASK (0x1000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT7_SHIFT (12U)
+/*! PMUX_OUT7 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT7_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT7_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT8_MASK (0x2000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT8_SHIFT (13U)
+/*! PMUX_OUT8 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT8_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT8_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT9_MASK (0x4000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT9_SHIFT (14U)
+/*! PMUX_OUT9 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT9_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT9_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT10_MASK (0x8000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT10_SHIFT (15U)
+/*! PMUX_OUT10 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT10_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT10_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT11_MASK (0x10000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT11_SHIFT (16U)
+/*! PMUX_OUT11 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT11_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT11_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT12_MASK (0x20000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT12_SHIFT (17U)
+/*! PMUX_OUT12 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT12(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT12_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT12_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT13_MASK (0x40000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT13_SHIFT (18U)
+/*! PMUX_OUT13 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT13(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT13_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT13_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT14_MASK (0x80000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT14_SHIFT (19U)
+/*! PMUX_OUT14 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT14(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT14_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT14_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT15_MASK (0x100000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT15_SHIFT (20U)
+/*! PMUX_OUT15 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT15(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT15_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT15_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT16_MASK (0x200000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT16_SHIFT (21U)
+/*! PMUX_OUT16 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT16(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT16_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT16_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT17_MASK (0x400000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT17_SHIFT (22U)
+/*! PMUX_OUT17 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT17(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT17_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT17_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT18_MASK (0x800000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT18_SHIFT (23U)
+/*! PMUX_OUT18 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT18(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT18_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT18_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT19_MASK (0x1000000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT19_SHIFT (24U)
+/*! PMUX_OUT19 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT19(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT19_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT19_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT20_MASK (0x2000000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT20_SHIFT (25U)
+/*! PMUX_OUT20 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT20(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT20_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT20_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT21_MASK (0x4000000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT21_SHIFT (26U)
+/*! PMUX_OUT21 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT21(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT21_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT21_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT22_MASK (0x8000000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT22_SHIFT (27U)
+/*! PMUX_OUT22 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT22(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT22_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT22_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT23_MASK (0x10000000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT23_SHIFT (28U)
+/*! PMUX_OUT23 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT23(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT23_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT23_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT24_MASK (0x20000000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT24_SHIFT (29U)
+/*! PMUX_OUT24 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT24(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT24_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT24_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT25_MASK (0x40000000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT25_SHIFT (30U)
+/*! PMUX_OUT25 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT25(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT25_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT25_MASK)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT26_MASK (0x80000000U)
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT26_SHIFT (31U)
+/*! PMUX_OUT26 - Mask bit
+ * 0b0..Masked
+ * 0b1..Not masked
+ */
+#define AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT26(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT26_SHIFT)) & AHB_SECURE_CTRL_DSP_INT_MASK0_PMUX_OUT26_MASK)
+/*! @} */
+
+/*! @name SEC_MASK_LOCK - Secure Mask Lock Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U)
+/*! SEC_GPIO_MASK0_LOCK - Secure GPIO _MASK0 Lock
+ * 0b00..Reserved
+ * 0b01..SEC_GPIO_MASK0 cannot be written
+ * 0b10..SEC_GPIO_MASK0 can be written
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U)
+/*! SEC_GPIO_MASK1_LOCK - Secure GPIO _MASK1 Lock
+ * 0b00..Reserved
+ * 0b01..SEC_GPIO_MASK1 cannot be written
+ * 0b10..SEC_GPIO_MASK1 can be written
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_MASK (0x30U)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_SHIFT (4U)
+/*! SEC_GPIO_MASK2_LOCK - Secure GPIO _MASK2 Lock
+ * 0b00..Reserved
+ * 0b01..SEC_GPIO_MASK2 cannot be written
+ * 0b10..SEC_GPIO_MASK2 can be written
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_MASK)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_MASK (0xC0U)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_SHIFT (6U)
+/*! SEC_GPIO_MASK3_LOCK - Secure GPIO _MASK3 Lock
+ * 0b00..Reserved
+ * 0b01..SEC_GPIO_MASK3 cannot be written
+ * 0b10..SEC_GPIO_MASK3 can be written
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_MASK)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK4_LOCK_MASK (0x300U)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK4_LOCK_SHIFT (8U)
+/*! SEC_GPIO_MASK4_LOCK - SEC_GPIO_MASK4 Lock
+ * 0b00..Reserved
+ * 0b01..SEC_GPIO_MASK4_LOCK cannot be written
+ * 0b10..SEC_GPIO_MASK4_LOCK can be written
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK4_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK4_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK4_LOCK_MASK)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK5_LOCK_MASK (0xC00U)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK5_LOCK_SHIFT (10U)
+/*! SEC_GPIO_MASK5_LOCK - SEC_GPIO_MASK5 Lock
+ * 0b00..Reserved
+ * 0b01..SEC_GPIO_MASK5 cannot be written
+ * 0b10..SEC_GPIO_MASK5 can be written
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK5_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK5_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK5_LOCK_MASK)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK6_LOCK_MASK (0x3000U)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK6_LOCK_SHIFT (12U)
+/*! SEC_GPIO_MASK6_LOCK - SEC_GPIO_MASK6 Lock
+ * 0b00..Reserved
+ * 0b01..SEC_GPIO_MASK6 cannot be written
+ * 0b10..SEC_GPIO_MASK6 can be written
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK6_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK6_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK6_LOCK_MASK)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK7_LOCK_MASK (0xC000U)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK7_LOCK_SHIFT (14U)
+/*! SEC_GPIO_MASK7_LOCK - SEC_GPIO_MASK7 Lock
+ * 0b00..Reserved
+ * 0b01..SEC_GPIO_MASK7 cannot be written
+ * 0b10..SEC_GPIO_MASK7 can be written
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK7_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK7_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK7_LOCK_MASK)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_DSP_INT_MASK_LOCK_MASK (0x30000U)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_DSP_INT_MASK_LOCK_SHIFT (16U)
+/*! SEC_DSP_INT_MASK_LOCK - SEC_DSP_INT_MASK Lock
+ * 0b00..Reserved
+ * 0b01..SEC_DSP_INT_MASK cannot be written
+ * 0b10..SEC_DSP_INT_MASK can be written
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_DSP_INT_MASK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_DSP_INT_MASK_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_DSP_INT_MASK_LOCK_MASK)
+/*! @} */
+
+/*! @name MASTER_SEC_LEVEL - Master Secure Level Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0x30U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (4U)
+/*! PQ - Power Quad
+ * 0b00..Non-secure and non-privileged Master
+ * 0b01..Non-secure and privileged Master
+ * 0b10..Secure and non-privileged Master
+ * 0b11..Secure and privileged Master
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DSP_MASK (0xC0U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DSP_SHIFT (6U)
+/*! DSP - DSP
+ * 0b00..Non-secure and non-privileged Master
+ * 0b01..Non-secure and privileged Master
+ * 0b10..Secure and non-privileged Master
+ * 0b11..Secure and privileged Master
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DSP(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DSP_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DSP_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA0_MASK (0x300U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA0_SHIFT (8U)
+/*! DMA0 - DMA 0
+ * 0b00..Non-secure and non-privileged Master
+ * 0b01..Non-secure and privileged Master
+ * 0b10..Secure and non-privileged Master
+ * 0b11..Secure and privileged Master
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA0_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA1_MASK (0xC00U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA1_SHIFT (10U)
+/*! DMA1 - DMA 1
+ * 0b00..Non-secure and non-privileged Master
+ * 0b01..Non-secure and privileged Master
+ * 0b10..Secure and non-privileged Master
+ * 0b11..Secure and privileged Master
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_DMA1_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA_I_MASK (0x3000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA_I_SHIFT (12U)
+/*! SDMA_I - Smart DMA (SDMA) Instruction
+ * 0b00..Non-secure and non-privileged Master
+ * 0b01..Non-secure and privileged Master
+ * 0b10..Secure and non-privileged Master
+ * 0b11..Secure and privileged Master
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA_I(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA_I_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA_I_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA_D_MASK (0xC000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA_D_SHIFT (14U)
+/*! SDMA_D - Smart DMA (SDMA) Data
+ * 0b00..Non-secure and non-privileged Master
+ * 0b01..Non-secure and privileged Master
+ * 0b10..Secure and non-privileged Master
+ * 0b11..Secure and privileged Master
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA_D(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA_D_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA_D_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO0_MASK (0x30000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO0_SHIFT (16U)
+/*! SDIO0 - SDIO 0
+ * 0b00..Non-secure and non-privileged Master
+ * 0b01..Non-secure and privileged Master
+ * 0b10..Secure and non-privileged Master
+ * 0b11..Secure and privileged Master
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO0_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO1_MASK (0xC0000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO1_SHIFT (18U)
+/*! SDIO1 - SDIO 1
+ * 0b00..Non-secure and non-privileged Master
+ * 0b01..Non-secure and privileged Master
+ * 0b10..Secure and non-privileged Master
+ * 0b11..Secure and privileged Master
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO1_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_GPU_MASK (0x300000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_GPU_SHIFT (20U)
+/*! GPU - GPU
+ * 0b00..Non-secure and non-privileged Master
+ * 0b01..Non-secure and privileged Master
+ * 0b10..Secure and non-privileged Master
+ * 0b11..Secure and privileged Master
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_GPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_GPU_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_GPU_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U)
+/*! MASTER_SEC_LEVEL_LOCK - Master Security Level Lock
+ * 0b00..Reserved
+ * 0b01..Lock writing to this register, including these (MASTER_SEC_LEVEL_LOCK) bits
+ * 0b10..This register can be written
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK)
+/*! @} */
+
+/*! @name MASTER_SEC_ANTI_POL_REG - Master Secure Level Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0x30U)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (4U)
+/*! PQ - Power Quad
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_DSP_MASK (0xC0U)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_DSP_SHIFT (6U)
+/*! DSP - DSP
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_DSP(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_DSP_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_DSP_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_DMA0_MASK (0x300U)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_DMA0_SHIFT (8U)
+/*! DMA0 - DMA 0
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_DMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_DMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_DMA0_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_DMA1_MASK (0xC00U)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_DMA1_SHIFT (10U)
+/*! DMA1 - DMA 1
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_DMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_DMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_DMA1_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA_I_MASK (0x3000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA_I_SHIFT (12U)
+/*! SDMA_I - Smart DMA (SDMA) Instruction
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA_I(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA_I_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA_I_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA_D_MASK (0xC000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA_D_SHIFT (14U)
+/*! SDMA_D - Smart DMA (SDMA) Data
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA_D(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA_D_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA_D_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO0_MASK (0x30000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO0_SHIFT (16U)
+/*! SDIO0 - SDIO 0
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO0_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO1_MASK (0xC0000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO1_SHIFT (18U)
+/*! SDIO1 - SDIO 1
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO1_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_GPU_MASK (0x300000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_GPU_SHIFT (20U)
+/*! GPU - GPU
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_GPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_GPU_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_GPU_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U)
+/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - Master Security Level Antipole Lock
+ * 0b00..Reserved
+ * 0b01..Lock writing to this register, including these (MASTER_SEC_LEVEL_ANTIPOL_LOCK) bits
+ * 0b10..This register can be written
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK)
+/*! @} */
+
+/*! @name CM33_LOCK_REG - Miscellaneous CPU0 Control Signals Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)
+/*! LOCK_NS_VTOR - Lock Non-Secure VTOR
+ * 0b00..Reserved
+ * 0b01..Locks Non-Secure VTOR
+ * 0b10..Non-Secure VTOR can be used
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)
+/*! LOCK_NS_MPU - Lock Non-Secure MPU
+ * 0b00..Reserved
+ * 0b01..Locks Non-Secure MPU
+ * 0b10..Non-Secure MPU can be used
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTOR_MASK (0x30U)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTOR_SHIFT (4U)
+/*! LOCK_S_VTOR - Lock Secure VTOR
+ * 0b00..Reserved
+ * 0b01..Locks Secure VTOR
+ * 0b10..Secure VTOR can be used
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTOR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTOR_MASK)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK (0xC0U)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT (6U)
+/*! LOCK_S_MPU - Lock Secure MPU
+ * 0b00..Reserved
+ * 0b01..Locks Secure MPU
+ * 0b10..Secure MPU can be used
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK (0x300U)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT (8U)
+/*! LOCK_SAU - Lock SAU
+ * 0b00..Reserved
+ * 0b01..SAU is locked
+ * 0b10..SAU can be used
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U)
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U)
+/*! CM33_LOCK_REG_LOCK - Lock CM33 Lock Register
+ * 0b00..Reserved
+ * 0b01..Does not allow writing to this register
+ * 0b10..Allows writing to this register
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK)
+/*! @} */
+
+/*! @name MISC_CTRL_DP_REG - Secure Control Duplicate Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U)
+/*! WRITE_LOCK - Write Lock
+ * 0b00..Reserved
+ * 0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed
+ * 0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
+/*! ENABLE_SECURE_CHECKING - Enable Secure Checking
+ * 0b00..Reserved
+ * 0b01..Enabled (restrictive mode)
+ * 0b10..Disabled
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
+/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking
+ * 0b00..Reserved
+ * 0b01..Enabled (restrictive mode)
+ * 0b10..Disabled
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
+/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking
+ * 0b00..Reserved
+ * 0b01..Enabled (restrictive mode)
+ * 0b10..Disabled
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
+/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort
+ * 0b00..Reserved
+ * 0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq
+ * (interrupt request) will still be asserted and serviced by ISR.
+ * 0b10..The violation detected by the secure checker will cause an abort.
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)
+/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable Simple Master Strict Mode
+ * 0b00..Reserved
+ * 0b01..Can access memories and peripherals at the same level or below that level
+ * 0b10..Can access memories and peripherals at same level only
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)
+/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable Smart Master Strict Mode
+ * 0b00..Reserved
+ * 0b01..Can access memories and peripherals at the same level or below that level
+ * 0b10..Can access memories and peripherals at same level only
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U)
+/*! IDAU_ALL_NS - IDAU All Non-Secure
+ * 0b00..Reserved
+ * 0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory.
+ * 0b10..IDAU is enabled (restrictive mode)
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK)
+/*! @} */
+
+/*! @name MISC_CTRL_REG - Secure Control Register */
+/*! @{ */
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U)
+/*! WRITE_LOCK - Write Lock
+ * 0b00..Reserved
+ * 0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed
+ * 0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
+/*! ENABLE_SECURE_CHECKING - Enable Secure Checking
+ * 0b00..Reserved
+ * 0b01..Enabled (restrictive mode)
+ * 0b10..Disabled
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
+/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking
+ * 0b00..Reserved
+ * 0b01..Enabled (restrictive mode)
+ * 0b10..Disabled
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
+/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking
+ * 0b00..Reserved
+ * 0b01..Enabled (restrictive mode)
+ * 0b10..Disabled
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
+/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort
+ * 0b00..Reserved
+ * 0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq
+ * (interrupt request) will still be asserted and serviced by ISR.
+ * 0b10..The violation detected by the secure checker will cause an abort.
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)
+/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable Simple Master Strict Mode
+ * 0b00..Reserved
+ * 0b01..Can access memories and peripherals at the same level or below that level
+ * 0b10..Can access memories and peripherals at same level only
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)
+/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable Smart Master Strict Mode
+ * 0b00..Reserved
+ * 0b01..Can access memories and peripherals at the same level or below that level
+ * 0b10..Can access memories and peripherals at same level only
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U)
+/*! IDAU_ALL_NS - IDAU All Non-Secure
+ * 0b00..Reserved
+ * 0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory.
+ * 0b10..IDAU is enabled (restrictive mode)
+ * 0b11..Reserved
+ */
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group AHB_SECURE_CTRL_Register_Masks */
+
+
+/* AHB_SECURE_CTRL - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral AHB_SECURE_CTRL base address */
+ #define AHB_SECURE_CTRL_BASE (0x50148000u)
+ /** Peripheral AHB_SECURE_CTRL base address */
+ #define AHB_SECURE_CTRL_BASE_NS (0x40148000u)
+ /** Peripheral AHB_SECURE_CTRL base pointer */
+ #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
+ /** Peripheral AHB_SECURE_CTRL base pointer */
+ #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS)
+ /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
+ #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE }
+ /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
+ #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL }
+ /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
+ #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS }
+ /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
+ #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS }
+#else
+ /** Peripheral AHB_SECURE_CTRL base address */
+ #define AHB_SECURE_CTRL_BASE (0x40148000u)
+ /** Peripheral AHB_SECURE_CTRL base pointer */
+ #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
+ /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
+ #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE }
+ /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
+ #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL }
+#endif
+
+/*!
+ * @}
+ */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- AXI_SWITCH_AMIB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXI_SWITCH_AMIB_Peripheral_Access_Layer AXI_SWITCH_AMIB Peripheral Access Layer
+ * @{
+ */
+
+/** AXI_SWITCH_AMIB - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __IO uint32_t FN_MOD_BM_ISS; /**< Bus Matrix Issuing Functionality Modification., offset: 0x8 */
+ uint8_t RESERVED_1[24];
+ __IO uint32_t FN_MOD2; /**< Bypass Merge, offset: 0x24 */
+ uint8_t RESERVED_2[224];
+ __IO uint32_t FN_MOD; /**< Issuing Functionality Modification, offset: 0x108 */
+} AXI_SWITCH_AMIB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- AXI_SWITCH_AMIB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXI_SWITCH_AMIB_Register_Masks AXI_SWITCH_AMIB Register Masks
+ * @{
+ */
+
+/*! @name FN_MOD_BM_ISS - Bus Matrix Issuing Functionality Modification. */
+/*! @{ */
+#define AXI_SWITCH_AMIB_FN_MOD_BM_ISS_FN_MOD_BM_ISS_MASK (0x3U)
+#define AXI_SWITCH_AMIB_FN_MOD_BM_ISS_FN_MOD_BM_ISS_SHIFT (0U)
+/*! FN_MOD_BM_ISS - Read channel QoS value
+ */
+#define AXI_SWITCH_AMIB_FN_MOD_BM_ISS_FN_MOD_BM_ISS(x) (((uint32_t)(((uint32_t)(x)) << AXI_SWITCH_AMIB_FN_MOD_BM_ISS_FN_MOD_BM_ISS_SHIFT)) & AXI_SWITCH_AMIB_FN_MOD_BM_ISS_FN_MOD_BM_ISS_MASK)
+/*! @} */
+
+/*! @name FN_MOD2 - Bypass Merge */
+/*! @{ */
+#define AXI_SWITCH_AMIB_FN_MOD2_FN_MOD2_MASK (0x1U)
+#define AXI_SWITCH_AMIB_FN_MOD2_FN_MOD2_SHIFT (0U)
+/*! FN_MOD2 - Bypass Merge
+ */
+#define AXI_SWITCH_AMIB_FN_MOD2_FN_MOD2(x) (((uint32_t)(((uint32_t)(x)) << AXI_SWITCH_AMIB_FN_MOD2_FN_MOD2_SHIFT)) & AXI_SWITCH_AMIB_FN_MOD2_FN_MOD2_MASK)
+/*! @} */
+
+/*! @name FN_MOD - Issuing Functionality Modification */
+/*! @{ */
+#define AXI_SWITCH_AMIB_FN_MOD_FN_MOD_MASK (0x3U)
+#define AXI_SWITCH_AMIB_FN_MOD_FN_MOD_SHIFT (0U)
+/*! FN_MOD - Bypass Merge
+ */
+#define AXI_SWITCH_AMIB_FN_MOD_FN_MOD(x) (((uint32_t)(((uint32_t)(x)) << AXI_SWITCH_AMIB_FN_MOD_FN_MOD_SHIFT)) & AXI_SWITCH_AMIB_FN_MOD_FN_MOD_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group AXI_SWITCH_AMIB_Register_Masks */
+
+
+/* AXI_SWITCH_AMIB - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral AXI_SWITCH_AMIB base address */
+ #define AXI_SWITCH_AMIB_BASE (0x50282000u)
+ /** Peripheral AXI_SWITCH_AMIB base address */
+ #define AXI_SWITCH_AMIB_BASE_NS (0x40282000u)
+ /** Peripheral AXI_SWITCH_AMIB base pointer */
+ #define AXI_SWITCH_AMIB ((AXI_SWITCH_AMIB_Type *)AXI_SWITCH_AMIB_BASE)
+ /** Peripheral AXI_SWITCH_AMIB base pointer */
+ #define AXI_SWITCH_AMIB_NS ((AXI_SWITCH_AMIB_Type *)AXI_SWITCH_AMIB_BASE_NS)
+ /** Array initializer of AXI_SWITCH_AMIB peripheral base addresses */
+ #define AXI_SWITCH_AMIB_BASE_ADDRS { AXI_SWITCH_AMIB_BASE }
+ /** Array initializer of AXI_SWITCH_AMIB peripheral base pointers */
+ #define AXI_SWITCH_AMIB_BASE_PTRS { AXI_SWITCH_AMIB }
+ /** Array initializer of AXI_SWITCH_AMIB peripheral base addresses */
+ #define AXI_SWITCH_AMIB_BASE_ADDRS_NS { AXI_SWITCH_AMIB_BASE_NS }
+ /** Array initializer of AXI_SWITCH_AMIB peripheral base pointers */
+ #define AXI_SWITCH_AMIB_BASE_PTRS_NS { AXI_SWITCH_AMIB_NS }
+#else
+ /** Peripheral AXI_SWITCH_AMIB base address */
+ #define AXI_SWITCH_AMIB_BASE (0x40282000u)
+ /** Peripheral AXI_SWITCH_AMIB base pointer */
+ #define AXI_SWITCH_AMIB ((AXI_SWITCH_AMIB_Type *)AXI_SWITCH_AMIB_BASE)
+ /** Array initializer of AXI_SWITCH_AMIB peripheral base addresses */
+ #define AXI_SWITCH_AMIB_BASE_ADDRS { AXI_SWITCH_AMIB_BASE }
+ /** Array initializer of AXI_SWITCH_AMIB peripheral base pointers */
+ #define AXI_SWITCH_AMIB_BASE_PTRS { AXI_SWITCH_AMIB }
+#endif
+
+/*!
+ * @}
+ */ /* end of group AXI_SWITCH_AMIB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- AXI_SWITCH_ASIB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXI_SWITCH_ASIB_Peripheral_Access_Layer AXI_SWITCH_ASIB Peripheral Access Layer
+ * @{
+ */
+
+/** AXI_SWITCH_ASIB - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[256];
+ __IO uint32_t READ_QOS; /**< Read channel QoS value, offset: 0x100 */
+ __IO uint32_t WRITE_QOS; /**< WRITE channel QoS value, offset: 0x104 */
+ __IO uint32_t FN_MOD; /**< Issuing Functionality Modification, offset: 0x108 */
+} AXI_SWITCH_ASIB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- AXI_SWITCH_ASIB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXI_SWITCH_ASIB_Register_Masks AXI_SWITCH_ASIB Register Masks
+ * @{
+ */
+
+/*! @name READ_QOS - Read channel QoS value */
+/*! @{ */
+#define AXI_SWITCH_ASIB_READ_QOS_READ_QOS_MASK (0xFU)
+#define AXI_SWITCH_ASIB_READ_QOS_READ_QOS_SHIFT (0U)
+/*! READ_QOS - Read channel QoS value
+ */
+#define AXI_SWITCH_ASIB_READ_QOS_READ_QOS(x) (((uint32_t)(((uint32_t)(x)) << AXI_SWITCH_ASIB_READ_QOS_READ_QOS_SHIFT)) & AXI_SWITCH_ASIB_READ_QOS_READ_QOS_MASK)
+/*! @} */
+
+/*! @name WRITE_QOS - WRITE channel QoS value */
+/*! @{ */
+#define AXI_SWITCH_ASIB_WRITE_QOS_WRITE_QOS_MASK (0xFU)
+#define AXI_SWITCH_ASIB_WRITE_QOS_WRITE_QOS_SHIFT (0U)
+/*! WRITE_QOS - Write channel QoS value
+ */
+#define AXI_SWITCH_ASIB_WRITE_QOS_WRITE_QOS(x) (((uint32_t)(((uint32_t)(x)) << AXI_SWITCH_ASIB_WRITE_QOS_WRITE_QOS_SHIFT)) & AXI_SWITCH_ASIB_WRITE_QOS_WRITE_QOS_MASK)
+/*! @} */
+
+/*! @name FN_MOD - Issuing Functionality Modification */
+/*! @{ */
+#define AXI_SWITCH_ASIB_FN_MOD_WRITE_QOS_MASK (0x3U)
+#define AXI_SWITCH_ASIB_FN_MOD_WRITE_QOS_SHIFT (0U)
+/*! WRITE_QOS - Write channel QoS value
+ */
+#define AXI_SWITCH_ASIB_FN_MOD_WRITE_QOS(x) (((uint32_t)(((uint32_t)(x)) << AXI_SWITCH_ASIB_FN_MOD_WRITE_QOS_SHIFT)) & AXI_SWITCH_ASIB_FN_MOD_WRITE_QOS_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group AXI_SWITCH_ASIB_Register_Masks */
+
+
+/* AXI_SWITCH_ASIB - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral AXI_SWITCH_ASIB base address */
+ #define AXI_SWITCH_ASIB_BASE (0x502C2000u)
+ /** Peripheral AXI_SWITCH_ASIB base address */
+ #define AXI_SWITCH_ASIB_BASE_NS (0x402C2000u)
+ /** Peripheral AXI_SWITCH_ASIB base pointer */
+ #define AXI_SWITCH_ASIB ((AXI_SWITCH_ASIB_Type *)AXI_SWITCH_ASIB_BASE)
+ /** Peripheral AXI_SWITCH_ASIB base pointer */
+ #define AXI_SWITCH_ASIB_NS ((AXI_SWITCH_ASIB_Type *)AXI_SWITCH_ASIB_BASE_NS)
+ /** Array initializer of AXI_SWITCH_ASIB peripheral base addresses */
+ #define AXI_SWITCH_ASIB_BASE_ADDRS { AXI_SWITCH_ASIB_BASE }
+ /** Array initializer of AXI_SWITCH_ASIB peripheral base pointers */
+ #define AXI_SWITCH_ASIB_BASE_PTRS { AXI_SWITCH_ASIB }
+ /** Array initializer of AXI_SWITCH_ASIB peripheral base addresses */
+ #define AXI_SWITCH_ASIB_BASE_ADDRS_NS { AXI_SWITCH_ASIB_BASE_NS }
+ /** Array initializer of AXI_SWITCH_ASIB peripheral base pointers */
+ #define AXI_SWITCH_ASIB_BASE_PTRS_NS { AXI_SWITCH_ASIB_NS }
+#else
+ /** Peripheral AXI_SWITCH_ASIB base address */
+ #define AXI_SWITCH_ASIB_BASE (0x402C2000u)
+ /** Peripheral AXI_SWITCH_ASIB base pointer */
+ #define AXI_SWITCH_ASIB ((AXI_SWITCH_ASIB_Type *)AXI_SWITCH_ASIB_BASE)
+ /** Array initializer of AXI_SWITCH_ASIB peripheral base addresses */
+ #define AXI_SWITCH_ASIB_BASE_ADDRS { AXI_SWITCH_ASIB_BASE }
+ /** Array initializer of AXI_SWITCH_ASIB peripheral base pointers */
+ #define AXI_SWITCH_ASIB_BASE_PTRS { AXI_SWITCH_ASIB }
+#endif
+
+/*!
+ * @}
+ */ /* end of group AXI_SWITCH_ASIB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CACHE64_CTRL Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CACHE64_CTRL_Peripheral_Access_Layer CACHE64_CTRL Peripheral Access Layer
+ * @{
+ */
+
+/** CACHE64_CTRL - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[2048];
+ __IO uint32_t CCR; /**< Cache control register, offset: 0x800 */
+ __IO uint32_t CLCR; /**< Cache line control register, offset: 0x804 */
+ __IO uint32_t CSAR; /**< Cache search address register, offset: 0x808 */
+ __IO uint32_t CCVR; /**< Cache read/write value register, offset: 0x80C */
+} CACHE64_CTRL_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CACHE64_CTRL Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CACHE64_CTRL_Register_Masks CACHE64_CTRL Register Masks
+ * @{
+ */
+
+/*! @name CCR - Cache control register */
+/*! @{ */
+#define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U)
+#define CACHE64_CTRL_CCR_ENCACHE_SHIFT (0U)
+/*! ENCACHE - Cache enable
+ * 0b0..Cache disabled
+ * 0b1..Cache enabled
+ */
+#define CACHE64_CTRL_CCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENCACHE_SHIFT)) & CACHE64_CTRL_CCR_ENCACHE_MASK)
+#define CACHE64_CTRL_CCR_ENWRBUF_MASK (0x2U)
+#define CACHE64_CTRL_CCR_ENWRBUF_SHIFT (1U)
+/*! ENWRBUF - Enable Write Buffer
+ * 0b0..Write buffer disabled
+ * 0b1..Write buffer enabled
+ */
+#define CACHE64_CTRL_CCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENWRBUF_SHIFT)) & CACHE64_CTRL_CCR_ENWRBUF_MASK)
+#define CACHE64_CTRL_CCR_INVW0_MASK (0x1000000U)
+#define CACHE64_CTRL_CCR_INVW0_SHIFT (24U)
+/*! INVW0 - Invalidate Way 0
+ * 0b0..No operation
+ * 0b1..When setting the GO bit, invalidate all lines in way 0.
+ */
+#define CACHE64_CTRL_CCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW0_SHIFT)) & CACHE64_CTRL_CCR_INVW0_MASK)
+#define CACHE64_CTRL_CCR_PUSHW0_MASK (0x2000000U)
+#define CACHE64_CTRL_CCR_PUSHW0_SHIFT (25U)
+/*! PUSHW0 - Push Way 0
+ * 0b0..No operation
+ * 0b1..When setting the GO bit, push all modified lines in way 0
+ */
+#define CACHE64_CTRL_CCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW0_SHIFT)) & CACHE64_CTRL_CCR_PUSHW0_MASK)
+#define CACHE64_CTRL_CCR_INVW1_MASK (0x4000000U)
+#define CACHE64_CTRL_CCR_INVW1_SHIFT (26U)
+/*! INVW1 - Invalidate Way 1
+ * 0b0..No operation
+ * 0b1..When setting the GO bit, invalidate all lines in way 1
+ */
+#define CACHE64_CTRL_CCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW1_SHIFT)) & CACHE64_CTRL_CCR_INVW1_MASK)
+#define CACHE64_CTRL_CCR_PUSHW1_MASK (0x8000000U)
+#define CACHE64_CTRL_CCR_PUSHW1_SHIFT (27U)
+/*! PUSHW1 - Push Way 1
+ * 0b0..No operation
+ * 0b1..When setting the GO bit, push all modified lines in way 1
+ */
+#define CACHE64_CTRL_CCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW1_SHIFT)) & CACHE64_CTRL_CCR_PUSHW1_MASK)
+#define CACHE64_CTRL_CCR_GO_MASK (0x80000000U)
+#define CACHE64_CTRL_CCR_GO_SHIFT (31U)
+/*! GO - Initiate Cache Command
+ * 0b0..Write: no effect. Read: no cache command active.
+ * 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.
+ */
+#define CACHE64_CTRL_CCR_GO(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_GO_SHIFT)) & CACHE64_CTRL_CCR_GO_MASK)
+/*! @} */
+
+/*! @name CLCR - Cache line control register */
+/*! @{ */
+#define CACHE64_CTRL_CLCR_LGO_MASK (0x1U)
+#define CACHE64_CTRL_CLCR_LGO_SHIFT (0U)
+/*! LGO - Initiate Cache Line Command
+ * 0b0..Write: no effect. Read: no line command active.
+ * 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.
+ */
+#define CACHE64_CTRL_CLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
+#define CACHE64_CTRL_CLCR_CACHEADDR_MASK (0x3FFCU)
+#define CACHE64_CTRL_CLCR_CACHEADDR_SHIFT (2U)
+/*! CACHEADDR - Cache address
+ */
+#define CACHE64_CTRL_CLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_CACHEADDR_SHIFT)) & CACHE64_CTRL_CLCR_CACHEADDR_MASK)
+#define CACHE64_CTRL_CLCR_WSEL_MASK (0x4000U)
+#define CACHE64_CTRL_CLCR_WSEL_SHIFT (14U)
+/*! WSEL - Way select
+ * 0b0..Way 0
+ * 0b1..Way 1
+ */
+#define CACHE64_CTRL_CLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_WSEL_SHIFT)) & CACHE64_CTRL_CLCR_WSEL_MASK)
+#define CACHE64_CTRL_CLCR_TDSEL_MASK (0x10000U)
+#define CACHE64_CTRL_CLCR_TDSEL_SHIFT (16U)
+/*! TDSEL - Tag/Data Select
+ * 0b0..Data
+ * 0b1..Tag
+ */
+#define CACHE64_CTRL_CLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_TDSEL_SHIFT)) & CACHE64_CTRL_CLCR_TDSEL_MASK)
+#define CACHE64_CTRL_CLCR_LCIVB_MASK (0x100000U)
+#define CACHE64_CTRL_CLCR_LCIVB_SHIFT (20U)
+/*! LCIVB - Line Command Initial Valid Bit
+ */
+#define CACHE64_CTRL_CLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIVB_SHIFT)) & CACHE64_CTRL_CLCR_LCIVB_MASK)
+#define CACHE64_CTRL_CLCR_LCIMB_MASK (0x200000U)
+#define CACHE64_CTRL_CLCR_LCIMB_SHIFT (21U)
+/*! LCIMB - Line Command Initial Modified Bit
+ */
+#define CACHE64_CTRL_CLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIMB_SHIFT)) & CACHE64_CTRL_CLCR_LCIMB_MASK)
+#define CACHE64_CTRL_CLCR_LCWAY_MASK (0x400000U)
+#define CACHE64_CTRL_CLCR_LCWAY_SHIFT (22U)
+/*! LCWAY - Line Command Way
+ */
+#define CACHE64_CTRL_CLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCWAY_SHIFT)) & CACHE64_CTRL_CLCR_LCWAY_MASK)
+#define CACHE64_CTRL_CLCR_LCMD_MASK (0x3000000U)
+#define CACHE64_CTRL_CLCR_LCMD_SHIFT (24U)
+/*! LCMD - Line Command
+ * 0b00..Search and read or write
+ * 0b01..Invalidate
+ * 0b10..Push
+ * 0b11..Clear
+ */
+#define CACHE64_CTRL_CLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCMD_SHIFT)) & CACHE64_CTRL_CLCR_LCMD_MASK)
+#define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U)
+#define CACHE64_CTRL_CLCR_LADSEL_SHIFT (26U)
+/*! LADSEL - Line Address Select
+ * 0b0..Cache address
+ * 0b1..Physical address
+ */
+#define CACHE64_CTRL_CLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
+#define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U)
+#define CACHE64_CTRL_CLCR_LACC_SHIFT (27U)
+/*! LACC - Line access type
+ * 0b0..Read
+ * 0b1..Write
+ */
+#define CACHE64_CTRL_CLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
+/*! @} */
+
+/*! @name CSAR - Cache search address register */
+/*! @{ */
+#define CACHE64_CTRL_CSAR_LGO_MASK (0x1U)
+#define CACHE64_CTRL_CSAR_LGO_SHIFT (0U)
+/*! LGO - Initiate Cache Line Command
+ * 0b0..Write: no effect. Read: no line command active.
+ * 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
+ */
+#define CACHE64_CTRL_CSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_LGO_SHIFT)) & CACHE64_CTRL_CSAR_LGO_MASK)
+#define CACHE64_CTRL_CSAR_PHYADDR27_1_MASK (0xFFFFFFEU)
+#define CACHE64_CTRL_CSAR_PHYADDR27_1_SHIFT (1U)
+/*! PHYADDR27_1 - Physical Address
+ */
+#define CACHE64_CTRL_CSAR_PHYADDR27_1(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_PHYADDR27_1_SHIFT)) & CACHE64_CTRL_CSAR_PHYADDR27_1_MASK)
+#define CACHE64_CTRL_CSAR_PHYADDR31_29_MASK (0xE0000000U)
+#define CACHE64_CTRL_CSAR_PHYADDR31_29_SHIFT (29U)
+/*! PHYADDR31_29 - Physical Address
+ */
+#define CACHE64_CTRL_CSAR_PHYADDR31_29(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_PHYADDR31_29_SHIFT)) & CACHE64_CTRL_CSAR_PHYADDR31_29_MASK)
+/*! @} */
+
+/*! @name CCVR - Cache read/write value register */
+/*! @{ */
+#define CACHE64_CTRL_CCVR_DATA_MASK (0xFFFFFFFFU)
+#define CACHE64_CTRL_CCVR_DATA_SHIFT (0U)
+/*! DATA - Cache read/write Data
+ */
+#define CACHE64_CTRL_CCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCVR_DATA_SHIFT)) & CACHE64_CTRL_CCVR_DATA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CACHE64_CTRL_Register_Masks */
+
+
+/* CACHE64_CTRL - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral CACHE64_CTRL0 base address */
+ #define CACHE64_CTRL0_BASE (0x50033000u)
+ /** Peripheral CACHE64_CTRL0 base address */
+ #define CACHE64_CTRL0_BASE_NS (0x40033000u)
+ /** Peripheral CACHE64_CTRL0 base pointer */
+ #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
+ /** Peripheral CACHE64_CTRL0 base pointer */
+ #define CACHE64_CTRL0_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS)
+ /** Peripheral CACHE64_CTRL1 base address */
+ #define CACHE64_CTRL1_BASE (0x50034000u)
+ /** Peripheral CACHE64_CTRL1 base address */
+ #define CACHE64_CTRL1_BASE_NS (0x40034000u)
+ /** Peripheral CACHE64_CTRL1 base pointer */
+ #define CACHE64_CTRL1 ((CACHE64_CTRL_Type *)CACHE64_CTRL1_BASE)
+ /** Peripheral CACHE64_CTRL1 base pointer */
+ #define CACHE64_CTRL1_NS ((CACHE64_CTRL_Type *)CACHE64_CTRL1_BASE_NS)
+ /** Array initializer of CACHE64_CTRL peripheral base addresses */
+ #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE }
+ /** Array initializer of CACHE64_CTRL peripheral base pointers */
+ #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 }
+ /** Array initializer of CACHE64_CTRL peripheral base addresses */
+ #define CACHE64_CTRL_BASE_ADDRS_NS { CACHE64_CTRL0_BASE_NS, CACHE64_CTRL1_BASE_NS }
+ /** Array initializer of CACHE64_CTRL peripheral base pointers */
+ #define CACHE64_CTRL_BASE_PTRS_NS { CACHE64_CTRL0_NS, CACHE64_CTRL1_NS }
+#else
+ /** Peripheral CACHE64_CTRL0 base address */
+ #define CACHE64_CTRL0_BASE (0x40033000u)
+ /** Peripheral CACHE64_CTRL0 base pointer */
+ #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
+ /** Peripheral CACHE64_CTRL1 base address */
+ #define CACHE64_CTRL1_BASE (0x40034000u)
+ /** Peripheral CACHE64_CTRL1 base pointer */
+ #define CACHE64_CTRL1 ((CACHE64_CTRL_Type *)CACHE64_CTRL1_BASE)
+ /** Array initializer of CACHE64_CTRL peripheral base addresses */
+ #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE }
+ /** Array initializer of CACHE64_CTRL peripheral base pointers */
+ #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 }
+#endif
+#if (__ARM_FEATURE_CMSE & 0x2)
+/** CACHE64_CTRL physical memory base address */
+ #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x38000000u }
+/** CACHE64_CTRL physical memory size */
+ #define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x08000000u }
+/** CACHE64_CTRL physical memory base address */
+ #define CACHE64_CTRL_PHYMEM_BASES_NS { 0x08000000u, 0x28000000u }
+/** CACHE64_CTRL physical memory size */
+ #define CACHE64_CTRL_PHYMEM_SIZES_NS { 0x08000000u, 0x08000000u }
+#else
+/** CACHE64_CTRL physical memory base address */
+ #define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x28000000u }
+/** CACHE64_CTRL physical memory size */
+ #define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x08000000u }
+#endif
+/* Backward compatibility */
+#define CACHE64_CTRL_CSAR_PHYADDR_MASK (CACHE64_CTRL_CSAR_PHYADDR27_1_MASK | CACHE64_CTRL_CSAR_PHYADDR31_29_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CACHE64_CTRL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CACHE64_POLSEL Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CACHE64_POLSEL_Peripheral_Access_Layer CACHE64_POLSEL Peripheral Access Layer
+ * @{
+ */
+
+/** CACHE64_POLSEL - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[20];
+ __IO uint32_t REG0_TOP; /**< Region 0 Top Boundary, offset: 0x14 */
+ __IO uint32_t REG1_TOP; /**< Region 1 Top Boundary, offset: 0x18 */
+ __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */
+} CACHE64_POLSEL_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CACHE64_POLSEL Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CACHE64_POLSEL_Register_Masks CACHE64_POLSEL Register Masks
+ * @{
+ */
+
+/*! @name REG0_TOP - Region 0 Top Boundary */
+/*! @{ */
+#define CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK (0x7FFFC00U)
+#define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U)
+/*! REG0_TOP - Upper limit of Region 0
+ */
+#define CACHE64_POLSEL_REG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) & CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK)
+/*! @} */
+
+/*! @name REG1_TOP - Region 1 Top Boundary */
+/*! @{ */
+#define CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK (0x7FFFC00U)
+#define CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT (10U)
+/*! REG1_TOP - Upper limit of Region 1
+ */
+#define CACHE64_POLSEL_REG1_TOP_REG1_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT)) & CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK)
+/*! @} */
+
+/*! @name POLSEL - Policy Select */
+/*! @{ */
+#define CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK (0x3U)
+#define CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT (0U)
+/*! REG0_POLICY - Policy Select for Region 0
+ * 0b00..Non-cache
+ * 0b01..Write-thru
+ * 0b10..Write-back
+ * 0b11..Invalid
+ */
+#define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK)
+#define CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK (0xCU)
+#define CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT (2U)
+/*! REG1_POLICY - Policy Select for Region 0
+ * 0b00..Non-cache
+ * 0b01..Write-thru
+ * 0b10..Write-back
+ * 0b11..Invalid
+ */
+#define CACHE64_POLSEL_POLSEL_REG1_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK)
+#define CACHE64_POLSEL_POLSEL_REG02_POLICY_MASK (0x30U)
+#define CACHE64_POLSEL_POLSEL_REG02_POLICY_SHIFT (4U)
+/*! REG02_POLICY - Policy Select for Region 0
+ * 0b00..Non-cache
+ * 0b01..Write-thru
+ * 0b10..Write-back
+ * 0b11..Invalid
+ */
+#define CACHE64_POLSEL_POLSEL_REG02_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG02_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG02_POLICY_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CACHE64_POLSEL_Register_Masks */
+
+
+/* CACHE64_POLSEL - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral CACHE64_POLSEL0 base address */
+ #define CACHE64_POLSEL0_BASE (0x50033000u)
+ /** Peripheral CACHE64_POLSEL0 base address */
+ #define CACHE64_POLSEL0_BASE_NS (0x40033000u)
+ /** Peripheral CACHE64_POLSEL0 base pointer */
+ #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE)
+ /** Peripheral CACHE64_POLSEL0 base pointer */
+ #define CACHE64_POLSEL0_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS)
+ /** Peripheral CACHE64_POLSEL1 base address */
+ #define CACHE64_POLSEL1_BASE (0x50034000u)
+ /** Peripheral CACHE64_POLSEL1 base address */
+ #define CACHE64_POLSEL1_BASE_NS (0x40034000u)
+ /** Peripheral CACHE64_POLSEL1 base pointer */
+ #define CACHE64_POLSEL1 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL1_BASE)
+ /** Peripheral CACHE64_POLSEL1 base pointer */
+ #define CACHE64_POLSEL1_NS ((CACHE64_POLSEL_Type *)CACHE64_POLSEL1_BASE_NS)
+ /** Array initializer of CACHE64_POLSEL peripheral base addresses */
+ #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE, CACHE64_POLSEL1_BASE }
+ /** Array initializer of CACHE64_POLSEL peripheral base pointers */
+ #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 }
+ /** Array initializer of CACHE64_POLSEL peripheral base addresses */
+ #define CACHE64_POLSEL_BASE_ADDRS_NS { CACHE64_POLSEL0_BASE_NS, CACHE64_POLSEL1_BASE_NS }
+ /** Array initializer of CACHE64_POLSEL peripheral base pointers */
+ #define CACHE64_POLSEL_BASE_PTRS_NS { CACHE64_POLSEL0_NS, CACHE64_POLSEL1_NS }
+#else
+ /** Peripheral CACHE64_POLSEL0 base address */
+ #define CACHE64_POLSEL0_BASE (0x40033000u)
+ /** Peripheral CACHE64_POLSEL0 base pointer */
+ #define CACHE64_POLSEL0 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE)
+ /** Peripheral CACHE64_POLSEL1 base address */
+ #define CACHE64_POLSEL1_BASE (0x40034000u)
+ /** Peripheral CACHE64_POLSEL1 base pointer */
+ #define CACHE64_POLSEL1 ((CACHE64_POLSEL_Type *)CACHE64_POLSEL1_BASE)
+ /** Array initializer of CACHE64_POLSEL peripheral base addresses */
+ #define CACHE64_POLSEL_BASE_ADDRS { CACHE64_POLSEL0_BASE, CACHE64_POLSEL1_BASE }
+ /** Array initializer of CACHE64_POLSEL peripheral base pointers */
+ #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group CACHE64_POLSEL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CASPER Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer
+ * @{
+ */
+
+/** CASPER - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL0; /**< Control 0, offset: 0x0 */
+ __IO uint32_t CTRL1; /**< Control 1, offset: 0x4 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t STATUS; /**< Status, offset: 0xC */
+ __IO uint32_t INTENSET; /**< Interrupt Enable Set, offset: 0x10 */
+ __IO uint32_t INTENCLR; /**< Interrupt Enable Clear, offset: 0x14 */
+ __I uint32_t INTSTAT; /**< Interrupt status, offset: 0x18 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t AREG; /**< A Register, offset: 0x20 */
+ __IO uint32_t BREG; /**< B Register, offset: 0x24 */
+ __IO uint32_t CREG; /**< C Register, offset: 0x28 */
+ __IO uint32_t DREG; /**< D Register, offset: 0x2C */
+ __IO uint32_t RES0; /**< Result Register 0, offset: 0x30 */
+ __IO uint32_t RES1; /**< Result Register 1, offset: 0x34 */
+ __IO uint32_t RES2; /**< Result Register 2, offset: 0x38 */
+ __IO uint32_t RES3; /**< Result Register 3, offset: 0x3C */
+ uint8_t RESERVED_2[32];
+ __IO uint32_t MASK; /**< Mask, offset: 0x60 */
+ __IO uint32_t REMASK; /**< Remask, offset: 0x64 */
+ uint8_t RESERVED_3[24];
+ __IO uint32_t LOCK; /**< Lock, offset: 0x80 */
+} CASPER_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CASPER Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CASPER_Register_Masks CASPER Register Masks
+ * @{
+ */
+
+/*! @name CTRL0 - Control 0 */
+/*! @{ */
+#define CASPER_CTRL0_ABBPAIR_MASK (0x1U)
+#define CASPER_CTRL0_ABBPAIR_SHIFT (0U)
+/*! ABBPAIR - ABOFF Bank Pair
+ * 0b0..Bank-pair 0 (1st)
+ * 0b1..Bank-pair 1 (2nd)
+ */
+#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK)
+#define CASPER_CTRL0_ABOFF_MASK (0x4U)
+#define CASPER_CTRL0_ABOFF_SHIFT (2U)
+/*! ABOFF - AB Offset
+ */
+#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK)
+#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U)
+#define CASPER_CTRL0_CDBPAIR_SHIFT (16U)
+/*! CDBPAIR - CDOFF Bank Pair
+ * 0b0..Bank-pair 0 (1st)
+ * 0b1..Bank-pair 1 (2nd)
+ */
+#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK)
+#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U)
+#define CASPER_CTRL0_CDOFF_SHIFT (18U)
+/*! CDOFF - CD Offset
+ */
+#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK)
+/*! @} */
+
+/*! @name CTRL1 - Control 1 */
+/*! @{ */
+#define CASPER_CTRL1_ITER_MASK (0xFFU)
+#define CASPER_CTRL1_ITER_SHIFT (0U)
+/*! ITER - Interation Counter
+ */
+#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK)
+#define CASPER_CTRL1_MODE_MASK (0xFF00U)
+#define CASPER_CTRL1_MODE_SHIFT (8U)
+/*! MODE - Mode
+ */
+#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
+#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U)
+#define CASPER_CTRL1_RESBPAIR_SHIFT (16U)
+/*! RESBPAIR - RESOFF Bank Pair
+ * 0b0..Bank-pair 0 (1st)
+ * 0b1..Bank-pair 1 (2nd)
+ */
+#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK)
+#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U)
+#define CASPER_CTRL1_RESOFF_SHIFT (18U)
+/*! RESOFF - Result Offset
+ */
+#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK)
+#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U)
+#define CASPER_CTRL1_CSKIP_SHIFT (30U)
+/*! CSKIP - Skip Rules on Carry
+ * 0b00..No Skip
+ * 0b01..Skip if Carry is 1
+ * 0b10..Skip if Carry is 0
+ * 0b11..Set CTRLOFF to CDOFF and Skip
+ */
+#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK)
+/*! @} */
+
+/*! @name STATUS - Status */
+/*! @{ */
+#define CASPER_STATUS_DONE_MASK (0x1U)
+#define CASPER_STATUS_DONE_SHIFT (0U)
+/*! DONE - Done
+ * 0b0..Busy or just cleared
+ * 0b1..Completed last operation
+ */
+#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK)
+#define CASPER_STATUS_CARRY_MASK (0x10U)
+#define CASPER_STATUS_CARRY_SHIFT (4U)
+/*! CARRY - Carry
+ * 0b0..Carry was 0 or no carry
+ * 0b1..Carry was 1
+ */
+#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK)
+#define CASPER_STATUS_BUSY_MASK (0x20U)
+#define CASPER_STATUS_BUSY_SHIFT (5U)
+/*! BUSY - Busy
+ * 0b0..Not busy - is idle
+ * 0b1..Is busy
+ */
+#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK)
+/*! @} */
+
+/*! @name INTENSET - Interrupt Enable Set */
+/*! @{ */
+#define CASPER_INTENSET_DONE_MASK (0x1U)
+#define CASPER_INTENSET_DONE_SHIFT (0U)
+/*! DONE - Done
+ * 0b0..Do not interrupt when done
+ * 0b1..Interrupt when done
+ */
+#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK)
+/*! @} */
+
+/*! @name INTENCLR - Interrupt Enable Clear */
+/*! @{ */
+#define CASPER_INTENCLR_DONE_MASK (0x1U)
+#define CASPER_INTENCLR_DONE_SHIFT (0U)
+/*! DONE - Done
+ * 0b0..If written 0, ignored
+ * 0b1..If written 1, do not interrupt when done.
+ */
+#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt status */
+/*! @{ */
+#define CASPER_INTSTAT_DONE_MASK (0x1U)
+#define CASPER_INTSTAT_DONE_SHIFT (0U)
+/*! DONE - If set, interrupt is caused by accelerator being done.
+ * 0b0..Not caused by accelerator being done
+ * 0b1..Caused by accelerator being done
+ */
+#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK)
+/*! @} */
+
+/*! @name AREG - A Register */
+/*! @{ */
+#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_AREG_REG_VALUE_SHIFT (0U)
+/*! REG_VALUE - Register Value
+ */
+#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK)
+/*! @} */
+
+/*! @name BREG - B Register */
+/*! @{ */
+#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_BREG_REG_VALUE_SHIFT (0U)
+/*! REG_VALUE - Register Value
+ */
+#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK)
+/*! @} */
+
+/*! @name CREG - C Register */
+/*! @{ */
+#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_CREG_REG_VALUE_SHIFT (0U)
+/*! REG_VALUE - Register Value
+ */
+#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK)
+/*! @} */
+
+/*! @name DREG - D Register */
+/*! @{ */
+#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_DREG_REG_VALUE_SHIFT (0U)
+/*! REG_VALUE - Register Value
+ */
+#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK)
+/*! @} */
+
+/*! @name RES0 - Result Register 0 */
+/*! @{ */
+#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_RES0_REG_VALUE_SHIFT (0U)
+/*! REG_VALUE - Register Value
+ */
+#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK)
+/*! @} */
+
+/*! @name RES1 - Result Register 1 */
+/*! @{ */
+#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_RES1_REG_VALUE_SHIFT (0U)
+/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc).
+ */
+#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK)
+/*! @} */
+
+/*! @name RES2 - Result Register 2 */
+/*! @{ */
+#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_RES2_REG_VALUE_SHIFT (0U)
+/*! REG_VALUE - Register Value
+ */
+#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK)
+/*! @} */
+
+/*! @name RES3 - Result Register 3 */
+/*! @{ */
+#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_RES3_REG_VALUE_SHIFT (0U)
+/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc).
+ */
+#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK)
+/*! @} */
+
+/*! @name MASK - Mask */
+/*! @{ */
+#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU)
+#define CASPER_MASK_MASK_SHIFT (0U)
+/*! MASK - Mask
+ */
+#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK)
+/*! @} */
+
+/*! @name REMASK - Remask */
+/*! @{ */
+#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU)
+#define CASPER_REMASK_MASK_SHIFT (0U)
+/*! MASK - Mask
+ */
+#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK)
+/*! @} */
+
+/*! @name LOCK - Lock */
+/*! @{ */
+#define CASPER_LOCK_LOCK_MASK (0x1U)
+#define CASPER_LOCK_LOCK_SHIFT (0U)
+/*! LOCK - Lock
+ * 0b0..Unlock
+ * 0b1..Lock to current security level
+ */
+#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK)
+#define CASPER_LOCK_KEY_MASK (0x1FFF0U)
+#define CASPER_LOCK_KEY_SHIFT (4U)
+/*! KEY - Key
+ * 0b0011100111101..Key Value
+ */
+#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CASPER_Register_Masks */
+
+
+/* CASPER - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral CASPER base address */
+ #define CASPER_BASE (0x50201000u)
+ /** Peripheral CASPER base address */
+ #define CASPER_BASE_NS (0x40201000u)
+ /** Peripheral CASPER base pointer */
+ #define CASPER ((CASPER_Type *)CASPER_BASE)
+ /** Peripheral CASPER base pointer */
+ #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS)
+ /** Array initializer of CASPER peripheral base addresses */
+ #define CASPER_BASE_ADDRS { CASPER_BASE }
+ /** Array initializer of CASPER peripheral base pointers */
+ #define CASPER_BASE_PTRS { CASPER }
+ /** Array initializer of CASPER peripheral base addresses */
+ #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS }
+ /** Array initializer of CASPER peripheral base pointers */
+ #define CASPER_BASE_PTRS_NS { CASPER_NS }
+#else
+ /** Peripheral CASPER base address */
+ #define CASPER_BASE (0x40201000u)
+ /** Peripheral CASPER base pointer */
+ #define CASPER ((CASPER_Type *)CASPER_BASE)
+ /** Array initializer of CASPER peripheral base addresses */
+ #define CASPER_BASE_ADDRS { CASPER_BASE }
+ /** Array initializer of CASPER peripheral base pointers */
+ #define CASPER_BASE_PTRS { CASPER }
+#endif
+/** Interrupt vectors for the CASPER peripheral type */
+#define CASPER_IRQS { CASPER_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CASPER_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CLKCTL0 Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CLKCTL0_Peripheral_Access_Layer CLKCTL0 Peripheral Access Layer
+ * @{
+ */
+
+/** CLKCTL0 - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[16];
+ __IO uint32_t PSCCTL0; /**< Clock Control 0, offset: 0x10 */
+ __IO uint32_t PSCCTL1; /**< Clock Control 1, offset: 0x14 */
+ __IO uint32_t PSCCTL2; /**< Clock Control 2, offset: 0x18 */
+ uint8_t RESERVED_1[36];
+ __O uint32_t PSCCTL0_SET; /**< Clock Control 0 Set, offset: 0x40 */
+ __O uint32_t PSCCTL1_SET; /**< Clock Control 1 Set, offset: 0x44 */
+ __O uint32_t PSCCTL2_SET; /**< Clock Control 2 Set, offset: 0x48 */
+ uint8_t RESERVED_2[36];
+ __O uint32_t PSCCTL0_CLR; /**< Clock Control 0 Clear, offset: 0x70 */
+ __O uint32_t PSCCTL1_CLR; /**< Clock Control 1 Clear, offset: 0x74 */
+ __O uint32_t PSCCTL2_CLR; /**< Clock Control 2 Clear, offset: 0x78 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t FRO_CONTROL; /**< Free Running Oscillator Control, offset: 0x80 */
+ __I uint32_t FRO_CAPVAL; /**< Free Running Oscillator Captured Value, offset: 0x84 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t FRO_RDTRIM; /**< Free Running Oscillator Trim, offset: 0x8C */
+ __IO uint32_t FRO_SCTRIM; /**< Free Running OscillatorSC Trim, offset: 0x90 */
+ uint8_t RESERVED_5[116];
+ __IO uint32_t FRODIVSEL; /**< FRO Clock Divider, offset: 0x108 */
+ __I uint32_t FROCLKSTATUS; /**< FRO Clock Status, offset: 0x10C */
+ __IO uint32_t FRODIVOEN; /**< FRO Enable Register, offset: 0x110 */
+ uint8_t RESERVED_6[28];
+ __IO uint32_t LOWFREQCLKDIV; /**< Low Frequency Clock Divider, offset: 0x130 */
+ uint8_t RESERVED_7[44];
+ __IO uint32_t SYSOSCCTL0; /**< System Oscillator Control 0, offset: 0x160 */
+ uint8_t RESERVED_8[4];
+ __IO uint32_t SYSOSCBYPASS; /**< OSC Clock Source Select, offset: 0x168 */
+ uint8_t RESERVED_9[36];
+ __IO uint32_t LPOSCCTL0; /**< Low Power Oscillator Control 0, offset: 0x190 */
+ uint8_t RESERVED_10[44];
+ __IO uint32_t OSC32KHZCTL0; /**< 32 KHz Oscillator Control 0, offset: 0x1C0 */
+ uint8_t RESERVED_11[60];
+ __IO uint32_t SYSPLL0CLKSEL; /**< System PLL 0 Clock Select, offset: 0x200 */
+ __IO uint32_t SYSPLL0CTL0; /**< System PLL0 Control 0, offset: 0x204 */
+ uint8_t RESERVED_12[4];
+ __IO uint32_t SYSPLL0LOCKTIMEDIV2; /**< System PLL0 Lock Time Div2, offset: 0x20C */
+ __IO uint32_t SYSPLL0NUM; /**< System PLL0 Numerator, offset: 0x210 */
+ __IO uint32_t SYSPLL0DENOM; /**< System PLL0 Denominator, offset: 0x214 */
+ __IO uint32_t SYSPLL0PFD; /**< System PLL0 PFD, offset: 0x218 */
+ uint8_t RESERVED_13[36];
+ __IO uint32_t MAINPLLCLKDIV; /**< Main PLL Clock Divider, offset: 0x240 */
+ __IO uint32_t DSPPLLCLKDIV; /**< DSP PLL Clock Divider, offset: 0x244 */
+ __IO uint32_t AUX0PLLCLKDIV; /**< AUX0 PLL Clock Divider, offset: 0x248 */
+ __IO uint32_t AUX1PLLCLKDIV; /**< AUX1 PLL Clock Divider, offset: 0x24C */
+ uint8_t RESERVED_14[432];
+ __IO uint32_t SYSCPUAHBCLKDIV; /**< System CPU AHB Clock Divider, offset: 0x400 */
+ uint8_t RESERVED_15[44];
+ __IO uint32_t MAINCLKSELA; /**< Main Clock Select A, offset: 0x430 */
+ __IO uint32_t MAINCLKSELB; /**< Main Clock Select B, offset: 0x434 */
+ uint8_t RESERVED_16[200];
+ __IO uint32_t PFCDIV[2]; /**< PFC divider 0 (trace clock)..PFC divider 1 (USB HS PHY bus clock), array offset: 0x500, array step: 0x4 */
+ uint8_t RESERVED_17[280];
+ __IO uint32_t FLEXSPI0FCLKSEL; /**< FlexSPI0 Functional Clock Select, offset: 0x620 */
+ __IO uint32_t FLEXSPI0FCLKDIV; /**< FlexSPI0 Functional Clock Divider, offset: 0x624 */
+ uint8_t RESERVED_18[8];
+ __IO uint32_t FLEXSPI1FCLKSEL; /**< FlexSPI1 Functional Clock Select, offset: 0x630 */
+ __IO uint32_t FLEXSPI1FCLKDIV; /**< FlexSPI1 Functional Clock Divider, offset: 0x634 */
+ uint8_t RESERVED_19[8];
+ __IO uint32_t SCTFCLKSEL; /**< SCT Functional Clock Select, offset: 0x640 */
+ __IO uint32_t SCTIN7CLKDIV; /**< SCT Functional Clock Divider, offset: 0x644 */
+ uint8_t RESERVED_20[24];
+ __IO uint32_t USBHSFCLKSEL; /**< High Speed USB Functional Clock Select, offset: 0x660 */
+ __IO uint32_t USBHSFCLKDIV; /**< High Speed USB Functional Clock Divider, offset: 0x664 */
+ uint8_t RESERVED_21[24];
+ __IO uint32_t SDIO0FCLKSEL; /**< SDIO0 Functional Clock Select, offset: 0x680 */
+ __IO uint32_t SDIO0FCLKDIV; /**< SDIO0 Functional Clock Divider, offset: 0x684 */
+ uint8_t RESERVED_22[8];
+ __IO uint32_t SDIO1FCLKSEL; /**< SDIO1 Functional Clock Select, offset: 0x690 */
+ __IO uint32_t SDIO1FCLKDIV; /**< SDIO1 Functional Clock Divider, offset: 0x694 */
+ uint8_t RESERVED_23[56];
+ __IO uint32_t ADC0FCLKSEL0; /**< ADC0 Functional Clock Select 0, offset: 0x6D0 */
+ __IO uint32_t ADC0FCLKSEL1; /**< ADC0 Functional Clock Select 1, offset: 0x6D4 */
+ __IO uint32_t ADC0FCLKDIV; /**< ADC0 Functional Clock Divider, offset: 0x6D8 */
+ uint8_t RESERVED_24[36];
+ __IO uint32_t UTICKFCLKSEL; /**< UTICK Functional Clock Select, offset: 0x700 */
+ uint8_t RESERVED_25[28];
+ __IO uint32_t WDT0FCLKSEL; /**< WDT0 Functional Clock Select, offset: 0x720 */
+ uint8_t RESERVED_26[12];
+ __IO uint32_t A32KHZWAKECLKSEL; /**< 32 KHz Wake Clock Source Select, offset: 0x730 */
+ __IO uint32_t A32KHZWAKECLKDIV; /**< 32 KHz Wake Clock Divider, offset: 0x734 */
+ uint8_t RESERVED_27[40];
+ __IO uint32_t SYSTICKFCLKSEL; /**< SYSTICK Functional Clock Select, offset: 0x760 */
+ __IO uint32_t SYSTICKFCLKDIV; /**< SYSTICK Functional Clock Divider, offset: 0x764 */
+ uint8_t RESERVED_28[8];
+ __IO uint32_t DPHYCLKSEL; /**< MIPI-DSI PHY Clock Select, offset: 0x770 */
+ __IO uint32_t DPHYCLKDIV; /**< MIPI-DSI PHY Clock Divider, offset: 0x774 */
+ __IO uint32_t DPHYESCCLKSEL; /**< MIPI-DSI DPHY Escape Mode Clock Select, offset: 0x778 */
+ __IO uint32_t DPHYESCRXCLKDIV; /**< MIPI-DSI DPHY Escape Mode Receive Clock Divider, offset: 0x77C */
+ __IO uint32_t DPHYESCTXCLKDIV; /**< MIPI-DSI DPHY Escape Mode Tramsmit Clock Divider, offset: 0x780 */
+ uint8_t RESERVED_29[12];
+ __IO uint32_t GPUCLKSEL; /**< GPU Clock Select, offset: 0x790 */
+ __IO uint32_t GPUCLKDIV; /**< GPU Clock Divider, offset: 0x794 */
+ uint8_t RESERVED_30[8];
+ __IO uint32_t DCPIXELCLKSEL; /**< LCDIF Pixel Clock Select, offset: 0x7A0 */
+ __IO uint32_t DCPIXELCLKDIV; /**< LCDIF Pixel Clock Divider, offset: 0x7A4 */
+} CLKCTL0_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CLKCTL0 Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CLKCTL0_Register_Masks CLKCTL0 Register Masks
+ * @{
+ */
+
+/*! @name PSCCTL0 - Clock Control 0 */
+/*! @{ */
+#define CLKCTL0_PSCCTL0_DSP_CLK_MASK (0x2U)
+#define CLKCTL0_PSCCTL0_DSP_CLK_SHIFT (1U)
+/*! DSP_CLK - DSP clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_DSP_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_DSP_CLK_SHIFT)) & CLKCTL0_PSCCTL0_DSP_CLK_MASK)
+#define CLKCTL0_PSCCTL0_ROM_CTRLR_CLK_MASK (0x4U)
+#define CLKCTL0_PSCCTL0_ROM_CTRLR_CLK_SHIFT (2U)
+/*! ROM_CTRLR_CLK - 128KB ROM Controller clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_ROM_CTRLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_ROM_CTRLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_ROM_CTRLR_CLK_MASK)
+#define CLKCTL0_PSCCTL0_AXI_SWITCH_CLK_MASK (0x8U)
+#define CLKCTL0_PSCCTL0_AXI_SWITCH_CLK_SHIFT (3U)
+/*! AXI_SWITCH_CLK - AXI Switch clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_AXI_SWITCH_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_AXI_SWITCH_CLK_SHIFT)) & CLKCTL0_PSCCTL0_AXI_SWITCH_CLK_MASK)
+#define CLKCTL0_PSCCTL0_AXI_CTLR_CLK_MASK (0x10U)
+#define CLKCTL0_PSCCTL0_AXI_CTLR_CLK_SHIFT (4U)
+/*! AXI_CTLR_CLK - AXI Controller clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_AXI_CTLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_AXI_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_AXI_CTLR_CLK_MASK)
+#define CLKCTL0_PSCCTL0_POWERQUAD_CLK_MASK (0x100U)
+#define CLKCTL0_PSCCTL0_POWERQUAD_CLK_SHIFT (8U)
+/*! POWERQUAD_CLK - POWERQUAD clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_POWERQUAD_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_POWERQUAD_CLK_SHIFT)) & CLKCTL0_PSCCTL0_POWERQUAD_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CASPER_CLK_MASK (0x200U)
+#define CLKCTL0_PSCCTL0_CASPER_CLK_SHIFT (9U)
+/*! CASPER_CLK - CASPER clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_CASPER_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CASPER_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CASPER_CLK_MASK)
+#define CLKCTL0_PSCCTL0_HASHCRYPT_CLK_MASK (0x400U)
+#define CLKCTL0_PSCCTL0_HASHCRYPT_CLK_SHIFT (10U)
+/*! HASHCRYPT_CLK - HASHCRYPT clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_HASHCRYPT_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_HASHCRYPT_CLK_SHIFT)) & CLKCTL0_PSCCTL0_HASHCRYPT_CLK_MASK)
+#define CLKCTL0_PSCCTL0_PUF_CLK_MASK (0x800U)
+#define CLKCTL0_PSCCTL0_PUF_CLK_SHIFT (11U)
+/*! PUF_CLK - PUF clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_PUF_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_PUF_CLK_SHIFT)) & CLKCTL0_PSCCTL0_PUF_CLK_MASK)
+#define CLKCTL0_PSCCTL0_RNG_CLK_MASK (0x1000U)
+#define CLKCTL0_PSCCTL0_RNG_CLK_SHIFT (12U)
+/*! RNG_CLK - Random Number Generator (RNG) clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_RNG_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_RNG_CLK_SHIFT)) & CLKCTL0_PSCCTL0_RNG_CLK_MASK)
+#define CLKCTL0_PSCCTL0_FLEXSPI0_OTFAD_CLK_MASK (0x10000U)
+#define CLKCTL0_PSCCTL0_FLEXSPI0_OTFAD_CLK_SHIFT (16U)
+/*! FLEXSPI0_OTFAD_CLK - FLEXSPI0 / OTFAD clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_FLEXSPI0_OTFAD_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_FLEXSPI0_OTFAD_CLK_SHIFT)) & CLKCTL0_PSCCTL0_FLEXSPI0_OTFAD_CLK_MASK)
+#define CLKCTL0_PSCCTL0_OTP_CTLR_CLK_MASK (0x20000U)
+#define CLKCTL0_PSCCTL0_OTP_CTLR_CLK_SHIFT (17U)
+/*! OTP_CTLR_CLK - OTP Controller clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_OTP_CTLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_OTP_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_OTP_CTLR_CLK_MASK)
+#define CLKCTL0_PSCCTL0_FLEXSPI1_CLK_MASK (0x40000U)
+#define CLKCTL0_PSCCTL0_FLEXSPI1_CLK_SHIFT (18U)
+/*! FLEXSPI1_CLK - FLEXSPI1 clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_FLEXSPI1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_FLEXSPI1_CLK_SHIFT)) & CLKCTL0_PSCCTL0_FLEXSPI1_CLK_MASK)
+#define CLKCTL0_PSCCTL0_USBHS_PHY_CLK_MASK (0x100000U)
+#define CLKCTL0_PSCCTL0_USBHS_PHY_CLK_SHIFT (20U)
+/*! USBHS_PHY_CLK - USB HS PHY clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_USBHS_PHY_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_USBHS_PHY_CLK_SHIFT)) & CLKCTL0_PSCCTL0_USBHS_PHY_CLK_MASK)
+#define CLKCTL0_PSCCTL0_USBHS_DEVICE_CLK_MASK (0x200000U)
+#define CLKCTL0_PSCCTL0_USBHS_DEVICE_CLK_SHIFT (21U)
+/*! USBHS_DEVICE_CLK - USB HS Device clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_USBHS_DEVICE_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_USBHS_DEVICE_CLK_SHIFT)) & CLKCTL0_PSCCTL0_USBHS_DEVICE_CLK_MASK)
+#define CLKCTL0_PSCCTL0_USBHS_HOST_CLK_MASK (0x400000U)
+#define CLKCTL0_PSCCTL0_USBHS_HOST_CLK_SHIFT (22U)
+/*! USBHS_HOST_CLK - USB HS Host clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_USBHS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_USBHS_HOST_CLK_SHIFT)) & CLKCTL0_PSCCTL0_USBHS_HOST_CLK_MASK)
+#define CLKCTL0_PSCCTL0_USBHS_SRAM_CLK_MASK (0x800000U)
+#define CLKCTL0_PSCCTL0_USBHS_SRAM_CLK_SHIFT (23U)
+/*! USBHS_SRAM_CLK - USB HS SRAM clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_USBHS_SRAM_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_USBHS_SRAM_CLK_SHIFT)) & CLKCTL0_PSCCTL0_USBHS_SRAM_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SCT_CLK_MASK (0x1000000U)
+#define CLKCTL0_PSCCTL0_SCT_CLK_SHIFT (24U)
+/*! SCT_CLK - SCT clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_SCT_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SCT_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SCT_CLK_MASK)
+#define CLKCTL0_PSCCTL0_GPU_CLK_MASK (0x4000000U)
+#define CLKCTL0_PSCCTL0_GPU_CLK_SHIFT (26U)
+/*! GPU_CLK - GPU clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_GPU_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_GPU_CLK_SHIFT)) & CLKCTL0_PSCCTL0_GPU_CLK_MASK)
+#define CLKCTL0_PSCCTL0_DISPLAY_CTLR_CLK_MASK (0x8000000U)
+#define CLKCTL0_PSCCTL0_DISPLAY_CTLR_CLK_SHIFT (27U)
+/*! DISPLAY_CTLR_CLK - Display Controller clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_DISPLAY_CTLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_DISPLAY_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_DISPLAY_CTLR_CLK_MASK)
+#define CLKCTL0_PSCCTL0_MIPI_DSI_CTLR_CLK_MASK (0x10000000U)
+#define CLKCTL0_PSCCTL0_MIPI_DSI_CTLR_CLK_SHIFT (28U)
+/*! MIPI_DSI_CTLR_CLK - MIPI-DSI Controller clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_MIPI_DSI_CTLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_MIPI_DSI_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_MIPI_DSI_CTLR_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SMARTDMA_CLK_MASK (0x40000000U)
+#define CLKCTL0_PSCCTL0_SMARTDMA_CLK_SHIFT (30U)
+/*! SMARTDMA_CLK - Smart DMA clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL0_SMARTDMA_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SMARTDMA_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SMARTDMA_CLK_MASK)
+/*! @} */
+
+/*! @name PSCCTL1 - Clock Control 1 */
+/*! @{ */
+#define CLKCTL0_PSCCTL1_SDIO0_CLK_MASK (0x4U)
+#define CLKCTL0_PSCCTL1_SDIO0_CLK_SHIFT (2U)
+/*! SDIO0_CLK - SDIO0 clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL1_SDIO0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SDIO0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SDIO0_CLK_MASK)
+#define CLKCTL0_PSCCTL1_SDIO1_CLK_MASK (0x8U)
+#define CLKCTL0_PSCCTL1_SDIO1_CLK_SHIFT (3U)
+/*! SDIO1_CLK - SDIO1 clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL1_SDIO1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SDIO1_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SDIO1_CLK_MASK)
+#define CLKCTL0_PSCCTL1_ACMP0_CLK_MASK (0x8000U)
+#define CLKCTL0_PSCCTL1_ACMP0_CLK_SHIFT (15U)
+/*! ACMP0_CLK - ACMP0 clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL1_ACMP0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_ACMP0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_ACMP0_CLK_MASK)
+#define CLKCTL0_PSCCTL1_ADC0_CLK_MASK (0x10000U)
+#define CLKCTL0_PSCCTL1_ADC0_CLK_SHIFT (16U)
+/*! ADC0_CLK - ADC0 clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL1_ADC0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_ADC0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_ADC0_CLK_MASK)
+#define CLKCTL0_PSCCTL1_SHSGPIO0_CLK_MASK (0x1000000U)
+#define CLKCTL0_PSCCTL1_SHSGPIO0_CLK_SHIFT (24U)
+/*! SHSGPIO0_CLK - SHSGPIO0 clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL1_SHSGPIO0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SHSGPIO0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SHSGPIO0_CLK_MASK)
+/*! @} */
+
+/*! @name PSCCTL2 - Clock Control 2 */
+/*! @{ */
+#define CLKCTL0_PSCCTL2_UTICK0_CLK_MASK (0x1U)
+#define CLKCTL0_PSCCTL2_UTICK0_CLK_SHIFT (0U)
+/*! UTICK0_CLK - Micro-Tick Timer 0 clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL2_UTICK0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_UTICK0_CLK_SHIFT)) & CLKCTL0_PSCCTL2_UTICK0_CLK_MASK)
+#define CLKCTL0_PSCCTL2_WWDT0_CLK_MASK (0x2U)
+#define CLKCTL0_PSCCTL2_WWDT0_CLK_SHIFT (1U)
+/*! WWDT0_CLK - Watchdog Timer 0 clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL2_WWDT0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_WWDT0_CLK_SHIFT)) & CLKCTL0_PSCCTL2_WWDT0_CLK_MASK)
+#define CLKCTL0_PSCCTL2_PMC_CLK_MASK (0x20000000U)
+#define CLKCTL0_PSCCTL2_PMC_CLK_SHIFT (29U)
+/*! PMC_CLK - Power Management Controller clock control
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_PSCCTL2_PMC_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_PMC_CLK_SHIFT)) & CLKCTL0_PSCCTL2_PMC_CLK_MASK)
+/*! @} */
+
+/*! @name PSCCTL0_SET - Clock Control 0 Set */
+/*! @{ */
+#define CLKCTL0_PSCCTL0_SET_DSP_CLK_MASK (0x2U)
+#define CLKCTL0_PSCCTL0_SET_DSP_CLK_SHIFT (1U)
+/*! DSP_CLK - DSP clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_DSP_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_DSP_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_DSP_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_ROM_CTRLR_CLK_MASK (0x4U)
+#define CLKCTL0_PSCCTL0_SET_ROM_CTRLR_CLK_SHIFT (2U)
+/*! ROM_CTRLR_CLK - 128KB ROM Controller clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_ROM_CTRLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_ROM_CTRLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_ROM_CTRLR_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_AXI_SWITCH_CLK_MASK (0x8U)
+#define CLKCTL0_PSCCTL0_SET_AXI_SWITCH_CLK_SHIFT (3U)
+/*! AXI_SWITCH_CLK - AXI Switch clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_AXI_SWITCH_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_AXI_SWITCH_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_AXI_SWITCH_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_AXI_CTLR_CLK_MASK (0x10U)
+#define CLKCTL0_PSCCTL0_SET_AXI_CTLR_CLK_SHIFT (4U)
+/*! AXI_CTLR_CLK - AXI Controller clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_AXI_CTLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_AXI_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_AXI_CTLR_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_POWERQUAD_CLK_MASK (0x100U)
+#define CLKCTL0_PSCCTL0_SET_POWERQUAD_CLK_SHIFT (8U)
+/*! POWERQUAD_CLK - POWERQUAD clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_POWERQUAD_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_POWERQUAD_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_POWERQUAD_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_CASPER_CLK_MASK (0x200U)
+#define CLKCTL0_PSCCTL0_SET_CASPER_CLK_SHIFT (9U)
+/*! CASPER_CLK - CASPER clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_CASPER_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_CASPER_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_CASPER_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_HASHCRYPT_CLK_MASK (0x400U)
+#define CLKCTL0_PSCCTL0_SET_HASHCRYPT_CLK_SHIFT (10U)
+/*! HASHCRYPT_CLK - HASHCRYPT clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_HASHCRYPT_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_HASHCRYPT_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_HASHCRYPT_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_PUF_CLK_MASK (0x800U)
+#define CLKCTL0_PSCCTL0_SET_PUF_CLK_SHIFT (11U)
+/*! PUF_CLK - PUF clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_PUF_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_PUF_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_PUF_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_RNG_CLK_MASK (0x1000U)
+#define CLKCTL0_PSCCTL0_SET_RNG_CLK_SHIFT (12U)
+/*! RNG_CLK - Random Number Generator (RNG) clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_RNG_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_RNG_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_RNG_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK (0x10000U)
+#define CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_SHIFT (16U)
+/*! FLEXSPI0_OTFAD_CLK - FLEXSPI0 / OTFAD clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_OTP_CTLR_CLK_MASK (0x20000U)
+#define CLKCTL0_PSCCTL0_SET_OTP_CTLR_CLK_SHIFT (17U)
+/*! OTP_CTLR_CLK - OTP Controller clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_OTP_CTLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_OTP_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_OTP_CTLR_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK (0x40000U)
+#define CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_SHIFT (18U)
+/*! FLEXSPI1_CLK - FLEXSPI1 clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_USBHS_PHY_CLK_MASK (0x100000U)
+#define CLKCTL0_PSCCTL0_SET_USBHS_PHY_CLK_SHIFT (20U)
+/*! USBHS_PHY_CLK - USB HS PHY clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_USBHS_PHY_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_USBHS_PHY_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_USBHS_PHY_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_USBHS_DEVICE_CLK_MASK (0x200000U)
+#define CLKCTL0_PSCCTL0_SET_USBHS_DEVICE_CLK_SHIFT (21U)
+/*! USBHS_DEVICE_CLK - USB HS Device clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_USBHS_DEVICE_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_USBHS_DEVICE_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_USBHS_DEVICE_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_USBHS_HOST_CLK_MASK (0x400000U)
+#define CLKCTL0_PSCCTL0_SET_USBHS_HOST_CLK_SHIFT (22U)
+/*! USBHS_HOST_CLK - USB HS Host clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_USBHS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_USBHS_HOST_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_USBHS_HOST_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_USBHS_SRAM_CLK_MASK (0x800000U)
+#define CLKCTL0_PSCCTL0_SET_USBHS_SRAM_CLK_SHIFT (23U)
+/*! USBHS_SRAM_CLK - USB HS SRAM clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_USBHS_SRAM_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_USBHS_SRAM_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_USBHS_SRAM_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_SCT_CLK_MASK (0x1000000U)
+#define CLKCTL0_PSCCTL0_SET_SCT_CLK_SHIFT (24U)
+/*! SCT_CLK - SCT clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_SCT_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_SCT_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_SCT_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_GPU_CLK_MASK (0x4000000U)
+#define CLKCTL0_PSCCTL0_SET_GPU_CLK_SHIFT (26U)
+/*! GPU_CLK - GPU clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_GPU_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_GPU_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_GPU_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_DISPLAY_CTLR_CLK_MASK (0x8000000U)
+#define CLKCTL0_PSCCTL0_SET_DISPLAY_CTLR_CLK_SHIFT (27U)
+/*! DISPLAY_CTLR_CLK - Display Controller clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_DISPLAY_CTLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_DISPLAY_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_DISPLAY_CTLR_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_MIPI_DSI_CTLR_CLK_MASK (0x10000000U)
+#define CLKCTL0_PSCCTL0_SET_MIPI_DSI_CTLR_CLK_SHIFT (28U)
+/*! MIPI_DSI_CTLR_CLK - MIPI-DSI Controller clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_MIPI_DSI_CTLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_MIPI_DSI_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_MIPI_DSI_CTLR_CLK_MASK)
+#define CLKCTL0_PSCCTL0_SET_SMARTDMA_CLK_MASK (0x40000000U)
+#define CLKCTL0_PSCCTL0_SET_SMARTDMA_CLK_SHIFT (30U)
+/*! SMARTDMA_CLK - Smart DMA clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_SET_SMARTDMA_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_SMARTDMA_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_SMARTDMA_CLK_MASK)
+/*! @} */
+
+/*! @name PSCCTL1_SET - Clock Control 1 Set */
+/*! @{ */
+#define CLKCTL0_PSCCTL1_SET_SDIO0_CLK_MASK (0x4U)
+#define CLKCTL0_PSCCTL1_SET_SDIO0_CLK_SHIFT (2U)
+/*! SDIO0_CLK - SDIO0 clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL1 register
+ */
+#define CLKCTL0_PSCCTL1_SET_SDIO0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_SDIO0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SET_SDIO0_CLK_MASK)
+#define CLKCTL0_PSCCTL1_SET_SDIO1_CLK_MASK (0x8U)
+#define CLKCTL0_PSCCTL1_SET_SDIO1_CLK_SHIFT (3U)
+/*! SDIO1_CLK - SDIO1 clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL1 register
+ */
+#define CLKCTL0_PSCCTL1_SET_SDIO1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_SDIO1_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SET_SDIO1_CLK_MASK)
+#define CLKCTL0_PSCCTL1_SET_ACMP0_CLK_MASK (0x8000U)
+#define CLKCTL0_PSCCTL1_SET_ACMP0_CLK_SHIFT (15U)
+/*! ACMP0_CLK - ACMP0 clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL1 register
+ */
+#define CLKCTL0_PSCCTL1_SET_ACMP0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_ACMP0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SET_ACMP0_CLK_MASK)
+#define CLKCTL0_PSCCTL1_SET_ADC0_CLK_MASK (0x10000U)
+#define CLKCTL0_PSCCTL1_SET_ADC0_CLK_SHIFT (16U)
+/*! ADC0_CLK - ADC0 clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL1 register
+ */
+#define CLKCTL0_PSCCTL1_SET_ADC0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_ADC0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SET_ADC0_CLK_MASK)
+#define CLKCTL0_PSCCTL1_SET_SHSGPIO0_CLK_MASK (0x1000000U)
+#define CLKCTL0_PSCCTL1_SET_SHSGPIO0_CLK_SHIFT (24U)
+/*! SHSGPIO0_CLK - SHSGPIO0 clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL1 register
+ */
+#define CLKCTL0_PSCCTL1_SET_SHSGPIO0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_SHSGPIO0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SET_SHSGPIO0_CLK_MASK)
+/*! @} */
+
+/*! @name PSCCTL2_SET - Clock Control 2 Set */
+/*! @{ */
+#define CLKCTL0_PSCCTL2_SET_UTICK0_CLK_MASK (0x1U)
+#define CLKCTL0_PSCCTL2_SET_UTICK0_CLK_SHIFT (0U)
+/*! UTICK0_CLK - Micro-Tick Timer 0 clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL2 register
+ */
+#define CLKCTL0_PSCCTL2_SET_UTICK0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_UTICK0_CLK_SHIFT)) & CLKCTL0_PSCCTL2_SET_UTICK0_CLK_MASK)
+#define CLKCTL0_PSCCTL2_SET_WWDT0_CLK_MASK (0x2U)
+#define CLKCTL0_PSCCTL2_SET_WWDT0_CLK_SHIFT (1U)
+/*! WWDT0_CLK - Watchdog Timer 0 clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL2 register
+ */
+#define CLKCTL0_PSCCTL2_SET_WWDT0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_WWDT0_CLK_SHIFT)) & CLKCTL0_PSCCTL2_SET_WWDT0_CLK_MASK)
+#define CLKCTL0_PSCCTL2_SET_PMC_MASK (0x20000000U)
+#define CLKCTL0_PSCCTL2_SET_PMC_SHIFT (29U)
+/*! PMC - Power Management Controller clock set
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit in PSCCTL2 register
+ */
+#define CLKCTL0_PSCCTL2_SET_PMC(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_PMC_SHIFT)) & CLKCTL0_PSCCTL2_SET_PMC_MASK)
+/*! @} */
+
+/*! @name PSCCTL0_CLR - Clock Control 0 Clear */
+/*! @{ */
+#define CLKCTL0_PSCCTL0_CLR_DSP_CLK_MASK (0x2U)
+#define CLKCTL0_PSCCTL0_CLR_DSP_CLK_SHIFT (1U)
+/*! DSP_CLK - DSP clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_DSP_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_DSP_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_DSP_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_ROM_CTRLR_CLK_MASK (0x4U)
+#define CLKCTL0_PSCCTL0_CLR_ROM_CTRLR_CLK_SHIFT (2U)
+/*! ROM_CTRLR_CLK - 128KB ROM Controller clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_ROM_CTRLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_ROM_CTRLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_ROM_CTRLR_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_AXI_SWITCH_CLK_MASK (0x8U)
+#define CLKCTL0_PSCCTL0_CLR_AXI_SWITCH_CLK_SHIFT (3U)
+/*! AXI_SWITCH_CLK - AXI Switch clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_AXI_SWITCH_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_AXI_SWITCH_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_AXI_SWITCH_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_AXI_CTLR_CLK_MASK (0x10U)
+#define CLKCTL0_PSCCTL0_CLR_AXI_CTLR_CLK_SHIFT (4U)
+/*! AXI_CTLR_CLK - AXI Controller clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_AXI_CTLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_AXI_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_AXI_CTLR_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_POWERQUAD_CLK_MASK (0x100U)
+#define CLKCTL0_PSCCTL0_CLR_POWERQUAD_CLK_SHIFT (8U)
+/*! POWERQUAD_CLK - POWERQUAD clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_POWERQUAD_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_POWERQUAD_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_POWERQUAD_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_CASPER_CLK_MASK (0x200U)
+#define CLKCTL0_PSCCTL0_CLR_CASPER_CLK_SHIFT (9U)
+/*! CASPER_CLK - CASPER clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_CASPER_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_CASPER_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_CASPER_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_HASHCRYPT_CLK_MASK (0x400U)
+#define CLKCTL0_PSCCTL0_CLR_HASHCRYPT_CLK_SHIFT (10U)
+/*! HASHCRYPT_CLK - HASHCRYPT clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_HASHCRYPT_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_HASHCRYPT_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_HASHCRYPT_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_PUF_CLK_MASK (0x800U)
+#define CLKCTL0_PSCCTL0_CLR_PUF_CLK_SHIFT (11U)
+/*! PUF_CLK - PUF clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_PUF_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_PUF_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_PUF_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_RNG_CLK_MASK (0x1000U)
+#define CLKCTL0_PSCCTL0_CLR_RNG_CLK_SHIFT (12U)
+/*! RNG_CLK - RNG clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_RNG_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_RNG_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_RNG_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_MASK (0x10000U)
+#define CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_SHIFT (16U)
+/*! FLEXSPI0_OTFAD_CLK - FLEXSPI0 / OTFAD clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_OTP_CTLR_CLK_MASK (0x20000U)
+#define CLKCTL0_PSCCTL0_CLR_OTP_CTLR_CLK_SHIFT (17U)
+/*! OTP_CTLR_CLK - OTP Controller clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_OTP_CTLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_OTP_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_OTP_CTLR_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_MASK (0x40000U)
+#define CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_SHIFT (18U)
+/*! FLEXSPI1_CLK - FLEXSPI1 clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_USBHS_PHY_CLK_MASK (0x100000U)
+#define CLKCTL0_PSCCTL0_CLR_USBHS_PHY_CLK_SHIFT (20U)
+/*! USBHS_PHY_CLK - USB HS PHY clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_USBHS_PHY_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_USBHS_PHY_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_USBHS_PHY_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_USBHS_DEVICE_CLK_MASK (0x200000U)
+#define CLKCTL0_PSCCTL0_CLR_USBHS_DEVICE_CLK_SHIFT (21U)
+/*! USBHS_DEVICE_CLK - USB HS Device clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_USBHS_DEVICE_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_USBHS_DEVICE_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_USBHS_DEVICE_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_USBHS_HOST_CLK_MASK (0x400000U)
+#define CLKCTL0_PSCCTL0_CLR_USBHS_HOST_CLK_SHIFT (22U)
+/*! USBHS_HOST_CLK - USB HS Host clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_USBHS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_USBHS_HOST_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_USBHS_HOST_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_USBHS_SRAM_CLK_MASK (0x800000U)
+#define CLKCTL0_PSCCTL0_CLR_USBHS_SRAM_CLK_SHIFT (23U)
+/*! USBHS_SRAM_CLK - USB HS SRAM clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_USBHS_SRAM_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_USBHS_SRAM_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_USBHS_SRAM_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_SCT_CLK_MASK (0x1000000U)
+#define CLKCTL0_PSCCTL0_CLR_SCT_CLK_SHIFT (24U)
+/*! SCT_CLK - SCT clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_SCT_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_SCT_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_SCT_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_GPU_CLK_MASK (0x4000000U)
+#define CLKCTL0_PSCCTL0_CLR_GPU_CLK_SHIFT (26U)
+/*! GPU_CLK - GPU clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_GPU_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_GPU_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_GPU_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_DISPLAY_CTLR_CLK_MASK (0x8000000U)
+#define CLKCTL0_PSCCTL0_CLR_DISPLAY_CTLR_CLK_SHIFT (27U)
+/*! DISPLAY_CTLR_CLK - Display Controller clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_DISPLAY_CTLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_DISPLAY_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_DISPLAY_CTLR_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_MIPI_DSI_CTLR_CLK_MASK (0x10000000U)
+#define CLKCTL0_PSCCTL0_CLR_MIPI_DSI_CTLR_CLK_SHIFT (28U)
+/*! MIPI_DSI_CTLR_CLK - MIPI-DSI Controller clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_MIPI_DSI_CTLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_MIPI_DSI_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_MIPI_DSI_CTLR_CLK_MASK)
+#define CLKCTL0_PSCCTL0_CLR_SMARTDMA_CLK_MASK (0x40000000U)
+#define CLKCTL0_PSCCTL0_CLR_SMARTDMA_CLK_SHIFT (30U)
+/*! SMARTDMA_CLK - Smart DMA clock set
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL0 register
+ */
+#define CLKCTL0_PSCCTL0_CLR_SMARTDMA_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_SMARTDMA_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_SMARTDMA_CLK_MASK)
+/*! @} */
+
+/*! @name PSCCTL1_CLR - Clock Control 1 Clear */
+/*! @{ */
+#define CLKCTL0_PSCCTL1_CLR_SDIO0_CLK_MASK (0x4U)
+#define CLKCTL0_PSCCTL1_CLR_SDIO0_CLK_SHIFT (2U)
+/*! SDIO0_CLK - SDIO0 clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL1 register
+ */
+#define CLKCTL0_PSCCTL1_CLR_SDIO0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_SDIO0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_CLR_SDIO0_CLK_MASK)
+#define CLKCTL0_PSCCTL1_CLR_SDIO1_CLK_MASK (0x8U)
+#define CLKCTL0_PSCCTL1_CLR_SDIO1_CLK_SHIFT (3U)
+/*! SDIO1_CLK - SDIO1 clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL1 register
+ */
+#define CLKCTL0_PSCCTL1_CLR_SDIO1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_SDIO1_CLK_SHIFT)) & CLKCTL0_PSCCTL1_CLR_SDIO1_CLK_MASK)
+#define CLKCTL0_PSCCTL1_CLR_ACMP0_CLK_MASK (0x8000U)
+#define CLKCTL0_PSCCTL1_CLR_ACMP0_CLK_SHIFT (15U)
+/*! ACMP0_CLK - ACMP0 clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL1 register
+ */
+#define CLKCTL0_PSCCTL1_CLR_ACMP0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_ACMP0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_CLR_ACMP0_CLK_MASK)
+#define CLKCTL0_PSCCTL1_CLR_ADC0_CLK_MASK (0x10000U)
+#define CLKCTL0_PSCCTL1_CLR_ADC0_CLK_SHIFT (16U)
+/*! ADC0_CLK - ADC0 clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL1 register
+ */
+#define CLKCTL0_PSCCTL1_CLR_ADC0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_ADC0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_CLR_ADC0_CLK_MASK)
+#define CLKCTL0_PSCCTL1_CLR_SHSGPIO0_CLK_MASK (0x1000000U)
+#define CLKCTL0_PSCCTL1_CLR_SHSGPIO0_CLK_SHIFT (24U)
+/*! SHSGPIO0_CLK - SHSGPIO0 clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL1 register
+ */
+#define CLKCTL0_PSCCTL1_CLR_SHSGPIO0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_SHSGPIO0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_CLR_SHSGPIO0_CLK_MASK)
+/*! @} */
+
+/*! @name PSCCTL2_CLR - Clock Control 2 Clear */
+/*! @{ */
+#define CLKCTL0_PSCCTL2_CLR_UTICK0_CLK_MASK (0x1U)
+#define CLKCTL0_PSCCTL2_CLR_UTICK0_CLK_SHIFT (0U)
+/*! UTICK0_CLK - Micro-Tick Timer 0 clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL2 register
+ */
+#define CLKCTL0_PSCCTL2_CLR_UTICK0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_UTICK0_CLK_SHIFT)) & CLKCTL0_PSCCTL2_CLR_UTICK0_CLK_MASK)
+#define CLKCTL0_PSCCTL2_CLR_WWDT0_CLK_MASK (0x2U)
+#define CLKCTL0_PSCCTL2_CLR_WWDT0_CLK_SHIFT (1U)
+/*! WWDT0_CLK - Watchdog Timer 0 clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL2 register
+ */
+#define CLKCTL0_PSCCTL2_CLR_WWDT0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_WWDT0_CLK_SHIFT)) & CLKCTL0_PSCCTL2_CLR_WWDT0_CLK_MASK)
+#define CLKCTL0_PSCCTL2_CLR_PMC_CLK_MASK (0x20000000U)
+#define CLKCTL0_PSCCTL2_CLR_PMC_CLK_SHIFT (29U)
+/*! PMC_CLK - Power Management Controller clock clear
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit in PSCCTL2 register
+ */
+#define CLKCTL0_PSCCTL2_CLR_PMC_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_PMC_CLK_SHIFT)) & CLKCTL0_PSCCTL2_CLR_PMC_CLK_MASK)
+/*! @} */
+
+/*! @name FRO_CONTROL - Free Running Oscillator Control */
+/*! @{ */
+#define CLKCTL0_FRO_CONTROL_EXP_COUNT_MASK (0xFFFFU)
+#define CLKCTL0_FRO_CONTROL_EXP_COUNT_SHIFT (0U)
+/*! EXP_COUNT - Expected Count
+ */
+#define CLKCTL0_FRO_CONTROL_EXP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO_CONTROL_EXP_COUNT_SHIFT)) & CLKCTL0_FRO_CONTROL_EXP_COUNT_MASK)
+#define CLKCTL0_FRO_CONTROL_THRESH_RANGE_UP_MASK (0x1F0000U)
+#define CLKCTL0_FRO_CONTROL_THRESH_RANGE_UP_SHIFT (16U)
+/*! THRESH_RANGE_UP - Threshold Range Upper Limit
+ */
+#define CLKCTL0_FRO_CONTROL_THRESH_RANGE_UP(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO_CONTROL_THRESH_RANGE_UP_SHIFT)) & CLKCTL0_FRO_CONTROL_THRESH_RANGE_UP_MASK)
+#define CLKCTL0_FRO_CONTROL_THRESH_RANGE_LOW_MASK (0x3E00000U)
+#define CLKCTL0_FRO_CONTROL_THRESH_RANGE_LOW_SHIFT (21U)
+/*! THRESH_RANGE_LOW - Threshold Range Lower Limit
+ */
+#define CLKCTL0_FRO_CONTROL_THRESH_RANGE_LOW(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO_CONTROL_THRESH_RANGE_LOW_SHIFT)) & CLKCTL0_FRO_CONTROL_THRESH_RANGE_LOW_MASK)
+#define CLKCTL0_FRO_CONTROL_ENA_TUNE_MASK (0x80000000U)
+#define CLKCTL0_FRO_CONTROL_ENA_TUNE_SHIFT (31U)
+/*! ENA_TUNE - Enable Tuning
+ * 0b0..Stop tuning
+ * 0b1..Start tuning
+ */
+#define CLKCTL0_FRO_CONTROL_ENA_TUNE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO_CONTROL_ENA_TUNE_SHIFT)) & CLKCTL0_FRO_CONTROL_ENA_TUNE_MASK)
+/*! @} */
+
+/*! @name FRO_CAPVAL - Free Running Oscillator Captured Value */
+/*! @{ */
+#define CLKCTL0_FRO_CAPVAL_CAPVAL_MASK (0xFFFFU)
+#define CLKCTL0_FRO_CAPVAL_CAPVAL_SHIFT (0U)
+/*! CAPVAL - Captured Value
+ */
+#define CLKCTL0_FRO_CAPVAL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO_CAPVAL_CAPVAL_SHIFT)) & CLKCTL0_FRO_CAPVAL_CAPVAL_MASK)
+#define CLKCTL0_FRO_CAPVAL_DATA_VALID_MASK (0x80000000U)
+#define CLKCTL0_FRO_CAPVAL_DATA_VALID_SHIFT (31U)
+/*! DATA_VALID - Data Valid
+ * 0b0..CAPVAL data is not valid
+ * 0b1..CAPVAL data is valid
+ */
+#define CLKCTL0_FRO_CAPVAL_DATA_VALID(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO_CAPVAL_DATA_VALID_SHIFT)) & CLKCTL0_FRO_CAPVAL_DATA_VALID_MASK)
+/*! @} */
+
+/*! @name FRO_RDTRIM - Free Running Oscillator Trim */
+/*! @{ */
+#define CLKCTL0_FRO_RDTRIM_TRIM_MASK (0x7FFU)
+#define CLKCTL0_FRO_RDTRIM_TRIM_SHIFT (0U)
+/*! TRIM - It is the trim value supplied to the oscillator
+ */
+#define CLKCTL0_FRO_RDTRIM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO_RDTRIM_TRIM_SHIFT)) & CLKCTL0_FRO_RDTRIM_TRIM_MASK)
+/*! @} */
+
+/*! @name FRO_SCTRIM - Free Running OscillatorSC Trim */
+/*! @{ */
+#define CLKCTL0_FRO_SCTRIM_TRIM_MASK (0x7FFU)
+#define CLKCTL0_FRO_SCTRIM_TRIM_SHIFT (0U)
+/*! TRIM - sc_trim value for the oscillator.
+ */
+#define CLKCTL0_FRO_SCTRIM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO_SCTRIM_TRIM_SHIFT)) & CLKCTL0_FRO_SCTRIM_TRIM_MASK)
+/*! @} */
+
+/*! @name FRODIVSEL - FRO Clock Divider */
+/*! @{ */
+#define CLKCTL0_FRODIVSEL_SEL_MASK (0x3U)
+#define CLKCTL0_FRODIVSEL_SEL_SHIFT (0U)
+/*! SEL - Select clock
+ * 0b00..FRO_DIV2
+ * 0b01..FRO_DIV4
+ * 0b10..FRO_DIV8
+ * 0b11..FRO_DIV16
+ */
+#define CLKCTL0_FRODIVSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRODIVSEL_SEL_SHIFT)) & CLKCTL0_FRODIVSEL_SEL_MASK)
+/*! @} */
+
+/*! @name FROCLKSTATUS - FRO Clock Status */
+/*! @{ */
+#define CLKCTL0_FROCLKSTATUS_CLK_OK_MASK (0x1U)
+#define CLKCTL0_FROCLKSTATUS_CLK_OK_SHIFT (0U)
+/*! CLK_OK - FRO Clock OK
+ * 0b0..FRO clock has not yet reached its final frequency
+ * 0b1..FRO clock has reached its final frequency
+ */
+#define CLKCTL0_FROCLKSTATUS_CLK_OK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FROCLKSTATUS_CLK_OK_SHIFT)) & CLKCTL0_FROCLKSTATUS_CLK_OK_MASK)
+/*! @} */
+
+/*! @name FRODIVOEN - FRO Enable Register */
+/*! @{ */
+#define CLKCTL0_FRODIVOEN_FRO_DIV1_O_EN_MASK (0x1U)
+#define CLKCTL0_FRODIVOEN_FRO_DIV1_O_EN_SHIFT (0U)
+/*! FRO_DIV1_O_EN - FRO Divided-by-1 Clock Enable
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_FRODIVOEN_FRO_DIV1_O_EN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRODIVOEN_FRO_DIV1_O_EN_SHIFT)) & CLKCTL0_FRODIVOEN_FRO_DIV1_O_EN_MASK)
+#define CLKCTL0_FRODIVOEN_FRO_DIV2_O_EN_MASK (0x2U)
+#define CLKCTL0_FRODIVOEN_FRO_DIV2_O_EN_SHIFT (1U)
+/*! FRO_DIV2_O_EN - FRO Divided-by-2 Clock Enable
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_FRODIVOEN_FRO_DIV2_O_EN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRODIVOEN_FRO_DIV2_O_EN_SHIFT)) & CLKCTL0_FRODIVOEN_FRO_DIV2_O_EN_MASK)
+#define CLKCTL0_FRODIVOEN_FRO_DIV4_O_EN_MASK (0x4U)
+#define CLKCTL0_FRODIVOEN_FRO_DIV4_O_EN_SHIFT (2U)
+/*! FRO_DIV4_O_EN - FRO Divided-by-4 Clock Enable
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_FRODIVOEN_FRO_DIV4_O_EN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRODIVOEN_FRO_DIV4_O_EN_SHIFT)) & CLKCTL0_FRODIVOEN_FRO_DIV4_O_EN_MASK)
+#define CLKCTL0_FRODIVOEN_FRO_DIV8_O_EN_MASK (0x8U)
+#define CLKCTL0_FRODIVOEN_FRO_DIV8_O_EN_SHIFT (3U)
+/*! FRO_DIV8_O_EN - FRO Divided-by-8 Clock Enable
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_FRODIVOEN_FRO_DIV8_O_EN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRODIVOEN_FRO_DIV8_O_EN_SHIFT)) & CLKCTL0_FRODIVOEN_FRO_DIV8_O_EN_MASK)
+#define CLKCTL0_FRODIVOEN_FRO_DIV16_O_EN_MASK (0x10U)
+#define CLKCTL0_FRODIVOEN_FRO_DIV16_O_EN_SHIFT (4U)
+/*! FRO_DIV16_O_EN - FRO Divided-by-16 Clock Enable
+ * 0b0..Disable clock
+ * 0b1..Enable clock
+ */
+#define CLKCTL0_FRODIVOEN_FRO_DIV16_O_EN(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRODIVOEN_FRO_DIV16_O_EN_SHIFT)) & CLKCTL0_FRODIVOEN_FRO_DIV16_O_EN_MASK)
+/*! @} */
+
+/*! @name LOWFREQCLKDIV - Low Frequency Clock Divider */
+/*! @{ */
+#define CLKCTL0_LOWFREQCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_LOWFREQCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Low Frequency Clock Divider Value
+ */
+#define CLKCTL0_LOWFREQCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_LOWFREQCLKDIV_DIV_SHIFT)) & CLKCTL0_LOWFREQCLKDIV_DIV_MASK)
+#define CLKCTL0_LOWFREQCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_LOWFREQCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_LOWFREQCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_LOWFREQCLKDIV_RESET_SHIFT)) & CLKCTL0_LOWFREQCLKDIV_RESET_MASK)
+#define CLKCTL0_LOWFREQCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_LOWFREQCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_LOWFREQCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_LOWFREQCLKDIV_HALT_SHIFT)) & CLKCTL0_LOWFREQCLKDIV_HALT_MASK)
+#define CLKCTL0_LOWFREQCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_LOWFREQCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider Status Flag
+ * 0b0..The Divider change has finished
+ * 0b1..The Divider value has changed
+ */
+#define CLKCTL0_LOWFREQCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_LOWFREQCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_LOWFREQCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SYSOSCCTL0 - System Oscillator Control 0 */
+/*! @{ */
+#define CLKCTL0_SYSOSCCTL0_LP_ENABLE_MASK (0x1U)
+#define CLKCTL0_SYSOSCCTL0_LP_ENABLE_SHIFT (0U)
+/*! LP_ENABLE - Low Power Mode Enable
+ * 0b0..Enable High Gain Mode (HP)
+ * 0b1..Enable Low Power mode (LP)
+ */
+#define CLKCTL0_SYSOSCCTL0_LP_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSOSCCTL0_LP_ENABLE_SHIFT)) & CLKCTL0_SYSOSCCTL0_LP_ENABLE_MASK)
+#define CLKCTL0_SYSOSCCTL0_BYPASS_ENABLE_MASK (0x2U)
+#define CLKCTL0_SYSOSCCTL0_BYPASS_ENABLE_SHIFT (1U)
+/*! BYPASS_ENABLE - Bypass Enable
+ * 0b0..Enable Normal mode. Oscillation with crystal connected.
+ * 0b1..Enable Bypass mode. In this mode a clock can be directly input into the XTALIN pin.
+ */
+#define CLKCTL0_SYSOSCCTL0_BYPASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSOSCCTL0_BYPASS_ENABLE_SHIFT)) & CLKCTL0_SYSOSCCTL0_BYPASS_ENABLE_MASK)
+/*! @} */
+
+/*! @name SYSOSCBYPASS - OSC Clock Source Select */
+/*! @{ */
+#define CLKCTL0_SYSOSCBYPASS_SEL_MASK (0x7U)
+#define CLKCTL0_SYSOSCBYPASS_SEL_SHIFT (0U)
+/*! SEL - Select SYSOSC Bypass
+ * 0b000..Select OSC Clock
+ * 0b001..Select Clock IN clock
+ * 0b010..Reserved
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed
+ */
+#define CLKCTL0_SYSOSCBYPASS_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSOSCBYPASS_SEL_SHIFT)) & CLKCTL0_SYSOSCBYPASS_SEL_MASK)
+/*! @} */
+
+/*! @name LPOSCCTL0 - Low Power Oscillator Control 0 */
+/*! @{ */
+#define CLKCTL0_LPOSCCTL0_CLKRDY_MASK (0x80000000U)
+#define CLKCTL0_LPOSCCTL0_CLKRDY_SHIFT (31U)
+/*! CLKRDY - LPOSC Clock Ready
+ * 0b0..LPOSC clock is not ready
+ * 0b1..LPOSC clock is ready
+ */
+#define CLKCTL0_LPOSCCTL0_CLKRDY(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_LPOSCCTL0_CLKRDY_SHIFT)) & CLKCTL0_LPOSCCTL0_CLKRDY_MASK)
+/*! @} */
+
+/*! @name OSC32KHZCTL0 - 32 KHz Oscillator Control 0 */
+/*! @{ */
+#define CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK (0x1U)
+#define CLKCTL0_OSC32KHZCTL0_ENA32KHZ_SHIFT (0U)
+/*! ENA32KHZ - 32 KHz Oscillator Enable
+ * 0b0..Disable oscillator
+ * 0b1..Enable oscillator
+ */
+#define CLKCTL0_OSC32KHZCTL0_ENA32KHZ(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_OSC32KHZCTL0_ENA32KHZ_SHIFT)) & CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK)
+/*! @} */
+
+/*! @name SYSPLL0CLKSEL - System PLL 0 Clock Select */
+/*! @{ */
+#define CLKCTL0_SYSPLL0CLKSEL_SEL_MASK (0x7U)
+#define CLKCTL0_SYSPLL0CLKSEL_SEL_SHIFT (0U)
+/*! SEL - System PLL0 Reference Input Clock Source
+ * 0b000..FRO_DIV8 Clock
+ * 0b001..OSC_CLK clock
+ * 0b010..Reserved
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL0_SYSPLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0CLKSEL_SEL_SHIFT)) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SYSPLL0CTL0 - System PLL0 Control 0 */
+/*! @{ */
+#define CLKCTL0_SYSPLL0CTL0_BYPASS_MASK (0x1U)
+#define CLKCTL0_SYSPLL0CTL0_BYPASS_SHIFT (0U)
+/*! BYPASS - SYSPLL0 BYPASS Mode
+ * 0b0..PFD outputs are PFD-programmed clocks
+ * 0b1..Bypass Mode: PFD outputs are sourced directly from rhe reference input clock
+ */
+#define CLKCTL0_SYSPLL0CTL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0CTL0_BYPASS_SHIFT)) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK)
+#define CLKCTL0_SYSPLL0CTL0_RESET_MASK (0x2U)
+#define CLKCTL0_SYSPLL0CTL0_RESET_SHIFT (1U)
+/*! RESET - SYSPLL0 Reset
+ * 0b0..SYSPLL0 reset is removed
+ * 0b1..SYSPLL0 is placed into reset
+ */
+#define CLKCTL0_SYSPLL0CTL0_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0CTL0_RESET_SHIFT)) & CLKCTL0_SYSPLL0CTL0_RESET_MASK)
+#define CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_MASK (0x2000U)
+#define CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_SHIFT (13U)
+/*! HOLDRINGOFF_ENA - Hold Ring Off Control
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_SHIFT)) & CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_MASK)
+#define CLKCTL0_SYSPLL0CTL0_MULT_MASK (0xFF0000U)
+#define CLKCTL0_SYSPLL0CTL0_MULT_SHIFT (16U)
+/*! MULT - Multiplication Factor
+ * 0b00010000..Divide by 16
+ * 0b00010001..Divide by 17
+ * 0b00010010..Divide by 18
+ * 0b00010011..Divide by 19
+ * 0b00010100..Divide by 20
+ * 0b00010101..Divide by 21
+ * 0b00010110..Divide by 22
+ */
+#define CLKCTL0_SYSPLL0CTL0_MULT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0CTL0_MULT_SHIFT)) & CLKCTL0_SYSPLL0CTL0_MULT_MASK)
+/*! @} */
+
+/*! @name SYSPLL0LOCKTIMEDIV2 - System PLL0 Lock Time Div2 */
+/*! @{ */
+#define CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK (0xFFFFU)
+#define CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT (0U)
+/*! LOCKTIMEDIV2 - SYSPLL0 Lock Time Divide-by-2
+ */
+#define CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT)) & CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK)
+/*! @} */
+
+/*! @name SYSPLL0NUM - System PLL0 Numerator */
+/*! @{ */
+#define CLKCTL0_SYSPLL0NUM_NUM_MASK (0x3FFFFFFFU)
+#define CLKCTL0_SYSPLL0NUM_NUM_SHIFT (0U)
+/*! NUM - Numerator of the SYSPLL0 fractional loop divider
+ */
+#define CLKCTL0_SYSPLL0NUM_NUM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0NUM_NUM_SHIFT)) & CLKCTL0_SYSPLL0NUM_NUM_MASK)
+/*! @} */
+
+/*! @name SYSPLL0DENOM - System PLL0 Denominator */
+/*! @{ */
+#define CLKCTL0_SYSPLL0DENOM_DENOM_MASK (0x3FFFFFFFU)
+#define CLKCTL0_SYSPLL0DENOM_DENOM_SHIFT (0U)
+/*! DENOM - Denominator of the SYSPLL0 fractional loop divider
+ */
+#define CLKCTL0_SYSPLL0DENOM_DENOM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0DENOM_DENOM_SHIFT)) & CLKCTL0_SYSPLL0DENOM_DENOM_MASK)
+/*! @} */
+
+/*! @name SYSPLL0PFD - System PLL0 PFD */
+/*! @{ */
+#define CLKCTL0_SYSPLL0PFD_PFD0_MASK (0x3FU)
+#define CLKCTL0_SYSPLL0PFD_PFD0_SHIFT (0U)
+/*! PFD0 - PLL Fractional Divider 0
+ */
+#define CLKCTL0_SYSPLL0PFD_PFD0(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD0_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD0_MASK)
+#define CLKCTL0_SYSPLL0PFD_PFD0_CLKRDY_MASK (0x40U)
+#define CLKCTL0_SYSPLL0PFD_PFD0_CLKRDY_SHIFT (6U)
+/*! PFD0_CLKRDY - PFD0 Clock Ready Status Flag
+ * 0b0..PFD0 clock is not ready
+ * 0b1..PFD0 clock is ready
+ */
+#define CLKCTL0_SYSPLL0PFD_PFD0_CLKRDY(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD0_CLKRDY_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD0_CLKRDY_MASK)
+#define CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_MASK (0x80U)
+#define CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_SHIFT (7U)
+/*! PFD0_CLKGATE - PFD0 Clock Gate
+ * 0b0..PFD0 clock is not gated
+ * 0b1..PFD0 clock is gated
+ */
+#define CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_MASK)
+#define CLKCTL0_SYSPLL0PFD_PFD1_MASK (0x3F00U)
+#define CLKCTL0_SYSPLL0PFD_PFD1_SHIFT (8U)
+/*! PFD1 - PLL Fractional Divider 1
+ */
+#define CLKCTL0_SYSPLL0PFD_PFD1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD1_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD1_MASK)
+#define CLKCTL0_SYSPLL0PFD_PFD1_CLKRDY_MASK (0x4000U)
+#define CLKCTL0_SYSPLL0PFD_PFD1_CLKRDY_SHIFT (14U)
+/*! PFD1_CLKRDY - PFD1 Clock Ready Status Flag
+ * 0b0..PFD1 clock is not ready
+ * 0b1..PFD1 clock is ready
+ */
+#define CLKCTL0_SYSPLL0PFD_PFD1_CLKRDY(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD1_CLKRDY_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD1_CLKRDY_MASK)
+#define CLKCTL0_SYSPLL0PFD_PFD1_CLKGATE_MASK (0x8000U)
+#define CLKCTL0_SYSPLL0PFD_PFD1_CLKGATE_SHIFT (15U)
+/*! PFD1_CLKGATE - PFD1 Clock Gate
+ * 0b0..PFD1 clock is not gated
+ * 0b1..PFD1 clock is gated
+ */
+#define CLKCTL0_SYSPLL0PFD_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD1_CLKGATE_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD1_CLKGATE_MASK)
+#define CLKCTL0_SYSPLL0PFD_PFD2_MASK (0x3F0000U)
+#define CLKCTL0_SYSPLL0PFD_PFD2_SHIFT (16U)
+/*! PFD2 - PLL Fractional Divider 2
+ */
+#define CLKCTL0_SYSPLL0PFD_PFD2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD2_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD2_MASK)
+#define CLKCTL0_SYSPLL0PFD_PFD2_CLKRDY_MASK (0x400000U)
+#define CLKCTL0_SYSPLL0PFD_PFD2_CLKRDY_SHIFT (22U)
+/*! PFD2_CLKRDY - PFD2 Clock Ready Status Flag
+ * 0b0..PFD2 clock is not ready
+ * 0b1..PFD2 clock is ready
+ */
+#define CLKCTL0_SYSPLL0PFD_PFD2_CLKRDY(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD2_CLKRDY_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD2_CLKRDY_MASK)
+#define CLKCTL0_SYSPLL0PFD_PFD2_CLKGATE_MASK (0x800000U)
+#define CLKCTL0_SYSPLL0PFD_PFD2_CLKGATE_SHIFT (23U)
+/*! PFD2_CLKGATE - PFD2 Clock Gate
+ * 0b0..PFD2 clock is not gated
+ * 0b1..PFD2 clock is gated
+ */
+#define CLKCTL0_SYSPLL0PFD_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD2_CLKGATE_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD2_CLKGATE_MASK)
+#define CLKCTL0_SYSPLL0PFD_PFD3_MASK (0x3F000000U)
+#define CLKCTL0_SYSPLL0PFD_PFD3_SHIFT (24U)
+/*! PFD3 - PLL Fractional Divider 3
+ */
+#define CLKCTL0_SYSPLL0PFD_PFD3(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD3_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD3_MASK)
+#define CLKCTL0_SYSPLL0PFD_PFD3_CLKRDY_MASK (0x40000000U)
+#define CLKCTL0_SYSPLL0PFD_PFD3_CLKRDY_SHIFT (30U)
+/*! PFD3_CLKRDY - PFD3 Clock Ready Status Flag
+ * 0b0..PFD3 clock is not ready
+ * 0b1..PFD3 clock is ready
+ */
+#define CLKCTL0_SYSPLL0PFD_PFD3_CLKRDY(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD3_CLKRDY_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD3_CLKRDY_MASK)
+#define CLKCTL0_SYSPLL0PFD_PFD3_CLKGATE_MASK (0x80000000U)
+#define CLKCTL0_SYSPLL0PFD_PFD3_CLKGATE_SHIFT (31U)
+/*! PFD3_CLKGATE - PFD3 Clock Gate
+ * 0b0..PFD3 clock is not gated
+ * 0b1..PFD3 clock is gated
+ */
+#define CLKCTL0_SYSPLL0PFD_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD3_CLKGATE_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD3_CLKGATE_MASK)
+/*! @} */
+
+/*! @name MAINPLLCLKDIV - Main PLL Clock Divider */
+/*! @{ */
+#define CLKCTL0_MAINPLLCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_MAINPLLCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Low Frequency Clock Divider Value
+ */
+#define CLKCTL0_MAINPLLCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINPLLCLKDIV_DIV_SHIFT)) & CLKCTL0_MAINPLLCLKDIV_DIV_MASK)
+#define CLKCTL0_MAINPLLCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_MAINPLLCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter
+ */
+#define CLKCTL0_MAINPLLCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINPLLCLKDIV_RESET_SHIFT)) & CLKCTL0_MAINPLLCLKDIV_RESET_MASK)
+#define CLKCTL0_MAINPLLCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_MAINPLLCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter
+ */
+#define CLKCTL0_MAINPLLCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINPLLCLKDIV_HALT_SHIFT)) & CLKCTL0_MAINPLLCLKDIV_HALT_MASK)
+#define CLKCTL0_MAINPLLCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_MAINPLLCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ */
+#define CLKCTL0_MAINPLLCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINPLLCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_MAINPLLCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name DSPPLLCLKDIV - DSP PLL Clock Divider */
+/*! @{ */
+#define CLKCTL0_DSPPLLCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_DSPPLLCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Low Frequency Clock Divider Value
+ */
+#define CLKCTL0_DSPPLLCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DSPPLLCLKDIV_DIV_SHIFT)) & CLKCTL0_DSPPLLCLKDIV_DIV_MASK)
+#define CLKCTL0_DSPPLLCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_DSPPLLCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter
+ */
+#define CLKCTL0_DSPPLLCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DSPPLLCLKDIV_RESET_SHIFT)) & CLKCTL0_DSPPLLCLKDIV_RESET_MASK)
+#define CLKCTL0_DSPPLLCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_DSPPLLCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter
+ */
+#define CLKCTL0_DSPPLLCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DSPPLLCLKDIV_HALT_SHIFT)) & CLKCTL0_DSPPLLCLKDIV_HALT_MASK)
+#define CLKCTL0_DSPPLLCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_DSPPLLCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ */
+#define CLKCTL0_DSPPLLCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DSPPLLCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_DSPPLLCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name AUX0PLLCLKDIV - AUX0 PLL Clock Divider */
+/*! @{ */
+#define CLKCTL0_AUX0PLLCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_AUX0PLLCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Low Frequency Clock Divider Value
+ */
+#define CLKCTL0_AUX0PLLCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX0PLLCLKDIV_DIV_SHIFT)) & CLKCTL0_AUX0PLLCLKDIV_DIV_MASK)
+#define CLKCTL0_AUX0PLLCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_AUX0PLLCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter
+ */
+#define CLKCTL0_AUX0PLLCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX0PLLCLKDIV_RESET_SHIFT)) & CLKCTL0_AUX0PLLCLKDIV_RESET_MASK)
+#define CLKCTL0_AUX0PLLCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_AUX0PLLCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter
+ */
+#define CLKCTL0_AUX0PLLCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX0PLLCLKDIV_HALT_SHIFT)) & CLKCTL0_AUX0PLLCLKDIV_HALT_MASK)
+#define CLKCTL0_AUX0PLLCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_AUX0PLLCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ */
+#define CLKCTL0_AUX0PLLCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX0PLLCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_AUX0PLLCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name AUX1PLLCLKDIV - AUX1 PLL Clock Divider */
+/*! @{ */
+#define CLKCTL0_AUX1PLLCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_AUX1PLLCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Low Frequency Clock Divider Value
+ */
+#define CLKCTL0_AUX1PLLCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX1PLLCLKDIV_DIV_SHIFT)) & CLKCTL0_AUX1PLLCLKDIV_DIV_MASK)
+#define CLKCTL0_AUX1PLLCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_AUX1PLLCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter
+ */
+#define CLKCTL0_AUX1PLLCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX1PLLCLKDIV_RESET_SHIFT)) & CLKCTL0_AUX1PLLCLKDIV_RESET_MASK)
+#define CLKCTL0_AUX1PLLCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_AUX1PLLCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter
+ */
+#define CLKCTL0_AUX1PLLCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX1PLLCLKDIV_HALT_SHIFT)) & CLKCTL0_AUX1PLLCLKDIV_HALT_MASK)
+#define CLKCTL0_AUX1PLLCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_AUX1PLLCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ */
+#define CLKCTL0_AUX1PLLCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_AUX1PLLCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_AUX1PLLCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SYSCPUAHBCLKDIV - System CPU AHB Clock Divider */
+/*! @{ */
+#define CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_SYSCPUAHBCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_SYSCPUAHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSCPUAHBCLKDIV_DIV_SHIFT)) & CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK)
+#define CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name MAINCLKSELA - Main Clock Select A */
+/*! @{ */
+#define CLKCTL0_MAINCLKSELA_SEL_MASK (0x3U)
+#define CLKCTL0_MAINCLKSELA_SEL_SHIFT (0U)
+/*! SEL - Control Main 1st Stage Control Clock Source
+ * 0b00..Low Power Oscillator Clock (LPOSC)
+ * 0b01..FRODIV which is the output of the FRODIVSEL mux
+ * 0b10..OSC_CLK clock
+ * 0b11..FRO_DIV1 clock
+ */
+#define CLKCTL0_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINCLKSELA_SEL_SHIFT)) & CLKCTL0_MAINCLKSELA_SEL_MASK)
+/*! @} */
+
+/*! @name MAINCLKSELB - Main Clock Select B */
+/*! @{ */
+#define CLKCTL0_MAINCLKSELB_SEL_MASK (0x3U)
+#define CLKCTL0_MAINCLKSELB_SEL_SHIFT (0U)
+/*! SEL - Main Clock Source Selection
+ * 0b00..MAINCLKSELA 1st Stage Clock
+ * 0b01..Main System PLL Clock
+ * 0b10..RTC 32 KHz Clock
+ * 0b11..Reserved
+ */
+#define CLKCTL0_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINCLKSELB_SEL_SHIFT)) & CLKCTL0_MAINCLKSELB_SEL_MASK)
+/*! @} */
+
+/*! @name PFCDIV - PFC divider 0 (trace clock)..PFC divider 1 (USB HS PHY bus clock) */
+/*! @{ */
+#define CLKCTL0_PFCDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_PFCDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_PFCDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PFCDIV_DIV_SHIFT)) & CLKCTL0_PFCDIV_DIV_MASK)
+#define CLKCTL0_PFCDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_PFCDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_PFCDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PFCDIV_RESET_SHIFT)) & CLKCTL0_PFCDIV_RESET_MASK)
+#define CLKCTL0_PFCDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_PFCDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_PFCDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PFCDIV_HALT_SHIFT)) & CLKCTL0_PFCDIV_HALT_MASK)
+#define CLKCTL0_PFCDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_PFCDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_PFCDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PFCDIV_REQFLAG_SHIFT)) & CLKCTL0_PFCDIV_REQFLAG_MASK)
+/*! @} */
+
+/* The count of CLKCTL0_PFCDIV */
+#define CLKCTL0_PFCDIV_COUNT (2U)
+
+/*! @name FLEXSPI0FCLKSEL - FlexSPI0 Functional Clock Select */
+/*! @{ */
+#define CLKCTL0_FLEXSPI0FCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL0_FLEXSPI0FCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..Main Clock
+ * 0b001..Main System PLL Clock
+ * 0b010..SYSPLL0 AUX0_PLL_Clock
+ * 0b011..FRO_DIV1 Clock
+ * 0b100..SYSPLL0 AUX1_PLL_Clock
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_FLEXSPI0FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI0FCLKSEL_SEL_SHIFT)) & CLKCTL0_FLEXSPI0FCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name FLEXSPI0FCLKDIV - FlexSPI0 Functional Clock Divider */
+/*! @{ */
+#define CLKCTL0_FLEXSPI0FCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_FLEXSPI0FCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_FLEXSPI0FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI0FCLKDIV_DIV_SHIFT)) & CLKCTL0_FLEXSPI0FCLKDIV_DIV_MASK)
+#define CLKCTL0_FLEXSPI0FCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_FLEXSPI0FCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_FLEXSPI0FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI0FCLKDIV_RESET_SHIFT)) & CLKCTL0_FLEXSPI0FCLKDIV_RESET_MASK)
+#define CLKCTL0_FLEXSPI0FCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_FLEXSPI0FCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_FLEXSPI0FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI0FCLKDIV_HALT_SHIFT)) & CLKCTL0_FLEXSPI0FCLKDIV_HALT_MASK)
+#define CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name FLEXSPI1FCLKSEL - FlexSPI1 Functional Clock Select */
+/*! @{ */
+#define CLKCTL0_FLEXSPI1FCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL0_FLEXSPI1FCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..Main Clock
+ * 0b001..Main System PLL Clock
+ * 0b010..SYSPLL0 AUX0_PLL_Clock
+ * 0b011..FRO_DIV1 Clock
+ * 0b100..SYSPLL0 AUX1_PLL_Clock
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_FLEXSPI1FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI1FCLKSEL_SEL_SHIFT)) & CLKCTL0_FLEXSPI1FCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name FLEXSPI1FCLKDIV - FlexSPI1 Functional Clock Divider */
+/*! @{ */
+#define CLKCTL0_FLEXSPI1FCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_FLEXSPI1FCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_FLEXSPI1FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI1FCLKDIV_DIV_SHIFT)) & CLKCTL0_FLEXSPI1FCLKDIV_DIV_MASK)
+#define CLKCTL0_FLEXSPI1FCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_FLEXSPI1FCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_FLEXSPI1FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI1FCLKDIV_RESET_SHIFT)) & CLKCTL0_FLEXSPI1FCLKDIV_RESET_MASK)
+#define CLKCTL0_FLEXSPI1FCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_FLEXSPI1FCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_FLEXSPI1FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI1FCLKDIV_HALT_SHIFT)) & CLKCTL0_FLEXSPI1FCLKDIV_HALT_MASK)
+#define CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SCTFCLKSEL - SCT Functional Clock Select */
+/*! @{ */
+#define CLKCTL0_SCTFCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL0_SCTFCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..Main Clock
+ * 0b001..Main System PLL Clock
+ * 0b010..SYSPLL0 AUX0_PLL_Clock
+ * 0b011..FRO_DIV1 Clock
+ * 0b100..SYSPLL0 AUX1_PLL_Clock
+ * 0b101..AUDIO PLL Clock
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_SCTFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTFCLKSEL_SEL_SHIFT)) & CLKCTL0_SCTFCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SCTIN7CLKDIV - SCT Functional Clock Divider */
+/*! @{ */
+#define CLKCTL0_SCTIN7CLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_SCTIN7CLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_SCTIN7CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTIN7CLKDIV_DIV_SHIFT)) & CLKCTL0_SCTIN7CLKDIV_DIV_MASK)
+#define CLKCTL0_SCTIN7CLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_SCTIN7CLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_SCTIN7CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTIN7CLKDIV_RESET_SHIFT)) & CLKCTL0_SCTIN7CLKDIV_RESET_MASK)
+#define CLKCTL0_SCTIN7CLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_SCTIN7CLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_SCTIN7CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTIN7CLKDIV_HALT_SHIFT)) & CLKCTL0_SCTIN7CLKDIV_HALT_MASK)
+#define CLKCTL0_SCTIN7CLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_SCTIN7CLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_SCTIN7CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTIN7CLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SCTIN7CLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name USBHSFCLKSEL - High Speed USB Functional Clock Select */
+/*! @{ */
+#define CLKCTL0_USBHSFCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL0_USBHSFCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..OSC_CLK Clock
+ * 0b001..Main Clock
+ * 0b010..Reserved
+ * 0b011..AUX0_PLL_CLOCK
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_USBHSFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_USBHSFCLKSEL_SEL_SHIFT)) & CLKCTL0_USBHSFCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name USBHSFCLKDIV - High Speed USB Functional Clock Divider */
+/*! @{ */
+#define CLKCTL0_USBHSFCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_USBHSFCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_USBHSFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_USBHSFCLKDIV_DIV_SHIFT)) & CLKCTL0_USBHSFCLKDIV_DIV_MASK)
+#define CLKCTL0_USBHSFCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_USBHSFCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_USBHSFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_USBHSFCLKDIV_RESET_SHIFT)) & CLKCTL0_USBHSFCLKDIV_RESET_MASK)
+#define CLKCTL0_USBHSFCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_USBHSFCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_USBHSFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_USBHSFCLKDIV_HALT_SHIFT)) & CLKCTL0_USBHSFCLKDIV_HALT_MASK)
+#define CLKCTL0_USBHSFCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_USBHSFCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_USBHSFCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_USBHSFCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_USBHSFCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SDIO0FCLKSEL - SDIO0 Functional Clock Select */
+/*! @{ */
+#define CLKCTL0_SDIO0FCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL0_SDIO0FCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..Main Clock
+ * 0b001..System PLL Clock
+ * 0b010..SYSPLL0 AUX0_PLL_Clock
+ * 0b011..FRO_DIV2
+ * 0b100..SYSPLL0 AUX1_PLL_Clock
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_SDIO0FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO0FCLKSEL_SEL_SHIFT)) & CLKCTL0_SDIO0FCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SDIO0FCLKDIV - SDIO0 Functional Clock Divider */
+/*! @{ */
+#define CLKCTL0_SDIO0FCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_SDIO0FCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_SDIO0FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO0FCLKDIV_DIV_SHIFT)) & CLKCTL0_SDIO0FCLKDIV_DIV_MASK)
+#define CLKCTL0_SDIO0FCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_SDIO0FCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_SDIO0FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO0FCLKDIV_RESET_SHIFT)) & CLKCTL0_SDIO0FCLKDIV_RESET_MASK)
+#define CLKCTL0_SDIO0FCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_SDIO0FCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_SDIO0FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO0FCLKDIV_HALT_SHIFT)) & CLKCTL0_SDIO0FCLKDIV_HALT_MASK)
+#define CLKCTL0_SDIO0FCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_SDIO0FCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_SDIO0FCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO0FCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SDIO0FCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SDIO1FCLKSEL - SDIO1 Functional Clock Select */
+/*! @{ */
+#define CLKCTL0_SDIO1FCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL0_SDIO1FCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..Main Clock
+ * 0b001..Main System PLL Clock
+ * 0b010..SYSPLL0 AUX0_PLL_Clock
+ * 0b011..FRO_DIV2
+ * 0b100..SYSPLL0 AUX1_PLL_Clock
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_SDIO1FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO1FCLKSEL_SEL_SHIFT)) & CLKCTL0_SDIO1FCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SDIO1FCLKDIV - SDIO1 Functional Clock Divider */
+/*! @{ */
+#define CLKCTL0_SDIO1FCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_SDIO1FCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_SDIO1FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO1FCLKDIV_DIV_SHIFT)) & CLKCTL0_SDIO1FCLKDIV_DIV_MASK)
+#define CLKCTL0_SDIO1FCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_SDIO1FCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_SDIO1FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO1FCLKDIV_RESET_SHIFT)) & CLKCTL0_SDIO1FCLKDIV_RESET_MASK)
+#define CLKCTL0_SDIO1FCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_SDIO1FCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_SDIO1FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO1FCLKDIV_HALT_SHIFT)) & CLKCTL0_SDIO1FCLKDIV_HALT_MASK)
+#define CLKCTL0_SDIO1FCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_SDIO1FCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_SDIO1FCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO1FCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SDIO1FCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name ADC0FCLKSEL0 - ADC0 Functional Clock Select 0 */
+/*! @{ */
+#define CLKCTL0_ADC0FCLKSEL0_SEL_MASK (0x7U)
+#define CLKCTL0_ADC0FCLKSEL0_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..OSC_CLK Clock
+ * 0b001..Low Power Oscillator Clock (LPOSC)
+ * 0b010..FRO_DIV4
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_ADC0FCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKSEL0_SEL_SHIFT)) & CLKCTL0_ADC0FCLKSEL0_SEL_MASK)
+/*! @} */
+
+/*! @name ADC0FCLKSEL1 - ADC0 Functional Clock Select 1 */
+/*! @{ */
+#define CLKCTL0_ADC0FCLKSEL1_SEL_MASK (0x7U)
+#define CLKCTL0_ADC0FCLKSEL1_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..ADC0FCLKSEL0 Multiplexed Output
+ * 0b001..SYSPLL0 MAIN_CLK (PFD0 Output)
+ * 0b010..SYSPLL0 AUX0_PLL_Clock
+ * 0b011..SYSPLL0 AUX1_PLL_Clock
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_ADC0FCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKSEL1_SEL_SHIFT)) & CLKCTL0_ADC0FCLKSEL1_SEL_MASK)
+/*! @} */
+
+/*! @name ADC0FCLKDIV - ADC0 Functional Clock Divider */
+/*! @{ */
+#define CLKCTL0_ADC0FCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_ADC0FCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_ADC0FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKDIV_DIV_SHIFT)) & CLKCTL0_ADC0FCLKDIV_DIV_MASK)
+#define CLKCTL0_ADC0FCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_ADC0FCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_ADC0FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKDIV_RESET_SHIFT)) & CLKCTL0_ADC0FCLKDIV_RESET_MASK)
+#define CLKCTL0_ADC0FCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_ADC0FCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_ADC0FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKDIV_HALT_SHIFT)) & CLKCTL0_ADC0FCLKDIV_HALT_MASK)
+#define CLKCTL0_ADC0FCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_ADC0FCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_ADC0FCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_ADC0FCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name UTICKFCLKSEL - UTICK Functional Clock Select */
+/*! @{ */
+#define CLKCTL0_UTICKFCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL0_UTICKFCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..Low Power Oscillator Clock (LPOSC)
+ * 0b001..Reserved
+ * 0b010..Reserved
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_UTICKFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_UTICKFCLKSEL_SEL_SHIFT)) & CLKCTL0_UTICKFCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name WDT0FCLKSEL - WDT0 Functional Clock Select */
+/*! @{ */
+#define CLKCTL0_WDT0FCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL0_WDT0FCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..Low Power Oscillator Clock (LPOSC)
+ * 0b001..Reserved
+ * 0b010..Reserved
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_WDT0FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_WDT0FCLKSEL_SEL_SHIFT)) & CLKCTL0_WDT0FCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name A32KHZWAKECLKSEL - 32 KHz Wake Clock Source Select */
+/*! @{ */
+#define CLKCTL0_A32KHZWAKECLKSEL_SEL_MASK (0x7U)
+#define CLKCTL0_A32KHZWAKECLKSEL_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..32 KHz
+ * 0b001..Low Power Oscillator Clock (LPOSC); divided by 32 by default
+ * 0b010..Reserved
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_A32KHZWAKECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_A32KHZWAKECLKSEL_SEL_SHIFT)) & CLKCTL0_A32KHZWAKECLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name A32KHZWAKECLKDIV - 32 KHz Wake Clock Divider */
+/*! @{ */
+#define CLKCTL0_A32KHZWAKECLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_A32KHZWAKECLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_A32KHZWAKECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_A32KHZWAKECLKDIV_DIV_SHIFT)) & CLKCTL0_A32KHZWAKECLKDIV_DIV_MASK)
+#define CLKCTL0_A32KHZWAKECLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_A32KHZWAKECLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_A32KHZWAKECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_A32KHZWAKECLKDIV_RESET_SHIFT)) & CLKCTL0_A32KHZWAKECLKDIV_RESET_MASK)
+#define CLKCTL0_A32KHZWAKECLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_A32KHZWAKECLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_A32KHZWAKECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_A32KHZWAKECLKDIV_HALT_SHIFT)) & CLKCTL0_A32KHZWAKECLKDIV_HALT_MASK)
+#define CLKCTL0_A32KHZWAKECLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_A32KHZWAKECLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_A32KHZWAKECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_A32KHZWAKECLKDIV_REQFLAG_SHIFT)) & CLKCTL0_A32KHZWAKECLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name SYSTICKFCLKSEL - SYSTICK Functional Clock Select */
+/*! @{ */
+#define CLKCTL0_SYSTICKFCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL0_SYSTICKFCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..Systick Divider Output Clock
+ * 0b001..Low Power Oscillator Clock (LPOSC)
+ * 0b010..32 KHz RTC Clock
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_SYSTICKFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKSEL_SEL_SHIFT)) & CLKCTL0_SYSTICKFCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SYSTICKFCLKDIV - SYSTICK Functional Clock Divider */
+/*! @{ */
+#define CLKCTL0_SYSTICKFCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_SYSTICKFCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_SYSTICKFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_DIV_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_DIV_MASK)
+#define CLKCTL0_SYSTICKFCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_SYSTICKFCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_SYSTICKFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_RESET_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_RESET_MASK)
+#define CLKCTL0_SYSTICKFCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_SYSTICKFCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_SYSTICKFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_HALT_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_HALT_MASK)
+#define CLKCTL0_SYSTICKFCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_SYSTICKFCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_SYSTICKFCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name DPHYCLKSEL - MIPI-DSI PHY Clock Select */
+/*! @{ */
+#define CLKCTL0_DPHYCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL0_DPHYCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..FRO_DIV1 Clock
+ * 0b001..SYSPLL0 MAIN_CLK (PFD0 Output)
+ * 0b010..SYSPLL0 AUX0_PLL_Clock
+ * 0b011..SYSPLL0 AUX1_PLL_Clock
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_DPHYCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYCLKSEL_SEL_SHIFT)) & CLKCTL0_DPHYCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name DPHYCLKDIV - MIPI-DSI PHY Clock Divider */
+/*! @{ */
+#define CLKCTL0_DPHYCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_DPHYCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_DPHYCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYCLKDIV_DIV_SHIFT)) & CLKCTL0_DPHYCLKDIV_DIV_MASK)
+#define CLKCTL0_DPHYCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_DPHYCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_DPHYCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYCLKDIV_RESET_SHIFT)) & CLKCTL0_DPHYCLKDIV_RESET_MASK)
+#define CLKCTL0_DPHYCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_DPHYCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_DPHYCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYCLKDIV_HALT_SHIFT)) & CLKCTL0_DPHYCLKDIV_HALT_MASK)
+#define CLKCTL0_DPHYCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_DPHYCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_DPHYCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_DPHYCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name DPHYESCCLKSEL - MIPI-DSI DPHY Escape Mode Clock Select */
+/*! @{ */
+#define CLKCTL0_DPHYESCCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL0_DPHYESCCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..FRO_DIV1 clock
+ * 0b001..FRO_DIV16 Clock
+ * 0b010..AUX0_PLL_CLK
+ * 0b011..AUX1_PLL_CLK
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_DPHYESCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCCLKSEL_SEL_SHIFT)) & CLKCTL0_DPHYESCCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name DPHYESCRXCLKDIV - MIPI-DSI DPHY Escape Mode Receive Clock Divider */
+/*! @{ */
+#define CLKCTL0_DPHYESCRXCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_DPHYESCRXCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_DPHYESCRXCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCRXCLKDIV_DIV_SHIFT)) & CLKCTL0_DPHYESCRXCLKDIV_DIV_MASK)
+#define CLKCTL0_DPHYESCRXCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_DPHYESCRXCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_DPHYESCRXCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCRXCLKDIV_RESET_SHIFT)) & CLKCTL0_DPHYESCRXCLKDIV_RESET_MASK)
+#define CLKCTL0_DPHYESCRXCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_DPHYESCRXCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_DPHYESCRXCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCRXCLKDIV_HALT_SHIFT)) & CLKCTL0_DPHYESCRXCLKDIV_HALT_MASK)
+#define CLKCTL0_DPHYESCRXCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_DPHYESCRXCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_DPHYESCRXCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCRXCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_DPHYESCRXCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name DPHYESCTXCLKDIV - MIPI-DSI DPHY Escape Mode Tramsmit Clock Divider */
+/*! @{ */
+#define CLKCTL0_DPHYESCTXCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_DPHYESCTXCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_DPHYESCTXCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCTXCLKDIV_DIV_SHIFT)) & CLKCTL0_DPHYESCTXCLKDIV_DIV_MASK)
+#define CLKCTL0_DPHYESCTXCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_DPHYESCTXCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_DPHYESCTXCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCTXCLKDIV_RESET_SHIFT)) & CLKCTL0_DPHYESCTXCLKDIV_RESET_MASK)
+#define CLKCTL0_DPHYESCTXCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_DPHYESCTXCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_DPHYESCTXCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCTXCLKDIV_HALT_SHIFT)) & CLKCTL0_DPHYESCTXCLKDIV_HALT_MASK)
+#define CLKCTL0_DPHYESCTXCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_DPHYESCTXCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_DPHYESCTXCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCTXCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_DPHYESCTXCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name GPUCLKSEL - GPU Clock Select */
+/*! @{ */
+#define CLKCTL0_GPUCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL0_GPUCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..Main Clock
+ * 0b001..FRO_DIV1 clock
+ * 0b010..SYSPLL0 MAIN_CLK (PFD0 Output)
+ * 0b011..SYSPLL0 AUX0_PLL_Clock
+ * 0b100..SYSPLL0 AUX1_PLL_Clock
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_GPUCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_GPUCLKSEL_SEL_SHIFT)) & CLKCTL0_GPUCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name GPUCLKDIV - GPU Clock Divider */
+/*! @{ */
+#define CLKCTL0_GPUCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_GPUCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_GPUCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_GPUCLKDIV_DIV_SHIFT)) & CLKCTL0_GPUCLKDIV_DIV_MASK)
+#define CLKCTL0_GPUCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_GPUCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_GPUCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_GPUCLKDIV_RESET_SHIFT)) & CLKCTL0_GPUCLKDIV_RESET_MASK)
+#define CLKCTL0_GPUCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_GPUCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_GPUCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_GPUCLKDIV_HALT_SHIFT)) & CLKCTL0_GPUCLKDIV_HALT_MASK)
+#define CLKCTL0_GPUCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_GPUCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_GPUCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_GPUCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_GPUCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name DCPIXELCLKSEL - LCDIF Pixel Clock Select */
+/*! @{ */
+#define CLKCTL0_DCPIXELCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL0_DCPIXELCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Select Clock Source
+ * 0b000..MIPI-DSI PHY Clock
+ * 0b001..Main Clock
+ * 0b010..FRO_DIV1 Clock
+ * 0b011..SYSPLL0 MAIN_CLK (PFD0 Output)
+ * 0b100..SYSPLL0 AUX0_PLL_Clock
+ * 0b101..SYSPLL0 AUX1_PLL_Clock
+ * 0b110..Reserved
+ * 0b111..None; this may be selected to reduce power when no output is needed.
+ */
+#define CLKCTL0_DCPIXELCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DCPIXELCLKSEL_SEL_SHIFT)) & CLKCTL0_DCPIXELCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name DCPIXELCLKDIV - LCDIF Pixel Clock Divider */
+/*! @{ */
+#define CLKCTL0_DCPIXELCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL0_DCPIXELCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Divider Value Selection
+ */
+#define CLKCTL0_DCPIXELCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DCPIXELCLKDIV_DIV_SHIFT)) & CLKCTL0_DCPIXELCLKDIV_DIV_MASK)
+#define CLKCTL0_DCPIXELCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL0_DCPIXELCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL0_DCPIXELCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DCPIXELCLKDIV_RESET_SHIFT)) & CLKCTL0_DCPIXELCLKDIV_RESET_MASK)
+#define CLKCTL0_DCPIXELCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL0_DCPIXELCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL0_DCPIXELCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DCPIXELCLKDIV_HALT_SHIFT)) & CLKCTL0_DCPIXELCLKDIV_HALT_MASK)
+#define CLKCTL0_DCPIXELCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL0_DCPIXELCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag
+ * 0b0..The change to the divider value has finished
+ * 0b1..A change is being made to the divider value
+ */
+#define CLKCTL0_DCPIXELCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DCPIXELCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_DCPIXELCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CLKCTL0_Register_Masks */
+
+
+/* CLKCTL0 - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral CLKCTL0 base address */
+ #define CLKCTL0_BASE (0x50001000u)
+ /** Peripheral CLKCTL0 base address */
+ #define CLKCTL0_BASE_NS (0x40001000u)
+ /** Peripheral CLKCTL0 base pointer */
+ #define CLKCTL0 ((CLKCTL0_Type *)CLKCTL0_BASE)
+ /** Peripheral CLKCTL0 base pointer */
+ #define CLKCTL0_NS ((CLKCTL0_Type *)CLKCTL0_BASE_NS)
+ /** Array initializer of CLKCTL0 peripheral base addresses */
+ #define CLKCTL0_BASE_ADDRS { CLKCTL0_BASE }
+ /** Array initializer of CLKCTL0 peripheral base pointers */
+ #define CLKCTL0_BASE_PTRS { CLKCTL0 }
+ /** Array initializer of CLKCTL0 peripheral base addresses */
+ #define CLKCTL0_BASE_ADDRS_NS { CLKCTL0_BASE_NS }
+ /** Array initializer of CLKCTL0 peripheral base pointers */
+ #define CLKCTL0_BASE_PTRS_NS { CLKCTL0_NS }
+#else
+ /** Peripheral CLKCTL0 base address */
+ #define CLKCTL0_BASE (0x40001000u)
+ /** Peripheral CLKCTL0 base pointer */
+ #define CLKCTL0 ((CLKCTL0_Type *)CLKCTL0_BASE)
+ /** Array initializer of CLKCTL0 peripheral base addresses */
+ #define CLKCTL0_BASE_ADDRS { CLKCTL0_BASE }
+ /** Array initializer of CLKCTL0 peripheral base pointers */
+ #define CLKCTL0_BASE_PTRS { CLKCTL0 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group CLKCTL0_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CLKCTL1 Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CLKCTL1_Peripheral_Access_Layer CLKCTL1 Peripheral Access Layer
+ * @{
+ */
+
+/** CLKCTL1 - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[16];
+ __IO uint32_t PSCCTL0; /**< Clock Control 0, offset: 0x10 */
+ __IO uint32_t PSCCTL1; /**< Clock Control 1, offset: 0x14 */
+ __IO uint32_t PSCCTL2; /**< Clock Control 2, offset: 0x18 */
+ uint8_t RESERVED_1[36];
+ __IO uint32_t PSCCTL0_SET; /**< Clock Set 0, offset: 0x40 */
+ __IO uint32_t PSCCTL1_SET; /**< Clock Set 1, offset: 0x44 */
+ __IO uint32_t PSCCTL2_SET; /**< Clock Set 2, offset: 0x48 */
+ uint8_t RESERVED_2[36];
+ __IO uint32_t PSCCTL0_CLR; /**< Clock Clear 0, offset: 0x70 */
+ __IO uint32_t PSCCTL1_CLR; /**< Clock Clear 1, offset: 0x74 */
+ __IO uint32_t PSCCTL2_CLR; /**< Clock Clear 2, offset: 0x78 */
+ uint8_t RESERVED_3[388];
+ __IO uint32_t AUDIOPLL0CLKSEL; /**< Audio PLL0 Clock Select, offset: 0x200 */
+ __IO uint32_t AUDIOPLL0CTL0; /**< Audio PLL0 Control 0, offset: 0x204 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t AUDIOPLL0LOCKTIMEDIV2; /**< Audio PLL0 Lock Time Divide-by-2, offset: 0x20C */
+ __IO uint32_t AUDIOPLL0NUM; /**< Audio PLL0 Numerator, offset: 0x210 */
+ __IO uint32_t AUDIOPLL0DENOM; /**< Audio PLL0 Denominator, offset: 0x214 */
+ __IO uint32_t AUDIOPLL0PFD; /**< Audio PLL0 PFD, offset: 0x218 */
+ uint8_t RESERVED_5[36];
+ __IO uint32_t AUDIOPLLCLKDIV; /**< Audio PLL Clock Divider, offset: 0x240 */
+ uint8_t RESERVED_6[444];
+ __IO uint32_t DSPCPUCLKDIV; /**< DSP CPU Clock Divider, offset: 0x400 */
+ uint8_t RESERVED_7[44];
+ __IO uint32_t DSPCPUCLKSELA; /**< DSP CPU Clock Select A, offset: 0x430 */
+ __IO uint32_t DSPCPUCLKSELB; /**< DSP CPU Clock Select B, offset: 0x434 */
+ uint8_t RESERVED_8[72];
+ __IO uint32_t OSEVENTTFCLKSEL; /**< OS Event Timer Functional Clock Select, offset: 0x480 */
+ uint8_t RESERVED_9[124];
+ struct { /* offset: 0x500, array step: 0x20 */
+ __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator 0 Clock Select..Fractional Rate Generator 16 Clock Select, array offset: 0x500, array step: 0x20 */
+ __IO uint32_t FRGCTL; /**< Fractional Rate Generator 0 Control..Fractional Rate Generator 16 Control, array offset: 0x504, array step: 0x20 */
+ __IO uint32_t FCFCLKSEL; /**< Flexcomm0 Clock Select..Flexcomm16 Clock Select, array offset: 0x508, array step: 0x20 */
+ uint8_t RESERVED_0[20];
+ } FLEXCOMM[17];
+ __IO uint32_t FRG17CLKSEL; /**< Fractional Rate Generator 17 Clock Select, offset: 0x720 */
+ __IO uint32_t FRG17CTL; /**< Fractional Rate Generator 17 Control, offset: 0x724 */
+ __IO uint32_t FLEXIOCLKSEL; /**< FlexIO Clock Select, offset: 0x728 */
+ uint8_t RESERVED_10[20];
+ __IO uint32_t FLEXIOCLKDIV; /**< FlexIO Clock Divider, offset: 0x740 */
+ uint8_t RESERVED_11[28];
+ __IO uint32_t FRGPLLCLKDIV; /**< Fractional Rate Generator PLL Clock Divider, offset: 0x760 */
+ uint8_t RESERVED_12[28];
+ __IO uint32_t DMIC0FCLKSEL; /**< DMIC0 Functional Clock Select, offset: 0x780 */
+ __IO uint32_t DMIC0FCLKDIV; /**< DMIC0 Functional Clock Divider, offset: 0x784 */
+ uint8_t RESERVED_13[24];
+ __IO uint32_t CT32BITFCLKSEL[5]; /**< CT32BIT bit timer 0 Functional Clock Select..CT32BIT bit timer 4 Functional Clock Select, array offset: 0x7A0, array step: 0x4 */
+ uint8_t RESERVED_14[12];
+ __IO uint32_t AUDIOMCLKSEL; /**< Audio MCLK Clock Select, offset: 0x7C0 */
+ __IO uint32_t AUDIOMCLKDIV; /**< Audio MCLK Clock Divider, offset: 0x7C4 */
+ uint8_t RESERVED_15[24];
+ __IO uint32_t CLKOUTSEL0; /**< CLKOUT Clock Select 0, offset: 0x7E0 */
+ __IO uint32_t CLKOUTSEL1; /**< CLKOUT Clock Select 1, offset: 0x7E4 */
+ __IO uint32_t CLKOUTFCLKDIV; /**< CLKOUT Functional Clock Divider, offset: 0x7E8 */
+ uint8_t RESERVED_16[20];
+ __IO uint32_t I3C01FCLKSEL; /**< I3C0, I3C1 Functional Clock Select, offset: 0x800 */
+ __IO uint32_t I3C01FCLKSTCSEL; /**< I3C0, I3C1 Functional Slow Time Control Clock Select, offset: 0x804 */
+ __IO uint32_t I3C01FCLKSTCDIV; /**< I3C0, I3C1 Functional Slow Time Control Clock Divider, offset: 0x808 */
+ __IO uint32_t I3C01FCLKSDIV; /**< I3C0, I3C1 Functional Slow Clock Divider, offset: 0x80C */
+ __IO uint32_t I3C01FCLKDIV; /**< I3C0, I3C1 Functional Clock Divider, offset: 0x810 */
+ __IO uint32_t I3C01FCLKSTSTCLKSEL; /**< I3C01 Functional Clock Select, offset: 0x814 */
+ uint8_t RESERVED_17[8];
+ __IO uint32_t WDT1FCLKSEL; /**< Watchdog Timer 1 Functional Clock Select, offset: 0x820 */
+ uint8_t RESERVED_18[12];
+ __IO uint32_t ACMP0FCLKSEL; /**< Analog Comparator 0 Clock Select, offset: 0x830 */
+ __IO uint32_t ACMP0FCLKDIV; /**< Analog comparator 0 FCLK divider, offset: 0x834 */
+} CLKCTL1_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CLKCTL1 Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CLKCTL1_Register_Masks CLKCTL1 Register Masks
+ * @{
+ */
+
+/*! @name PSCCTL0 - Clock Control 0 */
+/*! @{ */
+#define CLKCTL1_PSCCTL0_FC0_CLK_MASK (0x100U)
+#define CLKCTL1_PSCCTL0_FC0_CLK_SHIFT (8U)
+/*! FC0_CLK - Flexcomm Interface 0 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC0_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC0_CLK_MASK)
+#define CLKCTL1_PSCCTL0_FC1_CLK_MASK (0x200U)
+#define CLKCTL1_PSCCTL0_FC1_CLK_SHIFT (9U)
+/*! FC1_CLK - Flexcomm Interface 1 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC1_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC1_CLK_MASK)
+#define CLKCTL1_PSCCTL0_FC2_CLK_MASK (0x400U)
+#define CLKCTL1_PSCCTL0_FC2_CLK_SHIFT (10U)
+/*! FC2_CLK - Flexcomm Interface 2 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC2_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC2_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC2_CLK_MASK)
+#define CLKCTL1_PSCCTL0_FC3_CLK_MASK (0x800U)
+#define CLKCTL1_PSCCTL0_FC3_CLK_SHIFT (11U)
+/*! FC3_CLK - Flexcomm Interface 3 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC3_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC3_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC3_CLK_MASK)
+#define CLKCTL1_PSCCTL0_FC4_CLK_MASK (0x1000U)
+#define CLKCTL1_PSCCTL0_FC4_CLK_SHIFT (12U)
+/*! FC4_CLK - Flexcomm Interface 4 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC4_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC4_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC4_CLK_MASK)
+#define CLKCTL1_PSCCTL0_FC5_CLK_MASK (0x2000U)
+#define CLKCTL1_PSCCTL0_FC5_CLK_SHIFT (13U)
+/*! FC5_CLK - Flexcomm Interface 5 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC5_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC5_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC5_CLK_MASK)
+#define CLKCTL1_PSCCTL0_FC6_CLK_MASK (0x4000U)
+#define CLKCTL1_PSCCTL0_FC6_CLK_SHIFT (14U)
+/*! FC6_CLK - Flexcomm Interface 6 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC6_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC6_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC6_CLK_MASK)
+#define CLKCTL1_PSCCTL0_FC7_CLK_MASK (0x8000U)
+#define CLKCTL1_PSCCTL0_FC7_CLK_SHIFT (15U)
+/*! FC7_CLK - Flexcomm Interface 7 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC7_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC7_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC7_CLK_MASK)
+#define CLKCTL1_PSCCTL0_FC8_CLK_MASK (0x10000U)
+#define CLKCTL1_PSCCTL0_FC8_CLK_SHIFT (16U)
+/*! FC8_CLK - Flexcomm Interface 8 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC8_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC8_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC8_CLK_MASK)
+#define CLKCTL1_PSCCTL0_FC9_CLK_MASK (0x20000U)
+#define CLKCTL1_PSCCTL0_FC9_CLK_SHIFT (17U)
+/*! FC9_CLK - Flexcomm Interface 9 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC9_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC9_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC9_CLK_MASK)
+#define CLKCTL1_PSCCTL0_FC10_CLK_MASK (0x40000U)
+#define CLKCTL1_PSCCTL0_FC10_CLK_SHIFT (18U)
+/*! FC10_CLK - Flexcomm Interface 10 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC10_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC10_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC10_CLK_MASK)
+#define CLKCTL1_PSCCTL0_FC11_CLK_MASK (0x80000U)
+#define CLKCTL1_PSCCTL0_FC11_CLK_SHIFT (19U)
+/*! FC11_CLK - Flexcomm Interface 11 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC11_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC11_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC11_CLK_MASK)
+#define CLKCTL1_PSCCTL0_FC12_CLK_MASK (0x100000U)
+#define CLKCTL1_PSCCTL0_FC12_CLK_SHIFT (20U)
+/*! FC12_CLK - Flexcomm Interface 12 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC12_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC12_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC12_CLK_MASK)
+#define CLKCTL1_PSCCTL0_FC13_CLK_MASK (0x200000U)
+#define CLKCTL1_PSCCTL0_FC13_CLK_SHIFT (21U)
+/*! FC13_CLK - Flexcomm Interface 13 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC13_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC13_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC13_CLK_MASK)
+#define CLKCTL1_PSCCTL0_FC14_SPI_CLK_MASK (0x400000U)
+#define CLKCTL1_PSCCTL0_FC14_SPI_CLK_SHIFT (22U)
+/*! FC14_SPI_CLK - Flexcomm Interface 14 SPI clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC14_SPI_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC14_SPI_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC14_SPI_CLK_MASK)
+#define CLKCTL1_PSCCTL0_FC15_I2C_CLK_MASK (0x800000U)
+#define CLKCTL1_PSCCTL0_FC15_I2C_CLK_SHIFT (23U)
+/*! FC15_I2C_CLK - Flexcomm Interface 15 I2C clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC15_I2C_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC15_I2C_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC15_I2C_CLK_MASK)
+#define CLKCTL1_PSCCTL0_DMIC0_MASK (0x1000000U)
+#define CLKCTL1_PSCCTL0_DMIC0_SHIFT (24U)
+/*! DMIC0 - DMIC0 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_DMIC0_SHIFT)) & CLKCTL1_PSCCTL0_DMIC0_MASK)
+#define CLKCTL1_PSCCTL0_FC16_SPI_CLK_MASK (0x2000000U)
+#define CLKCTL1_PSCCTL0_FC16_SPI_CLK_SHIFT (25U)
+/*! FC16_SPI_CLK - Flexcomm Interface 16 SPI clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FC16_SPI_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC16_SPI_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC16_SPI_CLK_MASK)
+#define CLKCTL1_PSCCTL0_OSEVENT_TIMER_MASK (0x8000000U)
+#define CLKCTL1_PSCCTL0_OSEVENT_TIMER_SHIFT (27U)
+/*! OSEVENT_TIMER - OS event timer bus clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_OSEVENT_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_OSEVENT_TIMER_SHIFT)) & CLKCTL1_PSCCTL0_OSEVENT_TIMER_MASK)
+#define CLKCTL1_PSCCTL0_FlexIO_MASK (0x20000000U)
+#define CLKCTL1_PSCCTL0_FlexIO_SHIFT (29U)
+/*! FlexIO - FlexIO clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL0_FlexIO(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FlexIO_SHIFT)) & CLKCTL1_PSCCTL0_FlexIO_MASK)
+/*! @} */
+
+/*! @name PSCCTL1 - Clock Control 1 */
+/*! @{ */
+#define CLKCTL1_PSCCTL1_HSGPIO0_CLK_MASK (0x1U)
+#define CLKCTL1_PSCCTL1_HSGPIO0_CLK_SHIFT (0U)
+/*! HSGPIO0_CLK - Non-secure GPIO0 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL1_HSGPIO0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO0_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO0_CLK_MASK)
+#define CLKCTL1_PSCCTL1_HSGPIO1_CLK_MASK (0x2U)
+#define CLKCTL1_PSCCTL1_HSGPIO1_CLK_SHIFT (1U)
+/*! HSGPIO1_CLK - Non-secure GPIO1 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL1_HSGPIO1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO1_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO1_CLK_MASK)
+#define CLKCTL1_PSCCTL1_HSGPIO2_CLK_MASK (0x4U)
+#define CLKCTL1_PSCCTL1_HSGPIO2_CLK_SHIFT (2U)
+/*! HSGPIO2_CLK - Non-secure GPIO2 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL1_HSGPIO2_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO2_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO2_CLK_MASK)
+#define CLKCTL1_PSCCTL1_HSGPIO3_CLK_MASK (0x8U)
+#define CLKCTL1_PSCCTL1_HSGPIO3_CLK_SHIFT (3U)
+/*! HSGPIO3_CLK - Non-secure GPIO3 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL1_HSGPIO3_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO3_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO3_CLK_MASK)
+#define CLKCTL1_PSCCTL1_HSGPIO4_CLK_MASK (0x10U)
+#define CLKCTL1_PSCCTL1_HSGPIO4_CLK_SHIFT (4U)
+/*! HSGPIO4_CLK - Non-secure GPIO4 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL1_HSGPIO4_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO4_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO4_CLK_MASK)
+#define CLKCTL1_PSCCTL1_HSGPIO5_CLK_MASK (0x20U)
+#define CLKCTL1_PSCCTL1_HSGPIO5_CLK_SHIFT (5U)
+/*! HSGPIO5_CLK - Non-secure GPIO5 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL1_HSGPIO5_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO5_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO5_CLK_MASK)
+#define CLKCTL1_PSCCTL1_HSGPIO6_CLK_MASK (0x40U)
+#define CLKCTL1_PSCCTL1_HSGPIO6_CLK_SHIFT (6U)
+/*! HSGPIO6_CLK - Non-secure GPIO6 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL1_HSGPIO6_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO6_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO6_CLK_MASK)
+#define CLKCTL1_PSCCTL1_HSGPIO7_CLK_MASK (0x80U)
+#define CLKCTL1_PSCCTL1_HSGPIO7_CLK_SHIFT (7U)
+/*! HSGPIO7_CLK - Non-secure GPIO7 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL1_HSGPIO7_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO7_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO7_CLK_MASK)
+#define CLKCTL1_PSCCTL1_CRC_CLK_MASK (0x10000U)
+#define CLKCTL1_PSCCTL1_CRC_CLK_SHIFT (16U)
+/*! CRC_CLK - CRC clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL1_CRC_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CRC_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CRC_CLK_MASK)
+#define CLKCTL1_PSCCTL1_DMAC0_CLK_MASK (0x800000U)
+#define CLKCTL1_PSCCTL1_DMAC0_CLK_SHIFT (23U)
+/*! DMAC0_CLK - DMAC0 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL1_DMAC0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_DMAC0_CLK_SHIFT)) & CLKCTL1_PSCCTL1_DMAC0_CLK_MASK)
+#define CLKCTL1_PSCCTL1_DMAC1_CLK_MASK (0x1000000U)
+#define CLKCTL1_PSCCTL1_DMAC1_CLK_SHIFT (24U)
+/*! DMAC1_CLK - DMAC1 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL1_DMAC1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_DMAC1_CLK_SHIFT)) & CLKCTL1_PSCCTL1_DMAC1_CLK_MASK)
+#define CLKCTL1_PSCCTL1_MU_CLK_MASK (0x10000000U)
+#define CLKCTL1_PSCCTL1_MU_CLK_SHIFT (28U)
+/*! MU_CLK - Messaging Unit clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL1_MU_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_MU_CLK_SHIFT)) & CLKCTL1_PSCCTL1_MU_CLK_MASK)
+#define CLKCTL1_PSCCTL1_SEMA_CLK_MASK (0x20000000U)
+#define CLKCTL1_PSCCTL1_SEMA_CLK_SHIFT (29U)
+/*! SEMA_CLK - Semaphore clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL1_SEMA_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SEMA_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SEMA_CLK_MASK)
+#define CLKCTL1_PSCCTL1_FREQME_CLK_MASK (0x80000000U)
+#define CLKCTL1_PSCCTL1_FREQME_CLK_SHIFT (31U)
+/*! FREQME_CLK - Frequency Measurement clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL1_FREQME_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_FREQME_CLK_SHIFT)) & CLKCTL1_PSCCTL1_FREQME_CLK_MASK)
+/*! @} */
+
+/*! @name PSCCTL2 - Clock Control 2 */
+/*! @{ */
+#define CLKCTL1_PSCCTL2_CT32BIT0_CLK_MASK (0x1U)
+#define CLKCTL1_PSCCTL2_CT32BIT0_CLK_SHIFT (0U)
+/*! CT32BIT0_CLK - CT32BIT bit timer 0 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_CT32BIT0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CT32BIT0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CT32BIT0_CLK_MASK)
+#define CLKCTL1_PSCCTL2_CT32BIT1_CLK_MASK (0x2U)
+#define CLKCTL1_PSCCTL2_CT32BIT1_CLK_SHIFT (1U)
+/*! CT32BIT1_CLK - CT32BIT bit timer 1 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_CT32BIT1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CT32BIT1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CT32BIT1_CLK_MASK)
+#define CLKCTL1_PSCCTL2_CT32BIT2_CLK_MASK (0x4U)
+#define CLKCTL1_PSCCTL2_CT32BIT2_CLK_SHIFT (2U)
+/*! CT32BIT2_CLK - CT32BIT bit timer 2 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_CT32BIT2_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CT32BIT2_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CT32BIT2_CLK_MASK)
+#define CLKCTL1_PSCCTL2_CT32BIT3_CLK_MASK (0x8U)
+#define CLKCTL1_PSCCTL2_CT32BIT3_CLK_SHIFT (3U)
+/*! CT32BIT3_CLK - CT32BIT bit timer 3 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_CT32BIT3_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CT32BIT3_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CT32BIT3_CLK_MASK)
+#define CLKCTL1_PSCCTL2_CT32BIT4_CLK_MASK (0x10U)
+#define CLKCTL1_PSCCTL2_CT32BIT4_CLK_SHIFT (4U)
+/*! CT32BIT4_CLK - CT32BIT bit timer 4 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_CT32BIT4_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CT32BIT4_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CT32BIT4_CLK_MASK)
+#define CLKCTL1_PSCCTL2_RTCLITE_CLK_MASK (0x80U)
+#define CLKCTL1_PSCCTL2_RTCLITE_CLK_SHIFT (7U)
+/*! RTCLITE_CLK - RTC clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_RTCLITE_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_RTCLITE_CLK_SHIFT)) & CLKCTL1_PSCCTL2_RTCLITE_CLK_MASK)
+#define CLKCTL1_PSCCTL2_MRT0_CLK_MASK (0x100U)
+#define CLKCTL1_PSCCTL2_MRT0_CLK_SHIFT (8U)
+/*! MRT0_CLK - Multi-Rate Timer 0 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_MRT0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_MRT0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_MRT0_CLK_MASK)
+#define CLKCTL1_PSCCTL2_WWDT1_CLK_MASK (0x400U)
+#define CLKCTL1_PSCCTL2_WWDT1_CLK_SHIFT (10U)
+/*! WWDT1_CLK - Watchdog Timer 1 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_WWDT1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_WWDT1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_WWDT1_CLK_MASK)
+#define CLKCTL1_PSCCTL2_I3C0_CLK_MASK (0x10000U)
+#define CLKCTL1_PSCCTL2_I3C0_CLK_SHIFT (16U)
+/*! I3C0_CLK - I3C0 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_I3C0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_I3C0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_I3C0_CLK_MASK)
+#define CLKCTL1_PSCCTL2_I3C1_CLK_MASK (0x20000U)
+#define CLKCTL1_PSCCTL2_I3C1_CLK_SHIFT (17U)
+/*! I3C1_CLK - I3C1 clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_I3C1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_I3C1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_I3C1_CLK_MASK)
+#define CLKCTL1_PSCCTL2_GPIOINTCTL_CLK_MASK (0x40000000U)
+#define CLKCTL1_PSCCTL2_GPIOINTCTL_CLK_SHIFT (30U)
+/*! GPIOINTCTL_CLK - PINT clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_GPIOINTCTL_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_GPIOINTCTL_CLK_SHIFT)) & CLKCTL1_PSCCTL2_GPIOINTCTL_CLK_MASK)
+#define CLKCTL1_PSCCTL2_PIMCTL_CLK_MASK (0x80000000U)
+#define CLKCTL1_PSCCTL2_PIMCTL_CLK_SHIFT (31U)
+/*! PIMCTL_CLK - INPUTMUX clock control
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_PIMCTL_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_PIMCTL_CLK_SHIFT)) & CLKCTL1_PSCCTL2_PIMCTL_CLK_MASK)
+/*! @} */
+
+/*! @name PSCCTL0_SET - Clock Set 0 */
+/*! @{ */
+#define CLKCTL1_PSCCTL0_SET_FC0_CLK_MASK (0x100U)
+#define CLKCTL1_PSCCTL0_SET_FC0_CLK_SHIFT (8U)
+/*! FC0_CLK - Flexcomm Interface 0 clock set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC0_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC0_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC1_CLK_MASK (0x200U)
+#define CLKCTL1_PSCCTL0_SET_FC1_CLK_SHIFT (9U)
+/*! FC1_CLK - Flexcomm Interface 1 clock set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC1_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC1_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC2_CLK_MASK (0x400U)
+#define CLKCTL1_PSCCTL0_SET_FC2_CLK_SHIFT (10U)
+/*! FC2_CLK - Flexcomm Interface 2 clock set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC2_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC2_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC2_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC3_CLK_MASK (0x800U)
+#define CLKCTL1_PSCCTL0_SET_FC3_CLK_SHIFT (11U)
+/*! FC3_CLK - Flexcomm Interface 3 clock set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC3_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC3_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC3_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC4_CLK_MASK (0x1000U)
+#define CLKCTL1_PSCCTL0_SET_FC4_CLK_SHIFT (12U)
+/*! FC4_CLK - Flexcomm Interface 4 clock set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC4_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC4_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC4_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC5_CLK_MASK (0x2000U)
+#define CLKCTL1_PSCCTL0_SET_FC5_CLK_SHIFT (13U)
+/*! FC5_CLK - Flexcomm Interface 5 clock set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC5_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC5_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC5_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC6_CLK_MASK (0x4000U)
+#define CLKCTL1_PSCCTL0_SET_FC6_CLK_SHIFT (14U)
+/*! FC6_CLK - Flexcomm Interface 6 clock set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC6_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC6_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC6_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC7_CLK_MASK (0x8000U)
+#define CLKCTL1_PSCCTL0_SET_FC7_CLK_SHIFT (15U)
+/*! FC7_CLK - Flexcomm Interface 7 clock set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC7_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC7_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC7_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC8_CLK_MASK (0x10000U)
+#define CLKCTL1_PSCCTL0_SET_FC8_CLK_SHIFT (16U)
+/*! FC8_CLK - Flexcomm Interface 8 clock set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC8_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC8_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC8_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC9_CLK_MASK (0x20000U)
+#define CLKCTL1_PSCCTL0_SET_FC9_CLK_SHIFT (17U)
+/*! FC9_CLK - Flexcomm Interface 9 clock set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC9_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC9_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC9_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC10_CLK_MASK (0x40000U)
+#define CLKCTL1_PSCCTL0_SET_FC10_CLK_SHIFT (18U)
+/*! FC10_CLK - Flexcomm Interface 10 clock set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC10_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC10_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC10_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC11_CLK_MASK (0x80000U)
+#define CLKCTL1_PSCCTL0_SET_FC11_CLK_SHIFT (19U)
+/*! FC11_CLK - Flexcomm Interface 11 clock set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC11_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC11_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC11_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC12_CLK_MASK (0x100000U)
+#define CLKCTL1_PSCCTL0_SET_FC12_CLK_SHIFT (20U)
+/*! FC12_CLK - Flexcomm Interface 12 clock set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC12_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC12_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC12_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC13_CLK_MASK (0x200000U)
+#define CLKCTL1_PSCCTL0_SET_FC13_CLK_SHIFT (21U)
+/*! FC13_CLK - Flexcomm Interface 13 clock set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC13_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC13_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC13_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC14_SPI_CLK_MASK (0x400000U)
+#define CLKCTL1_PSCCTL0_SET_FC14_SPI_CLK_SHIFT (22U)
+/*! FC14_SPI_CLK - Flexcomm Interface 14 SPI clock control
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC14_SPI_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC14_SPI_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC14_SPI_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC15_I2C_CLK_MASK (0x800000U)
+#define CLKCTL1_PSCCTL0_SET_FC15_I2C_CLK_SHIFT (23U)
+/*! FC15_I2C_CLK - Flexcomm Interface 15 I2C clock control
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC15_I2C_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC15_I2C_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC15_I2C_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_DMIC0_MASK (0x1000000U)
+#define CLKCTL1_PSCCTL0_SET_DMIC0_SHIFT (24U)
+/*! DMIC0 - DMIC0 clock control
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_DMIC0_SHIFT)) & CLKCTL1_PSCCTL0_SET_DMIC0_MASK)
+#define CLKCTL1_PSCCTL0_SET_FC16_SPI_CLK_MASK (0x2000000U)
+#define CLKCTL1_PSCCTL0_SET_FC16_SPI_CLK_SHIFT (25U)
+/*! FC16_SPI_CLK - Flexcomm Interface 16 SPI clock control
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FC16_SPI_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC16_SPI_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC16_SPI_CLK_MASK)
+#define CLKCTL1_PSCCTL0_SET_OSEVENT_TIMER_MASK (0x8000000U)
+#define CLKCTL1_PSCCTL0_SET_OSEVENT_TIMER_SHIFT (27U)
+/*! OSEVENT_TIMER - OS event timer bus clock control
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_OSEVENT_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_OSEVENT_TIMER_SHIFT)) & CLKCTL1_PSCCTL0_SET_OSEVENT_TIMER_MASK)
+#define CLKCTL1_PSCCTL0_SET_FlexIO_MASK (0x20000000U)
+#define CLKCTL1_PSCCTL0_SET_FlexIO_SHIFT (29U)
+/*! FlexIO - FlexIO clock control
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_SET_FlexIO(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FlexIO_SHIFT)) & CLKCTL1_PSCCTL0_SET_FlexIO_MASK)
+/*! @} */
+
+/*! @name PSCCTL1_SET - Clock Set 1 */
+/*! @{ */
+#define CLKCTL1_PSCCTL1_SET_HSGPIO0_CLK_MASK (0x1U)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO0_CLK_SHIFT (0U)
+/*! HSGPIO0_CLK - Non-secure GPIO0 clock control set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_SET_HSGPIO0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO0_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO0_CLK_MASK)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO1_CLK_MASK (0x2U)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO1_CLK_SHIFT (1U)
+/*! HSGPIO1_CLK - Non-secure GPIO1 clock control set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_SET_HSGPIO1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO1_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO1_CLK_MASK)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO2_CLK_MASK (0x4U)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO2_CLK_SHIFT (2U)
+/*! HSGPIO2_CLK - Non-secure GPIO2 clock control set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_SET_HSGPIO2_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO2_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO2_CLK_MASK)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO3_CLK_MASK (0x8U)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO3_CLK_SHIFT (3U)
+/*! HSGPIO3_CLK - Non-secure GPIO3 clock control set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_SET_HSGPIO3_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO3_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO3_CLK_MASK)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO4_CLK_MASK (0x10U)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO4_CLK_SHIFT (4U)
+/*! HSGPIO4_CLK - Non-secure GPIO4 clock control set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_SET_HSGPIO4_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO4_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO4_CLK_MASK)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO5_CLK_MASK (0x20U)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO5_CLK_SHIFT (5U)
+/*! HSGPIO5_CLK - Non-secure GPIO5 clock control set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_SET_HSGPIO5_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO5_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO5_CLK_MASK)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO6_CLK_MASK (0x40U)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO6_CLK_SHIFT (6U)
+/*! HSGPIO6_CLK - Non-secure GPIO6 clock control set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_SET_HSGPIO6_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO6_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO6_CLK_MASK)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO7_CLK_MASK (0x80U)
+#define CLKCTL1_PSCCTL1_SET_HSGPIO7_CLK_SHIFT (7U)
+/*! HSGPIO7_CLK - Non-secure GPIO7 clock control set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_SET_HSGPIO7_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO7_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO7_CLK_MASK)
+#define CLKCTL1_PSCCTL1_SET_CRC_CLK_MASK (0x10000U)
+#define CLKCTL1_PSCCTL1_SET_CRC_CLK_SHIFT (16U)
+/*! CRC_CLK - CRC clock control set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_SET_CRC_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_CRC_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_CRC_CLK_MASK)
+#define CLKCTL1_PSCCTL1_SET_DMAC0_CLK_MASK (0x800000U)
+#define CLKCTL1_PSCCTL1_SET_DMAC0_CLK_SHIFT (23U)
+/*! DMAC0_CLK - DMAC0 clock control set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_SET_DMAC0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_DMAC0_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_DMAC0_CLK_MASK)
+#define CLKCTL1_PSCCTL1_SET_DMAC1_CLK_MASK (0x1000000U)
+#define CLKCTL1_PSCCTL1_SET_DMAC1_CLK_SHIFT (24U)
+/*! DMAC1_CLK - DMAC1 clock control set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_SET_DMAC1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_DMAC1_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_DMAC1_CLK_MASK)
+#define CLKCTL1_PSCCTL1_SET_MU_CLK_MASK (0x10000000U)
+#define CLKCTL1_PSCCTL1_SET_MU_CLK_SHIFT (28U)
+/*! MU_CLK - Messaging Unit clock control set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_SET_MU_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_MU_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_MU_CLK_MASK)
+#define CLKCTL1_PSCCTL1_SET_SEMA_CLK_MASK (0x20000000U)
+#define CLKCTL1_PSCCTL1_SET_SEMA_CLK_SHIFT (29U)
+/*! SEMA_CLK - Semaphore clock control set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_SET_SEMA_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_SEMA_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_SEMA_CLK_MASK)
+#define CLKCTL1_PSCCTL1_SET_FREQME_CLK_MASK (0x80000000U)
+#define CLKCTL1_PSCCTL1_SET_FREQME_CLK_SHIFT (31U)
+/*! FREQME_CLK - Frequency Measurement clock control set
+ * 0b0..No effect
+ * 0b1..Sets the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_SET_FREQME_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_FREQME_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_FREQME_CLK_MASK)
+/*! @} */
+
+/*! @name PSCCTL2_SET - Clock Set 2 */
+/*! @{ */
+#define CLKCTL1_PSCCTL2_SET_CT32BIT0_CLK_MASK (0x1U)
+#define CLKCTL1_PSCCTL2_SET_CT32BIT0_CLK_SHIFT (0U)
+/*! CT32BIT0_CLK - CT32BIT bit timer 0 clock set
+ * 0b0..No Effect
+ * 0b1..Set Bit
+ */
+#define CLKCTL1_PSCCTL2_SET_CT32BIT0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_CT32BIT0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_CT32BIT0_CLK_MASK)
+#define CLKCTL1_PSCCTL2_SET_CT32BIT1_CLK_MASK (0x2U)
+#define CLKCTL1_PSCCTL2_SET_CT32BIT1_CLK_SHIFT (1U)
+/*! CT32BIT1_CLK - CT32BIT bit timer 1 clock set
+ * 0b0..No Effect
+ * 0b1..Set Bit
+ */
+#define CLKCTL1_PSCCTL2_SET_CT32BIT1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_CT32BIT1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_CT32BIT1_CLK_MASK)
+#define CLKCTL1_PSCCTL2_SET_CT32BIT2_CLK_MASK (0x4U)
+#define CLKCTL1_PSCCTL2_SET_CT32BIT2_CLK_SHIFT (2U)
+/*! CT32BIT2_CLK - CT32BIT bit timer 2 clock set
+ * 0b0..No Effect
+ * 0b1..Set Bit
+ */
+#define CLKCTL1_PSCCTL2_SET_CT32BIT2_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_CT32BIT2_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_CT32BIT2_CLK_MASK)
+#define CLKCTL1_PSCCTL2_SET_CT32BIT3_CLK_MASK (0x8U)
+#define CLKCTL1_PSCCTL2_SET_CT32BIT3_CLK_SHIFT (3U)
+/*! CT32BIT3_CLK - CT32BIT bit timer 3 clock set
+ * 0b0..No Effect
+ * 0b1..Set Bit
+ */
+#define CLKCTL1_PSCCTL2_SET_CT32BIT3_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_CT32BIT3_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_CT32BIT3_CLK_MASK)
+#define CLKCTL1_PSCCTL2_SET_CT32BIT4_CLK_MASK (0x10U)
+#define CLKCTL1_PSCCTL2_SET_CT32BIT4_CLK_SHIFT (4U)
+/*! CT32BIT4_CLK - CT32BIT bit timer 4 clock set
+ * 0b0..No Effect
+ * 0b1..Set Bit
+ */
+#define CLKCTL1_PSCCTL2_SET_CT32BIT4_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_CT32BIT4_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_CT32BIT4_CLK_MASK)
+#define CLKCTL1_PSCCTL2_SET_RTCLITE_CLK_MASK (0x80U)
+#define CLKCTL1_PSCCTL2_SET_RTCLITE_CLK_SHIFT (7U)
+/*! RTCLITE_CLK - RTC clock control set
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_SET_RTCLITE_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_RTCLITE_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_RTCLITE_CLK_MASK)
+#define CLKCTL1_PSCCTL2_SET_MRT0_CLK_MASK (0x100U)
+#define CLKCTL1_PSCCTL2_SET_MRT0_CLK_SHIFT (8U)
+/*! MRT0_CLK - Multi-Rate Timer 0 clock control set
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_SET_MRT0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_MRT0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_MRT0_CLK_MASK)
+#define CLKCTL1_PSCCTL2_SET_WWDT1_CLK_MASK (0x400U)
+#define CLKCTL1_PSCCTL2_SET_WWDT1_CLK_SHIFT (10U)
+/*! WWDT1_CLK - Watchdog Timer 1 clock control set
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_SET_WWDT1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_WWDT1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_WWDT1_CLK_MASK)
+#define CLKCTL1_PSCCTL2_SET_I3C0_CLK_MASK (0x10000U)
+#define CLKCTL1_PSCCTL2_SET_I3C0_CLK_SHIFT (16U)
+/*! I3C0_CLK - I3C0 clock control set
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_SET_I3C0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_I3C0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_I3C0_CLK_MASK)
+#define CLKCTL1_PSCCTL2_SET_I3C1_CLK_MASK (0x20000U)
+#define CLKCTL1_PSCCTL2_SET_I3C1_CLK_SHIFT (17U)
+/*! I3C1_CLK - I3C1 clock control set
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_SET_I3C1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_I3C1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_I3C1_CLK_MASK)
+#define CLKCTL1_PSCCTL2_SET_GPIOINTCTL_CLK_MASK (0x40000000U)
+#define CLKCTL1_PSCCTL2_SET_GPIOINTCTL_CLK_SHIFT (30U)
+/*! GPIOINTCTL_CLK - PINT clock control set
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_SET_GPIOINTCTL_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_GPIOINTCTL_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_GPIOINTCTL_CLK_MASK)
+#define CLKCTL1_PSCCTL2_SET_PIMCTL_CLK_MASK (0x80000000U)
+#define CLKCTL1_PSCCTL2_SET_PIMCTL_CLK_SHIFT (31U)
+/*! PIMCTL_CLK - INPUTMUX clock control set
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_SET_PIMCTL_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_PIMCTL_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_PIMCTL_CLK_MASK)
+/*! @} */
+
+/*! @name PSCCTL0_CLR - Clock Clear 0 */
+/*! @{ */
+#define CLKCTL1_PSCCTL0_CLR_FC0_CLK_MASK (0x100U)
+#define CLKCTL1_PSCCTL0_CLR_FC0_CLK_SHIFT (8U)
+/*! FC0_CLK - Flexcomm Interface 0 clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC0_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC0_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC1_CLK_MASK (0x200U)
+#define CLKCTL1_PSCCTL0_CLR_FC1_CLK_SHIFT (9U)
+/*! FC1_CLK - Flexcomm Interface 1 clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC1_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC1_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC2_CLK_MASK (0x400U)
+#define CLKCTL1_PSCCTL0_CLR_FC2_CLK_SHIFT (10U)
+/*! FC2_CLK - Flexcomm Interface 2 clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC2_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC2_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC2_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC3_CLK_MASK (0x800U)
+#define CLKCTL1_PSCCTL0_CLR_FC3_CLK_SHIFT (11U)
+/*! FC3_CLK - Flexcomm Interface 3 clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC3_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC3_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC3_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC4_CLK_MASK (0x1000U)
+#define CLKCTL1_PSCCTL0_CLR_FC4_CLK_SHIFT (12U)
+/*! FC4_CLK - Flexcomm Interface 4 clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC4_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC4_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC4_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC5_CLK_MASK (0x2000U)
+#define CLKCTL1_PSCCTL0_CLR_FC5_CLK_SHIFT (13U)
+/*! FC5_CLK - Flexcomm Interface 5 clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC5_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC5_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC5_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC6_CLK_MASK (0x4000U)
+#define CLKCTL1_PSCCTL0_CLR_FC6_CLK_SHIFT (14U)
+/*! FC6_CLK - Flexcomm Interface 6 clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC6_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC6_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC6_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC7_CLK_MASK (0x8000U)
+#define CLKCTL1_PSCCTL0_CLR_FC7_CLK_SHIFT (15U)
+/*! FC7_CLK - Flexcomm Interface 7 clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC7_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC7_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC7_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC8_CLK_MASK (0x10000U)
+#define CLKCTL1_PSCCTL0_CLR_FC8_CLK_SHIFT (16U)
+/*! FC8_CLK - Flexcomm Interface 8 clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC8_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC8_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC8_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC9_CLK_MASK (0x20000U)
+#define CLKCTL1_PSCCTL0_CLR_FC9_CLK_SHIFT (17U)
+/*! FC9_CLK - Flexcomm Interface 9 clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC9_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC9_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC9_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC10_CLK_MASK (0x40000U)
+#define CLKCTL1_PSCCTL0_CLR_FC10_CLK_SHIFT (18U)
+/*! FC10_CLK - Flexcomm Interface 10 clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC10_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC10_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC10_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC11_CLK_MASK (0x80000U)
+#define CLKCTL1_PSCCTL0_CLR_FC11_CLK_SHIFT (19U)
+/*! FC11_CLK - Flexcomm Interface 11 clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC11_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC11_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC11_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC12_CLK_MASK (0x100000U)
+#define CLKCTL1_PSCCTL0_CLR_FC12_CLK_SHIFT (20U)
+/*! FC12_CLK - Flexcomm Interface 12 clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC12_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC12_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC12_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC13_CLK_MASK (0x200000U)
+#define CLKCTL1_PSCCTL0_CLR_FC13_CLK_SHIFT (21U)
+/*! FC13_CLK - Flexcomm Interface 13 clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC13_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC13_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC13_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC14_SPI_CLK_MASK (0x400000U)
+#define CLKCTL1_PSCCTL0_CLR_FC14_SPI_CLK_SHIFT (22U)
+/*! FC14_SPI_CLK - Flexcomm Interface 14 SPI clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC14_SPI_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC14_SPI_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC14_SPI_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC15_I2C_CLK_MASK (0x800000U)
+#define CLKCTL1_PSCCTL0_CLR_FC15_I2C_CLK_SHIFT (23U)
+/*! FC15_I2C_CLK - Flexcomm Interface 15 I2C clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC15_I2C_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC15_I2C_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC15_I2C_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_DMIC0_MASK (0x1000000U)
+#define CLKCTL1_PSCCTL0_CLR_DMIC0_SHIFT (24U)
+/*! DMIC0 - DMIC0 clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_DMIC0_SHIFT)) & CLKCTL1_PSCCTL0_CLR_DMIC0_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FC16_SPI_CLK_MASK (0x2000000U)
+#define CLKCTL1_PSCCTL0_CLR_FC16_SPI_CLK_SHIFT (25U)
+/*! FC16_SPI_CLK - Flexcomm Interface 16 SPI clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FC16_SPI_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC16_SPI_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC16_SPI_CLK_MASK)
+#define CLKCTL1_PSCCTL0_CLR_OSEVENT_TIMER_MASK (0x8000000U)
+#define CLKCTL1_PSCCTL0_CLR_OSEVENT_TIMER_SHIFT (27U)
+/*! OSEVENT_TIMER - OS event timer bus clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_OSEVENT_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_OSEVENT_TIMER_SHIFT)) & CLKCTL1_PSCCTL0_CLR_OSEVENT_TIMER_MASK)
+#define CLKCTL1_PSCCTL0_CLR_FlexIO_MASK (0x20000000U)
+#define CLKCTL1_PSCCTL0_CLR_FlexIO_SHIFT (29U)
+/*! FlexIO - FlexIO clock control clear
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL0 bit
+ */
+#define CLKCTL1_PSCCTL0_CLR_FlexIO(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FlexIO_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FlexIO_MASK)
+/*! @} */
+
+/*! @name PSCCTL1_CLR - Clock Clear 1 */
+/*! @{ */
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO0_CLK_MASK (0x1U)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO0_CLK_SHIFT (0U)
+/*! HSGPIO0_CLK - Non-secure GPIO0 clock control
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO0_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO0_CLK_MASK)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO1_CLK_MASK (0x2U)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO1_CLK_SHIFT (1U)
+/*! HSGPIO1_CLK - Non-secure GPIO1 clock control
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO1_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO1_CLK_MASK)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO2_CLK_MASK (0x4U)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO2_CLK_SHIFT (2U)
+/*! HSGPIO2_CLK - Non-secure GPIO2 clock control
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO2_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO2_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO2_CLK_MASK)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO3_CLK_MASK (0x8U)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO3_CLK_SHIFT (3U)
+/*! HSGPIO3_CLK - Non-secure GPIO3 clock control
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO3_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO3_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO3_CLK_MASK)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO4_CLK_MASK (0x10U)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO4_CLK_SHIFT (4U)
+/*! HSGPIO4_CLK - Non-secure GPIO4 clock control
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO4_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO4_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO4_CLK_MASK)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO5_CLK_MASK (0x20U)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO5_CLK_SHIFT (5U)
+/*! HSGPIO5_CLK - Non-secure GPIO5 clock control
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO5_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO5_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO5_CLK_MASK)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO6_CLK_MASK (0x40U)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO6_CLK_SHIFT (6U)
+/*! HSGPIO6_CLK - Non-secure GPIO6 clock control
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO6_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO6_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO6_CLK_MASK)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO7_CLK_MASK (0x80U)
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO7_CLK_SHIFT (7U)
+/*! HSGPIO7_CLK - Non-secure GPIO7 clock control
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_HSGPIO7_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO7_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO7_CLK_MASK)
+#define CLKCTL1_PSCCTL1_CLR_CRC_CLK_MASK (0x10000U)
+#define CLKCTL1_PSCCTL1_CLR_CRC_CLK_SHIFT (16U)
+/*! CRC_CLK - CRC clock control
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_CRC_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_CRC_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_CRC_CLK_MASK)
+#define CLKCTL1_PSCCTL1_CLR_DMAC0_CLK_MASK (0x800000U)
+#define CLKCTL1_PSCCTL1_CLR_DMAC0_CLK_SHIFT (23U)
+/*! DMAC0_CLK - DMAC0 clock control
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_DMAC0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_DMAC0_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_DMAC0_CLK_MASK)
+#define CLKCTL1_PSCCTL1_CLR_DMAC1_CLK_MASK (0x1000000U)
+#define CLKCTL1_PSCCTL1_CLR_DMAC1_CLK_SHIFT (24U)
+/*! DMAC1_CLK - DMAC1 clock control
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_DMAC1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_DMAC1_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_DMAC1_CLK_MASK)
+#define CLKCTL1_PSCCTL1_CLR_MU_CLK_MASK (0x10000000U)
+#define CLKCTL1_PSCCTL1_CLR_MU_CLK_SHIFT (28U)
+/*! MU_CLK - Messaging Unit clock control
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_MU_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_MU_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_MU_CLK_MASK)
+#define CLKCTL1_PSCCTL1_CLR_SEMA_CLK_MASK (0x20000000U)
+#define CLKCTL1_PSCCTL1_CLR_SEMA_CLK_SHIFT (29U)
+/*! SEMA_CLK - Semaphore clock control
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_SEMA_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_SEMA_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_SEMA_CLK_MASK)
+#define CLKCTL1_PSCCTL1_CLR_FREQME_CLK_MASK (0x80000000U)
+#define CLKCTL1_PSCCTL1_CLR_FREQME_CLK_SHIFT (31U)
+/*! FREQME_CLK - Frequency Measurement clock control
+ * 0b0..No effect
+ * 0b1..Clears the PSCCTL1 bit
+ */
+#define CLKCTL1_PSCCTL1_CLR_FREQME_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_FREQME_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_FREQME_CLK_MASK)
+/*! @} */
+
+/*! @name PSCCTL2_CLR - Clock Clear 2 */
+/*! @{ */
+#define CLKCTL1_PSCCTL2_CLR_CT32BIT0_CLK_MASK (0x1U)
+#define CLKCTL1_PSCCTL2_CLR_CT32BIT0_CLK_SHIFT (0U)
+/*! CT32BIT0_CLK - CT32BIT bit timer 0 clock clear
+ * 0b0..No Effect
+ * 0b1..Set Bit
+ */
+#define CLKCTL1_PSCCTL2_CLR_CT32BIT0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_CT32BIT0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_CT32BIT0_CLK_MASK)
+#define CLKCTL1_PSCCTL2_CLR_CT32BIT1_CLK_MASK (0x2U)
+#define CLKCTL1_PSCCTL2_CLR_CT32BIT1_CLK_SHIFT (1U)
+/*! CT32BIT1_CLK - CT32BIT bit timer 1 clock clear
+ * 0b0..No Effect
+ * 0b1..Set Bit
+ */
+#define CLKCTL1_PSCCTL2_CLR_CT32BIT1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_CT32BIT1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_CT32BIT1_CLK_MASK)
+#define CLKCTL1_PSCCTL2_CLR_CT32BIT2_CLK_MASK (0x4U)
+#define CLKCTL1_PSCCTL2_CLR_CT32BIT2_CLK_SHIFT (2U)
+/*! CT32BIT2_CLK - CT32BIT bit timer 2 clock clear
+ * 0b0..No Effect
+ * 0b1..Set Bit
+ */
+#define CLKCTL1_PSCCTL2_CLR_CT32BIT2_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_CT32BIT2_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_CT32BIT2_CLK_MASK)
+#define CLKCTL1_PSCCTL2_CLR_CT32BIT3_CLK_MASK (0x8U)
+#define CLKCTL1_PSCCTL2_CLR_CT32BIT3_CLK_SHIFT (3U)
+/*! CT32BIT3_CLK - CT32BIT bit timer 3 clock clear
+ * 0b0..No Effect
+ * 0b1..Set Bit
+ */
+#define CLKCTL1_PSCCTL2_CLR_CT32BIT3_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_CT32BIT3_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_CT32BIT3_CLK_MASK)
+#define CLKCTL1_PSCCTL2_CLR_CT32BIT4_CLK_MASK (0x10U)
+#define CLKCTL1_PSCCTL2_CLR_CT32BIT4_CLK_SHIFT (4U)
+/*! CT32BIT4_CLK - CT32BIT bit timer 4 clock clear
+ * 0b0..No Effect
+ * 0b1..Set Bit
+ */
+#define CLKCTL1_PSCCTL2_CLR_CT32BIT4_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_CT32BIT4_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_CT32BIT4_CLK_MASK)
+#define CLKCTL1_PSCCTL2_CLR_RTCLITE_CLK_MASK (0x80U)
+#define CLKCTL1_PSCCTL2_CLR_RTCLITE_CLK_SHIFT (7U)
+/*! RTCLITE_CLK - RTC clock control clear
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_CLR_RTCLITE_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_RTCLITE_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_RTCLITE_CLK_MASK)
+#define CLKCTL1_PSCCTL2_CLR_MRT0_CLK_MASK (0x100U)
+#define CLKCTL1_PSCCTL2_CLR_MRT0_CLK_SHIFT (8U)
+/*! MRT0_CLK - Multi-Rate Timer 0 clock control clear
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_CLR_MRT0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_MRT0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_MRT0_CLK_MASK)
+#define CLKCTL1_PSCCTL2_CLR_WWDT1_CLK_MASK (0x400U)
+#define CLKCTL1_PSCCTL2_CLR_WWDT1_CLK_SHIFT (10U)
+/*! WWDT1_CLK - Watchdog Timer 1 clock control clear
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_CLR_WWDT1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_WWDT1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_WWDT1_CLK_MASK)
+#define CLKCTL1_PSCCTL2_CLR_I3C0_CLK_MASK (0x10000U)
+#define CLKCTL1_PSCCTL2_CLR_I3C0_CLK_SHIFT (16U)
+/*! I3C0_CLK - I3C0 clock control clear
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_CLR_I3C0_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_I3C0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_I3C0_CLK_MASK)
+#define CLKCTL1_PSCCTL2_CLR_I3C1_CLK_MASK (0x20000U)
+#define CLKCTL1_PSCCTL2_CLR_I3C1_CLK_SHIFT (17U)
+/*! I3C1_CLK - I3C1 clock control clear
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_CLR_I3C1_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_I3C1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_I3C1_CLK_MASK)
+#define CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_MASK (0x40000000U)
+#define CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_SHIFT (30U)
+/*! GPIOINTCTL_CLK - PINT clock control clear
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_MASK)
+#define CLKCTL1_PSCCTL2_CLR_PIMCTL_CLK_MASK (0x80000000U)
+#define CLKCTL1_PSCCTL2_CLR_PIMCTL_CLK_SHIFT (31U)
+/*! PIMCTL_CLK - INPUTMUX clock control clear
+ * 0b0..Disable Clock
+ * 0b1..Enable Clock
+ */
+#define CLKCTL1_PSCCTL2_CLR_PIMCTL_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_PIMCTL_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_PIMCTL_CLK_MASK)
+/*! @} */
+
+/*! @name AUDIOPLL0CLKSEL - Audio PLL0 Clock Select */
+/*! @{ */
+#define CLKCTL1_AUDIOPLL0CLKSEL_SEL_MASK (0x7U)
+#define CLKCTL1_AUDIOPLL0CLKSEL_SEL_SHIFT (0U)
+/*! SEL - Audio PLL0 Clock Select
+ * 0b000..FRO_DIV8
+ * 0b001..OSC_CLK clock (User-Selectable)
+ * 0b010..Reserved
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_AUDIOPLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0CLKSEL_SEL_SHIFT)) & CLKCTL1_AUDIOPLL0CLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name AUDIOPLL0CTL0 - Audio PLL0 Control 0 */
+/*! @{ */
+#define CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK (0x1U)
+#define CLKCTL1_AUDIOPLL0CTL0_BYPASS_SHIFT (0U)
+/*! BYPASS - AUDIOPLL0 BYPASS Mode
+ * 0b0..PFD outputs are PFD-programmed clocks
+ * 0b1..Bypass Mode. PFD outputs are sourced directly from the reference input clock
+ */
+#define CLKCTL1_AUDIOPLL0CTL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0CTL0_BYPASS_SHIFT)) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK)
+#define CLKCTL1_AUDIOPLL0CTL0_RESET_MASK (0x2U)
+#define CLKCTL1_AUDIOPLL0CTL0_RESET_SHIFT (1U)
+/*! RESET - AUDIOPLL0 Reset
+ * 0b0..AUDIOPLL0 reset is removed
+ * 0b1..AUDIOPLL0 is placed into reset
+ */
+#define CLKCTL1_AUDIOPLL0CTL0_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0CTL0_RESET_SHIFT)) & CLKCTL1_AUDIOPLL0CTL0_RESET_MASK)
+#define CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK (0x2000U)
+#define CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_SHIFT (13U)
+/*! HOLDRINGOFF_ENA - Hold Ring Off Control
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_SHIFT)) & CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK)
+#define CLKCTL1_AUDIOPLL0CTL0_MULT_MASK (0xFF0000U)
+#define CLKCTL1_AUDIOPLL0CTL0_MULT_SHIFT (16U)
+/*! MULT - Multiplication Factor
+ * 0b00010000..Divide by 16
+ * 0b00010001..Divide by 17
+ * 0b00010010..Divide by 18
+ * 0b00010011..Divide by 19
+ * 0b00010100..Divide by 20
+ * 0b00010101..Divide by 21
+ * 0b00010110..Divide by 22
+ */
+#define CLKCTL1_AUDIOPLL0CTL0_MULT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0CTL0_MULT_SHIFT)) & CLKCTL1_AUDIOPLL0CTL0_MULT_MASK)
+/*! @} */
+
+/*! @name AUDIOPLL0LOCKTIMEDIV2 - Audio PLL0 Lock Time Divide-by-2 */
+/*! @{ */
+#define CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK (0xFFFFU)
+#define CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT (0U)
+/*! LOCKTIMEDIV2 - AUDIOPLL0 Lock Time Divide-by-2
+ */
+#define CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT)) & CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK)
+/*! @} */
+
+/*! @name AUDIOPLL0NUM - Audio PLL0 Numerator */
+/*! @{ */
+#define CLKCTL1_AUDIOPLL0NUM_NUM_MASK (0x3FFFFFFFU)
+#define CLKCTL1_AUDIOPLL0NUM_NUM_SHIFT (0U)
+/*! NUM - Numerator
+ */
+#define CLKCTL1_AUDIOPLL0NUM_NUM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0NUM_NUM_SHIFT)) & CLKCTL1_AUDIOPLL0NUM_NUM_MASK)
+/*! @} */
+
+/*! @name AUDIOPLL0DENOM - Audio PLL0 Denominator */
+/*! @{ */
+#define CLKCTL1_AUDIOPLL0DENOM_DENOM_MASK (0x3FFFFFFFU)
+#define CLKCTL1_AUDIOPLL0DENOM_DENOM_SHIFT (0U)
+/*! DENOM - Denominator
+ */
+#define CLKCTL1_AUDIOPLL0DENOM_DENOM(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0DENOM_DENOM_SHIFT)) & CLKCTL1_AUDIOPLL0DENOM_DENOM_MASK)
+/*! @} */
+
+/*! @name AUDIOPLL0PFD - Audio PLL0 PFD */
+/*! @{ */
+#define CLKCTL1_AUDIOPLL0PFD_PFD0_MASK (0x3FU)
+#define CLKCTL1_AUDIOPLL0PFD_PFD0_SHIFT (0U)
+/*! PFD0 - PLL Fractional Divider 0
+ */
+#define CLKCTL1_AUDIOPLL0PFD_PFD0(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD0_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD0_MASK)
+#define CLKCTL1_AUDIOPLL0PFD_PFD0_CLKRDY_MASK (0x40U)
+#define CLKCTL1_AUDIOPLL0PFD_PFD0_CLKRDY_SHIFT (6U)
+/*! PFD0_CLKRDY - PFD0 Clock Ready Status Flag
+ * 0b0..Not ready
+ * 0b1..Ready
+ */
+#define CLKCTL1_AUDIOPLL0PFD_PFD0_CLKRDY(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD0_CLKRDY_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD0_CLKRDY_MASK)
+#define CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK (0x80U)
+#define CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_SHIFT (7U)
+/*! PFD0_CLKGATE - PFD0 Clock Gate
+ * 0b0..PFD0 clock is not gated
+ * 0b1..PFD0 clock is gated
+ */
+#define CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK)
+#define CLKCTL1_AUDIOPLL0PFD_PFD1_MASK (0x3F00U)
+#define CLKCTL1_AUDIOPLL0PFD_PFD1_SHIFT (8U)
+/*! PFD1 - PLL Fractional Divider 1
+ */
+#define CLKCTL1_AUDIOPLL0PFD_PFD1(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD1_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD1_MASK)
+#define CLKCTL1_AUDIOPLL0PFD_PFD1_CLKRDY_MASK (0x4000U)
+#define CLKCTL1_AUDIOPLL0PFD_PFD1_CLKRDY_SHIFT (14U)
+/*! PFD1_CLKRDY - PFD1 Clock Ready Status Flag
+ * 0b0..Not ready
+ * 0b1..Ready
+ */
+#define CLKCTL1_AUDIOPLL0PFD_PFD1_CLKRDY(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD1_CLKRDY_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD1_CLKRDY_MASK)
+#define CLKCTL1_AUDIOPLL0PFD_PFD1_CLKGATE_MASK (0x8000U)
+#define CLKCTL1_AUDIOPLL0PFD_PFD1_CLKGATE_SHIFT (15U)
+/*! PFD1_CLKGATE - PFD1 Clock Gate
+ * 0b0..PFD1 clock is not gated
+ * 0b1..PFD1 clock is gated
+ */
+#define CLKCTL1_AUDIOPLL0PFD_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD1_CLKGATE_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD1_CLKGATE_MASK)
+#define CLKCTL1_AUDIOPLL0PFD_PFD2_MASK (0x3F0000U)
+#define CLKCTL1_AUDIOPLL0PFD_PFD2_SHIFT (16U)
+/*! PFD2 - PLL Fractional Divider 2
+ */
+#define CLKCTL1_AUDIOPLL0PFD_PFD2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD2_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD2_MASK)
+#define CLKCTL1_AUDIOPLL0PFD_PFD2_CLKRDY_MASK (0x400000U)
+#define CLKCTL1_AUDIOPLL0PFD_PFD2_CLKRDY_SHIFT (22U)
+/*! PFD2_CLKRDY - PFD2 Clock Ready Status Flag
+ * 0b0..Not ready
+ * 0b1..Ready
+ */
+#define CLKCTL1_AUDIOPLL0PFD_PFD2_CLKRDY(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD2_CLKRDY_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD2_CLKRDY_MASK)
+#define CLKCTL1_AUDIOPLL0PFD_PFD2_CLKGATE_MASK (0x800000U)
+#define CLKCTL1_AUDIOPLL0PFD_PFD2_CLKGATE_SHIFT (23U)
+/*! PFD2_CLKGATE - PFD2 Clock Gate
+ * 0b0..PFD2 clock is not gated
+ * 0b1..PFD2 clock is gated
+ */
+#define CLKCTL1_AUDIOPLL0PFD_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD2_CLKGATE_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD2_CLKGATE_MASK)
+#define CLKCTL1_AUDIOPLL0PFD_PFD3_MASK (0x3F000000U)
+#define CLKCTL1_AUDIOPLL0PFD_PFD3_SHIFT (24U)
+/*! PFD3 - PLL Fractional Divider 3
+ */
+#define CLKCTL1_AUDIOPLL0PFD_PFD3(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD3_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD3_MASK)
+#define CLKCTL1_AUDIOPLL0PFD_PFD3_CLKRDY_MASK (0x40000000U)
+#define CLKCTL1_AUDIOPLL0PFD_PFD3_CLKRDY_SHIFT (30U)
+/*! PFD3_CLKRDY - PFD3 Clock Ready Status Flag
+ * 0b0..Not ready
+ * 0b1..Ready
+ */
+#define CLKCTL1_AUDIOPLL0PFD_PFD3_CLKRDY(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD3_CLKRDY_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD3_CLKRDY_MASK)
+#define CLKCTL1_AUDIOPLL0PFD_PFD3_CLKGATE_MASK (0x80000000U)
+#define CLKCTL1_AUDIOPLL0PFD_PFD3_CLKGATE_SHIFT (31U)
+/*! PFD3_CLKGATE - PFD3 Clock Gate
+ * 0b0..PFD3 clock is not gated
+ * 0b1..PFD3 clock is gated
+ */
+#define CLKCTL1_AUDIOPLL0PFD_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD3_CLKGATE_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD3_CLKGATE_MASK)
+/*! @} */
+
+/*! @name AUDIOPLLCLKDIV - Audio PLL Clock Divider */
+/*! @{ */
+#define CLKCTL1_AUDIOPLLCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL1_AUDIOPLLCLKDIV_DIV_SHIFT (0U)
+/*! DIV - 32 KHz Wake Clock Divider Value
+ */
+#define CLKCTL1_AUDIOPLLCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLLCLKDIV_DIV_SHIFT)) & CLKCTL1_AUDIOPLLCLKDIV_DIV_MASK)
+#define CLKCTL1_AUDIOPLLCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL1_AUDIOPLLCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL1_AUDIOPLLCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLLCLKDIV_RESET_SHIFT)) & CLKCTL1_AUDIOPLLCLKDIV_RESET_MASK)
+#define CLKCTL1_AUDIOPLLCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL1_AUDIOPLLCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL1_AUDIOPLLCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLLCLKDIV_HALT_SHIFT)) & CLKCTL1_AUDIOPLLCLKDIV_HALT_MASK)
+#define CLKCTL1_AUDIOPLLCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL1_AUDIOPLLCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider Status Flag
+ * 0b0..The Divider change has finished
+ * 0b1..The Divider value has changed
+ */
+#define CLKCTL1_AUDIOPLLCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLLCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_AUDIOPLLCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name DSPCPUCLKDIV - DSP CPU Clock Divider */
+/*! @{ */
+#define CLKCTL1_DSPCPUCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL1_DSPCPUCLKDIV_DIV_SHIFT (0U)
+/*! DIV - DSP Clock Divider Value
+ */
+#define CLKCTL1_DSPCPUCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DSPCPUCLKDIV_DIV_SHIFT)) & CLKCTL1_DSPCPUCLKDIV_DIV_MASK)
+#define CLKCTL1_DSPCPUCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL1_DSPCPUCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL1_DSPCPUCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DSPCPUCLKDIV_RESET_SHIFT)) & CLKCTL1_DSPCPUCLKDIV_RESET_MASK)
+#define CLKCTL1_DSPCPUCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL1_DSPCPUCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL1_DSPCPUCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DSPCPUCLKDIV_HALT_SHIFT)) & CLKCTL1_DSPCPUCLKDIV_HALT_MASK)
+#define CLKCTL1_DSPCPUCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL1_DSPCPUCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider Status Flag
+ * 0b0..The Divider change has finished (clock being divided must be running for this status to change).
+ * 0b1..The Divider value has changed.
+ */
+#define CLKCTL1_DSPCPUCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DSPCPUCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_DSPCPUCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name DSPCPUCLKSELA - DSP CPU Clock Select A */
+/*! @{ */
+#define CLKCTL1_DSPCPUCLKSELA_SEL_MASK (0x3U)
+#define CLKCTL1_DSPCPUCLKSELA_SEL_SHIFT (0U)
+/*! SEL - DSP Main 1st Stage Control Clock Source
+ * 0b00..FRO_DIV1 Clock
+ * 0b01..OSC_CLK Clock
+ * 0b10..Low Power Oscillator Clock (LPOSC)
+ * 0b11..Reserved
+ */
+#define CLKCTL1_DSPCPUCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DSPCPUCLKSELA_SEL_SHIFT)) & CLKCTL1_DSPCPUCLKSELA_SEL_MASK)
+/*! @} */
+
+/*! @name DSPCPUCLKSELB - DSP CPU Clock Select B */
+/*! @{ */
+#define CLKCTL1_DSPCPUCLKSELB_SEL_MASK (0x3U)
+#define CLKCTL1_DSPCPUCLKSELB_SEL_SHIFT (0U)
+/*! SEL - Main Clock Source
+ * 0b00..MAINCLKSELA 1st Stage Clock
+ * 0b01..Main System PLL Clock
+ * 0b10..DSP System PLL Clock
+ * 0b11..RTC 32 KHz Clock
+ */
+#define CLKCTL1_DSPCPUCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DSPCPUCLKSELB_SEL_SHIFT)) & CLKCTL1_DSPCPUCLKSELB_SEL_MASK)
+/*! @} */
+
+/*! @name OSEVENTTFCLKSEL - OS Event Timer Functional Clock Select */
+/*! @{ */
+#define CLKCTL1_OSEVENTTFCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL1_OSEVENTTFCLKSEL_SEL_SHIFT (0U)
+/*! SEL - OS Event Timer Functional Clock Source
+ * 0b000..Low Power Oscillator Clock (LPOSC)
+ * 0b001..RTC 32 KHz Clock
+ * 0b010..HCLK Free-Running Clock (Global Time Stamping)
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_OSEVENTTFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_OSEVENTTFCLKSEL_SEL_SHIFT)) & CLKCTL1_OSEVENTTFCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name FRGCLKSEL - Fractional Rate Generator 0 Clock Select..Fractional Rate Generator 16 Clock Select */
+/*! @{ */
+#define CLKCTL1_FRGCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL1_FRGCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Fractional Generator 16 Clock Source
+ * 0b000..Main Clock
+ * 0b001..FRG PLL Clock
+ * 0b010..FRO_DIV4 clock
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGCLKSEL_SEL_SHIFT)) & CLKCTL1_FRGCLKSEL_SEL_MASK)
+/*! @} */
+
+/* The count of CLKCTL1_FRGCLKSEL */
+#define CLKCTL1_FRGCLKSEL_COUNT (17U)
+
+/*! @name FRGCTL - Fractional Rate Generator 0 Control..Fractional Rate Generator 16 Control */
+/*! @{ */
+#define CLKCTL1_FRGCTL_DIV_MASK (0xFFU)
+#define CLKCTL1_FRGCTL_DIV_SHIFT (0U)
+#define CLKCTL1_FRGCTL_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGCTL_DIV_SHIFT)) & CLKCTL1_FRGCTL_DIV_MASK)
+#define CLKCTL1_FRGCTL_MULT_MASK (0xFF00U)
+#define CLKCTL1_FRGCTL_MULT_SHIFT (8U)
+#define CLKCTL1_FRGCTL_MULT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGCTL_MULT_SHIFT)) & CLKCTL1_FRGCTL_MULT_MASK)
+/*! @} */
+
+/* The count of CLKCTL1_FRGCTL */
+#define CLKCTL1_FRGCTL_COUNT (17U)
+
+/*! @name FCFCLKSEL - Flexcomm0 Clock Select..Flexcomm16 Clock Select */
+/*! @{ */
+#define CLKCTL1_FCFCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL1_FCFCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Flexcomm Functional Clock Source
+ * 0b000..FRO_DIV4 clock
+ * 0b001..Audio PLL Clock
+ * 0b010..Master Clock In
+ * 0b011..FCn FRG Clock
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_FCFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FCFCLKSEL_SEL_SHIFT)) & CLKCTL1_FCFCLKSEL_SEL_MASK)
+/*! @} */
+
+/* The count of CLKCTL1_FCFCLKSEL */
+#define CLKCTL1_FCFCLKSEL_COUNT (17U)
+
+/*! @name FRG17CLKSEL - Fractional Rate Generator 17 Clock Select */
+/*! @{ */
+#define CLKCTL1_FRG17CLKSEL_SEL_MASK (0x7U)
+#define CLKCTL1_FRG17CLKSEL_SEL_SHIFT (0U)
+/*! SEL - Fractional Generator 17 Clock Source
+ * 0b000..Main Clock
+ * 0b001..FRG PLL Clock
+ * 0b010..FRO_DIV4 clock
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_FRG17CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRG17CLKSEL_SEL_SHIFT)) & CLKCTL1_FRG17CLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name FRG17CTL - Fractional Rate Generator 17 Control */
+/*! @{ */
+#define CLKCTL1_FRG17CTL_DIV_MASK (0xFFU)
+#define CLKCTL1_FRG17CTL_DIV_SHIFT (0U)
+#define CLKCTL1_FRG17CTL_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRG17CTL_DIV_SHIFT)) & CLKCTL1_FRG17CTL_DIV_MASK)
+#define CLKCTL1_FRG17CTL_MULT_MASK (0xFF00U)
+#define CLKCTL1_FRG17CTL_MULT_SHIFT (8U)
+#define CLKCTL1_FRG17CTL_MULT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRG17CTL_MULT_SHIFT)) & CLKCTL1_FRG17CTL_MULT_MASK)
+/*! @} */
+
+/*! @name FLEXIOCLKSEL - FlexIO Clock Select */
+/*! @{ */
+#define CLKCTL1_FLEXIOCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL1_FLEXIOCLKSEL_SEL_SHIFT (0U)
+/*! SEL - FlexIO Functional Clock Source
+ * 0b000..FRO_DIV2 Clock
+ * 0b001..Audio PLL Clock
+ * 0b010..Master Clock In
+ * 0b011..FC17 FRG Clock
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_FLEXIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FLEXIOCLKSEL_SEL_SHIFT)) & CLKCTL1_FLEXIOCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name FLEXIOCLKDIV - FlexIO Clock Divider */
+/*! @{ */
+#define CLKCTL1_FLEXIOCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL1_FLEXIOCLKDIV_DIV_SHIFT (0U)
+/*! DIV - FLEXIO Clock Divider Value
+ */
+#define CLKCTL1_FLEXIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FLEXIOCLKDIV_DIV_SHIFT)) & CLKCTL1_FLEXIOCLKDIV_DIV_MASK)
+#define CLKCTL1_FLEXIOCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL1_FLEXIOCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL1_FLEXIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FLEXIOCLKDIV_RESET_SHIFT)) & CLKCTL1_FLEXIOCLKDIV_RESET_MASK)
+#define CLKCTL1_FLEXIOCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL1_FLEXIOCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL1_FLEXIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FLEXIOCLKDIV_HALT_SHIFT)) & CLKCTL1_FLEXIOCLKDIV_HALT_MASK)
+#define CLKCTL1_FLEXIOCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL1_FLEXIOCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider Status Flag
+ * 0b0..The Divider change has finished (clock being divided must be running for this status to change).
+ * 0b1..The Divider value has changed
+ */
+#define CLKCTL1_FLEXIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FLEXIOCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_FLEXIOCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name FRGPLLCLKDIV - Fractional Rate Generator PLL Clock Divider */
+/*! @{ */
+#define CLKCTL1_FRGPLLCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL1_FRGPLLCLKDIV_DIV_SHIFT (0U)
+/*! DIV - FRG PLL Clock Divider Value
+ */
+#define CLKCTL1_FRGPLLCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGPLLCLKDIV_DIV_SHIFT)) & CLKCTL1_FRGPLLCLKDIV_DIV_MASK)
+#define CLKCTL1_FRGPLLCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL1_FRGPLLCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL1_FRGPLLCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGPLLCLKDIV_RESET_SHIFT)) & CLKCTL1_FRGPLLCLKDIV_RESET_MASK)
+#define CLKCTL1_FRGPLLCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL1_FRGPLLCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL1_FRGPLLCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGPLLCLKDIV_HALT_SHIFT)) & CLKCTL1_FRGPLLCLKDIV_HALT_MASK)
+#define CLKCTL1_FRGPLLCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL1_FRGPLLCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider Status Flag
+ * 0b0..The Divider change has finished (clock being divided must be running for this status to change).
+ * 0b1..The Divider value has changed.
+ */
+#define CLKCTL1_FRGPLLCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGPLLCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_FRGPLLCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name DMIC0FCLKSEL - DMIC0 Functional Clock Select */
+/*! @{ */
+#define CLKCTL1_DMIC0FCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL1_DMIC0FCLKSEL_SEL_SHIFT (0U)
+/*! SEL - DMIC Functional Clock Source
+ * 0b000..FRO Clock (Divided-by-4 selection)
+ * 0b001..Audio PLL Clock
+ * 0b010..Master Clock In
+ * 0b011..Low Power Oscillator Clock (LPOSC)
+ * 0b100..32 KHz Wake Clock
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_DMIC0FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DMIC0FCLKSEL_SEL_SHIFT)) & CLKCTL1_DMIC0FCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name DMIC0FCLKDIV - DMIC0 Functional Clock Divider */
+/*! @{ */
+#define CLKCTL1_DMIC0FCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL1_DMIC0FCLKDIV_DIV_SHIFT (0U)
+/*! DIV - 32 KHz Wake Clock Divider Value
+ */
+#define CLKCTL1_DMIC0FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DMIC0FCLKDIV_DIV_SHIFT)) & CLKCTL1_DMIC0FCLKDIV_DIV_MASK)
+#define CLKCTL1_DMIC0FCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL1_DMIC0FCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL1_DMIC0FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DMIC0FCLKDIV_RESET_SHIFT)) & CLKCTL1_DMIC0FCLKDIV_RESET_MASK)
+#define CLKCTL1_DMIC0FCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL1_DMIC0FCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL1_DMIC0FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DMIC0FCLKDIV_HALT_SHIFT)) & CLKCTL1_DMIC0FCLKDIV_HALT_MASK)
+#define CLKCTL1_DMIC0FCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL1_DMIC0FCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider Status Flag
+ * 0b0..The Divider change has finished (clock being divided must be running for this status to change).
+ * 0b1..The Divider value has changed.
+ */
+#define CLKCTL1_DMIC0FCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DMIC0FCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_DMIC0FCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name CT32BITFCLKSEL - CT32BIT bit timer 0 Functional Clock Select..CT32BIT bit timer 4 Functional Clock Select */
+/*! @{ */
+#define CLKCTL1_CT32BITFCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL1_CT32BITFCLKSEL_SEL_SHIFT (0U)
+/*! SEL - CT32BIT bit timer 4 Functional Clock Source
+ * 0b000..Main Clock
+ * 0b001..FRO_DIV1 Clock
+ * 0b010..Audio PLL Clock
+ * 0b011..Master Clock In
+ * 0b100..32 KHZ Wake Clock
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_CT32BITFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CT32BITFCLKSEL_SEL_SHIFT)) & CLKCTL1_CT32BITFCLKSEL_SEL_MASK)
+/*! @} */
+
+/* The count of CLKCTL1_CT32BITFCLKSEL */
+#define CLKCTL1_CT32BITFCLKSEL_COUNT (5U)
+
+/*! @name AUDIOMCLKSEL - Audio MCLK Clock Select */
+/*! @{ */
+#define CLKCTL1_AUDIOMCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL1_AUDIOMCLKSEL_SEL_SHIFT (0U)
+/*! SEL - Audio MCLK Clock Source Select
+ * 0b000..FRO_DIV8 Clock
+ * 0b001..AUDIO PLL Clock (Shared Domain)
+ * 0b010..Reserved
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_AUDIOMCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOMCLKSEL_SEL_SHIFT)) & CLKCTL1_AUDIOMCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name AUDIOMCLKDIV - Audio MCLK Clock Divider */
+/*! @{ */
+#define CLKCTL1_AUDIOMCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL1_AUDIOMCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Audio MCLK Clock Divider Value
+ */
+#define CLKCTL1_AUDIOMCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOMCLKDIV_DIV_SHIFT)) & CLKCTL1_AUDIOMCLKDIV_DIV_MASK)
+#define CLKCTL1_AUDIOMCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL1_AUDIOMCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL1_AUDIOMCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOMCLKDIV_RESET_SHIFT)) & CLKCTL1_AUDIOMCLKDIV_RESET_MASK)
+#define CLKCTL1_AUDIOMCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL1_AUDIOMCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL1_AUDIOMCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOMCLKDIV_HALT_SHIFT)) & CLKCTL1_AUDIOMCLKDIV_HALT_MASK)
+#define CLKCTL1_AUDIOMCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL1_AUDIOMCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider Status Flag
+ * 0b0..The Divider change has finished (clock being divided must be running for this status to change).
+ * 0b1..The Divider value has changed.
+ */
+#define CLKCTL1_AUDIOMCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOMCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_AUDIOMCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name CLKOUTSEL0 - CLKOUT Clock Select 0 */
+/*! @{ */
+#define CLKCTL1_CLKOUTSEL0_SEL_MASK (0x7U)
+#define CLKCTL1_CLKOUTSEL0_SEL_SHIFT (0U)
+/*! SEL - Clock Output Select 1st Stage
+ * 0b000..OSC_CLK Clock
+ * 0b001..Low Power Oscillator Clock (LPOSC)
+ * 0b010..FRO_DIV2 Clock
+ * 0b011..Main Clock
+ * 0b100..DSP Main Clock
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_CLKOUTSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTSEL0_SEL_SHIFT)) & CLKCTL1_CLKOUTSEL0_SEL_MASK)
+/*! @} */
+
+/*! @name CLKOUTSEL1 - CLKOUT Clock Select 1 */
+/*! @{ */
+#define CLKCTL1_CLKOUTSEL1_SEL_MASK (0x7U)
+#define CLKCTL1_CLKOUTSEL1_SEL_SHIFT (0U)
+/*! SEL - Clock Out Source
+ * 0b000..CLKOUTSEL0 Multiplexed Output
+ * 0b001..Main System PLL Clock
+ * 0b010..SYSPLL0 AUX0_PLL_Clock
+ * 0b011..DSP PLL Clock
+ * 0b100..SYSPLL0 AUX1_PLL_Clock
+ * 0b101..AUDIO PLL Clock
+ * 0b110..32 KHz RTC Clock
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_CLKOUTSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTSEL1_SEL_SHIFT)) & CLKCTL1_CLKOUTSEL1_SEL_MASK)
+/*! @} */
+
+/*! @name CLKOUTFCLKDIV - CLKOUT Functional Clock Divider */
+/*! @{ */
+#define CLKCTL1_CLKOUTFCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL1_CLKOUTFCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock-Out Clock Divider Value
+ */
+#define CLKCTL1_CLKOUTFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTFCLKDIV_DIV_SHIFT)) & CLKCTL1_CLKOUTFCLKDIV_DIV_MASK)
+#define CLKCTL1_CLKOUTFCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL1_CLKOUTFCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL1_CLKOUTFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTFCLKDIV_RESET_SHIFT)) & CLKCTL1_CLKOUTFCLKDIV_RESET_MASK)
+#define CLKCTL1_CLKOUTFCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL1_CLKOUTFCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL1_CLKOUTFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTFCLKDIV_HALT_SHIFT)) & CLKCTL1_CLKOUTFCLKDIV_HALT_MASK)
+#define CLKCTL1_CLKOUTFCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL1_CLKOUTFCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider Status Flag
+ * 0b0..The Divider change has finished (clock being divided must be running for this status to change).
+ * 0b1..The Divider value has changed
+ */
+#define CLKCTL1_CLKOUTFCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTFCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_CLKOUTFCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name I3C01FCLKSEL - I3C0, I3C1 Functional Clock Select */
+/*! @{ */
+#define CLKCTL1_I3C01FCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL1_I3C01FCLKSEL_SEL_SHIFT (0U)
+/*! SEL - I3C0, I3C1 Clock Source
+ * 0b000..Main Clock
+ * 0b001..FRO_DIV8 Clock
+ * 0b010..Reserved
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_I3C01FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSEL_SEL_SHIFT)) & CLKCTL1_I3C01FCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name I3C01FCLKSTCSEL - I3C0, I3C1 Functional Slow Time Control Clock Select */
+/*! @{ */
+#define CLKCTL1_I3C01FCLKSTCSEL_SEL_MASK (0x7U)
+#define CLKCTL1_I3C01FCLKSTCSEL_SEL_SHIFT (0U)
+/*! SEL - I3C0, I3C1 Clock Source
+ * 0b000..I3C0 FCLK
+ * 0b001..Low Power Oscillator Clock (LPOSC)
+ * 0b010..Reserved
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_I3C01FCLKSTCSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSTCSEL_SEL_SHIFT)) & CLKCTL1_I3C01FCLKSTCSEL_SEL_MASK)
+/*! @} */
+
+/*! @name I3C01FCLKSTCDIV - I3C0, I3C1 Functional Slow Time Control Clock Divider */
+/*! @{ */
+#define CLKCTL1_I3C01FCLKSTCDIV_DIV_MASK (0xFFU)
+#define CLKCTL1_I3C01FCLKSTCDIV_DIV_SHIFT (0U)
+/*! DIV - I3C0, I3C1 Clock Divider Value
+ */
+#define CLKCTL1_I3C01FCLKSTCDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSTCDIV_DIV_SHIFT)) & CLKCTL1_I3C01FCLKSTCDIV_DIV_MASK)
+#define CLKCTL1_I3C01FCLKSTCDIV_RESET_MASK (0x20000000U)
+#define CLKCTL1_I3C01FCLKSTCDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL1_I3C01FCLKSTCDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSTCDIV_RESET_SHIFT)) & CLKCTL1_I3C01FCLKSTCDIV_RESET_MASK)
+#define CLKCTL1_I3C01FCLKSTCDIV_HALT_MASK (0x40000000U)
+#define CLKCTL1_I3C01FCLKSTCDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL1_I3C01FCLKSTCDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSTCDIV_HALT_SHIFT)) & CLKCTL1_I3C01FCLKSTCDIV_HALT_MASK)
+#define CLKCTL1_I3C01FCLKSTCDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL1_I3C01FCLKSTCDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider Status Flag
+ * 0b0..The Divider change has finished (clock being divided must be running for this status to change).
+ * 0b1..The Divider value has changed.
+ */
+#define CLKCTL1_I3C01FCLKSTCDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSTCDIV_REQFLAG_SHIFT)) & CLKCTL1_I3C01FCLKSTCDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name I3C01FCLKSDIV - I3C0, I3C1 Functional Slow Clock Divider */
+/*! @{ */
+#define CLKCTL1_I3C01FCLKSDIV_DIV_MASK (0xFFU)
+#define CLKCTL1_I3C01FCLKSDIV_DIV_SHIFT (0U)
+/*! DIV - I3C0, I3C1 Clock Divider Value
+ */
+#define CLKCTL1_I3C01FCLKSDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSDIV_DIV_SHIFT)) & CLKCTL1_I3C01FCLKSDIV_DIV_MASK)
+#define CLKCTL1_I3C01FCLKSDIV_RESET_MASK (0x20000000U)
+#define CLKCTL1_I3C01FCLKSDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL1_I3C01FCLKSDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSDIV_RESET_SHIFT)) & CLKCTL1_I3C01FCLKSDIV_RESET_MASK)
+#define CLKCTL1_I3C01FCLKSDIV_HALT_MASK (0x40000000U)
+#define CLKCTL1_I3C01FCLKSDIV_HALT_SHIFT (30U)
+/*! HALT - Halt the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL1_I3C01FCLKSDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSDIV_HALT_SHIFT)) & CLKCTL1_I3C01FCLKSDIV_HALT_MASK)
+#define CLKCTL1_I3C01FCLKSDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL1_I3C01FCLKSDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider Status Flag
+ * 0b0..The Divider change has finished (clock being divided must be running for this status to change).
+ * 0b1..The Divider value has changed.
+ */
+#define CLKCTL1_I3C01FCLKSDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSDIV_REQFLAG_SHIFT)) & CLKCTL1_I3C01FCLKSDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name I3C01FCLKDIV - I3C0, I3C1 Functional Clock Divider */
+/*! @{ */
+#define CLKCTL1_I3C01FCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL1_I3C01FCLKDIV_DIV_SHIFT (0U)
+/*! DIV - I3C0, I3C1 Clock Divider Value
+ */
+#define CLKCTL1_I3C01FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKDIV_DIV_SHIFT)) & CLKCTL1_I3C01FCLKDIV_DIV_MASK)
+#define CLKCTL1_I3C01FCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL1_I3C01FCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL1_I3C01FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKDIV_RESET_SHIFT)) & CLKCTL1_I3C01FCLKDIV_RESET_MASK)
+#define CLKCTL1_I3C01FCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL1_I3C01FCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL1_I3C01FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKDIV_HALT_SHIFT)) & CLKCTL1_I3C01FCLKDIV_HALT_MASK)
+#define CLKCTL1_I3C01FCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL1_I3C01FCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider Status Flag
+ * 0b0..The Divider change has finished (clock being divided must be running for this status to change).
+ * 0b1..The Divider value has changed.
+ */
+#define CLKCTL1_I3C01FCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_I3C01FCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name I3C01FCLKSTSTCLKSEL - I3C01 Functional Clock Select */
+/*! @{ */
+#define CLKCTL1_I3C01FCLKSTSTCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL1_I3C01FCLKSTSTCLKSEL_SEL_SHIFT (0U)
+/*! SEL - I3C0, I3C1 FCLK Test Clock Source
+ * 0b000..Low Power Oscillator Clock (LPOSC)
+ * 0b001..Reserved
+ * 0b010..Reserved
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_I3C01FCLKSTSTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSTSTCLKSEL_SEL_SHIFT)) & CLKCTL1_I3C01FCLKSTSTCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name WDT1FCLKSEL - Watchdog Timer 1 Functional Clock Select */
+/*! @{ */
+#define CLKCTL1_WDT1FCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL1_WDT1FCLKSEL_SEL_SHIFT (0U)
+/*! SEL - WDT1 Functional Clock Source
+ * 0b000..Low Power Oscillator Clock (LPOSC)
+ * 0b001..Main Clock
+ * 0b010..Reserved
+ * 0b011..Reserved
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_WDT1FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_WDT1FCLKSEL_SEL_SHIFT)) & CLKCTL1_WDT1FCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name ACMP0FCLKSEL - Analog Comparator 0 Clock Select */
+/*! @{ */
+#define CLKCTL1_ACMP0FCLKSEL_SEL_MASK (0x7U)
+#define CLKCTL1_ACMP0FCLKSEL_SEL_SHIFT (0U)
+/*! SEL - ACMP0 Fast Functional Clock Source
+ * 0b000..Main Clock
+ * 0b001..FRO_DIV4 Clock
+ * 0b010..SYSPLL0 AUX0_PLL_Clock
+ * 0b011..SYSPLL0 AUX1_PLL_Clock
+ * 0b100..Reserved
+ * 0b101..Reserved
+ * 0b110..Reserved
+ * 0b111..None, output gated to reduce power
+ */
+#define CLKCTL1_ACMP0FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_ACMP0FCLKSEL_SEL_SHIFT)) & CLKCTL1_ACMP0FCLKSEL_SEL_MASK)
+/*! @} */
+
+/*! @name ACMP0FCLKDIV - Analog comparator 0 FCLK divider */
+/*! @{ */
+#define CLKCTL1_ACMP0FCLKDIV_DIV_MASK (0xFFU)
+#define CLKCTL1_ACMP0FCLKDIV_DIV_SHIFT (0U)
+/*! DIV - Clock Out Clock Divider Value
+ */
+#define CLKCTL1_ACMP0FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_ACMP0FCLKDIV_DIV_SHIFT)) & CLKCTL1_ACMP0FCLKDIV_DIV_MASK)
+#define CLKCTL1_ACMP0FCLKDIV_RESET_MASK (0x20000000U)
+#define CLKCTL1_ACMP0FCLKDIV_RESET_SHIFT (29U)
+/*! RESET - Reset the Divider Counter
+ * 0b0..No effect
+ * 0b1..Reset the Divider Counter
+ */
+#define CLKCTL1_ACMP0FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_ACMP0FCLKDIV_RESET_SHIFT)) & CLKCTL1_ACMP0FCLKDIV_RESET_MASK)
+#define CLKCTL1_ACMP0FCLKDIV_HALT_MASK (0x40000000U)
+#define CLKCTL1_ACMP0FCLKDIV_HALT_SHIFT (30U)
+/*! HALT - Halts the Divider Counter
+ * 0b0..No effect
+ * 0b1..Halt (stop) the Divider Counter
+ */
+#define CLKCTL1_ACMP0FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_ACMP0FCLKDIV_HALT_SHIFT)) & CLKCTL1_ACMP0FCLKDIV_HALT_MASK)
+#define CLKCTL1_ACMP0FCLKDIV_REQFLAG_MASK (0x80000000U)
+#define CLKCTL1_ACMP0FCLKDIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider Status Flag
+ * 0b0..The Divider change has finished (clock being divided must be running for this status to change).
+ * 0b1..The Divider value has changed.
+ */
+#define CLKCTL1_ACMP0FCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_ACMP0FCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_ACMP0FCLKDIV_REQFLAG_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CLKCTL1_Register_Masks */
+
+
+/* CLKCTL1 - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral CLKCTL1 base address */
+ #define CLKCTL1_BASE (0x50021000u)
+ /** Peripheral CLKCTL1 base address */
+ #define CLKCTL1_BASE_NS (0x40021000u)
+ /** Peripheral CLKCTL1 base pointer */
+ #define CLKCTL1 ((CLKCTL1_Type *)CLKCTL1_BASE)
+ /** Peripheral CLKCTL1 base pointer */
+ #define CLKCTL1_NS ((CLKCTL1_Type *)CLKCTL1_BASE_NS)
+ /** Array initializer of CLKCTL1 peripheral base addresses */
+ #define CLKCTL1_BASE_ADDRS { CLKCTL1_BASE }
+ /** Array initializer of CLKCTL1 peripheral base pointers */
+ #define CLKCTL1_BASE_PTRS { CLKCTL1 }
+ /** Array initializer of CLKCTL1 peripheral base addresses */
+ #define CLKCTL1_BASE_ADDRS_NS { CLKCTL1_BASE_NS }
+ /** Array initializer of CLKCTL1 peripheral base pointers */
+ #define CLKCTL1_BASE_PTRS_NS { CLKCTL1_NS }
+#else
+ /** Peripheral CLKCTL1 base address */
+ #define CLKCTL1_BASE (0x40021000u)
+ /** Peripheral CLKCTL1 base pointer */
+ #define CLKCTL1 ((CLKCTL1_Type *)CLKCTL1_BASE)
+ /** Array initializer of CLKCTL1 peripheral base addresses */
+ #define CLKCTL1_BASE_ADDRS { CLKCTL1_BASE }
+ /** Array initializer of CLKCTL1 peripheral base pointers */
+ #define CLKCTL1_BASE_PTRS { CLKCTL1 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group CLKCTL1_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
+ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
+ __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x8 */
+ __IO uint32_t C1; /**< CMP Control Register 1, offset: 0xC */
+ __IO uint32_t C2; /**< CMP Control Register 2, offset: 0x10 */
+ __IO uint32_t C3; /**< CMP Control Register 3, offset: 0x14 */
+ __IO uint32_t RR_TIMER_CR; /**< Round-Robin Timer Control Register, offset: 0x18 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define CMP_VERID_FEATURE_MASK (0xFFFFU)
+#define CMP_VERID_FEATURE_SHIFT (0U)
+/*! FEATURE - Feature Specification Number. This read only filed returns the feature set number.
+ */
+#define CMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)
+#define CMP_VERID_MINOR_MASK (0xFF0000U)
+#define CMP_VERID_MINOR_SHIFT (16U)
+/*! MINOR - Minor Version Number. This read only field returns the minor version number for the module specification.
+ */
+#define CMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)
+#define CMP_VERID_MAJOR_MASK (0xFF000000U)
+#define CMP_VERID_MAJOR_SHIFT (24U)
+/*! MAJOR - Major Version Number. This read only field returns the major version number for the module specification.
+ */
+#define CMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define CMP_PARAM_PARAM_MASK (0xFFFFFFFFU)
+#define CMP_PARAM_PARAM_SHIFT (0U)
+/*! PARAM - Parameter Registers. This read only filed returns the feature parameters implemented along with the Version ID register.
+ */
+#define CMP_PARAM_PARAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)
+/*! @} */
+
+/*! @name C0 - CMP Control Register 0 */
+/*! @{ */
+#define CMP_C0_HYSTCTR_MASK (0x3U)
+#define CMP_C0_HYSTCTR_SHIFT (0U)
+/*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level
+ * 0b00..The hard block output has level 0 hysteresis internally.
+ * 0b01..The hard block output has level 1 hysteresis internally.
+ * 0b10..The hard block output has level 2 hysteresis internally.
+ * 0b11..The hard block output has level 3 hysteresis internally.
+ */
+#define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK)
+#define CMP_C0_FILTER_CNT_MASK (0x70U)
+#define CMP_C0_FILTER_CNT_SHIFT (4U)
+/*! FILTER_CNT - Filter Sample Count
+ * 0b000..Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA.
+ * 0b001..1 consecutive sample must agree (comparator output is simply sampled).
+ * 0b010..2 consecutive samples must agree.
+ * 0b011..3 consecutive samples must agree.
+ * 0b100..4 consecutive samples must agree.
+ * 0b101..5 consecutive samples must agree.
+ * 0b110..6 consecutive samples must agree.
+ * 0b111..7 consecutive samples must agree.
+ */
+#define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK)
+#define CMP_C0_EN_MASK (0x100U)
+#define CMP_C0_EN_SHIFT (8U)
+/*! EN - Comparator Module Enable
+ * 0b0..Analog Comparator is disabled.
+ * 0b1..Analog Comparator is enabled.
+ */
+#define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK)
+#define CMP_C0_OPE_MASK (0x200U)
+#define CMP_C0_OPE_SHIFT (9U)
+/*! OPE - Comparator Output Pin Enable
+ * 0b0..When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin.
+ * 0b1..When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin.
+ */
+#define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK)
+#define CMP_C0_COS_MASK (0x400U)
+#define CMP_C0_COS_SHIFT (10U)
+/*! COS - Comparator Output Select
+ * 0b0..Set CMPO to equal COUT (filtered comparator output).
+ * 0b1..Set CMPO to equal COUTA (unfiltered comparator output).
+ */
+#define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK)
+#define CMP_C0_INVT_MASK (0x800U)
+#define CMP_C0_INVT_SHIFT (11U)
+/*! INVT - Comparator invert
+ * 0b0..Does not invert the comparator output.
+ * 0b1..Inverts the comparator output.
+ */
+#define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK)
+#define CMP_C0_PMODE_MASK (0x1000U)
+#define CMP_C0_PMODE_SHIFT (12U)
+/*! PMODE - Power Mode Select
+ * 0b0..Low Speed (LS) comparison mode is selected.
+ * 0b1..High Speed (HS) comparison mode is selected.
+ */
+#define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK)
+#define CMP_C0_WE_MASK (0x4000U)
+#define CMP_C0_WE_SHIFT (14U)
+/*! WE - Windowing Enable
+ * 0b0..Windowing mode is not selected.
+ * 0b1..Windowing mode is selected.
+ */
+#define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK)
+#define CMP_C0_SE_MASK (0x8000U)
+#define CMP_C0_SE_SHIFT (15U)
+/*! SE - Sample Enable
+ * 0b0..Sampling mode is not selected.
+ * 0b1..Sampling mode is selected.
+ */
+#define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK)
+#define CMP_C0_FPR_MASK (0xFF0000U)
+#define CMP_C0_FPR_SHIFT (16U)
+/*! FPR - Filter Sample Period
+ */
+#define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK)
+#define CMP_C0_COUT_MASK (0x1000000U)
+#define CMP_C0_COUT_SHIFT (24U)
+/*! COUT - Analog Comparator Output
+ */
+#define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK)
+#define CMP_C0_CFF_MASK (0x2000000U)
+#define CMP_C0_CFF_SHIFT (25U)
+/*! CFF - Analog Comparator Flag Falling
+ * 0b0..A falling edge has not been detected on COUT.
+ * 0b1..A falling edge on COUT has occurred.
+ */
+#define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK)
+#define CMP_C0_CFR_MASK (0x4000000U)
+#define CMP_C0_CFR_SHIFT (26U)
+/*! CFR - Analog Comparator Flag Rising
+ * 0b0..A rising edge has not been detected on COUT.
+ * 0b1..A rising edge on COUT has occurred.
+ */
+#define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
+#define CMP_C0_IEF_MASK (0x8000000U)
+#define CMP_C0_IEF_SHIFT (27U)
+/*! IEF - Comparator Interrupt Enable Falling
+ * 0b0..Interrupt is disabled.
+ * 0b1..Interrupt is enabled.
+ */
+#define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK)
+#define CMP_C0_IER_MASK (0x10000000U)
+#define CMP_C0_IER_SHIFT (28U)
+/*! IER - Comparator Interrupt Enable Rising
+ * 0b0..Interrupt is disabled.
+ * 0b1..Interrupt is enabled.
+ */
+#define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK)
+#define CMP_C0_DMAEN_MASK (0x40000000U)
+#define CMP_C0_DMAEN_SHIFT (30U)
+/*! DMAEN - DMA Enable
+ * 0b0..DMA is disabled.
+ * 0b1..DMA is enabled.
+ */
+#define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK)
+#define CMP_C0_LINKEN_MASK (0x80000000U)
+#define CMP_C0_LINKEN_SHIFT (31U)
+/*! LINKEN - CMP to DAC link enable.
+ * 0b0..CMP to DAC link is disabled
+ * 0b1..CMP to DAC link is enabled.
+ */
+#define CMP_C0_LINKEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK)
+/*! @} */
+
+/*! @name C1 - CMP Control Register 1 */
+/*! @{ */
+#define CMP_C1_VOSEL_MASK (0xFFU)
+#define CMP_C1_VOSEL_SHIFT (0U)
+/*! VOSEL - DAC Output Voltage Select
+ */
+#define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK)
+#define CMP_C1_DMODE_MASK (0x100U)
+#define CMP_C1_DMODE_SHIFT (8U)
+/*! DMODE - DAC Mode Selection
+ * 0b0..DAC is selected to work in low speed and low power mode.
+ * 0b1..DAC is selected to work in high speed high power mode.
+ */
+#define CMP_C1_DMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK)
+#define CMP_C1_VRSEL_MASK (0x200U)
+#define CMP_C1_VRSEL_SHIFT (9U)
+/*! VRSEL - Supply Voltage Reference Source Select
+ * 0b0..Vin1 is selected as resistor ladder network supply reference Vin. Vin1 is from internal PMC.
+ * 0b1..Vin2 is selected as resistor ladder network supply reference Vin. Vin2 is from PAD.
+ */
+#define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK)
+#define CMP_C1_DACEN_MASK (0x400U)
+#define CMP_C1_DACEN_SHIFT (10U)
+/*! DACEN - DAC Enable
+ * 0b0..DAC is disabled.
+ * 0b1..DAC is enabled.
+ */
+#define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK)
+#define CMP_C1_PSEL_SEC_MASK (0x7000U)
+#define CMP_C1_PSEL_SEC_SHIFT (12U)
+/*! PSEL_SEC - Secondary Plus channel select.
+ * 0b000..Input 0 for Plus Channel
+ * 0b001..Input 1 for Plus Channel
+ * 0b010..Input 2 for Plus Channel
+ * 0b011..Input 3 for Plus Channel
+ * 0b100..Input 4 for Plus Channel
+ * 0b101..Input 5 for Plus Channel
+ * 0b110..Input 6 for Plus Channel
+ * 0b111..Internal 8b DAC output for Plus Channel
+ */
+#define CMP_C1_PSEL_SEC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SEC_SHIFT)) & CMP_C1_PSEL_SEC_MASK)
+#define CMP_C1_CHN0_MASK (0x10000U)
+#define CMP_C1_CHN0_SHIFT (16U)
+/*! CHN0 - Channel 0 input enable
+ */
+#define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK)
+#define CMP_C1_CHN1_MASK (0x20000U)
+#define CMP_C1_CHN1_SHIFT (17U)
+/*! CHN1 - Channel 1 input enable
+ */
+#define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK)
+#define CMP_C1_CHN2_MASK (0x40000U)
+#define CMP_C1_CHN2_SHIFT (18U)
+/*! CHN2 - Channel 2 input enable
+ */
+#define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK)
+#define CMP_C1_CHN3_MASK (0x80000U)
+#define CMP_C1_CHN3_SHIFT (19U)
+/*! CHN3 - Channel 3 input enable
+ */
+#define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK)
+#define CMP_C1_CHN4_MASK (0x100000U)
+#define CMP_C1_CHN4_SHIFT (20U)
+/*! CHN4 - Channel 4 input enable
+ */
+#define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK)
+#define CMP_C1_CHN5_MASK (0x200000U)
+#define CMP_C1_CHN5_SHIFT (21U)
+/*! CHN5 - Channel 5 input enable
+ */
+#define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK)
+#define CMP_C1_MSEL_MASK (0x7000000U)
+#define CMP_C1_MSEL_SHIFT (24U)
+/*! MSEL - Minus Input MUX Control
+ * 0b000..Internal Negative Input 0 for Minus Channel -- Internal Minus Input
+ * 0b001..External Input 1 for Minus Channel -- Reference Input 0
+ * 0b010..External Input 2 for Minus Channel -- Reference Input 1
+ * 0b011..External Input 3 for Minus Channel -- Reference Input 2
+ * 0b100..External Input 4 for Minus Channel -- Reference Input 3
+ * 0b101..External Input 5 for Minus Channel -- Reference Input 4
+ * 0b110..External Input 6 for Minus Channel -- Reference Input 5
+ * 0b111..Internal 8b DAC output
+ */
+#define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK)
+#define CMP_C1_PSEL_MASK (0x70000000U)
+#define CMP_C1_PSEL_SHIFT (28U)
+/*! PSEL - Plus Input MUX Control
+ * 0b000..Internal Posivite Input 0 for Plus Channel -- Internal Minus Input
+ * 0b001..External Input 1 for Plus Channel -- Reference Input 0
+ * 0b010..External Input 2 for Plus Channel -- Reference Input 1
+ * 0b011..External Input 3 for Plus Channel -- Reference Input 2
+ * 0b100..External Input 4 for Plus Channel -- Reference Input 3
+ * 0b101..External Input 4 for Plus Channel -- Reference Input 4
+ * 0b110..External Input 4 for Plus Channel -- Reference Input 5
+ * 0b111..Internal 8b DAC output
+ */
+#define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK)
+/*! @} */
+
+/*! @name C2 - CMP Control Register 2 */
+/*! @{ */
+#define CMP_C2_ACOn_MASK (0x3FU)
+#define CMP_C2_ACOn_SHIFT (0U)
+/*! ACOn - ACOn
+ */
+#define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK)
+#define CMP_C2_INITMOD_MASK (0x3F00U)
+#define CMP_C2_INITMOD_SHIFT (8U)
+/*! INITMOD - Comparator and DAC initialization delay modulus.
+ */
+#define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK)
+#define CMP_C2_NSAM_MASK (0xC000U)
+#define CMP_C2_NSAM_SHIFT (14U)
+/*! NSAM - Number of sample clocks
+ * 0b00..The comparison result is sampled as soon as the active channel is scanned in one round-robin clock.
+ * 0b01..The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock.
+ * 0b10..The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock.
+ * 0b11..The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock.
+ */
+#define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK)
+#define CMP_C2_CH0F_MASK (0x10000U)
+#define CMP_C2_CH0F_SHIFT (16U)
+/*! CH0F - CH0F
+ */
+#define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK)
+#define CMP_C2_CH1F_MASK (0x20000U)
+#define CMP_C2_CH1F_SHIFT (17U)
+/*! CH1F - CH1F
+ */
+#define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK)
+#define CMP_C2_CH2F_MASK (0x40000U)
+#define CMP_C2_CH2F_SHIFT (18U)
+/*! CH2F - CH2F
+ */
+#define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK)
+#define CMP_C2_CH3F_MASK (0x80000U)
+#define CMP_C2_CH3F_SHIFT (19U)
+/*! CH3F - CH3F
+ */
+#define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK)
+#define CMP_C2_CH4F_MASK (0x100000U)
+#define CMP_C2_CH4F_SHIFT (20U)
+/*! CH4F - CH4F
+ */
+#define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK)
+#define CMP_C2_CH5F_MASK (0x200000U)
+#define CMP_C2_CH5F_SHIFT (21U)
+/*! CH5F - CH5F
+ */
+#define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK)
+#define CMP_C2_FXMXCH_MASK (0xE000000U)
+#define CMP_C2_FXMXCH_SHIFT (25U)
+/*! FXMXCH - Fixed channel selection
+ * 0b000..External Reference Input 0 is selected as the fixed reference input for the fixed mux port.
+ * 0b001..External Reference Input 1 is selected as the fixed reference input for the fixed mux port.
+ * 0b010..External Reference Input 2 is selected as the fixed reference input for the fixed mux port.
+ * 0b011..External Reference Input 3 is selected as the fixed reference input for the fixed mux port.
+ * 0b100..External Reference Input 4 is selected as the fixed reference input for the fixed mux port.
+ * 0b101..External Reference Input 5 is selected as the fixed reference input for the fixed mux port.
+ * 0b110..Reserved.
+ * 0b111..The 8bit DAC is selected as the fixed reference input for the fixed mux port.
+ */
+#define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK)
+#define CMP_C2_FXMP_MASK (0x20000000U)
+#define CMP_C2_FXMP_SHIFT (29U)
+/*! FXMP - Fixed MUX Port
+ * 0b0..The Plus port is fixed. Only the inputs to the Minus port are swept in each round.
+ * 0b1..The Minus port is fixed. Only the inputs to the Plus port are swept in each round.
+ */
+#define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK)
+#define CMP_C2_RRIE_MASK (0x40000000U)
+#define CMP_C2_RRIE_SHIFT (30U)
+/*! RRIE - Round-Robin interrupt enable
+ * 0b0..The round-robin interrupt is disabled.
+ * 0b1..The round-robin interrupt is enabled when a comparison result changes from the last sample.
+ */
+#define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK)
+/*! @} */
+
+/*! @name C3 - CMP Control Register 3 */
+/*! @{ */
+#define CMP_C3_ACPH2TC_MASK (0x70U)
+#define CMP_C3_ACPH2TC_SHIFT (4U)
+/*! ACPH2TC - Analog Comparator Phase2 Timing Control.
+ * 0b000..Phase2 active time in one sampling period equals to T
+ * 0b001..Phase2 active time in one sampling period equals to 2*T
+ * 0b010..Phase2 active time in one sampling period equals to 4*T
+ * 0b011..Phase2 active time in one sampling period equals to 8*T
+ * 0b100..Phase2 active time in one sampling period equals to 16*T
+ * 0b101..Phase2 active time in one sampling period equals to 32*T
+ * 0b110..Phase2 active time in one sampling period equals to 64*T
+ * 0b111..Phase2 active time in one sampling period equals to 16*T
+ */
+#define CMP_C3_ACPH2TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK)
+#define CMP_C3_ACPH1TC_MASK (0x700U)
+#define CMP_C3_ACPH1TC_SHIFT (8U)
+/*! ACPH1TC - Analog Comparator Phase1 Timing Control.
+ * 0b000..Phase1 active time in one sampling period equals to T
+ * 0b001..Phase1 active time in one sampling period equals to 2*T
+ * 0b010..Phase1 active time in one sampling period equals to 4*T
+ * 0b011..Phase1 active time in one sampling period equals to 8*T
+ * 0b100..Phase1 active time in one sampling period equals to T
+ * 0b101..Phase1 active time in one sampling period equals to T
+ * 0b110..Phase1 active time in one sampling period equals to T
+ * 0b111..Phase1 active time in one sampling period equals to 0
+ */
+#define CMP_C3_ACPH1TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK)
+#define CMP_C3_ACSAT_MASK (0x7000U)
+#define CMP_C3_ACSAT_SHIFT (12U)
+/*! ACSAT - Analog Comparator Sampling Time control.
+ * 0b000..The sampling time equals to T
+ * 0b001..The sampling time equasl to 2*T
+ * 0b010..The sampling time equasl to 4*T
+ * 0b011..The sampling time equasl to 8*T
+ * 0b100..The sampling time equasl to 16*T
+ * 0b101..The sampling time equasl to 32*T
+ * 0b110..The sampling time equasl to 64*T
+ * 0b111..The sampling time equasl to 256*T
+ */
+#define CMP_C3_ACSAT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK)
+#define CMP_C3_DMCS_MASK (0x10000U)
+#define CMP_C3_DMCS_SHIFT (16U)
+/*! DMCS - Discrete Mode Clock Selection
+ * 0b0..Slow clock is selected for the timing generation.
+ * 0b1..Fast clock is selected for the timing generation.
+ */
+#define CMP_C3_DMCS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK)
+#define CMP_C3_RDIVE_MASK (0x100000U)
+#define CMP_C3_RDIVE_SHIFT (20U)
+/*! RDIVE - Resistor Divider Enable
+ * 0b0..The resistor is not enabled even when either NCHEN or PCHEN is set to1 but the actual input is in the range of 0 - 1.8v.
+ * 0b1..The resistor is enabled because the inputs are above 1.8v.
+ */
+#define CMP_C3_RDIVE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK)
+#define CMP_C3_NCHCTEN_MASK (0x1000000U)
+#define CMP_C3_NCHCTEN_SHIFT (24U)
+/*! NCHCTEN - Negative Channel Continuous Mode Enable.
+ * 0b0..Negative channel is in Discrete Mode and special timing needs to be configured.
+ * 0b1..Negative channel is in Continuous Mode and no special timing is requried.
+ */
+#define CMP_C3_NCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK)
+#define CMP_C3_PCHCTEN_MASK (0x10000000U)
+#define CMP_C3_PCHCTEN_SHIFT (28U)
+/*! PCHCTEN - Positive Channel Continuous Mode Enable.
+ * 0b0..Positive channel is in Discrete Mode and special timing needs to be configured.
+ * 0b1..Positive channel is in Continuous Mode and no special timing is requried.
+ */
+#define CMP_C3_PCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK)
+/*! @} */
+
+/*! @name RR_TIMER_CR - Round-Robin Timer Control Register */
+/*! @{ */
+#define CMP_RR_TIMER_CR_RR_TIMER_RELOAD_MASK (0xFFFFFFFU)
+#define CMP_RR_TIMER_CR_RR_TIMER_RELOAD_SHIFT (0U)
+/*! RR_TIMER_RELOAD - This field establishes the repetitive count rate for the timer. Each time the
+ * timer counts down to zero it is reloaded with this value. The rr_trig signal will be generated
+ * at a rate of (rr_timer_reload + 1) times the rr_clock period (typically 30.6 uS)
+ */
+#define CMP_RR_TIMER_CR_RR_TIMER_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << CMP_RR_TIMER_CR_RR_TIMER_RELOAD_SHIFT)) & CMP_RR_TIMER_CR_RR_TIMER_RELOAD_MASK)
+#define CMP_RR_TIMER_CR_RR_TIMER_ENA_MASK (0x80000000U)
+#define CMP_RR_TIMER_CR_RR_TIMER_ENA_SHIFT (31U)
+/*! RR_TIMER_ENA - RR_TIMER enable
+ */
+#define CMP_RR_TIMER_CR_RR_TIMER_ENA(x) (((uint32_t)(((uint32_t)(x)) << CMP_RR_TIMER_CR_RR_TIMER_ENA_SHIFT)) & CMP_RR_TIMER_CR_RR_TIMER_ENA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral ACMP0 base address */
+ #define ACMP0_BASE (0x50139000u)
+ /** Peripheral ACMP0 base address */
+ #define ACMP0_BASE_NS (0x40139000u)
+ /** Peripheral ACMP0 base pointer */
+ #define ACMP0 ((CMP_Type *)ACMP0_BASE)
+ /** Peripheral ACMP0 base pointer */
+ #define ACMP0_NS ((CMP_Type *)ACMP0_BASE_NS)
+ /** Array initializer of CMP peripheral base addresses */
+ #define CMP_BASE_ADDRS { ACMP0_BASE }
+ /** Array initializer of CMP peripheral base pointers */
+ #define CMP_BASE_PTRS { ACMP0 }
+ /** Array initializer of CMP peripheral base addresses */
+ #define CMP_BASE_ADDRS_NS { ACMP0_BASE_NS }
+ /** Array initializer of CMP peripheral base pointers */
+ #define CMP_BASE_PTRS_NS { ACMP0_NS }
+#else
+ /** Peripheral ACMP0 base address */
+ #define ACMP0_BASE (0x40139000u)
+ /** Peripheral ACMP0 base pointer */
+ #define ACMP0 ((CMP_Type *)ACMP0_BASE)
+ /** Array initializer of CMP peripheral base addresses */
+ #define CMP_BASE_ADDRS { ACMP0_BASE }
+ /** Array initializer of CMP peripheral base pointers */
+ #define CMP_BASE_PTRS { ACMP0 }
+#endif
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS { ACMP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MODE; /**< MODE Register, offset: 0x0 */
+ __IO uint32_t SEED; /**< CRC Seed Register, offset: 0x4 */
+ union { /* offset: 0x8 */
+ __I uint32_t SUM; /**< CRC Sum, offset: 0x8 */
+ __IO uint32_t WR_DATA; /**< CRC Write Data, offset: 0x8 */
+ };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name MODE - MODE Register */
+/*! @{ */
+#define CRC_MODE_CRC_POLY_MASK (0x3U)
+#define CRC_MODE_CRC_POLY_SHIFT (0U)
+/*! CRC_POLY - CRC Polynomial
+ * 0b00..Use CRC-CCITT polynomial
+ * 0b01..Use CRC-16 polynomial
+ * 0b10..Use CRC-32 polynomial
+ * 0b11..Reserved
+ */
+#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
+#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
+#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
+/*! BIT_RVS_WR - Bit-order Reverse for Write Data
+ * 0b0..Do not use bit-order reverse for WR_DATA (per byte)
+ * 0b1..Use bit-order reverse for WR_DATA (per byte)
+ */
+#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
+#define CRC_MODE_CMPL_WR_MASK (0x8U)
+#define CRC_MODE_CMPL_WR_SHIFT (3U)
+/*! CMPL_WR - 1's Complement for Write Data
+ * 0b0..Do not use 1's complement for WR_DATA
+ * 0b1..Use 1's complement for WR_DATA
+ */
+#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
+#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
+#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
+/*! BIT_RVS_SUM - Bit-order Reverse for CRC Sum
+ * 0b0..Do not use bit-order reverse for CRC Sum
+ * 0b1..Use bit-order reverse for CRC Sum
+ */
+#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
+#define CRC_MODE_CMPL_SUM_MASK (0x20U)
+#define CRC_MODE_CMPL_SUM_SHIFT (5U)
+/*! CMPL_SUM - 1's Complement for CRC Sum
+ * 0b0..Do not use 1's complement for CRC Sum
+ * 0b1..Use 1's complement for CRC Sum
+ */
+#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
+/*! @} */
+
+/*! @name SEED - CRC Seed Register */
+/*! @{ */
+#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
+#define CRC_SEED_CRC_SEED_SHIFT (0U)
+/*! CRC_SEED - CRC Seed
+ */
+#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
+/*! @} */
+
+/*! @name SUM - CRC Sum */
+/*! @{ */
+#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
+#define CRC_SUM_CRC_SUM_SHIFT (0U)
+/*! CRC_SUM - CRC Sum
+ */
+#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
+/*! @} */
+
+/*! @name WR_DATA - CRC Write Data */
+/*! @{ */
+#define CRC_WR_DATA_WR_DATA_MASK (0xFFFFFFFFU)
+#define CRC_WR_DATA_WR_DATA_SHIFT (0U)
+/*! WR_DATA - CRC Write Data
+ */
+#define CRC_WR_DATA_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_WR_DATA_SHIFT)) & CRC_WR_DATA_WR_DATA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral CRC_ENGINE base address */
+ #define CRC_ENGINE_BASE (0x50120000u)
+ /** Peripheral CRC_ENGINE base address */
+ #define CRC_ENGINE_BASE_NS (0x40120000u)
+ /** Peripheral CRC_ENGINE base pointer */
+ #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
+ /** Peripheral CRC_ENGINE base pointer */
+ #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS)
+ /** Array initializer of CRC peripheral base addresses */
+ #define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
+ /** Array initializer of CRC peripheral base pointers */
+ #define CRC_BASE_PTRS { CRC_ENGINE }
+ /** Array initializer of CRC peripheral base addresses */
+ #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS }
+ /** Array initializer of CRC peripheral base pointers */
+ #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS }
+#else
+ /** Peripheral CRC_ENGINE base address */
+ #define CRC_ENGINE_BASE (0x40120000u)
+ /** Peripheral CRC_ENGINE base pointer */
+ #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
+ /** Array initializer of CRC peripheral base addresses */
+ #define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
+ /** Array initializer of CRC peripheral base pointers */
+ #define CRC_BASE_PTRS { CRC_ENGINE }
+#endif
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CTIMER Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
+ * @{
+ */
+
+/** CTIMER - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t IR; /**< Interrupt Register., offset: 0x0 */
+ __IO uint32_t TCR; /**< Timer Control Register, offset: 0x4 */
+ __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
+ __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
+ __IO uint32_t PC; /**< Prescale Counter., offset: 0x10 */
+ __IO uint32_t MCR; /**< Match Control Register., offset: 0x14 */
+ __IO uint32_t MR[4]; /**< Match Register, array offset: 0x18, array step: 0x4 */
+ __IO uint32_t CCR; /**< Capture Control Register, offset: 0x28 */
+ __I uint32_t CR[4]; /**< Capture Register, array offset: 0x2C, array step: 0x4 */
+ __IO uint32_t EMR; /**< External Match Register, offset: 0x3C */
+ uint8_t RESERVED_0[48];
+ __IO uint32_t CTCR; /**< Count Control Register, offset: 0x70 */
+ __IO uint32_t PWMC; /**< PWM Control Register, offset: 0x74 */
+ __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
+} CTIMER_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CTIMER Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
+ * @{
+ */
+
+/*! @name IR - Interrupt Register. */
+/*! @{ */
+#define CTIMER_IR_MR0INT_MASK (0x1U)
+#define CTIMER_IR_MR0INT_SHIFT (0U)
+/*! MR0INT - Interrupt flag for match channel 0
+ */
+#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
+#define CTIMER_IR_MR1INT_MASK (0x2U)
+#define CTIMER_IR_MR1INT_SHIFT (1U)
+/*! MR1INT - Interrupt flag for match channel 1
+ */
+#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
+#define CTIMER_IR_MR2INT_MASK (0x4U)
+#define CTIMER_IR_MR2INT_SHIFT (2U)
+/*! MR2INT - Interrupt flag for match channel 2
+ */
+#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
+#define CTIMER_IR_MR3INT_MASK (0x8U)
+#define CTIMER_IR_MR3INT_SHIFT (3U)
+/*! MR3INT - Interrupt flag for match channel 3
+ */
+#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
+#define CTIMER_IR_CR0INT_MASK (0x10U)
+#define CTIMER_IR_CR0INT_SHIFT (4U)
+/*! CR0INT - Interrupt flag for capture channel 0 event
+ */
+#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
+#define CTIMER_IR_CR1INT_MASK (0x20U)
+#define CTIMER_IR_CR1INT_SHIFT (5U)
+/*! CR1INT - Interrupt flag for capture channel 1 event
+ */
+#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
+#define CTIMER_IR_CR2INT_MASK (0x40U)
+#define CTIMER_IR_CR2INT_SHIFT (6U)
+/*! CR2INT - Interrupt flag for capture channel 2 event
+ */
+#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
+#define CTIMER_IR_CR3INT_MASK (0x80U)
+#define CTIMER_IR_CR3INT_SHIFT (7U)
+/*! CR3INT - Interrupt flag for capture channel 3 event
+ */
+#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
+/*! @} */
+
+/*! @name TCR - Timer Control Register */
+/*! @{ */
+#define CTIMER_TCR_CEN_MASK (0x1U)
+#define CTIMER_TCR_CEN_SHIFT (0U)
+/*! CEN - Counter enable.
+ * 0b0..Disabled. The counters are disabled.
+ * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
+ */
+#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
+#define CTIMER_TCR_CRST_MASK (0x2U)
+#define CTIMER_TCR_CRST_SHIFT (1U)
+/*! CRST - Counter reset.
+ * 0b0..Disabled. Do nothing.
+ * 0b1..Enabled
+ */
+#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
+/*! @} */
+
+/*! @name TC - Timer Counter */
+/*! @{ */
+#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
+#define CTIMER_TC_TCVAL_SHIFT (0U)
+/*! TCVAL - Timer counter value.
+ */
+#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
+/*! @} */
+
+/*! @name PR - Prescale Register */
+/*! @{ */
+#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
+#define CTIMER_PR_PRVAL_SHIFT (0U)
+/*! PRVAL - Prescale reload value.
+ */
+#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
+/*! @} */
+
+/*! @name PC - Prescale Counter. */
+/*! @{ */
+#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
+#define CTIMER_PC_PCVAL_SHIFT (0U)
+/*! PCVAL - Prescale counter value.
+ */
+#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
+/*! @} */
+
+/*! @name MCR - Match Control Register. */
+/*! @{ */
+#define CTIMER_MCR_MR0I_MASK (0x1U)
+#define CTIMER_MCR_MR0I_SHIFT (0U)
+/*! MR0I - Interrupt on MR0
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
+#define CTIMER_MCR_MR0R_MASK (0x2U)
+#define CTIMER_MCR_MR0R_SHIFT (1U)
+/*! MR0R - Reset on MR0
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
+#define CTIMER_MCR_MR0S_MASK (0x4U)
+#define CTIMER_MCR_MR0S_SHIFT (2U)
+/*! MR0S - Stop on MR0
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
+#define CTIMER_MCR_MR1I_MASK (0x8U)
+#define CTIMER_MCR_MR1I_SHIFT (3U)
+/*! MR1I - Interrupt on MR1
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
+#define CTIMER_MCR_MR1R_MASK (0x10U)
+#define CTIMER_MCR_MR1R_SHIFT (4U)
+/*! MR1R - Reset on MR1
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
+#define CTIMER_MCR_MR1S_MASK (0x20U)
+#define CTIMER_MCR_MR1S_SHIFT (5U)
+/*! MR1S - Stop on MR1
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
+#define CTIMER_MCR_MR2I_MASK (0x40U)
+#define CTIMER_MCR_MR2I_SHIFT (6U)
+/*! MR2I - Interrupt on MR2
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
+#define CTIMER_MCR_MR2R_MASK (0x80U)
+#define CTIMER_MCR_MR2R_SHIFT (7U)
+/*! MR2R - Reset on MR2
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
+#define CTIMER_MCR_MR2S_MASK (0x100U)
+#define CTIMER_MCR_MR2S_SHIFT (8U)
+/*! MR2S - Stop on MR2
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
+#define CTIMER_MCR_MR3I_MASK (0x200U)
+#define CTIMER_MCR_MR3I_SHIFT (9U)
+/*! MR3I - Interrupt on MR3
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
+#define CTIMER_MCR_MR3R_MASK (0x400U)
+#define CTIMER_MCR_MR3R_SHIFT (10U)
+/*! MR3R - Reset on MR3
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
+#define CTIMER_MCR_MR3S_MASK (0x800U)
+#define CTIMER_MCR_MR3S_SHIFT (11U)
+/*! MR3S - Stop on MR3
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
+#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
+#define CTIMER_MCR_MR0RL_SHIFT (24U)
+/*! MR0RL - Reload MR0
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
+#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
+#define CTIMER_MCR_MR1RL_SHIFT (25U)
+/*! MR1RL - Reload MR1
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
+#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
+#define CTIMER_MCR_MR2RL_SHIFT (26U)
+/*! MR2RL - Reload MR2
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
+#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
+#define CTIMER_MCR_MR3RL_SHIFT (27U)
+/*! MR3RL - Reload MR3
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
+/*! @} */
+
+/*! @name MR - Match Register */
+/*! @{ */
+#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
+#define CTIMER_MR_MATCH_SHIFT (0U)
+/*! MATCH - Timer counter match value.
+ */
+#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
+/*! @} */
+
+/* The count of CTIMER_MR */
+#define CTIMER_MR_COUNT (4U)
+
+/*! @name CCR - Capture Control Register */
+/*! @{ */
+#define CTIMER_CCR_CAP0RE_MASK (0x1U)
+#define CTIMER_CCR_CAP0RE_SHIFT (0U)
+/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
+#define CTIMER_CCR_CAP0FE_MASK (0x2U)
+#define CTIMER_CCR_CAP0FE_SHIFT (1U)
+/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
+#define CTIMER_CCR_CAP0I_MASK (0x4U)
+#define CTIMER_CCR_CAP0I_SHIFT (2U)
+/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
+#define CTIMER_CCR_CAP1RE_MASK (0x8U)
+#define CTIMER_CCR_CAP1RE_SHIFT (3U)
+/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
+#define CTIMER_CCR_CAP1FE_MASK (0x10U)
+#define CTIMER_CCR_CAP1FE_SHIFT (4U)
+/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
+#define CTIMER_CCR_CAP1I_MASK (0x20U)
+#define CTIMER_CCR_CAP1I_SHIFT (5U)
+/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
+#define CTIMER_CCR_CAP2RE_MASK (0x40U)
+#define CTIMER_CCR_CAP2RE_SHIFT (6U)
+/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
+#define CTIMER_CCR_CAP2FE_MASK (0x80U)
+#define CTIMER_CCR_CAP2FE_SHIFT (7U)
+/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
+#define CTIMER_CCR_CAP2I_MASK (0x100U)
+#define CTIMER_CCR_CAP2I_SHIFT (8U)
+/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
+#define CTIMER_CCR_CAP3RE_MASK (0x200U)
+#define CTIMER_CCR_CAP3RE_SHIFT (9U)
+/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
+#define CTIMER_CCR_CAP3FE_MASK (0x400U)
+#define CTIMER_CCR_CAP3FE_SHIFT (10U)
+/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
+#define CTIMER_CCR_CAP3I_MASK (0x800U)
+#define CTIMER_CCR_CAP3I_SHIFT (11U)
+/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
+/*! @} */
+
+/*! @name CR - Capture Register */
+/*! @{ */
+#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
+#define CTIMER_CR_CAP_SHIFT (0U)
+/*! CAP - Timer counter capture value.
+ */
+#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
+/*! @} */
+
+/* The count of CTIMER_CR */
+#define CTIMER_CR_COUNT (4U)
+
+/*! @name EMR - External Match Register */
+/*! @{ */
+#define CTIMER_EMR_EM0_MASK (0x1U)
+#define CTIMER_EMR_EM0_SHIFT (0U)
+/*! EM0 - External Match 0
+ */
+#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
+#define CTIMER_EMR_EM1_MASK (0x2U)
+#define CTIMER_EMR_EM1_SHIFT (1U)
+/*! EM1 - External Match 1
+ */
+#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
+#define CTIMER_EMR_EM2_MASK (0x4U)
+#define CTIMER_EMR_EM2_SHIFT (2U)
+/*! EM2 - External Match 2
+ */
+#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
+#define CTIMER_EMR_EM3_MASK (0x8U)
+#define CTIMER_EMR_EM3_SHIFT (3U)
+/*! EM3 - External Match 3
+ */
+#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
+#define CTIMER_EMR_EMC0_MASK (0x30U)
+#define CTIMER_EMR_EMC0_SHIFT (4U)
+/*! EMC0 - External Match Control 0
+ * 0b00..Do Nothing.
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
+#define CTIMER_EMR_EMC1_MASK (0xC0U)
+#define CTIMER_EMR_EMC1_SHIFT (6U)
+/*! EMC1 - External Match Control 1
+ * 0b00..Do Nothing
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
+#define CTIMER_EMR_EMC2_MASK (0x300U)
+#define CTIMER_EMR_EMC2_SHIFT (8U)
+/*! EMC2 - External Match Control 2
+ * 0b00..Do Nothing.
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
+#define CTIMER_EMR_EMC3_MASK (0xC00U)
+#define CTIMER_EMR_EMC3_SHIFT (10U)
+/*! EMC3 - External Match Control 3
+ * 0b00..Do Nothing.
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
+/*! @} */
+
+/*! @name CTCR - Count Control Register */
+/*! @{ */
+#define CTIMER_CTCR_CTMODE_MASK (0x3U)
+#define CTIMER_CTCR_CTMODE_SHIFT (0U)
+/*! CTMODE - The Count Control Register (CTCR) is used to select between Timer and Counter mode, and
+ * in Counter mode to select the pin and edge(s) for counting.
+ * 0b00..Timer Mode
+ * 0b01..Counter Mode rising edge
+ * 0b10..Counter Mode falling edge
+ * 0b11..Counter Mode dual edge
+ */
+#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
+#define CTIMER_CTCR_CINSEL_MASK (0xCU)
+#define CTIMER_CTCR_CINSEL_SHIFT (2U)
+/*! CINSEL - Count Input Select
+ * 0b00..Channel 0. CAPn.0 for CTIMERn
+ * 0b01..Channel 1. CAPn.1 for CTIMERn
+ * 0b10..Channel 2. CAPn.2 for CTIMERn
+ * 0b11..Channel 3. CAPn.3 for CTIMERn
+ */
+#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
+#define CTIMER_CTCR_ENCC_MASK (0x10U)
+#define CTIMER_CTCR_ENCC_SHIFT (4U)
+#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
+#define CTIMER_CTCR_SELCC_MASK (0xE0U)
+#define CTIMER_CTCR_SELCC_SHIFT (5U)
+/*! SELCC - Edge select
+ * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
+ * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
+ * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
+ * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
+ * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
+ * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
+ */
+#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
+/*! @} */
+
+/*! @name PWMC - PWM Control Register */
+/*! @{ */
+#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
+#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
+/*! PWMEN0 - PWM mode enable for channel0.
+ * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.
+ * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
+ */
+#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
+#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
+#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
+/*! PWMEN1 - PWM mode enable for channel1.
+ * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.
+ * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
+ */
+#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
+#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
+#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
+/*! PWMEN2 - PWM mode enable for channel2.
+ * 0b0..Match. CTIMERn_MAT2 is controlled by EM2.
+ * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
+ */
+#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
+#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
+#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
+/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
+ * 0b0..Match. CTIMERn_MAT3 is controlled by EM3.
+ * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
+ */
+#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
+/*! @} */
+
+/*! @name MSR - Match Shadow Register */
+/*! @{ */
+#define CTIMER_MSR_MATCH_SHADOW_MASK (0xFFFFFFFFU)
+#define CTIMER_MSR_MATCH_SHADOW_SHIFT (0U)
+/*! MATCH_SHADOW - Timer counter match shadow value.
+ */
+#define CTIMER_MSR_MATCH_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK)
+/*! @} */
+
+/* The count of CTIMER_MSR */
+#define CTIMER_MSR_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Register_Masks */
+
+
+/* CTIMER - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral CTIMER0 base address */
+ #define CTIMER0_BASE (0x50028000u)
+ /** Peripheral CTIMER0 base address */
+ #define CTIMER0_BASE_NS (0x40028000u)
+ /** Peripheral CTIMER0 base pointer */
+ #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
+ /** Peripheral CTIMER0 base pointer */
+ #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS)
+ /** Peripheral CTIMER1 base address */
+ #define CTIMER1_BASE (0x50029000u)
+ /** Peripheral CTIMER1 base address */
+ #define CTIMER1_BASE_NS (0x40029000u)
+ /** Peripheral CTIMER1 base pointer */
+ #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
+ /** Peripheral CTIMER1 base pointer */
+ #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS)
+ /** Peripheral CTIMER2 base address */
+ #define CTIMER2_BASE (0x5002A000u)
+ /** Peripheral CTIMER2 base address */
+ #define CTIMER2_BASE_NS (0x4002A000u)
+ /** Peripheral CTIMER2 base pointer */
+ #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
+ /** Peripheral CTIMER2 base pointer */
+ #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS)
+ /** Peripheral CTIMER3 base address */
+ #define CTIMER3_BASE (0x5002B000u)
+ /** Peripheral CTIMER3 base address */
+ #define CTIMER3_BASE_NS (0x4002B000u)
+ /** Peripheral CTIMER3 base pointer */
+ #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
+ /** Peripheral CTIMER3 base pointer */
+ #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS)
+ /** Peripheral CTIMER4 base address */
+ #define CTIMER4_BASE (0x5002C000u)
+ /** Peripheral CTIMER4 base address */
+ #define CTIMER4_BASE_NS (0x4002C000u)
+ /** Peripheral CTIMER4 base pointer */
+ #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
+ /** Peripheral CTIMER4 base pointer */
+ #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS)
+ /** Array initializer of CTIMER peripheral base addresses */
+ #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
+ /** Array initializer of CTIMER peripheral base pointers */
+ #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
+ /** Array initializer of CTIMER peripheral base addresses */
+ #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS }
+ /** Array initializer of CTIMER peripheral base pointers */
+ #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS }
+#else
+ /** Peripheral CTIMER0 base address */
+ #define CTIMER0_BASE (0x40028000u)
+ /** Peripheral CTIMER0 base pointer */
+ #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
+ /** Peripheral CTIMER1 base address */
+ #define CTIMER1_BASE (0x40029000u)
+ /** Peripheral CTIMER1 base pointer */
+ #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
+ /** Peripheral CTIMER2 base address */
+ #define CTIMER2_BASE (0x4002A000u)
+ /** Peripheral CTIMER2 base pointer */
+ #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
+ /** Peripheral CTIMER3 base address */
+ #define CTIMER3_BASE (0x4002B000u)
+ /** Peripheral CTIMER3 base pointer */
+ #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
+ /** Peripheral CTIMER4 base address */
+ #define CTIMER4_BASE (0x4002C000u)
+ /** Peripheral CTIMER4 base pointer */
+ #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
+ /** Array initializer of CTIMER peripheral base addresses */
+ #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
+ /** Array initializer of CTIMER peripheral base pointers */
+ #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
+#endif
+/** Interrupt vectors for the CTIMER peripheral type */
+#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DEBUGGER_MAILBOX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DEBUGGER_MAILBOX_Peripheral_Access_Layer DEBUGGER_MAILBOX Peripheral Access Layer
+ * @{
+ */
+
+/** DEBUGGER_MAILBOX - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSW; /**< Command and status word, offset: 0x0 */
+ __IO uint32_t REQUEST; /**< Request Value, offset: 0x4 */
+ __IO uint32_t RETURN; /**< Return Value, offset: 0x8 */
+ uint8_t RESERVED_0[240];
+ __I uint32_t ID; /**< Identification, offset: 0xFC */
+} DEBUGGER_MAILBOX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DEBUGGER_MAILBOX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DEBUGGER_MAILBOX_Register_Masks DEBUGGER_MAILBOX Register Masks
+ * @{
+ */
+
+/*! @name CSW - Command and status word */
+/*! @{ */
+#define DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_MASK (0x1U)
+#define DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_SHIFT (0U)
+/*! RESYNCH_REQ - Re-synchronization Request
+ * 0b0..No Request
+ * 0b1..Request for re-synchronization
+ */
+#define DEBUGGER_MAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_MASK)
+#define DEBUGGER_MAILBOX_CSW_REQ_PENDING_MASK (0x2U)
+#define DEBUGGER_MAILBOX_CSW_REQ_PENDING_SHIFT (1U)
+/*! REQ_PENDING - Request Pending
+ * 0b0..No Request Pending
+ * 0b1..Request for Re-synchronization Pending
+ */
+#define DEBUGGER_MAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_REQ_PENDING_SHIFT)) & DEBUGGER_MAILBOX_CSW_REQ_PENDING_MASK)
+#define DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_MASK (0x4U)
+#define DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_SHIFT (2U)
+/*! DBG_OR_ERR - Debug Overrun Error
+ * 0b0..No Debug Overrun error
+ * 0b1..Debug Overrun Error. A debug overrun occurred.
+ */
+#define DEBUGGER_MAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_MASK)
+#define DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_MASK (0x8U)
+#define DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_SHIFT (3U)
+/*! AHB_OR_ERR - AHB Overrun Error
+ * 0b0..No AHB Overrun Error
+ * 0b1..AHB Overrun Error. An AHB overrun occurred.
+ */
+#define DEBUGGER_MAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_MASK)
+#define DEBUGGER_MAILBOX_CSW_SOFT_RESET_MASK (0x10U)
+#define DEBUGGER_MAILBOX_CSW_SOFT_RESET_SHIFT (4U)
+/*! SOFT_RESET - Soft Reset
+ */
+#define DEBUGGER_MAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_SOFT_RESET_SHIFT)) & DEBUGGER_MAILBOX_CSW_SOFT_RESET_MASK)
+#define DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U)
+#define DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U)
+/*! CHIP_RESET_REQ - Chip Reset Request
+ */
+#define DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_MASK)
+/*! @} */
+
+/*! @name REQUEST - Request Value */
+/*! @{ */
+#define DEBUGGER_MAILBOX_REQUEST_REQUEST_MASK (0xFFFFFFFFU)
+#define DEBUGGER_MAILBOX_REQUEST_REQUEST_SHIFT (0U)
+/*! REQUEST - Request Value
+ */
+#define DEBUGGER_MAILBOX_REQUEST_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_REQUEST_REQUEST_SHIFT)) & DEBUGGER_MAILBOX_REQUEST_REQUEST_MASK)
+/*! @} */
+
+/*! @name RETURN - Return Value */
+/*! @{ */
+#define DEBUGGER_MAILBOX_RETURN_RETURN_MASK (0xFFFFFFFFU)
+#define DEBUGGER_MAILBOX_RETURN_RETURN_SHIFT (0U)
+/*! RETURN - Return Value
+ */
+#define DEBUGGER_MAILBOX_RETURN_RETURN(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_RETURN_RETURN_SHIFT)) & DEBUGGER_MAILBOX_RETURN_RETURN_MASK)
+/*! @} */
+
+/*! @name ID - Identification */
+/*! @{ */
+#define DEBUGGER_MAILBOX_ID_ID_MASK (0xFFFFFFFFU)
+#define DEBUGGER_MAILBOX_ID_ID_SHIFT (0U)
+/*! ID - Identification Value
+ */
+#define DEBUGGER_MAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_ID_ID_SHIFT)) & DEBUGGER_MAILBOX_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group DEBUGGER_MAILBOX_Register_Masks */
+
+
+/* DEBUGGER_MAILBOX - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral DEBUGGER_MAILBOX base address */
+ #define DEBUGGER_MAILBOX_BASE (0x5010F000u)
+ /** Peripheral DEBUGGER_MAILBOX base address */
+ #define DEBUGGER_MAILBOX_BASE_NS (0x4010F000u)
+ /** Peripheral DEBUGGER_MAILBOX base pointer */
+ #define DEBUGGER_MAILBOX ((DEBUGGER_MAILBOX_Type *)DEBUGGER_MAILBOX_BASE)
+ /** Peripheral DEBUGGER_MAILBOX base pointer */
+ #define DEBUGGER_MAILBOX_NS ((DEBUGGER_MAILBOX_Type *)DEBUGGER_MAILBOX_BASE_NS)
+ /** Array initializer of DEBUGGER_MAILBOX peripheral base addresses */
+ #define DEBUGGER_MAILBOX_BASE_ADDRS { DEBUGGER_MAILBOX_BASE }
+ /** Array initializer of DEBUGGER_MAILBOX peripheral base pointers */
+ #define DEBUGGER_MAILBOX_BASE_PTRS { DEBUGGER_MAILBOX }
+ /** Array initializer of DEBUGGER_MAILBOX peripheral base addresses */
+ #define DEBUGGER_MAILBOX_BASE_ADDRS_NS { DEBUGGER_MAILBOX_BASE_NS }
+ /** Array initializer of DEBUGGER_MAILBOX peripheral base pointers */
+ #define DEBUGGER_MAILBOX_BASE_PTRS_NS { DEBUGGER_MAILBOX_NS }
+#else
+ /** Peripheral DEBUGGER_MAILBOX base address */
+ #define DEBUGGER_MAILBOX_BASE (0x4010F000u)
+ /** Peripheral DEBUGGER_MAILBOX base pointer */
+ #define DEBUGGER_MAILBOX ((DEBUGGER_MAILBOX_Type *)DEBUGGER_MAILBOX_BASE)
+ /** Array initializer of DEBUGGER_MAILBOX peripheral base addresses */
+ #define DEBUGGER_MAILBOX_BASE_ADDRS { DEBUGGER_MAILBOX_BASE }
+ /** Array initializer of DEBUGGER_MAILBOX peripheral base pointers */
+ #define DEBUGGER_MAILBOX_BASE_PTRS { DEBUGGER_MAILBOX }
+#endif
+
+/*!
+ * @}
+ */ /* end of group DEBUGGER_MAILBOX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< DMA control, offset: 0x0 */
+ __I uint32_t INTSTAT; /**< Interrupt status, offset: 0x4 */
+ __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table, offset: 0x8 */
+ uint8_t RESERVED_0[20];
+ struct { /* offset: 0x20, array step: 0x60 */
+ __IO uint32_t ENABLESET; /**< Channel Enable read and set for all DMA channels, array offset: 0x20, array step: 0x60 */
+ __IO uint32_t ENABLESET1; /**< Channel Enable read and set for all DMA channels, array offset: 0x24, array step: 0x60 */
+ __IO uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels, array offset: 0x28, array step: 0x60 */
+ __IO uint32_t ENABLECLR1; /**< Channel Enable Clear for all DMA channels, array offset: 0x2C, array step: 0x60 */
+ __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels, array offset: 0x30, array step: 0x60 */
+ __I uint32_t ACTIVE1; /**< Channel Active status for all DMA channels, array offset: 0x34, array step: 0x60 */
+ __I uint32_t BUSY; /**< Channel Busy status for all DMA channels, array offset: 0x38, array step: 0x60 */
+ __I uint32_t BUSY1; /**< Channel Busy status for all DMA channels, array offset: 0x3C, array step: 0x60 */
+ __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels, array offset: 0x40, array step: 0x60 */
+ __IO uint32_t ERRINT1; /**< Error Interrupt status for all DMA channels, array offset: 0x44, array step: 0x60 */
+ __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels, array offset: 0x48, array step: 0x60 */
+ __IO uint32_t INTENSET1; /**< Interrupt Enable read and Set for all DMA channels, array offset: 0x4C, array step: 0x60 */
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels, array offset: 0x50, array step: 0x60 */
+ __O uint32_t INTENCLR1; /**< Interrupt Enable Clear for all DMA channels, array offset: 0x54, array step: 0x60 */
+ __IO uint32_t INTA; /**< Interrupt A status for all DMA channels, array offset: 0x58, array step: 0x60 */
+ __IO uint32_t INTA1; /**< Interrupt A status for all DMA channels, array offset: 0x5C, array step: 0x60 */
+ __IO uint32_t INTB; /**< Interrupt B status for all DMA channels, array offset: 0x60, array step: 0x60 */
+ __IO uint32_t INTB1; /**< Interrupt B status for all DMA channels, array offset: 0x64, array step: 0x60 */
+ __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels, array offset: 0x68, array step: 0x60 */
+ __O uint32_t SETVALID1; /**< Set ValidPending control bits for all DMA channels, array offset: 0x6C, array step: 0x60 */
+ __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels, array offset: 0x70, array step: 0x60 */
+ __O uint32_t SETTRIG1; /**< Set Trigger control bits for all DMA channels, array offset: 0x74, array step: 0x60 */
+ __O uint32_t ABORT; /**< Channel Abort control for all DMA channels, array offset: 0x78, array step: 0x60 */
+ __O uint32_t ABORT1; /**< Channel Abort control for all DMA channels, array offset: 0x7C, array step: 0x60 */
+ } COMMON[1];
+ uint8_t RESERVED_1[896];
+ struct { /* offset: 0x400, array step: 0x10 */
+ __IO uint32_t CFG; /**< Configuration register for DMA channel, array offset: 0x400, array step: 0x10 */
+ __I uint32_t CTLSTAT; /**< Control and status register for DMA channel, array offset: 0x404, array step: 0x10 */
+ __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel, array offset: 0x408, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } CHANNEL[37];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CTRL - DMA control */
+/*! @{ */
+#define DMA_CTRL_ENABLE_MASK (0x1U)
+#define DMA_CTRL_ENABLE_SHIFT (0U)
+/*! ENABLE - DMA controller master enable.
+ * 0b0..DMA controller is disabled.
+ * 0b1..Enabled.
+ */
+#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt status */
+/*! @{ */
+#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
+#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
+/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
+ * 0b0..No enabled interrupts are pending.
+ * 0b1..At least one enabled interrupt is pending.
+ */
+#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
+#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
+#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
+/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
+ * 0b0..No error interrupts are pending.
+ * 0b1..At least one error interrupt is pending.
+ */
+#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
+/*! @} */
+
+/*! @name SRAMBASE - SRAM address of the channel configuration table */
+/*! @{ */
+#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
+#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
+/*! OFFSET - Offset
+ */
+#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
+/*! @} */
+
+/*! @name COMMON_ENABLESET - Channel Enable read and set for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_ENABLESET_ENABLE0_MASK (0x1U)
+#define DMA_COMMON_ENABLESET_ENABLE0_SHIFT (0U)
+/*! ENABLE0 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE0_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE0_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE1_MASK (0x2U)
+#define DMA_COMMON_ENABLESET_ENABLE1_SHIFT (1U)
+/*! ENABLE1 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE1_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE1_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE2_MASK (0x4U)
+#define DMA_COMMON_ENABLESET_ENABLE2_SHIFT (2U)
+/*! ENABLE2 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE2_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE2_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE3_MASK (0x8U)
+#define DMA_COMMON_ENABLESET_ENABLE3_SHIFT (3U)
+/*! ENABLE3 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE3_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE3_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE4_MASK (0x10U)
+#define DMA_COMMON_ENABLESET_ENABLE4_SHIFT (4U)
+/*! ENABLE4 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE4_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE4_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE5_MASK (0x20U)
+#define DMA_COMMON_ENABLESET_ENABLE5_SHIFT (5U)
+/*! ENABLE5 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE5_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE5_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE6_MASK (0x40U)
+#define DMA_COMMON_ENABLESET_ENABLE6_SHIFT (6U)
+/*! ENABLE6 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE6_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE6_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE7_MASK (0x80U)
+#define DMA_COMMON_ENABLESET_ENABLE7_SHIFT (7U)
+/*! ENABLE7 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE7_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE7_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE8_MASK (0x100U)
+#define DMA_COMMON_ENABLESET_ENABLE8_SHIFT (8U)
+/*! ENABLE8 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE8_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE8_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE9_MASK (0x200U)
+#define DMA_COMMON_ENABLESET_ENABLE9_SHIFT (9U)
+/*! ENABLE9 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE9_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE9_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE10_MASK (0x400U)
+#define DMA_COMMON_ENABLESET_ENABLE10_SHIFT (10U)
+/*! ENABLE10 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE10_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE10_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE11_MASK (0x800U)
+#define DMA_COMMON_ENABLESET_ENABLE11_SHIFT (11U)
+/*! ENABLE11 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE11_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE11_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE12_MASK (0x1000U)
+#define DMA_COMMON_ENABLESET_ENABLE12_SHIFT (12U)
+/*! ENABLE12 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE12_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE12_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE13_MASK (0x2000U)
+#define DMA_COMMON_ENABLESET_ENABLE13_SHIFT (13U)
+/*! ENABLE13 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE13_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE13_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE14_MASK (0x4000U)
+#define DMA_COMMON_ENABLESET_ENABLE14_SHIFT (14U)
+/*! ENABLE14 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE14_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE14_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE15_MASK (0x8000U)
+#define DMA_COMMON_ENABLESET_ENABLE15_SHIFT (15U)
+/*! ENABLE15 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE15_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE15_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE16_MASK (0x10000U)
+#define DMA_COMMON_ENABLESET_ENABLE16_SHIFT (16U)
+/*! ENABLE16 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE16_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE16_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE17_MASK (0x20000U)
+#define DMA_COMMON_ENABLESET_ENABLE17_SHIFT (17U)
+/*! ENABLE17 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE17_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE17_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE18_MASK (0x40000U)
+#define DMA_COMMON_ENABLESET_ENABLE18_SHIFT (18U)
+/*! ENABLE18 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE18_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE18_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE19_MASK (0x80000U)
+#define DMA_COMMON_ENABLESET_ENABLE19_SHIFT (19U)
+/*! ENABLE19 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE19_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE19_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE20_MASK (0x100000U)
+#define DMA_COMMON_ENABLESET_ENABLE20_SHIFT (20U)
+/*! ENABLE20 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE20_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE20_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE21_MASK (0x200000U)
+#define DMA_COMMON_ENABLESET_ENABLE21_SHIFT (21U)
+/*! ENABLE21 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE21_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE21_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE22_MASK (0x400000U)
+#define DMA_COMMON_ENABLESET_ENABLE22_SHIFT (22U)
+/*! ENABLE22 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE22_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE22_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE23_MASK (0x800000U)
+#define DMA_COMMON_ENABLESET_ENABLE23_SHIFT (23U)
+/*! ENABLE23 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE23_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE23_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE24_MASK (0x1000000U)
+#define DMA_COMMON_ENABLESET_ENABLE24_SHIFT (24U)
+/*! ENABLE24 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE24_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE24_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE25_MASK (0x2000000U)
+#define DMA_COMMON_ENABLESET_ENABLE25_SHIFT (25U)
+/*! ENABLE25 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE25_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE25_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE26_MASK (0x4000000U)
+#define DMA_COMMON_ENABLESET_ENABLE26_SHIFT (26U)
+/*! ENABLE26 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE26_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE26_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE27_MASK (0x8000000U)
+#define DMA_COMMON_ENABLESET_ENABLE27_SHIFT (27U)
+/*! ENABLE27 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE27_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE27_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE28_MASK (0x10000000U)
+#define DMA_COMMON_ENABLESET_ENABLE28_SHIFT (28U)
+/*! ENABLE28 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE28_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE28_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE29_MASK (0x20000000U)
+#define DMA_COMMON_ENABLESET_ENABLE29_SHIFT (29U)
+/*! ENABLE29 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE29_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE29_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE30_MASK (0x40000000U)
+#define DMA_COMMON_ENABLESET_ENABLE30_SHIFT (30U)
+/*! ENABLE30 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE30_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE30_MASK)
+#define DMA_COMMON_ENABLESET_ENABLE31_MASK (0x80000000U)
+#define DMA_COMMON_ENABLESET_ENABLE31_SHIFT (31U)
+/*! ENABLE31 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENABLE31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE31_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLESET */
+#define DMA_COMMON_ENABLESET_COUNT (1U)
+
+/*! @name COMMON_ENABLESET1 - Channel Enable read and set for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_ENABLESET1_ENABLE32_MASK (0x1U)
+#define DMA_COMMON_ENABLESET1_ENABLE32_SHIFT (0U)
+/*! ENABLE32 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET1_ENABLE32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE32_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE32_MASK)
+#define DMA_COMMON_ENABLESET1_ENABLE33_MASK (0x2U)
+#define DMA_COMMON_ENABLESET1_ENABLE33_SHIFT (1U)
+/*! ENABLE33 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET1_ENABLE33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE33_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE33_MASK)
+#define DMA_COMMON_ENABLESET1_ENABLE34_MASK (0x4U)
+#define DMA_COMMON_ENABLESET1_ENABLE34_SHIFT (2U)
+/*! ENABLE34 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET1_ENABLE34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE34_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE34_MASK)
+#define DMA_COMMON_ENABLESET1_ENABLE35_MASK (0x8U)
+#define DMA_COMMON_ENABLESET1_ENABLE35_SHIFT (3U)
+/*! ENABLE35 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET1_ENABLE35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE35_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE35_MASK)
+#define DMA_COMMON_ENABLESET1_ENABLE36_MASK (0x10U)
+#define DMA_COMMON_ENABLESET1_ENABLE36_SHIFT (4U)
+/*! ENABLE36 - Enable for DMA channel
+ * 0b0..DMA channel is disabled.
+ * 0b1..DMA channel is enabled.
+ */
+#define DMA_COMMON_ENABLESET1_ENABLE36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE36_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE36_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLESET1 */
+#define DMA_COMMON_ENABLESET1_COUNT (1U)
+
+/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_ENABLECLR_CLR0_MASK (0x1U)
+#define DMA_COMMON_ENABLECLR_CLR0_SHIFT (0U)
+/*! CLR0 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR0_SHIFT)) & DMA_COMMON_ENABLECLR_CLR0_MASK)
+#define DMA_COMMON_ENABLECLR_CLR1_MASK (0x2U)
+#define DMA_COMMON_ENABLECLR_CLR1_SHIFT (1U)
+/*! CLR1 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR1_SHIFT)) & DMA_COMMON_ENABLECLR_CLR1_MASK)
+#define DMA_COMMON_ENABLECLR_CLR2_MASK (0x4U)
+#define DMA_COMMON_ENABLECLR_CLR2_SHIFT (2U)
+/*! CLR2 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR2_SHIFT)) & DMA_COMMON_ENABLECLR_CLR2_MASK)
+#define DMA_COMMON_ENABLECLR_CLR3_MASK (0x8U)
+#define DMA_COMMON_ENABLECLR_CLR3_SHIFT (3U)
+/*! CLR3 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR3_SHIFT)) & DMA_COMMON_ENABLECLR_CLR3_MASK)
+#define DMA_COMMON_ENABLECLR_CLR4_MASK (0x10U)
+#define DMA_COMMON_ENABLECLR_CLR4_SHIFT (4U)
+/*! CLR4 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR4_SHIFT)) & DMA_COMMON_ENABLECLR_CLR4_MASK)
+#define DMA_COMMON_ENABLECLR_CLR5_MASK (0x20U)
+#define DMA_COMMON_ENABLECLR_CLR5_SHIFT (5U)
+/*! CLR5 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR5_SHIFT)) & DMA_COMMON_ENABLECLR_CLR5_MASK)
+#define DMA_COMMON_ENABLECLR_CLR6_MASK (0x40U)
+#define DMA_COMMON_ENABLECLR_CLR6_SHIFT (6U)
+/*! CLR6 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR6_SHIFT)) & DMA_COMMON_ENABLECLR_CLR6_MASK)
+#define DMA_COMMON_ENABLECLR_CLR7_MASK (0x80U)
+#define DMA_COMMON_ENABLECLR_CLR7_SHIFT (7U)
+/*! CLR7 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR7_SHIFT)) & DMA_COMMON_ENABLECLR_CLR7_MASK)
+#define DMA_COMMON_ENABLECLR_CLR8_MASK (0x100U)
+#define DMA_COMMON_ENABLECLR_CLR8_SHIFT (8U)
+/*! CLR8 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR8_SHIFT)) & DMA_COMMON_ENABLECLR_CLR8_MASK)
+#define DMA_COMMON_ENABLECLR_CLR9_MASK (0x200U)
+#define DMA_COMMON_ENABLECLR_CLR9_SHIFT (9U)
+/*! CLR9 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR9_SHIFT)) & DMA_COMMON_ENABLECLR_CLR9_MASK)
+#define DMA_COMMON_ENABLECLR_CLR10_MASK (0x400U)
+#define DMA_COMMON_ENABLECLR_CLR10_SHIFT (10U)
+/*! CLR10 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR10_SHIFT)) & DMA_COMMON_ENABLECLR_CLR10_MASK)
+#define DMA_COMMON_ENABLECLR_CLR11_MASK (0x800U)
+#define DMA_COMMON_ENABLECLR_CLR11_SHIFT (11U)
+/*! CLR11 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR11_SHIFT)) & DMA_COMMON_ENABLECLR_CLR11_MASK)
+#define DMA_COMMON_ENABLECLR_CLR12_MASK (0x1000U)
+#define DMA_COMMON_ENABLECLR_CLR12_SHIFT (12U)
+/*! CLR12 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR12_SHIFT)) & DMA_COMMON_ENABLECLR_CLR12_MASK)
+#define DMA_COMMON_ENABLECLR_CLR13_MASK (0x2000U)
+#define DMA_COMMON_ENABLECLR_CLR13_SHIFT (13U)
+/*! CLR13 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR13_SHIFT)) & DMA_COMMON_ENABLECLR_CLR13_MASK)
+#define DMA_COMMON_ENABLECLR_CLR14_MASK (0x4000U)
+#define DMA_COMMON_ENABLECLR_CLR14_SHIFT (14U)
+/*! CLR14 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR14_SHIFT)) & DMA_COMMON_ENABLECLR_CLR14_MASK)
+#define DMA_COMMON_ENABLECLR_CLR15_MASK (0x8000U)
+#define DMA_COMMON_ENABLECLR_CLR15_SHIFT (15U)
+/*! CLR15 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR15_SHIFT)) & DMA_COMMON_ENABLECLR_CLR15_MASK)
+#define DMA_COMMON_ENABLECLR_CLR16_MASK (0x10000U)
+#define DMA_COMMON_ENABLECLR_CLR16_SHIFT (16U)
+/*! CLR16 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR16_SHIFT)) & DMA_COMMON_ENABLECLR_CLR16_MASK)
+#define DMA_COMMON_ENABLECLR_CLR17_MASK (0x20000U)
+#define DMA_COMMON_ENABLECLR_CLR17_SHIFT (17U)
+/*! CLR17 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR17_SHIFT)) & DMA_COMMON_ENABLECLR_CLR17_MASK)
+#define DMA_COMMON_ENABLECLR_CLR18_MASK (0x40000U)
+#define DMA_COMMON_ENABLECLR_CLR18_SHIFT (18U)
+/*! CLR18 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR18_SHIFT)) & DMA_COMMON_ENABLECLR_CLR18_MASK)
+#define DMA_COMMON_ENABLECLR_CLR19_MASK (0x80000U)
+#define DMA_COMMON_ENABLECLR_CLR19_SHIFT (19U)
+/*! CLR19 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR19_SHIFT)) & DMA_COMMON_ENABLECLR_CLR19_MASK)
+#define DMA_COMMON_ENABLECLR_CLR20_MASK (0x100000U)
+#define DMA_COMMON_ENABLECLR_CLR20_SHIFT (20U)
+/*! CLR20 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR20_SHIFT)) & DMA_COMMON_ENABLECLR_CLR20_MASK)
+#define DMA_COMMON_ENABLECLR_CLR21_MASK (0x200000U)
+#define DMA_COMMON_ENABLECLR_CLR21_SHIFT (21U)
+/*! CLR21 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR21_SHIFT)) & DMA_COMMON_ENABLECLR_CLR21_MASK)
+#define DMA_COMMON_ENABLECLR_CLR22_MASK (0x400000U)
+#define DMA_COMMON_ENABLECLR_CLR22_SHIFT (22U)
+/*! CLR22 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR22_SHIFT)) & DMA_COMMON_ENABLECLR_CLR22_MASK)
+#define DMA_COMMON_ENABLECLR_CLR23_MASK (0x800000U)
+#define DMA_COMMON_ENABLECLR_CLR23_SHIFT (23U)
+/*! CLR23 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR23_SHIFT)) & DMA_COMMON_ENABLECLR_CLR23_MASK)
+#define DMA_COMMON_ENABLECLR_CLR24_MASK (0x1000000U)
+#define DMA_COMMON_ENABLECLR_CLR24_SHIFT (24U)
+/*! CLR24 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR24_SHIFT)) & DMA_COMMON_ENABLECLR_CLR24_MASK)
+#define DMA_COMMON_ENABLECLR_CLR25_MASK (0x2000000U)
+#define DMA_COMMON_ENABLECLR_CLR25_SHIFT (25U)
+/*! CLR25 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR25_SHIFT)) & DMA_COMMON_ENABLECLR_CLR25_MASK)
+#define DMA_COMMON_ENABLECLR_CLR26_MASK (0x4000000U)
+#define DMA_COMMON_ENABLECLR_CLR26_SHIFT (26U)
+/*! CLR26 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR26_SHIFT)) & DMA_COMMON_ENABLECLR_CLR26_MASK)
+#define DMA_COMMON_ENABLECLR_CLR27_MASK (0x8000000U)
+#define DMA_COMMON_ENABLECLR_CLR27_SHIFT (27U)
+/*! CLR27 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR27_SHIFT)) & DMA_COMMON_ENABLECLR_CLR27_MASK)
+#define DMA_COMMON_ENABLECLR_CLR28_MASK (0x10000000U)
+#define DMA_COMMON_ENABLECLR_CLR28_SHIFT (28U)
+/*! CLR28 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR28_SHIFT)) & DMA_COMMON_ENABLECLR_CLR28_MASK)
+#define DMA_COMMON_ENABLECLR_CLR29_MASK (0x20000000U)
+#define DMA_COMMON_ENABLECLR_CLR29_SHIFT (29U)
+/*! CLR29 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR29_SHIFT)) & DMA_COMMON_ENABLECLR_CLR29_MASK)
+#define DMA_COMMON_ENABLECLR_CLR30_MASK (0x40000000U)
+#define DMA_COMMON_ENABLECLR_CLR30_SHIFT (30U)
+/*! CLR30 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR30_SHIFT)) & DMA_COMMON_ENABLECLR_CLR30_MASK)
+#define DMA_COMMON_ENABLECLR_CLR31_MASK (0x80000000U)
+#define DMA_COMMON_ENABLECLR_CLR31_SHIFT (31U)
+/*! CLR31 - Writing ones to this register clears the corresponding bits in ENABLESET0.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR_CLR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR31_SHIFT)) & DMA_COMMON_ENABLECLR_CLR31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLECLR */
+#define DMA_COMMON_ENABLECLR_COUNT (1U)
+
+/*! @name COMMON_ENABLECLR1 - Channel Enable Clear for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_ENABLECLR1_CLR32_MASK (0x1U)
+#define DMA_COMMON_ENABLECLR1_CLR32_SHIFT (0U)
+/*! CLR32 - Writing ones to this register clears the corresponding bits in ENABLESET1.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR1_CLR32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR32_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR32_MASK)
+#define DMA_COMMON_ENABLECLR1_CLR33_MASK (0x2U)
+#define DMA_COMMON_ENABLECLR1_CLR33_SHIFT (1U)
+/*! CLR33 - Writing ones to this register clears the corresponding bits in ENABLESET1.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR1_CLR33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR33_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR33_MASK)
+#define DMA_COMMON_ENABLECLR1_CLR34_MASK (0x4U)
+#define DMA_COMMON_ENABLECLR1_CLR34_SHIFT (2U)
+/*! CLR34 - Writing ones to this register clears the corresponding bits in ENABLESET1.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR1_CLR34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR34_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR34_MASK)
+#define DMA_COMMON_ENABLECLR1_CLR35_MASK (0x8U)
+#define DMA_COMMON_ENABLECLR1_CLR35_SHIFT (3U)
+/*! CLR35 - Writing ones to this register clears the corresponding bits in ENABLESET1.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR1_CLR35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR35_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR35_MASK)
+#define DMA_COMMON_ENABLECLR1_CLR36_MASK (0x10U)
+#define DMA_COMMON_ENABLECLR1_CLR36_SHIFT (4U)
+/*! CLR36 - Writing ones to this register clears the corresponding bits in ENABLESET1.
+ * 0b0..No effect.
+ * 0b1..DMA channel is cleared.
+ */
+#define DMA_COMMON_ENABLECLR1_CLR36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR36_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR36_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLECLR1 */
+#define DMA_COMMON_ENABLECLR1_COUNT (1U)
+
+/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_ACTIVE_ACTIVE0_MASK (0x1U)
+#define DMA_COMMON_ACTIVE_ACTIVE0_SHIFT (0U)
+/*! ACTIVE0 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE0_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE0_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE1_MASK (0x2U)
+#define DMA_COMMON_ACTIVE_ACTIVE1_SHIFT (1U)
+/*! ACTIVE1 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE1_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE1_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE2_MASK (0x4U)
+#define DMA_COMMON_ACTIVE_ACTIVE2_SHIFT (2U)
+/*! ACTIVE2 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE2_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE2_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE3_MASK (0x8U)
+#define DMA_COMMON_ACTIVE_ACTIVE3_SHIFT (3U)
+/*! ACTIVE3 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE3_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE3_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE4_MASK (0x10U)
+#define DMA_COMMON_ACTIVE_ACTIVE4_SHIFT (4U)
+/*! ACTIVE4 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE4_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE4_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE5_MASK (0x20U)
+#define DMA_COMMON_ACTIVE_ACTIVE5_SHIFT (5U)
+/*! ACTIVE5 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE5_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE5_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE6_MASK (0x40U)
+#define DMA_COMMON_ACTIVE_ACTIVE6_SHIFT (6U)
+/*! ACTIVE6 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE6_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE6_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE7_MASK (0x80U)
+#define DMA_COMMON_ACTIVE_ACTIVE7_SHIFT (7U)
+/*! ACTIVE7 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE7_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE7_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE8_MASK (0x100U)
+#define DMA_COMMON_ACTIVE_ACTIVE8_SHIFT (8U)
+/*! ACTIVE8 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE8_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE8_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE9_MASK (0x200U)
+#define DMA_COMMON_ACTIVE_ACTIVE9_SHIFT (9U)
+/*! ACTIVE9 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE9_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE9_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE10_MASK (0x400U)
+#define DMA_COMMON_ACTIVE_ACTIVE10_SHIFT (10U)
+/*! ACTIVE10 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE10_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE10_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE11_MASK (0x800U)
+#define DMA_COMMON_ACTIVE_ACTIVE11_SHIFT (11U)
+/*! ACTIVE11 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE11_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE11_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE12_MASK (0x1000U)
+#define DMA_COMMON_ACTIVE_ACTIVE12_SHIFT (12U)
+/*! ACTIVE12 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE12_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE12_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE13_MASK (0x2000U)
+#define DMA_COMMON_ACTIVE_ACTIVE13_SHIFT (13U)
+/*! ACTIVE13 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE13_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE13_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE14_MASK (0x4000U)
+#define DMA_COMMON_ACTIVE_ACTIVE14_SHIFT (14U)
+/*! ACTIVE14 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE14_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE14_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE15_MASK (0x8000U)
+#define DMA_COMMON_ACTIVE_ACTIVE15_SHIFT (15U)
+/*! ACTIVE15 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE15_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE15_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE16_MASK (0x10000U)
+#define DMA_COMMON_ACTIVE_ACTIVE16_SHIFT (16U)
+/*! ACTIVE16 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE16_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE16_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE17_MASK (0x20000U)
+#define DMA_COMMON_ACTIVE_ACTIVE17_SHIFT (17U)
+/*! ACTIVE17 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE17_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE17_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE18_MASK (0x40000U)
+#define DMA_COMMON_ACTIVE_ACTIVE18_SHIFT (18U)
+/*! ACTIVE18 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE18_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE18_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE19_MASK (0x80000U)
+#define DMA_COMMON_ACTIVE_ACTIVE19_SHIFT (19U)
+/*! ACTIVE19 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE19_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE19_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE20_MASK (0x100000U)
+#define DMA_COMMON_ACTIVE_ACTIVE20_SHIFT (20U)
+/*! ACTIVE20 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE20_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE20_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE21_MASK (0x200000U)
+#define DMA_COMMON_ACTIVE_ACTIVE21_SHIFT (21U)
+/*! ACTIVE21 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE21_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE21_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE22_MASK (0x400000U)
+#define DMA_COMMON_ACTIVE_ACTIVE22_SHIFT (22U)
+/*! ACTIVE22 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE22_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE22_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE23_MASK (0x800000U)
+#define DMA_COMMON_ACTIVE_ACTIVE23_SHIFT (23U)
+/*! ACTIVE23 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE23_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE23_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE24_MASK (0x1000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE24_SHIFT (24U)
+/*! ACTIVE24 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE24_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE24_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE25_MASK (0x2000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE25_SHIFT (25U)
+/*! ACTIVE25 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE25_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE25_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE26_MASK (0x4000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE26_SHIFT (26U)
+/*! ACTIVE26 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE26_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE26_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE27_MASK (0x8000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE27_SHIFT (27U)
+/*! ACTIVE27 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE27_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE27_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE28_MASK (0x10000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE28_SHIFT (28U)
+/*! ACTIVE28 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE28_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE28_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE29_MASK (0x20000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE29_SHIFT (29U)
+/*! ACTIVE29 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE29_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE29_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE30_MASK (0x40000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE30_SHIFT (30U)
+/*! ACTIVE30 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE30_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE30_MASK)
+#define DMA_COMMON_ACTIVE_ACTIVE31_MASK (0x80000000U)
+#define DMA_COMMON_ACTIVE_ACTIVE31_SHIFT (31U)
+/*! ACTIVE31 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE_ACTIVE31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE31_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ACTIVE */
+#define DMA_COMMON_ACTIVE_COUNT (1U)
+
+/*! @name COMMON_ACTIVE1 - Channel Active status for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_ACTIVE1_ACTIVE32_MASK (0x1U)
+#define DMA_COMMON_ACTIVE1_ACTIVE32_SHIFT (0U)
+/*! ACTIVE32 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE1_ACTIVE32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE32_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE32_MASK)
+#define DMA_COMMON_ACTIVE1_ACTIVE33_MASK (0x2U)
+#define DMA_COMMON_ACTIVE1_ACTIVE33_SHIFT (1U)
+/*! ACTIVE33 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE1_ACTIVE33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE33_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE33_MASK)
+#define DMA_COMMON_ACTIVE1_ACTIVE34_MASK (0x4U)
+#define DMA_COMMON_ACTIVE1_ACTIVE34_SHIFT (2U)
+/*! ACTIVE34 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE1_ACTIVE34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE34_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE34_MASK)
+#define DMA_COMMON_ACTIVE1_ACTIVE35_MASK (0x8U)
+#define DMA_COMMON_ACTIVE1_ACTIVE35_SHIFT (3U)
+/*! ACTIVE35 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE1_ACTIVE35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE35_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE35_MASK)
+#define DMA_COMMON_ACTIVE1_ACTIVE36_MASK (0x10U)
+#define DMA_COMMON_ACTIVE1_ACTIVE36_SHIFT (4U)
+/*! ACTIVE36 - Active flag for DMA channel.
+ * 0b0..DMA channel is not active.
+ * 0b1..DMA channel is active.
+ */
+#define DMA_COMMON_ACTIVE1_ACTIVE36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE36_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE36_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ACTIVE1 */
+#define DMA_COMMON_ACTIVE1_COUNT (1U)
+
+/*! @name COMMON_BUSY - Channel Busy status for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_BUSY_BUSY0_MASK (0x1U)
+#define DMA_COMMON_BUSY_BUSY0_SHIFT (0U)
+/*! BUSY0 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY0_SHIFT)) & DMA_COMMON_BUSY_BUSY0_MASK)
+#define DMA_COMMON_BUSY_BUSY1_MASK (0x2U)
+#define DMA_COMMON_BUSY_BUSY1_SHIFT (1U)
+/*! BUSY1 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY1_SHIFT)) & DMA_COMMON_BUSY_BUSY1_MASK)
+#define DMA_COMMON_BUSY_BUSY2_MASK (0x4U)
+#define DMA_COMMON_BUSY_BUSY2_SHIFT (2U)
+/*! BUSY2 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY2_SHIFT)) & DMA_COMMON_BUSY_BUSY2_MASK)
+#define DMA_COMMON_BUSY_BUSY3_MASK (0x8U)
+#define DMA_COMMON_BUSY_BUSY3_SHIFT (3U)
+/*! BUSY3 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY3_SHIFT)) & DMA_COMMON_BUSY_BUSY3_MASK)
+#define DMA_COMMON_BUSY_BUSY4_MASK (0x10U)
+#define DMA_COMMON_BUSY_BUSY4_SHIFT (4U)
+/*! BUSY4 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY4_SHIFT)) & DMA_COMMON_BUSY_BUSY4_MASK)
+#define DMA_COMMON_BUSY_BUSY5_MASK (0x20U)
+#define DMA_COMMON_BUSY_BUSY5_SHIFT (5U)
+/*! BUSY5 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY5_SHIFT)) & DMA_COMMON_BUSY_BUSY5_MASK)
+#define DMA_COMMON_BUSY_BUSY6_MASK (0x40U)
+#define DMA_COMMON_BUSY_BUSY6_SHIFT (6U)
+/*! BUSY6 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY6_SHIFT)) & DMA_COMMON_BUSY_BUSY6_MASK)
+#define DMA_COMMON_BUSY_BUSY7_MASK (0x80U)
+#define DMA_COMMON_BUSY_BUSY7_SHIFT (7U)
+/*! BUSY7 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY7_SHIFT)) & DMA_COMMON_BUSY_BUSY7_MASK)
+#define DMA_COMMON_BUSY_BUSY8_MASK (0x100U)
+#define DMA_COMMON_BUSY_BUSY8_SHIFT (8U)
+/*! BUSY8 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY8_SHIFT)) & DMA_COMMON_BUSY_BUSY8_MASK)
+#define DMA_COMMON_BUSY_BUSY9_MASK (0x200U)
+#define DMA_COMMON_BUSY_BUSY9_SHIFT (9U)
+/*! BUSY9 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY9_SHIFT)) & DMA_COMMON_BUSY_BUSY9_MASK)
+#define DMA_COMMON_BUSY_BUSY10_MASK (0x400U)
+#define DMA_COMMON_BUSY_BUSY10_SHIFT (10U)
+/*! BUSY10 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY10_SHIFT)) & DMA_COMMON_BUSY_BUSY10_MASK)
+#define DMA_COMMON_BUSY_BUSY11_MASK (0x800U)
+#define DMA_COMMON_BUSY_BUSY11_SHIFT (11U)
+/*! BUSY11 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY11_SHIFT)) & DMA_COMMON_BUSY_BUSY11_MASK)
+#define DMA_COMMON_BUSY_BUSY12_MASK (0x1000U)
+#define DMA_COMMON_BUSY_BUSY12_SHIFT (12U)
+/*! BUSY12 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY12_SHIFT)) & DMA_COMMON_BUSY_BUSY12_MASK)
+#define DMA_COMMON_BUSY_BUSY13_MASK (0x2000U)
+#define DMA_COMMON_BUSY_BUSY13_SHIFT (13U)
+/*! BUSY13 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY13_SHIFT)) & DMA_COMMON_BUSY_BUSY13_MASK)
+#define DMA_COMMON_BUSY_BUSY14_MASK (0x4000U)
+#define DMA_COMMON_BUSY_BUSY14_SHIFT (14U)
+/*! BUSY14 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY14_SHIFT)) & DMA_COMMON_BUSY_BUSY14_MASK)
+#define DMA_COMMON_BUSY_BUSY15_MASK (0x8000U)
+#define DMA_COMMON_BUSY_BUSY15_SHIFT (15U)
+/*! BUSY15 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY15_SHIFT)) & DMA_COMMON_BUSY_BUSY15_MASK)
+#define DMA_COMMON_BUSY_BUSY16_MASK (0x10000U)
+#define DMA_COMMON_BUSY_BUSY16_SHIFT (16U)
+/*! BUSY16 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY16_SHIFT)) & DMA_COMMON_BUSY_BUSY16_MASK)
+#define DMA_COMMON_BUSY_BUSY17_MASK (0x20000U)
+#define DMA_COMMON_BUSY_BUSY17_SHIFT (17U)
+/*! BUSY17 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY17_SHIFT)) & DMA_COMMON_BUSY_BUSY17_MASK)
+#define DMA_COMMON_BUSY_BUSY18_MASK (0x40000U)
+#define DMA_COMMON_BUSY_BUSY18_SHIFT (18U)
+/*! BUSY18 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY18_SHIFT)) & DMA_COMMON_BUSY_BUSY18_MASK)
+#define DMA_COMMON_BUSY_BUSY19_MASK (0x80000U)
+#define DMA_COMMON_BUSY_BUSY19_SHIFT (19U)
+/*! BUSY19 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY19_SHIFT)) & DMA_COMMON_BUSY_BUSY19_MASK)
+#define DMA_COMMON_BUSY_BUSY20_MASK (0x100000U)
+#define DMA_COMMON_BUSY_BUSY20_SHIFT (20U)
+/*! BUSY20 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY20_SHIFT)) & DMA_COMMON_BUSY_BUSY20_MASK)
+#define DMA_COMMON_BUSY_BUSY21_MASK (0x200000U)
+#define DMA_COMMON_BUSY_BUSY21_SHIFT (21U)
+/*! BUSY21 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY21_SHIFT)) & DMA_COMMON_BUSY_BUSY21_MASK)
+#define DMA_COMMON_BUSY_BUSY22_MASK (0x400000U)
+#define DMA_COMMON_BUSY_BUSY22_SHIFT (22U)
+/*! BUSY22 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY22_SHIFT)) & DMA_COMMON_BUSY_BUSY22_MASK)
+#define DMA_COMMON_BUSY_BUSY23_MASK (0x800000U)
+#define DMA_COMMON_BUSY_BUSY23_SHIFT (23U)
+/*! BUSY23 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY23_SHIFT)) & DMA_COMMON_BUSY_BUSY23_MASK)
+#define DMA_COMMON_BUSY_BUSY24_MASK (0x1000000U)
+#define DMA_COMMON_BUSY_BUSY24_SHIFT (24U)
+/*! BUSY24 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY24_SHIFT)) & DMA_COMMON_BUSY_BUSY24_MASK)
+#define DMA_COMMON_BUSY_BUSY25_MASK (0x2000000U)
+#define DMA_COMMON_BUSY_BUSY25_SHIFT (25U)
+/*! BUSY25 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY25_SHIFT)) & DMA_COMMON_BUSY_BUSY25_MASK)
+#define DMA_COMMON_BUSY_BUSY26_MASK (0x4000000U)
+#define DMA_COMMON_BUSY_BUSY26_SHIFT (26U)
+/*! BUSY26 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY26_SHIFT)) & DMA_COMMON_BUSY_BUSY26_MASK)
+#define DMA_COMMON_BUSY_BUSY27_MASK (0x8000000U)
+#define DMA_COMMON_BUSY_BUSY27_SHIFT (27U)
+/*! BUSY27 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY27_SHIFT)) & DMA_COMMON_BUSY_BUSY27_MASK)
+#define DMA_COMMON_BUSY_BUSY28_MASK (0x10000000U)
+#define DMA_COMMON_BUSY_BUSY28_SHIFT (28U)
+/*! BUSY28 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY28_SHIFT)) & DMA_COMMON_BUSY_BUSY28_MASK)
+#define DMA_COMMON_BUSY_BUSY29_MASK (0x20000000U)
+#define DMA_COMMON_BUSY_BUSY29_SHIFT (29U)
+/*! BUSY29 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY29_SHIFT)) & DMA_COMMON_BUSY_BUSY29_MASK)
+#define DMA_COMMON_BUSY_BUSY30_MASK (0x40000000U)
+#define DMA_COMMON_BUSY_BUSY30_SHIFT (30U)
+/*! BUSY30 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY30_SHIFT)) & DMA_COMMON_BUSY_BUSY30_MASK)
+#define DMA_COMMON_BUSY_BUSY31_MASK (0x80000000U)
+#define DMA_COMMON_BUSY_BUSY31_SHIFT (31U)
+/*! BUSY31 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY_BUSY31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY31_SHIFT)) & DMA_COMMON_BUSY_BUSY31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_BUSY */
+#define DMA_COMMON_BUSY_COUNT (1U)
+
+/*! @name COMMON_BUSY1 - Channel Busy status for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_BUSY1_BUSY32_MASK (0x1U)
+#define DMA_COMMON_BUSY1_BUSY32_SHIFT (0U)
+/*! BUSY32 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY1_BUSY32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY32_SHIFT)) & DMA_COMMON_BUSY1_BUSY32_MASK)
+#define DMA_COMMON_BUSY1_BUSY33_MASK (0x2U)
+#define DMA_COMMON_BUSY1_BUSY33_SHIFT (1U)
+/*! BUSY33 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY1_BUSY33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY33_SHIFT)) & DMA_COMMON_BUSY1_BUSY33_MASK)
+#define DMA_COMMON_BUSY1_BUSY34_MASK (0x4U)
+#define DMA_COMMON_BUSY1_BUSY34_SHIFT (2U)
+/*! BUSY34 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY1_BUSY34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY34_SHIFT)) & DMA_COMMON_BUSY1_BUSY34_MASK)
+#define DMA_COMMON_BUSY1_BUSY35_MASK (0x8U)
+#define DMA_COMMON_BUSY1_BUSY35_SHIFT (3U)
+/*! BUSY35 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY1_BUSY35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY35_SHIFT)) & DMA_COMMON_BUSY1_BUSY35_MASK)
+#define DMA_COMMON_BUSY1_BUSY36_MASK (0x10U)
+#define DMA_COMMON_BUSY1_BUSY36_SHIFT (4U)
+/*! BUSY36 - Busy flag for DMA channel.
+ * 0b0..DMA channel is not busy.
+ * 0b1..DMA channel is busy.
+ */
+#define DMA_COMMON_BUSY1_BUSY36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY36_SHIFT)) & DMA_COMMON_BUSY1_BUSY36_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_BUSY1 */
+#define DMA_COMMON_BUSY1_COUNT (1U)
+
+/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_ERRINT_ERR0_MASK (0x1U)
+#define DMA_COMMON_ERRINT_ERR0_SHIFT (0U)
+/*! ERR0 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR0_SHIFT)) & DMA_COMMON_ERRINT_ERR0_MASK)
+#define DMA_COMMON_ERRINT_ERR1_MASK (0x2U)
+#define DMA_COMMON_ERRINT_ERR1_SHIFT (1U)
+/*! ERR1 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR1_SHIFT)) & DMA_COMMON_ERRINT_ERR1_MASK)
+#define DMA_COMMON_ERRINT_ERR2_MASK (0x4U)
+#define DMA_COMMON_ERRINT_ERR2_SHIFT (2U)
+/*! ERR2 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR2_SHIFT)) & DMA_COMMON_ERRINT_ERR2_MASK)
+#define DMA_COMMON_ERRINT_ERR3_MASK (0x8U)
+#define DMA_COMMON_ERRINT_ERR3_SHIFT (3U)
+/*! ERR3 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR3_SHIFT)) & DMA_COMMON_ERRINT_ERR3_MASK)
+#define DMA_COMMON_ERRINT_ERR4_MASK (0x10U)
+#define DMA_COMMON_ERRINT_ERR4_SHIFT (4U)
+/*! ERR4 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR4_SHIFT)) & DMA_COMMON_ERRINT_ERR4_MASK)
+#define DMA_COMMON_ERRINT_ERR5_MASK (0x20U)
+#define DMA_COMMON_ERRINT_ERR5_SHIFT (5U)
+/*! ERR5 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR5_SHIFT)) & DMA_COMMON_ERRINT_ERR5_MASK)
+#define DMA_COMMON_ERRINT_ERR6_MASK (0x40U)
+#define DMA_COMMON_ERRINT_ERR6_SHIFT (6U)
+/*! ERR6 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR6_SHIFT)) & DMA_COMMON_ERRINT_ERR6_MASK)
+#define DMA_COMMON_ERRINT_ERR7_MASK (0x80U)
+#define DMA_COMMON_ERRINT_ERR7_SHIFT (7U)
+/*! ERR7 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR7_SHIFT)) & DMA_COMMON_ERRINT_ERR7_MASK)
+#define DMA_COMMON_ERRINT_ERR8_MASK (0x100U)
+#define DMA_COMMON_ERRINT_ERR8_SHIFT (8U)
+/*! ERR8 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR8_SHIFT)) & DMA_COMMON_ERRINT_ERR8_MASK)
+#define DMA_COMMON_ERRINT_ERR9_MASK (0x200U)
+#define DMA_COMMON_ERRINT_ERR9_SHIFT (9U)
+/*! ERR9 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR9_SHIFT)) & DMA_COMMON_ERRINT_ERR9_MASK)
+#define DMA_COMMON_ERRINT_ERR10_MASK (0x400U)
+#define DMA_COMMON_ERRINT_ERR10_SHIFT (10U)
+/*! ERR10 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR10_SHIFT)) & DMA_COMMON_ERRINT_ERR10_MASK)
+#define DMA_COMMON_ERRINT_ERR11_MASK (0x800U)
+#define DMA_COMMON_ERRINT_ERR11_SHIFT (11U)
+/*! ERR11 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR11_SHIFT)) & DMA_COMMON_ERRINT_ERR11_MASK)
+#define DMA_COMMON_ERRINT_ERR12_MASK (0x1000U)
+#define DMA_COMMON_ERRINT_ERR12_SHIFT (12U)
+/*! ERR12 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR12_SHIFT)) & DMA_COMMON_ERRINT_ERR12_MASK)
+#define DMA_COMMON_ERRINT_ERR13_MASK (0x2000U)
+#define DMA_COMMON_ERRINT_ERR13_SHIFT (13U)
+/*! ERR13 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR13_SHIFT)) & DMA_COMMON_ERRINT_ERR13_MASK)
+#define DMA_COMMON_ERRINT_ERR14_MASK (0x4000U)
+#define DMA_COMMON_ERRINT_ERR14_SHIFT (14U)
+/*! ERR14 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR14_SHIFT)) & DMA_COMMON_ERRINT_ERR14_MASK)
+#define DMA_COMMON_ERRINT_ERR15_MASK (0x8000U)
+#define DMA_COMMON_ERRINT_ERR15_SHIFT (15U)
+/*! ERR15 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR15_SHIFT)) & DMA_COMMON_ERRINT_ERR15_MASK)
+#define DMA_COMMON_ERRINT_ERR16_MASK (0x10000U)
+#define DMA_COMMON_ERRINT_ERR16_SHIFT (16U)
+/*! ERR16 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR16_SHIFT)) & DMA_COMMON_ERRINT_ERR16_MASK)
+#define DMA_COMMON_ERRINT_ERR17_MASK (0x20000U)
+#define DMA_COMMON_ERRINT_ERR17_SHIFT (17U)
+/*! ERR17 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR17_SHIFT)) & DMA_COMMON_ERRINT_ERR17_MASK)
+#define DMA_COMMON_ERRINT_ERR18_MASK (0x40000U)
+#define DMA_COMMON_ERRINT_ERR18_SHIFT (18U)
+/*! ERR18 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR18_SHIFT)) & DMA_COMMON_ERRINT_ERR18_MASK)
+#define DMA_COMMON_ERRINT_ERR19_MASK (0x80000U)
+#define DMA_COMMON_ERRINT_ERR19_SHIFT (19U)
+/*! ERR19 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR19_SHIFT)) & DMA_COMMON_ERRINT_ERR19_MASK)
+#define DMA_COMMON_ERRINT_ERR20_MASK (0x100000U)
+#define DMA_COMMON_ERRINT_ERR20_SHIFT (20U)
+/*! ERR20 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR20_SHIFT)) & DMA_COMMON_ERRINT_ERR20_MASK)
+#define DMA_COMMON_ERRINT_ERR21_MASK (0x200000U)
+#define DMA_COMMON_ERRINT_ERR21_SHIFT (21U)
+/*! ERR21 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR21_SHIFT)) & DMA_COMMON_ERRINT_ERR21_MASK)
+#define DMA_COMMON_ERRINT_ERR22_MASK (0x400000U)
+#define DMA_COMMON_ERRINT_ERR22_SHIFT (22U)
+/*! ERR22 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR22_SHIFT)) & DMA_COMMON_ERRINT_ERR22_MASK)
+#define DMA_COMMON_ERRINT_ERR23_MASK (0x800000U)
+#define DMA_COMMON_ERRINT_ERR23_SHIFT (23U)
+/*! ERR23 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR23_SHIFT)) & DMA_COMMON_ERRINT_ERR23_MASK)
+#define DMA_COMMON_ERRINT_ERR24_MASK (0x1000000U)
+#define DMA_COMMON_ERRINT_ERR24_SHIFT (24U)
+/*! ERR24 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR24_SHIFT)) & DMA_COMMON_ERRINT_ERR24_MASK)
+#define DMA_COMMON_ERRINT_ERR25_MASK (0x2000000U)
+#define DMA_COMMON_ERRINT_ERR25_SHIFT (25U)
+/*! ERR25 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR25_SHIFT)) & DMA_COMMON_ERRINT_ERR25_MASK)
+#define DMA_COMMON_ERRINT_ERR26_MASK (0x4000000U)
+#define DMA_COMMON_ERRINT_ERR26_SHIFT (26U)
+/*! ERR26 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR26_SHIFT)) & DMA_COMMON_ERRINT_ERR26_MASK)
+#define DMA_COMMON_ERRINT_ERR27_MASK (0x8000000U)
+#define DMA_COMMON_ERRINT_ERR27_SHIFT (27U)
+/*! ERR27 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR27_SHIFT)) & DMA_COMMON_ERRINT_ERR27_MASK)
+#define DMA_COMMON_ERRINT_ERR28_MASK (0x10000000U)
+#define DMA_COMMON_ERRINT_ERR28_SHIFT (28U)
+/*! ERR28 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR28_SHIFT)) & DMA_COMMON_ERRINT_ERR28_MASK)
+#define DMA_COMMON_ERRINT_ERR29_MASK (0x20000000U)
+#define DMA_COMMON_ERRINT_ERR29_SHIFT (29U)
+/*! ERR29 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR29_SHIFT)) & DMA_COMMON_ERRINT_ERR29_MASK)
+#define DMA_COMMON_ERRINT_ERR30_MASK (0x40000000U)
+#define DMA_COMMON_ERRINT_ERR30_SHIFT (30U)
+/*! ERR30 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR30_SHIFT)) & DMA_COMMON_ERRINT_ERR30_MASK)
+#define DMA_COMMON_ERRINT_ERR31_MASK (0x80000000U)
+#define DMA_COMMON_ERRINT_ERR31_SHIFT (31U)
+/*! ERR31 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR31_SHIFT)) & DMA_COMMON_ERRINT_ERR31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ERRINT */
+#define DMA_COMMON_ERRINT_COUNT (1U)
+
+/*! @name COMMON_ERRINT1 - Error Interrupt status for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_ERRINT1_ERR32_MASK (0x1U)
+#define DMA_COMMON_ERRINT1_ERR32_SHIFT (0U)
+/*! ERR32 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT1_ERR32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR32_SHIFT)) & DMA_COMMON_ERRINT1_ERR32_MASK)
+#define DMA_COMMON_ERRINT1_ERR33_MASK (0x2U)
+#define DMA_COMMON_ERRINT1_ERR33_SHIFT (1U)
+/*! ERR33 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT1_ERR33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR33_SHIFT)) & DMA_COMMON_ERRINT1_ERR33_MASK)
+#define DMA_COMMON_ERRINT1_ERR34_MASK (0x4U)
+#define DMA_COMMON_ERRINT1_ERR34_SHIFT (2U)
+/*! ERR34 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT1_ERR34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR34_SHIFT)) & DMA_COMMON_ERRINT1_ERR34_MASK)
+#define DMA_COMMON_ERRINT1_ERR35_MASK (0x8U)
+#define DMA_COMMON_ERRINT1_ERR35_SHIFT (3U)
+/*! ERR35 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT1_ERR35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR35_SHIFT)) & DMA_COMMON_ERRINT1_ERR35_MASK)
+#define DMA_COMMON_ERRINT1_ERR36_MASK (0x10U)
+#define DMA_COMMON_ERRINT1_ERR36_SHIFT (4U)
+/*! ERR36 - Error Interrupt flag for DMA channel.
+ * 0b0..The Error Interrupt is not active for DMA channel.
+ * 0b1..The Error Interrupt is pending for DMA channel.
+ */
+#define DMA_COMMON_ERRINT1_ERR36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR36_SHIFT)) & DMA_COMMON_ERRINT1_ERR36_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ERRINT1 */
+#define DMA_COMMON_ERRINT1_COUNT (1U)
+
+/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_INTENSET_INTEN0_MASK (0x1U)
+#define DMA_COMMON_INTENSET_INTEN0_SHIFT (0U)
+/*! INTEN0 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN0_SHIFT)) & DMA_COMMON_INTENSET_INTEN0_MASK)
+#define DMA_COMMON_INTENSET_INTEN1_MASK (0x2U)
+#define DMA_COMMON_INTENSET_INTEN1_SHIFT (1U)
+/*! INTEN1 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN1_SHIFT)) & DMA_COMMON_INTENSET_INTEN1_MASK)
+#define DMA_COMMON_INTENSET_INTEN2_MASK (0x4U)
+#define DMA_COMMON_INTENSET_INTEN2_SHIFT (2U)
+/*! INTEN2 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN2_SHIFT)) & DMA_COMMON_INTENSET_INTEN2_MASK)
+#define DMA_COMMON_INTENSET_INTEN3_MASK (0x8U)
+#define DMA_COMMON_INTENSET_INTEN3_SHIFT (3U)
+/*! INTEN3 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN3_SHIFT)) & DMA_COMMON_INTENSET_INTEN3_MASK)
+#define DMA_COMMON_INTENSET_INTEN4_MASK (0x10U)
+#define DMA_COMMON_INTENSET_INTEN4_SHIFT (4U)
+/*! INTEN4 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN4_SHIFT)) & DMA_COMMON_INTENSET_INTEN4_MASK)
+#define DMA_COMMON_INTENSET_INTEN5_MASK (0x20U)
+#define DMA_COMMON_INTENSET_INTEN5_SHIFT (5U)
+/*! INTEN5 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN5_SHIFT)) & DMA_COMMON_INTENSET_INTEN5_MASK)
+#define DMA_COMMON_INTENSET_INTEN6_MASK (0x40U)
+#define DMA_COMMON_INTENSET_INTEN6_SHIFT (6U)
+/*! INTEN6 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN6_SHIFT)) & DMA_COMMON_INTENSET_INTEN6_MASK)
+#define DMA_COMMON_INTENSET_INTEN7_MASK (0x80U)
+#define DMA_COMMON_INTENSET_INTEN7_SHIFT (7U)
+/*! INTEN7 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN7_SHIFT)) & DMA_COMMON_INTENSET_INTEN7_MASK)
+#define DMA_COMMON_INTENSET_INTEN8_MASK (0x100U)
+#define DMA_COMMON_INTENSET_INTEN8_SHIFT (8U)
+/*! INTEN8 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN8_SHIFT)) & DMA_COMMON_INTENSET_INTEN8_MASK)
+#define DMA_COMMON_INTENSET_INTEN9_MASK (0x200U)
+#define DMA_COMMON_INTENSET_INTEN9_SHIFT (9U)
+/*! INTEN9 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN9_SHIFT)) & DMA_COMMON_INTENSET_INTEN9_MASK)
+#define DMA_COMMON_INTENSET_INTEN10_MASK (0x400U)
+#define DMA_COMMON_INTENSET_INTEN10_SHIFT (10U)
+/*! INTEN10 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN10_SHIFT)) & DMA_COMMON_INTENSET_INTEN10_MASK)
+#define DMA_COMMON_INTENSET_INTEN11_MASK (0x800U)
+#define DMA_COMMON_INTENSET_INTEN11_SHIFT (11U)
+/*! INTEN11 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN11_SHIFT)) & DMA_COMMON_INTENSET_INTEN11_MASK)
+#define DMA_COMMON_INTENSET_INTEN12_MASK (0x1000U)
+#define DMA_COMMON_INTENSET_INTEN12_SHIFT (12U)
+/*! INTEN12 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN12_SHIFT)) & DMA_COMMON_INTENSET_INTEN12_MASK)
+#define DMA_COMMON_INTENSET_INTEN13_MASK (0x2000U)
+#define DMA_COMMON_INTENSET_INTEN13_SHIFT (13U)
+/*! INTEN13 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN13_SHIFT)) & DMA_COMMON_INTENSET_INTEN13_MASK)
+#define DMA_COMMON_INTENSET_INTEN14_MASK (0x4000U)
+#define DMA_COMMON_INTENSET_INTEN14_SHIFT (14U)
+/*! INTEN14 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN14_SHIFT)) & DMA_COMMON_INTENSET_INTEN14_MASK)
+#define DMA_COMMON_INTENSET_INTEN15_MASK (0x8000U)
+#define DMA_COMMON_INTENSET_INTEN15_SHIFT (15U)
+/*! INTEN15 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN15_SHIFT)) & DMA_COMMON_INTENSET_INTEN15_MASK)
+#define DMA_COMMON_INTENSET_INTEN16_MASK (0x10000U)
+#define DMA_COMMON_INTENSET_INTEN16_SHIFT (16U)
+/*! INTEN16 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN16_SHIFT)) & DMA_COMMON_INTENSET_INTEN16_MASK)
+#define DMA_COMMON_INTENSET_INTEN17_MASK (0x20000U)
+#define DMA_COMMON_INTENSET_INTEN17_SHIFT (17U)
+/*! INTEN17 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN17_SHIFT)) & DMA_COMMON_INTENSET_INTEN17_MASK)
+#define DMA_COMMON_INTENSET_INTEN18_MASK (0x40000U)
+#define DMA_COMMON_INTENSET_INTEN18_SHIFT (18U)
+/*! INTEN18 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN18_SHIFT)) & DMA_COMMON_INTENSET_INTEN18_MASK)
+#define DMA_COMMON_INTENSET_INTEN19_MASK (0x80000U)
+#define DMA_COMMON_INTENSET_INTEN19_SHIFT (19U)
+/*! INTEN19 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN19_SHIFT)) & DMA_COMMON_INTENSET_INTEN19_MASK)
+#define DMA_COMMON_INTENSET_INTEN20_MASK (0x100000U)
+#define DMA_COMMON_INTENSET_INTEN20_SHIFT (20U)
+/*! INTEN20 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN20_SHIFT)) & DMA_COMMON_INTENSET_INTEN20_MASK)
+#define DMA_COMMON_INTENSET_INTEN21_MASK (0x200000U)
+#define DMA_COMMON_INTENSET_INTEN21_SHIFT (21U)
+/*! INTEN21 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN21_SHIFT)) & DMA_COMMON_INTENSET_INTEN21_MASK)
+#define DMA_COMMON_INTENSET_INTEN22_MASK (0x400000U)
+#define DMA_COMMON_INTENSET_INTEN22_SHIFT (22U)
+/*! INTEN22 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN22_SHIFT)) & DMA_COMMON_INTENSET_INTEN22_MASK)
+#define DMA_COMMON_INTENSET_INTEN23_MASK (0x800000U)
+#define DMA_COMMON_INTENSET_INTEN23_SHIFT (23U)
+/*! INTEN23 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN23_SHIFT)) & DMA_COMMON_INTENSET_INTEN23_MASK)
+#define DMA_COMMON_INTENSET_INTEN24_MASK (0x1000000U)
+#define DMA_COMMON_INTENSET_INTEN24_SHIFT (24U)
+/*! INTEN24 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN24_SHIFT)) & DMA_COMMON_INTENSET_INTEN24_MASK)
+#define DMA_COMMON_INTENSET_INTEN25_MASK (0x2000000U)
+#define DMA_COMMON_INTENSET_INTEN25_SHIFT (25U)
+/*! INTEN25 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN25_SHIFT)) & DMA_COMMON_INTENSET_INTEN25_MASK)
+#define DMA_COMMON_INTENSET_INTEN26_MASK (0x4000000U)
+#define DMA_COMMON_INTENSET_INTEN26_SHIFT (26U)
+/*! INTEN26 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN26_SHIFT)) & DMA_COMMON_INTENSET_INTEN26_MASK)
+#define DMA_COMMON_INTENSET_INTEN27_MASK (0x8000000U)
+#define DMA_COMMON_INTENSET_INTEN27_SHIFT (27U)
+/*! INTEN27 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN27_SHIFT)) & DMA_COMMON_INTENSET_INTEN27_MASK)
+#define DMA_COMMON_INTENSET_INTEN28_MASK (0x10000000U)
+#define DMA_COMMON_INTENSET_INTEN28_SHIFT (28U)
+/*! INTEN28 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN28_SHIFT)) & DMA_COMMON_INTENSET_INTEN28_MASK)
+#define DMA_COMMON_INTENSET_INTEN29_MASK (0x20000000U)
+#define DMA_COMMON_INTENSET_INTEN29_SHIFT (29U)
+/*! INTEN29 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN29_SHIFT)) & DMA_COMMON_INTENSET_INTEN29_MASK)
+#define DMA_COMMON_INTENSET_INTEN30_MASK (0x40000000U)
+#define DMA_COMMON_INTENSET_INTEN30_SHIFT (30U)
+/*! INTEN30 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN30_SHIFT)) & DMA_COMMON_INTENSET_INTEN30_MASK)
+#define DMA_COMMON_INTENSET_INTEN31_MASK (0x80000000U)
+#define DMA_COMMON_INTENSET_INTEN31_SHIFT (31U)
+/*! INTEN31 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN31_SHIFT)) & DMA_COMMON_INTENSET_INTEN31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENSET */
+#define DMA_COMMON_INTENSET_COUNT (1U)
+
+/*! @name COMMON_INTENSET1 - Interrupt Enable read and Set for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_INTENSET1_INTEN32_MASK (0x1U)
+#define DMA_COMMON_INTENSET1_INTEN32_SHIFT (0U)
+/*! INTEN32 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET1_INTEN32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)
+#define DMA_COMMON_INTENSET1_INTEN33_MASK (0x2U)
+#define DMA_COMMON_INTENSET1_INTEN33_SHIFT (1U)
+/*! INTEN33 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET1_INTEN33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN33_SHIFT)) & DMA_COMMON_INTENSET1_INTEN33_MASK)
+#define DMA_COMMON_INTENSET1_INTEN34_MASK (0x4U)
+#define DMA_COMMON_INTENSET1_INTEN34_SHIFT (2U)
+/*! INTEN34 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET1_INTEN34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN34_SHIFT)) & DMA_COMMON_INTENSET1_INTEN34_MASK)
+#define DMA_COMMON_INTENSET1_INTEN35_MASK (0x8U)
+#define DMA_COMMON_INTENSET1_INTEN35_SHIFT (3U)
+/*! INTEN35 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET1_INTEN35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN35_SHIFT)) & DMA_COMMON_INTENSET1_INTEN35_MASK)
+#define DMA_COMMON_INTENSET1_INTEN36_MASK (0x10U)
+#define DMA_COMMON_INTENSET1_INTEN36_SHIFT (4U)
+/*! INTEN36 - Interrupt Enable read and set for DMA channel.
+ * 0b0..The Interrupt for DMA channel is disabled.
+ * 0b1..The Interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET1_INTEN36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN36_SHIFT)) & DMA_COMMON_INTENSET1_INTEN36_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENSET1 */
+#define DMA_COMMON_INTENSET1_COUNT (1U)
+
+/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_INTENCLR_CLR0_MASK (0x1U)
+#define DMA_COMMON_INTENCLR_CLR0_SHIFT (0U)
+/*! CLR0 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR0_SHIFT)) & DMA_COMMON_INTENCLR_CLR0_MASK)
+#define DMA_COMMON_INTENCLR_CLR1_MASK (0x2U)
+#define DMA_COMMON_INTENCLR_CLR1_SHIFT (1U)
+/*! CLR1 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR1_SHIFT)) & DMA_COMMON_INTENCLR_CLR1_MASK)
+#define DMA_COMMON_INTENCLR_CLR2_MASK (0x4U)
+#define DMA_COMMON_INTENCLR_CLR2_SHIFT (2U)
+/*! CLR2 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR2_SHIFT)) & DMA_COMMON_INTENCLR_CLR2_MASK)
+#define DMA_COMMON_INTENCLR_CLR3_MASK (0x8U)
+#define DMA_COMMON_INTENCLR_CLR3_SHIFT (3U)
+/*! CLR3 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR3_SHIFT)) & DMA_COMMON_INTENCLR_CLR3_MASK)
+#define DMA_COMMON_INTENCLR_CLR4_MASK (0x10U)
+#define DMA_COMMON_INTENCLR_CLR4_SHIFT (4U)
+/*! CLR4 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR4_SHIFT)) & DMA_COMMON_INTENCLR_CLR4_MASK)
+#define DMA_COMMON_INTENCLR_CLR5_MASK (0x20U)
+#define DMA_COMMON_INTENCLR_CLR5_SHIFT (5U)
+/*! CLR5 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR5_SHIFT)) & DMA_COMMON_INTENCLR_CLR5_MASK)
+#define DMA_COMMON_INTENCLR_CLR6_MASK (0x40U)
+#define DMA_COMMON_INTENCLR_CLR6_SHIFT (6U)
+/*! CLR6 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR6_SHIFT)) & DMA_COMMON_INTENCLR_CLR6_MASK)
+#define DMA_COMMON_INTENCLR_CLR7_MASK (0x80U)
+#define DMA_COMMON_INTENCLR_CLR7_SHIFT (7U)
+/*! CLR7 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR7_SHIFT)) & DMA_COMMON_INTENCLR_CLR7_MASK)
+#define DMA_COMMON_INTENCLR_CLR8_MASK (0x100U)
+#define DMA_COMMON_INTENCLR_CLR8_SHIFT (8U)
+/*! CLR8 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR8_SHIFT)) & DMA_COMMON_INTENCLR_CLR8_MASK)
+#define DMA_COMMON_INTENCLR_CLR9_MASK (0x200U)
+#define DMA_COMMON_INTENCLR_CLR9_SHIFT (9U)
+/*! CLR9 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR9_SHIFT)) & DMA_COMMON_INTENCLR_CLR9_MASK)
+#define DMA_COMMON_INTENCLR_CLR10_MASK (0x400U)
+#define DMA_COMMON_INTENCLR_CLR10_SHIFT (10U)
+/*! CLR10 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR10_SHIFT)) & DMA_COMMON_INTENCLR_CLR10_MASK)
+#define DMA_COMMON_INTENCLR_CLR11_MASK (0x800U)
+#define DMA_COMMON_INTENCLR_CLR11_SHIFT (11U)
+/*! CLR11 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR11_SHIFT)) & DMA_COMMON_INTENCLR_CLR11_MASK)
+#define DMA_COMMON_INTENCLR_CLR12_MASK (0x1000U)
+#define DMA_COMMON_INTENCLR_CLR12_SHIFT (12U)
+/*! CLR12 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR12_SHIFT)) & DMA_COMMON_INTENCLR_CLR12_MASK)
+#define DMA_COMMON_INTENCLR_CLR13_MASK (0x2000U)
+#define DMA_COMMON_INTENCLR_CLR13_SHIFT (13U)
+/*! CLR13 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR13_SHIFT)) & DMA_COMMON_INTENCLR_CLR13_MASK)
+#define DMA_COMMON_INTENCLR_CLR14_MASK (0x4000U)
+#define DMA_COMMON_INTENCLR_CLR14_SHIFT (14U)
+/*! CLR14 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR14_SHIFT)) & DMA_COMMON_INTENCLR_CLR14_MASK)
+#define DMA_COMMON_INTENCLR_CLR15_MASK (0x8000U)
+#define DMA_COMMON_INTENCLR_CLR15_SHIFT (15U)
+/*! CLR15 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR15_SHIFT)) & DMA_COMMON_INTENCLR_CLR15_MASK)
+#define DMA_COMMON_INTENCLR_CLR16_MASK (0x10000U)
+#define DMA_COMMON_INTENCLR_CLR16_SHIFT (16U)
+/*! CLR16 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR16_SHIFT)) & DMA_COMMON_INTENCLR_CLR16_MASK)
+#define DMA_COMMON_INTENCLR_CLR17_MASK (0x20000U)
+#define DMA_COMMON_INTENCLR_CLR17_SHIFT (17U)
+/*! CLR17 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR17_SHIFT)) & DMA_COMMON_INTENCLR_CLR17_MASK)
+#define DMA_COMMON_INTENCLR_CLR18_MASK (0x40000U)
+#define DMA_COMMON_INTENCLR_CLR18_SHIFT (18U)
+/*! CLR18 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR18_SHIFT)) & DMA_COMMON_INTENCLR_CLR18_MASK)
+#define DMA_COMMON_INTENCLR_CLR19_MASK (0x80000U)
+#define DMA_COMMON_INTENCLR_CLR19_SHIFT (19U)
+/*! CLR19 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR19_SHIFT)) & DMA_COMMON_INTENCLR_CLR19_MASK)
+#define DMA_COMMON_INTENCLR_CLR20_MASK (0x100000U)
+#define DMA_COMMON_INTENCLR_CLR20_SHIFT (20U)
+/*! CLR20 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR20_SHIFT)) & DMA_COMMON_INTENCLR_CLR20_MASK)
+#define DMA_COMMON_INTENCLR_CLR21_MASK (0x200000U)
+#define DMA_COMMON_INTENCLR_CLR21_SHIFT (21U)
+/*! CLR21 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR21_SHIFT)) & DMA_COMMON_INTENCLR_CLR21_MASK)
+#define DMA_COMMON_INTENCLR_CLR22_MASK (0x400000U)
+#define DMA_COMMON_INTENCLR_CLR22_SHIFT (22U)
+/*! CLR22 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR22_SHIFT)) & DMA_COMMON_INTENCLR_CLR22_MASK)
+#define DMA_COMMON_INTENCLR_CLR23_MASK (0x800000U)
+#define DMA_COMMON_INTENCLR_CLR23_SHIFT (23U)
+/*! CLR23 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR23_SHIFT)) & DMA_COMMON_INTENCLR_CLR23_MASK)
+#define DMA_COMMON_INTENCLR_CLR24_MASK (0x1000000U)
+#define DMA_COMMON_INTENCLR_CLR24_SHIFT (24U)
+/*! CLR24 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR24_SHIFT)) & DMA_COMMON_INTENCLR_CLR24_MASK)
+#define DMA_COMMON_INTENCLR_CLR25_MASK (0x2000000U)
+#define DMA_COMMON_INTENCLR_CLR25_SHIFT (25U)
+/*! CLR25 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR25_SHIFT)) & DMA_COMMON_INTENCLR_CLR25_MASK)
+#define DMA_COMMON_INTENCLR_CLR26_MASK (0x4000000U)
+#define DMA_COMMON_INTENCLR_CLR26_SHIFT (26U)
+/*! CLR26 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR26_SHIFT)) & DMA_COMMON_INTENCLR_CLR26_MASK)
+#define DMA_COMMON_INTENCLR_CLR27_MASK (0x8000000U)
+#define DMA_COMMON_INTENCLR_CLR27_SHIFT (27U)
+/*! CLR27 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR27_SHIFT)) & DMA_COMMON_INTENCLR_CLR27_MASK)
+#define DMA_COMMON_INTENCLR_CLR28_MASK (0x10000000U)
+#define DMA_COMMON_INTENCLR_CLR28_SHIFT (28U)
+/*! CLR28 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR28_SHIFT)) & DMA_COMMON_INTENCLR_CLR28_MASK)
+#define DMA_COMMON_INTENCLR_CLR29_MASK (0x20000000U)
+#define DMA_COMMON_INTENCLR_CLR29_SHIFT (29U)
+/*! CLR29 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR29_SHIFT)) & DMA_COMMON_INTENCLR_CLR29_MASK)
+#define DMA_COMMON_INTENCLR_CLR30_MASK (0x40000000U)
+#define DMA_COMMON_INTENCLR_CLR30_SHIFT (30U)
+/*! CLR30 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR30_SHIFT)) & DMA_COMMON_INTENCLR_CLR30_MASK)
+#define DMA_COMMON_INTENCLR_CLR31_MASK (0x80000000U)
+#define DMA_COMMON_INTENCLR_CLR31_SHIFT (31U)
+/*! CLR31 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
+ */
+#define DMA_COMMON_INTENCLR_CLR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR31_SHIFT)) & DMA_COMMON_INTENCLR_CLR31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENCLR */
+#define DMA_COMMON_INTENCLR_COUNT (1U)
+
+/*! @name COMMON_INTENCLR1 - Interrupt Enable Clear for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_INTENCLR1_CLR32_MASK (0x1U)
+#define DMA_COMMON_INTENCLR1_CLR32_SHIFT (0U)
+/*! CLR32 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
+ */
+#define DMA_COMMON_INTENCLR1_CLR32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR32_SHIFT)) & DMA_COMMON_INTENCLR1_CLR32_MASK)
+#define DMA_COMMON_INTENCLR1_CLR33_MASK (0x2U)
+#define DMA_COMMON_INTENCLR1_CLR33_SHIFT (1U)
+/*! CLR33 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
+ */
+#define DMA_COMMON_INTENCLR1_CLR33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR33_SHIFT)) & DMA_COMMON_INTENCLR1_CLR33_MASK)
+#define DMA_COMMON_INTENCLR1_CLR34_MASK (0x4U)
+#define DMA_COMMON_INTENCLR1_CLR34_SHIFT (2U)
+/*! CLR34 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
+ */
+#define DMA_COMMON_INTENCLR1_CLR34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR34_SHIFT)) & DMA_COMMON_INTENCLR1_CLR34_MASK)
+#define DMA_COMMON_INTENCLR1_CLR35_MASK (0x8U)
+#define DMA_COMMON_INTENCLR1_CLR35_SHIFT (3U)
+/*! CLR35 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
+ */
+#define DMA_COMMON_INTENCLR1_CLR35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR35_SHIFT)) & DMA_COMMON_INTENCLR1_CLR35_MASK)
+#define DMA_COMMON_INTENCLR1_CLR36_MASK (0x10U)
+#define DMA_COMMON_INTENCLR1_CLR36_SHIFT (4U)
+/*! CLR36 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
+ */
+#define DMA_COMMON_INTENCLR1_CLR36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR36_SHIFT)) & DMA_COMMON_INTENCLR1_CLR36_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENCLR1 */
+#define DMA_COMMON_INTENCLR1_COUNT (1U)
+
+/*! @name COMMON_INTA - Interrupt A status for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_INTA_INTA0_MASK (0x1U)
+#define DMA_COMMON_INTA_INTA0_SHIFT (0U)
+/*! INTA0 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA0_SHIFT)) & DMA_COMMON_INTA_INTA0_MASK)
+#define DMA_COMMON_INTA_INTA1_MASK (0x2U)
+#define DMA_COMMON_INTA_INTA1_SHIFT (1U)
+/*! INTA1 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA1_SHIFT)) & DMA_COMMON_INTA_INTA1_MASK)
+#define DMA_COMMON_INTA_INTA2_MASK (0x4U)
+#define DMA_COMMON_INTA_INTA2_SHIFT (2U)
+/*! INTA2 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA2_SHIFT)) & DMA_COMMON_INTA_INTA2_MASK)
+#define DMA_COMMON_INTA_INTA3_MASK (0x8U)
+#define DMA_COMMON_INTA_INTA3_SHIFT (3U)
+/*! INTA3 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA3_SHIFT)) & DMA_COMMON_INTA_INTA3_MASK)
+#define DMA_COMMON_INTA_INTA4_MASK (0x10U)
+#define DMA_COMMON_INTA_INTA4_SHIFT (4U)
+/*! INTA4 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA4_SHIFT)) & DMA_COMMON_INTA_INTA4_MASK)
+#define DMA_COMMON_INTA_INTA5_MASK (0x20U)
+#define DMA_COMMON_INTA_INTA5_SHIFT (5U)
+/*! INTA5 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA5_SHIFT)) & DMA_COMMON_INTA_INTA5_MASK)
+#define DMA_COMMON_INTA_INTA6_MASK (0x40U)
+#define DMA_COMMON_INTA_INTA6_SHIFT (6U)
+/*! INTA6 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA6_SHIFT)) & DMA_COMMON_INTA_INTA6_MASK)
+#define DMA_COMMON_INTA_INTA7_MASK (0x80U)
+#define DMA_COMMON_INTA_INTA7_SHIFT (7U)
+/*! INTA7 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA7_SHIFT)) & DMA_COMMON_INTA_INTA7_MASK)
+#define DMA_COMMON_INTA_INTA8_MASK (0x100U)
+#define DMA_COMMON_INTA_INTA8_SHIFT (8U)
+/*! INTA8 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA8_SHIFT)) & DMA_COMMON_INTA_INTA8_MASK)
+#define DMA_COMMON_INTA_INTA9_MASK (0x200U)
+#define DMA_COMMON_INTA_INTA9_SHIFT (9U)
+/*! INTA9 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA9_SHIFT)) & DMA_COMMON_INTA_INTA9_MASK)
+#define DMA_COMMON_INTA_INTA10_MASK (0x400U)
+#define DMA_COMMON_INTA_INTA10_SHIFT (10U)
+/*! INTA10 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA10_SHIFT)) & DMA_COMMON_INTA_INTA10_MASK)
+#define DMA_COMMON_INTA_INTA11_MASK (0x800U)
+#define DMA_COMMON_INTA_INTA11_SHIFT (11U)
+/*! INTA11 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA11_SHIFT)) & DMA_COMMON_INTA_INTA11_MASK)
+#define DMA_COMMON_INTA_INTA12_MASK (0x1000U)
+#define DMA_COMMON_INTA_INTA12_SHIFT (12U)
+/*! INTA12 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA12_SHIFT)) & DMA_COMMON_INTA_INTA12_MASK)
+#define DMA_COMMON_INTA_INTA13_MASK (0x2000U)
+#define DMA_COMMON_INTA_INTA13_SHIFT (13U)
+/*! INTA13 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA13_SHIFT)) & DMA_COMMON_INTA_INTA13_MASK)
+#define DMA_COMMON_INTA_INTA14_MASK (0x4000U)
+#define DMA_COMMON_INTA_INTA14_SHIFT (14U)
+/*! INTA14 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA14_SHIFT)) & DMA_COMMON_INTA_INTA14_MASK)
+#define DMA_COMMON_INTA_INTA15_MASK (0x8000U)
+#define DMA_COMMON_INTA_INTA15_SHIFT (15U)
+/*! INTA15 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA15_SHIFT)) & DMA_COMMON_INTA_INTA15_MASK)
+#define DMA_COMMON_INTA_INTA16_MASK (0x10000U)
+#define DMA_COMMON_INTA_INTA16_SHIFT (16U)
+/*! INTA16 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA16_SHIFT)) & DMA_COMMON_INTA_INTA16_MASK)
+#define DMA_COMMON_INTA_INTA17_MASK (0x20000U)
+#define DMA_COMMON_INTA_INTA17_SHIFT (17U)
+/*! INTA17 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA17_SHIFT)) & DMA_COMMON_INTA_INTA17_MASK)
+#define DMA_COMMON_INTA_INTA18_MASK (0x40000U)
+#define DMA_COMMON_INTA_INTA18_SHIFT (18U)
+/*! INTA18 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA18_SHIFT)) & DMA_COMMON_INTA_INTA18_MASK)
+#define DMA_COMMON_INTA_INTA19_MASK (0x80000U)
+#define DMA_COMMON_INTA_INTA19_SHIFT (19U)
+/*! INTA19 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA19_SHIFT)) & DMA_COMMON_INTA_INTA19_MASK)
+#define DMA_COMMON_INTA_INTA20_MASK (0x100000U)
+#define DMA_COMMON_INTA_INTA20_SHIFT (20U)
+/*! INTA20 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA20_SHIFT)) & DMA_COMMON_INTA_INTA20_MASK)
+#define DMA_COMMON_INTA_INTA21_MASK (0x200000U)
+#define DMA_COMMON_INTA_INTA21_SHIFT (21U)
+/*! INTA21 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA21_SHIFT)) & DMA_COMMON_INTA_INTA21_MASK)
+#define DMA_COMMON_INTA_INTA22_MASK (0x400000U)
+#define DMA_COMMON_INTA_INTA22_SHIFT (22U)
+/*! INTA22 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA22_SHIFT)) & DMA_COMMON_INTA_INTA22_MASK)
+#define DMA_COMMON_INTA_INTA23_MASK (0x800000U)
+#define DMA_COMMON_INTA_INTA23_SHIFT (23U)
+/*! INTA23 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA23_SHIFT)) & DMA_COMMON_INTA_INTA23_MASK)
+#define DMA_COMMON_INTA_INTA24_MASK (0x1000000U)
+#define DMA_COMMON_INTA_INTA24_SHIFT (24U)
+/*! INTA24 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA24_SHIFT)) & DMA_COMMON_INTA_INTA24_MASK)
+#define DMA_COMMON_INTA_INTA25_MASK (0x2000000U)
+#define DMA_COMMON_INTA_INTA25_SHIFT (25U)
+/*! INTA25 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA25_SHIFT)) & DMA_COMMON_INTA_INTA25_MASK)
+#define DMA_COMMON_INTA_INTA26_MASK (0x4000000U)
+#define DMA_COMMON_INTA_INTA26_SHIFT (26U)
+/*! INTA26 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA26_SHIFT)) & DMA_COMMON_INTA_INTA26_MASK)
+#define DMA_COMMON_INTA_INTA27_MASK (0x8000000U)
+#define DMA_COMMON_INTA_INTA27_SHIFT (27U)
+/*! INTA27 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA27_SHIFT)) & DMA_COMMON_INTA_INTA27_MASK)
+#define DMA_COMMON_INTA_INTA28_MASK (0x10000000U)
+#define DMA_COMMON_INTA_INTA28_SHIFT (28U)
+/*! INTA28 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA28_SHIFT)) & DMA_COMMON_INTA_INTA28_MASK)
+#define DMA_COMMON_INTA_INTA29_MASK (0x20000000U)
+#define DMA_COMMON_INTA_INTA29_SHIFT (29U)
+/*! INTA29 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA29_SHIFT)) & DMA_COMMON_INTA_INTA29_MASK)
+#define DMA_COMMON_INTA_INTA30_MASK (0x40000000U)
+#define DMA_COMMON_INTA_INTA30_SHIFT (30U)
+/*! INTA30 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA30_SHIFT)) & DMA_COMMON_INTA_INTA30_MASK)
+#define DMA_COMMON_INTA_INTA31_MASK (0x80000000U)
+#define DMA_COMMON_INTA_INTA31_SHIFT (31U)
+/*! INTA31 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_INTA31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA31_SHIFT)) & DMA_COMMON_INTA_INTA31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTA */
+#define DMA_COMMON_INTA_COUNT (1U)
+
+/*! @name COMMON_INTA1 - Interrupt A status for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_INTA1_INTA32_MASK (0x1U)
+#define DMA_COMMON_INTA1_INTA32_SHIFT (0U)
+/*! INTA32 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA1_INTA32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA32_SHIFT)) & DMA_COMMON_INTA1_INTA32_MASK)
+#define DMA_COMMON_INTA1_INTA33_MASK (0x2U)
+#define DMA_COMMON_INTA1_INTA33_SHIFT (1U)
+/*! INTA33 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA1_INTA33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA33_SHIFT)) & DMA_COMMON_INTA1_INTA33_MASK)
+#define DMA_COMMON_INTA1_INTA34_MASK (0x4U)
+#define DMA_COMMON_INTA1_INTA34_SHIFT (2U)
+/*! INTA34 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA1_INTA34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA34_SHIFT)) & DMA_COMMON_INTA1_INTA34_MASK)
+#define DMA_COMMON_INTA1_INTA35_MASK (0x8U)
+#define DMA_COMMON_INTA1_INTA35_SHIFT (3U)
+/*! INTA35 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA1_INTA35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA35_SHIFT)) & DMA_COMMON_INTA1_INTA35_MASK)
+#define DMA_COMMON_INTA1_INTA36_MASK (0x10U)
+#define DMA_COMMON_INTA1_INTA36_SHIFT (4U)
+/*! INTA36 - Interrupt A status for DMA channel.
+ * 0b0..The DMA channel interrupt A is not active.
+ * 0b1..The DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA1_INTA36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA36_SHIFT)) & DMA_COMMON_INTA1_INTA36_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTA1 */
+#define DMA_COMMON_INTA1_COUNT (1U)
+
+/*! @name COMMON_INTB - Interrupt B status for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_INTB_INTB0_MASK (0x1U)
+#define DMA_COMMON_INTB_INTB0_SHIFT (0U)
+/*! INTB0 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB0_SHIFT)) & DMA_COMMON_INTB_INTB0_MASK)
+#define DMA_COMMON_INTB_INTB1_MASK (0x2U)
+#define DMA_COMMON_INTB_INTB1_SHIFT (1U)
+/*! INTB1 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB1_SHIFT)) & DMA_COMMON_INTB_INTB1_MASK)
+#define DMA_COMMON_INTB_INTB2_MASK (0x4U)
+#define DMA_COMMON_INTB_INTB2_SHIFT (2U)
+/*! INTB2 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB2_SHIFT)) & DMA_COMMON_INTB_INTB2_MASK)
+#define DMA_COMMON_INTB_INTB3_MASK (0x8U)
+#define DMA_COMMON_INTB_INTB3_SHIFT (3U)
+/*! INTB3 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB3_SHIFT)) & DMA_COMMON_INTB_INTB3_MASK)
+#define DMA_COMMON_INTB_INTB4_MASK (0x10U)
+#define DMA_COMMON_INTB_INTB4_SHIFT (4U)
+/*! INTB4 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB4_SHIFT)) & DMA_COMMON_INTB_INTB4_MASK)
+#define DMA_COMMON_INTB_INTB5_MASK (0x20U)
+#define DMA_COMMON_INTB_INTB5_SHIFT (5U)
+/*! INTB5 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB5_SHIFT)) & DMA_COMMON_INTB_INTB5_MASK)
+#define DMA_COMMON_INTB_INTB6_MASK (0x40U)
+#define DMA_COMMON_INTB_INTB6_SHIFT (6U)
+/*! INTB6 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB6_SHIFT)) & DMA_COMMON_INTB_INTB6_MASK)
+#define DMA_COMMON_INTB_INTB7_MASK (0x80U)
+#define DMA_COMMON_INTB_INTB7_SHIFT (7U)
+/*! INTB7 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB7_SHIFT)) & DMA_COMMON_INTB_INTB7_MASK)
+#define DMA_COMMON_INTB_INTB8_MASK (0x100U)
+#define DMA_COMMON_INTB_INTB8_SHIFT (8U)
+/*! INTB8 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB8_SHIFT)) & DMA_COMMON_INTB_INTB8_MASK)
+#define DMA_COMMON_INTB_INTB9_MASK (0x200U)
+#define DMA_COMMON_INTB_INTB9_SHIFT (9U)
+/*! INTB9 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB9_SHIFT)) & DMA_COMMON_INTB_INTB9_MASK)
+#define DMA_COMMON_INTB_INTB10_MASK (0x400U)
+#define DMA_COMMON_INTB_INTB10_SHIFT (10U)
+/*! INTB10 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB10_SHIFT)) & DMA_COMMON_INTB_INTB10_MASK)
+#define DMA_COMMON_INTB_INTB11_MASK (0x800U)
+#define DMA_COMMON_INTB_INTB11_SHIFT (11U)
+/*! INTB11 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB11_SHIFT)) & DMA_COMMON_INTB_INTB11_MASK)
+#define DMA_COMMON_INTB_INTB12_MASK (0x1000U)
+#define DMA_COMMON_INTB_INTB12_SHIFT (12U)
+/*! INTB12 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB12_SHIFT)) & DMA_COMMON_INTB_INTB12_MASK)
+#define DMA_COMMON_INTB_INTB13_MASK (0x2000U)
+#define DMA_COMMON_INTB_INTB13_SHIFT (13U)
+/*! INTB13 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB13_SHIFT)) & DMA_COMMON_INTB_INTB13_MASK)
+#define DMA_COMMON_INTB_INTB14_MASK (0x4000U)
+#define DMA_COMMON_INTB_INTB14_SHIFT (14U)
+/*! INTB14 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB14_SHIFT)) & DMA_COMMON_INTB_INTB14_MASK)
+#define DMA_COMMON_INTB_INTB15_MASK (0x8000U)
+#define DMA_COMMON_INTB_INTB15_SHIFT (15U)
+/*! INTB15 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB15_SHIFT)) & DMA_COMMON_INTB_INTB15_MASK)
+#define DMA_COMMON_INTB_INTB16_MASK (0x10000U)
+#define DMA_COMMON_INTB_INTB16_SHIFT (16U)
+/*! INTB16 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB16_SHIFT)) & DMA_COMMON_INTB_INTB16_MASK)
+#define DMA_COMMON_INTB_INTB17_MASK (0x20000U)
+#define DMA_COMMON_INTB_INTB17_SHIFT (17U)
+/*! INTB17 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB17_SHIFT)) & DMA_COMMON_INTB_INTB17_MASK)
+#define DMA_COMMON_INTB_INTB18_MASK (0x40000U)
+#define DMA_COMMON_INTB_INTB18_SHIFT (18U)
+/*! INTB18 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB18_SHIFT)) & DMA_COMMON_INTB_INTB18_MASK)
+#define DMA_COMMON_INTB_INTB19_MASK (0x80000U)
+#define DMA_COMMON_INTB_INTB19_SHIFT (19U)
+/*! INTB19 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB19_SHIFT)) & DMA_COMMON_INTB_INTB19_MASK)
+#define DMA_COMMON_INTB_INTB20_MASK (0x100000U)
+#define DMA_COMMON_INTB_INTB20_SHIFT (20U)
+/*! INTB20 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB20_SHIFT)) & DMA_COMMON_INTB_INTB20_MASK)
+#define DMA_COMMON_INTB_INTB21_MASK (0x200000U)
+#define DMA_COMMON_INTB_INTB21_SHIFT (21U)
+/*! INTB21 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB21_SHIFT)) & DMA_COMMON_INTB_INTB21_MASK)
+#define DMA_COMMON_INTB_INTB22_MASK (0x400000U)
+#define DMA_COMMON_INTB_INTB22_SHIFT (22U)
+/*! INTB22 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB22_SHIFT)) & DMA_COMMON_INTB_INTB22_MASK)
+#define DMA_COMMON_INTB_INTB23_MASK (0x800000U)
+#define DMA_COMMON_INTB_INTB23_SHIFT (23U)
+/*! INTB23 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB23_SHIFT)) & DMA_COMMON_INTB_INTB23_MASK)
+#define DMA_COMMON_INTB_INTB24_MASK (0x1000000U)
+#define DMA_COMMON_INTB_INTB24_SHIFT (24U)
+/*! INTB24 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB24_SHIFT)) & DMA_COMMON_INTB_INTB24_MASK)
+#define DMA_COMMON_INTB_INTB25_MASK (0x2000000U)
+#define DMA_COMMON_INTB_INTB25_SHIFT (25U)
+/*! INTB25 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB25_SHIFT)) & DMA_COMMON_INTB_INTB25_MASK)
+#define DMA_COMMON_INTB_INTB26_MASK (0x4000000U)
+#define DMA_COMMON_INTB_INTB26_SHIFT (26U)
+/*! INTB26 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB26_SHIFT)) & DMA_COMMON_INTB_INTB26_MASK)
+#define DMA_COMMON_INTB_INTB27_MASK (0x8000000U)
+#define DMA_COMMON_INTB_INTB27_SHIFT (27U)
+/*! INTB27 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB27_SHIFT)) & DMA_COMMON_INTB_INTB27_MASK)
+#define DMA_COMMON_INTB_INTB28_MASK (0x10000000U)
+#define DMA_COMMON_INTB_INTB28_SHIFT (28U)
+/*! INTB28 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB28_SHIFT)) & DMA_COMMON_INTB_INTB28_MASK)
+#define DMA_COMMON_INTB_INTB29_MASK (0x20000000U)
+#define DMA_COMMON_INTB_INTB29_SHIFT (29U)
+/*! INTB29 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB29_SHIFT)) & DMA_COMMON_INTB_INTB29_MASK)
+#define DMA_COMMON_INTB_INTB30_MASK (0x40000000U)
+#define DMA_COMMON_INTB_INTB30_SHIFT (30U)
+/*! INTB30 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB30_SHIFT)) & DMA_COMMON_INTB_INTB30_MASK)
+#define DMA_COMMON_INTB_INTB31_MASK (0x80000000U)
+#define DMA_COMMON_INTB_INTB31_SHIFT (31U)
+/*! INTB31 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_INTB31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB31_SHIFT)) & DMA_COMMON_INTB_INTB31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTB */
+#define DMA_COMMON_INTB_COUNT (1U)
+
+/*! @name COMMON_INTB1 - Interrupt B status for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_INTB1_INTB0_MASK (0x1U)
+#define DMA_COMMON_INTB1_INTB0_SHIFT (0U)
+/*! INTB0 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB1_INTB0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB0_SHIFT)) & DMA_COMMON_INTB1_INTB0_MASK)
+#define DMA_COMMON_INTB1_INTB1_MASK (0x2U)
+#define DMA_COMMON_INTB1_INTB1_SHIFT (1U)
+/*! INTB1 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB1_INTB1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB1_SHIFT)) & DMA_COMMON_INTB1_INTB1_MASK)
+#define DMA_COMMON_INTB1_INTB2_MASK (0x4U)
+#define DMA_COMMON_INTB1_INTB2_SHIFT (2U)
+/*! INTB2 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB1_INTB2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB2_SHIFT)) & DMA_COMMON_INTB1_INTB2_MASK)
+#define DMA_COMMON_INTB1_INTB3_MASK (0x8U)
+#define DMA_COMMON_INTB1_INTB3_SHIFT (3U)
+/*! INTB3 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB1_INTB3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB3_SHIFT)) & DMA_COMMON_INTB1_INTB3_MASK)
+#define DMA_COMMON_INTB1_INTB4_MASK (0x10U)
+#define DMA_COMMON_INTB1_INTB4_SHIFT (4U)
+/*! INTB4 - Interrupt B status for DMA channel.
+ * 0b0..The DMA channel interrupt B is not active.
+ * 0b1..The DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB1_INTB4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB4_SHIFT)) & DMA_COMMON_INTB1_INTB4_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTB1 */
+#define DMA_COMMON_INTB1_COUNT (1U)
+
+/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_SETVALID_SETVALID0_MASK (0x1U)
+#define DMA_COMMON_SETVALID_SETVALID0_SHIFT (0U)
+/*! SETVALID0 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID0_SHIFT)) & DMA_COMMON_SETVALID_SETVALID0_MASK)
+#define DMA_COMMON_SETVALID_SETVALID1_MASK (0x2U)
+#define DMA_COMMON_SETVALID_SETVALID1_SHIFT (1U)
+/*! SETVALID1 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID1_SHIFT)) & DMA_COMMON_SETVALID_SETVALID1_MASK)
+#define DMA_COMMON_SETVALID_SETVALID2_MASK (0x4U)
+#define DMA_COMMON_SETVALID_SETVALID2_SHIFT (2U)
+/*! SETVALID2 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID2_SHIFT)) & DMA_COMMON_SETVALID_SETVALID2_MASK)
+#define DMA_COMMON_SETVALID_SETVALID3_MASK (0x8U)
+#define DMA_COMMON_SETVALID_SETVALID3_SHIFT (3U)
+/*! SETVALID3 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID3_SHIFT)) & DMA_COMMON_SETVALID_SETVALID3_MASK)
+#define DMA_COMMON_SETVALID_SETVALID4_MASK (0x10U)
+#define DMA_COMMON_SETVALID_SETVALID4_SHIFT (4U)
+/*! SETVALID4 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID4_SHIFT)) & DMA_COMMON_SETVALID_SETVALID4_MASK)
+#define DMA_COMMON_SETVALID_SETVALID5_MASK (0x20U)
+#define DMA_COMMON_SETVALID_SETVALID5_SHIFT (5U)
+/*! SETVALID5 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID5_SHIFT)) & DMA_COMMON_SETVALID_SETVALID5_MASK)
+#define DMA_COMMON_SETVALID_SETVALID6_MASK (0x40U)
+#define DMA_COMMON_SETVALID_SETVALID6_SHIFT (6U)
+/*! SETVALID6 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID6_SHIFT)) & DMA_COMMON_SETVALID_SETVALID6_MASK)
+#define DMA_COMMON_SETVALID_SETVALID7_MASK (0x80U)
+#define DMA_COMMON_SETVALID_SETVALID7_SHIFT (7U)
+/*! SETVALID7 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID7_SHIFT)) & DMA_COMMON_SETVALID_SETVALID7_MASK)
+#define DMA_COMMON_SETVALID_SETVALID8_MASK (0x100U)
+#define DMA_COMMON_SETVALID_SETVALID8_SHIFT (8U)
+/*! SETVALID8 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID8_SHIFT)) & DMA_COMMON_SETVALID_SETVALID8_MASK)
+#define DMA_COMMON_SETVALID_SETVALID9_MASK (0x200U)
+#define DMA_COMMON_SETVALID_SETVALID9_SHIFT (9U)
+/*! SETVALID9 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID9_SHIFT)) & DMA_COMMON_SETVALID_SETVALID9_MASK)
+#define DMA_COMMON_SETVALID_SETVALID10_MASK (0x400U)
+#define DMA_COMMON_SETVALID_SETVALID10_SHIFT (10U)
+/*! SETVALID10 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID10_SHIFT)) & DMA_COMMON_SETVALID_SETVALID10_MASK)
+#define DMA_COMMON_SETVALID_SETVALID11_MASK (0x800U)
+#define DMA_COMMON_SETVALID_SETVALID11_SHIFT (11U)
+/*! SETVALID11 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID11_SHIFT)) & DMA_COMMON_SETVALID_SETVALID11_MASK)
+#define DMA_COMMON_SETVALID_SETVALID12_MASK (0x1000U)
+#define DMA_COMMON_SETVALID_SETVALID12_SHIFT (12U)
+/*! SETVALID12 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID12_SHIFT)) & DMA_COMMON_SETVALID_SETVALID12_MASK)
+#define DMA_COMMON_SETVALID_SETVALID13_MASK (0x2000U)
+#define DMA_COMMON_SETVALID_SETVALID13_SHIFT (13U)
+/*! SETVALID13 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID13_SHIFT)) & DMA_COMMON_SETVALID_SETVALID13_MASK)
+#define DMA_COMMON_SETVALID_SETVALID14_MASK (0x4000U)
+#define DMA_COMMON_SETVALID_SETVALID14_SHIFT (14U)
+/*! SETVALID14 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID14_SHIFT)) & DMA_COMMON_SETVALID_SETVALID14_MASK)
+#define DMA_COMMON_SETVALID_SETVALID15_MASK (0x8000U)
+#define DMA_COMMON_SETVALID_SETVALID15_SHIFT (15U)
+/*! SETVALID15 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID15_SHIFT)) & DMA_COMMON_SETVALID_SETVALID15_MASK)
+#define DMA_COMMON_SETVALID_SETVALID16_MASK (0x10000U)
+#define DMA_COMMON_SETVALID_SETVALID16_SHIFT (16U)
+/*! SETVALID16 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID16_SHIFT)) & DMA_COMMON_SETVALID_SETVALID16_MASK)
+#define DMA_COMMON_SETVALID_SETVALID17_MASK (0x20000U)
+#define DMA_COMMON_SETVALID_SETVALID17_SHIFT (17U)
+/*! SETVALID17 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID17_SHIFT)) & DMA_COMMON_SETVALID_SETVALID17_MASK)
+#define DMA_COMMON_SETVALID_SETVALID18_MASK (0x40000U)
+#define DMA_COMMON_SETVALID_SETVALID18_SHIFT (18U)
+/*! SETVALID18 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID18_SHIFT)) & DMA_COMMON_SETVALID_SETVALID18_MASK)
+#define DMA_COMMON_SETVALID_SETVALID19_MASK (0x80000U)
+#define DMA_COMMON_SETVALID_SETVALID19_SHIFT (19U)
+/*! SETVALID19 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID19_SHIFT)) & DMA_COMMON_SETVALID_SETVALID19_MASK)
+#define DMA_COMMON_SETVALID_SETVALID20_MASK (0x100000U)
+#define DMA_COMMON_SETVALID_SETVALID20_SHIFT (20U)
+/*! SETVALID20 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID20_SHIFT)) & DMA_COMMON_SETVALID_SETVALID20_MASK)
+#define DMA_COMMON_SETVALID_SETVALID21_MASK (0x200000U)
+#define DMA_COMMON_SETVALID_SETVALID21_SHIFT (21U)
+/*! SETVALID21 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID21_SHIFT)) & DMA_COMMON_SETVALID_SETVALID21_MASK)
+#define DMA_COMMON_SETVALID_SETVALID22_MASK (0x400000U)
+#define DMA_COMMON_SETVALID_SETVALID22_SHIFT (22U)
+/*! SETVALID22 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID22_SHIFT)) & DMA_COMMON_SETVALID_SETVALID22_MASK)
+#define DMA_COMMON_SETVALID_SETVALID23_MASK (0x800000U)
+#define DMA_COMMON_SETVALID_SETVALID23_SHIFT (23U)
+/*! SETVALID23 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID23_SHIFT)) & DMA_COMMON_SETVALID_SETVALID23_MASK)
+#define DMA_COMMON_SETVALID_SETVALID24_MASK (0x1000000U)
+#define DMA_COMMON_SETVALID_SETVALID24_SHIFT (24U)
+/*! SETVALID24 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID24_SHIFT)) & DMA_COMMON_SETVALID_SETVALID24_MASK)
+#define DMA_COMMON_SETVALID_SETVALID25_MASK (0x2000000U)
+#define DMA_COMMON_SETVALID_SETVALID25_SHIFT (25U)
+/*! SETVALID25 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID25_SHIFT)) & DMA_COMMON_SETVALID_SETVALID25_MASK)
+#define DMA_COMMON_SETVALID_SETVALID26_MASK (0x4000000U)
+#define DMA_COMMON_SETVALID_SETVALID26_SHIFT (26U)
+/*! SETVALID26 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID26_SHIFT)) & DMA_COMMON_SETVALID_SETVALID26_MASK)
+#define DMA_COMMON_SETVALID_SETVALID27_MASK (0x8000000U)
+#define DMA_COMMON_SETVALID_SETVALID27_SHIFT (27U)
+/*! SETVALID27 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID27_SHIFT)) & DMA_COMMON_SETVALID_SETVALID27_MASK)
+#define DMA_COMMON_SETVALID_SETVALID28_MASK (0x10000000U)
+#define DMA_COMMON_SETVALID_SETVALID28_SHIFT (28U)
+/*! SETVALID28 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID28_SHIFT)) & DMA_COMMON_SETVALID_SETVALID28_MASK)
+#define DMA_COMMON_SETVALID_SETVALID29_MASK (0x20000000U)
+#define DMA_COMMON_SETVALID_SETVALID29_SHIFT (29U)
+/*! SETVALID29 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID29_SHIFT)) & DMA_COMMON_SETVALID_SETVALID29_MASK)
+#define DMA_COMMON_SETVALID_SETVALID30_MASK (0x40000000U)
+#define DMA_COMMON_SETVALID_SETVALID30_SHIFT (30U)
+/*! SETVALID30 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID30_SHIFT)) & DMA_COMMON_SETVALID_SETVALID30_MASK)
+#define DMA_COMMON_SETVALID_SETVALID31_MASK (0x80000000U)
+#define DMA_COMMON_SETVALID_SETVALID31_SHIFT (31U)
+/*! SETVALID31 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID_SETVALID31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID31_SHIFT)) & DMA_COMMON_SETVALID_SETVALID31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETVALID */
+#define DMA_COMMON_SETVALID_COUNT (1U)
+
+/*! @name COMMON_SETVALID1 - Set ValidPending control bits for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_SETVALID1_SETVALID32_MASK (0x1U)
+#define DMA_COMMON_SETVALID1_SETVALID32_SHIFT (0U)
+/*! SETVALID32 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID1_SETVALID32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID32_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID32_MASK)
+#define DMA_COMMON_SETVALID1_SETVALID33_MASK (0x2U)
+#define DMA_COMMON_SETVALID1_SETVALID33_SHIFT (1U)
+/*! SETVALID33 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID1_SETVALID33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID33_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID33_MASK)
+#define DMA_COMMON_SETVALID1_SETVALID34_MASK (0x4U)
+#define DMA_COMMON_SETVALID1_SETVALID34_SHIFT (2U)
+/*! SETVALID34 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID1_SETVALID34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID34_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID34_MASK)
+#define DMA_COMMON_SETVALID1_SETVALID35_MASK (0x8U)
+#define DMA_COMMON_SETVALID1_SETVALID35_SHIFT (3U)
+/*! SETVALID35 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID1_SETVALID35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID35_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID35_MASK)
+#define DMA_COMMON_SETVALID1_SETVALID36_MASK (0x10U)
+#define DMA_COMMON_SETVALID1_SETVALID36_SHIFT (4U)
+/*! SETVALID36 - SetValid control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the ValidPending control bit for DMA channel.
+ */
+#define DMA_COMMON_SETVALID1_SETVALID36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID36_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID36_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETVALID1 */
+#define DMA_COMMON_SETVALID1_COUNT (1U)
+
+/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_SETTRIG_SETTRIG0_MASK (0x1U)
+#define DMA_COMMON_SETTRIG_SETTRIG0_SHIFT (0U)
+/*! SETTRIG0 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG0_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG0_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG1_MASK (0x2U)
+#define DMA_COMMON_SETTRIG_SETTRIG1_SHIFT (1U)
+/*! SETTRIG1 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG1_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG1_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG2_MASK (0x4U)
+#define DMA_COMMON_SETTRIG_SETTRIG2_SHIFT (2U)
+/*! SETTRIG2 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG2_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG2_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG3_MASK (0x8U)
+#define DMA_COMMON_SETTRIG_SETTRIG3_SHIFT (3U)
+/*! SETTRIG3 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG3_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG3_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG4_MASK (0x10U)
+#define DMA_COMMON_SETTRIG_SETTRIG4_SHIFT (4U)
+/*! SETTRIG4 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG4_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG4_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG5_MASK (0x20U)
+#define DMA_COMMON_SETTRIG_SETTRIG5_SHIFT (5U)
+/*! SETTRIG5 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG5_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG5_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG6_MASK (0x40U)
+#define DMA_COMMON_SETTRIG_SETTRIG6_SHIFT (6U)
+/*! SETTRIG6 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG6_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG6_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG7_MASK (0x80U)
+#define DMA_COMMON_SETTRIG_SETTRIG7_SHIFT (7U)
+/*! SETTRIG7 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG7_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG7_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG8_MASK (0x100U)
+#define DMA_COMMON_SETTRIG_SETTRIG8_SHIFT (8U)
+/*! SETTRIG8 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG8_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG8_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG9_MASK (0x200U)
+#define DMA_COMMON_SETTRIG_SETTRIG9_SHIFT (9U)
+/*! SETTRIG9 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG9_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG9_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG10_MASK (0x400U)
+#define DMA_COMMON_SETTRIG_SETTRIG10_SHIFT (10U)
+/*! SETTRIG10 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG10_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG10_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG11_MASK (0x800U)
+#define DMA_COMMON_SETTRIG_SETTRIG11_SHIFT (11U)
+/*! SETTRIG11 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG11_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG11_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG12_MASK (0x1000U)
+#define DMA_COMMON_SETTRIG_SETTRIG12_SHIFT (12U)
+/*! SETTRIG12 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG12_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG12_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG13_MASK (0x2000U)
+#define DMA_COMMON_SETTRIG_SETTRIG13_SHIFT (13U)
+/*! SETTRIG13 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG13_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG13_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG14_MASK (0x4000U)
+#define DMA_COMMON_SETTRIG_SETTRIG14_SHIFT (14U)
+/*! SETTRIG14 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG14_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG14_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG15_MASK (0x8000U)
+#define DMA_COMMON_SETTRIG_SETTRIG15_SHIFT (15U)
+/*! SETTRIG15 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG15_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG15_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG16_MASK (0x10000U)
+#define DMA_COMMON_SETTRIG_SETTRIG16_SHIFT (16U)
+/*! SETTRIG16 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG16_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG16_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG17_MASK (0x20000U)
+#define DMA_COMMON_SETTRIG_SETTRIG17_SHIFT (17U)
+/*! SETTRIG17 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG17_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG17_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG18_MASK (0x40000U)
+#define DMA_COMMON_SETTRIG_SETTRIG18_SHIFT (18U)
+/*! SETTRIG18 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG18_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG18_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG19_MASK (0x80000U)
+#define DMA_COMMON_SETTRIG_SETTRIG19_SHIFT (19U)
+/*! SETTRIG19 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG19_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG19_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG20_MASK (0x100000U)
+#define DMA_COMMON_SETTRIG_SETTRIG20_SHIFT (20U)
+/*! SETTRIG20 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG20_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG20_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG21_MASK (0x200000U)
+#define DMA_COMMON_SETTRIG_SETTRIG21_SHIFT (21U)
+/*! SETTRIG21 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG21_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG21_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG22_MASK (0x400000U)
+#define DMA_COMMON_SETTRIG_SETTRIG22_SHIFT (22U)
+/*! SETTRIG22 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG22_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG22_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG23_MASK (0x800000U)
+#define DMA_COMMON_SETTRIG_SETTRIG23_SHIFT (23U)
+/*! SETTRIG23 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG23_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG23_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG24_MASK (0x1000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG24_SHIFT (24U)
+/*! SETTRIG24 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG24_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG24_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG25_MASK (0x2000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG25_SHIFT (25U)
+/*! SETTRIG25 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG25_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG25_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG26_MASK (0x4000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG26_SHIFT (26U)
+/*! SETTRIG26 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG26_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG26_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG27_MASK (0x8000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG27_SHIFT (27U)
+/*! SETTRIG27 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG27_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG27_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG28_MASK (0x10000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG28_SHIFT (28U)
+/*! SETTRIG28 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG28_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG28_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG29_MASK (0x20000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG29_SHIFT (29U)
+/*! SETTRIG29 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG29_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG29_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG30_MASK (0x40000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG30_SHIFT (30U)
+/*! SETTRIG30 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG30_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG30_MASK)
+#define DMA_COMMON_SETTRIG_SETTRIG31_MASK (0x80000000U)
+#define DMA_COMMON_SETTRIG_SETTRIG31_SHIFT (31U)
+/*! SETTRIG31 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG_SETTRIG31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG31_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETTRIG */
+#define DMA_COMMON_SETTRIG_COUNT (1U)
+
+/*! @name COMMON_SETTRIG1 - Set Trigger control bits for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_SETTRIG1_SETTRIG32_MASK (0x1U)
+#define DMA_COMMON_SETTRIG1_SETTRIG32_SHIFT (0U)
+/*! SETTRIG32 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG1_SETTRIG32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG32_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG32_MASK)
+#define DMA_COMMON_SETTRIG1_SETTRIG33_MASK (0x2U)
+#define DMA_COMMON_SETTRIG1_SETTRIG33_SHIFT (1U)
+/*! SETTRIG33 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG1_SETTRIG33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG33_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG33_MASK)
+#define DMA_COMMON_SETTRIG1_SETTRIG34_MASK (0x4U)
+#define DMA_COMMON_SETTRIG1_SETTRIG34_SHIFT (2U)
+/*! SETTRIG34 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG1_SETTRIG34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG34_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG34_MASK)
+#define DMA_COMMON_SETTRIG1_SETTRIG35_MASK (0x8U)
+#define DMA_COMMON_SETTRIG1_SETTRIG35_SHIFT (3U)
+/*! SETTRIG35 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG1_SETTRIG35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG35_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG35_MASK)
+#define DMA_COMMON_SETTRIG1_SETTRIG36_MASK (0x10U)
+#define DMA_COMMON_SETTRIG1_SETTRIG36_SHIFT (4U)
+/*! SETTRIG36 - Set Trigger control bit for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Sets the Trig bit for DMA channel.
+ */
+#define DMA_COMMON_SETTRIG1_SETTRIG36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG36_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG36_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETTRIG1 */
+#define DMA_COMMON_SETTRIG1_COUNT (1U)
+
+/*! @name COMMON_ABORT - Channel Abort control for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_ABORT_ABORT0_MASK (0x1U)
+#define DMA_COMMON_ABORT_ABORT0_SHIFT (0U)
+/*! ABORT0 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT0_SHIFT)) & DMA_COMMON_ABORT_ABORT0_MASK)
+#define DMA_COMMON_ABORT_ABORT1_MASK (0x2U)
+#define DMA_COMMON_ABORT_ABORT1_SHIFT (1U)
+/*! ABORT1 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT1_SHIFT)) & DMA_COMMON_ABORT_ABORT1_MASK)
+#define DMA_COMMON_ABORT_ABORT2_MASK (0x4U)
+#define DMA_COMMON_ABORT_ABORT2_SHIFT (2U)
+/*! ABORT2 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT2_SHIFT)) & DMA_COMMON_ABORT_ABORT2_MASK)
+#define DMA_COMMON_ABORT_ABORT3_MASK (0x8U)
+#define DMA_COMMON_ABORT_ABORT3_SHIFT (3U)
+/*! ABORT3 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT3_SHIFT)) & DMA_COMMON_ABORT_ABORT3_MASK)
+#define DMA_COMMON_ABORT_ABORT4_MASK (0x10U)
+#define DMA_COMMON_ABORT_ABORT4_SHIFT (4U)
+/*! ABORT4 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT4_SHIFT)) & DMA_COMMON_ABORT_ABORT4_MASK)
+#define DMA_COMMON_ABORT_ABORT5_MASK (0x20U)
+#define DMA_COMMON_ABORT_ABORT5_SHIFT (5U)
+/*! ABORT5 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT5_SHIFT)) & DMA_COMMON_ABORT_ABORT5_MASK)
+#define DMA_COMMON_ABORT_ABORT6_MASK (0x40U)
+#define DMA_COMMON_ABORT_ABORT6_SHIFT (6U)
+/*! ABORT6 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT6_SHIFT)) & DMA_COMMON_ABORT_ABORT6_MASK)
+#define DMA_COMMON_ABORT_ABORT7_MASK (0x80U)
+#define DMA_COMMON_ABORT_ABORT7_SHIFT (7U)
+/*! ABORT7 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT7_SHIFT)) & DMA_COMMON_ABORT_ABORT7_MASK)
+#define DMA_COMMON_ABORT_ABORT8_MASK (0x100U)
+#define DMA_COMMON_ABORT_ABORT8_SHIFT (8U)
+/*! ABORT8 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT8_SHIFT)) & DMA_COMMON_ABORT_ABORT8_MASK)
+#define DMA_COMMON_ABORT_ABORT9_MASK (0x200U)
+#define DMA_COMMON_ABORT_ABORT9_SHIFT (9U)
+/*! ABORT9 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT9_SHIFT)) & DMA_COMMON_ABORT_ABORT9_MASK)
+#define DMA_COMMON_ABORT_ABORT10_MASK (0x400U)
+#define DMA_COMMON_ABORT_ABORT10_SHIFT (10U)
+/*! ABORT10 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT10_SHIFT)) & DMA_COMMON_ABORT_ABORT10_MASK)
+#define DMA_COMMON_ABORT_ABORT11_MASK (0x800U)
+#define DMA_COMMON_ABORT_ABORT11_SHIFT (11U)
+/*! ABORT11 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT11_SHIFT)) & DMA_COMMON_ABORT_ABORT11_MASK)
+#define DMA_COMMON_ABORT_ABORT12_MASK (0x1000U)
+#define DMA_COMMON_ABORT_ABORT12_SHIFT (12U)
+/*! ABORT12 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT12_SHIFT)) & DMA_COMMON_ABORT_ABORT12_MASK)
+#define DMA_COMMON_ABORT_ABORT13_MASK (0x2000U)
+#define DMA_COMMON_ABORT_ABORT13_SHIFT (13U)
+/*! ABORT13 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT13_SHIFT)) & DMA_COMMON_ABORT_ABORT13_MASK)
+#define DMA_COMMON_ABORT_ABORT14_MASK (0x4000U)
+#define DMA_COMMON_ABORT_ABORT14_SHIFT (14U)
+/*! ABORT14 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT14_SHIFT)) & DMA_COMMON_ABORT_ABORT14_MASK)
+#define DMA_COMMON_ABORT_ABORT15_MASK (0x8000U)
+#define DMA_COMMON_ABORT_ABORT15_SHIFT (15U)
+/*! ABORT15 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT15_SHIFT)) & DMA_COMMON_ABORT_ABORT15_MASK)
+#define DMA_COMMON_ABORT_ABORT16_MASK (0x10000U)
+#define DMA_COMMON_ABORT_ABORT16_SHIFT (16U)
+/*! ABORT16 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT16_SHIFT)) & DMA_COMMON_ABORT_ABORT16_MASK)
+#define DMA_COMMON_ABORT_ABORT17_MASK (0x20000U)
+#define DMA_COMMON_ABORT_ABORT17_SHIFT (17U)
+/*! ABORT17 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT17_SHIFT)) & DMA_COMMON_ABORT_ABORT17_MASK)
+#define DMA_COMMON_ABORT_ABORT18_MASK (0x40000U)
+#define DMA_COMMON_ABORT_ABORT18_SHIFT (18U)
+/*! ABORT18 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT18_SHIFT)) & DMA_COMMON_ABORT_ABORT18_MASK)
+#define DMA_COMMON_ABORT_ABORT19_MASK (0x80000U)
+#define DMA_COMMON_ABORT_ABORT19_SHIFT (19U)
+/*! ABORT19 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT19_SHIFT)) & DMA_COMMON_ABORT_ABORT19_MASK)
+#define DMA_COMMON_ABORT_ABORT20_MASK (0x100000U)
+#define DMA_COMMON_ABORT_ABORT20_SHIFT (20U)
+/*! ABORT20 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT20_SHIFT)) & DMA_COMMON_ABORT_ABORT20_MASK)
+#define DMA_COMMON_ABORT_ABORT21_MASK (0x200000U)
+#define DMA_COMMON_ABORT_ABORT21_SHIFT (21U)
+/*! ABORT21 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT21_SHIFT)) & DMA_COMMON_ABORT_ABORT21_MASK)
+#define DMA_COMMON_ABORT_ABORT22_MASK (0x400000U)
+#define DMA_COMMON_ABORT_ABORT22_SHIFT (22U)
+/*! ABORT22 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT22_SHIFT)) & DMA_COMMON_ABORT_ABORT22_MASK)
+#define DMA_COMMON_ABORT_ABORT23_MASK (0x800000U)
+#define DMA_COMMON_ABORT_ABORT23_SHIFT (23U)
+/*! ABORT23 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT23_SHIFT)) & DMA_COMMON_ABORT_ABORT23_MASK)
+#define DMA_COMMON_ABORT_ABORT24_MASK (0x1000000U)
+#define DMA_COMMON_ABORT_ABORT24_SHIFT (24U)
+/*! ABORT24 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT24_SHIFT)) & DMA_COMMON_ABORT_ABORT24_MASK)
+#define DMA_COMMON_ABORT_ABORT25_MASK (0x2000000U)
+#define DMA_COMMON_ABORT_ABORT25_SHIFT (25U)
+/*! ABORT25 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT25_SHIFT)) & DMA_COMMON_ABORT_ABORT25_MASK)
+#define DMA_COMMON_ABORT_ABORT26_MASK (0x4000000U)
+#define DMA_COMMON_ABORT_ABORT26_SHIFT (26U)
+/*! ABORT26 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT26_SHIFT)) & DMA_COMMON_ABORT_ABORT26_MASK)
+#define DMA_COMMON_ABORT_ABORT27_MASK (0x8000000U)
+#define DMA_COMMON_ABORT_ABORT27_SHIFT (27U)
+/*! ABORT27 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT27_SHIFT)) & DMA_COMMON_ABORT_ABORT27_MASK)
+#define DMA_COMMON_ABORT_ABORT28_MASK (0x10000000U)
+#define DMA_COMMON_ABORT_ABORT28_SHIFT (28U)
+/*! ABORT28 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT28_SHIFT)) & DMA_COMMON_ABORT_ABORT28_MASK)
+#define DMA_COMMON_ABORT_ABORT29_MASK (0x20000000U)
+#define DMA_COMMON_ABORT_ABORT29_SHIFT (29U)
+/*! ABORT29 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT29_SHIFT)) & DMA_COMMON_ABORT_ABORT29_MASK)
+#define DMA_COMMON_ABORT_ABORT30_MASK (0x40000000U)
+#define DMA_COMMON_ABORT_ABORT30_SHIFT (30U)
+/*! ABORT30 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT30_SHIFT)) & DMA_COMMON_ABORT_ABORT30_MASK)
+#define DMA_COMMON_ABORT_ABORT31_MASK (0x80000000U)
+#define DMA_COMMON_ABORT_ABORT31_SHIFT (31U)
+/*! ABORT31 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT_ABORT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT31_SHIFT)) & DMA_COMMON_ABORT_ABORT31_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ABORT */
+#define DMA_COMMON_ABORT_COUNT (1U)
+
+/*! @name COMMON_ABORT1 - Channel Abort control for all DMA channels */
+/*! @{ */
+#define DMA_COMMON_ABORT1_ABORT32_MASK (0x1U)
+#define DMA_COMMON_ABORT1_ABORT32_SHIFT (0U)
+/*! ABORT32 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT1_ABORT32(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT32_SHIFT)) & DMA_COMMON_ABORT1_ABORT32_MASK)
+#define DMA_COMMON_ABORT1_ABORT33_MASK (0x2U)
+#define DMA_COMMON_ABORT1_ABORT33_SHIFT (1U)
+/*! ABORT33 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT1_ABORT33(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT33_SHIFT)) & DMA_COMMON_ABORT1_ABORT33_MASK)
+#define DMA_COMMON_ABORT1_ABORT34_MASK (0x4U)
+#define DMA_COMMON_ABORT1_ABORT34_SHIFT (2U)
+/*! ABORT34 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT1_ABORT34(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT34_SHIFT)) & DMA_COMMON_ABORT1_ABORT34_MASK)
+#define DMA_COMMON_ABORT1_ABORT35_MASK (0x8U)
+#define DMA_COMMON_ABORT1_ABORT35_SHIFT (3U)
+/*! ABORT35 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT1_ABORT35(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT35_SHIFT)) & DMA_COMMON_ABORT1_ABORT35_MASK)
+#define DMA_COMMON_ABORT1_ABORT36_MASK (0x10U)
+#define DMA_COMMON_ABORT1_ABORT36_SHIFT (4U)
+/*! ABORT36 - Abort control for DMA channel.
+ * 0b0..No effect.
+ * 0b1..Aborts DMA operations on channel.
+ */
+#define DMA_COMMON_ABORT1_ABORT36(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT36_SHIFT)) & DMA_COMMON_ABORT1_ABORT36_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ABORT1 */
+#define DMA_COMMON_ABORT1_COUNT (1U)
+
+/*! @name CHANNEL_CFG - Configuration register for DMA channel */
+/*! @{ */
+#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
+/*! PERIPHREQEN - Peripheral request Enable.
+ * 0b0..Peripheral DMA requests disabled.
+ * 0b1..Peripheral DMA requests enabled.
+ */
+#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
+#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
+#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
+/*! HWTRIGEN - Hardware Triggering Enable for channel.
+ * 0b0..Hardware triggering not used for channel.
+ * 0b1..Hardware triggering used for channel.
+ */
+#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
+#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
+#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
+/*! TRIGPOL - Trigger Polarity.
+ * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
+ * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
+ */
+#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
+#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
+#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
+/*! TRIGTYPE - Trigger Type.
+ * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
+ * 0b1..Level.
+ */
+#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
+#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
+#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
+/*! TRIGBURST - Trigger Burst.
+ * 0b0..Single transfer.
+ * 0b1..Burst transfer.
+ */
+#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
+#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
+#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
+/*! BURSTPOWER - Burst Power.
+ */
+#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
+/*! SRCBURSTWRAP - Source Burst Wrap.
+ * 0b0..Disabled.
+ * 0b1..Enabled.
+ */
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
+/*! DSTBURSTWRAP - Destination Burst Wrap.
+ * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
+ * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
+ */
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
+#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
+/*! CHPRIORITY - Priority of channel when multiple DMA requests are pending.
+ */
+#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_CFG */
+#define DMA_CHANNEL_CFG_COUNT (37U)
+
+/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel */
+/*! @{ */
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
+/*! VALIDPENDING - Valid pending flag for this channel.
+ * 0b0..No effect on DMA operation.
+ * 0b1..Valid pending.
+ */
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
+#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
+#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
+/*! TRIG - Trigger flag.
+ * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
+ * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
+ */
+#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_CTLSTAT */
+#define DMA_CHANNEL_CTLSTAT_COUNT (37U)
+
+/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel */
+/*! @{ */
+#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
+/*! CFGVALID - Configuration Valid flag.
+ * 0b0..Not valid.
+ * 0b1..Valid.
+ */
+#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
+#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
+#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
+/*! RELOAD - Reload.
+ * 0b0..Disabled. The channels' control structure should not be reloaded when the current descriptor is exhausted.
+ * 0b1..Enabled. The channels' control structure should be reloaded when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
+/*! SWTRIG - Software Trigger.
+ * 0b0..Not set.
+ * 0b1..Set.
+ */
+#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
+/*! CLRTRIG - Clear Trigger.
+ * 0b0..Not cleared.
+ * 0b1..Cleared.
+ */
+#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
+#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
+/*! SETINTA - Set Interrupt flag A for channel.
+ * 0b0..No effect.
+ * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
+#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
+/*! SETINTB - Set Interrupt flag B for channel.
+ * 0b0..No effect.
+ * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
+#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
+#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
+/*! WIDTH - Transfer width used for this DMA channel.
+ * 0b00..8-bit.
+ * 0b01..16-bit.
+ * 0b10..32-bit.
+ * 0b11..Reserved.
+ */
+#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
+#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
+#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
+/*! SRCINC - Source address increment
+ * 0b00..No increment.
+ * 0b01..1 x width.
+ * 0b10..2 x width.
+ * 0b11..4 x width.
+ */
+#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
+#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
+#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
+/*! DSTINC - Destination address increment
+ * 0b00..No increment.
+ * 0b01..1 x width.
+ * 0b10..2 x width.
+ * 0b11..4 x width.
+ */
+#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
+/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded.
+ */
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_XFERCFG */
+#define DMA_CHANNEL_XFERCFG_COUNT (37U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral DMA0 base address */
+ #define DMA0_BASE (0x50104000u)
+ /** Peripheral DMA0 base address */
+ #define DMA0_BASE_NS (0x40104000u)
+ /** Peripheral DMA0 base pointer */
+ #define DMA0 ((DMA_Type *)DMA0_BASE)
+ /** Peripheral DMA0 base pointer */
+ #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS)
+ /** Peripheral DMA1 base address */
+ #define DMA1_BASE (0x50105000u)
+ /** Peripheral DMA1 base address */
+ #define DMA1_BASE_NS (0x40105000u)
+ /** Peripheral DMA1 base pointer */
+ #define DMA1 ((DMA_Type *)DMA1_BASE)
+ /** Peripheral DMA1 base pointer */
+ #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS)
+ /** Array initializer of DMA peripheral base addresses */
+ #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE }
+ /** Array initializer of DMA peripheral base pointers */
+ #define DMA_BASE_PTRS { DMA0, DMA1 }
+ /** Array initializer of DMA peripheral base addresses */
+ #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS }
+ /** Array initializer of DMA peripheral base pointers */
+ #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS }
+#else
+ /** Peripheral DMA0 base address */
+ #define DMA0_BASE (0x40104000u)
+ /** Peripheral DMA0 base pointer */
+ #define DMA0 ((DMA_Type *)DMA0_BASE)
+ /** Peripheral DMA1 base address */
+ #define DMA1_BASE (0x40105000u)
+ /** Peripheral DMA1 base pointer */
+ #define DMA1 ((DMA_Type *)DMA1_BASE)
+ /** Array initializer of DMA peripheral base addresses */
+ #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE }
+ /** Array initializer of DMA peripheral base pointers */
+ #define DMA_BASE_PTRS { DMA0, DMA1 }
+#endif
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMIC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
+ * @{
+ */
+
+/** DMIC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x100 */
+ __IO uint32_t OSR; /**< Oversample Rate, array offset: 0x0, array step: 0x100 */
+ __IO uint32_t DIVHFCLK; /**< DMIC Clock, array offset: 0x4, array step: 0x100 */
+ __IO uint32_t PREAC2FSCOEF; /**< Compensation Filter for 2 FS, array offset: 0x8, array step: 0x100 */
+ __IO uint32_t PREAC4FSCOEF; /**< Compensation Filter for 4 FS, array offset: 0xC, array step: 0x100 */
+ __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift, array offset: 0x10, array step: 0x100 */
+ uint8_t RESERVED_0[108];
+ __IO uint32_t FIFO_CTRL; /**< FIFO Control, array offset: 0x80, array step: 0x100 */
+ __IO uint32_t FIFO_STATUS; /**< FIFO Status, array offset: 0x84, array step: 0x100 */
+ __I uint32_t FIFO_DATA; /**< FIFO Data, array offset: 0x88, array step: 0x100 */
+ __IO uint32_t PHY_CTRL; /**< Physical Control, array offset: 0x8C, array step: 0x100 */
+ __IO uint32_t DC_CTRL; /**< DC Filter Control, array offset: 0x90, array step: 0x100 */
+ uint8_t RESERVED_1[108];
+ } CHANNEL[8];
+ uint8_t RESERVED_0[1792];
+ __IO uint32_t CHANEN; /**< Channel Enable, offset: 0xF00 */
+ uint8_t RESERVED_1[12];
+ __IO uint32_t USE2FS; /**< Use 2 FS register, offset: 0xF10 */
+ __IO uint32_t GLOBAL_SYNC_EN; /**< Global Channel Synchronization Enable, offset: 0xF14 */
+ __IO uint32_t GLOBAL_COUNT_VAL; /**< Global channel synchronization counter value, offset: 0xF18 */
+ __IO uint32_t DECRESET; /**< DMIC decimator reset, offset: 0xF1C */
+ uint8_t RESERVED_2[96];
+ __IO uint32_t HWVADGAIN; /**< HWVAD Input Gain, offset: 0xF80 */
+ __IO uint32_t HWVADHPFS; /**< HWVAD Filter Control, offset: 0xF84 */
+ __IO uint32_t HWVADST10; /**< HWVAD Control, offset: 0xF88 */
+ __IO uint32_t HWVADRSTT; /**< HWVAD Filter Reset, offset: 0xF8C */
+ __IO uint32_t HWVADTHGN; /**< HWVAD Noise Estimator Gain, offset: 0xF90 */
+ __IO uint32_t HWVADTHGS; /**< HWVAD Signal Estimator Gain, offset: 0xF94 */
+ __I uint32_t HWVADLOWZ; /**< HWVAD Noise Envelope Estimator, offset: 0xF98 */
+} DMIC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMIC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Register_Masks DMIC Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_OSR - Oversample Rate */
+/*! @{ */
+#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU)
+#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U)
+/*! OSR - Oversample Rate
+ */
+#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_OSR */
+#define DMIC_CHANNEL_OSR_COUNT (8U)
+
+/*! @name CHANNEL_DIVHFCLK - DMIC Clock */
+/*! @{ */
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU)
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U)
+/*! PDMDIV - PDM Clock Divider Value
+ * 0b0000..Divide by 1
+ * 0b0001..Divide by 2
+ * 0b0010..Divide by 3
+ * 0b0011..Divide by 4
+ * 0b0100..Divide by 6
+ * 0b0101..Divide by 8
+ * 0b0110..Divide by 12
+ * 0b0111..Divide by 16
+ * 0b1000..Divide by 24
+ * 0b1001..Divide by 32
+ * 0b1010..Divide by 48
+ * 0b1011..Divide by 64
+ * 0b1100..Divide by 96
+ * 0b1101..Divide by 128
+ * 0b1110-0b1111..Reserved
+ */
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_DIVHFCLK */
+#define DMIC_CHANNEL_DIVHFCLK_COUNT (8U)
+
+/*! @name CHANNEL_PREAC2FSCOEF - Compensation Filter for 2 FS */
+/*! @{ */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U)
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U)
+/*! COMP - Compensation value
+ * 0b00..Compensation = 0. This is the recommended setting.
+ * 0b01..Compensation = -0.16
+ * 0b10..Compensation = -0.15
+ * 0b11..Compensation = -0.13
+ */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (8U)
+
+/*! @name CHANNEL_PREAC4FSCOEF - Compensation Filter for 4 FS */
+/*! @{ */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U)
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U)
+/*! COMP - Compensation value
+ * 0b00..Compensation = 0. This is the recommended setting.
+ * 0b01..Compensation = -0.16
+ * 0b10..Compensation = -0.15
+ * 0b11..Compensation = -0.13
+ */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (8U)
+
+/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift */
+/*! @{ */
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x1FU)
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U)
+/*! GAIN - Gain
+ */
+#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_GAINSHIFT */
+#define DMIC_CHANNEL_GAINSHIFT_COUNT (8U)
+
+/*! @name CHANNEL_FIFO_CTRL - FIFO Control */
+/*! @{ */
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U)
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U)
+/*! ENABLE - FIFO Enable.
+ * 0b0..Disabled.
+ * 0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U)
+/*! RESETN - FIFO Reset
+ * 0b0..Reset the FIFO. This must be cleared before resuming operation.
+ * 0b1..Normal operation
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U)
+/*! INTEN - Interrupt Enable.
+ * 0b0..FIFO level interrupts are not enabled.
+ * 0b1..FIFO level interrupts are enabled.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U)
+/*! DMAEN - DMA Enable
+ * 0b0..DMA requests are not enabled.
+ * 0b1..DMA requests based on FIFO level are enabled.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U)
+/*! TRIGLVL - FIFO Trigger Level for Interrupt
+ * 0b00000..Trigger when the FIFO has received one entry (is no longer empty).
+ * 0b00001..Trigger when the FIFO has received two entries.
+ * 0b01110..Trigger when the FIFO has received 15 entries.
+ * 0b01111..Trigger when the FIFO has received 16 entries (has become full).
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_CTRL */
+#define DMIC_CHANNEL_FIFO_CTRL_COUNT (8U)
+
+/*! @name CHANNEL_FIFO_STATUS - FIFO Status */
+/*! @{ */
+#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U)
+#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U)
+/*! INT - Status of Interrupt (write 1 to clear)
+ */
+#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U)
+/*! OVERRUN - Overrun Detected (write 1 to clear)
+ */
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U)
+/*! UNDERRUN - Underrun Detected (write 1 to clear)
+ */
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_STATUS */
+#define DMIC_CHANNEL_FIFO_STATUS_COUNT (8U)
+
+/*! @name CHANNEL_FIFO_DATA - FIFO Data */
+/*! @{ */
+#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU)
+#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U)
+/*! DATA - PCM Data
+ */
+#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_DATA */
+#define DMIC_CHANNEL_FIFO_DATA_COUNT (8U)
+
+/*! @name CHANNEL_PHY_CTRL - Physical Control */
+/*! @{ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U)
+/*! PHY_FALL - Capture DMIC on Falling edge (0 means on rising)
+ * 0b0..Capture PDM_DATA on the rising edge of PDM_CLK.
+ * 0b1..Capture PDM_DATA on the falling edge of PDM_CLK.
+ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U)
+/*! PHY_HALF - Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)
+ * 0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
+ * 0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate that the decimator is providing.
+ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PHY_CTRL */
+#define DMIC_CHANNEL_PHY_CTRL_COUNT (8U)
+
+/*! @name CHANNEL_DC_CTRL - DC Filter Control */
+/*! @{ */
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U)
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U)
+/*! DCPOLE - DC Block Filter
+ * 0b00..Flat Response, no filter
+ * 0b01..155 Hz
+ * 0b10..78 Hz
+ * 0b11..39 Hz
+ */
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U)
+/*! DCGAIN - DC Gain
+ */
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
+/*! SATURATEAT16BIT - Saturate at 16 Bit
+ * 0b0..Do not Saturate. Results roll over if out range and do not saturate.
+ * 0b1..Saturate. If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
+ */
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
+#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK (0x200U)
+#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_SHIFT (9U)
+/*! SIGNEXTEND - Sign Extend
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_DC_CTRL */
+#define DMIC_CHANNEL_DC_CTRL_COUNT (8U)
+
+/*! @name CHANEN - Channel Enable */
+/*! @{ */
+#define DMIC_CHANEN_EN_CH0_MASK (0x1U)
+#define DMIC_CHANEN_EN_CH0_SHIFT (0U)
+/*! EN_CH0 - Enable Channel n
+ * 0b0..PDM channel n is disabled.
+ * 0b1..PDM channel n is enabled.
+ */
+#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
+#define DMIC_CHANEN_EN_CH1_MASK (0x2U)
+#define DMIC_CHANEN_EN_CH1_SHIFT (1U)
+/*! EN_CH1 - Enable Channel n
+ * 0b0..PDM channel n is disabled.
+ * 0b1..PDM channel n is enabled.
+ */
+#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
+#define DMIC_CHANEN_EN_CH2_MASK (0x4U)
+#define DMIC_CHANEN_EN_CH2_SHIFT (2U)
+/*! EN_CH2 - Enable Channel n
+ * 0b0..PDM channel n is disabled.
+ * 0b1..PDM channel n is enabled.
+ */
+#define DMIC_CHANEN_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH2_SHIFT)) & DMIC_CHANEN_EN_CH2_MASK)
+#define DMIC_CHANEN_EN_CH3_MASK (0x8U)
+#define DMIC_CHANEN_EN_CH3_SHIFT (3U)
+/*! EN_CH3 - Enable Channel n
+ * 0b0..PDM channel n is disabled.
+ * 0b1..PDM channel n is enabled.
+ */
+#define DMIC_CHANEN_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH3_SHIFT)) & DMIC_CHANEN_EN_CH3_MASK)
+#define DMIC_CHANEN_EN_CH4_MASK (0x10U)
+#define DMIC_CHANEN_EN_CH4_SHIFT (4U)
+/*! EN_CH4 - Enable Channel n
+ * 0b0..PDM channel n is disabled.
+ * 0b1..PDM channel n is enabled.
+ */
+#define DMIC_CHANEN_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH4_SHIFT)) & DMIC_CHANEN_EN_CH4_MASK)
+#define DMIC_CHANEN_EN_CH5_MASK (0x20U)
+#define DMIC_CHANEN_EN_CH5_SHIFT (5U)
+/*! EN_CH5 - Enable Channel n
+ * 0b0..PDM channel n is disabled.
+ * 0b1..PDM channel n is enabled.
+ */
+#define DMIC_CHANEN_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH5_SHIFT)) & DMIC_CHANEN_EN_CH5_MASK)
+#define DMIC_CHANEN_EN_CH6_MASK (0x40U)
+#define DMIC_CHANEN_EN_CH6_SHIFT (6U)
+/*! EN_CH6 - Enable Channel n
+ * 0b0..PDM channel n is disabled.
+ * 0b1..PDM channel n is enabled.
+ */
+#define DMIC_CHANEN_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH6_SHIFT)) & DMIC_CHANEN_EN_CH6_MASK)
+#define DMIC_CHANEN_EN_CH7_MASK (0x80U)
+#define DMIC_CHANEN_EN_CH7_SHIFT (7U)
+/*! EN_CH7 - Enable Channel n
+ * 0b0..PDM channel n is disabled.
+ * 0b1..PDM channel n is enabled.
+ */
+#define DMIC_CHANEN_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH7_SHIFT)) & DMIC_CHANEN_EN_CH7_MASK)
+/*! @} */
+
+/*! @name USE2FS - Use 2 FS register */
+/*! @{ */
+#define DMIC_USE2FS_USE2FS_MASK (0x1U)
+#define DMIC_USE2FS_USE2FS_SHIFT (0U)
+/*! USE2FS - Use 2FS register
+ * 0b0..Use 1 FS output for PCM data.
+ * 0b1..Use 2 FS output for PCM data.
+ */
+#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
+/*! @} */
+
+/*! @name GLOBAL_SYNC_EN - Global Channel Synchronization Enable */
+/*! @{ */
+#define DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_MASK (0xFFU)
+#define DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_SHIFT (0U)
+/*! CH_SYNC_EN - Channel synch enable
+ */
+#define DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_SHIFT)) & DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_MASK)
+/*! @} */
+
+/*! @name GLOBAL_COUNT_VAL - Global channel synchronization counter value */
+/*! @{ */
+#define DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_MASK (0xFFFFFFFFU)
+#define DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_SHIFT (0U)
+/*! CCOUNTVAL - Channel Counter Value
+ */
+#define DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_SHIFT)) & DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_MASK)
+/*! @} */
+
+/*! @name DECRESET - DMIC decimator reset */
+/*! @{ */
+#define DMIC_DECRESET_DECRESET_MASK (0xFFU)
+#define DMIC_DECRESET_DECRESET_SHIFT (0U)
+/*! DECRESET - Decimator reset
+ * 0b00000000..Disable
+ * 0b00000001..Enable
+ */
+#define DMIC_DECRESET_DECRESET(x) (((uint32_t)(((uint32_t)(x)) << DMIC_DECRESET_DECRESET_SHIFT)) & DMIC_DECRESET_DECRESET_MASK)
+/*! @} */
+
+/*! @name HWVADGAIN - HWVAD Input Gain */
+/*! @{ */
+#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU)
+#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U)
+/*! INPUTGAIN - Input Gain
+ * 0b0000..-10 bits
+ * 0b0001..-8 bits
+ * 0b0010..-6 bits
+ * 0b0011..-4 bits
+ * 0b0100..-2 bits
+ * 0b0101..0 bits (default)
+ * 0b0110..+2 bits
+ * 0b0111..+4 bits
+ * 0b1000..+6 bits
+ * 0b1001..+8 bits
+ * 0b1010..+10 bits
+ * 0b1011..+12 bits
+ * 0b1100..+14 bits
+ * 0b1101-0b1111..Reserved
+ */
+#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
+/*! @} */
+
+/*! @name HWVADHPFS - HWVAD Filter Control */
+/*! @{ */
+#define DMIC_HWVADHPFS_HPFS_MASK (0x3U)
+#define DMIC_HWVADHPFS_HPFS_SHIFT (0U)
+/*! HPFS - The HPFS field chooses the High Pass filter in first part of HWVAD.
+ * 0b00..Bypass
+ * 0b01..High Pass 1750 Hz
+ * 0b10..High Pass 215 Hz
+ * 0b11..Reserved
+ */
+#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
+/*! @} */
+
+/*! @name HWVADST10 - HWVAD Control */
+/*! @{ */
+#define DMIC_HWVADST10_ST10_MASK (0x1U)
+#define DMIC_HWVADST10_ST10_SHIFT (0U)
+/*! ST10 - STAGE 1
+ * 0b0..Normal operation, waiting for HWVAD trigger event (stage 0).
+ * 0b1..Reset internal interrupt flag by writing a '1' (stage 1) pulse.
+ */
+#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
+/*! @} */
+
+/*! @name HWVADRSTT - HWVAD Filter Reset */
+/*! @{ */
+#define DMIC_HWVADRSTT_RSST_MASK (0x1U)
+#define DMIC_HWVADRSTT_RSST_SHIFT (0U)
+/*! RSST - Reset HWVAD
+ */
+#define DMIC_HWVADRSTT_RSST(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSST_SHIFT)) & DMIC_HWVADRSTT_RSST_MASK)
+/*! @} */
+
+/*! @name HWVADTHGN - HWVAD Noise Estimator Gain */
+/*! @{ */
+#define DMIC_HWVADTHGN_THGN_MASK (0xFU)
+#define DMIC_HWVADTHGN_THGN_SHIFT (0U)
+/*! THGN - Gain Factor for Noise Estimator
+ */
+#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
+/*! @} */
+
+/*! @name HWVADTHGS - HWVAD Signal Estimator Gain */
+/*! @{ */
+#define DMIC_HWVADTHGS_THGS_MASK (0xFU)
+#define DMIC_HWVADTHGS_THGS_SHIFT (0U)
+/*! THGS - Signal Gain Factor
+ */
+#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
+/*! @} */
+
+/*! @name HWVADLOWZ - HWVAD Noise Envelope Estimator */
+/*! @{ */
+#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU)
+#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U)
+/*! LOWZ - Average Noise-floor Value
+ */
+#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group DMIC_Register_Masks */
+
+
+/* DMIC - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral DMIC0 base address */
+ #define DMIC0_BASE (0x50121000u)
+ /** Peripheral DMIC0 base address */
+ #define DMIC0_BASE_NS (0x40121000u)
+ /** Peripheral DMIC0 base pointer */
+ #define DMIC0 ((DMIC_Type *)DMIC0_BASE)
+ /** Peripheral DMIC0 base pointer */
+ #define DMIC0_NS ((DMIC_Type *)DMIC0_BASE_NS)
+ /** Array initializer of DMIC peripheral base addresses */
+ #define DMIC_BASE_ADDRS { DMIC0_BASE }
+ /** Array initializer of DMIC peripheral base pointers */
+ #define DMIC_BASE_PTRS { DMIC0 }
+ /** Array initializer of DMIC peripheral base addresses */
+ #define DMIC_BASE_ADDRS_NS { DMIC0_BASE_NS }
+ /** Array initializer of DMIC peripheral base pointers */
+ #define DMIC_BASE_PTRS_NS { DMIC0_NS }
+#else
+ /** Peripheral DMIC0 base address */
+ #define DMIC0_BASE (0x40121000u)
+ /** Peripheral DMIC0 base pointer */
+ #define DMIC0 ((DMIC_Type *)DMIC0_BASE)
+ /** Array initializer of DMIC peripheral base addresses */
+ #define DMIC_BASE_ADDRS { DMIC0_BASE }
+ /** Array initializer of DMIC peripheral base pointers */
+ #define DMIC_BASE_PTRS { DMIC0 }
+#endif
+/** Interrupt vectors for the DMIC peripheral type */
+#define DMIC_IRQS { DMIC0_IRQn }
+#define DMIC_HWVAD_IRQS { HWVAD0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMIC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FLEXCOMM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXCOMM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[4088];
+ __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm module ID, offset: 0xFF8 */
+ __I uint32_t PID; /**< Peripheral Identification, offset: 0xFFC */
+} FLEXCOMM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FLEXCOMM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
+ * @{
+ */
+
+/*! @name PSELID - Peripheral Select and Flexcomm module ID */
+/*! @{ */
+#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)
+#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)
+/*! PERSEL - Peripheral Select
+ * 0b000..No peripheral selected.
+ * 0b001..USART function selected
+ * 0b010..SPI function selected
+ * 0b011..I2C
+ * 0b100..I2S Transmit
+ * 0b101..I2S Receive
+ * 0b110..Reserved
+ * 0b111..Reserved
+ */
+#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
+#define FLEXCOMM_PSELID_LOCK_MASK (0x8U)
+#define FLEXCOMM_PSELID_LOCK_SHIFT (3U)
+/*! LOCK - Lock the peripheral select
+ * 0b0..Peripheral select can be changed by software.
+ * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm module or the entire device is reset.
+ */
+#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
+#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U)
+#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U)
+/*! USARTPRESENT - USART present indicator
+ * 0b0..This Flexcomm module does not include the USART function.
+ * 0b1..This Flexcomm module includes the USART function.
+ */
+#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
+#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U)
+#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U)
+/*! SPIPRESENT - SPI present indicator
+ * 0b0..This Flexcomm module does not include the SPI function.
+ * 0b1..This Flexcomm module includes the SPI function.
+ */
+#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U)
+#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U)
+/*! I2CPRESENT - I2C present indicator
+ * 0b0..I2C Not Present
+ * 0b1..I2C Present
+ */
+#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U)
+#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U)
+/*! I2SPRESENT - I2S Present
+ * 0b0..I2S Not Present
+ * 0b1..I2S Present
+ */
+#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
+#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U)
+#define FLEXCOMM_PSELID_ID_SHIFT (12U)
+/*! ID - Flexcomm ID
+ */
+#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
+/*! @} */
+
+/*! @name PID - Peripheral Identification */
+/*! @{ */
+#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U)
+#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U)
+/*! Minor_Rev - Minor revision of module implementation
+ */
+#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
+#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U)
+#define FLEXCOMM_PID_Major_Rev_SHIFT (12U)
+/*! Major_Rev - Major revision of module implementation
+ */
+#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
+#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U)
+#define FLEXCOMM_PID_ID_SHIFT (16U)
+/*! ID - Module identifier for the selected function
+ */
+#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Register_Masks */
+
+
+/* FLEXCOMM - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral FLEXCOMM0 base address */
+ #define FLEXCOMM0_BASE (0x50106000u)
+ /** Peripheral FLEXCOMM0 base address */
+ #define FLEXCOMM0_BASE_NS (0x40106000u)
+ /** Peripheral FLEXCOMM0 base pointer */
+ #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
+ /** Peripheral FLEXCOMM0 base pointer */
+ #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS)
+ /** Peripheral FLEXCOMM1 base address */
+ #define FLEXCOMM1_BASE (0x50107000u)
+ /** Peripheral FLEXCOMM1 base address */
+ #define FLEXCOMM1_BASE_NS (0x40107000u)
+ /** Peripheral FLEXCOMM1 base pointer */
+ #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
+ /** Peripheral FLEXCOMM1 base pointer */
+ #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS)
+ /** Peripheral FLEXCOMM2 base address */
+ #define FLEXCOMM2_BASE (0x50108000u)
+ /** Peripheral FLEXCOMM2 base address */
+ #define FLEXCOMM2_BASE_NS (0x40108000u)
+ /** Peripheral FLEXCOMM2 base pointer */
+ #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
+ /** Peripheral FLEXCOMM2 base pointer */
+ #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS)
+ /** Peripheral FLEXCOMM3 base address */
+ #define FLEXCOMM3_BASE (0x50109000u)
+ /** Peripheral FLEXCOMM3 base address */
+ #define FLEXCOMM3_BASE_NS (0x40109000u)
+ /** Peripheral FLEXCOMM3 base pointer */
+ #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
+ /** Peripheral FLEXCOMM3 base pointer */
+ #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS)
+ /** Peripheral FLEXCOMM4 base address */
+ #define FLEXCOMM4_BASE (0x50122000u)
+ /** Peripheral FLEXCOMM4 base address */
+ #define FLEXCOMM4_BASE_NS (0x40122000u)
+ /** Peripheral FLEXCOMM4 base pointer */
+ #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
+ /** Peripheral FLEXCOMM4 base pointer */
+ #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS)
+ /** Peripheral FLEXCOMM5 base address */
+ #define FLEXCOMM5_BASE (0x50123000u)
+ /** Peripheral FLEXCOMM5 base address */
+ #define FLEXCOMM5_BASE_NS (0x40123000u)
+ /** Peripheral FLEXCOMM5 base pointer */
+ #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
+ /** Peripheral FLEXCOMM5 base pointer */
+ #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS)
+ /** Peripheral FLEXCOMM6 base address */
+ #define FLEXCOMM6_BASE (0x50124000u)
+ /** Peripheral FLEXCOMM6 base address */
+ #define FLEXCOMM6_BASE_NS (0x40124000u)
+ /** Peripheral FLEXCOMM6 base pointer */
+ #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
+ /** Peripheral FLEXCOMM6 base pointer */
+ #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS)
+ /** Peripheral FLEXCOMM7 base address */
+ #define FLEXCOMM7_BASE (0x50125000u)
+ /** Peripheral FLEXCOMM7 base address */
+ #define FLEXCOMM7_BASE_NS (0x40125000u)
+ /** Peripheral FLEXCOMM7 base pointer */
+ #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
+ /** Peripheral FLEXCOMM7 base pointer */
+ #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS)
+ /** Peripheral FLEXCOMM8 base address */
+ #define FLEXCOMM8_BASE (0x50209000u)
+ /** Peripheral FLEXCOMM8 base address */
+ #define FLEXCOMM8_BASE_NS (0x40209000u)
+ /** Peripheral FLEXCOMM8 base pointer */
+ #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
+ /** Peripheral FLEXCOMM8 base pointer */
+ #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS)
+ /** Peripheral FLEXCOMM9 base address */
+ #define FLEXCOMM9_BASE (0x5020A000u)
+ /** Peripheral FLEXCOMM9 base address */
+ #define FLEXCOMM9_BASE_NS (0x4020A000u)
+ /** Peripheral FLEXCOMM9 base pointer */
+ #define FLEXCOMM9 ((FLEXCOMM_Type *)FLEXCOMM9_BASE)
+ /** Peripheral FLEXCOMM9 base pointer */
+ #define FLEXCOMM9_NS ((FLEXCOMM_Type *)FLEXCOMM9_BASE_NS)
+ /** Peripheral FLEXCOMM10 base address */
+ #define FLEXCOMM10_BASE (0x5020B000u)
+ /** Peripheral FLEXCOMM10 base address */
+ #define FLEXCOMM10_BASE_NS (0x4020B000u)
+ /** Peripheral FLEXCOMM10 base pointer */
+ #define FLEXCOMM10 ((FLEXCOMM_Type *)FLEXCOMM10_BASE)
+ /** Peripheral FLEXCOMM10 base pointer */
+ #define FLEXCOMM10_NS ((FLEXCOMM_Type *)FLEXCOMM10_BASE_NS)
+ /** Peripheral FLEXCOMM11 base address */
+ #define FLEXCOMM11_BASE (0x5020C000u)
+ /** Peripheral FLEXCOMM11 base address */
+ #define FLEXCOMM11_BASE_NS (0x4020C000u)
+ /** Peripheral FLEXCOMM11 base pointer */
+ #define FLEXCOMM11 ((FLEXCOMM_Type *)FLEXCOMM11_BASE)
+ /** Peripheral FLEXCOMM11 base pointer */
+ #define FLEXCOMM11_NS ((FLEXCOMM_Type *)FLEXCOMM11_BASE_NS)
+ /** Peripheral FLEXCOMM12 base address */
+ #define FLEXCOMM12_BASE (0x5020D000u)
+ /** Peripheral FLEXCOMM12 base address */
+ #define FLEXCOMM12_BASE_NS (0x4020D000u)
+ /** Peripheral FLEXCOMM12 base pointer */
+ #define FLEXCOMM12 ((FLEXCOMM_Type *)FLEXCOMM12_BASE)
+ /** Peripheral FLEXCOMM12 base pointer */
+ #define FLEXCOMM12_NS ((FLEXCOMM_Type *)FLEXCOMM12_BASE_NS)
+ /** Peripheral FLEXCOMM13 base address */
+ #define FLEXCOMM13_BASE (0x5020E000u)
+ /** Peripheral FLEXCOMM13 base address */
+ #define FLEXCOMM13_BASE_NS (0x4020E000u)
+ /** Peripheral FLEXCOMM13 base pointer */
+ #define FLEXCOMM13 ((FLEXCOMM_Type *)FLEXCOMM13_BASE)
+ /** Peripheral FLEXCOMM13 base pointer */
+ #define FLEXCOMM13_NS ((FLEXCOMM_Type *)FLEXCOMM13_BASE_NS)
+ /** Peripheral FLEXCOMM14 base address */
+ #define FLEXCOMM14_BASE (0x50126000u)
+ /** Peripheral FLEXCOMM14 base address */
+ #define FLEXCOMM14_BASE_NS (0x40126000u)
+ /** Peripheral FLEXCOMM14 base pointer */
+ #define FLEXCOMM14 ((FLEXCOMM_Type *)FLEXCOMM14_BASE)
+ /** Peripheral FLEXCOMM14 base pointer */
+ #define FLEXCOMM14_NS ((FLEXCOMM_Type *)FLEXCOMM14_BASE_NS)
+ /** Peripheral FLEXCOMM15 base address */
+ #define FLEXCOMM15_BASE (0x50127000u)
+ /** Peripheral FLEXCOMM15 base address */
+ #define FLEXCOMM15_BASE_NS (0x40127000u)
+ /** Peripheral FLEXCOMM15 base pointer */
+ #define FLEXCOMM15 ((FLEXCOMM_Type *)FLEXCOMM15_BASE)
+ /** Peripheral FLEXCOMM15 base pointer */
+ #define FLEXCOMM15_NS ((FLEXCOMM_Type *)FLEXCOMM15_BASE_NS)
+ /** Peripheral FLEXCOMM16 base address */
+ #define FLEXCOMM16_BASE (0x50128000u)
+ /** Peripheral FLEXCOMM16 base address */
+ #define FLEXCOMM16_BASE_NS (0x40128000u)
+ /** Peripheral FLEXCOMM16 base pointer */
+ #define FLEXCOMM16 ((FLEXCOMM_Type *)FLEXCOMM16_BASE)
+ /** Peripheral FLEXCOMM16 base pointer */
+ #define FLEXCOMM16_NS ((FLEXCOMM_Type *)FLEXCOMM16_BASE_NS)
+ /** Array initializer of FLEXCOMM peripheral base addresses */
+ #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE, FLEXCOMM10_BASE, FLEXCOMM11_BASE, FLEXCOMM12_BASE, FLEXCOMM13_BASE, FLEXCOMM14_BASE, FLEXCOMM15_BASE, FLEXCOMM16_BASE }
+ /** Array initializer of FLEXCOMM peripheral base pointers */
+ #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9, FLEXCOMM10, FLEXCOMM11, FLEXCOMM12, FLEXCOMM13, FLEXCOMM14, FLEXCOMM15, FLEXCOMM16 }
+ /** Array initializer of FLEXCOMM peripheral base addresses */
+ #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS, FLEXCOMM9_BASE_NS, FLEXCOMM10_BASE_NS, FLEXCOMM11_BASE_NS, FLEXCOMM12_BASE_NS, FLEXCOMM13_BASE_NS, FLEXCOMM14_BASE_NS, FLEXCOMM15_BASE_NS, FLEXCOMM16_BASE_NS }
+ /** Array initializer of FLEXCOMM peripheral base pointers */
+ #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS, FLEXCOMM9_NS, FLEXCOMM10_NS, FLEXCOMM11_NS, FLEXCOMM12_NS, FLEXCOMM13_NS, FLEXCOMM14_NS, FLEXCOMM15_NS, FLEXCOMM16_NS }
+#else
+ /** Peripheral FLEXCOMM0 base address */
+ #define FLEXCOMM0_BASE (0x40106000u)
+ /** Peripheral FLEXCOMM0 base pointer */
+ #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
+ /** Peripheral FLEXCOMM1 base address */
+ #define FLEXCOMM1_BASE (0x40107000u)
+ /** Peripheral FLEXCOMM1 base pointer */
+ #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
+ /** Peripheral FLEXCOMM2 base address */
+ #define FLEXCOMM2_BASE (0x40108000u)
+ /** Peripheral FLEXCOMM2 base pointer */
+ #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
+ /** Peripheral FLEXCOMM3 base address */
+ #define FLEXCOMM3_BASE (0x40109000u)
+ /** Peripheral FLEXCOMM3 base pointer */
+ #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
+ /** Peripheral FLEXCOMM4 base address */
+ #define FLEXCOMM4_BASE (0x40122000u)
+ /** Peripheral FLEXCOMM4 base pointer */
+ #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
+ /** Peripheral FLEXCOMM5 base address */
+ #define FLEXCOMM5_BASE (0x40123000u)
+ /** Peripheral FLEXCOMM5 base pointer */
+ #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
+ /** Peripheral FLEXCOMM6 base address */
+ #define FLEXCOMM6_BASE (0x40124000u)
+ /** Peripheral FLEXCOMM6 base pointer */
+ #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
+ /** Peripheral FLEXCOMM7 base address */
+ #define FLEXCOMM7_BASE (0x40125000u)
+ /** Peripheral FLEXCOMM7 base pointer */
+ #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
+ /** Peripheral FLEXCOMM8 base address */
+ #define FLEXCOMM8_BASE (0x40209000u)
+ /** Peripheral FLEXCOMM8 base pointer */
+ #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
+ /** Peripheral FLEXCOMM9 base address */
+ #define FLEXCOMM9_BASE (0x4020A000u)
+ /** Peripheral FLEXCOMM9 base pointer */
+ #define FLEXCOMM9 ((FLEXCOMM_Type *)FLEXCOMM9_BASE)
+ /** Peripheral FLEXCOMM10 base address */
+ #define FLEXCOMM10_BASE (0x4020B000u)
+ /** Peripheral FLEXCOMM10 base pointer */
+ #define FLEXCOMM10 ((FLEXCOMM_Type *)FLEXCOMM10_BASE)
+ /** Peripheral FLEXCOMM11 base address */
+ #define FLEXCOMM11_BASE (0x4020C000u)
+ /** Peripheral FLEXCOMM11 base pointer */
+ #define FLEXCOMM11 ((FLEXCOMM_Type *)FLEXCOMM11_BASE)
+ /** Peripheral FLEXCOMM12 base address */
+ #define FLEXCOMM12_BASE (0x4020D000u)
+ /** Peripheral FLEXCOMM12 base pointer */
+ #define FLEXCOMM12 ((FLEXCOMM_Type *)FLEXCOMM12_BASE)
+ /** Peripheral FLEXCOMM13 base address */
+ #define FLEXCOMM13_BASE (0x4020E000u)
+ /** Peripheral FLEXCOMM13 base pointer */
+ #define FLEXCOMM13 ((FLEXCOMM_Type *)FLEXCOMM13_BASE)
+ /** Peripheral FLEXCOMM14 base address */
+ #define FLEXCOMM14_BASE (0x40126000u)
+ /** Peripheral FLEXCOMM14 base pointer */
+ #define FLEXCOMM14 ((FLEXCOMM_Type *)FLEXCOMM14_BASE)
+ /** Peripheral FLEXCOMM15 base address */
+ #define FLEXCOMM15_BASE (0x40127000u)
+ /** Peripheral FLEXCOMM15 base pointer */
+ #define FLEXCOMM15 ((FLEXCOMM_Type *)FLEXCOMM15_BASE)
+ /** Peripheral FLEXCOMM16 base address */
+ #define FLEXCOMM16_BASE (0x40128000u)
+ /** Peripheral FLEXCOMM16 base pointer */
+ #define FLEXCOMM16 ((FLEXCOMM_Type *)FLEXCOMM16_BASE)
+ /** Array initializer of FLEXCOMM peripheral base addresses */
+ #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE, FLEXCOMM10_BASE, FLEXCOMM11_BASE, FLEXCOMM12_BASE, FLEXCOMM13_BASE, FLEXCOMM14_BASE, FLEXCOMM15_BASE, FLEXCOMM16_BASE }
+ /** Array initializer of FLEXCOMM peripheral base pointers */
+ #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9, FLEXCOMM10, FLEXCOMM11, FLEXCOMM12, FLEXCOMM13, FLEXCOMM14, FLEXCOMM15, FLEXCOMM16 }
+#endif
+/** Interrupt vectors for the FLEXCOMM peripheral type */
+#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn, FLEXCOMM11_IRQn, FLEXCOMM12_IRQn, FLEXCOMM13_IRQn, FLEXCOMM14_IRQn, FLEXCOMM15_IRQn, FLEXCOMM16_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FLEXIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXIO - Register Layout Typedef */
+typedef struct {
+ __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
+ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
+ __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
+ __I uint32_t PIN; /**< Pin State Register, offset: 0xC */
+ __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
+ __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
+ __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
+ __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
+ __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t TIMERSDEN; /**< Timer Status DMA Enable, offset: 0x38 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t TRGSTAT; /**< Trigger Status Register, offset: 0x48 */
+ __IO uint32_t TRIGIEN; /**< External Trigger Interrupt Enable Register, offset: 0x4C */
+ __IO uint32_t PINSTAT; /**< Pin Status Register, offset: 0x50 */
+ __IO uint32_t PINIEN; /**< Pin Interrupt Enable Register, offset: 0x54 */
+ __IO uint32_t PINREN; /**< Pin Rising Edge Enable Register, offset: 0x58 */
+ __IO uint32_t PINFEN; /**< Pin Falling Edge Enable Register, offset: 0x5C */
+ __IO uint32_t PINOUTD; /**< Pin Output Data Register, offset: 0x60 */
+ __IO uint32_t PINOUTE; /**< Pin Output Enable Register, offset: 0x64 */
+ __O uint32_t PINOUTDIS; /**< Pin Output Disable Register, offset: 0x68 */
+ __O uint32_t PINOUTCLR; /**< Pin Output Clear Register, offset: 0x6C */
+ __O uint32_t PINOUTSET; /**< Pin Output Set Register, offset: 0x70 */
+ __O uint32_t PINOUTTOG; /**< Pin Output Toggle Register, offset: 0x74 */
+ uint8_t RESERVED_5[8];
+ __IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
+ uint8_t RESERVED_6[96];
+ __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
+ uint8_t RESERVED_7[224];
+ __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
+ uint8_t RESERVED_8[96];
+ __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
+ uint8_t RESERVED_9[96];
+ __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
+ uint8_t RESERVED_10[96];
+ __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
+ uint8_t RESERVED_11[96];
+ __IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
+ uint8_t RESERVED_12[96];
+ __IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
+ uint8_t RESERVED_13[96];
+ __IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
+ uint8_t RESERVED_14[352];
+ __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
+ uint8_t RESERVED_15[96];
+ __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
+ uint8_t RESERVED_16[96];
+ __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
+ uint8_t RESERVED_17[96];
+ __IO uint32_t SHIFTBUFOES[8]; /**< Shifter Buffer N Odd Even Swapped Register, array offset: 0x800, array step: 0x4 */
+ uint8_t RESERVED_18[96];
+ __IO uint32_t SHIFTBUFEOS[8]; /**< Shifter Buffer N Even Odd Swapped Register, array offset: 0x880, array step: 0x4 */
+ uint8_t RESERVED_19[96];
+ __IO uint32_t SHIFTBUFHBS[8]; /**< Shifter Buffer N Halfword Byte Swapped Register, array offset: 0x900, array step: 0x4 */
+} FLEXIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FLEXIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
+#define FLEXIO_VERID_FEATURE_SHIFT (0U)
+/*! FEATURE - Feature Specification Number
+ * 0b0000000000000000..Standard features implemented.
+ * 0b0000000000000001..Supports state, logic and parallel modes.
+ * 0b0000000000000010..Supports pin control registers.
+ * 0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers.
+ */
+#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
+#define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
+#define FLEXIO_VERID_MINOR_SHIFT (16U)
+/*! MINOR - Minor Version Number
+ */
+#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
+#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
+#define FLEXIO_VERID_MAJOR_SHIFT (24U)
+/*! MAJOR - Major Version Number
+ */
+#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
+#define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
+/*! SHIFTER - Shifter Number
+ */
+#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
+#define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
+#define FLEXIO_PARAM_TIMER_SHIFT (8U)
+/*! TIMER - Timer Number
+ */
+#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
+#define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
+#define FLEXIO_PARAM_PIN_SHIFT (16U)
+/*! PIN - Pin Number
+ */
+#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
+#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
+#define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
+/*! TRIGGER - Trigger Number
+ */
+#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
+/*! @} */
+
+/*! @name CTRL - FlexIO Control Register */
+/*! @{ */
+#define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
+#define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
+/*! FLEXEN - FlexIO Enable
+ * 0b0..FlexIO module is disabled.
+ * 0b1..FlexIO module is enabled.
+ */
+#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
+#define FLEXIO_CTRL_SWRST_MASK (0x2U)
+#define FLEXIO_CTRL_SWRST_SHIFT (1U)
+/*! SWRST - Software Reset
+ * 0b0..Software reset is disabled
+ * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
+ */
+#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
+#define FLEXIO_CTRL_FASTACC_MASK (0x4U)
+#define FLEXIO_CTRL_FASTACC_SHIFT (2U)
+/*! FASTACC - Fast Access
+ * 0b0..Configures for normal register accesses to FlexIO
+ * 0b1..Configures for fast register accesses to FlexIO
+ */
+#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
+#define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
+#define FLEXIO_CTRL_DBGE_SHIFT (30U)
+/*! DBGE - Debug Enable
+ * 0b0..FlexIO is disabled in debug modes.
+ * 0b1..FlexIO is enabled in debug modes
+ */
+#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
+#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
+#define FLEXIO_CTRL_DOZEN_SHIFT (31U)
+/*! DOZEN - Doze Enable
+ * 0b0..FlexIO enabled in Doze modes.
+ * 0b1..FlexIO disabled in Doze modes.
+ */
+#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
+/*! @} */
+
+/*! @name PIN - Pin State Register */
+/*! @{ */
+#define FLEXIO_PIN_PDI_MASK (0xFFFFU)
+#define FLEXIO_PIN_PDI_SHIFT (0U)
+/*! PDI - Pin Data Input
+ */
+#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
+/*! @} */
+
+/*! @name SHIFTSTAT - Shifter Status Register */
+/*! @{ */
+#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU)
+#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
+/*! SSF - Shifter Status Flag
+ */
+#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
+/*! @} */
+
+/*! @name SHIFTERR - Shifter Error Register */
+/*! @{ */
+#define FLEXIO_SHIFTERR_SEF_MASK (0xFFU)
+#define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
+/*! SEF - Shifter Error Flags
+ */
+#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
+/*! @} */
+
+/*! @name TIMSTAT - Timer Status Register */
+/*! @{ */
+#define FLEXIO_TIMSTAT_TSF_MASK (0xFFU)
+#define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
+/*! TSF - Timer Status Flags
+ */
+#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
+/*! @} */
+
+/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
+/*! @{ */
+#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU)
+#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
+/*! SSIE - Shifter Status Interrupt Enable
+ */
+#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
+/*! @} */
+
+/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
+/*! @{ */
+#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU)
+#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
+/*! SEIE - Shifter Error Interrupt Enable
+ */
+#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
+/*! @} */
+
+/*! @name TIMIEN - Timer Interrupt Enable Register */
+/*! @{ */
+#define FLEXIO_TIMIEN_TEIE_MASK (0xFFU)
+#define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
+/*! TEIE - Timer Status Interrupt Enable
+ */
+#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
+/*! @} */
+
+/*! @name SHIFTSDEN - Shifter Status DMA Enable */
+/*! @{ */
+#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU)
+#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
+/*! SSDE - Shifter Status DMA Enable
+ */
+#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
+/*! @} */
+
+/*! @name TIMERSDEN - Timer Status DMA Enable */
+/*! @{ */
+#define FLEXIO_TIMERSDEN_TSDE_MASK (0xFFU)
+#define FLEXIO_TIMERSDEN_TSDE_SHIFT (0U)
+/*! TSDE - Timer Status DMA Enable
+ */
+#define FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)
+/*! @} */
+
+/*! @name SHIFTSTATE - Shifter State Register */
+/*! @{ */
+#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
+#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
+/*! STATE - Current State Pointer
+ */
+#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
+/*! @} */
+
+/*! @name TRGSTAT - Trigger Status Register */
+/*! @{ */
+#define FLEXIO_TRGSTAT_ETSF_MASK (0xFFFFU)
+#define FLEXIO_TRGSTAT_ETSF_SHIFT (0U)
+/*! ETSF - External Trigger Status Flags
+ */
+#define FLEXIO_TRGSTAT_ETSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK)
+/*! @} */
+
+/*! @name TRIGIEN - External Trigger Interrupt Enable Register */
+/*! @{ */
+#define FLEXIO_TRIGIEN_TRIE_MASK (0xFFFFU)
+#define FLEXIO_TRIGIEN_TRIE_SHIFT (0U)
+/*! TRIE - External Trigger Interrupt Enable
+ */
+#define FLEXIO_TRIGIEN_TRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK)
+/*! @} */
+
+/*! @name PINSTAT - Pin Status Register */
+/*! @{ */
+#define FLEXIO_PINSTAT_PSF_MASK (0xFFFFU)
+#define FLEXIO_PINSTAT_PSF_SHIFT (0U)
+/*! PSF - Pin Status Flags
+ */
+#define FLEXIO_PINSTAT_PSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK)
+/*! @} */
+
+/*! @name PINIEN - Pin Interrupt Enable Register */
+/*! @{ */
+#define FLEXIO_PINIEN_PSIE_MASK (0xFFFFU)
+#define FLEXIO_PINIEN_PSIE_SHIFT (0U)
+/*! PSIE - Pin Status Interrupt Enable
+ */
+#define FLEXIO_PINIEN_PSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK)
+/*! @} */
+
+/*! @name PINREN - Pin Rising Edge Enable Register */
+/*! @{ */
+#define FLEXIO_PINREN_PRE_MASK (0xFFFFU)
+#define FLEXIO_PINREN_PRE_SHIFT (0U)
+/*! PRE - Pin Rising Edge
+ */
+#define FLEXIO_PINREN_PRE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK)
+/*! @} */
+
+/*! @name PINFEN - Pin Falling Edge Enable Register */
+/*! @{ */
+#define FLEXIO_PINFEN_PFE_MASK (0xFFFFU)
+#define FLEXIO_PINFEN_PFE_SHIFT (0U)
+/*! PFE - Pin Falling Edge
+ */
+#define FLEXIO_PINFEN_PFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK)
+/*! @} */
+
+/*! @name PINOUTD - Pin Output Data Register */
+/*! @{ */
+#define FLEXIO_PINOUTD_OUTD_MASK (0xFFFFU)
+#define FLEXIO_PINOUTD_OUTD_SHIFT (0U)
+/*! OUTD - Output Data
+ */
+#define FLEXIO_PINOUTD_OUTD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK)
+/*! @} */
+
+/*! @name PINOUTE - Pin Output Enable Register */
+/*! @{ */
+#define FLEXIO_PINOUTE_OUTE_MASK (0xFFFFU)
+#define FLEXIO_PINOUTE_OUTE_SHIFT (0U)
+/*! OUTE - Output Enable
+ */
+#define FLEXIO_PINOUTE_OUTE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK)
+/*! @} */
+
+/*! @name PINOUTDIS - Pin Output Disable Register */
+/*! @{ */
+#define FLEXIO_PINOUTDIS_OUTDIS_MASK (0xFFFFU)
+#define FLEXIO_PINOUTDIS_OUTDIS_SHIFT (0U)
+/*! OUTDIS - Output Disable
+ */
+#define FLEXIO_PINOUTDIS_OUTDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK)
+/*! @} */
+
+/*! @name PINOUTCLR - Pin Output Clear Register */
+/*! @{ */
+#define FLEXIO_PINOUTCLR_OUTCLR_MASK (0xFFFFU)
+#define FLEXIO_PINOUTCLR_OUTCLR_SHIFT (0U)
+/*! OUTCLR - Output Clear
+ */
+#define FLEXIO_PINOUTCLR_OUTCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK)
+/*! @} */
+
+/*! @name PINOUTSET - Pin Output Set Register */
+/*! @{ */
+#define FLEXIO_PINOUTSET_OUTSET_MASK (0xFFFFU)
+#define FLEXIO_PINOUTSET_OUTSET_SHIFT (0U)
+/*! OUTSET - Output Set
+ */
+#define FLEXIO_PINOUTSET_OUTSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK)
+/*! @} */
+
+/*! @name PINOUTTOG - Pin Output Toggle Register */
+/*! @{ */
+#define FLEXIO_PINOUTTOG_OUTTOG_MASK (0xFFFFU)
+#define FLEXIO_PINOUTTOG_OUTTOG_SHIFT (0U)
+/*! OUTTOG - Output Toggle
+ */
+#define FLEXIO_PINOUTTOG_OUTTOG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK)
+/*! @} */
+
+/*! @name SHIFTCTL - Shifter Control N Register */
+/*! @{ */
+#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
+#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
+/*! SMOD - Shifter Mode
+ * 0b000..Disabled.
+ * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
+ * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
+ * 0b011..Reserved.
+ * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
+ * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
+ * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
+ * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
+ */
+#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
+#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
+#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
+/*! PINPOL - Shifter Pin Polarity
+ * 0b0..Pin is active high
+ * 0b1..Pin is active low
+ */
+#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
+#define FLEXIO_SHIFTCTL_PINSEL_MASK (0xF00U)
+#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
+/*! PINSEL - Shifter Pin Select
+ */
+#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
+#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
+#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
+/*! PINCFG - Shifter Pin Configuration
+ * 0b00..Shifter pin output disabled
+ * 0b01..Shifter pin open drain or bidirectional output enable
+ * 0b10..Shifter pin bidirectional output data
+ * 0b11..Shifter pin output
+ */
+#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
+#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
+#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
+/*! TIMPOL - Timer Polarity
+ * 0b0..Shift on posedge of Shift clock
+ * 0b1..Shift on negedge of Shift clock
+ */
+#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
+#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U)
+#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
+/*! TIMSEL - Timer Select
+ */
+#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTCTL */
+#define FLEXIO_SHIFTCTL_COUNT (8U)
+
+/*! @name SHIFTCFG - Shifter Configuration N Register */
+/*! @{ */
+#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
+#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
+/*! SSTART - Shifter Start bit
+ * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
+ * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
+ * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
+ * 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
+ */
+#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
+#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
+#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
+/*! SSTOP - Shifter Stop bit
+ * 0b00..Stop bit disabled for transmitter/receiver/match store
+ * 0b01..Reserved for transmitter/receiver/match store
+ * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
+ * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
+ */
+#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
+#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
+#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
+/*! INSRC - Input Source
+ * 0b0..Pin
+ * 0b1..Shifter N+1 Output
+ */
+#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
+#define FLEXIO_SHIFTCFG_LATST_MASK (0x200U)
+#define FLEXIO_SHIFTCFG_LATST_SHIFT (9U)
+/*! LATST - Late Store
+ * 0b0..Shift register stores the pre-shift register state.
+ * 0b1..Shift register stores the post-shift register state.
+ */
+#define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)
+#define FLEXIO_SHIFTCFG_SSIZE_MASK (0x1000U)
+#define FLEXIO_SHIFTCFG_SSIZE_SHIFT (12U)
+/*! SSIZE - Shifter Size
+ * 0b0..Shift register is 32-bit.
+ * 0b1..Shift register is 24-bit.
+ */
+#define FLEXIO_SHIFTCFG_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK)
+#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0xF0000U)
+#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
+/*! PWIDTH - Parallel Width
+ */
+#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTCFG */
+#define FLEXIO_SHIFTCFG_COUNT (8U)
+
+/*! @name SHIFTBUF - Shifter Buffer N Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
+/*! SHIFTBUF - Shift Buffer
+ */
+#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUF */
+#define FLEXIO_SHIFTBUF_COUNT (8U)
+
+/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
+/*! SHIFTBUFBIS - Shift Buffer
+ */
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFBIS */
+#define FLEXIO_SHIFTBUFBIS_COUNT (8U)
+
+/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
+/*! SHIFTBUFBYS - Shift Buffer
+ */
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFBYS */
+#define FLEXIO_SHIFTBUFBYS_COUNT (8U)
+
+/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
+/*! SHIFTBUFBBS - Shift Buffer
+ */
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFBBS */
+#define FLEXIO_SHIFTBUFBBS_COUNT (8U)
+
+/*! @name TIMCTL - Timer Control N Register */
+/*! @{ */
+#define FLEXIO_TIMCTL_TIMOD_MASK (0x7U)
+#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
+/*! TIMOD - Timer Mode
+ * 0b000..Timer Disabled.
+ * 0b001..Dual 8-bit counters baud mode.
+ * 0b010..Dual 8-bit counters PWM high mode.
+ * 0b011..Single 16-bit counter mode.
+ * 0b100..Single 16-bit counter disable mode.
+ * 0b101..Dual 8-bit counters word mode.
+ * 0b110..Dual 8-bit counters PWM low mode.
+ * 0b111..Single 16-bit input capture mode.
+ */
+#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
+#define FLEXIO_TIMCTL_ONETIM_MASK (0x20U)
+#define FLEXIO_TIMCTL_ONETIM_SHIFT (5U)
+/*! ONETIM - Timer One Time Operation
+ * 0b0..The timer enable event is generated as normal.
+ * 0b1..The timer enable event is blocked unless timer status flag is clear.
+ */
+#define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)
+#define FLEXIO_TIMCTL_PININS_MASK (0x40U)
+#define FLEXIO_TIMCTL_PININS_SHIFT (6U)
+/*! PININS - Timer Pin Input Select
+ * 0b0..Timer pin input and output are selected by PINSEL.
+ * 0b1..Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL.
+ */
+#define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)
+#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
+#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
+/*! PINPOL - Timer Pin Polarity
+ * 0b0..Pin is active high
+ * 0b1..Pin is active low
+ */
+#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
+#define FLEXIO_TIMCTL_PINSEL_MASK (0xF00U)
+#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
+/*! PINSEL - Timer Pin Select
+ */
+#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
+#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
+#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
+/*! PINCFG - Timer Pin Configuration
+ * 0b00..Timer pin output disabled
+ * 0b01..Timer pin open drain or bidirectional output enable
+ * 0b10..Timer pin bidirectional output data
+ * 0b11..Timer pin output
+ */
+#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
+#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
+#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
+/*! TRGSRC - Trigger Source
+ * 0b0..External trigger selected
+ * 0b1..Internal trigger selected
+ */
+#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
+#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
+#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
+/*! TRGPOL - Trigger Polarity
+ * 0b0..Trigger active high
+ * 0b1..Trigger active low
+ */
+#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
+#define FLEXIO_TIMCTL_TRGSEL_MASK (0x1F000000U)
+#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
+/*! TRGSEL - Trigger Select
+ */
+#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
+/*! @} */
+
+/* The count of FLEXIO_TIMCTL */
+#define FLEXIO_TIMCTL_COUNT (8U)
+
+/*! @name TIMCFG - Timer Configuration N Register */
+/*! @{ */
+#define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
+#define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
+/*! TSTART - Timer Start Bit
+ * 0b0..Start bit disabled
+ * 0b1..Start bit enabled
+ */
+#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
+#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
+#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
+/*! TSTOP - Timer Stop Bit
+ * 0b00..Stop bit disabled
+ * 0b01..Stop bit is enabled on timer compare
+ * 0b10..Stop bit is enabled on timer disable
+ * 0b11..Stop bit is enabled on timer compare and timer disable
+ */
+#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
+#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
+#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
+/*! TIMENA - Timer Enable
+ * 0b000..Timer always enabled
+ * 0b001..Timer enabled on Timer N-1 enable
+ * 0b010..Timer enabled on Trigger high
+ * 0b011..Timer enabled on Trigger high and Pin high
+ * 0b100..Timer enabled on Pin rising edge
+ * 0b101..Timer enabled on Pin rising edge and Trigger high
+ * 0b110..Timer enabled on Trigger rising edge
+ * 0b111..Timer enabled on Trigger rising or falling edge
+ */
+#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
+#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
+#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
+/*! TIMDIS - Timer Disable
+ * 0b000..Timer never disabled
+ * 0b001..Timer disabled on Timer N-1 disable
+ * 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
+ * 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
+ * 0b100..Timer disabled on Pin rising or falling edge
+ * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
+ * 0b110..Timer disabled on Trigger falling edge
+ * 0b111..Reserved
+ */
+#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
+#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
+#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
+/*! TIMRST - Timer Reset
+ * 0b000..Timer never reset
+ * 0b001..Timer reset on Timer Output high.
+ * 0b010..Timer reset on Timer Pin equal to Timer Output
+ * 0b011..Timer reset on Timer Trigger equal to Timer Output
+ * 0b100..Timer reset on Timer Pin rising edge
+ * 0b101..Reserved
+ * 0b110..Timer reset on Trigger rising edge
+ * 0b111..Timer reset on Trigger rising or falling edge
+ */
+#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
+#define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U)
+#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
+/*! TIMDEC - Timer Decrement
+ * 0b000..Decrement counter on FlexIO clock, Shift clock equals Timer output.
+ * 0b001..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
+ * 0b010..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
+ * 0b011..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
+ * 0b100..Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output.
+ * 0b101..Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output.
+ * 0b110..Decrement counter on Pin input (rising edge), Shift clock equals Pin input.
+ * 0b111..Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input.
+ */
+#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
+#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
+#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
+/*! TIMOUT - Timer Output
+ * 0b00..Timer output is logic one when enabled and is not affected by timer reset
+ * 0b01..Timer output is logic zero when enabled and is not affected by timer reset
+ * 0b10..Timer output is logic one when enabled and on timer reset
+ * 0b11..Timer output is logic zero when enabled and on timer reset
+ */
+#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
+/*! @} */
+
+/* The count of FLEXIO_TIMCFG */
+#define FLEXIO_TIMCFG_COUNT (8U)
+
+/*! @name TIMCMP - Timer Compare N Register */
+/*! @{ */
+#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
+#define FLEXIO_TIMCMP_CMP_SHIFT (0U)
+/*! CMP - Timer Compare Value
+ */
+#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
+/*! @} */
+
+/* The count of FLEXIO_TIMCMP */
+#define FLEXIO_TIMCMP_COUNT (8U)
+
+/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
+/*! SHIFTBUFNBS - Shift Buffer
+ */
+#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFNBS */
+#define FLEXIO_SHIFTBUFNBS_COUNT (8U)
+
+/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
+/*! SHIFTBUFHWS - Shift Buffer
+ */
+#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFHWS */
+#define FLEXIO_SHIFTBUFHWS_COUNT (8U)
+
+/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
+/*! SHIFTBUFNIS - Shift Buffer
+ */
+#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFNIS */
+#define FLEXIO_SHIFTBUFNIS_COUNT (8U)
+
+/*! @name SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U)
+/*! SHIFTBUFOES - Shift Buffer
+ */
+#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFOES */
+#define FLEXIO_SHIFTBUFOES_COUNT (8U)
+
+/*! @name SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U)
+/*! SHIFTBUFEOS - Shift Buffer
+ */
+#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFEOS */
+#define FLEXIO_SHIFTBUFEOS_COUNT (8U)
+
+/*! @name SHIFTBUFHBS - Shifter Buffer N Halfword Byte Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT (0U)
+/*! SHIFTBUFHBS - Shift Buffer
+ */
+#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFHBS */
+#define FLEXIO_SHIFTBUFHBS_COUNT (8U)
+
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Register_Masks */
+
+
+/* FLEXIO - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral FLEXIO0 base address */
+ #define FLEXIO0_BASE (0x50032000u)
+ /** Peripheral FLEXIO0 base address */
+ #define FLEXIO0_BASE_NS (0x40032000u)
+ /** Peripheral FLEXIO0 base pointer */
+ #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE)
+ /** Peripheral FLEXIO0 base pointer */
+ #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS)
+ /** Array initializer of FLEXIO peripheral base addresses */
+ #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE }
+ /** Array initializer of FLEXIO peripheral base pointers */
+ #define FLEXIO_BASE_PTRS { FLEXIO0 }
+ /** Array initializer of FLEXIO peripheral base addresses */
+ #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS }
+ /** Array initializer of FLEXIO peripheral base pointers */
+ #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS }
+#else
+ /** Peripheral FLEXIO0 base address */
+ #define FLEXIO0_BASE (0x40032000u)
+ /** Peripheral FLEXIO0 base pointer */
+ #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE)
+ /** Array initializer of FLEXIO peripheral base addresses */
+ #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE }
+ /** Array initializer of FLEXIO peripheral base pointers */
+ #define FLEXIO_BASE_PTRS { FLEXIO0 }
+#endif
+/** Interrupt vectors for the FLEXIO peripheral type */
+#define FLEXIO_IRQS { FLEXIO_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FLEXSPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXSPI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */
+ __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */
+ __IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */
+ __IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */
+ __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */
+ __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */
+ __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */
+ __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */
+ __IO uint32_t AHBRXBUFCR0[8]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_0[32];
+ __IO uint32_t FLSHCR0[4]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */
+ __IO uint32_t FLSHCR1[4]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */
+ __IO uint32_t FLSHCR2[4]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */
+ uint8_t RESERVED_2[8];
+ __IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */
+ __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */
+ uint8_t RESERVED_3[8];
+ __IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */
+ __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0xB4 */
+ __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */
+ __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */
+ __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_4[24];
+ __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */
+ __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */
+ __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */
+ __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */
+ __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */
+ __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */
+ uint8_t RESERVED_5[8];
+ __I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
+ __O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
+ __IO uint32_t LUT[64]; /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */
+} FLEXSPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FLEXSPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
+ * @{
+ */
+
+/*! @name MCR0 - Module Control Register 0 */
+/*! @{ */
+#define FLEXSPI_MCR0_SWRESET_MASK (0x1U)
+#define FLEXSPI_MCR0_SWRESET_SHIFT (0U)
+/*! SWRESET - Software Reset
+ */
+#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
+#define FLEXSPI_MCR0_MDIS_MASK (0x2U)
+#define FLEXSPI_MCR0_MDIS_SHIFT (1U)
+/*! MDIS - Module Disable
+ */
+#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
+#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)
+#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)
+/*! RXCLKSRC - Sample Clock source selection for Flash Reading
+ * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
+ * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
+ * 0b10..Reserved
+ * 0b11..Flash provided Read strobe and input from DQS pad
+ */
+#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
+#define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U)
+#define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U)
+/*! SERCLKDIV - The serial root clock could be divided inside FlexSPI wrapper. Refer Clocks chapter for more details on clocking.
+ * 0b000..Divided by 1
+ * 0b001..Divided by 2
+ * 0b010..Divided by 3
+ * 0b011..Divided by 4
+ * 0b100..Divided by 5
+ * 0b101..Divided by 6
+ * 0b110..Divided by 7
+ * 0b111..Divided by 8
+ */
+#define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
+#define FLEXSPI_MCR0_HSEN_MASK (0x800U)
+#define FLEXSPI_MCR0_HSEN_SHIFT (11U)
+/*! HSEN - Half Speed Serial Flash access Enable.
+ * 0b0..Disable divide by 2 of serial flash clock for half speed commands.
+ * 0b1..Enable divide by 2 of serial flash clock for half speed commands.
+ */
+#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
+#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U)
+#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U)
+/*! DOZEEN - Doze mode enable bit
+ * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
+ * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
+ */
+#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
+#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)
+#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)
+/*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications,
+ * external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is
+ * enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).
+ * 0b0..Disable.
+ * 0b1..Enable.
+ */
+#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
+#define FLEXSPI_MCR0_LEARNEN_MASK (0x8000U)
+#define FLEXSPI_MCR0_LEARNEN_SHIFT (15U)
+/*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is
+ * disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction
+ * is correctly executed.
+ * 0b0..Disable.
+ * 0b1..Enable.
+ */
+#define FLEXSPI_MCR0_LEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK)
+#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)
+#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)
+/*! IPGRANTWAIT - Time out wait cycle for IP command grant.
+ */
+#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
+#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)
+#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)
+/*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant.
+ */
+#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
+/*! @} */
+
+/*! @name MCR1 - Module Control Register 1 */
+/*! @{ */
+#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)
+#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)
+#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
+#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)
+#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U)
+#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
+/*! @} */
+
+/*! @name MCR2 - Module Control Register 2 */
+/*! @{ */
+#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)
+#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)
+/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned
+ * automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or
+ * AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP
+ * mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
+ * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
+ * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
+ */
+#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
+#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)
+#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)
+/*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is
+ * written with 0x1. This bit will be auto-cleared immediately.
+ */
+#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
+#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)
+#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)
+/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
+ * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash
+ * A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1,
+ * FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be
+ * ignored.
+ * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
+ */
+#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
+#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)
+#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)
+/*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to
+ * A_SCLK). In this case, port B flash access is not available. After changing the value of this
+ * field, MCR0[SWRESET] should be set.
+ * 0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available.
+ * 0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
+ */
+#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
+#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)
+#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)
+/*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.
+ */
+#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
+/*! @} */
+
+/*! @name AHBCR - AHB Bus Control Register */
+/*! @{ */
+#define FLEXSPI_AHBCR_APAREN_MASK (0x1U)
+#define FLEXSPI_AHBCR_APAREN_SHIFT (0U)
+/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) .
+ * 0b0..Flash will be accessed in Individual mode.
+ * 0b1..Flash will be accessed in Parallel mode.
+ */
+#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
+#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)
+#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)
+/*! CACHABLEEN - Enable AHB bus cachable read access support.
+ * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
+ * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
+ */
+#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
+#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)
+#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)
+/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat
+ * of AHB write access, refer for more details about AHB bufferable write.
+ * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus
+ * ready after all data is transmitted to External device and AHB command finished.
+ * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
+ * granted by arbitrator and will not wait for AHB command finished.
+ */
+#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
+#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)
+#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)
+/*! PREFETCHEN - AHB Read Prefetch Enable.
+ */
+#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
+#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U)
+#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U)
+/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
+ * 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is word-addressable.
+ * 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB
+ * burst required to meet the alignment requirement.
+ */
+#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
+#define FLEXSPI_AHBCR_READSZALIGN_MASK (0x400U)
+#define FLEXSPI_AHBCR_READSZALIGN_SHIFT (10U)
+/*! READSZALIGN - AHB Read Size Alignment
+ * 0b0..AHB read size will be decided by other register setting like PREFETCH_EN,OTFAD_EN...
+ * 0b1..AHB read size to up size to 8 bytes aligned, no prefetching
+ */
+#define FLEXSPI_AHBCR_READSZALIGN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK)
+/*! @} */
+
+/*! @name INTEN - Interrupt Enable Register */
+/*! @{ */
+#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)
+#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)
+/*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable.
+ */
+#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
+#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)
+#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)
+/*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable.
+ */
+#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
+#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)
+#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)
+/*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable.
+ */
+#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
+#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)
+#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)
+/*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable.
+ */
+#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
+#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)
+#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)
+/*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable.
+ */
+#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
+#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)
+#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)
+/*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable.
+ */
+#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
+#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)
+#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)
+/*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable.
+ */
+#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
+#define FLEXSPI_INTEN_DATALEARNFAILEN_MASK (0x80U)
+#define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT (7U)
+/*! DATALEARNFAILEN - Data Learning failed interrupt enable.
+ */
+#define FLEXSPI_INTEN_DATALEARNFAILEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK)
+#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)
+#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)
+/*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable.
+ */
+#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
+#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)
+#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)
+/*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable.
+ */
+#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
+#define FLEXSPI_INTEN_AHBBUSERROREN_MASK (0x400U)
+#define FLEXSPI_INTEN_AHBBUSERROREN_SHIFT (10U)
+/*! AHBBUSERROREN - AHB Bus error interrupt enable.Refer Interrupts chapter for more details.
+ */
+#define FLEXSPI_INTEN_AHBBUSERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK)
+#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)
+#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)
+/*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
+ */
+#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
+#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)
+#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)
+/*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.
+ */
+#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
+#define FLEXSPI_INTEN_KEYDONEEN_MASK (0x1000U)
+#define FLEXSPI_INTEN_KEYDONEEN_SHIFT (12U)
+/*! KEYDONEEN - OTFAD key blob processing done interrupt enable.Refer Interrupts chapter for more details.
+ */
+#define FLEXSPI_INTEN_KEYDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK)
+#define FLEXSPI_INTEN_KEYERROREN_MASK (0x2000U)
+#define FLEXSPI_INTEN_KEYERROREN_SHIFT (13U)
+/*! KEYERROREN - OTFAD key blob processing error interrupt enable.Refer Interrupts chapter for more details.
+ */
+#define FLEXSPI_INTEN_KEYERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK)
+/*! @} */
+
+/*! @name INTR - Interrupt Register */
+/*! @{ */
+#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U)
+#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U)
+/*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also
+ * generated when there is IPCMDGE or IPCMDERR interrupt generated.
+ */
+#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
+#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U)
+#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U)
+/*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt.
+ */
+#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
+#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U)
+#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U)
+/*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt.
+ */
+#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
+#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U)
+#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U)
+/*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for
+ * IP command, this command will be ignored and not executed at all.
+ */
+#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
+#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U)
+#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U)
+/*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for
+ * AHB command, this command will be ignored and not executed at all.
+ */
+#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
+#define FLEXSPI_INTR_IPRXWA_MASK (0x20U)
+#define FLEXSPI_INTR_IPRXWA_SHIFT (5U)
+/*! IPRXWA - IP RX FIFO watermark available interrupt.
+ */
+#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
+#define FLEXSPI_INTR_IPTXWE_MASK (0x40U)
+#define FLEXSPI_INTR_IPTXWE_SHIFT (6U)
+/*! IPTXWE - IP TX FIFO watermark empty interrupt.
+ */
+#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
+#define FLEXSPI_INTR_DATALEARNFAIL_MASK (0x80U)
+#define FLEXSPI_INTR_DATALEARNFAIL_SHIFT (7U)
+/*! DATALEARNFAIL - Data Learning failed interrupt.
+ */
+#define FLEXSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK)
+#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)
+#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)
+/*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt.
+ */
+#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
+#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)
+#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)
+/*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt.
+ */
+#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
+#define FLEXSPI_INTR_AHBBUSERROR_MASK (0x400U)
+#define FLEXSPI_INTR_AHBBUSERROR_SHIFT (10U)
+/*! AHBBUSERROR - AHB Bus timeout or AHB bus illegal access Flash during OTFAD key blob processing interrupt.
+ */
+#define FLEXSPI_INTR_AHBBUSERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK)
+#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)
+#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)
+/*! AHBBUSTIMEOUT - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
+ */
+#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
+#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)
+#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)
+/*! SEQTIMEOUT - Sequence execution timeout interrupt.
+ */
+#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
+#define FLEXSPI_INTR_KEYDONE_MASK (0x1000U)
+#define FLEXSPI_INTR_KEYDONE_SHIFT (12U)
+/*! KEYDONE - OTFAD key blob processing done interrupt.
+ */
+#define FLEXSPI_INTR_KEYDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK)
+#define FLEXSPI_INTR_KEYERROR_MASK (0x2000U)
+#define FLEXSPI_INTR_KEYERROR_SHIFT (13U)
+/*! KEYERROR - OTFAD key blob processing error interrupt.
+ */
+#define FLEXSPI_INTR_KEYERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK)
+/*! @} */
+
+/*! @name LUTKEY - LUT Key Register */
+/*! @{ */
+#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
+#define FLEXSPI_LUTKEY_KEY_SHIFT (0U)
+/*! KEY - The Key to lock or unlock LUT.
+ */
+#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
+/*! @} */
+
+/*! @name LUTCR - LUT Control Register */
+/*! @{ */
+#define FLEXSPI_LUTCR_LOCK_MASK (0x1U)
+#define FLEXSPI_LUTCR_LOCK_SHIFT (0U)
+/*! LOCK - Lock LUT
+ */
+#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
+#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U)
+#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U)
+/*! UNLOCK - Unlock LUT
+ */
+#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
+/*! @} */
+
+/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */
+/*! @{ */
+#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x1FFU) /* Merged from fields with different position or width, of widths (8, 9), largest definition used */
+#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)
+/*! BUFSZ - AHB RX Buffer Size in 64 bits.
+ */
+#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) /* Merged from fields with different position or width, of widths (8, 9), largest definition used */
+#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)
+#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)
+/*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).
+ */
+#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
+#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U)
+#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)
+/*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest.
+ */
+#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
+#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)
+#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)
+/*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
+ */
+#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_AHBRXBUFCR0 */
+#define FLEXSPI_AHBRXBUFCR0_COUNT (8U)
+
+/*! @name FLSHCR0 - Flash Control Register 0 */
+/*! @{ */
+#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)
+#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)
+/*! FLSHSZ - Flash Size in KByte.
+ */
+#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_FLSHCR0 */
+#define FLEXSPI_FLSHCR0_COUNT (4U)
+
+/*! @name FLSHCR1 - Flash Control Register 1 */
+/*! @{ */
+#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)
+#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U)
+/*! TCSS - Serial Flash CS setup time.
+ */
+#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
+#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)
+#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U)
+/*! TCSH - Serial Flash CS Hold time.
+ */
+#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
+#define FLEXSPI_FLSHCR1_WA_MASK (0x400U)
+#define FLEXSPI_FLSHCR1_WA_SHIFT (10U)
+/*! WA - Word Addressable.
+ */
+#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
+#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U)
+#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U)
+/*! CAS - Column Address Size.
+ */
+#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
+#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)
+#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)
+/*! CSINTERVALUNIT - CS interval unit
+ * 0b0..The CS interval unit is 1 serial clock cycle
+ * 0b1..The CS interval unit is 256 serial clock cycle
+ */
+#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
+#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)
+#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)
+/*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection
+ * deassertion and flash device Chip selection assertion. If external flash has a limitation on
+ * the interval between command sequences, this field should be set accordingly. If there is no
+ * limitation, set this field with value 0x0.
+ */
+#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_FLSHCR1 */
+#define FLEXSPI_FLSHCR1_COUNT (4U)
+
+/*! @name FLSHCR2 - Flash Control Register 2 */
+/*! @{ */
+#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)
+#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)
+/*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT.
+ */
+#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
+#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)
+#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)
+/*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT.
+ */
+#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
+#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)
+#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)
+/*! AWRSEQID - Sequence Index for AHB Write triggered Command.
+ */
+#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
+#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)
+#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)
+/*! AWRSEQNUM - Sequence Number for AHB Write triggered Command.
+ */
+#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
+#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)
+#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)
+#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
+#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)
+#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)
+/*! AWRWAITUNIT - AWRWAIT unit
+ * 0b000..The AWRWAIT unit is 2 ahb clock cycle
+ * 0b001..The AWRWAIT unit is 8 ahb clock cycle
+ * 0b010..The AWRWAIT unit is 32 ahb clock cycle
+ * 0b011..The AWRWAIT unit is 128 ahb clock cycle
+ * 0b100..The AWRWAIT unit is 512 ahb clock cycle
+ * 0b101..The AWRWAIT unit is 2048 ahb clock cycle
+ * 0b110..The AWRWAIT unit is 8192 ahb clock cycle
+ * 0b111..The AWRWAIT unit is 32768 ahb clock cycle
+ */
+#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
+#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)
+#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)
+/*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS.
+ * Refer Programmable Sequence Engine for details.
+ */
+#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_FLSHCR2 */
+#define FLEXSPI_FLSHCR2_COUNT (4U)
+
+/*! @name FLSHCR4 - Flash Control Register 4 */
+/*! @{ */
+#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)
+#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)
+/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
+ * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
+ * burst start address alignment when flash is accessed in individual mode.
+ * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
+ * burst start address alignment when flash is accessed in individual mode.
+ */
+#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
+#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U)
+#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U)
+/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
+ * memory device on port A, this bit must be set.
+ * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
+ * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
+ */
+#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
+#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U)
+#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U)
+/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for
+ * memory device on port B, this bit must be set.
+ * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
+ * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
+ */
+#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
+/*! @} */
+
+/*! @name IPCR0 - IP Control Register 0 */
+/*! @{ */
+#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)
+#define FLEXSPI_IPCR0_SFAR_SHIFT (0U)
+/*! SFAR - Serial Flash Address for IP command.
+ */
+#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
+/*! @} */
+
+/*! @name IPCR1 - IP Control Register 1 */
+/*! @{ */
+#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)
+#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U)
+/*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command.
+ */
+#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
+#define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)
+#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U)
+/*! ISEQID - Sequence Index in LUT for IP command.
+ */
+#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
+#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)
+#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)
+/*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1.
+ */
+#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
+#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)
+#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U)
+/*! IPAREN - Parallel mode Enabled for IP command.
+ * 0b0..Flash will be accessed in Individual mode.
+ * 0b1..Flash will be accessed in Parallel mode.
+ */
+#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
+/*! @} */
+
+/*! @name IPCMD - IP Command Register */
+/*! @{ */
+#define FLEXSPI_IPCMD_TRG_MASK (0x1U)
+#define FLEXSPI_IPCMD_TRG_SHIFT (0U)
+/*! TRG - Setting this bit will trigger an IP Command.
+ */
+#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
+/*! @} */
+
+/*! @name DLPR - Data Learn Pattern Register */
+/*! @{ */
+#define FLEXSPI_DLPR_DLP_MASK (0xFFFFFFFFU)
+#define FLEXSPI_DLPR_DLP_SHIFT (0U)
+/*! DLP - Data Learning Pattern.
+ */
+#define FLEXSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK)
+/*! @} */
+
+/*! @name IPRXFCR - IP RX FIFO Control Register */
+/*! @{ */
+#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)
+#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)
+/*! CLRIPRXF - Clear all valid data entries in IP RX FIFO.
+ */
+#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
+#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)
+#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)
+/*! RXDMAEN - IP RX FIFO reading by DMA enabled.
+ * 0b0..IP RX FIFO would be read by processor.
+ * 0b1..IP RX FIFO would be read by DMA.
+ */
+#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
+#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x1FCU)
+#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)
+/*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits.
+ */
+#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
+/*! @} */
+
+/*! @name IPTXFCR - IP TX FIFO Control Register */
+/*! @{ */
+#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)
+#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)
+/*! CLRIPTXF - Clear all valid data entries in IP TX FIFO.
+ */
+#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
+#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)
+#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)
+/*! TXDMAEN - IP TX FIFO filling by DMA enabled.
+ * 0b0..IP TX FIFO would be filled by processor.
+ * 0b1..IP TX FIFO would be filled by DMA.
+ */
+#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
+#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x1FCU)
+#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)
+/*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits.
+ */
+#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
+/*! @} */
+
+/*! @name DLLCR - DLL Control Register 0 */
+/*! @{ */
+#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U)
+#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U)
+/*! DLLEN - DLL calibration enable.
+ */
+#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
+#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U)
+#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U)
+/*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the
+ * DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset
+ * action is edge triggered, so software need to clear this bit after set this bit (no delay
+ * limitation).
+ */
+#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
+#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)
+#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)
+/*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle
+ * of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1,
+ * OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended.
+ */
+#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
+#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U)
+#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U)
+/*! OVRDEN - Slave clock delay line delay cell number selection override enable.
+ */
+#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
+#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)
+#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)
+/*! OVRDVAL - Slave clock delay line delay cell number selection override value.
+ */
+#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_DLLCR */
+#define FLEXSPI_DLLCR_COUNT (2U)
+
+/*! @name STS0 - Status Register 0 */
+/*! @{ */
+#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U)
+#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U)
+/*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command
+ * sequence executing on FlexSPI interface.
+ */
+#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
+#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U)
+#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U)
+/*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command
+ * sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state
+ * (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So
+ * this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
+ */
+#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
+#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)
+#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)
+/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
+ * by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
+ * 0b00..Triggered by AHB read command (triggered by AHB read).
+ * 0b01..Triggered by AHB write command (triggered by AHB Write).
+ * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
+ * 0b11..Triggered by suspended command (resumed).
+ */
+#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
+#define FLEXSPI_STS0_DATALEARNPHASEA_MASK (0xF0U)
+#define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT (4U)
+/*! DATALEARNPHASEA - Indicate the sampling clock phase selection on Port A after Data Learning.
+ */
+#define FLEXSPI_STS0_DATALEARNPHASEA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK)
+#define FLEXSPI_STS0_DATALEARNPHASEB_MASK (0xF00U)
+#define FLEXSPI_STS0_DATALEARNPHASEB_SHIFT (8U)
+/*! DATALEARNPHASEB - Indicate the sampling clock phase selection on Port B after Data Learning.
+ */
+#define FLEXSPI_STS0_DATALEARNPHASEB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEB_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEB_MASK)
+/*! @} */
+
+/*! @name STS1 - Status Register 1 */
+/*! @{ */
+#define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)
+#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)
+/*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field
+ * will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
+ */
+#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
+#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)
+#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)
+/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
+ * cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
+ * 0b0000..No error.
+ * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
+ * 0b0011..There is unknown instruction opcode in the sequence.
+ * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
+ * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
+ * 0b1110..Sequence execution timeout.
+ */
+#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
+#define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)
+#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U)
+/*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be
+ * cleared when INTR[IPCMDERR] is write-1-clear(w1c).
+ */
+#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
+#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)
+#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)
+/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
+ * cleared when INTR[IPCMDERR] is write-1-clear(w1c).
+ * 0b0000..No error.
+ * 0b0010..IP command with JMP_ON_CS instruction used in the sequence.
+ * 0b0011..There is unknown instruction opcode in the sequence.
+ * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
+ * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
+ * 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
+ * 0b1110..Sequence execution timeout.
+ * 0b1111..Flash boundary crossed.
+ */
+#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
+/*! @} */
+
+/*! @name STS2 - Status Register 2 */
+/*! @{ */
+#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U)
+#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U)
+/*! ASLVLOCK - Flash A sample clock slave delay line locked.
+ */
+#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
+#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U)
+#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U)
+/*! AREFLOCK - Flash A sample clock reference delay line locked.
+ */
+#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
+#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU)
+#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U)
+/*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection .
+ */
+#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
+#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U)
+#define FLEXSPI_STS2_AREFSEL_SHIFT (8U)
+/*! AREFSEL - Flash A sample clock reference delay line delay cell number selection.
+ */
+#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
+#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)
+#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U)
+/*! BSLVLOCK - Flash B sample clock slave delay line locked.
+ */
+#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
+#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U)
+#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U)
+/*! BREFLOCK - Flash B sample clock reference delay line locked.
+ */
+#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
+#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)
+#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U)
+/*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection.
+ */
+#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
+#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)
+#define FLEXSPI_STS2_BREFSEL_SHIFT (24U)
+/*! BREFSEL - Flash B sample clock reference delay line delay cell number selection.
+ */
+#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
+/*! @} */
+
+/*! @name AHBSPNDSTS - AHB Suspend Status Register */
+/*! @{ */
+#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)
+#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)
+/*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended.
+ */
+#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
+#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)
+#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)
+/*! BUFID - AHB RX BUF ID for suspended command sequence.
+ */
+#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
+#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)
+#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)
+/*! DATLFT - Left Data size for suspended command sequence (in byte).
+ */
+#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
+/*! @} */
+
+/*! @name IPRXFSTS - IP RX FIFO Status Register */
+/*! @{ */
+#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)
+#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U)
+/*! FILL - Fill level of IP RX FIFO.
+ */
+#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
+#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)
+#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)
+/*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits.
+ */
+#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
+/*! @} */
+
+/*! @name IPTXFSTS - IP TX FIFO Status Register */
+/*! @{ */
+#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)
+#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U)
+/*! FILL - Fill level of IP TX FIFO.
+ */
+#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
+#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)
+#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)
+/*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits.
+ */
+#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
+/*! @} */
+
+/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
+/*! @{ */
+#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)
+#define FLEXSPI_RFDR_RXDATA_SHIFT (0U)
+/*! RXDATA - RX Data
+ */
+#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_RFDR */
+#define FLEXSPI_RFDR_COUNT (32U)
+
+/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
+/*! @{ */
+#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)
+#define FLEXSPI_TFDR_TXDATA_SHIFT (0U)
+/*! TXDATA - TX Data
+ */
+#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_TFDR */
+#define FLEXSPI_TFDR_COUNT (32U)
+
+/*! @name LUT - LUT 0..LUT 63 */
+/*! @{ */
+#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
+#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
+/*! OPERAND0 - OPERAND0
+ */
+#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
+#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
+#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
+/*! NUM_PADS0 - NUM_PADS0
+ */
+#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
+#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
+#define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
+/*! OPCODE0 - OPCODE
+ */
+#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
+#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
+#define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
+/*! OPERAND1 - OPERAND1
+ */
+#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
+#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
+#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
+/*! NUM_PADS1 - NUM_PADS1
+ */
+#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
+#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
+#define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
+/*! OPCODE1 - OPCODE1
+ */
+#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
+/*! @} */
+
+/* The count of FLEXSPI_LUT */
+#define FLEXSPI_LUT_COUNT (64U)
+
+
+/*!
+ * @}
+ */ /* end of group FLEXSPI_Register_Masks */
+
+
+/* FLEXSPI - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral FLEXSPI0 base address */
+ #define FLEXSPI0_BASE (0x50134000u)
+ /** Peripheral FLEXSPI0 base address */
+ #define FLEXSPI0_BASE_NS (0x40134000u)
+ /** Peripheral FLEXSPI0 base pointer */
+ #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE)
+ /** Peripheral FLEXSPI0 base pointer */
+ #define FLEXSPI0_NS ((FLEXSPI_Type *)FLEXSPI0_BASE_NS)
+ /** Peripheral FLEXSPI1 base address */
+ #define FLEXSPI1_BASE (0x5013C000u)
+ /** Peripheral FLEXSPI1 base address */
+ #define FLEXSPI1_BASE_NS (0x4013C000u)
+ /** Peripheral FLEXSPI1 base pointer */
+ #define FLEXSPI1 ((FLEXSPI_Type *)FLEXSPI1_BASE)
+ /** Peripheral FLEXSPI1 base pointer */
+ #define FLEXSPI1_NS ((FLEXSPI_Type *)FLEXSPI1_BASE_NS)
+ /** Array initializer of FLEXSPI peripheral base addresses */
+ #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE, FLEXSPI1_BASE }
+ /** Array initializer of FLEXSPI peripheral base pointers */
+ #define FLEXSPI_BASE_PTRS { FLEXSPI0, FLEXSPI1 }
+ /** Array initializer of FLEXSPI peripheral base addresses */
+ #define FLEXSPI_BASE_ADDRS_NS { FLEXSPI0_BASE_NS, FLEXSPI1_BASE_NS }
+ /** Array initializer of FLEXSPI peripheral base pointers */
+ #define FLEXSPI_BASE_PTRS_NS { FLEXSPI0_NS, FLEXSPI1_NS }
+#else
+ /** Peripheral FLEXSPI0 base address */
+ #define FLEXSPI0_BASE (0x40134000u)
+ /** Peripheral FLEXSPI0 base pointer */
+ #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE)
+ /** Peripheral FLEXSPI1 base address */
+ #define FLEXSPI1_BASE (0x4013C000u)
+ /** Peripheral FLEXSPI1 base pointer */
+ #define FLEXSPI1 ((FLEXSPI_Type *)FLEXSPI1_BASE)
+ /** Array initializer of FLEXSPI peripheral base addresses */
+ #define FLEXSPI_BASE_ADDRS { FLEXSPI0_BASE, FLEXSPI1_BASE }
+ /** Array initializer of FLEXSPI peripheral base pointers */
+ #define FLEXSPI_BASE_PTRS { FLEXSPI0, FLEXSPI1 }
+#endif
+/** Interrupt vectors for the FLEXSPI peripheral type */
+#define FLEXSPI_IRQS { FLEXSPI0_FLEXSPI1_IRQn, FLEXSPI0_FLEXSPI1_IRQn }
+#if (__ARM_FEATURE_CMSE & 0x2)
+/** FlexSPI0 AMBA address */
+#define FlexSPI0_AMBA_BASE (0x18000000u)
+/** FlexSPI1 AMBA address */
+#define FlexSPI1_AMBA_BASE (0x38000000u)
+/** FlexSPI0 AMBA address */
+#define FlexSPI0_AMBA_BASE_NS (0x08000000U)
+/** FlexSPI1 AMBA address */
+#define FlexSPI1_AMBA_BASE_NS (0x28000000U)
+#else
+/** FlexSPI0 AMBA address */
+#define FlexSPI0_AMBA_BASE (0x08000000U)
+/** FlexSPI1 AMBA address */
+#define FlexSPI1_AMBA_BASE (0x28000000U)
+#endif
+
+
+/*!
+ * @}
+ */ /* end of group FLEXSPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FREQME Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer
+ * @{
+ */
+
+/** FREQME - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ __I uint32_t FREQMECTRL_R; /**< Frequency Measurement (in Read mode), offset: 0x0 */
+ __O uint32_t FREQMECTRL_W; /**< Frequency Measurement (in Write mode), offset: 0x0 */
+ };
+} FREQME_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FREQME Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FREQME_Register_Masks FREQME Register Masks
+ * @{
+ */
+
+/*! @name FREQMECTRL_R - Frequency Measurement (in Read mode) */
+/*! @{ */
+#define FREQME_FREQMECTRL_R_RESULT_MASK (0x7FFFFFFFU)
+#define FREQME_FREQMECTRL_R_RESULT_SHIFT (0U)
+/*! RESULT - Result
+ */
+#define FREQME_FREQMECTRL_R_RESULT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_R_RESULT_SHIFT)) & FREQME_FREQMECTRL_R_RESULT_MASK)
+#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_MASK (0x80000000U)
+#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_SHIFT (31U)
+/*! MEASURE_IN_PROGRESS - Measure in Progress
+ * 0b0..Process complete. Measurement cycle is complete. The results are ready in the RESULT field.
+ * 0b1..In Progress. Measurement cycle is in progress.
+ */
+#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_MASK)
+/*! @} */
+
+/*! @name FREQMECTRL_W - Frequency Measurement (in Write mode) */
+/*! @{ */
+#define FREQME_FREQMECTRL_W_REF_SCALE_MASK (0x1FU)
+#define FREQME_FREQMECTRL_W_REF_SCALE_SHIFT (0U)
+/*! REF_SCALE - Reference Clock Scaling Factor
+ * 0b00000..Count cycle = 2 ^ 0 = 1
+ * 0b00001..Count cycle = 2 ^ 1 = 2
+ * 0b00010..Count cycle = 2 ^ 2 = 4
+ * 0b11111..Count cycle = 2 ^ 31 = 2,147,483,648
+ */
+#define FREQME_FREQMECTRL_W_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_REF_SCALE_SHIFT)) & FREQME_FREQMECTRL_W_REF_SCALE_MASK)
+#define FREQME_FREQMECTRL_W_PULSE_MODE_MASK (0x100U)
+#define FREQME_FREQMECTRL_W_PULSE_MODE_SHIFT (8U)
+/*! PULSE_MODE - Pulse Width Measurement mode select
+ * 0b0..Frequency Measurement Mode. FREQMECTRL works in a Frequency Measurement mode. Once the measurement starts
+ * (real count start is aligned at rising edge arrival on reference clock), the target counter increments by
+ * the target clock until the reference counter running by the reference clock reaches the count end point
+ * selected by REF_SCALE.
+ * 0b1..Pulse Width Measurement mode. FREQMECTRL works in a Pulse Width Measurement mode, measuring the high or
+ * low period of reference clock input selected by PULSE_POL. The target counter starts incrementing by the
+ * target clock once a corresponding trigger edge (rising edge for high period measurement and falling edge for
+ * low period) occurs.
+ */
+#define FREQME_FREQMECTRL_W_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_PULSE_MODE_SHIFT)) & FREQME_FREQMECTRL_W_PULSE_MODE_MASK)
+#define FREQME_FREQMECTRL_W_PULSE_POL_MASK (0x200U)
+#define FREQME_FREQMECTRL_W_PULSE_POL_SHIFT (9U)
+/*! PULSE_POL - Pulse Polarity
+ * 0b0..High Period. High period of reference clock is measured in Pulse Width Measurement mode triggered by the
+ * rising edge on the reference clock input.
+ * 0b1..Low Period. Low period of reference clock is measured in Pulse Width Measurement mode triggered by the
+ * falling edge on the reference clock input.
+ */
+#define FREQME_FREQMECTRL_W_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_PULSE_POL_SHIFT)) & FREQME_FREQMECTRL_W_PULSE_POL_MASK)
+#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK (0x80000000U)
+#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_SHIFT (31U)
+/*! MEASURE_IN_PROGRESS - Measure in Progress
+ * 0b0..Force Terminate
+ * 0b1..Initiates Measurement Cycle
+ */
+#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FREQME_Register_Masks */
+
+
+/* FREQME - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral FREQME base address */
+ #define FREQME_BASE (0x5002F000u)
+ /** Peripheral FREQME base address */
+ #define FREQME_BASE_NS (0x4002F000u)
+ /** Peripheral FREQME base pointer */
+ #define FREQME ((FREQME_Type *)FREQME_BASE)
+ /** Peripheral FREQME base pointer */
+ #define FREQME_NS ((FREQME_Type *)FREQME_BASE_NS)
+ /** Array initializer of FREQME peripheral base addresses */
+ #define FREQME_BASE_ADDRS { FREQME_BASE }
+ /** Array initializer of FREQME peripheral base pointers */
+ #define FREQME_BASE_PTRS { FREQME }
+ /** Array initializer of FREQME peripheral base addresses */
+ #define FREQME_BASE_ADDRS_NS { FREQME_BASE_NS }
+ /** Array initializer of FREQME peripheral base pointers */
+ #define FREQME_BASE_PTRS_NS { FREQME_NS }
+#else
+ /** Peripheral FREQME base address */
+ #define FREQME_BASE (0x4002F000u)
+ /** Peripheral FREQME base pointer */
+ #define FREQME ((FREQME_Type *)FREQME_BASE)
+ /** Array initializer of FREQME peripheral base addresses */
+ #define FREQME_BASE_ADDRS { FREQME_BASE }
+ /** Array initializer of FREQME peripheral base pointers */
+ #define FREQME_BASE_PTRS { FREQME }
+#endif
+
+/*!
+ * @}
+ */ /* end of group FREQME_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t B[7][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
+ uint8_t RESERVED_0[3872];
+ __IO uint32_t W[7][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
+ uint8_t RESERVED_1[3200];
+ __O uint32_t DIR[8]; /**< Port direction, array offset: 0x2000, array step: 0x4 */
+ uint8_t RESERVED_2[96];
+ __IO uint32_t MASK[8]; /**< Port mask, array offset: 0x2080, array step: 0x4 */
+ uint8_t RESERVED_3[96];
+ __IO uint32_t PIN[8]; /**< Port pin, array offset: 0x2100, array step: 0x4 */
+ uint8_t RESERVED_4[96];
+ __IO uint32_t MPIN[8]; /**< Masked Port Pin, array offset: 0x2180, array step: 0x4 */
+ uint8_t RESERVED_5[96];
+ __IO uint32_t SET[8]; /**< Port set, array offset: 0x2200, array step: 0x4 */
+ uint8_t RESERVED_6[96];
+ __IO uint32_t CLR[8]; /**< Port clear, array offset: 0x2280, array step: 0x4 */
+ uint8_t RESERVED_7[96];
+ __O uint32_t NOT[8]; /**< Port toggle, array offset: 0x2300, array step: 0x4 */
+ uint8_t RESERVED_8[96];
+ __O uint32_t DIRSET[8]; /**< Port direction set, array offset: 0x2380, array step: 0x4 */
+ uint8_t RESERVED_9[96];
+ __IO uint32_t DIRCLR[8]; /**< Port direction clear, array offset: 0x2400, array step: 0x4 */
+ uint8_t RESERVED_10[96];
+ __O uint32_t DIRNOT[8]; /**< Port direction toggle, array offset: 0x2480, array step: 0x4 */
+ uint8_t RESERVED_11[96];
+ __IO uint32_t INTENA[8]; /**< Interrupt A enable control, array offset: 0x2500, array step: 0x4 */
+ uint8_t RESERVED_12[96];
+ __IO uint32_t INTENB[8]; /**< Interrupt B enable control, array offset: 0x2580, array step: 0x4 */
+ uint8_t RESERVED_13[96];
+ __IO uint32_t INTPOL[8]; /**< Interupt polarity control, array offset: 0x2600, array step: 0x4 */
+ uint8_t RESERVED_14[96];
+ __IO uint32_t INTEDG[8]; /**< Interrupt edge select, array offset: 0x2680, array step: 0x4 */
+ uint8_t RESERVED_15[96];
+ __IO uint32_t INTSTATA[8]; /**< Interrupt status for interrupt A, array offset: 0x2700, array step: 0x4 */
+ uint8_t RESERVED_16[96];
+ __IO uint32_t INTSTATB[8]; /**< Interrupt status for interrupt B, array offset: 0x2780, array step: 0x4 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name B - Byte pin registers for all port GPIO pins */
+/*! @{ */
+#define GPIO_B_PBYTE_MASK (0x1U)
+#define GPIO_B_PBYTE_SHIFT (0U)
+/*! PBYTE - Port Byte
+ */
+#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
+/*! @} */
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT (7U)
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT2 (32U)
+
+/*! @name W - Word pin registers for all port GPIO pins */
+/*! @{ */
+#define GPIO_W_PWORD_MASK (0xFFFFFFFFU)
+#define GPIO_W_PWORD_SHIFT (0U)
+/*! PWORD - PWORD
+ */
+#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
+/*! @} */
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT (7U)
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT2 (32U)
+
+/*! @name DIR - Port direction */
+/*! @{ */
+#define GPIO_DIR_DIRP0_MASK (0x1U)
+#define GPIO_DIR_DIRP0_SHIFT (0U)
+/*! DIRP0 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP0_SHIFT)) & GPIO_DIR_DIRP0_MASK)
+#define GPIO_DIR_DIRP1_MASK (0x2U)
+#define GPIO_DIR_DIRP1_SHIFT (1U)
+/*! DIRP1 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP1_SHIFT)) & GPIO_DIR_DIRP1_MASK)
+#define GPIO_DIR_DIRP2_MASK (0x4U)
+#define GPIO_DIR_DIRP2_SHIFT (2U)
+/*! DIRP2 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP2_SHIFT)) & GPIO_DIR_DIRP2_MASK)
+#define GPIO_DIR_DIRP3_MASK (0x8U)
+#define GPIO_DIR_DIRP3_SHIFT (3U)
+/*! DIRP3 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP3_SHIFT)) & GPIO_DIR_DIRP3_MASK)
+#define GPIO_DIR_DIRP4_MASK (0x10U)
+#define GPIO_DIR_DIRP4_SHIFT (4U)
+/*! DIRP4 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP4_SHIFT)) & GPIO_DIR_DIRP4_MASK)
+#define GPIO_DIR_DIRP5_MASK (0x20U)
+#define GPIO_DIR_DIRP5_SHIFT (5U)
+/*! DIRP5 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP5_SHIFT)) & GPIO_DIR_DIRP5_MASK)
+#define GPIO_DIR_DIRP6_MASK (0x40U)
+#define GPIO_DIR_DIRP6_SHIFT (6U)
+/*! DIRP6 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP6_SHIFT)) & GPIO_DIR_DIRP6_MASK)
+#define GPIO_DIR_DIRP7_MASK (0x80U)
+#define GPIO_DIR_DIRP7_SHIFT (7U)
+/*! DIRP7 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP7_SHIFT)) & GPIO_DIR_DIRP7_MASK)
+#define GPIO_DIR_DIRP8_MASK (0x100U)
+#define GPIO_DIR_DIRP8_SHIFT (8U)
+/*! DIRP8 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP8_SHIFT)) & GPIO_DIR_DIRP8_MASK)
+#define GPIO_DIR_DIRP9_MASK (0x200U)
+#define GPIO_DIR_DIRP9_SHIFT (9U)
+/*! DIRP9 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP9_SHIFT)) & GPIO_DIR_DIRP9_MASK)
+#define GPIO_DIR_DIRP10_MASK (0x400U)
+#define GPIO_DIR_DIRP10_SHIFT (10U)
+/*! DIRP10 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP10_SHIFT)) & GPIO_DIR_DIRP10_MASK)
+#define GPIO_DIR_DIRP11_MASK (0x800U)
+#define GPIO_DIR_DIRP11_SHIFT (11U)
+/*! DIRP11 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP11_SHIFT)) & GPIO_DIR_DIRP11_MASK)
+#define GPIO_DIR_DIRP12_MASK (0x1000U)
+#define GPIO_DIR_DIRP12_SHIFT (12U)
+/*! DIRP12 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP12_SHIFT)) & GPIO_DIR_DIRP12_MASK)
+#define GPIO_DIR_DIRP13_MASK (0x2000U)
+#define GPIO_DIR_DIRP13_SHIFT (13U)
+/*! DIRP13 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP13_SHIFT)) & GPIO_DIR_DIRP13_MASK)
+#define GPIO_DIR_DIRP14_MASK (0x4000U)
+#define GPIO_DIR_DIRP14_SHIFT (14U)
+/*! DIRP14 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP14_SHIFT)) & GPIO_DIR_DIRP14_MASK)
+#define GPIO_DIR_DIRP15_MASK (0x8000U)
+#define GPIO_DIR_DIRP15_SHIFT (15U)
+/*! DIRP15 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP15_SHIFT)) & GPIO_DIR_DIRP15_MASK)
+#define GPIO_DIR_DIRP16_MASK (0x10000U)
+#define GPIO_DIR_DIRP16_SHIFT (16U)
+/*! DIRP16 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP16_SHIFT)) & GPIO_DIR_DIRP16_MASK)
+#define GPIO_DIR_DIRP17_MASK (0x20000U)
+#define GPIO_DIR_DIRP17_SHIFT (17U)
+/*! DIRP17 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP17_SHIFT)) & GPIO_DIR_DIRP17_MASK)
+#define GPIO_DIR_DIRP18_MASK (0x40000U)
+#define GPIO_DIR_DIRP18_SHIFT (18U)
+/*! DIRP18 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP18_SHIFT)) & GPIO_DIR_DIRP18_MASK)
+#define GPIO_DIR_DIRP19_MASK (0x80000U)
+#define GPIO_DIR_DIRP19_SHIFT (19U)
+/*! DIRP19 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP19_SHIFT)) & GPIO_DIR_DIRP19_MASK)
+#define GPIO_DIR_DIRP20_MASK (0x100000U)
+#define GPIO_DIR_DIRP20_SHIFT (20U)
+/*! DIRP20 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP20_SHIFT)) & GPIO_DIR_DIRP20_MASK)
+#define GPIO_DIR_DIRP21_MASK (0x200000U)
+#define GPIO_DIR_DIRP21_SHIFT (21U)
+/*! DIRP21 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP21_SHIFT)) & GPIO_DIR_DIRP21_MASK)
+#define GPIO_DIR_DIRP22_MASK (0x400000U)
+#define GPIO_DIR_DIRP22_SHIFT (22U)
+/*! DIRP22 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP22_SHIFT)) & GPIO_DIR_DIRP22_MASK)
+#define GPIO_DIR_DIRP23_MASK (0x800000U)
+#define GPIO_DIR_DIRP23_SHIFT (23U)
+/*! DIRP23 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP23_SHIFT)) & GPIO_DIR_DIRP23_MASK)
+#define GPIO_DIR_DIRP24_MASK (0x1000000U)
+#define GPIO_DIR_DIRP24_SHIFT (24U)
+/*! DIRP24 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP24_SHIFT)) & GPIO_DIR_DIRP24_MASK)
+#define GPIO_DIR_DIRP25_MASK (0x2000000U)
+#define GPIO_DIR_DIRP25_SHIFT (25U)
+/*! DIRP25 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP25_SHIFT)) & GPIO_DIR_DIRP25_MASK)
+#define GPIO_DIR_DIRP26_MASK (0x4000000U)
+#define GPIO_DIR_DIRP26_SHIFT (26U)
+/*! DIRP26 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP26_SHIFT)) & GPIO_DIR_DIRP26_MASK)
+#define GPIO_DIR_DIRP27_MASK (0x8000000U)
+#define GPIO_DIR_DIRP27_SHIFT (27U)
+/*! DIRP27 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP27_SHIFT)) & GPIO_DIR_DIRP27_MASK)
+#define GPIO_DIR_DIRP28_MASK (0x10000000U)
+#define GPIO_DIR_DIRP28_SHIFT (28U)
+/*! DIRP28 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP28_SHIFT)) & GPIO_DIR_DIRP28_MASK)
+#define GPIO_DIR_DIRP29_MASK (0x20000000U)
+#define GPIO_DIR_DIRP29_SHIFT (29U)
+/*! DIRP29 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP29_SHIFT)) & GPIO_DIR_DIRP29_MASK)
+#define GPIO_DIR_DIRP30_MASK (0x40000000U)
+#define GPIO_DIR_DIRP30_SHIFT (30U)
+/*! DIRP30 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP30_SHIFT)) & GPIO_DIR_DIRP30_MASK)
+#define GPIO_DIR_DIRP31_MASK (0x80000000U)
+#define GPIO_DIR_DIRP31_SHIFT (31U)
+/*! DIRP31 - Selects pin direction for pin PIOa_b.
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define GPIO_DIR_DIRP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP31_SHIFT)) & GPIO_DIR_DIRP31_MASK)
+/*! @} */
+
+/* The count of GPIO_DIR */
+#define GPIO_DIR_COUNT (8U)
+
+/*! @name MASK - Port mask */
+/*! @{ */
+#define GPIO_MASK_MASKP0_MASK (0x1U)
+#define GPIO_MASK_MASKP0_SHIFT (0U)
+/*! MASKP0 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP0_SHIFT)) & GPIO_MASK_MASKP0_MASK)
+#define GPIO_MASK_MASKP1_MASK (0x2U)
+#define GPIO_MASK_MASKP1_SHIFT (1U)
+/*! MASKP1 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP1_SHIFT)) & GPIO_MASK_MASKP1_MASK)
+#define GPIO_MASK_MASKP2_MASK (0x4U)
+#define GPIO_MASK_MASKP2_SHIFT (2U)
+/*! MASKP2 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP2_SHIFT)) & GPIO_MASK_MASKP2_MASK)
+#define GPIO_MASK_MASKP3_MASK (0x8U)
+#define GPIO_MASK_MASKP3_SHIFT (3U)
+/*! MASKP3 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP3_SHIFT)) & GPIO_MASK_MASKP3_MASK)
+#define GPIO_MASK_MASKP4_MASK (0x10U)
+#define GPIO_MASK_MASKP4_SHIFT (4U)
+/*! MASKP4 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP4_SHIFT)) & GPIO_MASK_MASKP4_MASK)
+#define GPIO_MASK_MASKP5_MASK (0x20U)
+#define GPIO_MASK_MASKP5_SHIFT (5U)
+/*! MASKP5 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP5_SHIFT)) & GPIO_MASK_MASKP5_MASK)
+#define GPIO_MASK_MASKP6_MASK (0x40U)
+#define GPIO_MASK_MASKP6_SHIFT (6U)
+/*! MASKP6 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP6_SHIFT)) & GPIO_MASK_MASKP6_MASK)
+#define GPIO_MASK_MASKP7_MASK (0x80U)
+#define GPIO_MASK_MASKP7_SHIFT (7U)
+/*! MASKP7 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP7_SHIFT)) & GPIO_MASK_MASKP7_MASK)
+#define GPIO_MASK_MASKP8_MASK (0x100U)
+#define GPIO_MASK_MASKP8_SHIFT (8U)
+/*! MASKP8 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP8_SHIFT)) & GPIO_MASK_MASKP8_MASK)
+#define GPIO_MASK_MASKP9_MASK (0x200U)
+#define GPIO_MASK_MASKP9_SHIFT (9U)
+/*! MASKP9 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP9_SHIFT)) & GPIO_MASK_MASKP9_MASK)
+#define GPIO_MASK_MASKP10_MASK (0x400U)
+#define GPIO_MASK_MASKP10_SHIFT (10U)
+/*! MASKP10 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP10_SHIFT)) & GPIO_MASK_MASKP10_MASK)
+#define GPIO_MASK_MASKP11_MASK (0x800U)
+#define GPIO_MASK_MASKP11_SHIFT (11U)
+/*! MASKP11 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP11_SHIFT)) & GPIO_MASK_MASKP11_MASK)
+#define GPIO_MASK_MASKP12_MASK (0x1000U)
+#define GPIO_MASK_MASKP12_SHIFT (12U)
+/*! MASKP12 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP12_SHIFT)) & GPIO_MASK_MASKP12_MASK)
+#define GPIO_MASK_MASKP13_MASK (0x2000U)
+#define GPIO_MASK_MASKP13_SHIFT (13U)
+/*! MASKP13 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP13_SHIFT)) & GPIO_MASK_MASKP13_MASK)
+#define GPIO_MASK_MASKP14_MASK (0x4000U)
+#define GPIO_MASK_MASKP14_SHIFT (14U)
+/*! MASKP14 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP14_SHIFT)) & GPIO_MASK_MASKP14_MASK)
+#define GPIO_MASK_MASKP15_MASK (0x8000U)
+#define GPIO_MASK_MASKP15_SHIFT (15U)
+/*! MASKP15 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP15_SHIFT)) & GPIO_MASK_MASKP15_MASK)
+#define GPIO_MASK_MASKP16_MASK (0x10000U)
+#define GPIO_MASK_MASKP16_SHIFT (16U)
+/*! MASKP16 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP16_SHIFT)) & GPIO_MASK_MASKP16_MASK)
+#define GPIO_MASK_MASKP17_MASK (0x20000U)
+#define GPIO_MASK_MASKP17_SHIFT (17U)
+/*! MASKP17 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP17_SHIFT)) & GPIO_MASK_MASKP17_MASK)
+#define GPIO_MASK_MASKP18_MASK (0x40000U)
+#define GPIO_MASK_MASKP18_SHIFT (18U)
+/*! MASKP18 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP18_SHIFT)) & GPIO_MASK_MASKP18_MASK)
+#define GPIO_MASK_MASKP19_MASK (0x80000U)
+#define GPIO_MASK_MASKP19_SHIFT (19U)
+/*! MASKP19 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP19_SHIFT)) & GPIO_MASK_MASKP19_MASK)
+#define GPIO_MASK_MASKP20_MASK (0x100000U)
+#define GPIO_MASK_MASKP20_SHIFT (20U)
+/*! MASKP20 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP20_SHIFT)) & GPIO_MASK_MASKP20_MASK)
+#define GPIO_MASK_MASKP21_MASK (0x200000U)
+#define GPIO_MASK_MASKP21_SHIFT (21U)
+/*! MASKP21 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP21_SHIFT)) & GPIO_MASK_MASKP21_MASK)
+#define GPIO_MASK_MASKP22_MASK (0x400000U)
+#define GPIO_MASK_MASKP22_SHIFT (22U)
+/*! MASKP22 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP22_SHIFT)) & GPIO_MASK_MASKP22_MASK)
+#define GPIO_MASK_MASKP23_MASK (0x800000U)
+#define GPIO_MASK_MASKP23_SHIFT (23U)
+/*! MASKP23 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP23_SHIFT)) & GPIO_MASK_MASKP23_MASK)
+#define GPIO_MASK_MASKP24_MASK (0x1000000U)
+#define GPIO_MASK_MASKP24_SHIFT (24U)
+/*! MASKP24 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP24_SHIFT)) & GPIO_MASK_MASKP24_MASK)
+#define GPIO_MASK_MASKP25_MASK (0x2000000U)
+#define GPIO_MASK_MASKP25_SHIFT (25U)
+/*! MASKP25 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP25_SHIFT)) & GPIO_MASK_MASKP25_MASK)
+#define GPIO_MASK_MASKP26_MASK (0x4000000U)
+#define GPIO_MASK_MASKP26_SHIFT (26U)
+/*! MASKP26 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP26_SHIFT)) & GPIO_MASK_MASKP26_MASK)
+#define GPIO_MASK_MASKP27_MASK (0x8000000U)
+#define GPIO_MASK_MASKP27_SHIFT (27U)
+/*! MASKP27 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP27_SHIFT)) & GPIO_MASK_MASKP27_MASK)
+#define GPIO_MASK_MASKP28_MASK (0x10000000U)
+#define GPIO_MASK_MASKP28_SHIFT (28U)
+/*! MASKP28 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP28_SHIFT)) & GPIO_MASK_MASKP28_MASK)
+#define GPIO_MASK_MASKP29_MASK (0x20000000U)
+#define GPIO_MASK_MASKP29_SHIFT (29U)
+/*! MASKP29 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP29_SHIFT)) & GPIO_MASK_MASKP29_MASK)
+#define GPIO_MASK_MASKP30_MASK (0x40000000U)
+#define GPIO_MASK_MASKP30_SHIFT (30U)
+/*! MASKP30 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP30_SHIFT)) & GPIO_MASK_MASKP30_MASK)
+#define GPIO_MASK_MASKP31_MASK (0x80000000U)
+#define GPIO_MASK_MASKP31_SHIFT (31U)
+/*! MASKP31 - Port Mask
+ * 0b0..Read MPIN: pin state; write MPIN: load output bit
+ * 0b1..Read MPIN: 0; write MPIN: output bit not affected
+ */
+#define GPIO_MASK_MASKP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP31_SHIFT)) & GPIO_MASK_MASKP31_MASK)
+/*! @} */
+
+/* The count of GPIO_MASK */
+#define GPIO_MASK_COUNT (8U)
+
+/*! @name PIN - Port pin */
+/*! @{ */
+#define GPIO_PIN_PORT0_MASK (0x1U)
+#define GPIO_PIN_PORT0_SHIFT (0U)
+/*! PORT0 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT0_SHIFT)) & GPIO_PIN_PORT0_MASK)
+#define GPIO_PIN_PORT1_MASK (0x2U)
+#define GPIO_PIN_PORT1_SHIFT (1U)
+/*! PORT1 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT1_SHIFT)) & GPIO_PIN_PORT1_MASK)
+#define GPIO_PIN_PORT2_MASK (0x4U)
+#define GPIO_PIN_PORT2_SHIFT (2U)
+/*! PORT2 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT2_SHIFT)) & GPIO_PIN_PORT2_MASK)
+#define GPIO_PIN_PORT3_MASK (0x8U)
+#define GPIO_PIN_PORT3_SHIFT (3U)
+/*! PORT3 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT3_SHIFT)) & GPIO_PIN_PORT3_MASK)
+#define GPIO_PIN_PORT4_MASK (0x10U)
+#define GPIO_PIN_PORT4_SHIFT (4U)
+/*! PORT4 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT4_SHIFT)) & GPIO_PIN_PORT4_MASK)
+#define GPIO_PIN_PORT5_MASK (0x20U)
+#define GPIO_PIN_PORT5_SHIFT (5U)
+/*! PORT5 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT5_SHIFT)) & GPIO_PIN_PORT5_MASK)
+#define GPIO_PIN_PORT6_MASK (0x40U)
+#define GPIO_PIN_PORT6_SHIFT (6U)
+/*! PORT6 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT6_SHIFT)) & GPIO_PIN_PORT6_MASK)
+#define GPIO_PIN_PORT7_MASK (0x80U)
+#define GPIO_PIN_PORT7_SHIFT (7U)
+/*! PORT7 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT7_SHIFT)) & GPIO_PIN_PORT7_MASK)
+#define GPIO_PIN_PORT8_MASK (0x100U)
+#define GPIO_PIN_PORT8_SHIFT (8U)
+/*! PORT8 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT8_SHIFT)) & GPIO_PIN_PORT8_MASK)
+#define GPIO_PIN_PORT9_MASK (0x200U)
+#define GPIO_PIN_PORT9_SHIFT (9U)
+/*! PORT9 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT9_SHIFT)) & GPIO_PIN_PORT9_MASK)
+#define GPIO_PIN_PORT10_MASK (0x400U)
+#define GPIO_PIN_PORT10_SHIFT (10U)
+/*! PORT10 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT10_SHIFT)) & GPIO_PIN_PORT10_MASK)
+#define GPIO_PIN_PORT11_MASK (0x800U)
+#define GPIO_PIN_PORT11_SHIFT (11U)
+/*! PORT11 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT11_SHIFT)) & GPIO_PIN_PORT11_MASK)
+#define GPIO_PIN_PORT12_MASK (0x1000U)
+#define GPIO_PIN_PORT12_SHIFT (12U)
+/*! PORT12 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT12_SHIFT)) & GPIO_PIN_PORT12_MASK)
+#define GPIO_PIN_PORT13_MASK (0x2000U)
+#define GPIO_PIN_PORT13_SHIFT (13U)
+/*! PORT13 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT13_SHIFT)) & GPIO_PIN_PORT13_MASK)
+#define GPIO_PIN_PORT14_MASK (0x4000U)
+#define GPIO_PIN_PORT14_SHIFT (14U)
+/*! PORT14 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT14_SHIFT)) & GPIO_PIN_PORT14_MASK)
+#define GPIO_PIN_PORT15_MASK (0x8000U)
+#define GPIO_PIN_PORT15_SHIFT (15U)
+/*! PORT15 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT15_SHIFT)) & GPIO_PIN_PORT15_MASK)
+#define GPIO_PIN_PORT16_MASK (0x10000U)
+#define GPIO_PIN_PORT16_SHIFT (16U)
+/*! PORT16 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT16_SHIFT)) & GPIO_PIN_PORT16_MASK)
+#define GPIO_PIN_PORT17_MASK (0x20000U)
+#define GPIO_PIN_PORT17_SHIFT (17U)
+/*! PORT17 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT17_SHIFT)) & GPIO_PIN_PORT17_MASK)
+#define GPIO_PIN_PORT18_MASK (0x40000U)
+#define GPIO_PIN_PORT18_SHIFT (18U)
+/*! PORT18 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT18_SHIFT)) & GPIO_PIN_PORT18_MASK)
+#define GPIO_PIN_PORT19_MASK (0x80000U)
+#define GPIO_PIN_PORT19_SHIFT (19U)
+/*! PORT19 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT19_SHIFT)) & GPIO_PIN_PORT19_MASK)
+#define GPIO_PIN_PORT20_MASK (0x100000U)
+#define GPIO_PIN_PORT20_SHIFT (20U)
+/*! PORT20 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT20_SHIFT)) & GPIO_PIN_PORT20_MASK)
+#define GPIO_PIN_PORT21_MASK (0x200000U)
+#define GPIO_PIN_PORT21_SHIFT (21U)
+/*! PORT21 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT21_SHIFT)) & GPIO_PIN_PORT21_MASK)
+#define GPIO_PIN_PORT22_MASK (0x400000U)
+#define GPIO_PIN_PORT22_SHIFT (22U)
+/*! PORT22 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT22_SHIFT)) & GPIO_PIN_PORT22_MASK)
+#define GPIO_PIN_PORT23_MASK (0x800000U)
+#define GPIO_PIN_PORT23_SHIFT (23U)
+/*! PORT23 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT23_SHIFT)) & GPIO_PIN_PORT23_MASK)
+#define GPIO_PIN_PORT24_MASK (0x1000000U)
+#define GPIO_PIN_PORT24_SHIFT (24U)
+/*! PORT24 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT24_SHIFT)) & GPIO_PIN_PORT24_MASK)
+#define GPIO_PIN_PORT25_MASK (0x2000000U)
+#define GPIO_PIN_PORT25_SHIFT (25U)
+/*! PORT25 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT25_SHIFT)) & GPIO_PIN_PORT25_MASK)
+#define GPIO_PIN_PORT26_MASK (0x4000000U)
+#define GPIO_PIN_PORT26_SHIFT (26U)
+/*! PORT26 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT26_SHIFT)) & GPIO_PIN_PORT26_MASK)
+#define GPIO_PIN_PORT27_MASK (0x8000000U)
+#define GPIO_PIN_PORT27_SHIFT (27U)
+/*! PORT27 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT27_SHIFT)) & GPIO_PIN_PORT27_MASK)
+#define GPIO_PIN_PORT28_MASK (0x10000000U)
+#define GPIO_PIN_PORT28_SHIFT (28U)
+/*! PORT28 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT28_SHIFT)) & GPIO_PIN_PORT28_MASK)
+#define GPIO_PIN_PORT29_MASK (0x20000000U)
+#define GPIO_PIN_PORT29_SHIFT (29U)
+/*! PORT29 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT29_SHIFT)) & GPIO_PIN_PORT29_MASK)
+#define GPIO_PIN_PORT30_MASK (0x40000000U)
+#define GPIO_PIN_PORT30_SHIFT (30U)
+/*! PORT30 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT30_SHIFT)) & GPIO_PIN_PORT30_MASK)
+#define GPIO_PIN_PORT31_MASK (0x80000000U)
+#define GPIO_PIN_PORT31_SHIFT (31U)
+/*! PORT31 - Port pins
+ * 0b0..Read- pin is low; Write- clear output bit
+ * 0b1..Read- pin is high; Write- set output bit
+ */
+#define GPIO_PIN_PORT31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT31_SHIFT)) & GPIO_PIN_PORT31_MASK)
+/*! @} */
+
+/* The count of GPIO_PIN */
+#define GPIO_PIN_COUNT (8U)
+
+/*! @name MPIN - Masked Port Pin */
+/*! @{ */
+#define GPIO_MPIN_MPORTP0_MASK (0x1U)
+#define GPIO_MPIN_MPORTP0_SHIFT (0U)
+/*! MPORTP0 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP0_SHIFT)) & GPIO_MPIN_MPORTP0_MASK)
+#define GPIO_MPIN_MPORTP1_MASK (0x2U)
+#define GPIO_MPIN_MPORTP1_SHIFT (1U)
+/*! MPORTP1 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP1_SHIFT)) & GPIO_MPIN_MPORTP1_MASK)
+#define GPIO_MPIN_MPORTP2_MASK (0x4U)
+#define GPIO_MPIN_MPORTP2_SHIFT (2U)
+/*! MPORTP2 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP2_SHIFT)) & GPIO_MPIN_MPORTP2_MASK)
+#define GPIO_MPIN_MPORTP3_MASK (0x8U)
+#define GPIO_MPIN_MPORTP3_SHIFT (3U)
+/*! MPORTP3 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP3_SHIFT)) & GPIO_MPIN_MPORTP3_MASK)
+#define GPIO_MPIN_MPORTP4_MASK (0x10U)
+#define GPIO_MPIN_MPORTP4_SHIFT (4U)
+/*! MPORTP4 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP4_SHIFT)) & GPIO_MPIN_MPORTP4_MASK)
+#define GPIO_MPIN_MPORTP5_MASK (0x20U)
+#define GPIO_MPIN_MPORTP5_SHIFT (5U)
+/*! MPORTP5 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP5_SHIFT)) & GPIO_MPIN_MPORTP5_MASK)
+#define GPIO_MPIN_MPORTP6_MASK (0x40U)
+#define GPIO_MPIN_MPORTP6_SHIFT (6U)
+/*! MPORTP6 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP6_SHIFT)) & GPIO_MPIN_MPORTP6_MASK)
+#define GPIO_MPIN_MPORTP7_MASK (0x80U)
+#define GPIO_MPIN_MPORTP7_SHIFT (7U)
+/*! MPORTP7 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP7_SHIFT)) & GPIO_MPIN_MPORTP7_MASK)
+#define GPIO_MPIN_MPORTP8_MASK (0x100U)
+#define GPIO_MPIN_MPORTP8_SHIFT (8U)
+/*! MPORTP8 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP8_SHIFT)) & GPIO_MPIN_MPORTP8_MASK)
+#define GPIO_MPIN_MPORTP9_MASK (0x200U)
+#define GPIO_MPIN_MPORTP9_SHIFT (9U)
+/*! MPORTP9 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP9_SHIFT)) & GPIO_MPIN_MPORTP9_MASK)
+#define GPIO_MPIN_MPORTP10_MASK (0x400U)
+#define GPIO_MPIN_MPORTP10_SHIFT (10U)
+/*! MPORTP10 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP10_SHIFT)) & GPIO_MPIN_MPORTP10_MASK)
+#define GPIO_MPIN_MPORTP11_MASK (0x800U)
+#define GPIO_MPIN_MPORTP11_SHIFT (11U)
+/*! MPORTP11 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP11_SHIFT)) & GPIO_MPIN_MPORTP11_MASK)
+#define GPIO_MPIN_MPORTP12_MASK (0x1000U)
+#define GPIO_MPIN_MPORTP12_SHIFT (12U)
+/*! MPORTP12 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP12_SHIFT)) & GPIO_MPIN_MPORTP12_MASK)
+#define GPIO_MPIN_MPORTP13_MASK (0x2000U)
+#define GPIO_MPIN_MPORTP13_SHIFT (13U)
+/*! MPORTP13 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP13_SHIFT)) & GPIO_MPIN_MPORTP13_MASK)
+#define GPIO_MPIN_MPORTP14_MASK (0x4000U)
+#define GPIO_MPIN_MPORTP14_SHIFT (14U)
+/*! MPORTP14 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP14_SHIFT)) & GPIO_MPIN_MPORTP14_MASK)
+#define GPIO_MPIN_MPORTP15_MASK (0x8000U)
+#define GPIO_MPIN_MPORTP15_SHIFT (15U)
+/*! MPORTP15 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP15_SHIFT)) & GPIO_MPIN_MPORTP15_MASK)
+#define GPIO_MPIN_MPORTP16_MASK (0x10000U)
+#define GPIO_MPIN_MPORTP16_SHIFT (16U)
+/*! MPORTP16 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP16_SHIFT)) & GPIO_MPIN_MPORTP16_MASK)
+#define GPIO_MPIN_MPORTP17_MASK (0x20000U)
+#define GPIO_MPIN_MPORTP17_SHIFT (17U)
+/*! MPORTP17 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP17_SHIFT)) & GPIO_MPIN_MPORTP17_MASK)
+#define GPIO_MPIN_MPORTP18_MASK (0x40000U)
+#define GPIO_MPIN_MPORTP18_SHIFT (18U)
+/*! MPORTP18 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP18_SHIFT)) & GPIO_MPIN_MPORTP18_MASK)
+#define GPIO_MPIN_MPORTP19_MASK (0x80000U)
+#define GPIO_MPIN_MPORTP19_SHIFT (19U)
+/*! MPORTP19 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP19_SHIFT)) & GPIO_MPIN_MPORTP19_MASK)
+#define GPIO_MPIN_MPORTP20_MASK (0x100000U)
+#define GPIO_MPIN_MPORTP20_SHIFT (20U)
+/*! MPORTP20 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP20_SHIFT)) & GPIO_MPIN_MPORTP20_MASK)
+#define GPIO_MPIN_MPORTP21_MASK (0x200000U)
+#define GPIO_MPIN_MPORTP21_SHIFT (21U)
+/*! MPORTP21 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP21_SHIFT)) & GPIO_MPIN_MPORTP21_MASK)
+#define GPIO_MPIN_MPORTP22_MASK (0x400000U)
+#define GPIO_MPIN_MPORTP22_SHIFT (22U)
+/*! MPORTP22 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP22_SHIFT)) & GPIO_MPIN_MPORTP22_MASK)
+#define GPIO_MPIN_MPORTP23_MASK (0x800000U)
+#define GPIO_MPIN_MPORTP23_SHIFT (23U)
+/*! MPORTP23 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP23_SHIFT)) & GPIO_MPIN_MPORTP23_MASK)
+#define GPIO_MPIN_MPORTP24_MASK (0x1000000U)
+#define GPIO_MPIN_MPORTP24_SHIFT (24U)
+/*! MPORTP24 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP24_SHIFT)) & GPIO_MPIN_MPORTP24_MASK)
+#define GPIO_MPIN_MPORTP25_MASK (0x2000000U)
+#define GPIO_MPIN_MPORTP25_SHIFT (25U)
+/*! MPORTP25 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP25_SHIFT)) & GPIO_MPIN_MPORTP25_MASK)
+#define GPIO_MPIN_MPORTP26_MASK (0x4000000U)
+#define GPIO_MPIN_MPORTP26_SHIFT (26U)
+/*! MPORTP26 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP26_SHIFT)) & GPIO_MPIN_MPORTP26_MASK)
+#define GPIO_MPIN_MPORTP27_MASK (0x8000000U)
+#define GPIO_MPIN_MPORTP27_SHIFT (27U)
+/*! MPORTP27 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP27_SHIFT)) & GPIO_MPIN_MPORTP27_MASK)
+#define GPIO_MPIN_MPORTP28_MASK (0x10000000U)
+#define GPIO_MPIN_MPORTP28_SHIFT (28U)
+/*! MPORTP28 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP28_SHIFT)) & GPIO_MPIN_MPORTP28_MASK)
+#define GPIO_MPIN_MPORTP29_MASK (0x20000000U)
+#define GPIO_MPIN_MPORTP29_SHIFT (29U)
+/*! MPORTP29 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP29_SHIFT)) & GPIO_MPIN_MPORTP29_MASK)
+#define GPIO_MPIN_MPORTP30_MASK (0x40000000U)
+#define GPIO_MPIN_MPORTP30_SHIFT (30U)
+/*! MPORTP30 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP30_SHIFT)) & GPIO_MPIN_MPORTP30_MASK)
+#define GPIO_MPIN_MPORTP31_MASK (0x80000000U)
+#define GPIO_MPIN_MPORTP31_SHIFT (31U)
+/*! MPORTP31 - Mask bits for port pins
+ * 0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
+ * corresponding bit in the MASK register is 0
+ * 0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
+ * corresponding bit in the MASK register is 0
+ */
+#define GPIO_MPIN_MPORTP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP31_SHIFT)) & GPIO_MPIN_MPORTP31_MASK)
+/*! @} */
+
+/* The count of GPIO_MPIN */
+#define GPIO_MPIN_COUNT (8U)
+
+/*! @name SET - Port set */
+/*! @{ */
+#define GPIO_SET_SETP_MASK (0xFFFFFFFFU)
+#define GPIO_SET_SETP_SHIFT (0U)
+/*! SETP - Read or set output bits
+ * 0b00000000000000000000000000000000..Read- output bit; write- no operation
+ * 0b00000000000000000000000000000001..Read- output bit; write- set output bit
+ */
+#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
+/*! @} */
+
+/* The count of GPIO_SET */
+#define GPIO_SET_COUNT (8U)
+
+/*! @name CLR - Port clear */
+/*! @{ */
+#define GPIO_CLR_CLRP0_MASK (0x1U)
+#define GPIO_CLR_CLRP0_SHIFT (0U)
+/*! CLRP0 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP0_SHIFT)) & GPIO_CLR_CLRP0_MASK)
+#define GPIO_CLR_CLRP1_MASK (0x2U)
+#define GPIO_CLR_CLRP1_SHIFT (1U)
+/*! CLRP1 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP1_SHIFT)) & GPIO_CLR_CLRP1_MASK)
+#define GPIO_CLR_CLRP2_MASK (0x4U)
+#define GPIO_CLR_CLRP2_SHIFT (2U)
+/*! CLRP2 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP2_SHIFT)) & GPIO_CLR_CLRP2_MASK)
+#define GPIO_CLR_CLRP3_MASK (0x8U)
+#define GPIO_CLR_CLRP3_SHIFT (3U)
+/*! CLRP3 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP3_SHIFT)) & GPIO_CLR_CLRP3_MASK)
+#define GPIO_CLR_CLRP4_MASK (0x10U)
+#define GPIO_CLR_CLRP4_SHIFT (4U)
+/*! CLRP4 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP4_SHIFT)) & GPIO_CLR_CLRP4_MASK)
+#define GPIO_CLR_CLRP5_MASK (0x20U)
+#define GPIO_CLR_CLRP5_SHIFT (5U)
+/*! CLRP5 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP5_SHIFT)) & GPIO_CLR_CLRP5_MASK)
+#define GPIO_CLR_CLRP6_MASK (0x40U)
+#define GPIO_CLR_CLRP6_SHIFT (6U)
+/*! CLRP6 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP6_SHIFT)) & GPIO_CLR_CLRP6_MASK)
+#define GPIO_CLR_CLRP7_MASK (0x80U)
+#define GPIO_CLR_CLRP7_SHIFT (7U)
+/*! CLRP7 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP7_SHIFT)) & GPIO_CLR_CLRP7_MASK)
+#define GPIO_CLR_CLRP8_MASK (0x100U)
+#define GPIO_CLR_CLRP8_SHIFT (8U)
+/*! CLRP8 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP8_SHIFT)) & GPIO_CLR_CLRP8_MASK)
+#define GPIO_CLR_CLRP9_MASK (0x200U)
+#define GPIO_CLR_CLRP9_SHIFT (9U)
+/*! CLRP9 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP9_SHIFT)) & GPIO_CLR_CLRP9_MASK)
+#define GPIO_CLR_CLRP10_MASK (0x400U)
+#define GPIO_CLR_CLRP10_SHIFT (10U)
+/*! CLRP10 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP10_SHIFT)) & GPIO_CLR_CLRP10_MASK)
+#define GPIO_CLR_CLRP11_MASK (0x800U)
+#define GPIO_CLR_CLRP11_SHIFT (11U)
+/*! CLRP11 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP11_SHIFT)) & GPIO_CLR_CLRP11_MASK)
+#define GPIO_CLR_CLRP12_MASK (0x1000U)
+#define GPIO_CLR_CLRP12_SHIFT (12U)
+/*! CLRP12 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP12_SHIFT)) & GPIO_CLR_CLRP12_MASK)
+#define GPIO_CLR_CLRP13_MASK (0x2000U)
+#define GPIO_CLR_CLRP13_SHIFT (13U)
+/*! CLRP13 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP13_SHIFT)) & GPIO_CLR_CLRP13_MASK)
+#define GPIO_CLR_CLRP14_MASK (0x4000U)
+#define GPIO_CLR_CLRP14_SHIFT (14U)
+/*! CLRP14 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP14_SHIFT)) & GPIO_CLR_CLRP14_MASK)
+#define GPIO_CLR_CLRP15_MASK (0x8000U)
+#define GPIO_CLR_CLRP15_SHIFT (15U)
+/*! CLRP15 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP15_SHIFT)) & GPIO_CLR_CLRP15_MASK)
+#define GPIO_CLR_CLRP16_MASK (0x10000U)
+#define GPIO_CLR_CLRP16_SHIFT (16U)
+/*! CLRP16 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP16_SHIFT)) & GPIO_CLR_CLRP16_MASK)
+#define GPIO_CLR_CLRP17_MASK (0x20000U)
+#define GPIO_CLR_CLRP17_SHIFT (17U)
+/*! CLRP17 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP17_SHIFT)) & GPIO_CLR_CLRP17_MASK)
+#define GPIO_CLR_CLRP18_MASK (0x40000U)
+#define GPIO_CLR_CLRP18_SHIFT (18U)
+/*! CLRP18 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP18_SHIFT)) & GPIO_CLR_CLRP18_MASK)
+#define GPIO_CLR_CLRP19_MASK (0x80000U)
+#define GPIO_CLR_CLRP19_SHIFT (19U)
+/*! CLRP19 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP19_SHIFT)) & GPIO_CLR_CLRP19_MASK)
+#define GPIO_CLR_CLRP20_MASK (0x100000U)
+#define GPIO_CLR_CLRP20_SHIFT (20U)
+/*! CLRP20 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP20_SHIFT)) & GPIO_CLR_CLRP20_MASK)
+#define GPIO_CLR_CLRP21_MASK (0x200000U)
+#define GPIO_CLR_CLRP21_SHIFT (21U)
+/*! CLRP21 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP21_SHIFT)) & GPIO_CLR_CLRP21_MASK)
+#define GPIO_CLR_CLRP22_MASK (0x400000U)
+#define GPIO_CLR_CLRP22_SHIFT (22U)
+/*! CLRP22 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP22_SHIFT)) & GPIO_CLR_CLRP22_MASK)
+#define GPIO_CLR_CLRP23_MASK (0x800000U)
+#define GPIO_CLR_CLRP23_SHIFT (23U)
+/*! CLRP23 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP23_SHIFT)) & GPIO_CLR_CLRP23_MASK)
+#define GPIO_CLR_CLRP24_MASK (0x1000000U)
+#define GPIO_CLR_CLRP24_SHIFT (24U)
+/*! CLRP24 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP24_SHIFT)) & GPIO_CLR_CLRP24_MASK)
+#define GPIO_CLR_CLRP25_MASK (0x2000000U)
+#define GPIO_CLR_CLRP25_SHIFT (25U)
+/*! CLRP25 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP25_SHIFT)) & GPIO_CLR_CLRP25_MASK)
+#define GPIO_CLR_CLRP26_MASK (0x4000000U)
+#define GPIO_CLR_CLRP26_SHIFT (26U)
+/*! CLRP26 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP26_SHIFT)) & GPIO_CLR_CLRP26_MASK)
+#define GPIO_CLR_CLRP27_MASK (0x8000000U)
+#define GPIO_CLR_CLRP27_SHIFT (27U)
+/*! CLRP27 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP27_SHIFT)) & GPIO_CLR_CLRP27_MASK)
+#define GPIO_CLR_CLRP28_MASK (0x10000000U)
+#define GPIO_CLR_CLRP28_SHIFT (28U)
+/*! CLRP28 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP28_SHIFT)) & GPIO_CLR_CLRP28_MASK)
+#define GPIO_CLR_CLRP29_MASK (0x20000000U)
+#define GPIO_CLR_CLRP29_SHIFT (29U)
+/*! CLRP29 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP29_SHIFT)) & GPIO_CLR_CLRP29_MASK)
+#define GPIO_CLR_CLRP30_MASK (0x40000000U)
+#define GPIO_CLR_CLRP30_SHIFT (30U)
+/*! CLRP30 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP30_SHIFT)) & GPIO_CLR_CLRP30_MASK)
+#define GPIO_CLR_CLRP31_MASK (0x80000000U)
+#define GPIO_CLR_CLRP31_SHIFT (31U)
+/*! CLRP31 - Clear output bits
+ * 0b0..No operation
+ * 0b1..Clears output bit
+ */
+#define GPIO_CLR_CLRP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP31_SHIFT)) & GPIO_CLR_CLRP31_MASK)
+/*! @} */
+
+/* The count of GPIO_CLR */
+#define GPIO_CLR_COUNT (8U)
+
+/*! @name NOT - Port toggle */
+/*! @{ */
+#define GPIO_NOT_NOTP0_MASK (0x1U)
+#define GPIO_NOT_NOTP0_SHIFT (0U)
+/*! NOTP0 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP0_SHIFT)) & GPIO_NOT_NOTP0_MASK)
+#define GPIO_NOT_NOTP1_MASK (0x2U)
+#define GPIO_NOT_NOTP1_SHIFT (1U)
+/*! NOTP1 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP1_SHIFT)) & GPIO_NOT_NOTP1_MASK)
+#define GPIO_NOT_NOTP2_MASK (0x4U)
+#define GPIO_NOT_NOTP2_SHIFT (2U)
+/*! NOTP2 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP2_SHIFT)) & GPIO_NOT_NOTP2_MASK)
+#define GPIO_NOT_NOTP3_MASK (0x8U)
+#define GPIO_NOT_NOTP3_SHIFT (3U)
+/*! NOTP3 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP3_SHIFT)) & GPIO_NOT_NOTP3_MASK)
+#define GPIO_NOT_NOTP4_MASK (0x10U)
+#define GPIO_NOT_NOTP4_SHIFT (4U)
+/*! NOTP4 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP4_SHIFT)) & GPIO_NOT_NOTP4_MASK)
+#define GPIO_NOT_NOTP5_MASK (0x20U)
+#define GPIO_NOT_NOTP5_SHIFT (5U)
+/*! NOTP5 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP5_SHIFT)) & GPIO_NOT_NOTP5_MASK)
+#define GPIO_NOT_NOTP6_MASK (0x40U)
+#define GPIO_NOT_NOTP6_SHIFT (6U)
+/*! NOTP6 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP6_SHIFT)) & GPIO_NOT_NOTP6_MASK)
+#define GPIO_NOT_NOTP7_MASK (0x80U)
+#define GPIO_NOT_NOTP7_SHIFT (7U)
+/*! NOTP7 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP7_SHIFT)) & GPIO_NOT_NOTP7_MASK)
+#define GPIO_NOT_NOTP8_MASK (0x100U)
+#define GPIO_NOT_NOTP8_SHIFT (8U)
+/*! NOTP8 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP8_SHIFT)) & GPIO_NOT_NOTP8_MASK)
+#define GPIO_NOT_NOTP9_MASK (0x200U)
+#define GPIO_NOT_NOTP9_SHIFT (9U)
+/*! NOTP9 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP9_SHIFT)) & GPIO_NOT_NOTP9_MASK)
+#define GPIO_NOT_NOTP10_MASK (0x400U)
+#define GPIO_NOT_NOTP10_SHIFT (10U)
+/*! NOTP10 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP10_SHIFT)) & GPIO_NOT_NOTP10_MASK)
+#define GPIO_NOT_NOTP11_MASK (0x800U)
+#define GPIO_NOT_NOTP11_SHIFT (11U)
+/*! NOTP11 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP11_SHIFT)) & GPIO_NOT_NOTP11_MASK)
+#define GPIO_NOT_NOTP12_MASK (0x1000U)
+#define GPIO_NOT_NOTP12_SHIFT (12U)
+/*! NOTP12 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP12_SHIFT)) & GPIO_NOT_NOTP12_MASK)
+#define GPIO_NOT_NOTP13_MASK (0x2000U)
+#define GPIO_NOT_NOTP13_SHIFT (13U)
+/*! NOTP13 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP13_SHIFT)) & GPIO_NOT_NOTP13_MASK)
+#define GPIO_NOT_NOTP14_MASK (0x4000U)
+#define GPIO_NOT_NOTP14_SHIFT (14U)
+/*! NOTP14 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP14_SHIFT)) & GPIO_NOT_NOTP14_MASK)
+#define GPIO_NOT_NOTP15_MASK (0x8000U)
+#define GPIO_NOT_NOTP15_SHIFT (15U)
+/*! NOTP15 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP15_SHIFT)) & GPIO_NOT_NOTP15_MASK)
+#define GPIO_NOT_NOTP16_MASK (0x10000U)
+#define GPIO_NOT_NOTP16_SHIFT (16U)
+/*! NOTP16 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP16_SHIFT)) & GPIO_NOT_NOTP16_MASK)
+#define GPIO_NOT_NOTP17_MASK (0x20000U)
+#define GPIO_NOT_NOTP17_SHIFT (17U)
+/*! NOTP17 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP17_SHIFT)) & GPIO_NOT_NOTP17_MASK)
+#define GPIO_NOT_NOTP18_MASK (0x40000U)
+#define GPIO_NOT_NOTP18_SHIFT (18U)
+/*! NOTP18 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP18_SHIFT)) & GPIO_NOT_NOTP18_MASK)
+#define GPIO_NOT_NOTP19_MASK (0x80000U)
+#define GPIO_NOT_NOTP19_SHIFT (19U)
+/*! NOTP19 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP19_SHIFT)) & GPIO_NOT_NOTP19_MASK)
+#define GPIO_NOT_NOTP20_MASK (0x100000U)
+#define GPIO_NOT_NOTP20_SHIFT (20U)
+/*! NOTP20 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP20_SHIFT)) & GPIO_NOT_NOTP20_MASK)
+#define GPIO_NOT_NOTP21_MASK (0x200000U)
+#define GPIO_NOT_NOTP21_SHIFT (21U)
+/*! NOTP21 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP21_SHIFT)) & GPIO_NOT_NOTP21_MASK)
+#define GPIO_NOT_NOTP22_MASK (0x400000U)
+#define GPIO_NOT_NOTP22_SHIFT (22U)
+/*! NOTP22 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP22_SHIFT)) & GPIO_NOT_NOTP22_MASK)
+#define GPIO_NOT_NOTP23_MASK (0x800000U)
+#define GPIO_NOT_NOTP23_SHIFT (23U)
+/*! NOTP23 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP23_SHIFT)) & GPIO_NOT_NOTP23_MASK)
+#define GPIO_NOT_NOTP24_MASK (0x1000000U)
+#define GPIO_NOT_NOTP24_SHIFT (24U)
+/*! NOTP24 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP24_SHIFT)) & GPIO_NOT_NOTP24_MASK)
+#define GPIO_NOT_NOTP25_MASK (0x2000000U)
+#define GPIO_NOT_NOTP25_SHIFT (25U)
+/*! NOTP25 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP25_SHIFT)) & GPIO_NOT_NOTP25_MASK)
+#define GPIO_NOT_NOTP26_MASK (0x4000000U)
+#define GPIO_NOT_NOTP26_SHIFT (26U)
+/*! NOTP26 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP26_SHIFT)) & GPIO_NOT_NOTP26_MASK)
+#define GPIO_NOT_NOTP27_MASK (0x8000000U)
+#define GPIO_NOT_NOTP27_SHIFT (27U)
+/*! NOTP27 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP27_SHIFT)) & GPIO_NOT_NOTP27_MASK)
+#define GPIO_NOT_NOTP28_MASK (0x10000000U)
+#define GPIO_NOT_NOTP28_SHIFT (28U)
+/*! NOTP28 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP28_SHIFT)) & GPIO_NOT_NOTP28_MASK)
+#define GPIO_NOT_NOTP29_MASK (0x20000000U)
+#define GPIO_NOT_NOTP29_SHIFT (29U)
+/*! NOTP29 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP29_SHIFT)) & GPIO_NOT_NOTP29_MASK)
+#define GPIO_NOT_NOTP30_MASK (0x40000000U)
+#define GPIO_NOT_NOTP30_SHIFT (30U)
+/*! NOTP30 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP30_SHIFT)) & GPIO_NOT_NOTP30_MASK)
+#define GPIO_NOT_NOTP31_MASK (0x80000000U)
+#define GPIO_NOT_NOTP31_SHIFT (31U)
+/*! NOTP31 - Toggle output bits
+ * 0b0..No operation
+ * 0b1..Toggle output bit
+ */
+#define GPIO_NOT_NOTP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP31_SHIFT)) & GPIO_NOT_NOTP31_MASK)
+/*! @} */
+
+/* The count of GPIO_NOT */
+#define GPIO_NOT_COUNT (8U)
+
+/*! @name DIRSET - Port direction set */
+/*! @{ */
+#define GPIO_DIRSET_DIRSETP0_MASK (0x1U)
+#define GPIO_DIRSET_DIRSETP0_SHIFT (0U)
+/*! DIRSETP0 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP0_SHIFT)) & GPIO_DIRSET_DIRSETP0_MASK)
+#define GPIO_DIRSET_DIRSETP1_MASK (0x2U)
+#define GPIO_DIRSET_DIRSETP1_SHIFT (1U)
+/*! DIRSETP1 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP1_SHIFT)) & GPIO_DIRSET_DIRSETP1_MASK)
+#define GPIO_DIRSET_DIRSETP2_MASK (0x4U)
+#define GPIO_DIRSET_DIRSETP2_SHIFT (2U)
+/*! DIRSETP2 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP2_SHIFT)) & GPIO_DIRSET_DIRSETP2_MASK)
+#define GPIO_DIRSET_DIRSETP3_MASK (0x8U)
+#define GPIO_DIRSET_DIRSETP3_SHIFT (3U)
+/*! DIRSETP3 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP3_SHIFT)) & GPIO_DIRSET_DIRSETP3_MASK)
+#define GPIO_DIRSET_DIRSETP4_MASK (0x10U)
+#define GPIO_DIRSET_DIRSETP4_SHIFT (4U)
+/*! DIRSETP4 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP4_SHIFT)) & GPIO_DIRSET_DIRSETP4_MASK)
+#define GPIO_DIRSET_DIRSETP5_MASK (0x20U)
+#define GPIO_DIRSET_DIRSETP5_SHIFT (5U)
+/*! DIRSETP5 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP5_SHIFT)) & GPIO_DIRSET_DIRSETP5_MASK)
+#define GPIO_DIRSET_DIRSETP6_MASK (0x40U)
+#define GPIO_DIRSET_DIRSETP6_SHIFT (6U)
+/*! DIRSETP6 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP6_SHIFT)) & GPIO_DIRSET_DIRSETP6_MASK)
+#define GPIO_DIRSET_DIRSETP7_MASK (0x80U)
+#define GPIO_DIRSET_DIRSETP7_SHIFT (7U)
+/*! DIRSETP7 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP7_SHIFT)) & GPIO_DIRSET_DIRSETP7_MASK)
+#define GPIO_DIRSET_DIRSETP8_MASK (0x100U)
+#define GPIO_DIRSET_DIRSETP8_SHIFT (8U)
+/*! DIRSETP8 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP8_SHIFT)) & GPIO_DIRSET_DIRSETP8_MASK)
+#define GPIO_DIRSET_DIRSETP9_MASK (0x200U)
+#define GPIO_DIRSET_DIRSETP9_SHIFT (9U)
+/*! DIRSETP9 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP9_SHIFT)) & GPIO_DIRSET_DIRSETP9_MASK)
+#define GPIO_DIRSET_DIRSETP10_MASK (0x400U)
+#define GPIO_DIRSET_DIRSETP10_SHIFT (10U)
+/*! DIRSETP10 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP10_SHIFT)) & GPIO_DIRSET_DIRSETP10_MASK)
+#define GPIO_DIRSET_DIRSETP11_MASK (0x800U)
+#define GPIO_DIRSET_DIRSETP11_SHIFT (11U)
+/*! DIRSETP11 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP11_SHIFT)) & GPIO_DIRSET_DIRSETP11_MASK)
+#define GPIO_DIRSET_DIRSETP12_MASK (0x1000U)
+#define GPIO_DIRSET_DIRSETP12_SHIFT (12U)
+/*! DIRSETP12 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP12_SHIFT)) & GPIO_DIRSET_DIRSETP12_MASK)
+#define GPIO_DIRSET_DIRSETP13_MASK (0x2000U)
+#define GPIO_DIRSET_DIRSETP13_SHIFT (13U)
+/*! DIRSETP13 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP13_SHIFT)) & GPIO_DIRSET_DIRSETP13_MASK)
+#define GPIO_DIRSET_DIRSETP14_MASK (0x4000U)
+#define GPIO_DIRSET_DIRSETP14_SHIFT (14U)
+/*! DIRSETP14 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP14_SHIFT)) & GPIO_DIRSET_DIRSETP14_MASK)
+#define GPIO_DIRSET_DIRSETP15_MASK (0x8000U)
+#define GPIO_DIRSET_DIRSETP15_SHIFT (15U)
+/*! DIRSETP15 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP15_SHIFT)) & GPIO_DIRSET_DIRSETP15_MASK)
+#define GPIO_DIRSET_DIRSETP16_MASK (0x10000U)
+#define GPIO_DIRSET_DIRSETP16_SHIFT (16U)
+/*! DIRSETP16 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP16_SHIFT)) & GPIO_DIRSET_DIRSETP16_MASK)
+#define GPIO_DIRSET_DIRSETP17_MASK (0x20000U)
+#define GPIO_DIRSET_DIRSETP17_SHIFT (17U)
+/*! DIRSETP17 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP17_SHIFT)) & GPIO_DIRSET_DIRSETP17_MASK)
+#define GPIO_DIRSET_DIRSETP18_MASK (0x40000U)
+#define GPIO_DIRSET_DIRSETP18_SHIFT (18U)
+/*! DIRSETP18 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP18_SHIFT)) & GPIO_DIRSET_DIRSETP18_MASK)
+#define GPIO_DIRSET_DIRSETP19_MASK (0x80000U)
+#define GPIO_DIRSET_DIRSETP19_SHIFT (19U)
+/*! DIRSETP19 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP19_SHIFT)) & GPIO_DIRSET_DIRSETP19_MASK)
+#define GPIO_DIRSET_DIRSETP20_MASK (0x100000U)
+#define GPIO_DIRSET_DIRSETP20_SHIFT (20U)
+/*! DIRSETP20 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP20_SHIFT)) & GPIO_DIRSET_DIRSETP20_MASK)
+#define GPIO_DIRSET_DIRSETP21_MASK (0x200000U)
+#define GPIO_DIRSET_DIRSETP21_SHIFT (21U)
+/*! DIRSETP21 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP21_SHIFT)) & GPIO_DIRSET_DIRSETP21_MASK)
+#define GPIO_DIRSET_DIRSETP22_MASK (0x400000U)
+#define GPIO_DIRSET_DIRSETP22_SHIFT (22U)
+/*! DIRSETP22 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP22_SHIFT)) & GPIO_DIRSET_DIRSETP22_MASK)
+#define GPIO_DIRSET_DIRSETP23_MASK (0x800000U)
+#define GPIO_DIRSET_DIRSETP23_SHIFT (23U)
+/*! DIRSETP23 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP23_SHIFT)) & GPIO_DIRSET_DIRSETP23_MASK)
+#define GPIO_DIRSET_DIRSETP24_MASK (0x1000000U)
+#define GPIO_DIRSET_DIRSETP24_SHIFT (24U)
+/*! DIRSETP24 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP24_SHIFT)) & GPIO_DIRSET_DIRSETP24_MASK)
+#define GPIO_DIRSET_DIRSETP25_MASK (0x2000000U)
+#define GPIO_DIRSET_DIRSETP25_SHIFT (25U)
+/*! DIRSETP25 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP25_SHIFT)) & GPIO_DIRSET_DIRSETP25_MASK)
+#define GPIO_DIRSET_DIRSETP26_MASK (0x4000000U)
+#define GPIO_DIRSET_DIRSETP26_SHIFT (26U)
+/*! DIRSETP26 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP26_SHIFT)) & GPIO_DIRSET_DIRSETP26_MASK)
+#define GPIO_DIRSET_DIRSETP27_MASK (0x8000000U)
+#define GPIO_DIRSET_DIRSETP27_SHIFT (27U)
+/*! DIRSETP27 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP27_SHIFT)) & GPIO_DIRSET_DIRSETP27_MASK)
+#define GPIO_DIRSET_DIRSETP28_MASK (0x10000000U)
+#define GPIO_DIRSET_DIRSETP28_SHIFT (28U)
+/*! DIRSETP28 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP28_SHIFT)) & GPIO_DIRSET_DIRSETP28_MASK)
+#define GPIO_DIRSET_DIRSETP29_MASK (0x20000000U)
+#define GPIO_DIRSET_DIRSETP29_SHIFT (29U)
+/*! DIRSETP29 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP29_SHIFT)) & GPIO_DIRSET_DIRSETP29_MASK)
+#define GPIO_DIRSET_DIRSETP30_MASK (0x40000000U)
+#define GPIO_DIRSET_DIRSETP30_SHIFT (30U)
+/*! DIRSETP30 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP30_SHIFT)) & GPIO_DIRSET_DIRSETP30_MASK)
+#define GPIO_DIRSET_DIRSETP31_MASK (0x80000000U)
+#define GPIO_DIRSET_DIRSETP31_SHIFT (31U)
+/*! DIRSETP31 - Direction set bits for Port pins
+ * 0b0..No operation
+ * 0b1..Sets direction bit
+ */
+#define GPIO_DIRSET_DIRSETP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP31_SHIFT)) & GPIO_DIRSET_DIRSETP31_MASK)
+/*! @} */
+
+/* The count of GPIO_DIRSET */
+#define GPIO_DIRSET_COUNT (8U)
+
+/*! @name DIRCLR - Port direction clear */
+/*! @{ */
+#define GPIO_DIRCLR_DIRCLRP0_MASK (0x1U)
+#define GPIO_DIRCLR_DIRCLRP0_SHIFT (0U)
+/*! DIRCLRP0 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP0_SHIFT)) & GPIO_DIRCLR_DIRCLRP0_MASK)
+#define GPIO_DIRCLR_DIRCLRP1_MASK (0x2U)
+#define GPIO_DIRCLR_DIRCLRP1_SHIFT (1U)
+/*! DIRCLRP1 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP1_SHIFT)) & GPIO_DIRCLR_DIRCLRP1_MASK)
+#define GPIO_DIRCLR_DIRCLRP2_MASK (0x4U)
+#define GPIO_DIRCLR_DIRCLRP2_SHIFT (2U)
+/*! DIRCLRP2 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP2_SHIFT)) & GPIO_DIRCLR_DIRCLRP2_MASK)
+#define GPIO_DIRCLR_DIRCLRP3_MASK (0x8U)
+#define GPIO_DIRCLR_DIRCLRP3_SHIFT (3U)
+/*! DIRCLRP3 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP3_SHIFT)) & GPIO_DIRCLR_DIRCLRP3_MASK)
+#define GPIO_DIRCLR_DIRCLRP4_MASK (0x10U)
+#define GPIO_DIRCLR_DIRCLRP4_SHIFT (4U)
+/*! DIRCLRP4 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP4_SHIFT)) & GPIO_DIRCLR_DIRCLRP4_MASK)
+#define GPIO_DIRCLR_DIRCLRP5_MASK (0x20U)
+#define GPIO_DIRCLR_DIRCLRP5_SHIFT (5U)
+/*! DIRCLRP5 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP5_SHIFT)) & GPIO_DIRCLR_DIRCLRP5_MASK)
+#define GPIO_DIRCLR_DIRCLRP6_MASK (0x40U)
+#define GPIO_DIRCLR_DIRCLRP6_SHIFT (6U)
+/*! DIRCLRP6 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP6_SHIFT)) & GPIO_DIRCLR_DIRCLRP6_MASK)
+#define GPIO_DIRCLR_DIRCLRP7_MASK (0x80U)
+#define GPIO_DIRCLR_DIRCLRP7_SHIFT (7U)
+/*! DIRCLRP7 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP7_SHIFT)) & GPIO_DIRCLR_DIRCLRP7_MASK)
+#define GPIO_DIRCLR_DIRCLRP8_MASK (0x100U)
+#define GPIO_DIRCLR_DIRCLRP8_SHIFT (8U)
+/*! DIRCLRP8 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP8_SHIFT)) & GPIO_DIRCLR_DIRCLRP8_MASK)
+#define GPIO_DIRCLR_DIRCLRP9_MASK (0x200U)
+#define GPIO_DIRCLR_DIRCLRP9_SHIFT (9U)
+/*! DIRCLRP9 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP9_SHIFT)) & GPIO_DIRCLR_DIRCLRP9_MASK)
+#define GPIO_DIRCLR_DIRCLRP10_MASK (0x400U)
+#define GPIO_DIRCLR_DIRCLRP10_SHIFT (10U)
+/*! DIRCLRP10 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP10_SHIFT)) & GPIO_DIRCLR_DIRCLRP10_MASK)
+#define GPIO_DIRCLR_DIRCLRP11_MASK (0x800U)
+#define GPIO_DIRCLR_DIRCLRP11_SHIFT (11U)
+/*! DIRCLRP11 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP11_SHIFT)) & GPIO_DIRCLR_DIRCLRP11_MASK)
+#define GPIO_DIRCLR_DIRCLRP12_MASK (0x1000U)
+#define GPIO_DIRCLR_DIRCLRP12_SHIFT (12U)
+/*! DIRCLRP12 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP12_SHIFT)) & GPIO_DIRCLR_DIRCLRP12_MASK)
+#define GPIO_DIRCLR_DIRCLRP13_MASK (0x2000U)
+#define GPIO_DIRCLR_DIRCLRP13_SHIFT (13U)
+/*! DIRCLRP13 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP13_SHIFT)) & GPIO_DIRCLR_DIRCLRP13_MASK)
+#define GPIO_DIRCLR_DIRCLRP14_MASK (0x4000U)
+#define GPIO_DIRCLR_DIRCLRP14_SHIFT (14U)
+/*! DIRCLRP14 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP14_SHIFT)) & GPIO_DIRCLR_DIRCLRP14_MASK)
+#define GPIO_DIRCLR_DIRCLRP15_MASK (0x8000U)
+#define GPIO_DIRCLR_DIRCLRP15_SHIFT (15U)
+/*! DIRCLRP15 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP15_SHIFT)) & GPIO_DIRCLR_DIRCLRP15_MASK)
+#define GPIO_DIRCLR_DIRCLRP16_MASK (0x10000U)
+#define GPIO_DIRCLR_DIRCLRP16_SHIFT (16U)
+/*! DIRCLRP16 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP16_SHIFT)) & GPIO_DIRCLR_DIRCLRP16_MASK)
+#define GPIO_DIRCLR_DIRCLRP17_MASK (0x20000U)
+#define GPIO_DIRCLR_DIRCLRP17_SHIFT (17U)
+/*! DIRCLRP17 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP17_SHIFT)) & GPIO_DIRCLR_DIRCLRP17_MASK)
+#define GPIO_DIRCLR_DIRCLRP18_MASK (0x40000U)
+#define GPIO_DIRCLR_DIRCLRP18_SHIFT (18U)
+/*! DIRCLRP18 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP18_SHIFT)) & GPIO_DIRCLR_DIRCLRP18_MASK)
+#define GPIO_DIRCLR_DIRCLRP19_MASK (0x80000U)
+#define GPIO_DIRCLR_DIRCLRP19_SHIFT (19U)
+/*! DIRCLRP19 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP19_SHIFT)) & GPIO_DIRCLR_DIRCLRP19_MASK)
+#define GPIO_DIRCLR_DIRCLRP20_MASK (0x100000U)
+#define GPIO_DIRCLR_DIRCLRP20_SHIFT (20U)
+/*! DIRCLRP20 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP20_SHIFT)) & GPIO_DIRCLR_DIRCLRP20_MASK)
+#define GPIO_DIRCLR_DIRCLRP21_MASK (0x200000U)
+#define GPIO_DIRCLR_DIRCLRP21_SHIFT (21U)
+/*! DIRCLRP21 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP21_SHIFT)) & GPIO_DIRCLR_DIRCLRP21_MASK)
+#define GPIO_DIRCLR_DIRCLRP22_MASK (0x400000U)
+#define GPIO_DIRCLR_DIRCLRP22_SHIFT (22U)
+/*! DIRCLRP22 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP22_SHIFT)) & GPIO_DIRCLR_DIRCLRP22_MASK)
+#define GPIO_DIRCLR_DIRCLRP23_MASK (0x800000U)
+#define GPIO_DIRCLR_DIRCLRP23_SHIFT (23U)
+/*! DIRCLRP23 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP23_SHIFT)) & GPIO_DIRCLR_DIRCLRP23_MASK)
+#define GPIO_DIRCLR_DIRCLRP24_MASK (0x1000000U)
+#define GPIO_DIRCLR_DIRCLRP24_SHIFT (24U)
+/*! DIRCLRP24 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP24_SHIFT)) & GPIO_DIRCLR_DIRCLRP24_MASK)
+#define GPIO_DIRCLR_DIRCLRP25_MASK (0x2000000U)
+#define GPIO_DIRCLR_DIRCLRP25_SHIFT (25U)
+/*! DIRCLRP25 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP25_SHIFT)) & GPIO_DIRCLR_DIRCLRP25_MASK)
+#define GPIO_DIRCLR_DIRCLRP26_MASK (0x4000000U)
+#define GPIO_DIRCLR_DIRCLRP26_SHIFT (26U)
+/*! DIRCLRP26 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP26_SHIFT)) & GPIO_DIRCLR_DIRCLRP26_MASK)
+#define GPIO_DIRCLR_DIRCLRP27_MASK (0x8000000U)
+#define GPIO_DIRCLR_DIRCLRP27_SHIFT (27U)
+/*! DIRCLRP27 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP27_SHIFT)) & GPIO_DIRCLR_DIRCLRP27_MASK)
+#define GPIO_DIRCLR_DIRCLRP28_MASK (0x10000000U)
+#define GPIO_DIRCLR_DIRCLRP28_SHIFT (28U)
+/*! DIRCLRP28 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP28_SHIFT)) & GPIO_DIRCLR_DIRCLRP28_MASK)
+#define GPIO_DIRCLR_DIRCLRP29_MASK (0x20000000U)
+#define GPIO_DIRCLR_DIRCLRP29_SHIFT (29U)
+/*! DIRCLRP29 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP29_SHIFT)) & GPIO_DIRCLR_DIRCLRP29_MASK)
+#define GPIO_DIRCLR_DIRCLRP30_MASK (0x40000000U)
+#define GPIO_DIRCLR_DIRCLRP30_SHIFT (30U)
+/*! DIRCLRP30 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP30_SHIFT)) & GPIO_DIRCLR_DIRCLRP30_MASK)
+#define GPIO_DIRCLR_DIRCLRP31_MASK (0x80000000U)
+#define GPIO_DIRCLR_DIRCLRP31_SHIFT (31U)
+/*! DIRCLRP31 - Clear direction bits.
+ * 0b0..No operation
+ * 0b1..Clears direction bits
+ */
+#define GPIO_DIRCLR_DIRCLRP31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP31_SHIFT)) & GPIO_DIRCLR_DIRCLRP31_MASK)
+/*! @} */
+
+/* The count of GPIO_DIRCLR */
+#define GPIO_DIRCLR_COUNT (8U)
+
+/*! @name DIRNOT - Port direction toggle */
+/*! @{ */
+#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU)
+#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)
+/*! DIRNOTP - Toggle direction bits.
+ * 0b00000000000000000000000000000..No operation
+ * 0b00000000000000000000000000001..Toggles direction bit
+ */
+#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
+/*! @} */
+
+/* The count of GPIO_DIRNOT */
+#define GPIO_DIRNOT_COUNT (8U)
+
+/*! @name INTENA - Interrupt A enable control */
+/*! @{ */
+#define GPIO_INTENA_INT_EN0_MASK (0x1U)
+#define GPIO_INTENA_INT_EN0_SHIFT (0U)
+/*! INT_EN0 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN0_SHIFT)) & GPIO_INTENA_INT_EN0_MASK)
+#define GPIO_INTENA_INT_EN1_MASK (0x2U)
+#define GPIO_INTENA_INT_EN1_SHIFT (1U)
+/*! INT_EN1 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN1_SHIFT)) & GPIO_INTENA_INT_EN1_MASK)
+#define GPIO_INTENA_INT_EN2_MASK (0x4U)
+#define GPIO_INTENA_INT_EN2_SHIFT (2U)
+/*! INT_EN2 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN2_SHIFT)) & GPIO_INTENA_INT_EN2_MASK)
+#define GPIO_INTENA_INT_EN3_MASK (0x8U)
+#define GPIO_INTENA_INT_EN3_SHIFT (3U)
+/*! INT_EN3 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN3_SHIFT)) & GPIO_INTENA_INT_EN3_MASK)
+#define GPIO_INTENA_INT_EN4_MASK (0x10U)
+#define GPIO_INTENA_INT_EN4_SHIFT (4U)
+/*! INT_EN4 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN4_SHIFT)) & GPIO_INTENA_INT_EN4_MASK)
+#define GPIO_INTENA_INT_EN5_MASK (0x20U)
+#define GPIO_INTENA_INT_EN5_SHIFT (5U)
+/*! INT_EN5 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN5_SHIFT)) & GPIO_INTENA_INT_EN5_MASK)
+#define GPIO_INTENA_INT_EN6_MASK (0x40U)
+#define GPIO_INTENA_INT_EN6_SHIFT (6U)
+/*! INT_EN6 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN6_SHIFT)) & GPIO_INTENA_INT_EN6_MASK)
+#define GPIO_INTENA_INT_EN7_MASK (0x80U)
+#define GPIO_INTENA_INT_EN7_SHIFT (7U)
+/*! INT_EN7 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN7_SHIFT)) & GPIO_INTENA_INT_EN7_MASK)
+#define GPIO_INTENA_INT_EN8_MASK (0x100U)
+#define GPIO_INTENA_INT_EN8_SHIFT (8U)
+/*! INT_EN8 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN8_SHIFT)) & GPIO_INTENA_INT_EN8_MASK)
+#define GPIO_INTENA_INT_EN9_MASK (0x200U)
+#define GPIO_INTENA_INT_EN9_SHIFT (9U)
+/*! INT_EN9 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN9_SHIFT)) & GPIO_INTENA_INT_EN9_MASK)
+#define GPIO_INTENA_INT_EN10_MASK (0x400U)
+#define GPIO_INTENA_INT_EN10_SHIFT (10U)
+/*! INT_EN10 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN10_SHIFT)) & GPIO_INTENA_INT_EN10_MASK)
+#define GPIO_INTENA_INT_EN11_MASK (0x800U)
+#define GPIO_INTENA_INT_EN11_SHIFT (11U)
+/*! INT_EN11 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN11_SHIFT)) & GPIO_INTENA_INT_EN11_MASK)
+#define GPIO_INTENA_INT_EN12_MASK (0x1000U)
+#define GPIO_INTENA_INT_EN12_SHIFT (12U)
+/*! INT_EN12 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN12_SHIFT)) & GPIO_INTENA_INT_EN12_MASK)
+#define GPIO_INTENA_INT_EN13_MASK (0x2000U)
+#define GPIO_INTENA_INT_EN13_SHIFT (13U)
+/*! INT_EN13 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN13_SHIFT)) & GPIO_INTENA_INT_EN13_MASK)
+#define GPIO_INTENA_INT_EN14_MASK (0x4000U)
+#define GPIO_INTENA_INT_EN14_SHIFT (14U)
+/*! INT_EN14 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN14_SHIFT)) & GPIO_INTENA_INT_EN14_MASK)
+#define GPIO_INTENA_INT_EN15_MASK (0x8000U)
+#define GPIO_INTENA_INT_EN15_SHIFT (15U)
+/*! INT_EN15 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN15_SHIFT)) & GPIO_INTENA_INT_EN15_MASK)
+#define GPIO_INTENA_INT_EN16_MASK (0x10000U)
+#define GPIO_INTENA_INT_EN16_SHIFT (16U)
+/*! INT_EN16 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN16_SHIFT)) & GPIO_INTENA_INT_EN16_MASK)
+#define GPIO_INTENA_INT_EN17_MASK (0x20000U)
+#define GPIO_INTENA_INT_EN17_SHIFT (17U)
+/*! INT_EN17 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN17_SHIFT)) & GPIO_INTENA_INT_EN17_MASK)
+#define GPIO_INTENA_INT_EN18_MASK (0x40000U)
+#define GPIO_INTENA_INT_EN18_SHIFT (18U)
+/*! INT_EN18 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN18_SHIFT)) & GPIO_INTENA_INT_EN18_MASK)
+#define GPIO_INTENA_INT_EN19_MASK (0x80000U)
+#define GPIO_INTENA_INT_EN19_SHIFT (19U)
+/*! INT_EN19 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN19_SHIFT)) & GPIO_INTENA_INT_EN19_MASK)
+#define GPIO_INTENA_INT_EN20_MASK (0x100000U)
+#define GPIO_INTENA_INT_EN20_SHIFT (20U)
+/*! INT_EN20 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN20_SHIFT)) & GPIO_INTENA_INT_EN20_MASK)
+#define GPIO_INTENA_INT_EN21_MASK (0x200000U)
+#define GPIO_INTENA_INT_EN21_SHIFT (21U)
+/*! INT_EN21 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN21_SHIFT)) & GPIO_INTENA_INT_EN21_MASK)
+#define GPIO_INTENA_INT_EN22_MASK (0x400000U)
+#define GPIO_INTENA_INT_EN22_SHIFT (22U)
+/*! INT_EN22 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN22_SHIFT)) & GPIO_INTENA_INT_EN22_MASK)
+#define GPIO_INTENA_INT_EN23_MASK (0x800000U)
+#define GPIO_INTENA_INT_EN23_SHIFT (23U)
+/*! INT_EN23 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN23_SHIFT)) & GPIO_INTENA_INT_EN23_MASK)
+#define GPIO_INTENA_INT_EN24_MASK (0x1000000U)
+#define GPIO_INTENA_INT_EN24_SHIFT (24U)
+/*! INT_EN24 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN24_SHIFT)) & GPIO_INTENA_INT_EN24_MASK)
+#define GPIO_INTENA_INT_EN25_MASK (0x2000000U)
+#define GPIO_INTENA_INT_EN25_SHIFT (25U)
+/*! INT_EN25 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN25_SHIFT)) & GPIO_INTENA_INT_EN25_MASK)
+#define GPIO_INTENA_INT_EN26_MASK (0x4000000U)
+#define GPIO_INTENA_INT_EN26_SHIFT (26U)
+/*! INT_EN26 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN26_SHIFT)) & GPIO_INTENA_INT_EN26_MASK)
+#define GPIO_INTENA_INT_EN27_MASK (0x8000000U)
+#define GPIO_INTENA_INT_EN27_SHIFT (27U)
+/*! INT_EN27 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN27_SHIFT)) & GPIO_INTENA_INT_EN27_MASK)
+#define GPIO_INTENA_INT_EN28_MASK (0x10000000U)
+#define GPIO_INTENA_INT_EN28_SHIFT (28U)
+/*! INT_EN28 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN28_SHIFT)) & GPIO_INTENA_INT_EN28_MASK)
+#define GPIO_INTENA_INT_EN29_MASK (0x20000000U)
+#define GPIO_INTENA_INT_EN29_SHIFT (29U)
+/*! INT_EN29 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN29_SHIFT)) & GPIO_INTENA_INT_EN29_MASK)
+#define GPIO_INTENA_INT_EN30_MASK (0x40000000U)
+#define GPIO_INTENA_INT_EN30_SHIFT (30U)
+/*! INT_EN30 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN30_SHIFT)) & GPIO_INTENA_INT_EN30_MASK)
+#define GPIO_INTENA_INT_EN31_MASK (0x80000000U)
+#define GPIO_INTENA_INT_EN31_SHIFT (31U)
+/*! INT_EN31 - Interrupt A enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt A
+ * 0b1..Pin contributes to GPIO interrupt A
+ */
+#define GPIO_INTENA_INT_EN31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN31_SHIFT)) & GPIO_INTENA_INT_EN31_MASK)
+/*! @} */
+
+/* The count of GPIO_INTENA */
+#define GPIO_INTENA_COUNT (8U)
+
+/*! @name INTENB - Interrupt B enable control */
+/*! @{ */
+#define GPIO_INTENB_INT_EN0_MASK (0x1U)
+#define GPIO_INTENB_INT_EN0_SHIFT (0U)
+/*! INT_EN0 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN0_SHIFT)) & GPIO_INTENB_INT_EN0_MASK)
+#define GPIO_INTENB_INT_EN1_MASK (0x2U)
+#define GPIO_INTENB_INT_EN1_SHIFT (1U)
+/*! INT_EN1 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN1_SHIFT)) & GPIO_INTENB_INT_EN1_MASK)
+#define GPIO_INTENB_INT_EN2_MASK (0x4U)
+#define GPIO_INTENB_INT_EN2_SHIFT (2U)
+/*! INT_EN2 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN2_SHIFT)) & GPIO_INTENB_INT_EN2_MASK)
+#define GPIO_INTENB_INT_EN3_MASK (0x8U)
+#define GPIO_INTENB_INT_EN3_SHIFT (3U)
+/*! INT_EN3 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN3_SHIFT)) & GPIO_INTENB_INT_EN3_MASK)
+#define GPIO_INTENB_INT_EN4_MASK (0x10U)
+#define GPIO_INTENB_INT_EN4_SHIFT (4U)
+/*! INT_EN4 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN4_SHIFT)) & GPIO_INTENB_INT_EN4_MASK)
+#define GPIO_INTENB_INT_EN5_MASK (0x20U)
+#define GPIO_INTENB_INT_EN5_SHIFT (5U)
+/*! INT_EN5 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN5_SHIFT)) & GPIO_INTENB_INT_EN5_MASK)
+#define GPIO_INTENB_INT_EN6_MASK (0x40U)
+#define GPIO_INTENB_INT_EN6_SHIFT (6U)
+/*! INT_EN6 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN6_SHIFT)) & GPIO_INTENB_INT_EN6_MASK)
+#define GPIO_INTENB_INT_EN7_MASK (0x80U)
+#define GPIO_INTENB_INT_EN7_SHIFT (7U)
+/*! INT_EN7 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN7_SHIFT)) & GPIO_INTENB_INT_EN7_MASK)
+#define GPIO_INTENB_INT_EN8_MASK (0x100U)
+#define GPIO_INTENB_INT_EN8_SHIFT (8U)
+/*! INT_EN8 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN8_SHIFT)) & GPIO_INTENB_INT_EN8_MASK)
+#define GPIO_INTENB_INT_EN9_MASK (0x200U)
+#define GPIO_INTENB_INT_EN9_SHIFT (9U)
+/*! INT_EN9 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN9_SHIFT)) & GPIO_INTENB_INT_EN9_MASK)
+#define GPIO_INTENB_INT_EN10_MASK (0x400U)
+#define GPIO_INTENB_INT_EN10_SHIFT (10U)
+/*! INT_EN10 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN10_SHIFT)) & GPIO_INTENB_INT_EN10_MASK)
+#define GPIO_INTENB_INT_EN11_MASK (0x800U)
+#define GPIO_INTENB_INT_EN11_SHIFT (11U)
+/*! INT_EN11 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN11_SHIFT)) & GPIO_INTENB_INT_EN11_MASK)
+#define GPIO_INTENB_INT_EN12_MASK (0x1000U)
+#define GPIO_INTENB_INT_EN12_SHIFT (12U)
+/*! INT_EN12 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN12_SHIFT)) & GPIO_INTENB_INT_EN12_MASK)
+#define GPIO_INTENB_INT_EN13_MASK (0x2000U)
+#define GPIO_INTENB_INT_EN13_SHIFT (13U)
+/*! INT_EN13 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN13_SHIFT)) & GPIO_INTENB_INT_EN13_MASK)
+#define GPIO_INTENB_INT_EN14_MASK (0x4000U)
+#define GPIO_INTENB_INT_EN14_SHIFT (14U)
+/*! INT_EN14 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN14_SHIFT)) & GPIO_INTENB_INT_EN14_MASK)
+#define GPIO_INTENB_INT_EN15_MASK (0x8000U)
+#define GPIO_INTENB_INT_EN15_SHIFT (15U)
+/*! INT_EN15 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN15_SHIFT)) & GPIO_INTENB_INT_EN15_MASK)
+#define GPIO_INTENB_INT_EN16_MASK (0x10000U)
+#define GPIO_INTENB_INT_EN16_SHIFT (16U)
+/*! INT_EN16 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN16_SHIFT)) & GPIO_INTENB_INT_EN16_MASK)
+#define GPIO_INTENB_INT_EN17_MASK (0x20000U)
+#define GPIO_INTENB_INT_EN17_SHIFT (17U)
+/*! INT_EN17 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN17_SHIFT)) & GPIO_INTENB_INT_EN17_MASK)
+#define GPIO_INTENB_INT_EN18_MASK (0x40000U)
+#define GPIO_INTENB_INT_EN18_SHIFT (18U)
+/*! INT_EN18 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN18_SHIFT)) & GPIO_INTENB_INT_EN18_MASK)
+#define GPIO_INTENB_INT_EN19_MASK (0x80000U)
+#define GPIO_INTENB_INT_EN19_SHIFT (19U)
+/*! INT_EN19 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN19_SHIFT)) & GPIO_INTENB_INT_EN19_MASK)
+#define GPIO_INTENB_INT_EN20_MASK (0x100000U)
+#define GPIO_INTENB_INT_EN20_SHIFT (20U)
+/*! INT_EN20 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN20_SHIFT)) & GPIO_INTENB_INT_EN20_MASK)
+#define GPIO_INTENB_INT_EN21_MASK (0x200000U)
+#define GPIO_INTENB_INT_EN21_SHIFT (21U)
+/*! INT_EN21 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN21_SHIFT)) & GPIO_INTENB_INT_EN21_MASK)
+#define GPIO_INTENB_INT_EN22_MASK (0x400000U)
+#define GPIO_INTENB_INT_EN22_SHIFT (22U)
+/*! INT_EN22 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN22_SHIFT)) & GPIO_INTENB_INT_EN22_MASK)
+#define GPIO_INTENB_INT_EN23_MASK (0x800000U)
+#define GPIO_INTENB_INT_EN23_SHIFT (23U)
+/*! INT_EN23 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN23_SHIFT)) & GPIO_INTENB_INT_EN23_MASK)
+#define GPIO_INTENB_INT_EN24_MASK (0x1000000U)
+#define GPIO_INTENB_INT_EN24_SHIFT (24U)
+/*! INT_EN24 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN24_SHIFT)) & GPIO_INTENB_INT_EN24_MASK)
+#define GPIO_INTENB_INT_EN25_MASK (0x2000000U)
+#define GPIO_INTENB_INT_EN25_SHIFT (25U)
+/*! INT_EN25 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN25_SHIFT)) & GPIO_INTENB_INT_EN25_MASK)
+#define GPIO_INTENB_INT_EN26_MASK (0x4000000U)
+#define GPIO_INTENB_INT_EN26_SHIFT (26U)
+/*! INT_EN26 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN26_SHIFT)) & GPIO_INTENB_INT_EN26_MASK)
+#define GPIO_INTENB_INT_EN27_MASK (0x8000000U)
+#define GPIO_INTENB_INT_EN27_SHIFT (27U)
+/*! INT_EN27 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN27_SHIFT)) & GPIO_INTENB_INT_EN27_MASK)
+#define GPIO_INTENB_INT_EN28_MASK (0x10000000U)
+#define GPIO_INTENB_INT_EN28_SHIFT (28U)
+/*! INT_EN28 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN28_SHIFT)) & GPIO_INTENB_INT_EN28_MASK)
+#define GPIO_INTENB_INT_EN29_MASK (0x20000000U)
+#define GPIO_INTENB_INT_EN29_SHIFT (29U)
+/*! INT_EN29 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN29_SHIFT)) & GPIO_INTENB_INT_EN29_MASK)
+#define GPIO_INTENB_INT_EN30_MASK (0x40000000U)
+#define GPIO_INTENB_INT_EN30_SHIFT (30U)
+/*! INT_EN30 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN30_SHIFT)) & GPIO_INTENB_INT_EN30_MASK)
+#define GPIO_INTENB_INT_EN31_MASK (0x80000000U)
+#define GPIO_INTENB_INT_EN31_SHIFT (31U)
+/*! INT_EN31 - Interrupt B enable bits.
+ * 0b0..Pin does not contribute to GPIO interrupt B
+ * 0b1..Pin contributes to GPIO interrupt B
+ */
+#define GPIO_INTENB_INT_EN31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN31_SHIFT)) & GPIO_INTENB_INT_EN31_MASK)
+/*! @} */
+
+/* The count of GPIO_INTENB */
+#define GPIO_INTENB_COUNT (8U)
+
+/*! @name INTPOL - Interupt polarity control */
+/*! @{ */
+#define GPIO_INTPOL_POL_CTL0_MASK (0x1U)
+#define GPIO_INTPOL_POL_CTL0_SHIFT (0U)
+/*! POL_CTL0 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL0_SHIFT)) & GPIO_INTPOL_POL_CTL0_MASK)
+#define GPIO_INTPOL_POL_CTL1_MASK (0x2U)
+#define GPIO_INTPOL_POL_CTL1_SHIFT (1U)
+/*! POL_CTL1 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL1_SHIFT)) & GPIO_INTPOL_POL_CTL1_MASK)
+#define GPIO_INTPOL_POL_CTL2_MASK (0x4U)
+#define GPIO_INTPOL_POL_CTL2_SHIFT (2U)
+/*! POL_CTL2 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL2_SHIFT)) & GPIO_INTPOL_POL_CTL2_MASK)
+#define GPIO_INTPOL_POL_CTL3_MASK (0x8U)
+#define GPIO_INTPOL_POL_CTL3_SHIFT (3U)
+/*! POL_CTL3 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL3_SHIFT)) & GPIO_INTPOL_POL_CTL3_MASK)
+#define GPIO_INTPOL_POL_CTL4_MASK (0x10U)
+#define GPIO_INTPOL_POL_CTL4_SHIFT (4U)
+/*! POL_CTL4 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL4_SHIFT)) & GPIO_INTPOL_POL_CTL4_MASK)
+#define GPIO_INTPOL_POL_CTL5_MASK (0x20U)
+#define GPIO_INTPOL_POL_CTL5_SHIFT (5U)
+/*! POL_CTL5 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL5_SHIFT)) & GPIO_INTPOL_POL_CTL5_MASK)
+#define GPIO_INTPOL_POL_CTL6_MASK (0x40U)
+#define GPIO_INTPOL_POL_CTL6_SHIFT (6U)
+/*! POL_CTL6 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL6_SHIFT)) & GPIO_INTPOL_POL_CTL6_MASK)
+#define GPIO_INTPOL_POL_CTL7_MASK (0x80U)
+#define GPIO_INTPOL_POL_CTL7_SHIFT (7U)
+/*! POL_CTL7 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL7_SHIFT)) & GPIO_INTPOL_POL_CTL7_MASK)
+#define GPIO_INTPOL_POL_CTL8_MASK (0x100U)
+#define GPIO_INTPOL_POL_CTL8_SHIFT (8U)
+/*! POL_CTL8 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL8_SHIFT)) & GPIO_INTPOL_POL_CTL8_MASK)
+#define GPIO_INTPOL_POL_CTL9_MASK (0x200U)
+#define GPIO_INTPOL_POL_CTL9_SHIFT (9U)
+/*! POL_CTL9 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL9_SHIFT)) & GPIO_INTPOL_POL_CTL9_MASK)
+#define GPIO_INTPOL_POL_CTL10_MASK (0x400U)
+#define GPIO_INTPOL_POL_CTL10_SHIFT (10U)
+/*! POL_CTL10 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL10_SHIFT)) & GPIO_INTPOL_POL_CTL10_MASK)
+#define GPIO_INTPOL_POL_CTL11_MASK (0x800U)
+#define GPIO_INTPOL_POL_CTL11_SHIFT (11U)
+/*! POL_CTL11 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL11_SHIFT)) & GPIO_INTPOL_POL_CTL11_MASK)
+#define GPIO_INTPOL_POL_CTL12_MASK (0x1000U)
+#define GPIO_INTPOL_POL_CTL12_SHIFT (12U)
+/*! POL_CTL12 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL12_SHIFT)) & GPIO_INTPOL_POL_CTL12_MASK)
+#define GPIO_INTPOL_POL_CTL13_MASK (0x2000U)
+#define GPIO_INTPOL_POL_CTL13_SHIFT (13U)
+/*! POL_CTL13 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL13_SHIFT)) & GPIO_INTPOL_POL_CTL13_MASK)
+#define GPIO_INTPOL_POL_CTL14_MASK (0x4000U)
+#define GPIO_INTPOL_POL_CTL14_SHIFT (14U)
+/*! POL_CTL14 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL14_SHIFT)) & GPIO_INTPOL_POL_CTL14_MASK)
+#define GPIO_INTPOL_POL_CTL15_MASK (0x8000U)
+#define GPIO_INTPOL_POL_CTL15_SHIFT (15U)
+/*! POL_CTL15 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL15_SHIFT)) & GPIO_INTPOL_POL_CTL15_MASK)
+#define GPIO_INTPOL_POL_CTL16_MASK (0x10000U)
+#define GPIO_INTPOL_POL_CTL16_SHIFT (16U)
+/*! POL_CTL16 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL16_SHIFT)) & GPIO_INTPOL_POL_CTL16_MASK)
+#define GPIO_INTPOL_POL_CTL17_MASK (0x20000U)
+#define GPIO_INTPOL_POL_CTL17_SHIFT (17U)
+/*! POL_CTL17 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL17_SHIFT)) & GPIO_INTPOL_POL_CTL17_MASK)
+#define GPIO_INTPOL_POL_CTL18_MASK (0x40000U)
+#define GPIO_INTPOL_POL_CTL18_SHIFT (18U)
+/*! POL_CTL18 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL18_SHIFT)) & GPIO_INTPOL_POL_CTL18_MASK)
+#define GPIO_INTPOL_POL_CTL19_MASK (0x80000U)
+#define GPIO_INTPOL_POL_CTL19_SHIFT (19U)
+/*! POL_CTL19 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL19_SHIFT)) & GPIO_INTPOL_POL_CTL19_MASK)
+#define GPIO_INTPOL_POL_CTL20_MASK (0x100000U)
+#define GPIO_INTPOL_POL_CTL20_SHIFT (20U)
+/*! POL_CTL20 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL20_SHIFT)) & GPIO_INTPOL_POL_CTL20_MASK)
+#define GPIO_INTPOL_POL_CTL21_MASK (0x200000U)
+#define GPIO_INTPOL_POL_CTL21_SHIFT (21U)
+/*! POL_CTL21 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL21_SHIFT)) & GPIO_INTPOL_POL_CTL21_MASK)
+#define GPIO_INTPOL_POL_CTL22_MASK (0x400000U)
+#define GPIO_INTPOL_POL_CTL22_SHIFT (22U)
+/*! POL_CTL22 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL22_SHIFT)) & GPIO_INTPOL_POL_CTL22_MASK)
+#define GPIO_INTPOL_POL_CTL23_MASK (0x800000U)
+#define GPIO_INTPOL_POL_CTL23_SHIFT (23U)
+/*! POL_CTL23 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL23_SHIFT)) & GPIO_INTPOL_POL_CTL23_MASK)
+#define GPIO_INTPOL_POL_CTL24_MASK (0x1000000U)
+#define GPIO_INTPOL_POL_CTL24_SHIFT (24U)
+/*! POL_CTL24 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL24_SHIFT)) & GPIO_INTPOL_POL_CTL24_MASK)
+#define GPIO_INTPOL_POL_CTL25_MASK (0x2000000U)
+#define GPIO_INTPOL_POL_CTL25_SHIFT (25U)
+/*! POL_CTL25 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL25_SHIFT)) & GPIO_INTPOL_POL_CTL25_MASK)
+#define GPIO_INTPOL_POL_CTL26_MASK (0x4000000U)
+#define GPIO_INTPOL_POL_CTL26_SHIFT (26U)
+/*! POL_CTL26 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL26_SHIFT)) & GPIO_INTPOL_POL_CTL26_MASK)
+#define GPIO_INTPOL_POL_CTL27_MASK (0x8000000U)
+#define GPIO_INTPOL_POL_CTL27_SHIFT (27U)
+/*! POL_CTL27 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL27_SHIFT)) & GPIO_INTPOL_POL_CTL27_MASK)
+#define GPIO_INTPOL_POL_CTL28_MASK (0x10000000U)
+#define GPIO_INTPOL_POL_CTL28_SHIFT (28U)
+/*! POL_CTL28 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL28_SHIFT)) & GPIO_INTPOL_POL_CTL28_MASK)
+#define GPIO_INTPOL_POL_CTL29_MASK (0x20000000U)
+#define GPIO_INTPOL_POL_CTL29_SHIFT (29U)
+/*! POL_CTL29 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL29_SHIFT)) & GPIO_INTPOL_POL_CTL29_MASK)
+#define GPIO_INTPOL_POL_CTL30_MASK (0x40000000U)
+#define GPIO_INTPOL_POL_CTL30_SHIFT (30U)
+/*! POL_CTL30 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL30_SHIFT)) & GPIO_INTPOL_POL_CTL30_MASK)
+#define GPIO_INTPOL_POL_CTL31_MASK (0x80000000U)
+#define GPIO_INTPOL_POL_CTL31_SHIFT (31U)
+/*! POL_CTL31 - Polarity control for each pin
+ * 0b0..High level or rising edge triggered
+ * 0b1..Low level or falling edge triggered
+ */
+#define GPIO_INTPOL_POL_CTL31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL31_SHIFT)) & GPIO_INTPOL_POL_CTL31_MASK)
+/*! @} */
+
+/* The count of GPIO_INTPOL */
+#define GPIO_INTPOL_COUNT (8U)
+
+/*! @name INTEDG - Interrupt edge select */
+/*! @{ */
+#define GPIO_INTEDG_EDGE0_MASK (0x1U)
+#define GPIO_INTEDG_EDGE0_SHIFT (0U)
+/*! EDGE0 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE0_SHIFT)) & GPIO_INTEDG_EDGE0_MASK)
+#define GPIO_INTEDG_EDGE1_MASK (0x2U)
+#define GPIO_INTEDG_EDGE1_SHIFT (1U)
+/*! EDGE1 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE1_SHIFT)) & GPIO_INTEDG_EDGE1_MASK)
+#define GPIO_INTEDG_EDGE2_MASK (0x4U)
+#define GPIO_INTEDG_EDGE2_SHIFT (2U)
+/*! EDGE2 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE2_SHIFT)) & GPIO_INTEDG_EDGE2_MASK)
+#define GPIO_INTEDG_EDGE3_MASK (0x8U)
+#define GPIO_INTEDG_EDGE3_SHIFT (3U)
+/*! EDGE3 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE3_SHIFT)) & GPIO_INTEDG_EDGE3_MASK)
+#define GPIO_INTEDG_EDGE4_MASK (0x10U)
+#define GPIO_INTEDG_EDGE4_SHIFT (4U)
+/*! EDGE4 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE4_SHIFT)) & GPIO_INTEDG_EDGE4_MASK)
+#define GPIO_INTEDG_EDGE5_MASK (0x20U)
+#define GPIO_INTEDG_EDGE5_SHIFT (5U)
+/*! EDGE5 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE5_SHIFT)) & GPIO_INTEDG_EDGE5_MASK)
+#define GPIO_INTEDG_EDGE6_MASK (0x40U)
+#define GPIO_INTEDG_EDGE6_SHIFT (6U)
+/*! EDGE6 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE6_SHIFT)) & GPIO_INTEDG_EDGE6_MASK)
+#define GPIO_INTEDG_EDGE7_MASK (0x80U)
+#define GPIO_INTEDG_EDGE7_SHIFT (7U)
+/*! EDGE7 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE7_SHIFT)) & GPIO_INTEDG_EDGE7_MASK)
+#define GPIO_INTEDG_EDGE8_MASK (0x100U)
+#define GPIO_INTEDG_EDGE8_SHIFT (8U)
+/*! EDGE8 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE8_SHIFT)) & GPIO_INTEDG_EDGE8_MASK)
+#define GPIO_INTEDG_EDGE9_MASK (0x200U)
+#define GPIO_INTEDG_EDGE9_SHIFT (9U)
+/*! EDGE9 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE9_SHIFT)) & GPIO_INTEDG_EDGE9_MASK)
+#define GPIO_INTEDG_EDGE10_MASK (0x400U)
+#define GPIO_INTEDG_EDGE10_SHIFT (10U)
+/*! EDGE10 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE10_SHIFT)) & GPIO_INTEDG_EDGE10_MASK)
+#define GPIO_INTEDG_EDGE11_MASK (0x800U)
+#define GPIO_INTEDG_EDGE11_SHIFT (11U)
+/*! EDGE11 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE11_SHIFT)) & GPIO_INTEDG_EDGE11_MASK)
+#define GPIO_INTEDG_EDGE12_MASK (0x1000U)
+#define GPIO_INTEDG_EDGE12_SHIFT (12U)
+/*! EDGE12 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE12_SHIFT)) & GPIO_INTEDG_EDGE12_MASK)
+#define GPIO_INTEDG_EDGE13_MASK (0x2000U)
+#define GPIO_INTEDG_EDGE13_SHIFT (13U)
+/*! EDGE13 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE13_SHIFT)) & GPIO_INTEDG_EDGE13_MASK)
+#define GPIO_INTEDG_EDGE14_MASK (0x4000U)
+#define GPIO_INTEDG_EDGE14_SHIFT (14U)
+/*! EDGE14 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE14_SHIFT)) & GPIO_INTEDG_EDGE14_MASK)
+#define GPIO_INTEDG_EDGE15_MASK (0x8000U)
+#define GPIO_INTEDG_EDGE15_SHIFT (15U)
+/*! EDGE15 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE15_SHIFT)) & GPIO_INTEDG_EDGE15_MASK)
+#define GPIO_INTEDG_EDGE16_MASK (0x10000U)
+#define GPIO_INTEDG_EDGE16_SHIFT (16U)
+/*! EDGE16 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE16_SHIFT)) & GPIO_INTEDG_EDGE16_MASK)
+#define GPIO_INTEDG_EDGE17_MASK (0x20000U)
+#define GPIO_INTEDG_EDGE17_SHIFT (17U)
+/*! EDGE17 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE17_SHIFT)) & GPIO_INTEDG_EDGE17_MASK)
+#define GPIO_INTEDG_EDGE18_MASK (0x40000U)
+#define GPIO_INTEDG_EDGE18_SHIFT (18U)
+/*! EDGE18 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE18_SHIFT)) & GPIO_INTEDG_EDGE18_MASK)
+#define GPIO_INTEDG_EDGE19_MASK (0x80000U)
+#define GPIO_INTEDG_EDGE19_SHIFT (19U)
+/*! EDGE19 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE19_SHIFT)) & GPIO_INTEDG_EDGE19_MASK)
+#define GPIO_INTEDG_EDGE20_MASK (0x100000U)
+#define GPIO_INTEDG_EDGE20_SHIFT (20U)
+/*! EDGE20 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE20_SHIFT)) & GPIO_INTEDG_EDGE20_MASK)
+#define GPIO_INTEDG_EDGE21_MASK (0x200000U)
+#define GPIO_INTEDG_EDGE21_SHIFT (21U)
+/*! EDGE21 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE21_SHIFT)) & GPIO_INTEDG_EDGE21_MASK)
+#define GPIO_INTEDG_EDGE22_MASK (0x400000U)
+#define GPIO_INTEDG_EDGE22_SHIFT (22U)
+/*! EDGE22 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE22_SHIFT)) & GPIO_INTEDG_EDGE22_MASK)
+#define GPIO_INTEDG_EDGE23_MASK (0x800000U)
+#define GPIO_INTEDG_EDGE23_SHIFT (23U)
+/*! EDGE23 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE23_SHIFT)) & GPIO_INTEDG_EDGE23_MASK)
+#define GPIO_INTEDG_EDGE24_MASK (0x1000000U)
+#define GPIO_INTEDG_EDGE24_SHIFT (24U)
+/*! EDGE24 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE24_SHIFT)) & GPIO_INTEDG_EDGE24_MASK)
+#define GPIO_INTEDG_EDGE25_MASK (0x2000000U)
+#define GPIO_INTEDG_EDGE25_SHIFT (25U)
+/*! EDGE25 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE25_SHIFT)) & GPIO_INTEDG_EDGE25_MASK)
+#define GPIO_INTEDG_EDGE26_MASK (0x4000000U)
+#define GPIO_INTEDG_EDGE26_SHIFT (26U)
+/*! EDGE26 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE26_SHIFT)) & GPIO_INTEDG_EDGE26_MASK)
+#define GPIO_INTEDG_EDGE27_MASK (0x8000000U)
+#define GPIO_INTEDG_EDGE27_SHIFT (27U)
+/*! EDGE27 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE27_SHIFT)) & GPIO_INTEDG_EDGE27_MASK)
+#define GPIO_INTEDG_EDGE28_MASK (0x10000000U)
+#define GPIO_INTEDG_EDGE28_SHIFT (28U)
+/*! EDGE28 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE28_SHIFT)) & GPIO_INTEDG_EDGE28_MASK)
+#define GPIO_INTEDG_EDGE29_MASK (0x20000000U)
+#define GPIO_INTEDG_EDGE29_SHIFT (29U)
+/*! EDGE29 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE29_SHIFT)) & GPIO_INTEDG_EDGE29_MASK)
+#define GPIO_INTEDG_EDGE30_MASK (0x40000000U)
+#define GPIO_INTEDG_EDGE30_SHIFT (30U)
+/*! EDGE30 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE30_SHIFT)) & GPIO_INTEDG_EDGE30_MASK)
+#define GPIO_INTEDG_EDGE31_MASK (0x80000000U)
+#define GPIO_INTEDG_EDGE31_SHIFT (31U)
+/*! EDGE31 - Edge or level mode select bits.
+ * 0b0..Level mode
+ * 0b1..Edge mode
+ */
+#define GPIO_INTEDG_EDGE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE31_SHIFT)) & GPIO_INTEDG_EDGE31_MASK)
+/*! @} */
+
+/* The count of GPIO_INTEDG */
+#define GPIO_INTEDG_COUNT (8U)
+
+/*! @name INTSTATA - Interrupt status for interrupt A */
+/*! @{ */
+#define GPIO_INTSTATA_STATUS_MASK (0xFFFFFFFFU)
+#define GPIO_INTSTATA_STATUS_SHIFT (0U)
+/*! STATUS - Interrupt status.
+ */
+#define GPIO_INTSTATA_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTSTATA_STATUS_SHIFT)) & GPIO_INTSTATA_STATUS_MASK)
+/*! @} */
+
+/* The count of GPIO_INTSTATA */
+#define GPIO_INTSTATA_COUNT (8U)
+
+/*! @name INTSTATB - Interrupt status for interrupt B */
+/*! @{ */
+#define GPIO_INTSTATB_STATUS_MASK (0xFFFFFFFFU)
+#define GPIO_INTSTATB_STATUS_SHIFT (0U)
+/*! STATUS - Interrupt status
+ */
+#define GPIO_INTSTATB_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_INTSTATB_STATUS_SHIFT)) & GPIO_INTSTATB_STATUS_MASK)
+/*! @} */
+
+/* The count of GPIO_INTSTATB */
+#define GPIO_INTSTATB_COUNT (8U)
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral GPIO base address */
+ #define GPIO_BASE (0x50100000u)
+ /** Peripheral GPIO base address */
+ #define GPIO_BASE_NS (0x40100000u)
+ /** Peripheral GPIO base pointer */
+ #define GPIO ((GPIO_Type *)GPIO_BASE)
+ /** Peripheral GPIO base pointer */
+ #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS)
+ /** Peripheral SECGPIO base address */
+ #define SECGPIO_BASE (0x50204000u)
+ /** Peripheral SECGPIO base address */
+ #define SECGPIO_BASE_NS (0x40204000u)
+ /** Peripheral SECGPIO base pointer */
+ #define SECGPIO ((GPIO_Type *)SECGPIO_BASE)
+ /** Peripheral SECGPIO base pointer */
+ #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS)
+ /** Array initializer of GPIO peripheral base addresses */
+ #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE }
+ /** Array initializer of GPIO peripheral base pointers */
+ #define GPIO_BASE_PTRS { GPIO, SECGPIO }
+ /** Array initializer of GPIO peripheral base addresses */
+ #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS }
+ /** Array initializer of GPIO peripheral base pointers */
+ #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS }
+#else
+ /** Peripheral GPIO base address */
+ #define GPIO_BASE (0x40100000u)
+ /** Peripheral GPIO base pointer */
+ #define GPIO ((GPIO_Type *)GPIO_BASE)
+ /** Peripheral SECGPIO base address */
+ #define SECGPIO_BASE (0x40204000u)
+ /** Peripheral SECGPIO base pointer */
+ #define SECGPIO ((GPIO_Type *)SECGPIO_BASE)
+ /** Array initializer of GPIO peripheral base addresses */
+ #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE }
+ /** Array initializer of GPIO peripheral base pointers */
+ #define GPIO_BASE_PTRS { GPIO, SECGPIO }
+#endif
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- HASHCRYPT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer
+ * @{
+ */
+
+/** HASHCRYPT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< Control, offset: 0x0 */
+ __IO uint32_t STATUS; /**< Status, offset: 0x4 */
+ __IO uint32_t INTENSET; /**< Interrupt Enable, offset: 0x8 */
+ __IO uint32_t INTENCLR; /**< Interrupt Clear, offset: 0xC */
+ __IO uint32_t MEMCTRL; /**< Memory Control, offset: 0x10 */
+ __IO uint32_t MEMADDR; /**< Memory Address, offset: 0x14 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t INDATA; /**< Input Data, offset: 0x20 */
+ __O uint32_t ALIAS[7]; /**< Alias, array offset: 0x24, array step: 0x4 */
+ __I uint32_t DIGEST0[8]; /**< Digest0 n/Output Data0 n, array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_1[32];
+ __IO uint32_t CRYPTCFG; /**< Cryptographic Configuration, offset: 0x80 */
+ __I uint32_t CONFIG; /**< Configuration, offset: 0x84 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t LOCK; /**< Lock, offset: 0x8C */
+ __O uint32_t MASK[4]; /**< Mask, array offset: 0x90, array step: 0x4 */
+ __IO uint32_t RELOAD[8]; /**< DIGEST/OUTDATA Reload, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_3[16];
+ __O uint32_t PRNG_SEED; /**< PRNG Seed, offset: 0xD0 */
+ uint8_t RESERVED_4[4];
+ __O uint32_t PRNG_OUT; /**< PRNG Output, offset: 0xD8 */
+} HASHCRYPT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- HASHCRYPT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control */
+/*! @{ */
+#define HASHCRYPT_CTRL_MODE_MASK (0x7U)
+#define HASHCRYPT_CTRL_MODE_SHIFT (0U)
+/*! MODE - Operational Mode
+ * 0b000..Disabled
+ * 0b001..SHA1 is enabled
+ * 0b010..SHA2-256 is enabled
+ * 0b011..
+ * 0b100..AES is enabled (see also CRYPTCFG register for more controls)
+ * 0b101..ICB-AES is enabled (see also CRYPTCFG register for more controls)
+ * 0b110..
+ * 0b111..
+ */
+#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK)
+#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U)
+#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U)
+/*! NEW_HASH - New Hash Operation
+ * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result.
+ */
+#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK)
+#define HASHCRYPT_CTRL_RELOAD_MASK (0x20U)
+#define HASHCRYPT_CTRL_RELOAD_SHIFT (5U)
+/*! RELOAD - Reload
+ * 0b0..Disabled
+ * 0b1..Allows the SHA RELOAD registers to be used.
+ */
+#define HASHCRYPT_CTRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_RELOAD_SHIFT)) & HASHCRYPT_CTRL_RELOAD_MASK)
+#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U)
+#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U)
+/*! DMA_I - DMA to Fill INDATA.
+ * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used.
+ * 0b1..DMA will push in the data.
+ */
+#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK)
+#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U)
+#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U)
+/*! DMA_O - DMA to Drain the Digest/Output
+ * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt.
+ * 0b1..DMA will drain the data.
+ */
+#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK)
+#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U)
+#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U)
+/*! HASHSWPB - Hash Swap Bytes
+ */
+#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK)
+/*! @} */
+
+/*! @name STATUS - Status */
+/*! @{ */
+#define HASHCRYPT_STATUS_WAITING_MASK (0x1U)
+#define HASHCRYPT_STATUS_WAITING_SHIFT (0U)
+/*! WAITING - Waiting for Data
+ * 0b0..Not waiting for data - may be disabled or may be busy. For cryptographic uses, this is not set if IsLast
+ * is set nor will it set until at least 1 word is read of the output.
+ * 0b1..Waiting for data to be written (16 words)
+ */
+#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK)
+#define HASHCRYPT_STATUS_DIGEST_MASK (0x2U)
+#define HASHCRYPT_STATUS_DIGEST_SHIFT (1U)
+/*! DIGEST - Digest/Outdata
+ * 0b0..Digest is not ready
+ * 0b1..Digest is ready. Application may read it or may write more data.
+ */
+#define HASHCRYPT_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK)
+#define HASHCRYPT_STATUS_ERROR_MASK (0x4U)
+#define HASHCRYPT_STATUS_ERROR_SHIFT (2U)
+/*! ERROR - Error
+ * 0b0..No error.
+ * 0b1..An error occurred since last cleared (written 1 to clear).
+ */
+#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK)
+#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U)
+#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U)
+/*! NEEDKEY - Need Key to be Written
+ * 0b0..No Key is needed and writes will not be treated as Key
+ * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING.
+ */
+#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK)
+#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U)
+#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U)
+/*! NEEDIV - Need IV/Nonce
+ * 0b0..No IV/Nonce is needed, either because written already or because not needed.
+ * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING.
+ */
+#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK)
+#define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U)
+#define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U)
+/*! ICBIDX - ICB Index Count
+ */
+#define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK)
+/*! @} */
+
+/*! @name INTENSET - Interrupt Enable */
+/*! @{ */
+#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U)
+#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U)
+/*! WAITING - Interrupt When Waiting for Data Input
+ * 0b0..Interrupt not enabled when waiting
+ * 0b1..Interrupt is enabled when waiting
+ */
+#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK)
+#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U)
+#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U)
+/*! DIGEST - Digest/Outdata
+ * 0b0..Interrupt not enabled when Digest is ready
+ * 0b1..Interrupt is enabled when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done).
+ */
+#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK)
+#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U)
+#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U)
+/*! ERROR - Interrupt on Error
+ * 0b0..Interrupt not enabled on Error.
+ * 0b1..Interrupt is enabled on Error (until cleared).
+ */
+#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK)
+/*! @} */
+
+/*! @name INTENCLR - Interrupt Clear */
+/*! @{ */
+#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U)
+#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U)
+/*! WAITING - Waiting
+ */
+#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK)
+#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U)
+#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U)
+/*! DIGEST - Digest
+ */
+#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK)
+#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U)
+#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U)
+/*! ERROR - Error
+ */
+#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK)
+/*! @} */
+
+/*! @name MEMCTRL - Memory Control */
+/*! @{ */
+#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U)
+#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U)
+/*! MASTER - Master
+ * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA.
+ * 0b1..Mastering is enabled and DMA and INDATA should not be used.
+ */
+#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK)
+#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U)
+#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U)
+/*! COUNT - Count
+ * 0b00000000000..Done. Nothing to process
+ * 0b00000000001..One 512-bit block to hash
+ * 0b00000000010..Two 512-bit block to hash
+ * 0b00000000011..Three 512-bit block to hash
+ */
+#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK)
+/*! @} */
+
+/*! @name MEMADDR - Memory Address */
+/*! @{ */
+#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU)
+#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U)
+/*! BASE - Base
+ */
+#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK)
+/*! @} */
+
+/*! @name INDATA - Input Data */
+/*! @{ */
+#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU)
+#define HASHCRYPT_INDATA_DATA_SHIFT (0U)
+/*! DATA - Data
+ */
+#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK)
+/*! @} */
+
+/*! @name ALIAS - Alias */
+/*! @{ */
+#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU)
+#define HASHCRYPT_ALIAS_DATA_SHIFT (0U)
+/*! DATA - Data
+ */
+#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK)
+/*! @} */
+
+/* The count of HASHCRYPT_ALIAS */
+#define HASHCRYPT_ALIAS_COUNT (7U)
+
+/*! @name DIGEST0 - Digest0 n/Output Data0 n */
+/*! @{ */
+#define HASHCRYPT_DIGEST0_DIGEST_MASK (0xFFFFFFFFU)
+#define HASHCRYPT_DIGEST0_DIGEST_SHIFT (0U)
+/*! DIGEST - Digest
+ */
+#define HASHCRYPT_DIGEST0_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK)
+/*! @} */
+
+/* The count of HASHCRYPT_DIGEST0 */
+#define HASHCRYPT_DIGEST0_COUNT (8U)
+
+/*! @name CRYPTCFG - Cryptographic Configuration */
+/*! @{ */
+#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U)
+#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U)
+/*! MSW1ST_OUT - Most Significant Word 1st Out
+ */
+#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK)
+#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U)
+#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U)
+/*! SWAPKEY - Swap Key
+ */
+#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK)
+#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U)
+#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U)
+/*! SWAPDAT - Swap Data/IV Inputs
+ */
+#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK)
+#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U)
+#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U)
+/*! MSW1ST - Most Significant Word 1st Load
+ */
+#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK)
+#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U)
+#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U)
+/*! AESMODE - AES Cipher Mode
+ * 0b00..ECB - used as is
+ * 0b01..CBC mode (see details on IV/nonce)
+ * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS.
+ * 0b11..Reserved
+ */
+#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK)
+#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U)
+#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U)
+/*! AESDECRYPT - AES Decrypt
+ * 0b0..Encrypt
+ * 0b1..Decrypt
+ */
+#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK)
+#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U)
+#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U)
+/*! AESSECRET - AES Secret
+ * 0b0..User key provided in normal way
+ * 0b1..Secret key provided in hidden way by HW
+ */
+#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK)
+#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U)
+#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U)
+/*! AESKEYSZ - AES Key Size
+ * 0b00..128 bit key
+ * 0b01..192 bit key
+ * 0b10..256 bit key
+ * 0b11..Reserved
+ */
+#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK)
+#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U)
+#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U)
+/*! AESCTRPOS - AES CTR Position
+ */
+#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK)
+#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U)
+#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U)
+/*! STREAMLAST - Stream Last
+ */
+#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK)
+#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U)
+#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U)
+/*! ICBSZ - ICB Size
+ * 0b00..32 bits of the IV/ctr are used (from 127:96)
+ * 0b01..64 bits of the IV/ctr are used (from 127:64)
+ * 0b10..96 bits of the IV/ctr are used (from 127:32)
+ * 0b11..All 128 bits of the IV/ctr are used
+ */
+#define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK)
+#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U)
+#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U)
+/*! ICBSTRM - ICB Stream Size
+ * 0b00..8 blocks
+ * 0b01..16 blocks
+ * 0b10..32 blocks
+ * 0b11..64 blocks
+ */
+#define HASHCRYPT_CRYPTCFG_ICBSTRM(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK)
+/*! @} */
+
+/*! @name CONFIG - Configuration */
+/*! @{ */
+#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U)
+#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U)
+/*! DUAL - Reads 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit
+ */
+#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK)
+#define HASHCRYPT_CONFIG_DMA_MASK (0x2U)
+#define HASHCRYPT_CONFIG_DMA_SHIFT (1U)
+/*! DMA - Reads 1 if DMA is connected
+ */
+#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK)
+#define HASHCRYPT_CONFIG_AHB_MASK (0x8U)
+#define HASHCRYPT_CONFIG_AHB_SHIFT (3U)
+/*! AHB - Reads 1 if AHB Master is enabled
+ */
+#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK)
+#define HASHCRYPT_CONFIG_AES_MASK (0x40U)
+#define HASHCRYPT_CONFIG_AES_SHIFT (6U)
+/*! AES - Reads 1 if AES 128 is included
+ */
+#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK)
+#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U)
+#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U)
+/*! AESKEY - Reads 1 if AES 192 and 256 also included
+ */
+#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK)
+#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U)
+#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U)
+/*! SECRET - Reads 1 if AES Secret key is available
+ */
+#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK)
+#define HASHCRYPT_CONFIG_ICB_MASK (0x800U)
+#define HASHCRYPT_CONFIG_ICB_SHIFT (11U)
+/*! ICB - ICB
+ */
+#define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK)
+/*! @} */
+
+/*! @name LOCK - Lock */
+/*! @{ */
+#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U)
+#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U)
+/*! SECLOCK - Secure Lock
+ * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests.
+ * 0b01..Locks to the current security level. AHB Master will issue requests at this level.
+ */
+#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK)
+#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U)
+#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U)
+/*! PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0
+ */
+#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK)
+/*! @} */
+
+/*! @name MASK - Mask */
+/*! @{ */
+#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU)
+#define HASHCRYPT_MASK_MASK_SHIFT (0U)
+/*! MASK - A random word.
+ */
+#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK)
+/*! @} */
+
+/* The count of HASHCRYPT_MASK */
+#define HASHCRYPT_MASK_COUNT (4U)
+
+/*! @name RELOAD - DIGEST/OUTDATA Reload */
+/*! @{ */
+#define HASHCRYPT_RELOAD_DIGEST_MASK (0xFFFFFFFFU)
+#define HASHCRYPT_RELOAD_DIGEST_SHIFT (0U)
+/*! DIGEST - SHA Digest word to reload.
+ */
+#define HASHCRYPT_RELOAD_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_RELOAD_DIGEST_SHIFT)) & HASHCRYPT_RELOAD_DIGEST_MASK)
+/*! @} */
+
+/* The count of HASHCRYPT_RELOAD */
+#define HASHCRYPT_RELOAD_COUNT (8U)
+
+/*! @name PRNG_SEED - PRNG Seed */
+/*! @{ */
+#define HASHCRYPT_PRNG_SEED_PRNG_SEED_MASK (0xFFFFFFFFU)
+#define HASHCRYPT_PRNG_SEED_PRNG_SEED_SHIFT (0U)
+/*! PRNG_SEED - SHA Digest word to reload.
+ */
+#define HASHCRYPT_PRNG_SEED_PRNG_SEED(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_PRNG_SEED_PRNG_SEED_SHIFT)) & HASHCRYPT_PRNG_SEED_PRNG_SEED_MASK)
+/*! @} */
+
+/*! @name PRNG_OUT - PRNG Output */
+/*! @{ */
+#define HASHCRYPT_PRNG_OUT_PRNG_OUT_R_MASK (0xFFFFFFFFU)
+#define HASHCRYPT_PRNG_OUT_PRNG_OUT_R_SHIFT (0U)
+/*! PRNG_OUT_R - SHA Digest word to reload.
+ */
+#define HASHCRYPT_PRNG_OUT_PRNG_OUT_R(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_PRNG_OUT_PRNG_OUT_R_SHIFT)) & HASHCRYPT_PRNG_OUT_PRNG_OUT_R_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group HASHCRYPT_Register_Masks */
+
+
+/* HASHCRYPT - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral HASHCRYPT base address */
+ #define HASHCRYPT_BASE (0x50208000u)
+ /** Peripheral HASHCRYPT base address */
+ #define HASHCRYPT_BASE_NS (0x40208000u)
+ /** Peripheral HASHCRYPT base pointer */
+ #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE)
+ /** Peripheral HASHCRYPT base pointer */
+ #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS)
+ /** Array initializer of HASHCRYPT peripheral base addresses */
+ #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE }
+ /** Array initializer of HASHCRYPT peripheral base pointers */
+ #define HASHCRYPT_BASE_PTRS { HASHCRYPT }
+ /** Array initializer of HASHCRYPT peripheral base addresses */
+ #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS }
+ /** Array initializer of HASHCRYPT peripheral base pointers */
+ #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS }
+#else
+ /** Peripheral HASHCRYPT base address */
+ #define HASHCRYPT_BASE (0x40208000u)
+ /** Peripheral HASHCRYPT base pointer */
+ #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE)
+ /** Array initializer of HASHCRYPT peripheral base addresses */
+ #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE }
+ /** Array initializer of HASHCRYPT peripheral base pointers */
+ #define HASHCRYPT_BASE_PTRS { HASHCRYPT }
+#endif
+/** Interrupt vectors for the HASHCRYPT peripheral type */
+#define HASHCRYPT_IRQS { HASHCRYPT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group HASHCRYPT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[2048];
+ __IO uint32_t CFG; /**< Configuration Register, offset: 0x800 */
+ __IO uint32_t STAT; /**< Status Register, offset: 0x804 */
+ __IO uint32_t INTENSET; /**< Interrupt Enable Set Register, offset: 0x808 */
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear Register, offset: 0x80C */
+ __IO uint32_t TIMEOUT; /**< Time-out Register, offset: 0x810 */
+ __IO uint32_t CLKDIV; /**< Clock Divider Register, offset: 0x814 */
+ __I uint32_t INTSTAT; /**< Interrupt Status Register, offset: 0x818 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t MSTCTL; /**< Master Control Register, offset: 0x820 */
+ __IO uint32_t MSTTIME; /**< Master Timing Register, offset: 0x824 */
+ __IO uint32_t MSTDAT; /**< Master Data Register, offset: 0x828 */
+ uint8_t RESERVED_2[20];
+ __IO uint32_t SLVCTL; /**< Slave Control Register, offset: 0x840 */
+ __IO uint32_t SLVDAT; /**< Slave Data Register, offset: 0x844 */
+ __IO uint32_t SLVADR[4]; /**< Slave Address Register, array offset: 0x848, array step: 0x4 */
+ __IO uint32_t SLVQUAL0; /**< Slave Qualification for Address 0 Register, offset: 0x858 */
+ uint8_t RESERVED_3[36];
+ __I uint32_t MONRXDAT; /**< Monitor Receiver Data Register, offset: 0x880 */
+ uint8_t RESERVED_4[1912];
+ __I uint32_t ID; /**< Peripheral Identification Register, offset: 0xFFC */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name CFG - Configuration Register */
+/*! @{ */
+#define I2C_CFG_MSTEN_MASK (0x1U)
+#define I2C_CFG_MSTEN_SHIFT (0U)
+/*! MSTEN - Master Enable
+ * 0b0..Disabled. The I2C Master function is disabled. When disabled, the Master configuration settings are not
+ * changed, but the Master function is internally reset.
+ * 0b1..Enabled. The I2C Master function is enabled.
+ */
+#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
+#define I2C_CFG_SLVEN_MASK (0x2U)
+#define I2C_CFG_SLVEN_SHIFT (1U)
+/*! SLVEN - Slave Enable
+ * 0b0..Disabled. The I2C slave function is disabled. When disabled, the Slave configuration settings are not
+ * changed, but the Slave function is internally reset.
+ * 0b1..Enabled. The I2C slave function is enabled.
+ */
+#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
+#define I2C_CFG_MONEN_MASK (0x4U)
+#define I2C_CFG_MONEN_SHIFT (2U)
+/*! MONEN - Monitor Enable
+ * 0b0..Disabled. The I2C Monitor function is disabled. When disabled, the Monitor function configuration
+ * settings are not changed, but the Monitor function is internally reset.
+ * 0b1..Enabled. The I2C Monitor function is enabled.
+ */
+#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
+#define I2C_CFG_TIMEOUTEN_MASK (0x8U)
+#define I2C_CFG_TIMEOUTEN_SHIFT (3U)
+/*! TIMEOUTEN - I2C bus Time-out Enable
+ * 0b0..Disabled. The time-out function is disabled. When disabled, the time-out function is internally reset.
+ * 0b1..Enabled. The time-out function is enabled. Both types of time-out flags will be generated and will cause
+ * interrupts if those flags are enabled. Typically, only one time-out flag will be used in a system.
+ */
+#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
+#define I2C_CFG_MONCLKSTR_MASK (0x10U)
+#define I2C_CFG_MONCLKSTR_SHIFT (4U)
+/*! MONCLKSTR - Monitor function Clock Stretching
+ * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
+ * to read data provided by the Monitor function before it (the data) is overwritten. This mode can be used
+ * when non-invasive monitoring is critical.
+ * 0b1..Enabled. The Monitor function will perform clock stretching, to ensure that the software or DMA can read
+ * all incoming data supplied by the Monitor function.
+ */
+#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
+#define I2C_CFG_HSCAPABLE_MASK (0x20U)
+#define I2C_CFG_HSCAPABLE_SHIFT (5U)
+/*! HSCAPABLE - High Speed mode Capable enable
+ * 0b0..Fast mode Plus enable
+ * 0b1..High Speed mode enable
+ */
+#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
+/*! @} */
+
+/*! @name STAT - Status Register */
+/*! @{ */
+#define I2C_STAT_MSTPENDING_MASK (0x1U)
+#define I2C_STAT_MSTPENDING_SHIFT (0U)
+/*! MSTPENDING - Master Pending
+ * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
+ * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
+ * idle state, then the master is waiting to receive or transmit data, or is waiting for the NACK bit.
+ */
+#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
+#define I2C_STAT_MSTSTATE_MASK (0xEU)
+#define I2C_STAT_MSTSTATE_SHIFT (1U)
+/*! MSTSTATE - Master State code
+ * 0b000..Idle. The Master function is available to be used for a new transaction.
+ * 0b001..Receive ready. Received data is available (in Master Receiver mode). Address plus Read was previously sent and Acknowledged by a slave.
+ * 0b010..Transmit ready. Data can be transmitted (in Master Transmitter mode). Address plus Write was previously sent and Acknowledged by a slave.
+ * 0b011..NACK Address. Slave NACKed address.
+ * 0b100..NACK Data. Slave NACKed transmitted data.
+ */
+#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
+#define I2C_STAT_MSTARBLOSS_MASK (0x10U)
+#define I2C_STAT_MSTARBLOSS_SHIFT (4U)
+/*! MSTARBLOSS - Master Arbitration Loss flag
+ * 0b0..No Arbitration Loss has occurred
+ * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master
+ * function has already stopped driving the bus and has gone into an idle state. Software can respond by doing
+ * nothing, or by sending a Start (to attempt to gain control of the bus when the bus next becomes idle).
+ */
+#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
+#define I2C_STAT_MSTSTSTPERR_MASK (0x40U)
+#define I2C_STAT_MSTSTSTPERR_SHIFT (6U)
+/*! MSTSTSTPERR - Master Start/Stop Error flag
+ * 0b0..No Start/Stop Error has occurred.
+ * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when Start
+ * or Stop is not allowed by the I2C specification. The Master interface has stopped driving the bus and
+ * gone into an idle state; no action is required. A request for a Start could be made, or software could
+ * attempt to make sure that the bus has not stalled.
+ */
+#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
+#define I2C_STAT_SLVPENDING_MASK (0x100U)
+#define I2C_STAT_SLVPENDING_SHIFT (8U)
+/*! SLVPENDING - Slave Pending
+ * 0b0..In progress. The Slave function does not currently need software service.
+ * 0b1..Pending. The Slave function needs software service. Information about what is needed is in the Slave state field (SLVSTATE).
+ */
+#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
+#define I2C_STAT_SLVSTATE_MASK (0x600U)
+#define I2C_STAT_SLVSTATE_SHIFT (9U)
+/*! SLVSTATE - Slave State
+ * 0b00..Slave address. Address plus R/W received. At least one of the 4 slave addresses has been matched by hardware.
+ * 0b01..Slave receive. Received data is available (in Slave Receiver mode).
+ * 0b10..Slave transmit. Data can be transmitted (in Slave Transmitter mode).
+ * 0b11..Reserved
+ */
+#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
+#define I2C_STAT_SLVNOTSTR_MASK (0x800U)
+#define I2C_STAT_SLVNOTSTR_SHIFT (11U)
+/*! SLVNOTSTR - Slave Not Stretching
+ * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleepmode cannot be entered at this time.
+ * 0b1..Not stretching. The slave function is not currently stretching the I2C bus clock. Deep-sleep mode can be entered at this time.
+ */
+#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
+#define I2C_STAT_SLVIDX_MASK (0x3000U)
+#define I2C_STAT_SLVIDX_SHIFT (12U)
+/*! SLVIDX - Slave address match Index T
+ * 0b00..Address 0. Slave address 0 was matched.
+ * 0b01..Address 1. Slave address 1 was matched.
+ * 0b10..Address 2. Slave address 2 was matched.
+ * 0b11..Address 3. Slave address 3 was matched.
+ */
+#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
+#define I2C_STAT_SLVSEL_MASK (0x4000U)
+#define I2C_STAT_SLVSEL_SHIFT (14U)
+/*! SLVSEL - Slave selected flag
+ * 0b0..Not selected. The Slave function is not currently selected.
+ * 0b1..Selected. The Slave function is currently selected.
+ */
+#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
+#define I2C_STAT_SLVDESEL_MASK (0x8000U)
+#define I2C_STAT_SLVDESEL_SHIFT (15U)
+/*! SLVDESEL - Slave Deselected flag
+ * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that the Slave is
+ * currently selected. That information is in the SLVSEL flag.
+ * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
+ * changing from 1 to 0. See SLVSEL for details about when that event occurs.
+ */
+#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
+#define I2C_STAT_MONRDY_MASK (0x10000U)
+#define I2C_STAT_MONRDY_SHIFT (16U)
+/*! MONRDY - Monitor Ready
+ * 0b0..No data. The Monitor function does not currently have data available.
+ * 0b1..Data waiting. The Monitor function has data waiting to be read.
+ */
+#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
+#define I2C_STAT_MONOV_MASK (0x20000U)
+#define I2C_STAT_MONOV_SHIFT (17U)
+/*! MONOV - Monitor Overflow flag
+ * 0b0..No overrun. Monitor data has not overrun.
+ * 0b1..Overrun. A Monitor data overrun has occurred. An overrun can only happen when Monitor clock stretching
+ * not enabled via the CFG[MONCLKSTR] bit. Writing 1 to MONOV bit clears the MONOV flag.
+ */
+#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
+#define I2C_STAT_MONACTIVE_MASK (0x40000U)
+#define I2C_STAT_MONACTIVE_SHIFT (18U)
+/*! MONACTIVE - Monitor Active flag
+ * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
+ * 0b1..Active. The Monitor function considers the I2C bus to be active.
+ */
+#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
+#define I2C_STAT_MONIDLE_MASK (0x80000U)
+#define I2C_STAT_MONIDLE_SHIFT (19U)
+/*! MONIDLE - Monitor Idle flag
+ * 0b0..Not idle. The I2C bus is not idle, or MONIDLE flag has been cleared by software.
+ * 0b1..Idle. The I2C bus has gone idle at least once, since the last time MONIDLE flag was cleared by software.
+ */
+#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
+#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)
+#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)
+/*! EVENTTIMEOUT - Event Time-out Interrupt flag
+ * 0b0..No time-out. I2C bus events have not caused a time-out.
+ * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
+ */
+#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
+#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)
+#define I2C_STAT_SCLTIMEOUT_SHIFT (25U)
+/*! SCLTIMEOUT - SCL Time-out Interrupt flag
+ * 0b0..No time-out. SCL low time has not caused a time-out.
+ * 0b1..Time-out. SCL low time has caused a time-out.
+ */
+#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
+/*! @} */
+
+/*! @name INTENSET - Interrupt Enable Set Register */
+/*! @{ */
+#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)
+#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)
+/*! MSTPENDINGEN - Master Pending interrupt Enable
+ * 0b0..Disabled. The MstPending interrupt is disabled.
+ * 0b1..Enabled. The MstPending interrupt is enabled.
+ */
+#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
+#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)
+#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)
+/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable
+ * 0b0..Disabled. The MstArbLoss interrupt is disabled.
+ * 0b1..Enabled. The MstArbLoss interrupt is enabled.
+ */
+#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
+#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)
+#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)
+/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable
+ * 0b0..Disabled. The MstStStpErr interrupt is disabled.
+ * 0b1..Enabled. The MstStStpErr interrupt is enabled.
+ */
+#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
+#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)
+#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)
+/*! SLVPENDINGEN - Slave Pending interrupt Enable
+ * 0b0..Disabled. The SlvPending interrupt is disabled.
+ * 0b1..Enabled. The SlvPending interrupt is enabled.
+ */
+#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
+#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)
+#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)
+/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable
+ * 0b0..Disabled. The SlvNotStr interrupt is disabled.
+ * 0b1..Enabled. The SlvNotStr interrupt is enabled.
+ */
+#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
+#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)
+#define I2C_INTENSET_SLVDESELEN_SHIFT (15U)
+/*! SLVDESELEN - Slave Deselect interrupt Enable
+ * 0b0..Disabled. The SlvDeSel interrupt is disabled.
+ * 0b1..Enabled. The SlvDeSel interrupt is enabled.
+ */
+#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
+#define I2C_INTENSET_MONRDYEN_MASK (0x10000U)
+#define I2C_INTENSET_MONRDYEN_SHIFT (16U)
+/*! MONRDYEN - Monitor data Ready interrupt Enable
+ * 0b0..Disabled. The MonRdy interrupt is disabled.
+ * 0b1..Enabled. The MonRdy interrupt is enabled.
+ */
+#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
+#define I2C_INTENSET_MONOVEN_MASK (0x20000U)
+#define I2C_INTENSET_MONOVEN_SHIFT (17U)
+/*! MONOVEN - Monitor Overrun interrupt Enable
+ * 0b0..Disabled. The MonOv interrupt is disabled.
+ * 0b1..Enabled. The MonOv interrupt is enabled.
+ */
+#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
+#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)
+#define I2C_INTENSET_MONIDLEEN_SHIFT (19U)
+/*! MONIDLEEN - Monitor Idle interrupt Enable
+ * 0b0..Disabled. The MonIdle interrupt is disabled.
+ * 0b1..Enabled. The MonIdle interrupt is enabled.
+ */
+#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
+#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)
+#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)
+/*! EVENTTIMEOUTEN - Event Time-out interrupt Enable
+ * 0b0..Disabled. The Event time-out interrupt is disabled.
+ * 0b1..Enabled. The Event time-out interrupt is enabled.
+ */
+#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
+#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)
+#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)
+/*! SCLTIMEOUTEN - SCL Time-out interrupt Enable
+ * 0b0..Disabled. The SCL time-out interrupt is disabled.
+ * 0b1..Enabled. The SCL time-out interrupt is enabled.
+ */
+#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
+/*! @} */
+
+/*! @name INTENCLR - Interrupt Enable Clear Register */
+/*! @{ */
+#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)
+#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)
+/*! MSTPENDINGCLR - Master Pending interrupt clear
+ * 0b0..No effect on interrupt
+ * 0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
+#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)
+#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)
+/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear
+ * 0b0..No effect on interrupt
+ * 0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)
+/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear
+ * 0b0..No effect on interrupt
+ * 0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
+#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)
+#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)
+/*! SLVPENDINGCLR - Slave Pending interrupt clear
+ * 0b0..No effect on interrupt
+ * 0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
+#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)
+#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)
+/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear
+ * 0b0..No effect on interrupt
+ * 0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
+#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)
+#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)
+/*! SLVDESELCLR - Slave Deselect interrupt clear
+ * 0b0..No effect on interrupt
+ * 0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
+#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)
+#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)
+/*! MONRDYCLR - Monitor data Ready interrupt clear
+ * 0b0..No effect on interrupt
+ * 0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
+#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)
+#define I2C_INTENCLR_MONOVCLR_SHIFT (17U)
+/*! MONOVCLR - Monitor Overrun interrupt clear
+ * 0b0..No effect on interrupt
+ * 0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
+#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)
+#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)
+/*! MONIDLECLR - Monitor Idle interrupt clear
+ * 0b0..No effect on interrupt
+ * 0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)
+/*! EVENTTIMEOUTCLR - Event time-out interrupt clear
+ * 0b0..No effect on interrupt
+ * 0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)
+/*! SCLTIMEOUTCLR - SCL time-out interrupt clear
+ * 0b0..No effect on interrupt
+ * 0b1..Clears the interrupt bit in INTENSET register
+ */
+#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
+/*! @} */
+
+/*! @name TIMEOUT - Time-out Register */
+/*! @{ */
+#define I2C_TIMEOUT_TOMIN_MASK (0xFU)
+#define I2C_TIMEOUT_TOMIN_SHIFT (0U)
+/*! TOMIN - Time-out time value, the bottom 4 bits
+ */
+#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
+#define I2C_TIMEOUT_TO_MASK (0xFFF0U)
+#define I2C_TIMEOUT_TO_SHIFT (4U)
+/*! TO - Time-out time value
+ * 0b000000000000..A time-out will occur after 16 counts of the I2C function clock.
+ * 0b000000000001..A time-out will occur after 32 counts of the I2C function clock.
+ * 0b111111111111..A time-out will occur after 65,536 counts of the I2C function clock.
+ */
+#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
+/*! @} */
+
+/*! @name CLKDIV - Clock Divider Register */
+/*! @{ */
+#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)
+#define I2C_CLKDIV_DIVVAL_SHIFT (0U)
+/*! DIVVAL - Divider Value
+ * 0b0000000000000000..FCLK is used directly by the I2C.
+ * 0b0000000000000001..FCLK is divided by 2 before being used by the I2C.
+ * 0b0000000000000010..FCLK is divided by 3 before being used by the I2C.
+ * 0b1111111111111111..FCLK is divided by 65,536 before being used by the I2C.
+ */
+#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt Status Register */
+/*! @{ */
+#define I2C_INTSTAT_MSTPENDING_MASK (0x1U)
+#define I2C_INTSTAT_MSTPENDING_SHIFT (0U)
+/*! MSTPENDING - Master Pending
+ * 0b0..Not active
+ * 0b1..Active
+ */
+#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
+#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)
+#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)
+/*! MSTARBLOSS - Master Arbitration Loss flag
+ * 0b0..Not active
+ * 0b1..Active
+ */
+#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
+#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)
+#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)
+/*! MSTSTSTPERR - Master Start/Stop Error flag
+ * 0b0..Not active
+ * 0b1..Active
+ */
+#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
+#define I2C_INTSTAT_SLVPENDING_MASK (0x100U)
+#define I2C_INTSTAT_SLVPENDING_SHIFT (8U)
+/*! SLVPENDING - Slave Pending
+ * 0b0..Not active
+ * 0b1..Active
+ */
+#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
+#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)
+#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)
+/*! SLVNOTSTR - Slave Not Stretching status
+ * 0b0..Not active
+ * 0b1..Active
+ */
+#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
+#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)
+#define I2C_INTSTAT_SLVDESEL_SHIFT (15U)
+/*! SLVDESEL - Slave Deselected flag
+ * 0b0..Not active
+ * 0b1..Active
+ */
+#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
+#define I2C_INTSTAT_MONRDY_MASK (0x10000U)
+#define I2C_INTSTAT_MONRDY_SHIFT (16U)
+/*! MONRDY - Monitor Ready
+ * 0b0..Not active
+ * 0b1..Active
+ */
+#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
+#define I2C_INTSTAT_MONOV_MASK (0x20000U)
+#define I2C_INTSTAT_MONOV_SHIFT (17U)
+/*! MONOV - Monitor Overflow flag
+ * 0b0..Not active
+ * 0b1..Active
+ */
+#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
+#define I2C_INTSTAT_MONIDLE_MASK (0x80000U)
+#define I2C_INTSTAT_MONIDLE_SHIFT (19U)
+/*! MONIDLE - Monitor Idle flag
+ * 0b0..Not active
+ * 0b1..Active
+ */
+#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
+#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)
+#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)
+/*! EVENTTIMEOUT - Event Time-out Interrupt flag
+ * 0b0..Not active
+ * 0b1..Active
+ */
+#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
+#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)
+#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)
+/*! SCLTIMEOUT - SCL Time-out Interrupt flag
+ * 0b0..Not active
+ * 0b1..Active
+ */
+#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
+/*! @} */
+
+/*! @name MSTCTL - Master Control Register */
+/*! @{ */
+#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)
+#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)
+/*! MSTCONTINUE - Master Continue(write-only)
+ * 0b0..No effect
+ * 0b1..Continue. Informs the Master function to continue to the next operation. This action must done after
+ * writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
+ */
+#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
+#define I2C_MSTCTL_MSTSTART_MASK (0x2U)
+#define I2C_MSTCTL_MSTSTART_SHIFT (1U)
+/*! MSTSTART - Master Start control(write-only)
+ * 0b0..No effect
+ * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
+ */
+#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
+#define I2C_MSTCTL_MSTSTOP_MASK (0x4U)
+#define I2C_MSTCTL_MSTSTOP_SHIFT (2U)
+/*! MSTSTOP - Master Stop control(write-only)
+ * 0b0..No effect
+ * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
+ * if the master is receiving data from the slave (in Master Receiver mode).
+ */
+#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
+#define I2C_MSTCTL_MSTDMA_MASK (0x8U)
+#define I2C_MSTCTL_MSTDMA_SHIFT (3U)
+/*! MSTDMA - Master DMA enable
+ * 0b0..Disable. No DMA requests are generated for master operation.
+ * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating
+ * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
+ */
+#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
+/*! @} */
+
+/*! @name MSTTIME - Master Timing Register */
+/*! @{ */
+#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)
+#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)
+/*! MSTSCLLOW - Master SCL Low time
+ * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
+ * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
+ * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
+ * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
+ * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
+ * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
+ * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
+ * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
+ */
+#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
+#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)
+#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)
+/*! MSTSCLHIGH - Master SCL High time
+ * 0b000..2 clocks. Minimum SCL high time is 2 clocks of the I2C clock pre-divider.
+ * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
+ * 0b010..4 clocks. Minimum SCL high time is 4 clocks of the I2C clock pre-divider.
+ * 0b011..5 clocks. Minimum SCL high time is 5 clocks of the I2C clock pre-divider.
+ * 0b100..6 clocks. Minimum SCL high time is 6 clocks of the I2C clock pre-divider.
+ * 0b101..7 clocks. Minimum SCL high time is 7 clocks of the I2C clock pre-divider.
+ * 0b110..8 clocks. Minimum SCL high time is 8 clocks of the I2C clock pre-divider.
+ * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
+ */
+#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
+/*! @} */
+
+/*! @name MSTDAT - Master Data Register */
+/*! @{ */
+#define I2C_MSTDAT_DATA_MASK (0xFFU)
+#define I2C_MSTDAT_DATA_SHIFT (0U)
+/*! DATA - Master function data register
+ */
+#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
+/*! @} */
+
+/*! @name SLVCTL - Slave Control Register */
+/*! @{ */
+#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)
+#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)
+/*! SLVCONTINUE - Slave Continue
+ * 0b0..No effect
+ * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the STAT[SLVPENDING]
+ * flag. This must be done after writing transmit data, reading received data, or any other housekeeping
+ * related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be
+ * set unless SLVPENDING = 1.
+ */
+#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
+#define I2C_SLVCTL_SLVNACK_MASK (0x2U)
+#define I2C_SLVCTL_SLVNACK_SHIFT (1U)
+/*! SLVNACK - Slave NACK
+ * 0b0..No effect
+ * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (in Slave Receiver mode).
+ */
+#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
+#define I2C_SLVCTL_SLVDMA_MASK (0x8U)
+#define I2C_SLVCTL_SLVDMA_SHIFT (3U)
+/*! SLVDMA - Slave DMA enable
+ * 0b0..Disabled. No DMA requests are issued for Slave mode operation.
+ * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception.
+ */
+#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
+#define I2C_SLVCTL_AUTOACK_MASK (0x100U)
+#define I2C_SLVCTL_AUTOACK_SHIFT (8U)
+/*! AUTOACK - Automatic Acknowledge
+ * 0b0..Normal, non-automatic operation. If AUTONACK = 0, then a SlvPending interrupt is generated when a
+ * matching address is received. If AUTONACK = 1, then received addresses are NACKed (ignored).
+ * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately,
+ * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does
+ * not match AUTOMATCHREAD, then the behavior will depend on the SLVADR0[AUTONACK] bit: if AUTONACK is set,
+ * then it will be Nacked; if AUTONACK is clear, then a SlvPending interrupt is generated.
+ */
+#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
+#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U)
+#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U)
+/*! AUTOMATCHREAD - Automatic Match Read
+ * 0b0..In Automatic Mode, the expected next operation is an I2C write.
+ * 0b1..In Automatic Mode, the expected next operation is an I2C read.
+ */
+#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
+/*! @} */
+
+/*! @name SLVDAT - Slave Data Register */
+/*! @{ */
+#define I2C_SLVDAT_DATA_MASK (0xFFU)
+#define I2C_SLVDAT_DATA_SHIFT (0U)
+/*! DATA - Slave function data register
+ */
+#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
+/*! @} */
+
+/*! @name SLVADR - Slave Address Register */
+/*! @{ */
+#define I2C_SLVADR_SADISABLE_MASK (0x1U)
+#define I2C_SLVADR_SADISABLE_SHIFT (0U)
+/*! SADISABLE - Slave Address n Disable
+ * 0b0..Enabled. Slave Address n is enabled.
+ * 0b1..Ignored. Slave Address n is ignored.
+ */
+#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
+#define I2C_SLVADR_SLVADR_MASK (0xFEU)
+#define I2C_SLVADR_SLVADR_SHIFT (1U)
+/*! SLVADR - Slave Address.
+ */
+#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
+#define I2C_SLVADR_AUTONACK_MASK (0x8000U)
+#define I2C_SLVADR_AUTONACK_SHIFT (15U)
+/*! AUTONACK - Automatic NACK operation
+ * 0b0..Normal operation, matching I2C addresses are not ignored.
+ * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, and the address
+ * matches SLVADRn, and AUTOMATCHREAD matches the direction.
+ */
+#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
+/*! @} */
+
+/* The count of I2C_SLVADR */
+#define I2C_SLVADR_COUNT (4U)
+
+/*! @name SLVQUAL0 - Slave Qualification for Address 0 Register */
+/*! @{ */
+#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)
+#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)
+/*! QUALMODE0 - Qualify mode for slave address 0
+ * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
+ * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
+ */
+#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
+#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)
+#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)
+/*! SLVQUAL0 - Slave address Qualifier for address 0
+ */
+#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
+/*! @} */
+
+/*! @name MONRXDAT - Monitor Receiver Data Register */
+/*! @{ */
+#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)
+#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)
+/*! MONRXDAT - Monitor function Receiver Data
+ */
+#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
+#define I2C_MONRXDAT_MONSTART_MASK (0x100U)
+#define I2C_MONRXDAT_MONSTART_SHIFT (8U)
+/*! MONSTART - Monitor Received Start
+ * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.
+ * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.
+ */
+#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
+#define I2C_MONRXDAT_MONRESTART_MASK (0x200U)
+#define I2C_MONRXDAT_MONRESTART_SHIFT (9U)
+/*! MONRESTART - Monitor Received Repeated Start
+ * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
+ * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
+ */
+#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
+#define I2C_MONRXDAT_MONNACK_MASK (0x400U)
+#define I2C_MONRXDAT_MONNACK_SHIFT (10U)
+/*! MONNACK - Monitor Received NACK
+ * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
+ * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
+ */
+#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
+/*! @} */
+
+/*! @name ID - Peripheral Identification Register */
+/*! @{ */
+#define I2C_ID_APERTURE_MASK (0xFFU)
+#define I2C_ID_APERTURE_SHIFT (0U)
+/*! APERTURE - Aperture
+ */
+#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
+#define I2C_ID_MINOR_REV_MASK (0xF00U)
+#define I2C_ID_MINOR_REV_SHIFT (8U)
+/*! MINOR_REV - Minor revision of module implementation
+ */
+#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
+#define I2C_ID_MAJOR_REV_MASK (0xF000U)
+#define I2C_ID_MAJOR_REV_SHIFT (12U)
+/*! MAJOR_REV - Major revision of module implementation
+ */
+#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
+#define I2C_ID_ID_MASK (0xFFFF0000U)
+#define I2C_ID_ID_SHIFT (16U)
+/*! ID - Module identifier for the selected function
+ */
+#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral I2C0 base address */
+ #define I2C0_BASE (0x50106000u)
+ /** Peripheral I2C0 base address */
+ #define I2C0_BASE_NS (0x40106000u)
+ /** Peripheral I2C0 base pointer */
+ #define I2C0 ((I2C_Type *)I2C0_BASE)
+ /** Peripheral I2C0 base pointer */
+ #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS)
+ /** Peripheral I2C1 base address */
+ #define I2C1_BASE (0x50107000u)
+ /** Peripheral I2C1 base address */
+ #define I2C1_BASE_NS (0x40107000u)
+ /** Peripheral I2C1 base pointer */
+ #define I2C1 ((I2C_Type *)I2C1_BASE)
+ /** Peripheral I2C1 base pointer */
+ #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS)
+ /** Peripheral I2C2 base address */
+ #define I2C2_BASE (0x50108000u)
+ /** Peripheral I2C2 base address */
+ #define I2C2_BASE_NS (0x40108000u)
+ /** Peripheral I2C2 base pointer */
+ #define I2C2 ((I2C_Type *)I2C2_BASE)
+ /** Peripheral I2C2 base pointer */
+ #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS)
+ /** Peripheral I2C3 base address */
+ #define I2C3_BASE (0x50109000u)
+ /** Peripheral I2C3 base address */
+ #define I2C3_BASE_NS (0x40109000u)
+ /** Peripheral I2C3 base pointer */
+ #define I2C3 ((I2C_Type *)I2C3_BASE)
+ /** Peripheral I2C3 base pointer */
+ #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS)
+ /** Peripheral I2C4 base address */
+ #define I2C4_BASE (0x50122000u)
+ /** Peripheral I2C4 base address */
+ #define I2C4_BASE_NS (0x40122000u)
+ /** Peripheral I2C4 base pointer */
+ #define I2C4 ((I2C_Type *)I2C4_BASE)
+ /** Peripheral I2C4 base pointer */
+ #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS)
+ /** Peripheral I2C5 base address */
+ #define I2C5_BASE (0x50123000u)
+ /** Peripheral I2C5 base address */
+ #define I2C5_BASE_NS (0x40123000u)
+ /** Peripheral I2C5 base pointer */
+ #define I2C5 ((I2C_Type *)I2C5_BASE)
+ /** Peripheral I2C5 base pointer */
+ #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS)
+ /** Peripheral I2C6 base address */
+ #define I2C6_BASE (0x50124000u)
+ /** Peripheral I2C6 base address */
+ #define I2C6_BASE_NS (0x40124000u)
+ /** Peripheral I2C6 base pointer */
+ #define I2C6 ((I2C_Type *)I2C6_BASE)
+ /** Peripheral I2C6 base pointer */
+ #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS)
+ /** Peripheral I2C7 base address */
+ #define I2C7_BASE (0x50125000u)
+ /** Peripheral I2C7 base address */
+ #define I2C7_BASE_NS (0x40125000u)
+ /** Peripheral I2C7 base pointer */
+ #define I2C7 ((I2C_Type *)I2C7_BASE)
+ /** Peripheral I2C7 base pointer */
+ #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS)
+ /** Peripheral I2C8 base address */
+ #define I2C8_BASE (0x50209000u)
+ /** Peripheral I2C8 base address */
+ #define I2C8_BASE_NS (0x40209000u)
+ /** Peripheral I2C8 base pointer */
+ #define I2C8 ((I2C_Type *)I2C8_BASE)
+ /** Peripheral I2C8 base pointer */
+ #define I2C8_NS ((I2C_Type *)I2C8_BASE_NS)
+ /** Peripheral I2C9 base address */
+ #define I2C9_BASE (0x5020A000u)
+ /** Peripheral I2C9 base address */
+ #define I2C9_BASE_NS (0x4020A000u)
+ /** Peripheral I2C9 base pointer */
+ #define I2C9 ((I2C_Type *)I2C9_BASE)
+ /** Peripheral I2C9 base pointer */
+ #define I2C9_NS ((I2C_Type *)I2C9_BASE_NS)
+ /** Peripheral I2C10 base address */
+ #define I2C10_BASE (0x5020B000u)
+ /** Peripheral I2C10 base address */
+ #define I2C10_BASE_NS (0x4020B000u)
+ /** Peripheral I2C10 base pointer */
+ #define I2C10 ((I2C_Type *)I2C10_BASE)
+ /** Peripheral I2C10 base pointer */
+ #define I2C10_NS ((I2C_Type *)I2C10_BASE_NS)
+ /** Peripheral I2C11 base address */
+ #define I2C11_BASE (0x5020C000u)
+ /** Peripheral I2C11 base address */
+ #define I2C11_BASE_NS (0x4020C000u)
+ /** Peripheral I2C11 base pointer */
+ #define I2C11 ((I2C_Type *)I2C11_BASE)
+ /** Peripheral I2C11 base pointer */
+ #define I2C11_NS ((I2C_Type *)I2C11_BASE_NS)
+ /** Peripheral I2C12 base address */
+ #define I2C12_BASE (0x5020D000u)
+ /** Peripheral I2C12 base address */
+ #define I2C12_BASE_NS (0x4020D000u)
+ /** Peripheral I2C12 base pointer */
+ #define I2C12 ((I2C_Type *)I2C12_BASE)
+ /** Peripheral I2C12 base pointer */
+ #define I2C12_NS ((I2C_Type *)I2C12_BASE_NS)
+ /** Peripheral I2C13 base address */
+ #define I2C13_BASE (0x5020E000u)
+ /** Peripheral I2C13 base address */
+ #define I2C13_BASE_NS (0x4020E000u)
+ /** Peripheral I2C13 base pointer */
+ #define I2C13 ((I2C_Type *)I2C13_BASE)
+ /** Peripheral I2C13 base pointer */
+ #define I2C13_NS ((I2C_Type *)I2C13_BASE_NS)
+ /** Peripheral I2C15 base address */
+ #define I2C15_BASE (0x50127000u)
+ /** Peripheral I2C15 base address */
+ #define I2C15_BASE_NS (0x40127000u)
+ /** Peripheral I2C15 base pointer */
+ #define I2C15 ((I2C_Type *)I2C15_BASE)
+ /** Peripheral I2C15 base pointer */
+ #define I2C15_NS ((I2C_Type *)I2C15_BASE_NS)
+ /** Array initializer of I2C peripheral base addresses */
+ #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE, I2C10_BASE, I2C11_BASE, I2C12_BASE, I2C13_BASE, I2C15_BASE }
+ /** Array initializer of I2C peripheral base pointers */
+ #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I2C10, I2C11, I2C12, I2C13, I2C15 }
+ /** Array initializer of I2C peripheral base addresses */
+ #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS, I2C8_BASE_NS, I2C9_BASE_NS, I2C10_BASE_NS, I2C11_BASE_NS, I2C12_BASE_NS, I2C13_BASE_NS, I2C15_BASE_NS }
+ /** Array initializer of I2C peripheral base pointers */
+ #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS, I2C8_NS, I2C9_NS, I2C10_NS, I2C11_NS, I2C12_NS, I2C13_NS, I2C15_NS }
+#else
+ /** Peripheral I2C0 base address */
+ #define I2C0_BASE (0x40106000u)
+ /** Peripheral I2C0 base pointer */
+ #define I2C0 ((I2C_Type *)I2C0_BASE)
+ /** Peripheral I2C1 base address */
+ #define I2C1_BASE (0x40107000u)
+ /** Peripheral I2C1 base pointer */
+ #define I2C1 ((I2C_Type *)I2C1_BASE)
+ /** Peripheral I2C2 base address */
+ #define I2C2_BASE (0x40108000u)
+ /** Peripheral I2C2 base pointer */
+ #define I2C2 ((I2C_Type *)I2C2_BASE)
+ /** Peripheral I2C3 base address */
+ #define I2C3_BASE (0x40109000u)
+ /** Peripheral I2C3 base pointer */
+ #define I2C3 ((I2C_Type *)I2C3_BASE)
+ /** Peripheral I2C4 base address */
+ #define I2C4_BASE (0x40122000u)
+ /** Peripheral I2C4 base pointer */
+ #define I2C4 ((I2C_Type *)I2C4_BASE)
+ /** Peripheral I2C5 base address */
+ #define I2C5_BASE (0x40123000u)
+ /** Peripheral I2C5 base pointer */
+ #define I2C5 ((I2C_Type *)I2C5_BASE)
+ /** Peripheral I2C6 base address */
+ #define I2C6_BASE (0x40124000u)
+ /** Peripheral I2C6 base pointer */
+ #define I2C6 ((I2C_Type *)I2C6_BASE)
+ /** Peripheral I2C7 base address */
+ #define I2C7_BASE (0x40125000u)
+ /** Peripheral I2C7 base pointer */
+ #define I2C7 ((I2C_Type *)I2C7_BASE)
+ /** Peripheral I2C8 base address */
+ #define I2C8_BASE (0x40209000u)
+ /** Peripheral I2C8 base pointer */
+ #define I2C8 ((I2C_Type *)I2C8_BASE)
+ /** Peripheral I2C9 base address */
+ #define I2C9_BASE (0x4020A000u)
+ /** Peripheral I2C9 base pointer */
+ #define I2C9 ((I2C_Type *)I2C9_BASE)
+ /** Peripheral I2C10 base address */
+ #define I2C10_BASE (0x4020B000u)
+ /** Peripheral I2C10 base pointer */
+ #define I2C10 ((I2C_Type *)I2C10_BASE)
+ /** Peripheral I2C11 base address */
+ #define I2C11_BASE (0x4020C000u)
+ /** Peripheral I2C11 base pointer */
+ #define I2C11 ((I2C_Type *)I2C11_BASE)
+ /** Peripheral I2C12 base address */
+ #define I2C12_BASE (0x4020D000u)
+ /** Peripheral I2C12 base pointer */
+ #define I2C12 ((I2C_Type *)I2C12_BASE)
+ /** Peripheral I2C13 base address */
+ #define I2C13_BASE (0x4020E000u)
+ /** Peripheral I2C13 base pointer */
+ #define I2C13 ((I2C_Type *)I2C13_BASE)
+ /** Peripheral I2C15 base address */
+ #define I2C15_BASE (0x40127000u)
+ /** Peripheral I2C15 base pointer */
+ #define I2C15 ((I2C_Type *)I2C15_BASE)
+ /** Array initializer of I2C peripheral base addresses */
+ #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE, I2C10_BASE, I2C11_BASE, I2C12_BASE, I2C13_BASE, I2C15_BASE }
+ /** Array initializer of I2C peripheral base pointers */
+ #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I2C10, I2C11, I2C12, I2C13, I2C15 }
+#endif
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn, FLEXCOMM11_IRQn, FLEXCOMM12_IRQn, FLEXCOMM13_IRQn, FLEXCOMM15_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[3072];
+ __IO uint32_t CFG1; /**< Configuration Register 1 for the Primary Channel Pair, offset: 0xC00 */
+ __IO uint32_t CFG2; /**< Configuration Register 2 for the Primary Channel Pair, offset: 0xC04 */
+ __IO uint32_t STAT; /**< Status Register for the Primary Channel Pair, offset: 0xC08 */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t DIV; /**< Clock Divider, offset: 0xC1C */
+ struct { /* offset: 0xC20, array step: 0x20 */
+ __IO uint32_t PCFG1; /**< Configuration Register 1 for Channel Pair 1..Configuration Register 1 for Channel Pair 3, array offset: 0xC20, array step: 0x20 */
+ __IO uint32_t PCFG2; /**< Configuration Register 2 for Channel Pair 1..Configuration Register 2 for Channel Pair 3, array offset: 0xC24, array step: 0x20 */
+ __I uint32_t PSTAT; /**< Status Register for Channel Pair 1..Status Register for Channel Pair 3, array offset: 0xC28, array step: 0x20 */
+ uint8_t RESERVED_0[20];
+ } SECCHANNEL[3];
+ uint8_t RESERVED_2[384];
+ __IO uint32_t FIFOCFG; /**< FIFO Configuration and Enable, offset: 0xE00 */
+ __IO uint32_t FIFOSTAT; /**< FIFO Status, offset: 0xE04 */
+ __IO uint32_t FIFOTRIG; /**< FIFO Trigger Settings, offset: 0xE08 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t FIFOINTENSET; /**< FIFO Interrupt Enable Set and Read, offset: 0xE10 */
+ __IO uint32_t FIFOINTENCLR; /**< FIFO Interrupt Enable Clear and Read, offset: 0xE14 */
+ __I uint32_t FIFOINTSTAT; /**< FIFO Interrupt Status, offset: 0xE18 */
+ uint8_t RESERVED_4[4];
+ __O uint32_t FIFOWR; /**< FIFO Write Data, offset: 0xE20 */
+ __O uint32_t FIFOWR48H; /**< FIFO Write Data for Upper Data Bits, offset: 0xE24 */
+ uint8_t RESERVED_5[8];
+ __I uint32_t FIFORD; /**< FIFO Read Data, offset: 0xE30 */
+ __I uint32_t FIFORD48H; /**< FIFO Read Data for Upper Data Bits, offset: 0xE34 */
+ uint8_t RESERVED_6[8];
+ __I uint32_t FIFORDNOPOP; /**< FIFO Data Read with No FIFO Pop, offset: 0xE40 */
+ __I uint32_t FIFORD48HNOPOP; /**< FIFO Data Read for Upper Data Bits with No FIFO Pop, offset: 0xE44 */
+ __I uint32_t FIFOSIZE; /**< FIFO Size Register, offset: 0xE48 */
+ uint8_t RESERVED_7[432];
+ __I uint32_t ID; /**< I2S Module Identification, offset: 0xFFC */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name CFG1 - Configuration Register 1 for the Primary Channel Pair */
+/*! @{ */
+#define I2S_CFG1_MAINENABLE_MASK (0x1U)
+#define I2S_CFG1_MAINENABLE_SHIFT (0U)
+/*! MAINENABLE - Main Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
+#define I2S_CFG1_DATAPAUSE_MASK (0x2U)
+#define I2S_CFG1_DATAPAUSE_SHIFT (1U)
+/*! DATAPAUSE - Data Flow Pause
+ * 0b0..Normal operation
+ * 0b1..Pause
+ */
+#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
+#define I2S_CFG1_PAIRCOUNT_MASK (0xCU)
+#define I2S_CFG1_PAIRCOUNT_SHIFT (2U)
+/*! PAIRCOUNT - Pair Count
+ * 0b00..One Pair
+ * 0b01..Two Pairs
+ * 0b10..Three Pairs
+ * 0b11..Four Pairs
+ */
+#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
+#define I2S_CFG1_MSTSLVCFG_MASK (0x30U)
+#define I2S_CFG1_MSTSLVCFG_SHIFT (4U)
+/*! MSTSLVCFG - Master/Slave Configuration Selection
+ * 0b00..Normal Slave Mode
+ * 0b01..WS Synchronized Master Mode
+ * 0b10..Master Using an Existing SCK Mode
+ * 0b11..Normal Master Mode
+ */
+#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
+#define I2S_CFG1_MODE_MASK (0xC0U)
+#define I2S_CFG1_MODE_SHIFT (6U)
+/*! MODE - Mode
+ * 0b00..Classic Mode
+ * 0b01..DSP mode WS 50% duty cycle
+ * 0b10..DSP mode WS 1 clock
+ * 0b11..DSP mode WS 1 data
+ */
+#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
+#define I2S_CFG1_RIGHTLOW_MASK (0x100U)
+#define I2S_CFG1_RIGHTLOW_SHIFT (8U)
+/*! RIGHTLOW - Right Channel Low
+ * 0b0..Right high
+ * 0b1..Right low
+ */
+#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
+#define I2S_CFG1_LEFTJUST_MASK (0x200U)
+#define I2S_CFG1_LEFTJUST_SHIFT (9U)
+/*! LEFTJUST - Left-Justify Data
+ * 0b0..Right-justified
+ * 0b1..Left-justified
+ */
+#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
+#define I2S_CFG1_ONECHANNEL_MASK (0x400U)
+#define I2S_CFG1_ONECHANNEL_SHIFT (10U)
+/*! ONECHANNEL - Single Channel Mode
+ * 0b0..Dual channel
+ * 0b1..Single channel
+ */
+#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
+#define I2S_CFG1_PDMDATA_MASK (0x800U)
+#define I2S_CFG1_PDMDATA_SHIFT (11U)
+/*! PDMDATA - PDM Data Selection
+ * 0b0..Normal Operation
+ * 0b1..DMIC subsystem
+ */
+#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)
+#define I2S_CFG1_SCK_POL_MASK (0x1000U)
+#define I2S_CFG1_SCK_POL_SHIFT (12U)
+/*! SCK_POL - SCK Polarity
+ * 0b0..Falling edge
+ * 0b1..Rising edge
+ */
+#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
+#define I2S_CFG1_WS_POL_MASK (0x2000U)
+#define I2S_CFG1_WS_POL_SHIFT (13U)
+/*! WS_POL - WS Polarity
+ * 0b0..Not inverted
+ * 0b1..Inverted. The WS signal is inverted.
+ */
+#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
+#define I2S_CFG1_DATALEN_MASK (0x1F0000U)
+#define I2S_CFG1_DATALEN_SHIFT (16U)
+/*! DATALEN - Data Length
+ * 0b00011..Data is 4 bits in length.
+ * 0b00100..Data is 5 bits in length.
+ * 0b00111..Data is 8 bits in length.
+ * 0b11110..Data is 31 bits in length.
+ * 0b11111..Data is 32 bits in length.
+ */
+#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
+/*! @} */
+
+/*! @name CFG2 - Configuration Register 2 for the Primary Channel Pair */
+/*! @{ */
+#define I2S_CFG2_FRAMELEN_MASK (0x7FFU)
+#define I2S_CFG2_FRAMELEN_SHIFT (0U)
+/*! FRAMELEN - Frame Length
+ * 0b00000000011..Frame is 4 bits in total length
+ * 0b00000000100..Frame is 5 bits in total length
+ * 0b00111111111..Frame is 512 bits in total length
+ * 0b11111111111..Frame is 2048 bits in total length
+ */
+#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
+#define I2S_CFG2_POSITION_MASK (0x7FF0000U)
+#define I2S_CFG2_POSITION_SHIFT (16U)
+/*! POSITION - Data Position
+ * 0b00000000000..Data begins at bit position 0 (the first bit position) within the frame or WS phase
+ * 0b00000000001..Data begins at bit position 1 within the frame or WS phase
+ * 0b00000000010..Data begins at bit position 2 within the frame or WS phase
+ */
+#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
+/*! @} */
+
+/*! @name STAT - Status Register for the Primary Channel Pair */
+/*! @{ */
+#define I2S_STAT_BUSY_MASK (0x1U)
+#define I2S_STAT_BUSY_SHIFT (0U)
+/*! BUSY - Busy Status
+ * 0b0..Idle
+ * 0b1..Busy
+ */
+#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
+#define I2S_STAT_SLVFRMERR_MASK (0x2U)
+#define I2S_STAT_SLVFRMERR_SHIFT (1U)
+/*! SLVFRMERR - Slave Frame Error
+ * 0b0..No error
+ * 0b1..Error
+ */
+#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
+#define I2S_STAT_LR_MASK (0x4U)
+#define I2S_STAT_LR_SHIFT (2U)
+/*! LR - Left/Right Indication
+ * 0b0..Left channel
+ * 0b1..Right channel
+ */
+#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
+#define I2S_STAT_DATAPAUSED_MASK (0x8U)
+#define I2S_STAT_DATAPAUSED_SHIFT (3U)
+/*! DATAPAUSED - Data Paused
+ * 0b0..Not Paused
+ * 0b1..Paused
+ */
+#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
+/*! @} */
+
+/*! @name DIV - Clock Divider */
+/*! @{ */
+#define I2S_DIV_DIV_MASK (0xFFFU)
+#define I2S_DIV_DIV_SHIFT (0U)
+/*! DIV - Divider
+ * 0b000000000000..FCLK is used directly.
+ * 0b000000000001..FCLK is divided by 2.
+ * 0b000000000010..FCLK is divided by 3.
+ * 0b111111111111..FCLK is divided by 4,096.
+ */
+#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
+/*! @} */
+
+/*! @name SECCHANNEL_PCFG1 - Configuration Register 1 for Channel Pair 1..Configuration Register 1 for Channel Pair 3 */
+/*! @{ */
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U)
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U)
+/*! PAIRENABLE - Pair Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U)
+/*! ONECHANNEL - Single Channel Mode
+ * 0b0..Dual Channel
+ * 0b1..Single Channel
+ */
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK)
+/*! @} */
+
+/* The count of I2S_SECCHANNEL_PCFG1 */
+#define I2S_SECCHANNEL_PCFG1_COUNT (3U)
+
+/*! @name SECCHANNEL_PCFG2 - Configuration Register 2 for Channel Pair 1..Configuration Register 2 for Channel Pair 3 */
+/*! @{ */
+#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U)
+#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U)
+/*! POSITION - Data Position
+ */
+#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK)
+/*! @} */
+
+/* The count of I2S_SECCHANNEL_PCFG2 */
+#define I2S_SECCHANNEL_PCFG2_COUNT (3U)
+
+/*! @name SECCHANNEL_PSTAT - Status Register for Channel Pair 1..Status Register for Channel Pair 3 */
+/*! @{ */
+#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U)
+#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U)
+/*! BUSY - Busy Status for Channel Pair
+ * 0b0..Idle. The transmitter/receiver for this channel pair is currently idle.
+ * 0b1..Busy. The transmitter/receiver for this channel pair is currently processing data.
+ */
+#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U)
+/*! SLVFRMERR - Save Frame Error Flag
+ * 0b0..No Error
+ * 0b1..Error
+ */
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK)
+#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U)
+#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U)
+/*! LR - Left/Right Indication
+ * 0b0..Left channel
+ * 0b1..Right channel
+ */
+#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U)
+/*! DATAPAUSED - Data Paused Status Flag
+ * 0b0..Data Not Paused. Data is not currently paused. A data pause may have been requested but is not yet in
+ * force, waiting for an allowed pause point. Refer to the description in CFG1[DATAPAUSE].
+ * 0b1..Data Paused. A data pause has been requested and is now in force.
+ */
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK)
+/*! @} */
+
+/* The count of I2S_SECCHANNEL_PSTAT */
+#define I2S_SECCHANNEL_PSTAT_COUNT (3U)
+
+/*! @name FIFOCFG - FIFO Configuration and Enable */
+/*! @{ */
+#define I2S_FIFOCFG_ENABLETX_MASK (0x1U)
+#define I2S_FIFOCFG_ENABLETX_SHIFT (0U)
+/*! ENABLETX - Enable Transmit FIFO
+ * 0b0..Disabled Transmit. The transmit FIFO is not enabled.
+ * 0b1..Enabled transmit. The transmit FIFO is enabled.
+ */
+#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
+#define I2S_FIFOCFG_ENABLERX_MASK (0x2U)
+#define I2S_FIFOCFG_ENABLERX_SHIFT (1U)
+/*! ENABLERX - Enable Receive FIFO
+ * 0b0..Disabled. The receive FIFO is not enabled.
+ * 0b1..Enabled. The receive FIFO is enabled.
+ */
+#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
+#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U)
+#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U)
+/*! TXI2SE0 - Transmit I2S Empty 0
+ * 0b0..Last value
+ * 0b1..Zero
+ */
+#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
+#define I2S_FIFOCFG_PACK48_MASK (0x8U)
+#define I2S_FIFOCFG_PACK48_SHIFT (3U)
+/*! PACK48 - Packing Format 48-bit data
+ * 0b0..Bits_24
+ * 0b1..Bits_32_16
+ */
+#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
+#define I2S_FIFOCFG_SIZE_MASK (0x30U)
+#define I2S_FIFOCFG_SIZE_SHIFT (4U)
+/*! SIZE - FIFO Size Configuration
+ * 0b10..Size 32 Bits
+ * 0b11..Size 48 Bits
+ */
+#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
+#define I2S_FIFOCFG_DMATX_MASK (0x1000U)
+#define I2S_FIFOCFG_DMATX_SHIFT (12U)
+/*! DMATX - DMA Transmit
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
+#define I2S_FIFOCFG_DMARX_MASK (0x2000U)
+#define I2S_FIFOCFG_DMARX_SHIFT (13U)
+/*! DMARX - DMA Receive
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
+#define I2S_FIFOCFG_WAKETX_MASK (0x4000U)
+#define I2S_FIFOCFG_WAKETX_SHIFT (14U)
+/*! WAKETX - Wake-up for Transmit FIFO Level
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
+#define I2S_FIFOCFG_WAKERX_MASK (0x8000U)
+#define I2S_FIFOCFG_WAKERX_SHIFT (15U)
+/*! WAKERX - Wake-up for Receive FIFO Level
+ * 0b0..Only enabled interrupts wake up the device from reduced power modes.
+ * 0b1..A device wake-up for DMA occurs if the receive FIFO level reaches the value specified by FIFOTRIG[RXLVL],
+ * even when the RXLVL interrupt is not enabled.
+ */
+#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
+#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U)
+#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U)
+/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
+ */
+#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
+#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U)
+#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U)
+/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
+ */
+#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
+#define I2S_FIFOCFG_POPDBG_MASK (0x40000U)
+#define I2S_FIFOCFG_POPDBG_SHIFT (18U)
+/*! POPDBG - Pop FIFO for Debug Reads
+ * 0b0..Debug reads of the FIFO do not pop the FIFO.
+ * 0b1..A debug read causes the FIFO to pop.
+ */
+#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK)
+/*! @} */
+
+/*! @name FIFOSTAT - FIFO Status */
+/*! @{ */
+#define I2S_FIFOSTAT_TXERR_MASK (0x1U)
+#define I2S_FIFOSTAT_TXERR_SHIFT (0U)
+/*! TXERR - TX FIFO Error
+ * 0b0..No transmit FIFO error occured
+ * 0b1..Transmit FIFO error occured
+ */
+#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
+#define I2S_FIFOSTAT_RXERR_MASK (0x2U)
+#define I2S_FIFOSTAT_RXERR_SHIFT (1U)
+/*! RXERR - RX FIFO Error
+ * 0b0..No receive FIFO error occured
+ * 0b1..Receive FIFO error occured
+ */
+#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
+#define I2S_FIFOSTAT_PERINT_MASK (0x8U)
+#define I2S_FIFOSTAT_PERINT_SHIFT (3U)
+/*! PERINT - Peripheral Interrupt
+ * 0b0..No interrupt
+ * 0b1..Interrupt
+ */
+#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
+#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U)
+#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U)
+/*! TXEMPTY - Transmit FIFO Empty
+ * 0b0..Transmit FIFO is not empty
+ * 0b1..Transmit FIFO is empty; however, the peripheral may still be processing the last piece of data.
+ */
+#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
+#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U)
+#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U)
+/*! TXNOTFULL - Transmit FIFO Not Full
+ * 0b0..Transmit FIFO is full, and another write would cause an overflow
+ * 0b1..Transmit FIFO is not full, so more data can be written
+ */
+#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
+#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
+#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
+/*! RXNOTEMPTY - Receive FIFO Not Empty
+ * 0b0..Receive FIFO is empty
+ * 0b1..Receive FIFO is not empty, so data can be read.
+ */
+#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
+#define I2S_FIFOSTAT_RXFULL_MASK (0x80U)
+#define I2S_FIFOSTAT_RXFULL_SHIFT (7U)
+/*! RXFULL - Receive FIFO Full
+ * 0b0..Receive FIFO is not full
+ * 0b1..Receive FIFO is full
+ */
+#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
+#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U)
+#define I2S_FIFOSTAT_TXLVL_SHIFT (8U)
+/*! TXLVL - Transmit FIFO Current Level
+ * 0b00000..TX FIFO is empty
+ */
+#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
+#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U)
+#define I2S_FIFOSTAT_RXLVL_SHIFT (16U)
+/*! RXLVL - Receive FIFO Current Level
+ * 0b00000..RX FIFO is empty
+ */
+#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOTRIG - FIFO Trigger Settings */
+/*! @{ */
+#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U)
+#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U)
+/*! TXLVLENA - Transmit FIFO Level Trigger Enable
+ * 0b0..Transmit FIFO level does not generate a FIFO level trigger.
+ * 0b1..An trigger generates if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
+ */
+#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
+#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U)
+#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U)
+/*! RXLVLENA - Receive FIFO Level Trigger Enable
+ * 0b0..Receive FIFO level does not generate a FIFO level trigger.
+ * 0b1..An trigger generates if the receive FIFO level reaches the value specified by the RXLVL.
+ */
+#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
+#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U)
+#define I2S_FIFOTRIG_TXLVL_SHIFT (8U)
+/*! TXLVL - Transmit FIFO Level Trigger Point
+ * 0b0000..Trigger when the TX FIFO becomes empty.
+ * 0b0001..Trigger when the TX FIFO level decreases to one entry.
+ * 0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full).
+ */
+#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
+#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U)
+#define I2S_FIFOTRIG_RXLVL_SHIFT (16U)
+/*! RXLVL - Receive FIFO Level Trigger Point
+ * 0b0000..Trigger when the RX FIFO has received 1 entry (the FIFO is no longer empty).
+ * 0b0001..Trigger when the RX FIFO has received 2 entries.
+ * 0b1111..Trigger when the RX FIFO has received 16 entries (the FIFO has become full).
+ */
+#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENSET - FIFO Interrupt Enable Set and Read */
+/*! @{ */
+#define I2S_FIFOINTENSET_TXERR_MASK (0x1U)
+#define I2S_FIFOINTENSET_TXERR_SHIFT (0U)
+/*! TXERR - Transmit Error Interrupt
+ * 0b0..Disabled. No interrupt generates for a transmit error.
+ * 0b1..Enabled. An interrupt generates when a transmit error occurs.
+ */
+#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
+#define I2S_FIFOINTENSET_RXERR_MASK (0x2U)
+#define I2S_FIFOINTENSET_RXERR_SHIFT (1U)
+/*! RXERR - Receive Error Interrupt
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
+#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U)
+#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U)
+/*! TXLVL - Transmit Level Interrupt
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
+#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U)
+#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U)
+/*! RXLVL - Receive Level Interrupt
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear and Read */
+/*! @{ */
+#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U)
+#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U)
+/*! TXERR - Transmit Error Interrupt Clear
+ * 0b0..Interrupt is not cleared.
+ * 0b1..Interrupt is cleared.
+ */
+#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
+#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U)
+#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U)
+/*! RXERR - Receive Error Interrupt Clear
+ * 0b0..Interrupt is not cleared.
+ * 0b1..Interrupt is cleared.
+ */
+#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
+#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U)
+#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U)
+/*! TXLVL - Transmit Level Interrupt Clear
+ * 0b0..Interrupt is not cleared.
+ * 0b1..Interrupt is cleared.
+ */
+#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
+#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U)
+#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U)
+/*! RXLVL - Receive Level Interrupt Clear
+ * 0b0..Interrupt is not cleared.
+ * 0b1..Interrupt is cleared.
+ */
+#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTSTAT - FIFO Interrupt Status */
+/*! @{ */
+#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U)
+#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U)
+/*! TXERR - TX FIFO Error Interrupt Status
+ * 0b0..Not pending
+ * 0b1..Pending
+ */
+#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
+#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U)
+#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U)
+/*! RXERR - RX FIFO Error Interrupt Status
+ * 0b0..Not pending
+ * 0b1..Pending
+ */
+#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
+#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U)
+#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U)
+/*! TXLVL - Transmit FIFO Level Interrupt Status
+ * 0b0..Not pending
+ * 0b1..Pending
+ */
+#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
+#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U)
+#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U)
+/*! RXLVL - Receive FIFO Level Interrupt Status
+ * 0b0..Not pending
+ * 0b1..Pending
+ */
+#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
+#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U)
+#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U)
+/*! PERINT - Peripheral Interrupt Status
+ * 0b0..Not pending
+ * 0b1..Pending
+ */
+#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
+/*! @} */
+
+/*! @name FIFOWR - FIFO Write Data */
+/*! @{ */
+#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU)
+#define I2S_FIFOWR_TXDATA_SHIFT (0U)
+/*! TXDATA - Transmit Data to the FIFO
+ */
+#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
+/*! @} */
+
+/*! @name FIFOWR48H - FIFO Write Data for Upper Data Bits */
+/*! @{ */
+#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU)
+#define I2S_FIFOWR48H_TXDATA_SHIFT (0U)
+/*! TXDATA - Transmit Data to the FIFO
+ */
+#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD - FIFO Read Data */
+/*! @{ */
+#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU)
+#define I2S_FIFORD_RXDATA_SHIFT (0U)
+/*! RXDATA - Received Data from the FIFO
+ */
+#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD48H - FIFO Read Data for Upper Data Bits */
+/*! @{ */
+#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU)
+#define I2S_FIFORD48H_RXDATA_SHIFT (0U)
+/*! RXDATA - Received Data from the FIFO
+ */
+#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORDNOPOP - FIFO Data Read with No FIFO Pop */
+/*! @{ */
+#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU)
+#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U)
+/*! RXDATA - Received Data from the FIFO
+ */
+#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD48HNOPOP - FIFO Data Read for Upper Data Bits with No FIFO Pop */
+/*! @{ */
+#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU)
+#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U)
+/*! RXDATA - Received Data from the FIFO
+ */
+#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
+/*! @} */
+
+/*! @name FIFOSIZE - FIFO Size Register */
+/*! @{ */
+#define I2S_FIFOSIZE_FIFOSIZE_MASK (0x1FU)
+#define I2S_FIFOSIZE_FIFOSIZE_SHIFT (0U)
+#define I2S_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK)
+/*! @} */
+
+/*! @name ID - I2S Module Identification */
+/*! @{ */
+#define I2S_ID_APERTURE_MASK (0xFFU)
+#define I2S_ID_APERTURE_SHIFT (0U)
+/*! APERTURE - Aperture
+ */
+#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK)
+#define I2S_ID_MINOR_REV_MASK (0xF00U)
+#define I2S_ID_MINOR_REV_SHIFT (8U)
+/*! MINOR_REV - Minor Revision
+ */
+#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK)
+#define I2S_ID_MAJOR_REV_MASK (0xF000U)
+#define I2S_ID_MAJOR_REV_SHIFT (12U)
+/*! MAJOR_REV - Major Revision
+ */
+#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK)
+#define I2S_ID_ID_MASK (0xFFFF0000U)
+#define I2S_ID_ID_SHIFT (16U)
+/*! ID - Module Identifier
+ */
+#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral I2S0 base address */
+ #define I2S0_BASE (0x50106000u)
+ /** Peripheral I2S0 base address */
+ #define I2S0_BASE_NS (0x40106000u)
+ /** Peripheral I2S0 base pointer */
+ #define I2S0 ((I2S_Type *)I2S0_BASE)
+ /** Peripheral I2S0 base pointer */
+ #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS)
+ /** Peripheral I2S1 base address */
+ #define I2S1_BASE (0x50107000u)
+ /** Peripheral I2S1 base address */
+ #define I2S1_BASE_NS (0x40107000u)
+ /** Peripheral I2S1 base pointer */
+ #define I2S1 ((I2S_Type *)I2S1_BASE)
+ /** Peripheral I2S1 base pointer */
+ #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS)
+ /** Peripheral I2S2 base address */
+ #define I2S2_BASE (0x50108000u)
+ /** Peripheral I2S2 base address */
+ #define I2S2_BASE_NS (0x40108000u)
+ /** Peripheral I2S2 base pointer */
+ #define I2S2 ((I2S_Type *)I2S2_BASE)
+ /** Peripheral I2S2 base pointer */
+ #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS)
+ /** Peripheral I2S3 base address */
+ #define I2S3_BASE (0x50109000u)
+ /** Peripheral I2S3 base address */
+ #define I2S3_BASE_NS (0x40109000u)
+ /** Peripheral I2S3 base pointer */
+ #define I2S3 ((I2S_Type *)I2S3_BASE)
+ /** Peripheral I2S3 base pointer */
+ #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS)
+ /** Peripheral I2S4 base address */
+ #define I2S4_BASE (0x50122000u)
+ /** Peripheral I2S4 base address */
+ #define I2S4_BASE_NS (0x40122000u)
+ /** Peripheral I2S4 base pointer */
+ #define I2S4 ((I2S_Type *)I2S4_BASE)
+ /** Peripheral I2S4 base pointer */
+ #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS)
+ /** Peripheral I2S5 base address */
+ #define I2S5_BASE (0x50123000u)
+ /** Peripheral I2S5 base address */
+ #define I2S5_BASE_NS (0x40123000u)
+ /** Peripheral I2S5 base pointer */
+ #define I2S5 ((I2S_Type *)I2S5_BASE)
+ /** Peripheral I2S5 base pointer */
+ #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS)
+ /** Peripheral I2S6 base address */
+ #define I2S6_BASE (0x50124000u)
+ /** Peripheral I2S6 base address */
+ #define I2S6_BASE_NS (0x40124000u)
+ /** Peripheral I2S6 base pointer */
+ #define I2S6 ((I2S_Type *)I2S6_BASE)
+ /** Peripheral I2S6 base pointer */
+ #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS)
+ /** Peripheral I2S7 base address */
+ #define I2S7_BASE (0x50125000u)
+ /** Peripheral I2S7 base address */
+ #define I2S7_BASE_NS (0x40125000u)
+ /** Peripheral I2S7 base pointer */
+ #define I2S7 ((I2S_Type *)I2S7_BASE)
+ /** Peripheral I2S7 base pointer */
+ #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS)
+ /** Peripheral I2S8 base address */
+ #define I2S8_BASE (0x50209000u)
+ /** Peripheral I2S8 base address */
+ #define I2S8_BASE_NS (0x40209000u)
+ /** Peripheral I2S8 base pointer */
+ #define I2S8 ((I2S_Type *)I2S8_BASE)
+ /** Peripheral I2S8 base pointer */
+ #define I2S8_NS ((I2S_Type *)I2S8_BASE_NS)
+ /** Peripheral I2S9 base address */
+ #define I2S9_BASE (0x5020A000u)
+ /** Peripheral I2S9 base address */
+ #define I2S9_BASE_NS (0x4020A000u)
+ /** Peripheral I2S9 base pointer */
+ #define I2S9 ((I2S_Type *)I2S9_BASE)
+ /** Peripheral I2S9 base pointer */
+ #define I2S9_NS ((I2S_Type *)I2S9_BASE_NS)
+ /** Peripheral I2S10 base address */
+ #define I2S10_BASE (0x5020B000u)
+ /** Peripheral I2S10 base address */
+ #define I2S10_BASE_NS (0x4020B000u)
+ /** Peripheral I2S10 base pointer */
+ #define I2S10 ((I2S_Type *)I2S10_BASE)
+ /** Peripheral I2S10 base pointer */
+ #define I2S10_NS ((I2S_Type *)I2S10_BASE_NS)
+ /** Peripheral I2S11 base address */
+ #define I2S11_BASE (0x5020C000u)
+ /** Peripheral I2S11 base address */
+ #define I2S11_BASE_NS (0x4020C000u)
+ /** Peripheral I2S11 base pointer */
+ #define I2S11 ((I2S_Type *)I2S11_BASE)
+ /** Peripheral I2S11 base pointer */
+ #define I2S11_NS ((I2S_Type *)I2S11_BASE_NS)
+ /** Peripheral I2S12 base address */
+ #define I2S12_BASE (0x5020D000u)
+ /** Peripheral I2S12 base address */
+ #define I2S12_BASE_NS (0x4020D000u)
+ /** Peripheral I2S12 base pointer */
+ #define I2S12 ((I2S_Type *)I2S12_BASE)
+ /** Peripheral I2S12 base pointer */
+ #define I2S12_NS ((I2S_Type *)I2S12_BASE_NS)
+ /** Peripheral I2S13 base address */
+ #define I2S13_BASE (0x5020E000u)
+ /** Peripheral I2S13 base address */
+ #define I2S13_BASE_NS (0x4020E000u)
+ /** Peripheral I2S13 base pointer */
+ #define I2S13 ((I2S_Type *)I2S13_BASE)
+ /** Peripheral I2S13 base pointer */
+ #define I2S13_NS ((I2S_Type *)I2S13_BASE_NS)
+ /** Array initializer of I2S peripheral base addresses */
+ #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE, I2S8_BASE, I2S9_BASE, I2S10_BASE, I2S11_BASE, I2S12_BASE, I2S13_BASE }
+ /** Array initializer of I2S peripheral base pointers */
+ #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7, I2S8, I2S9, I2S10, I2S11, I2S12, I2S13 }
+ /** Array initializer of I2S peripheral base addresses */
+ #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS, I2S8_BASE_NS, I2S9_BASE_NS, I2S10_BASE_NS, I2S11_BASE_NS, I2S12_BASE_NS, I2S13_BASE_NS }
+ /** Array initializer of I2S peripheral base pointers */
+ #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS, I2S8_NS, I2S9_NS, I2S10_NS, I2S11_NS, I2S12_NS, I2S13_NS }
+#else
+ /** Peripheral I2S0 base address */
+ #define I2S0_BASE (0x40106000u)
+ /** Peripheral I2S0 base pointer */
+ #define I2S0 ((I2S_Type *)I2S0_BASE)
+ /** Peripheral I2S1 base address */
+ #define I2S1_BASE (0x40107000u)
+ /** Peripheral I2S1 base pointer */
+ #define I2S1 ((I2S_Type *)I2S1_BASE)
+ /** Peripheral I2S2 base address */
+ #define I2S2_BASE (0x40108000u)
+ /** Peripheral I2S2 base pointer */
+ #define I2S2 ((I2S_Type *)I2S2_BASE)
+ /** Peripheral I2S3 base address */
+ #define I2S3_BASE (0x40109000u)
+ /** Peripheral I2S3 base pointer */
+ #define I2S3 ((I2S_Type *)I2S3_BASE)
+ /** Peripheral I2S4 base address */
+ #define I2S4_BASE (0x40122000u)
+ /** Peripheral I2S4 base pointer */
+ #define I2S4 ((I2S_Type *)I2S4_BASE)
+ /** Peripheral I2S5 base address */
+ #define I2S5_BASE (0x40123000u)
+ /** Peripheral I2S5 base pointer */
+ #define I2S5 ((I2S_Type *)I2S5_BASE)
+ /** Peripheral I2S6 base address */
+ #define I2S6_BASE (0x40124000u)
+ /** Peripheral I2S6 base pointer */
+ #define I2S6 ((I2S_Type *)I2S6_BASE)
+ /** Peripheral I2S7 base address */
+ #define I2S7_BASE (0x40125000u)
+ /** Peripheral I2S7 base pointer */
+ #define I2S7 ((I2S_Type *)I2S7_BASE)
+ /** Peripheral I2S8 base address */
+ #define I2S8_BASE (0x40209000u)
+ /** Peripheral I2S8 base pointer */
+ #define I2S8 ((I2S_Type *)I2S8_BASE)
+ /** Peripheral I2S9 base address */
+ #define I2S9_BASE (0x4020A000u)
+ /** Peripheral I2S9 base pointer */
+ #define I2S9 ((I2S_Type *)I2S9_BASE)
+ /** Peripheral I2S10 base address */
+ #define I2S10_BASE (0x4020B000u)
+ /** Peripheral I2S10 base pointer */
+ #define I2S10 ((I2S_Type *)I2S10_BASE)
+ /** Peripheral I2S11 base address */
+ #define I2S11_BASE (0x4020C000u)
+ /** Peripheral I2S11 base pointer */
+ #define I2S11 ((I2S_Type *)I2S11_BASE)
+ /** Peripheral I2S12 base address */
+ #define I2S12_BASE (0x4020D000u)
+ /** Peripheral I2S12 base pointer */
+ #define I2S12 ((I2S_Type *)I2S12_BASE)
+ /** Peripheral I2S13 base address */
+ #define I2S13_BASE (0x4020E000u)
+ /** Peripheral I2S13 base pointer */
+ #define I2S13 ((I2S_Type *)I2S13_BASE)
+ /** Array initializer of I2S peripheral base addresses */
+ #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE, I2S8_BASE, I2S9_BASE, I2S10_BASE, I2S11_BASE, I2S12_BASE, I2S13_BASE }
+ /** Array initializer of I2S peripheral base pointers */
+ #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7, I2S8, I2S9, I2S10, I2S11, I2S12, I2S13 }
+#endif
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn, FLEXCOMM11_IRQn, FLEXCOMM12_IRQn, FLEXCOMM13_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I3C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer
+ * @{
+ */
+
+/** I3C - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCONFIG; /**< Master Configuration Register, offset: 0x0 */
+ __IO uint32_t SCONFIG; /**< Slave Configuration Register, offset: 0x4 */
+ __IO uint32_t SSTATUS; /**< Slave Status Register, offset: 0x8 */
+ __IO uint32_t SCTRL; /**< Slave Control Register, offset: 0xC */
+ __IO uint32_t SINTSET; /**< Slave Interrupt Set Register, offset: 0x10 */
+ __IO uint32_t SINTCLR; /**< Slave Interrupt Clear Register, offset: 0x14 */
+ __I uint32_t SINTMASKED; /**< Slave Interrupt Mask Register, offset: 0x18 */
+ __IO uint32_t SERRWARN; /**< Slave Errors and Warnings Register, offset: 0x1C */
+ __IO uint32_t SDMACTRL; /**< Slave DMA Control Register, offset: 0x20 */
+ uint8_t RESERVED_0[8];
+ __IO uint32_t SDATACTRL; /**< Slave Data Control Register, offset: 0x2C */
+ __O uint32_t SWDATAB; /**< Slave Write Data Byte Register, offset: 0x30 */
+ __O uint32_t SWDATABE; /**< Slave Write Data Byte End, offset: 0x34 */
+ __O uint32_t SWDATAH; /**< Slave Write Data Half-word Register, offset: 0x38 */
+ __O uint32_t SWDATAHE; /**< Slave Write Data Half-word End Register, offset: 0x3C */
+ __I uint32_t SRDATAB; /**< Slave Read Data Byte Register, offset: 0x40 */
+ uint8_t RESERVED_1[4];
+ __I uint32_t SRDATAH; /**< Slave Read Data Half-word Register, offset: 0x48 */
+ uint8_t RESERVED_2[20];
+ __I uint32_t SCAPABILITIES; /**< Slave Capabilities Register, offset: 0x60 */
+ __IO uint32_t SDYNADDR; /**< Slave Dynamic Address Register, offset: 0x64 */
+ __IO uint32_t SMAXLIMITS; /**< Slave Maximum Limits Register, offset: 0x68 */
+ __IO uint32_t SIDPARTNO; /**< Slave ID Part Number Register, offset: 0x6C */
+ __IO uint32_t SIDEXT; /**< Slave ID Extension Register, offset: 0x70 */
+ __IO uint32_t SVENDORID; /**< Slave Vendor ID Register, offset: 0x74 */
+ __IO uint32_t STCCLOCK; /**< Slave Time Control Clock Register, offset: 0x78 */
+ __I uint32_t SMSGMAPADDR; /**< Slave Message-Mapped Address Register, offset: 0x7C */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t MCTRL; /**< Master Main Control Register, offset: 0x84 */
+ __IO uint32_t MSTATUS; /**< Master Status Register, offset: 0x88 */
+ __IO uint32_t MIBIRULES; /**< Master In-band Interrupt Registry and Rules Register, offset: 0x8C */
+ __IO uint32_t MINTSET; /**< Master Interrupt Set Register, offset: 0x90 */
+ __O uint32_t MINTCLR; /**< Master Interrupt Clear Register, offset: 0x94 */
+ __I uint32_t MINTMASKED; /**< Master Interrupt Mask Register, offset: 0x98 */
+ __IO uint32_t MERRWARN; /**< Master Errors and Warnings Register, offset: 0x9C */
+ __IO uint32_t MDMACTRL; /**< Master DMA Control Register, offset: 0xA0 */
+ uint8_t RESERVED_4[8];
+ __IO uint32_t MDATACTRL; /**< Master Data Control Register, offset: 0xAC */
+ __O uint32_t MWDATAB; /**< Master Write Data Byte Register, offset: 0xB0 */
+ __O uint32_t MWDATABE; /**< Master Write Data Byte End Register, offset: 0xB4 */
+ __O uint32_t MWDATAH; /**< Master Write Data Half-word Register, offset: 0xB8 */
+ __O uint32_t MWDATAHE; /**< Master Write Data Byte End Register, offset: 0xBC */
+ __I uint32_t MRDATAB; /**< Master Read Data Byte Register, offset: 0xC0 */
+ uint8_t RESERVED_5[4];
+ __I uint32_t MRDATAH; /**< Master Read Data Half-word Register, offset: 0xC8 */
+ uint8_t RESERVED_6[4];
+ union { /* offset: 0xD0 */
+ __O uint32_t MWMSG_SDR_CONTROL; /**< Master Write Message in SDR mode, offset: 0xD0 */
+ __O uint32_t MWMSG_SDR_DATA; /**< Master Write Message Data in SDR mode, offset: 0xD0 */
+ };
+ __I uint32_t MRMSG_SDR; /**< Master Read Message in SDR mode, offset: 0xD4 */
+ union { /* offset: 0xD8 */
+ __O uint32_t MWMSG_DDR_CONTROL; /**< Master Write Message in DDR mode, offset: 0xD8 */
+ __O uint32_t MWMSG_DDR_DATA; /**< Master Write Message Data in DDR mode, offset: 0xD8 */
+ };
+ __IO uint32_t MRMSG_DDR; /**< Master Read Message in DDR mode, offset: 0xDC */
+ uint8_t RESERVED_7[4];
+ __IO uint32_t MDYNADDR; /**< Master Dynamic Address Register, offset: 0xE4 */
+ uint8_t RESERVED_8[3860];
+ __I uint32_t SID; /**< Slave Module ID Register, offset: 0xFFC */
+} I3C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I3C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I3C_Register_Masks I3C Register Masks
+ * @{
+ */
+
+/*! @name MCONFIG - Master Configuration Register */
+/*! @{ */
+#define I3C_MCONFIG_MSTENA_MASK (0x3U)
+#define I3C_MCONFIG_MSTENA_SHIFT (0U)
+/*! MSTENA - Master enable
+ * 0b00..MASTER_OFF: Master is off (is not enabled). If MASTER_OFF is enabled, then the I3C module can only use slave mode.
+ * 0b01..MASTER_ON: Master is on (is enabled). When used from start-up, this I3C module is master by default (the
+ * main master). The module will control the bus unless the master is handed off. If the master is handed
+ * off, then MSTENA must move to 2 after that happens. The handoff means emitting GETACCMST and if accepted,
+ * the module will emit a STOP and set the MSTENA bit to 2 (or 0).
+ * 0b10..MASTER_CAPABLE: The I3C module is master-capable; however the module is operating as a slave now. When
+ * used from the start, the I3C module will start as a slave, but will be prepared to switch to master mode.
+ * To switch to master mode, the slave emits an Master Request (MR), or gets a GETACCMST CCC command and
+ * accepts it (to switch on the STOP).
+ * 0b11..RESERVED
+ */
+#define I3C_MCONFIG_MSTENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK)
+#define I3C_MCONFIG_DISTO_MASK (0x8U)
+#define I3C_MCONFIG_DISTO_SHIFT (3U)
+/*! DISTO - Disable Timeout
+ */
+#define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK)
+#define I3C_MCONFIG_HKEEP_MASK (0x30U)
+#define I3C_MCONFIG_HKEEP_SHIFT (4U)
+/*! HKEEP - High-Keeper
+ * 0b00..NONE: Use PUR (Pull-Up Resistor). Hold SCL High.
+ * 0b01..WIRED_IN: Wired-in High Keeper controls; use pin_HK (High Keeper) controls.
+ * 0b10..PASSIVE_SDA: Passive on SDA; can Hi-Z (high impedance) for Bus Free (IDLE) and hold.
+ * 0b11..PASSIVE_ON_SDA_SCL: Passive on SDA and SCL; can Hi-Z (high impedance) both for Bus Free (IDLE), and can Hi-Z SDA for hold.
+ */
+#define I3C_MCONFIG_HKEEP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK)
+#define I3C_MCONFIG_ODSTOP_MASK (0x40U)
+#define I3C_MCONFIG_ODSTOP_SHIFT (6U)
+/*! ODSTOP - Open drain stop
+ */
+#define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK)
+#define I3C_MCONFIG_PPBAUD_MASK (0xF00U)
+#define I3C_MCONFIG_PPBAUD_SHIFT (8U)
+/*! PPBAUD - Push-pull baud rate
+ */
+#define I3C_MCONFIG_PPBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK)
+#define I3C_MCONFIG_PPLOW_MASK (0xF000U)
+#define I3C_MCONFIG_PPLOW_SHIFT (12U)
+/*! PPLOW - Push-Pull low
+ */
+#define I3C_MCONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
+#define I3C_MCONFIG_ODBAUD_MASK (0xFF0000U)
+#define I3C_MCONFIG_ODBAUD_SHIFT (16U)
+/*! ODBAUD - Open drain baud rate
+ */
+#define I3C_MCONFIG_ODBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK)
+#define I3C_MCONFIG_ODHPP_MASK (0x1000000U)
+#define I3C_MCONFIG_ODHPP_SHIFT (24U)
+/*! ODHPP - Open drain high push-pull
+ */
+#define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
+#define I3C_MCONFIG_SKEW_MASK (0xE000000U)
+#define I3C_MCONFIG_SKEW_SHIFT (25U)
+/*! SKEW - Skew
+ */
+#define I3C_MCONFIG_SKEW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK)
+#define I3C_MCONFIG_I2CBAUD_MASK (0xF0000000U)
+#define I3C_MCONFIG_I2CBAUD_SHIFT (28U)
+/*! I2CBAUD - I2C baud rate
+ */
+#define I3C_MCONFIG_I2CBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK)
+/*! @} */
+
+/*! @name SCONFIG - Slave Configuration Register */
+/*! @{ */
+#define I3C_SCONFIG_SLVENA_MASK (0x1U)
+#define I3C_SCONFIG_SLVENA_SHIFT (0U)
+/*! SLVENA - Slave enable
+ */
+#define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)
+#define I3C_SCONFIG_NACK_MASK (0x2U)
+#define I3C_SCONFIG_NACK_SHIFT (1U)
+/*! NACK - Not acknowledge
+ */
+#define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK)
+#define I3C_SCONFIG_MATCHSS_MASK (0x4U)
+#define I3C_SCONFIG_MATCHSS_SHIFT (2U)
+/*! MATCHSS - Match START or STOP
+ */
+#define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK)
+#define I3C_SCONFIG_S0IGNORE_MASK (0x8U)
+#define I3C_SCONFIG_S0IGNORE_SHIFT (3U)
+/*! S0IGNORE - S0/S1 errors ignore
+ */
+#define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK)
+#define I3C_SCONFIG_DDROK_MASK (0x10U)
+#define I3C_SCONFIG_DDROK_SHIFT (4U)
+/*! DDROK - Double Data Rate OK
+ */
+#define I3C_SCONFIG_DDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_DDROK_SHIFT)) & I3C_SCONFIG_DDROK_MASK)
+#define I3C_SCONFIG_IDRAND_MASK (0x100U)
+#define I3C_SCONFIG_IDRAND_SHIFT (8U)
+/*! IDRAND - ID random
+ */
+#define I3C_SCONFIG_IDRAND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_IDRAND_SHIFT)) & I3C_SCONFIG_IDRAND_MASK)
+#define I3C_SCONFIG_OFFLINE_MASK (0x200U)
+#define I3C_SCONFIG_OFFLINE_SHIFT (9U)
+/*! OFFLINE - Offline
+ */
+#define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK)
+#define I3C_SCONFIG_BAMATCH_MASK (0xFF0000U)
+#define I3C_SCONFIG_BAMATCH_SHIFT (16U)
+/*! BAMATCH - Bus available match
+ */
+#define I3C_SCONFIG_BAMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK)
+#define I3C_SCONFIG_SADDR_MASK (0xFE000000U)
+#define I3C_SCONFIG_SADDR_SHIFT (25U)
+/*! SADDR - Static address
+ */
+#define I3C_SCONFIG_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK)
+/*! @} */
+
+/*! @name SSTATUS - Slave Status Register */
+/*! @{ */
+#define I3C_SSTATUS_STNOTSTOP_MASK (0x1U)
+#define I3C_SSTATUS_STNOTSTOP_SHIFT (0U)
+/*! STNOTSTOP - Status not stop
+ */
+#define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK)
+#define I3C_SSTATUS_STMSG_MASK (0x2U)
+#define I3C_SSTATUS_STMSG_SHIFT (1U)
+/*! STMSG - Status message
+ */
+#define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK)
+#define I3C_SSTATUS_STCCCH_MASK (0x4U)
+#define I3C_SSTATUS_STCCCH_SHIFT (2U)
+/*! STCCCH - Status Common Command Code Handler
+ */
+#define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK)
+#define I3C_SSTATUS_STREQRD_MASK (0x8U)
+#define I3C_SSTATUS_STREQRD_SHIFT (3U)
+/*! STREQRD - Status required
+ */
+#define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK)
+#define I3C_SSTATUS_STREQWR_MASK (0x10U)
+#define I3C_SSTATUS_STREQWR_SHIFT (4U)
+/*! STREQWR - Status request write
+ */
+#define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK)
+#define I3C_SSTATUS_STDAA_MASK (0x20U)
+#define I3C_SSTATUS_STDAA_SHIFT (5U)
+/*! STDAA - Status Dynamic Address Assignment
+ */
+#define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK)
+#define I3C_SSTATUS_STHDR_MASK (0x40U)
+#define I3C_SSTATUS_STHDR_SHIFT (6U)
+/*! STHDR - Status High Data Rate
+ */
+#define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK)
+#define I3C_SSTATUS_START_MASK (0x100U)
+#define I3C_SSTATUS_START_SHIFT (8U)
+/*! START - Start
+ */
+#define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK)
+#define I3C_SSTATUS_MATCHED_MASK (0x200U)
+#define I3C_SSTATUS_MATCHED_SHIFT (9U)
+/*! MATCHED - Matched
+ */
+#define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK)
+#define I3C_SSTATUS_STOP_MASK (0x400U)
+#define I3C_SSTATUS_STOP_SHIFT (10U)
+/*! STOP - Stop
+ */
+#define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK)
+#define I3C_SSTATUS_RX_PEND_MASK (0x800U)
+#define I3C_SSTATUS_RX_PEND_SHIFT (11U)
+/*! RX_PEND - Received message pending
+ */
+#define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK)
+#define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U)
+#define I3C_SSTATUS_TXNOTFULL_SHIFT (12U)
+/*! TXNOTFULL - Transmit buffer is not full
+ */
+#define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK)
+#define I3C_SSTATUS_DACHG_MASK (0x2000U)
+#define I3C_SSTATUS_DACHG_SHIFT (13U)
+/*! DACHG - DACHG
+ */
+#define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK)
+#define I3C_SSTATUS_CCC_MASK (0x4000U)
+#define I3C_SSTATUS_CCC_SHIFT (14U)
+/*! CCC - Common Command Code
+ */
+#define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK)
+#define I3C_SSTATUS_ERRWARN_MASK (0x8000U)
+#define I3C_SSTATUS_ERRWARN_SHIFT (15U)
+/*! ERRWARN - Error warning
+ */
+#define I3C_SSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK)
+#define I3C_SSTATUS_HDRMATCH_MASK (0x10000U)
+#define I3C_SSTATUS_HDRMATCH_SHIFT (16U)
+/*! HDRMATCH - High Data Rate command match
+ */
+#define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK)
+#define I3C_SSTATUS_CHANDLED_MASK (0x20000U)
+#define I3C_SSTATUS_CHANDLED_SHIFT (17U)
+/*! CHANDLED - Common-Command-Code handled
+ */
+#define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK)
+#define I3C_SSTATUS_EVENT_MASK (0x40000U)
+#define I3C_SSTATUS_EVENT_SHIFT (18U)
+/*! EVENT - Event
+ */
+#define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK)
+#define I3C_SSTATUS_EVDET_MASK (0x300000U)
+#define I3C_SSTATUS_EVDET_SHIFT (20U)
+/*! EVDET - Event details
+ * 0b00..NONE: no event or no pending event
+ * 0b01..NO_REQUEST: Request not sent yet. Either there was no START yet, or is waiting for Bus-Available or Bus-Idle (HJ).
+ * 0b10..NACKED: Not acknowledged(Request sent and NACKed); the module will try again.
+ * 0b11..ACKED: Acknowledged (Request sent and ACKed), so Done (unless the time control data is still being sent).
+ */
+#define I3C_SSTATUS_EVDET(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK)
+#define I3C_SSTATUS_IBIDIS_MASK (0x1000000U)
+#define I3C_SSTATUS_IBIDIS_SHIFT (24U)
+/*! IBIDIS - In-Band Interrupts are disabled
+ */
+#define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK)
+#define I3C_SSTATUS_MRDIS_MASK (0x2000000U)
+#define I3C_SSTATUS_MRDIS_SHIFT (25U)
+/*! MRDIS - Master requests are disabled
+ */
+#define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK)
+#define I3C_SSTATUS_HJDIS_MASK (0x8000000U)
+#define I3C_SSTATUS_HJDIS_SHIFT (27U)
+/*! HJDIS - Hot-Join is disabled
+ */
+#define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK)
+#define I3C_SSTATUS_ACTSTATE_MASK (0x30000000U)
+#define I3C_SSTATUS_ACTSTATE_SHIFT (28U)
+/*! ACTSTATE - Activity state from Common Command Codes (CCC)
+ * 0b00..NO_LATENCY: normal bus operations
+ * 0b01..LATENCY_1MS: 1 ms of latency
+ * 0b10..LATENCY_100MS: 100 ms of latency
+ * 0b11..LATENCY_10S: 10 seconds of latency
+ */
+#define I3C_SSTATUS_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK)
+#define I3C_SSTATUS_TIMECTRL_MASK (0xC0000000U)
+#define I3C_SSTATUS_TIMECTRL_SHIFT (30U)
+/*! TIMECTRL - Time control
+ * 0b00..NO_TIME_CONTROL: No time control is enabled
+ * 0b01..Reserved
+ * 0b10..ASYNC_MODE: Asynchronous standard mode (0) is enabled
+ * 0b11..RESERVED
+ */
+#define I3C_SSTATUS_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK)
+/*! @} */
+
+/*! @name SCTRL - Slave Control Register */
+/*! @{ */
+#define I3C_SCTRL_EVENT_MASK (0x3U)
+#define I3C_SCTRL_EVENT_SHIFT (0U)
+/*! EVENT - EVENT
+ * 0b00..NORMAL_MODE: If EVENT is set to 0 after was a non-0 value, event processing will cancel if the event
+ * processing has not yet started; if event processing has already been started, then event processing will not
+ * be be cancelled.
+ * 0b01..IBI: Start an In-Band Interrupt. This will try to push an IBI interrupt onto the I3C bus. If data is
+ * associated with the IBI, then the data will be read from the SCTRL.IBIDATA field. If time control is
+ * enabled, then this data will also include any time control-related bytes; additionally, the IBIDATA byte will
+ * have bit 7 set to 1 automatically (as is required for time control). The IBI interrupt will occur after the
+ * 1st (mandatory) IBIDATA, if any.
+ * 0b10..MASTER_REQUEST: Start a Master-Request.
+ * 0b11..HOT_JOIN_REQUEST: Start a Hot-Join request. A Hot-Join Request should only be used when the device is
+ * powered on after the I3C bus is already powered up, or when the device is connected using hot insertion
+ * methods (the device is powered up when it is physically inserted onto the powered-up I3C bus). The hot join
+ * will wait for Bus Idle, and SCTRL.EVENT=HOT_JOIN_REQUEST must be set before the slave enable
+ * (SCONFIG.SLVENA).
+ */
+#define I3C_SCTRL_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK)
+#define I3C_SCTRL_IBIDATA_MASK (0xFF00U)
+#define I3C_SCTRL_IBIDATA_SHIFT (8U)
+/*! IBIDATA - In-Band Interrupt data
+ */
+#define I3C_SCTRL_IBIDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK)
+#define I3C_SCTRL_PENDINT_MASK (0xF0000U)
+#define I3C_SCTRL_PENDINT_SHIFT (16U)
+/*! PENDINT - Pending interrupt
+ */
+#define I3C_SCTRL_PENDINT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK)
+#define I3C_SCTRL_ACTSTATE_MASK (0x300000U)
+#define I3C_SCTRL_ACTSTATE_SHIFT (20U)
+/*! ACTSTATE - Activity state (of slave)
+ */
+#define I3C_SCTRL_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK)
+#define I3C_SCTRL_VENDINFO_MASK (0xFF000000U)
+#define I3C_SCTRL_VENDINFO_SHIFT (24U)
+/*! VENDINFO - Vendor information
+ */
+#define I3C_SCTRL_VENDINFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK)
+/*! @} */
+
+/*! @name SINTSET - Slave Interrupt Set Register */
+/*! @{ */
+#define I3C_SINTSET_START_MASK (0x100U)
+#define I3C_SINTSET_START_SHIFT (8U)
+/*! START - Start interrupt enable
+ */
+#define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK)
+#define I3C_SINTSET_MATCHED_MASK (0x200U)
+#define I3C_SINTSET_MATCHED_SHIFT (9U)
+/*! MATCHED - Match interrupt enable
+ */
+#define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK)
+#define I3C_SINTSET_STOP_MASK (0x400U)
+#define I3C_SINTSET_STOP_SHIFT (10U)
+/*! STOP - Stop interrupt enable
+ */
+#define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK)
+#define I3C_SINTSET_RXPEND_MASK (0x800U)
+#define I3C_SINTSET_RXPEND_SHIFT (11U)
+/*! RXPEND - Receive interrupt enable
+ */
+#define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK)
+#define I3C_SINTSET_TXSEND_MASK (0x1000U)
+#define I3C_SINTSET_TXSEND_SHIFT (12U)
+/*! TXSEND - Transmit interrupt enable
+ */
+#define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK)
+#define I3C_SINTSET_DACHG_MASK (0x2000U)
+#define I3C_SINTSET_DACHG_SHIFT (13U)
+/*! DACHG - Dynamic address change interrupt enable
+ */
+#define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK)
+#define I3C_SINTSET_CCC_MASK (0x4000U)
+#define I3C_SINTSET_CCC_SHIFT (14U)
+/*! CCC - Common Command Code (CCC) (that was not handled by I3C module) interrupt enable
+ */
+#define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK)
+#define I3C_SINTSET_ERRWARN_MASK (0x8000U)
+#define I3C_SINTSET_ERRWARN_SHIFT (15U)
+/*! ERRWARN - Error/warning interrupt enable
+ */
+#define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK)
+#define I3C_SINTSET_DDRMATCHED_MASK (0x10000U)
+#define I3C_SINTSET_DDRMATCHED_SHIFT (16U)
+/*! DDRMATCHED - Double Data Rate (DDR) interrupt enable
+ */
+#define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK)
+#define I3C_SINTSET_CHANDLED_MASK (0x20000U)
+#define I3C_SINTSET_CHANDLED_SHIFT (17U)
+/*! CHANDLED - Common Command Code (CCC) (that was handled by I3C module) interrupt enable
+ */
+#define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK)
+#define I3C_SINTSET_EVENT_MASK (0x40000U)
+#define I3C_SINTSET_EVENT_SHIFT (18U)
+/*! EVENT - Event interrupt enable
+ */
+#define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK)
+/*! @} */
+
+/*! @name SINTCLR - Slave Interrupt Clear Register */
+/*! @{ */
+#define I3C_SINTCLR_START_MASK (0x100U)
+#define I3C_SINTCLR_START_SHIFT (8U)
+/*! START - START interrupt enable clear
+ */
+#define I3C_SINTCLR_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK)
+#define I3C_SINTCLR_MATCHED_MASK (0x200U)
+#define I3C_SINTCLR_MATCHED_SHIFT (9U)
+/*! MATCHED - MATCHED interrupt enable clear
+ */
+#define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK)
+#define I3C_SINTCLR_STOP_MASK (0x400U)
+#define I3C_SINTCLR_STOP_SHIFT (10U)
+/*! STOP - STOP interrupt enable clear
+ */
+#define I3C_SINTCLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK)
+#define I3C_SINTCLR_RXPEND_MASK (0x800U)
+#define I3C_SINTCLR_RXPEND_SHIFT (11U)
+/*! RXPEND - RXPEND interrupt enable clear
+ */
+#define I3C_SINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK)
+#define I3C_SINTCLR_TXSEND_MASK (0x1000U)
+#define I3C_SINTCLR_TXSEND_SHIFT (12U)
+/*! TXSEND - TXSEND interrupt enable clear
+ */
+#define I3C_SINTCLR_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK)
+#define I3C_SINTCLR_DACHG_MASK (0x2000U)
+#define I3C_SINTCLR_DACHG_SHIFT (13U)
+/*! DACHG - DACHG interrupt enable clear
+ */
+#define I3C_SINTCLR_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK)
+#define I3C_SINTCLR_CCC_MASK (0x4000U)
+#define I3C_SINTCLR_CCC_SHIFT (14U)
+/*! CCC - CCC interrupt enable clear
+ */
+#define I3C_SINTCLR_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK)
+#define I3C_SINTCLR_ERRWARN_MASK (0x8000U)
+#define I3C_SINTCLR_ERRWARN_SHIFT (15U)
+/*! ERRWARN - ERRWARN interrupt enable clear
+ */
+#define I3C_SINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK)
+#define I3C_SINTCLR_DDRMATCHED_MASK (0x10000U)
+#define I3C_SINTCLR_DDRMATCHED_SHIFT (16U)
+/*! DDRMATCHED - DDRMATCHED interrupt enable clear
+ */
+#define I3C_SINTCLR_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK)
+#define I3C_SINTCLR_CHANDLED_MASK (0x20000U)
+#define I3C_SINTCLR_CHANDLED_SHIFT (17U)
+/*! CHANDLED - CHANDLED interrupt enable clear
+ */
+#define I3C_SINTCLR_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK)
+#define I3C_SINTCLR_EVENT_MASK (0x40000U)
+#define I3C_SINTCLR_EVENT_SHIFT (18U)
+/*! EVENT - EVENT interrupt enable clear
+ */
+#define I3C_SINTCLR_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK)
+/*! @} */
+
+/*! @name SINTMASKED - Slave Interrupt Mask Register */
+/*! @{ */
+#define I3C_SINTMASKED_START_MASK (0x100U)
+#define I3C_SINTMASKED_START_SHIFT (8U)
+/*! START - START interrupt mask
+ */
+#define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK)
+#define I3C_SINTMASKED_MATCHED_MASK (0x200U)
+#define I3C_SINTMASKED_MATCHED_SHIFT (9U)
+/*! MATCHED - MATCHED interrupt mask
+ */
+#define I3C_SINTMASKED_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK)
+#define I3C_SINTMASKED_STOP_MASK (0x400U)
+#define I3C_SINTMASKED_STOP_SHIFT (10U)
+/*! STOP - STOP interrupt mask
+ */
+#define I3C_SINTMASKED_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK)
+#define I3C_SINTMASKED_RXPEND_MASK (0x800U)
+#define I3C_SINTMASKED_RXPEND_SHIFT (11U)
+/*! RXPEND - RXPEND interrupt mask
+ */
+#define I3C_SINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK)
+#define I3C_SINTMASKED_TXSEND_MASK (0x1000U)
+#define I3C_SINTMASKED_TXSEND_SHIFT (12U)
+/*! TXSEND - TXSEND interrupt mask
+ */
+#define I3C_SINTMASKED_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK)
+#define I3C_SINTMASKED_DACHG_MASK (0x2000U)
+#define I3C_SINTMASKED_DACHG_SHIFT (13U)
+/*! DACHG - DACHG interrupt mask
+ */
+#define I3C_SINTMASKED_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK)
+#define I3C_SINTMASKED_CCC_MASK (0x4000U)
+#define I3C_SINTMASKED_CCC_SHIFT (14U)
+/*! CCC - CCC interrupt mask
+ */
+#define I3C_SINTMASKED_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK)
+#define I3C_SINTMASKED_ERRWARN_MASK (0x8000U)
+#define I3C_SINTMASKED_ERRWARN_SHIFT (15U)
+/*! ERRWARN - ERRWARN interrupt mask
+ */
+#define I3C_SINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK)
+#define I3C_SINTMASKED_DDRMATCHED_MASK (0x10000U)
+#define I3C_SINTMASKED_DDRMATCHED_SHIFT (16U)
+/*! DDRMATCHED - DDRMATCHED interrupt mask
+ */
+#define I3C_SINTMASKED_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK)
+#define I3C_SINTMASKED_CHANDLED_MASK (0x20000U)
+#define I3C_SINTMASKED_CHANDLED_SHIFT (17U)
+/*! CHANDLED - CHANDLED interrupt mask
+ */
+#define I3C_SINTMASKED_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK)
+#define I3C_SINTMASKED_EVENT_MASK (0x40000U)
+#define I3C_SINTMASKED_EVENT_SHIFT (18U)
+/*! EVENT - EVENT interrupt mask
+ */
+#define I3C_SINTMASKED_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK)
+/*! @} */
+
+/*! @name SERRWARN - Slave Errors and Warnings Register */
+/*! @{ */
+#define I3C_SERRWARN_ORUN_MASK (0x1U)
+#define I3C_SERRWARN_ORUN_SHIFT (0U)
+/*! ORUN - Overrun error
+ */
+#define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK)
+#define I3C_SERRWARN_URUN_MASK (0x2U)
+#define I3C_SERRWARN_URUN_SHIFT (1U)
+/*! URUN - Underrun error
+ */
+#define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK)
+#define I3C_SERRWARN_URUNNACK_MASK (0x4U)
+#define I3C_SERRWARN_URUNNACK_SHIFT (2U)
+/*! URUNNACK - Underrun and Not Acknowledged (NACKed) error
+ */
+#define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK)
+#define I3C_SERRWARN_TERM_MASK (0x8U)
+#define I3C_SERRWARN_TERM_SHIFT (3U)
+/*! TERM - Terminated error
+ */
+#define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK)
+#define I3C_SERRWARN_INVSTART_MASK (0x10U)
+#define I3C_SERRWARN_INVSTART_SHIFT (4U)
+/*! INVSTART - Invalid start error
+ */
+#define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK)
+#define I3C_SERRWARN_SPAR_MASK (0x100U)
+#define I3C_SERRWARN_SPAR_SHIFT (8U)
+/*! SPAR - SDR parity error
+ */
+#define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK)
+#define I3C_SERRWARN_HPAR_MASK (0x200U)
+#define I3C_SERRWARN_HPAR_SHIFT (9U)
+/*! HPAR - HDR parity error
+ */
+#define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK)
+#define I3C_SERRWARN_HCRC_MASK (0x400U)
+#define I3C_SERRWARN_HCRC_SHIFT (10U)
+/*! HCRC - HDR-DDR CRC error
+ */
+#define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK)
+#define I3C_SERRWARN_S0S1_MASK (0x800U)
+#define I3C_SERRWARN_S0S1_SHIFT (11U)
+/*! S0S1 - S0 or S1 error
+ */
+#define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK)
+#define I3C_SERRWARN_OREAD_MASK (0x10000U)
+#define I3C_SERRWARN_OREAD_SHIFT (16U)
+/*! OREAD - Over-read error
+ */
+#define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK)
+#define I3C_SERRWARN_OWRITE_MASK (0x20000U)
+#define I3C_SERRWARN_OWRITE_SHIFT (17U)
+/*! OWRITE - Over-write error
+ */
+#define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK)
+/*! @} */
+
+/*! @name SDMACTRL - Slave DMA Control Register */
+/*! @{ */
+#define I3C_SDMACTRL_DMAFB_MASK (0x3U)
+#define I3C_SDMACTRL_DMAFB_SHIFT (0U)
+/*! DMAFB - DMA Read (From-bus) trigger
+ * 0b00..DMA not used
+ * 0b01..DMA is enabled for 1 frame
+ * 0b10..DMA enable
+ */
+#define I3C_SDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK)
+#define I3C_SDMACTRL_DMATB_MASK (0xCU)
+#define I3C_SDMACTRL_DMATB_SHIFT (2U)
+/*! DMATB - DMA Write (To-bus) trigger
+ * 0b00..NOT_USED: DMA is not used
+ * 0b01..ENABLE_ONE_FRAME: DMA is enabled for 1 Frame (ended by DMA or terminated). DMATB auto-clears on a STOP
+ * or START (see the Match START or STOP bit (SCONFIG.MATCHSS).
+ * 0b10..ENABLE: DMA is enabled until turned off. Normally, ENABLE should only be used with Master Message mode.
+ */
+#define I3C_SDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK)
+#define I3C_SDMACTRL_DMAWIDTH_MASK (0x30U)
+#define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U)
+/*! DMAWIDTH - Width of DMA operations
+ * 0b00..BYTE
+ * 0b01..BYTE_AGAIN
+ * 0b10..HALF_WORD: Half word (16 bits). This will make sure that 2 bytes are free/available in the FIFO.
+ * 0b11..RESERVED
+ */
+#define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK)
+/*! @} */
+
+/*! @name SDATACTRL - Slave Data Control Register */
+/*! @{ */
+#define I3C_SDATACTRL_FLUSHTB_MASK (0x1U)
+#define I3C_SDATACTRL_FLUSHTB_SHIFT (0U)
+/*! FLUSHTB - Flush the to-bus buffer/FIFO
+ */
+#define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK)
+#define I3C_SDATACTRL_FLUSHFB_MASK (0x2U)
+#define I3C_SDATACTRL_FLUSHFB_SHIFT (1U)
+/*! FLUSHFB - Flushes the from-bus buffer/FIFO
+ */
+#define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK)
+#define I3C_SDATACTRL_UNLOCK_MASK (0x8U)
+#define I3C_SDATACTRL_UNLOCK_SHIFT (3U)
+/*! UNLOCK - Unlock
+ */
+#define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK)
+#define I3C_SDATACTRL_TXTRIG_MASK (0x30U)
+#define I3C_SDATACTRL_TXTRIG_SHIFT (4U)
+/*! TXTRIG - Trigger level for TX FIFO emptiness
+ * 0b00..Trigger on empty
+ * 0b01..Trigger on ¼ full or less
+ * 0b10..Trigger on .5 full or less
+ * 0b11..Trigger on 1 less than full or less (Default)
+ */
+#define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK)
+#define I3C_SDATACTRL_RXTRIG_MASK (0xC0U)
+#define I3C_SDATACTRL_RXTRIG_SHIFT (6U)
+/*! RXTRIG - Trigger level for RX FIFO fullness
+ * 0b00..Trigger on not empty
+ * 0b01..Trigger on ¼ or more full
+ * 0b10..Trigger on .5 or more full
+ * 0b11..Trigger on 3/4 or more full
+ */
+#define I3C_SDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK)
+#define I3C_SDATACTRL_TXCOUNT_MASK (0x1F0000U)
+#define I3C_SDATACTRL_TXCOUNT_SHIFT (16U)
+/*! TXCOUNT - Count of bytes in TX
+ */
+#define I3C_SDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK)
+#define I3C_SDATACTRL_RXCOUNT_MASK (0x1F000000U)
+#define I3C_SDATACTRL_RXCOUNT_SHIFT (24U)
+/*! RXCOUNT - Count of bytes in RX
+ */
+#define I3C_SDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK)
+#define I3C_SDATACTRL_TXFULL_MASK (0x40000000U)
+#define I3C_SDATACTRL_TXFULL_SHIFT (30U)
+/*! TXFULL - TX is full
+ * 0b1..TX is full
+ * 0b0..TX is not full
+ */
+#define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK)
+#define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U)
+#define I3C_SDATACTRL_RXEMPTY_SHIFT (31U)
+/*! RXEMPTY - RX is empty
+ * 0b1..RX is empty
+ * 0b0..RX is not empty
+ */
+#define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK)
+/*! @} */
+
+/*! @name SWDATAB - Slave Write Data Byte Register */
+/*! @{ */
+#define I3C_SWDATAB_DATA_MASK (0xFFU)
+#define I3C_SWDATAB_DATA_SHIFT (0U)
+/*! DATA - The data byte to send to the master
+ */
+#define I3C_SWDATAB_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK)
+#define I3C_SWDATAB_END_MASK (0x100U)
+#define I3C_SWDATAB_END_SHIFT (8U)
+/*! END - End
+ */
+#define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK)
+#define I3C_SWDATAB_END_ALSO_MASK (0x10000U)
+#define I3C_SWDATAB_END_ALSO_SHIFT (16U)
+/*! END_ALSO - End also
+ */
+#define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK)
+/*! @} */
+
+/*! @name SWDATABE - Slave Write Data Byte End */
+/*! @{ */
+#define I3C_SWDATABE_DATA_MASK (0xFFU)
+#define I3C_SWDATABE_DATA_SHIFT (0U)
+/*! DATA - The data byte to send to the master
+ */
+#define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK)
+/*! @} */
+
+/*! @name SWDATAH - Slave Write Data Half-word Register */
+/*! @{ */
+#define I3C_SWDATAH_DATA0_MASK (0xFFU)
+#define I3C_SWDATAH_DATA0_SHIFT (0U)
+/*! DATA0 - The 1st byte to send to the master
+ */
+#define I3C_SWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK)
+#define I3C_SWDATAH_DATA1_MASK (0xFF00U)
+#define I3C_SWDATAH_DATA1_SHIFT (8U)
+/*! DATA1 - The 2nd byte to send to the master
+ */
+#define I3C_SWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK)
+#define I3C_SWDATAH_END_MASK (0x10000U)
+#define I3C_SWDATAH_END_SHIFT (16U)
+/*! END - End of message
+ */
+#define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK)
+/*! @} */
+
+/*! @name SWDATAHE - Slave Write Data Half-word End Register */
+/*! @{ */
+#define I3C_SWDATAHE_DATA0_MASK (0xFFU)
+#define I3C_SWDATAHE_DATA0_SHIFT (0U)
+/*! DATA0 - The 1st byte to send to the master
+ */
+#define I3C_SWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK)
+#define I3C_SWDATAHE_DATA1_MASK (0xFF00U)
+#define I3C_SWDATAHE_DATA1_SHIFT (8U)
+/*! DATA1 - The 2nd byte to send to the master
+ */
+#define I3C_SWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK)
+/*! @} */
+
+/*! @name SRDATAB - Slave Read Data Byte Register */
+/*! @{ */
+#define I3C_SRDATAB_DATA0_MASK (0xFFU)
+#define I3C_SRDATAB_DATA0_SHIFT (0U)
+/*! DATA0 - Byte read from the master
+ */
+#define I3C_SRDATAB_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK)
+/*! @} */
+
+/*! @name SRDATAH - Slave Read Data Half-word Register */
+/*! @{ */
+#define I3C_SRDATAH_LSB_MASK (0xFFU)
+#define I3C_SRDATAH_LSB_SHIFT (0U)
+/*! LSB - The 1st byte read from the slave
+ */
+#define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK)
+#define I3C_SRDATAH_MSB_MASK (0xFF00U)
+#define I3C_SRDATAH_MSB_SHIFT (8U)
+/*! MSB - The 2nd byte read from the slave
+ */
+#define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK)
+/*! @} */
+
+/*! @name SCAPABILITIES - Slave Capabilities Register */
+/*! @{ */
+#define I3C_SCAPABILITIES_IDENA_MASK (0x3U)
+#define I3C_SCAPABILITIES_IDENA_SHIFT (0U)
+/*! IDENA - ID 48b handler
+ * 0b00..APPLICATION: Application handles ID 48b
+ * 0b01..HW: Hardware handles ID 48b
+ * 0b10..HW_BUT: in hardware but the I3C module instance handles ID 48b.
+ * 0b11..PARTNO: a part number register (PARTNO) handles ID 48b
+ */
+#define I3C_SCAPABILITIES_IDENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK)
+#define I3C_SCAPABILITIES_IDREG_MASK (0x3CU)
+#define I3C_SCAPABILITIES_IDREG_SHIFT (2U)
+/*! IDREG - ID register
+ */
+#define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK)
+#define I3C_SCAPABILITIES_HDRSUPP_MASK (0x1C0U)
+#define I3C_SCAPABILITIES_HDRSUPP_SHIFT (6U)
+/*! HDRSUPP - HDR support
+ */
+#define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK)
+#define I3C_SCAPABILITIES_MASTER_MASK (0x200U)
+#define I3C_SCAPABILITIES_MASTER_SHIFT (9U)
+/*! MASTER - Master
+ * 0b0..MASTERNOTSUPPORTED: master capability is not supported.
+ * 0b1..MASTERSUPPORTED: master capability is supported.
+ */
+#define I3C_SCAPABILITIES_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK)
+#define I3C_SCAPABILITIES_SADDR_MASK (0xC00U)
+#define I3C_SCAPABILITIES_SADDR_SHIFT (10U)
+/*! SADDR - Static address
+ * 0b00..NO_STATIC: No static address
+ * 0b01..STATIC: Static address is fixed in hardware
+ * 0b10..HW_CONTROL: Hardware controls the static address dynamically (for example, from the pin strap)
+ * 0b11..CONFIG: SCONFIG register supplies the static address
+ */
+#define I3C_SCAPABILITIES_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK)
+#define I3C_SCAPABILITIES_CCCHANDLE_MASK (0xF000U)
+#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U)
+/*! CCCHANDLE - Common Command Codes (CCC) handling
+ */
+#define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK)
+#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK (0x1F0000U)
+#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U)
+/*! IBI_MR_HJ - In-Band Interrupts, Master Requests, Hot Join events
+ */
+#define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK)
+#define I3C_SCAPABILITIES_TIMECTRL_MASK (0x200000U)
+#define I3C_SCAPABILITIES_TIMECTRL_SHIFT (21U)
+/*! TIMECTRL - Time control
+ * 0b0..NO_TIME_CONTROL_TYPE: No time control is enabled
+ * 0b1..ATLEAST1_TIME_CONTROL: at least one time-control type is supported
+ */
+#define I3C_SCAPABILITIES_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK)
+#define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U)
+#define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U)
+/*! EXTFIFO - External FIFO
+ * 0b001..STD_EXT_FIFO: standard available/free external FIFO
+ * 0b011..RESERVED
+ */
+#define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK)
+#define I3C_SCAPABILITIES_FIFOTX_MASK (0xC000000U)
+#define I3C_SCAPABILITIES_FIFOTX_SHIFT (26U)
+/*! FIFOTX - FIFO transmit
+ * 0b00..FIFO_2BYTE: 2-byte TX FIFO, the default FIFO transmit value (FIFOTX)
+ * 0b01..FIFO_4BYTE: 4-byte TX FIFO
+ * 0b10..FIFO_8BYTE: 8-byte TX FIFO
+ * 0b11..FIFO_16BYTE: 16-byte TX FIFO
+ */
+#define I3C_SCAPABILITIES_FIFOTX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK)
+#define I3C_SCAPABILITIES_FIFORX_MASK (0x30000000U)
+#define I3C_SCAPABILITIES_FIFORX_SHIFT (28U)
+/*! FIFORX - FIFO receive
+ * 0b00..FIFO_2BYTE: 2 (or 3)-byte RX FIFO, the default FIFO receive value (FIFORX)
+ * 0b01..FIFO_4BYTE: 4-byte RX FIFO
+ * 0b10..FIFO_8BYTE: 8-byte RX FIFO
+ * 0b11..FIFO_16BYTE: 16-byte RX FIFO
+ */
+#define I3C_SCAPABILITIES_FIFORX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK)
+#define I3C_SCAPABILITIES_INT_MASK (0x40000000U)
+#define I3C_SCAPABILITIES_INT_SHIFT (30U)
+/*! INT - INT
+ * 0b1..Interrupts are supported
+ * 0b0..Interrupts are not supported
+ */
+#define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK)
+#define I3C_SCAPABILITIES_DMA_MASK (0x80000000U)
+#define I3C_SCAPABILITIES_DMA_SHIFT (31U)
+/*! DMA - DMA
+ * 0b1..DMA is supported
+ * 0b0..DMA is not supported
+ */
+#define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK)
+/*! @} */
+
+/*! @name SDYNADDR - Slave Dynamic Address Register */
+/*! @{ */
+#define I3C_SDYNADDR_DAVALID_MASK (0x1U)
+#define I3C_SDYNADDR_DAVALID_SHIFT (0U)
+/*! DAVALID - DAVALID
+ * 0b0..DANOTASSIGNED: a Dynamic Address is not assigned
+ * 0b1..DAASSIGNED: a Dynamic Address is assigned
+ */
+#define I3C_SDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK)
+#define I3C_SDYNADDR_DADDR_MASK (0xFEU)
+#define I3C_SDYNADDR_DADDR_SHIFT (1U)
+/*! DADDR - Dynamic address
+ */
+#define I3C_SDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK)
+#define I3C_SDYNADDR_MAPIDX_MASK (0xF00U)
+#define I3C_SDYNADDR_MAPIDX_SHIFT (8U)
+/*! MAPIDX - Mapped Dynamic Address
+ */
+#define I3C_SDYNADDR_MAPIDX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPIDX_SHIFT)) & I3C_SDYNADDR_MAPIDX_MASK)
+#define I3C_SDYNADDR_MAPSA_MASK (0x1000U)
+#define I3C_SDYNADDR_MAPSA_SHIFT (12U)
+/*! MAPSA - Map a Static Address
+ */
+#define I3C_SDYNADDR_MAPSA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK)
+#define I3C_SDYNADDR_KEY_MASK (0xFFFF0000U)
+#define I3C_SDYNADDR_KEY_SHIFT (16U)
+/*! KEY - Key
+ */
+#define I3C_SDYNADDR_KEY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK)
+/*! @} */
+
+/*! @name SMAXLIMITS - Slave Maximum Limits Register */
+/*! @{ */
+#define I3C_SMAXLIMITS_MAXRD_MASK (0xFFFU)
+#define I3C_SMAXLIMITS_MAXRD_SHIFT (0U)
+/*! MAXRD - Maximum read length
+ */
+#define I3C_SMAXLIMITS_MAXRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK)
+#define I3C_SMAXLIMITS_MAXWR_MASK (0xFFF0000U)
+#define I3C_SMAXLIMITS_MAXWR_SHIFT (16U)
+/*! MAXWR - Maximum write length
+ */
+#define I3C_SMAXLIMITS_MAXWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK)
+/*! @} */
+
+/*! @name SIDPARTNO - Slave ID Part Number Register */
+/*! @{ */
+#define I3C_SIDPARTNO_PARTNO_MASK (0xFFFFFFFFU)
+#define I3C_SIDPARTNO_PARTNO_SHIFT (0U)
+/*! PARTNO - Part number
+ */
+#define I3C_SIDPARTNO_PARTNO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK)
+/*! @} */
+
+/*! @name SIDEXT - Slave ID Extension Register */
+/*! @{ */
+#define I3C_SIDEXT_DCR_MASK (0xFF00U)
+#define I3C_SIDEXT_DCR_SHIFT (8U)
+/*! DCR - Device Characteristic Register
+ */
+#define I3C_SIDEXT_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK)
+#define I3C_SIDEXT_BCR_MASK (0xFF0000U)
+#define I3C_SIDEXT_BCR_SHIFT (16U)
+/*! BCR - Bus Characteristics Register
+ */
+#define I3C_SIDEXT_BCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK)
+/*! @} */
+
+/*! @name SVENDORID - Slave Vendor ID Register */
+/*! @{ */
+#define I3C_SVENDORID_VID_MASK (0x7FFFU)
+#define I3C_SVENDORID_VID_SHIFT (0U)
+/*! VID - Vendor ID
+ */
+#define I3C_SVENDORID_VID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK)
+/*! @} */
+
+/*! @name STCCLOCK - Slave Time Control Clock Register */
+/*! @{ */
+#define I3C_STCCLOCK_ACCURACY_MASK (0xFFU)
+#define I3C_STCCLOCK_ACCURACY_SHIFT (0U)
+/*! ACCURACY - Clock accuracy
+ */
+#define I3C_STCCLOCK_ACCURACY(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK)
+#define I3C_STCCLOCK_FREQ_MASK (0xFF00U)
+#define I3C_STCCLOCK_FREQ_SHIFT (8U)
+/*! FREQ - Clock frequency
+ */
+#define I3C_STCCLOCK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK)
+/*! @} */
+
+/*! @name SMSGMAPADDR - Slave Message-Mapped Address Register */
+/*! @{ */
+#define I3C_SMSGMAPADDR_MAPLAST_MASK (0xFU)
+#define I3C_SMSGMAPADDR_MAPLAST_SHIFT (0U)
+/*! MAPLAST - Matched address index
+ */
+#define I3C_SMSGMAPADDR_MAPLAST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK)
+#define I3C_SMSGMAPADDR_MAPLASTM1_MASK (0xF00U)
+#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT (8U)
+/*! MAPLASTM1 - Previous match index 1
+ */
+#define I3C_SMSGMAPADDR_MAPLASTM1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK)
+#define I3C_SMSGMAPADDR_MAPLASTM2_MASK (0xF0000U)
+#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT (16U)
+/*! MAPLASTM2 - Previous match index 2
+ */
+#define I3C_SMSGMAPADDR_MAPLASTM2(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK)
+/*! @} */
+
+/*! @name MCTRL - Master Main Control Register */
+/*! @{ */
+#define I3C_MCTRL_REQUEST_MASK (0x7U)
+#define I3C_MCTRL_REQUEST_SHIFT (0U)
+/*! REQUEST - Request
+ * 0b000..NONE: Returns to this when finished with any request. The MSTATUS register indicates the master's
+ * state. See also AutoIBI mode. NONE is only written as 0: when setting RDTERM to 1 (to stop a read in
+ * progress) or when setting IBI reponse field (IBIRESP) for MSG use
+ * 0b001..EMITSTARTADDR: Emit START with address and direction from a stopped state or in the middle of a Single
+ * Data Rate (SDR) message. If from a stopped state (IDLE), then emit start may be prevented by an event
+ * (like IBI, MR, HJ), in which case the appropriate interrupt is signaled; note that Emit START can be
+ * resubmitted.
+ * 0b010..EMITSTOP: Emit a STOP on bus. Must be in Single Data Rate (SDR) mode. If in Dynamic Address Assignment
+ * (DAA) mode, Emit stop will exit DAA mode.
+ * 0b011..IBIACKNACK: Manual In-Band Interrupt (IBI) Acknowledge (ACK) or Not Acknowledge (NACK). When IBIRESP
+ * has indicated a hold on an In-Band Interrupt to allow a manual decision, this request completes it. Uses
+ * IBIRESP to provide the information.
+ * 0b100..PROCESSDAA: If not in Dynamic Address Assignment (DAA) mode now, will issue START, 7E, ENTDAA, and then
+ * will emit 7E/R to process first Slave. Will stop just before the new Dynamic Address (DA) is to be
+ * emitted. The DA is written using MWDATAB bits 6:0 and then ProcessDAA is requested again to write the new
+ * address, and then starts the next; an MSTATUS indicating NACK means DA was not accepted (e.g. parity
+ * error). If Process DAA is NACKed on the 7E/R, the interrupt will indicate so and this will emit a STOP.
+ * 0b101..RESERVED
+ * 0b110..FORCEEXIT and IBHR: Emit an Exit Pattern from any state, but end Double Data Rate (DDR) (including
+ * MSGDDR), if in DDR mode now. Includes a STOP afterward. If TYPE != 0, then it will perform an IBHR (In-Band
+ * Hardware Reset). If TYPE=2, then it does a normal reset (DEFRST can prevent the reset). If TYPE=3, it
+ * does a forced reset (will always reset).
+ * 0b111..AUTOIBI: Hold in a stopped state, but auto-emit START,7E when the slave is holding down SDA to get an
+ * In-Band Interrupt (IBI). Actual In-Band Interrupt handling is defined by IBIRESP.
+ */
+#define I3C_MCTRL_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK)
+#define I3C_MCTRL_TYPE_MASK (0x30U)
+#define I3C_MCTRL_TYPE_SHIFT (4U)
+/*! TYPE - Bus type with START
+ * 0b00..I3C: Normally the SDR mode of I3C. For ForceExit, the Exit pattern.
+ * 0b01..I2C: Normally the Standard I2C protocol.
+ * 0b10..DDR: (Double Data Rate): Normally the HDR-DDR mode of I3C. Enter DDR mode (7E and then ENTHDR0), if the
+ * module is not already in DDR mode. The 1st byte written to the TX FIFO should be a command, and should
+ * already be in the FIFO. To end DDR mode, use ForceExit. For ForceExit, the normal IBHR (In-Band Hardware
+ * Reset).
+ * 0b11..For ForcedExit, this is forced IBHR.
+ */
+#define I3C_MCTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK)
+#define I3C_MCTRL_IBIRESP_MASK (0xC0U)
+#define I3C_MCTRL_IBIRESP_SHIFT (6U)
+/*! IBIRESP - In-Band Interrupt (IBI) response
+ * 0b00..ACK: Acknowledge. A mandatory byte (or not) is decided by the Master In-band Interrupt Registry and
+ * Rules Register (MIBIRULES). To limit the maximum number of IBI bytes, configure the Read Termination field
+ * (MCTRL.RDTERM).
+ * 0b01..NACK: Not acknowledge
+ * 0b10..ACK_WITH_MANDATORY: Acknowledge with mandatory byte (ignores the MIBIRULES register). Acknowledge with
+ * mandatory byte should not be used, unless only slaves with a mandatory byte can cause an In-Band Interrupt.
+ * 0b11..MANUAL: stop and wait for a decision using the IBIAckNack request
+ */
+#define I3C_MCTRL_IBIRESP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK)
+#define I3C_MCTRL_DIR_MASK (0x100U)
+#define I3C_MCTRL_DIR_SHIFT (8U)
+/*! DIR - DIR
+ * 0b0..DIRWRITE: Write
+ * 0b1..DIRREAD: Read
+ */
+#define I3C_MCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK)
+#define I3C_MCTRL_ADDR_MASK (0xFE00U)
+#define I3C_MCTRL_ADDR_SHIFT (9U)
+/*! ADDR - ADDR
+ */
+#define I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
+#define I3C_MCTRL_RDTERM_MASK (0xFF0000U)
+#define I3C_MCTRL_RDTERM_SHIFT (16U)
+/*! RDTERM - Read terminate
+ */
+#define I3C_MCTRL_RDTERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK)
+/*! @} */
+
+/*! @name MSTATUS - Master Status Register */
+/*! @{ */
+#define I3C_MSTATUS_STATE_MASK (0x7U)
+#define I3C_MSTATUS_STATE_SHIFT (0U)
+/*! STATE - State of the master
+ * 0b000..IDLE: the bus has STOPped.
+ * 0b001..SLVREQ: (Slave Request state) the bus has STOPped but a slave is holding SDA low. If using auto-emit
+ * IBI (MCTRL.AutoIBI), then the master will not stay in the Slave Request state.
+ * 0b010..MSGSDR: in Single Data Rate (SDR) Message state (from using MWMSG_SDR)
+ * 0b011..NORMACT: normal active Single Data Rate (SDR) state (from using MCTRL and MWDATAn and MRDATAn
+ * registers). The master will stay in the NORMACT state until a STOP is issued.
+ * 0b100..MSGDDR: in Double Data Rate (DDR) Message mode (from using MWMSG_DDR or using the normal method with
+ * DDR). The master will stay in the DDR state, until the master exits using EXIT (emits the Exit pattern).
+ * 0b101..DAA: in Enter Dynamic Address Assignment (ENTDAA) mode
+ * 0b110..IBIACK: waiting for an In-Band Interrupt (IBI) ACK/NACK decision
+ * 0b111..IBIRCV: Receiving an In-Band Interrupt (IBI); this IBIRCV state is used after IBI/MR/HJ has won the
+ * arbitration, and IBIRCV state is also used for IBI mandatory byte (if any) and any bytes that follow.
+ */
+#define I3C_MSTATUS_STATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK)
+#define I3C_MSTATUS_BETWEEN_MASK (0x10U)
+#define I3C_MSTATUS_BETWEEN_SHIFT (4U)
+/*! BETWEEN - Between messages or Dynamic Address Assignments (DAA)
+ */
+#define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK)
+#define I3C_MSTATUS_NACKED_MASK (0x20U)
+#define I3C_MSTATUS_NACKED_SHIFT (5U)
+/*! NACKED - Not acknowledged
+ */
+#define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK)
+#define I3C_MSTATUS_IBITYPE_MASK (0xC0U)
+#define I3C_MSTATUS_IBITYPE_SHIFT (6U)
+/*! IBITYPE - In-Band Interrupt (IBI) type
+ * 0b00..NONE: cleared when IBI Won bit (MSTATUS.IBIWON) is cleared
+ * 0b01..IBI: In-Band Interrupt
+ * 0b10..MR: Master Request
+ * 0b11..HJ: Hot-Join
+ */
+#define I3C_MSTATUS_IBITYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK)
+#define I3C_MSTATUS_SLVSTART_MASK (0x100U)
+#define I3C_MSTATUS_SLVSTART_SHIFT (8U)
+/*! SLVSTART - Slave start
+ */
+#define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK)
+#define I3C_MSTATUS_MCTRLDONE_MASK (0x200U)
+#define I3C_MSTATUS_MCTRLDONE_SHIFT (9U)
+/*! MCTRLDONE - Master control done
+ */
+#define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK)
+#define I3C_MSTATUS_COMPLETE_MASK (0x400U)
+#define I3C_MSTATUS_COMPLETE_SHIFT (10U)
+/*! COMPLETE - COMPLETE
+ */
+#define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK)
+#define I3C_MSTATUS_RXPEND_MASK (0x800U)
+#define I3C_MSTATUS_RXPEND_SHIFT (11U)
+/*! RXPEND - RXPEND
+ */
+#define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK)
+#define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U)
+#define I3C_MSTATUS_TXNOTFULL_SHIFT (12U)
+/*! TXNOTFULL - TX buffer/FIFO not yet full
+ */
+#define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK)
+#define I3C_MSTATUS_IBIWON_MASK (0x2000U)
+#define I3C_MSTATUS_IBIWON_SHIFT (13U)
+/*! IBIWON - In-Band Interrupt (IBI) won
+ */
+#define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK)
+#define I3C_MSTATUS_ERRWARN_MASK (0x8000U)
+#define I3C_MSTATUS_ERRWARN_SHIFT (15U)
+/*! ERRWARN - Error or warning
+ */
+#define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK)
+#define I3C_MSTATUS_NOWMASTER_MASK (0x80000U)
+#define I3C_MSTATUS_NOWMASTER_SHIFT (19U)
+/*! NOWMASTER - Now master (now this module is a master)
+ */
+#define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK)
+#define I3C_MSTATUS_IBIADDR_MASK (0x7F000000U)
+#define I3C_MSTATUS_IBIADDR_SHIFT (24U)
+/*! IBIADDR - IBI address
+ */
+#define I3C_MSTATUS_IBIADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK)
+/*! @} */
+
+/*! @name MIBIRULES - Master In-band Interrupt Registry and Rules Register */
+/*! @{ */
+#define I3C_MIBIRULES_ADDR0_MASK (0x3FU)
+#define I3C_MIBIRULES_ADDR0_SHIFT (0U)
+/*! ADDR0 - ADDR0
+ */
+#define I3C_MIBIRULES_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK)
+#define I3C_MIBIRULES_ADDR1_MASK (0xFC0U)
+#define I3C_MIBIRULES_ADDR1_SHIFT (6U)
+/*! ADDR1 - ADDR1
+ */
+#define I3C_MIBIRULES_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK)
+#define I3C_MIBIRULES_ADDR2_MASK (0x3F000U)
+#define I3C_MIBIRULES_ADDR2_SHIFT (12U)
+/*! ADDR2 - ADDR2
+ */
+#define I3C_MIBIRULES_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK)
+#define I3C_MIBIRULES_ADDR3_MASK (0xFC0000U)
+#define I3C_MIBIRULES_ADDR3_SHIFT (18U)
+/*! ADDR3 - ADDR3
+ */
+#define I3C_MIBIRULES_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK)
+#define I3C_MIBIRULES_ADDR4_MASK (0x3F000000U)
+#define I3C_MIBIRULES_ADDR4_SHIFT (24U)
+/*! ADDR4 - ADDR4
+ */
+#define I3C_MIBIRULES_ADDR4(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK)
+#define I3C_MIBIRULES_MSB0_MASK (0x40000000U)
+#define I3C_MIBIRULES_MSB0_SHIFT (30U)
+/*! MSB0 - Set Most Significant address Bit to 0
+ */
+#define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK)
+#define I3C_MIBIRULES_NOBYTE_MASK (0x80000000U)
+#define I3C_MIBIRULES_NOBYTE_SHIFT (31U)
+/*! NOBYTE - No IBI byte
+ */
+#define I3C_MIBIRULES_NOBYTE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK)
+/*! @} */
+
+/*! @name MINTSET - Master Interrupt Set Register */
+/*! @{ */
+#define I3C_MINTSET_SLVSTART_MASK (0x100U)
+#define I3C_MINTSET_SLVSTART_SHIFT (8U)
+/*! SLVSTART - Slave start interrupt enable
+ */
+#define I3C_MINTSET_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK)
+#define I3C_MINTSET_MCTRLDONE_MASK (0x200U)
+#define I3C_MINTSET_MCTRLDONE_SHIFT (9U)
+/*! MCTRLDONE - Master control done interrupt enable
+ */
+#define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK)
+#define I3C_MINTSET_COMPLETE_MASK (0x400U)
+#define I3C_MINTSET_COMPLETE_SHIFT (10U)
+/*! COMPLETE - Completed message interrupt enable
+ */
+#define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK)
+#define I3C_MINTSET_RXPEND_MASK (0x800U)
+#define I3C_MINTSET_RXPEND_SHIFT (11U)
+/*! RXPEND - RX pending interrupt enable
+ */
+#define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK)
+#define I3C_MINTSET_TXNOTFULL_MASK (0x1000U)
+#define I3C_MINTSET_TXNOTFULL_SHIFT (12U)
+/*! TXNOTFULL - TX buffer/FIFO is not full interrupt enable
+ */
+#define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK)
+#define I3C_MINTSET_IBIWON_MASK (0x2000U)
+#define I3C_MINTSET_IBIWON_SHIFT (13U)
+/*! IBIWON - In-Band Interrupt (IBI) won interrupt enable
+ */
+#define I3C_MINTSET_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK)
+#define I3C_MINTSET_ERRWARN_MASK (0x8000U)
+#define I3C_MINTSET_ERRWARN_SHIFT (15U)
+/*! ERRWARN - Error or warning (ERRWARN) interrupt enable
+ */
+#define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK)
+#define I3C_MINTSET_NOWMASTER_MASK (0x80000U)
+#define I3C_MINTSET_NOWMASTER_SHIFT (19U)
+/*! NOWMASTER - Now master (now this I3C module is a master) interrupt enable
+ */
+#define I3C_MINTSET_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK)
+/*! @} */
+
+/*! @name MINTCLR - Master Interrupt Clear Register */
+/*! @{ */
+#define I3C_MINTCLR_SLVSTART_MASK (0x100U)
+#define I3C_MINTCLR_SLVSTART_SHIFT (8U)
+/*! SLVSTART - SLVSTART interrupt enable clear
+ */
+#define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK)
+#define I3C_MINTCLR_MCTRLDONE_MASK (0x200U)
+#define I3C_MINTCLR_MCTRLDONE_SHIFT (9U)
+/*! MCTRLDONE - MCTRLDONE interrupt enable clear
+ */
+#define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK)
+#define I3C_MINTCLR_COMPLETE_MASK (0x400U)
+#define I3C_MINTCLR_COMPLETE_SHIFT (10U)
+/*! COMPLETE - COMPLETE interrupt enable clear
+ */
+#define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK)
+#define I3C_MINTCLR_RXPEND_MASK (0x800U)
+#define I3C_MINTCLR_RXPEND_SHIFT (11U)
+/*! RXPEND - RXPEND interrupt enable clear
+ */
+#define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK)
+#define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U)
+#define I3C_MINTCLR_TXNOTFULL_SHIFT (12U)
+/*! TXNOTFULL - TXNOTFULL interrupt enable clear
+ */
+#define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK)
+#define I3C_MINTCLR_IBIWON_MASK (0x2000U)
+#define I3C_MINTCLR_IBIWON_SHIFT (13U)
+/*! IBIWON - IBIWON interrupt enable clear
+ */
+#define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK)
+#define I3C_MINTCLR_ERRWARN_MASK (0x8000U)
+#define I3C_MINTCLR_ERRWARN_SHIFT (15U)
+/*! ERRWARN - ERRWARN interrupt enable clear
+ */
+#define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK)
+#define I3C_MINTCLR_NOWMASTER_MASK (0x80000U)
+#define I3C_MINTCLR_NOWMASTER_SHIFT (19U)
+/*! NOWMASTER - NOWMASTER interrupt enable clear
+ */
+#define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK)
+/*! @} */
+
+/*! @name MINTMASKED - Master Interrupt Mask Register */
+/*! @{ */
+#define I3C_MINTMASKED_SLVSTART_MASK (0x100U)
+#define I3C_MINTMASKED_SLVSTART_SHIFT (8U)
+/*! SLVSTART - SLVSTART interrupt mask
+ */
+#define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK)
+#define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U)
+#define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U)
+/*! MCTRLDONE - MCTRLDONE interrupt mask
+ */
+#define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK)
+#define I3C_MINTMASKED_COMPLETE_MASK (0x400U)
+#define I3C_MINTMASKED_COMPLETE_SHIFT (10U)
+/*! COMPLETE - COMPLETE interrupt mask
+ */
+#define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK)
+#define I3C_MINTMASKED_RXPEND_MASK (0x800U)
+#define I3C_MINTMASKED_RXPEND_SHIFT (11U)
+/*! RXPEND - RXPEND interrupt mask
+ */
+#define I3C_MINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK)
+#define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U)
+#define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U)
+/*! TXNOTFULL - TXNOTFULL interrupt mask
+ */
+#define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK)
+#define I3C_MINTMASKED_IBIWON_MASK (0x2000U)
+#define I3C_MINTMASKED_IBIWON_SHIFT (13U)
+/*! IBIWON - IBIWON interrupt mask
+ */
+#define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK)
+#define I3C_MINTMASKED_ERRWARN_MASK (0x8000U)
+#define I3C_MINTMASKED_ERRWARN_SHIFT (15U)
+/*! ERRWARN - ERRWARN interrupt mask
+ */
+#define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK)
+#define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U)
+#define I3C_MINTMASKED_NOWMASTER_SHIFT (19U)
+/*! NOWMASTER - NOWMASTER interrupt mask
+ */
+#define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK)
+/*! @} */
+
+/*! @name MERRWARN - Master Errors and Warnings Register */
+/*! @{ */
+#define I3C_MERRWARN_NACK_MASK (0x4U)
+#define I3C_MERRWARN_NACK_SHIFT (2U)
+/*! NACK - Not acknowledge (NACK) error
+ */
+#define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK)
+#define I3C_MERRWARN_WRABT_MASK (0x8U)
+#define I3C_MERRWARN_WRABT_SHIFT (3U)
+/*! WRABT - WRABT (Write abort) error
+ */
+#define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK)
+#define I3C_MERRWARN_TERM_MASK (0x10U)
+#define I3C_MERRWARN_TERM_SHIFT (4U)
+/*! TERM - Terminate error
+ */
+#define I3C_MERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK)
+#define I3C_MERRWARN_HPAR_MASK (0x200U)
+#define I3C_MERRWARN_HPAR_SHIFT (9U)
+/*! HPAR - High data rate parity
+ */
+#define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK)
+#define I3C_MERRWARN_HCRC_MASK (0x400U)
+#define I3C_MERRWARN_HCRC_SHIFT (10U)
+/*! HCRC - High data rate CRC error
+ */
+#define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK)
+#define I3C_MERRWARN_OREAD_MASK (0x10000U)
+#define I3C_MERRWARN_OREAD_SHIFT (16U)
+/*! OREAD - Over-read error
+ */
+#define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK)
+#define I3C_MERRWARN_OWRITE_MASK (0x20000U)
+#define I3C_MERRWARN_OWRITE_SHIFT (17U)
+/*! OWRITE - Over-write error
+ */
+#define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK)
+#define I3C_MERRWARN_MSGERR_MASK (0x40000U)
+#define I3C_MERRWARN_MSGERR_SHIFT (18U)
+/*! MSGERR - Message error
+ */
+#define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK)
+#define I3C_MERRWARN_INVREQ_MASK (0x80000U)
+#define I3C_MERRWARN_INVREQ_SHIFT (19U)
+/*! INVREQ - Invalid request error
+ */
+#define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK)
+#define I3C_MERRWARN_TIMEOUT_MASK (0x100000U)
+#define I3C_MERRWARN_TIMEOUT_SHIFT (20U)
+/*! TIMEOUT - TIMEOUT error
+ */
+#define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK)
+/*! @} */
+
+/*! @name MDMACTRL - Master DMA Control Register */
+/*! @{ */
+#define I3C_MDMACTRL_DMAFB_MASK (0x3U)
+#define I3C_MDMACTRL_DMAFB_SHIFT (0U)
+/*! DMAFB - DMA from bus
+ * 0b00..NOT_USED: DMA is not used
+ * 0b01..ENABLE_ONE_FRAME: DMA is enabled for 1 frame. DMAFB auto-clears on STOP or repeated START. See MCONFIG.MATCHSS.
+ * 0b10..ENABLE: DMA is enabled until the DMA is turned off.
+ */
+#define I3C_MDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK)
+#define I3C_MDMACTRL_DMATB_MASK (0xCU)
+#define I3C_MDMACTRL_DMATB_SHIFT (2U)
+/*! DMATB - DMA to bus
+ * 0b00..NOT_USED: DMA is not used
+ * 0b01..ENABLE_ONE_FRAME: DMA is enabled for 1 frame (ended by DMA or Terminated). DMATB auto-clears on STOP or START. See MCONFIG.MATCHSS.
+ * 0b10..ENABLE: DMA is enabled until DMA is turned off. Normally DMA ENABLE should only be used in Master Message mode.
+ */
+#define I3C_MDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK)
+#define I3C_MDMACTRL_DMAWIDTH_MASK (0x30U)
+#define I3C_MDMACTRL_DMAWIDTH_SHIFT (4U)
+/*! DMAWIDTH - DMA width
+ * 0b00..BYTE
+ * 0b01..BYTE_AGAIN
+ * 0b10..HALF_WORD: Half-word (16 bits). This will make sure that 2 bytes are free/available in FIFO.
+ * 0b11..RESERVED
+ */
+#define I3C_MDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK)
+/*! @} */
+
+/*! @name MDATACTRL - Master Data Control Register */
+/*! @{ */
+#define I3C_MDATACTRL_FLUSHTB_MASK (0x1U)
+#define I3C_MDATACTRL_FLUSHTB_SHIFT (0U)
+/*! FLUSHTB - Flush to-bus buffer/FIFO
+ */
+#define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK)
+#define I3C_MDATACTRL_FLUSHFB_MASK (0x2U)
+#define I3C_MDATACTRL_FLUSHFB_SHIFT (1U)
+/*! FLUSHFB - Flush from-bus buffer/FIFO
+ */
+#define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK)
+#define I3C_MDATACTRL_UNLOCK_MASK (0x4U)
+#define I3C_MDATACTRL_UNLOCK_SHIFT (2U)
+/*! UNLOCK - Unlock
+ */
+#define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK)
+#define I3C_MDATACTRL_TXTRIG_MASK (0x30U)
+#define I3C_MDATACTRL_TXTRIG_SHIFT (4U)
+/*! TXTRIG - TX trigger level
+ */
+#define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK)
+#define I3C_MDATACTRL_RXTRIG_MASK (0xC0U)
+#define I3C_MDATACTRL_RXTRIG_SHIFT (6U)
+/*! RXTRIG - RX trigger level
+ */
+#define I3C_MDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK)
+#define I3C_MDATACTRL_TXCOUNT_MASK (0x1F0000U)
+#define I3C_MDATACTRL_TXCOUNT_SHIFT (16U)
+/*! TXCOUNT - TX byte count
+ */
+#define I3C_MDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK)
+#define I3C_MDATACTRL_RXCOUNT_MASK (0x1F000000U)
+#define I3C_MDATACTRL_RXCOUNT_SHIFT (24U)
+/*! RXCOUNT - RX byte count
+ */
+#define I3C_MDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK)
+#define I3C_MDATACTRL_TXFULL_MASK (0x40000000U)
+#define I3C_MDATACTRL_TXFULL_SHIFT (30U)
+/*! TXFULL - TX is full
+ */
+#define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK)
+#define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U)
+#define I3C_MDATACTRL_RXEMPTY_SHIFT (31U)
+/*! RXEMPTY - RX is empty
+ */
+#define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK)
+/*! @} */
+
+/*! @name MWDATAB - Master Write Data Byte Register */
+/*! @{ */
+#define I3C_MWDATAB_VALUE_MASK (0xFFU)
+#define I3C_MWDATAB_VALUE_SHIFT (0U)
+/*! VALUE - Data byte
+ */
+#define I3C_MWDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK)
+#define I3C_MWDATAB_END_MASK (0x100U)
+#define I3C_MWDATAB_END_SHIFT (8U)
+/*! END - End of message
+ */
+#define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK)
+#define I3C_MWDATAB_END_ALSO_MASK (0x10000U)
+#define I3C_MWDATAB_END_ALSO_SHIFT (16U)
+/*! END_ALSO - End of message also
+ */
+#define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK)
+/*! @} */
+
+/*! @name MWDATABE - Master Write Data Byte End Register */
+/*! @{ */
+#define I3C_MWDATABE_VALUE_MASK (0xFFU)
+#define I3C_MWDATABE_VALUE_SHIFT (0U)
+/*! VALUE - Data
+ */
+#define I3C_MWDATABE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK)
+/*! @} */
+
+/*! @name MWDATAH - Master Write Data Half-word Register */
+/*! @{ */
+#define I3C_MWDATAH_DATA0_MASK (0xFFU)
+#define I3C_MWDATAH_DATA0_SHIFT (0U)
+/*! DATA0 - Data byte 0
+ */
+#define I3C_MWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK)
+#define I3C_MWDATAH_DATA1_MASK (0xFF00U)
+#define I3C_MWDATAH_DATA1_SHIFT (8U)
+/*! DATA1 - Data byte 1
+ */
+#define I3C_MWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK)
+#define I3C_MWDATAH_END_MASK (0x10000U)
+#define I3C_MWDATAH_END_SHIFT (16U)
+/*! END - End of message
+ */
+#define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK)
+/*! @} */
+
+/*! @name MWDATAHE - Master Write Data Byte End Register */
+/*! @{ */
+#define I3C_MWDATAHE_DATA0_MASK (0xFFU)
+#define I3C_MWDATAHE_DATA0_SHIFT (0U)
+/*! DATA0 - DATA 0
+ */
+#define I3C_MWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK)
+#define I3C_MWDATAHE_DATA1_MASK (0xFF00U)
+#define I3C_MWDATAHE_DATA1_SHIFT (8U)
+/*! DATA1 - DATA 1
+ */
+#define I3C_MWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK)
+/*! @} */
+
+/*! @name MRDATAB - Master Read Data Byte Register */
+/*! @{ */
+#define I3C_MRDATAB_VALUE_MASK (0xFFU)
+#define I3C_MRDATAB_VALUE_SHIFT (0U)
+/*! VALUE - VALUE
+ */
+#define I3C_MRDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK)
+/*! @} */
+
+/*! @name MRDATAH - Master Read Data Half-word Register */
+/*! @{ */
+#define I3C_MRDATAH_LSB_MASK (0xFFU)
+#define I3C_MRDATAH_LSB_SHIFT (0U)
+/*! LSB - LSB
+ */
+#define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK)
+#define I3C_MRDATAH_MSB_MASK (0xFF00U)
+#define I3C_MRDATAH_MSB_SHIFT (8U)
+/*! MSB - MSB
+ */
+#define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK)
+/*! @} */
+
+/*! @name MWMSG_SDR_CONTROL - Master Write Message in SDR mode */
+/*! @{ */
+#define I3C_MWMSG_SDR_CONTROL_DIR_MASK (0x1U)
+#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT (0U)
+/*! DIR - Direction
+ * 0b0..Write
+ * 0b1..Read
+ */
+#define I3C_MWMSG_SDR_CONTROL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK)
+#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK (0xFEU)
+#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT (1U)
+/*! ADDR - Address to be written to
+ */
+#define I3C_MWMSG_SDR_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK)
+#define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U)
+#define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U)
+/*! END - End of SDR message
+ */
+#define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK)
+#define I3C_MWMSG_SDR_CONTROL_I2C_MASK (0x400U)
+#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT (10U)
+/*! I2C - I2C
+ * 0b0..I3C message
+ * 0b1..I2C message
+ */
+#define I3C_MWMSG_SDR_CONTROL_I2C(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK)
+#define I3C_MWMSG_SDR_CONTROL_LEN_MASK (0xF800U)
+#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT (11U)
+/*! LEN - Length
+ */
+#define I3C_MWMSG_SDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK)
+/*! @} */
+
+/*! @name MWMSG_SDR_DATA - Master Write Message Data in SDR mode */
+/*! @{ */
+#define I3C_MWMSG_SDR_DATA_DATA16B_MASK (0xFFFFU)
+#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT (0U)
+/*! DATA16B - Data
+ */
+#define I3C_MWMSG_SDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK)
+#define I3C_MWMSG_SDR_DATA_END_MASK (0x10000U)
+#define I3C_MWMSG_SDR_DATA_END_SHIFT (16U)
+/*! END - End of message
+ */
+#define I3C_MWMSG_SDR_DATA_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_END_SHIFT)) & I3C_MWMSG_SDR_DATA_END_MASK)
+/*! @} */
+
+/*! @name MRMSG_SDR - Master Read Message in SDR mode */
+/*! @{ */
+#define I3C_MRMSG_SDR_DATA_MASK (0xFFFFU)
+#define I3C_MRMSG_SDR_DATA_SHIFT (0U)
+/*! DATA - Data
+ */
+#define I3C_MRMSG_SDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK)
+/*! @} */
+
+/*! @name MWMSG_DDR_CONTROL - Master Write Message in DDR mode */
+/*! @{ */
+#define I3C_MWMSG_DDR_CONTROL_LEN_MASK (0x3FFU)
+#define I3C_MWMSG_DDR_CONTROL_LEN_SHIFT (0U)
+/*! LEN - Length of message
+ */
+#define I3C_MWMSG_DDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL_LEN_MASK)
+#define I3C_MWMSG_DDR_CONTROL_END_MASK (0x4000U)
+#define I3C_MWMSG_DDR_CONTROL_END_SHIFT (14U)
+/*! END - End of message
+ */
+#define I3C_MWMSG_DDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL_END_MASK)
+/*! @} */
+
+/*! @name MWMSG_DDR_DATA - Master Write Message Data in DDR mode */
+/*! @{ */
+#define I3C_MWMSG_DDR_DATA_DATA16B_MASK (0xFFFFU)
+#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT (0U)
+/*! DATA16B - Data
+ */
+#define I3C_MWMSG_DDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK)
+#define I3C_MWMSG_DDR_DATA_END_MASK (0x10000U)
+#define I3C_MWMSG_DDR_DATA_END_SHIFT (16U)
+/*! END - End of message
+ */
+#define I3C_MWMSG_DDR_DATA_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_END_SHIFT)) & I3C_MWMSG_DDR_DATA_END_MASK)
+/*! @} */
+
+/*! @name MRMSG_DDR - Master Read Message in DDR mode */
+/*! @{ */
+#define I3C_MRMSG_DDR_DATA_MASK (0xFFFFU)
+#define I3C_MRMSG_DDR_DATA_SHIFT (0U)
+/*! DATA - Data
+ */
+#define I3C_MRMSG_DDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK)
+#define I3C_MRMSG_DDR_CLEN_MASK (0x3FF0000U)
+#define I3C_MRMSG_DDR_CLEN_SHIFT (16U)
+/*! CLEN - Current length
+ */
+#define I3C_MRMSG_DDR_CLEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_CLEN_SHIFT)) & I3C_MRMSG_DDR_CLEN_MASK)
+/*! @} */
+
+/*! @name MDYNADDR - Master Dynamic Address Register */
+/*! @{ */
+#define I3C_MDYNADDR_DAVALID_MASK (0x1U)
+#define I3C_MDYNADDR_DAVALID_SHIFT (0U)
+/*! DAVALID - Dynamic address valid
+ */
+#define I3C_MDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK)
+#define I3C_MDYNADDR_DADDR_MASK (0xFEU)
+#define I3C_MDYNADDR_DADDR_SHIFT (1U)
+/*! DADDR - Dynamic address
+ */
+#define I3C_MDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK)
+/*! @} */
+
+/*! @name SID - Slave Module ID Register */
+/*! @{ */
+#define I3C_SID_ID_MASK (0xFFFFFFFFU)
+#define I3C_SID_ID_SHIFT (0U)
+/*! ID - ID
+ */
+#define I3C_SID_ID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I3C_Register_Masks */
+
+
+/* I3C - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral I3C0 base address */
+ #define I3C0_BASE (0x50036000u)
+ /** Peripheral I3C0 base address */
+ #define I3C0_BASE_NS (0x40036000u)
+ /** Peripheral I3C0 base pointer */
+ #define I3C0 ((I3C_Type *)I3C0_BASE)
+ /** Peripheral I3C0 base pointer */
+ #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS)
+ /** Peripheral I3C1 base address */
+ #define I3C1_BASE (0x50037000u)
+ /** Peripheral I3C1 base address */
+ #define I3C1_BASE_NS (0x40037000u)
+ /** Peripheral I3C1 base pointer */
+ #define I3C1 ((I3C_Type *)I3C1_BASE)
+ /** Peripheral I3C1 base pointer */
+ #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS)
+ /** Array initializer of I3C peripheral base addresses */
+ #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE }
+ /** Array initializer of I3C peripheral base pointers */
+ #define I3C_BASE_PTRS { I3C0, I3C1 }
+ /** Array initializer of I3C peripheral base addresses */
+ #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS }
+ /** Array initializer of I3C peripheral base pointers */
+ #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS }
+#else
+ /** Peripheral I3C0 base address */
+ #define I3C0_BASE (0x40036000u)
+ /** Peripheral I3C0 base pointer */
+ #define I3C0 ((I3C_Type *)I3C0_BASE)
+ /** Peripheral I3C1 base address */
+ #define I3C1_BASE (0x40037000u)
+ /** Peripheral I3C1 base pointer */
+ #define I3C1 ((I3C_Type *)I3C1_BASE)
+ /** Array initializer of I3C peripheral base addresses */
+ #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE }
+ /** Array initializer of I3C peripheral base pointers */
+ #define I3C_BASE_PTRS { I3C0, I3C1 }
+#endif
+/** Interrupt vectors for the I3C peripheral type */
+#define I3C_IRQS { I3C0_IRQn, I3C1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I3C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- INPUTMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
+ * @{
+ */
+
+/** INPUTMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SCT0_IN_SEL[7]; /**< SCT Peripheral Input multiplexer 0..SCT Peripheral Input multiplexer 6, array offset: 0x0, array step: 0x4 */
+ uint8_t RESERVED_0[228];
+ __IO uint32_t PINT_SEL[8]; /**< GPIO Pin Input Multiplexer 0..GPIO Pin Input Multiplexer 7, array offset: 0x100, array step: 0x4 */
+ uint8_t RESERVED_1[32];
+ __IO uint32_t DSP_INT_SEL[27]; /**< Fusion DSP Interrupt Input Multiplexer, array offset: 0x140, array step: 0x4 */
+ uint8_t RESERVED_2[84];
+ __IO uint32_t DMAC0_ITRIG_SEL[37]; /**< DMAC0 Input Trigger Select, array offset: 0x200, array step: 0x4 */
+ uint8_t RESERVED_3[108];
+ __IO uint32_t DMAC0_OTRIG_SEL[4]; /**< DMAC0 Output Trigger Select, array offset: 0x300, array step: 0x4 */
+ uint8_t RESERVED_4[16];
+ __IO uint32_t DMAC0_CHMUX_SEL[16]; /**< DMAC0 Channel mux select 0..DMAC0 Channel mux select 15, array offset: 0x320, array step: 0x4 */
+ uint8_t RESERVED_5[160];
+ __IO uint32_t DMAC1_ITRIG_SEL[37]; /**< DMAC1 Input Trigger Select, array offset: 0x400, array step: 0x4 */
+ uint8_t RESERVED_6[108];
+ __IO uint32_t DMAC1_OTRIG_SEL[4]; /**< DMAC1 Output Trigger Select, array offset: 0x500, array step: 0x4 */
+ uint8_t RESERVED_7[16];
+ __IO uint32_t DMAC1_CHMUX_SEL[16]; /**< DMAC1 Channel mux select 0..DMAC1 Channel mux select 15, array offset: 0x520, array step: 0x4 */
+ uint8_t RESERVED_8[160];
+ __IO uint32_t CT32BIT_CAP_SEL[5][4]; /**< CT32BIT Timer Capture Multiplexers, array offset: 0x600, array step: index*0x10, index2*0x4 */
+ uint8_t RESERVED_9[176];
+ __IO uint32_t FMEASURE_CH_SEL[2]; /**< Frequency Measurement Input Channel Multiplexers, array offset: 0x700, array step: 0x4 */
+ uint8_t RESERVED_10[24];
+ __IO uint32_t SMART_DMA_TRIG_CH_SEL[8]; /**< SMART_DMA trigger channel select, array offset: 0x720, array step: 0x4 */
+ __IO uint32_t DMAC0_REQ_ENA0; /**< DMAC0 request enable 0, offset: 0x740 */
+ __IO uint32_t DMAC0_REQ_ENA1; /**< DMAC0 request enable 1, offset: 0x744 */
+ __IO uint32_t DMAC0_REQ_ENA0_SET; /**< DMAC0 request enable set 0, offset: 0x748 */
+ __IO uint32_t DMAC0_REQ_ENA1_SET; /**< DMAC0 request enable set 1, offset: 0x74C */
+ __IO uint32_t DMAC0_REQ_ENA0_CLR; /**< DMAC0 request enable clear 0, offset: 0x750 */
+ __IO uint32_t DMAC0_REQ_ENA1_CLR; /**< DMAC0 request enable 1 clear, offset: 0x754 */
+ uint8_t RESERVED_11[8];
+ __IO uint32_t DMAC1_REQ_ENA0; /**< DMAC1 request enable 0, offset: 0x760 */
+ __IO uint32_t DMAC1_REQ_ENA1; /**< DMAC1 request enable 1, offset: 0x764 */
+ __IO uint32_t DMAC1_REQ_ENA0_SET; /**< DMAC1 request enable set 0, offset: 0x768 */
+ __IO uint32_t DMAC1_REQ_ENA1_SET; /**< DMAC1 request enable set 1, offset: 0x76C */
+ __IO uint32_t DMAC1_REQ_ENA0_CLR; /**< DMAC1 request enable clear 0, offset: 0x770 */
+ __IO uint32_t DMAC1_REQ_ENA1_CLR; /**< DMAC1 request enable 1 clear, offset: 0x774 */
+ uint8_t RESERVED_12[8];
+ __IO uint32_t DMAC0_ITRIG_ENA0; /**< DMAC0 Input Trigger Enable 0, offset: 0x780 */
+ uint8_t RESERVED_13[4];
+ __O uint32_t DMAC0_ITRIG_ENA0_SET; /**< DMAC0 Input Trigger Enable 0 Set, offset: 0x788 */
+ uint8_t RESERVED_14[4];
+ __O uint32_t DMAC0_ITRIG_ENA0_CLR; /**< DMAC0 Input Trigger Enable 0 Clear, offset: 0x790 */
+ uint8_t RESERVED_15[12];
+ __IO uint32_t DMAC1_ITRIG_ENA0; /**< DMAC1 Input Trigger Enable 0, offset: 0x7A0 */
+ uint8_t RESERVED_16[4];
+ __O uint32_t DMAC1_ITRIG_ENA0_SET; /**< DMAC1 Input Trigger Enable 0 set, offset: 0x7A8 */
+ uint8_t RESERVED_17[4];
+ __O uint32_t DMAC1_ITRIG_ENA0_CLR; /**< DMAC1 Input Trigger Enable 0 clear, offset: 0x7B0 */
+} INPUTMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- INPUTMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
+ * @{
+ */
+
+/*! @name SCT0_IN_SEL - SCT Peripheral Input multiplexer 0..SCT Peripheral Input multiplexer 6 */
+/*! @{ */
+#define INPUTMUX_SCT0_IN_SEL_SCT_IN_SEL_MASK (0x1FU)
+#define INPUTMUX_SCT0_IN_SEL_SCT_IN_SEL_SHIFT (0U)
+/*! SCT_IN_SEL - SCT0 Input Selection.
+ * 0b00000..SCT0_PIN_INP0
+ * 0b00001..SCT0_PIN_INP1
+ * 0b00010..SCT0_PIN_INP2
+ * 0b00011..SCT0_PIN_INP3
+ * 0b00100..SCT0_PIN_INP4
+ * 0b00101..SCT0_PIN_INP5
+ * 0b00110..SCT0_PIN_INP6
+ * 0b00111..SCT0_PIN_INP7
+ * 0b01000..CT32BIT0_MAT0
+ * 0b01001..CT32BIT1_MAT0
+ * 0b01010..CT32BIT2_MAT0
+ * 0b01011..CT32BIT3_MAT0
+ * 0b01100..CT32BIT4_MAT0
+ * 0b01101..ADCIRQ
+ * 0b01110..GPIOINT_BMATCH
+ * 0b01111..USB0_FRAME_TOGGLE
+ * 0b10000..CMP0_OUT
+ * 0b10001..SHARED I2S0_SCLK
+ * 0b10010..SHARED I2S1_SCLK
+ * 0b10011..SHARED I2S0_WS
+ * 0b10100..SHARED I2S1_WS
+ * 0b10101..MCLK
+ * 0b10110..ARM_TXEV
+ * 0b10111..DEBUG_HALTED
+ * 0b11000..Reserved
+ * 0b11001..Reserved
+ * 0b11010..Reserved
+ * 0b11011..Reserved
+ * 0b11100..Reserved
+ * 0b11101..Reserved
+ * 0b11110..Reserved
+ * 0b11111..Reserved
+ */
+#define INPUTMUX_SCT0_IN_SEL_SCT_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_IN_SEL_SCT_IN_SEL_SHIFT)) & INPUTMUX_SCT0_IN_SEL_SCT_IN_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_SCT0_IN_SEL */
+#define INPUTMUX_SCT0_IN_SEL_COUNT (7U)
+
+/*! @name PINT_SEL - GPIO Pin Input Multiplexer 0..GPIO Pin Input Multiplexer 7 */
+/*! @{ */
+#define INPUTMUX_PINT_SEL_PINT_SEL_MASK (0xFFU)
+#define INPUTMUX_PINT_SEL_PINT_SEL_SHIFT (0U)
+/*! PINT_SEL - Interrupt select
+ */
+#define INPUTMUX_PINT_SEL_PINT_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINT_SEL_PINT_SEL_SHIFT)) & INPUTMUX_PINT_SEL_PINT_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_PINT_SEL */
+#define INPUTMUX_PINT_SEL_COUNT (8U)
+
+/*! @name DSP_INT_SEL - Fusion DSP Interrupt Input Multiplexer */
+/*! @{ */
+#define INPUTMUX_DSP_INT_SEL_DSP_INT_SEL_MASK (0x3FU)
+#define INPUTMUX_DSP_INT_SEL_DSP_INT_SEL_SHIFT (0U)
+/*! DSP_INT_SEL
+ * 0b000000..FLEXCOMM0_IRQ
+ * 0b000001..FLEXCOMM1_IRQ
+ * 0b000010..FLEXCOMM2_IRQ
+ * 0b000011..FLEXCOMM3_IRQ
+ * 0b000100..FLEXCOMM4_IRQ
+ * 0b000101..FLEXCOMM5_IRQ
+ * 0b000110..FLEXCOMM6_IRQ
+ * 0b000111..FLEXCOMM7_IRQ
+ * 0b001000..FLEXCOMM14_IRQ
+ * 0b001001..FLEXCOMM16_IRQ
+ * 0b001010..GPIO_INT0_IRQ0
+ * 0b001011..GPIO_INT0_IRQ1
+ * 0b001100..GPIO_INT0_IRQ2
+ * 0b001101..GPIO_INT0_IRQ3
+ * 0b001110..GPIO_INT0_IRQ4
+ * 0b001111..GPIO_INT0_IRQ5
+ * 0b010000..GPIO_INT0_IRQ6
+ * 0b010001..GPIO_INT0_IRQ7
+ * 0b010010..NSHSGPIO_INT0_IRQ0
+ * 0b010011..NSHSGPIO_INT1_IRQ1
+ * 0b010100..WDT1
+ * 0b010101..DMAC0_IRQ
+ * 0b010110..DMAC1_IRQ
+ * 0b010111..MU_B_IRQ
+ * 0b011000..UTICK0_IRQ
+ * 0b011001..MRT0_IRQ
+ * 0b011010..OS_EVENT_TIMER or OS_EVENT_WAKEUP
+ * 0b011011..CTIMER0
+ * 0b011100..CTIMER1
+ * 0b011101..CTIMER2
+ * 0b011110..CTIMER3
+ * 0b011111..CTIMER4
+ * 0b100000..RTC_LITE0_ALARM or RTC_LITE0_WAKEUP
+ * 0b100001..I3C0
+ * 0b100010..I3C1
+ * 0b100011..DMIC0
+ * 0b100100..HWVAD
+ * 0b100101..LCDIF_IRQ
+ * 0b100110..GPU_IRQ
+ * 0b100111..SMARTDMA_IRQ
+ * 0b101000..FLEXIO_IRQ
+ */
+#define INPUTMUX_DSP_INT_SEL_DSP_INT_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DSP_INT_SEL_DSP_INT_SEL_SHIFT)) & INPUTMUX_DSP_INT_SEL_DSP_INT_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_DSP_INT_SEL */
+#define INPUTMUX_DSP_INT_SEL_COUNT (27U)
+
+/*! @name DMAC0_ITRIG_SEL - DMAC0 Input Trigger Select */
+/*! @{ */
+#define INPUTMUX_DMAC0_ITRIG_SEL_DMAC0_ITRIG_SEL_MASK (0x1FU)
+#define INPUTMUX_DMAC0_ITRIG_SEL_DMAC0_ITRIG_SEL_SHIFT (0U)
+/*! DMAC0_ITRIG_SEL - DMA Input Trigger Selection.
+ * 0b00000..GPIO_INT0
+ * 0b00001..GPIO_INT1
+ * 0b00010..GPIO_INT2
+ * 0b00011..GPIO_INT3
+ * 0b00100..T0_DMAREQ_M0
+ * 0b00101..T0_DMAREQ_M1
+ * 0b00110..T1_DMAREQ_M0
+ * 0b00111..T1_DMAREQ_M1
+ * 0b01000..T2_DMAREQ_M0
+ * 0b01001..T2_DMAREQ_M1
+ * 0b01010..T3_DMAREQ_M0
+ * 0b01011..T3_DMAREQ_M1
+ * 0b01100..T4_DMAREQ_M0
+ * 0b01101..T4_DMAREQ_M1
+ * 0b01110..DMA0_TRIGOUT_A
+ * 0b01111..DMA0_TRIGOUT_B
+ * 0b10000..DMA0_TRIGOUT_C
+ * 0b10001..DMA0_TRIGOUT_D
+ * 0b10010..SCT_DMAC0_REQ0
+ * 0b10011..SCT_DMAC1_REQ1
+ * 0b10100..HASHCRYPT_OUT_DMA
+ * 0b10101..ACMP_DMA
+ * 0b10110..FlexSPI0_RX_DMA
+ * 0b10111..FlexSPI0_TX_DMA
+ * 0b11000..ADC_DMA
+ * 0b11001..FlexSPI1_RX_DMA
+ * 0b11010..FlexSPI1_TX_DMA
+ * 0b11011..Reserved
+ * 0b11100..Reserved
+ * 0b11101..Reserved
+ * 0b11111..Reserved
+ */
+#define INPUTMUX_DMAC0_ITRIG_SEL_DMAC0_ITRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_SEL_DMAC0_ITRIG_SEL_SHIFT)) & INPUTMUX_DMAC0_ITRIG_SEL_DMAC0_ITRIG_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_DMAC0_ITRIG_SEL */
+#define INPUTMUX_DMAC0_ITRIG_SEL_COUNT (37U)
+
+/*! @name DMAC0_OTRIG_SEL - DMAC0 Output Trigger Select */
+/*! @{ */
+#define INPUTMUX_DMAC0_OTRIG_SEL_DMAC0_OTRIG_SEL_MASK (0x3FU)
+#define INPUTMUX_DMAC0_OTRIG_SEL_DMAC0_OTRIG_SEL_SHIFT (0U)
+/*! DMAC0_OTRIG_SEL
+ * 0b000000..DMAC0_OTRIG_CH0
+ * 0b000001..DMAC0_OTRIG_CH1
+ * 0b000010..DMAC0_OTRIG_CH2
+ * 0b000011..DMAC0_OTRIG_CH3
+ * 0b000100..DMAC0_OTRIG_CH4
+ * 0b000101..DMAC0_OTRIG_CH5
+ * 0b000110..DMAC0_OTRIG_CH6
+ * 0b000111..DMAC0_OTRIG_CH7
+ * 0b001000..DMAC0_OTRIG_CH8
+ * 0b001001..DMAC0_OTRIG_CH9
+ * 0b001010..DMAC0_OTRIG_CH10
+ * 0b001011..DMAC0_OTRIG_CH11
+ * 0b001100..DMAC0_OTRIG_CH12
+ * 0b001101..DMAC0_OTRIG_CH13
+ * 0b001110..DMAC0_OTRIG_CH14
+ * 0b001111..DMAC0_OTRIG_CH15
+ * 0b010000..DMAC0_OTRIG_CH16
+ * 0b010001..DMAC0_OTRIG_CH17
+ * 0b010010..DMAC0_OTRIG_CH18
+ * 0b010011..DMAC0_OTRIG_CH19
+ * 0b010100..DMAC0_OTRIG_CH20
+ * 0b010101..DMAC0_OTRIG_CH21
+ * 0b010110..DMAC0_OTRIG_CH22
+ * 0b010111..DMAC0_OTRIG_CH23
+ * 0b011000..DMAC0_OTRIG_CH24
+ * 0b011001..DMAC0_OTRIG_CH25
+ * 0b011010..DMAC0_OTRIG_CH26
+ * 0b011011..DMAC0_OTRIG_CH27
+ * 0b011100..DMAC0_OTRIG_CH28
+ * 0b011101..DMAC0_OTRIG_CH29
+ * 0b011110..DMAC0_OTRIG_CH30
+ * 0b011111..DMAC0_OTRIG_CH31
+ * 0b100000..DMAC0_OTRIG_CH32
+ * 0b100001..DMAC0_OTRIG_CH33
+ * 0b100010..DMAC0_OTRIG_CH34
+ * 0b100011..DMAC0_OTRIG_CH35
+ * 0b100100..DMAC0_OTRIG_CH36
+ */
+#define INPUTMUX_DMAC0_OTRIG_SEL_DMAC0_OTRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_OTRIG_SEL_DMAC0_OTRIG_SEL_SHIFT)) & INPUTMUX_DMAC0_OTRIG_SEL_DMAC0_OTRIG_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_DMAC0_OTRIG_SEL */
+#define INPUTMUX_DMAC0_OTRIG_SEL_COUNT (4U)
+
+/*! @name DMAC0_CHMUX_SEL - DMAC0 Channel mux select 0..DMAC0 Channel mux select 15 */
+/*! @{ */
+#define INPUTMUX_DMAC0_CHMUX_SEL_DMAC0_CHMUX_SEL_MASK (0x1U)
+#define INPUTMUX_DMAC0_CHMUX_SEL_DMAC0_CHMUX_SEL_SHIFT (0U)
+/*! DMAC0_CHMUX_SEL - DMAC0 Channel mux select 1
+ * 0b0..DMIC_CH0_DMA
+ * 0b1..FLEXCOM8_RX_DMA
+ */
+#define INPUTMUX_DMAC0_CHMUX_SEL_DMAC0_CHMUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_CHMUX_SEL_DMAC0_CHMUX_SEL_SHIFT)) & INPUTMUX_DMAC0_CHMUX_SEL_DMAC0_CHMUX_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_DMAC0_CHMUX_SEL */
+#define INPUTMUX_DMAC0_CHMUX_SEL_COUNT (16U)
+
+/*! @name DMAC1_ITRIG_SEL - DMAC1 Input Trigger Select */
+/*! @{ */
+#define INPUTMUX_DMAC1_ITRIG_SEL_DMAC1_ITRIG_SEL_MASK (0x1FU)
+#define INPUTMUX_DMAC1_ITRIG_SEL_DMAC1_ITRIG_SEL_SHIFT (0U)
+/*! DMAC1_ITRIG_SEL - DMA Input Trigger Selection.
+ * 0b00000..GPIO_INT0
+ * 0b00001..GPIO_INT1
+ * 0b00010..GPIO_INT2
+ * 0b00011..GPIO_INT3
+ * 0b00100..T0_DMAREQ_M0
+ * 0b00101..T0_DMAREQ_M1
+ * 0b00110..T1_DMAREQ_M0
+ * 0b00111..T1_DMAREQ_M1
+ * 0b01000..T2_DMAREQ_M0
+ * 0b01001..T2_DMAREQ_M1
+ * 0b01010..T3_DMAREQ_M0
+ * 0b01011..T3_DMAREQ_M1
+ * 0b01100..T4_DMAREQ_M0
+ * 0b01101..T4_DMAREQ_M1
+ * 0b01110..DMA0_TRIGOUT_A
+ * 0b01111..DMA0_TRIGOUT_B
+ * 0b10000..DMA0_TRIGOUT_C
+ * 0b10001..DMA0_TRIGOUT_D
+ * 0b10010..SCT_DMAC0_REQ0
+ * 0b10011..SCT_DMAC1_REQ1
+ * 0b10100..HASHCRYPT_OUT_DMA
+ * 0b10101..ACMP_DMA
+ * 0b10110..FlexSPI0_RX_DMA
+ * 0b10111..FlexSPI0_TX_DMA
+ * 0b11000..ADC_DMA
+ * 0b11001..FlexSPI1_RX_DMA
+ * 0b11010..FlexSPI1_TX_DMA
+ * 0b11011..Reserved
+ * 0b11100..Reserved
+ * 0b11101..Reserved
+ * 0b11111..Reserved
+ */
+#define INPUTMUX_DMAC1_ITRIG_SEL_DMAC1_ITRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_SEL_DMAC1_ITRIG_SEL_SHIFT)) & INPUTMUX_DMAC1_ITRIG_SEL_DMAC1_ITRIG_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_DMAC1_ITRIG_SEL */
+#define INPUTMUX_DMAC1_ITRIG_SEL_COUNT (37U)
+
+/*! @name DMAC1_OTRIG_SEL - DMAC1 Output Trigger Select */
+/*! @{ */
+#define INPUTMUX_DMAC1_OTRIG_SEL_DMAC1_OTRIG_SEL_MASK (0x3FU)
+#define INPUTMUX_DMAC1_OTRIG_SEL_DMAC1_OTRIG_SEL_SHIFT (0U)
+/*! DMAC1_OTRIG_SEL - DMA Output Trigger Selection.
+ * 0b000000..DMAC1_OTRIG_CH0
+ * 0b000001..DMAC1_OTRIG_CH1
+ * 0b000010..DMAC1_OTRIG_CH2
+ * 0b000011..DMAC1_OTRIG_CH3
+ * 0b000100..DMAC1_OTRIG_CH4
+ * 0b000101..DMAC1_OTRIG_CH5
+ * 0b000110..DMAC1_OTRIG_CH6
+ * 0b000111..DMAC1_OTRIG_CH7
+ * 0b001000..DMAC1_OTRIG_CH8
+ * 0b001001..DMAC1_OTRIG_CH9
+ * 0b001010..DMAC1_OTRIG_CH10
+ * 0b001011..DMAC1_OTRIG_CH11
+ * 0b001100..DMAC1_OTRIG_CH12
+ * 0b001101..DMAC1_OTRIG_CH13
+ * 0b001110..DMAC1_OTRIG_CH14
+ * 0b001111..DMAC1_OTRIG_CH15
+ * 0b010000..DMAC1_OTRIG_CH16
+ * 0b010001..DMAC1_OTRIG_CH17
+ * 0b010010..DMAC1_OTRIG_CH18
+ * 0b010011..DMAC1_OTRIG_CH19
+ * 0b010100..DMAC1_OTRIG_CH20
+ * 0b010101..DMAC1_OTRIG_CH21
+ * 0b010110..DMAC1_OTRIG_CH22
+ * 0b010111..DMAC1_OTRIG_CH23
+ * 0b011000..DMAC1_OTRIG_CH24
+ * 0b011001..DMAC1_OTRIG_CH25
+ * 0b011010..DMAC1_OTRIG_CH26
+ * 0b011011..DMAC1_OTRIG_CH27
+ * 0b011100..DMAC1_OTRIG_CH28
+ * 0b011101..DMAC1_OTRIG_CH29
+ * 0b011110..DMAC1_OTRIG_CH30
+ * 0b011111..DMAC1_OTRIG_CH31
+ * 0b100000..DMAC1_OTRIG_CH32
+ * 0b100001..DMAC1_OTRIG_CH33
+ * 0b100010..DMAC1_OTRIG_CH34
+ * 0b100011..DMAC1_OTRIG_CH35
+ * 0b100100..DMAC1_OTRIG_CH36
+ */
+#define INPUTMUX_DMAC1_OTRIG_SEL_DMAC1_OTRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_OTRIG_SEL_DMAC1_OTRIG_SEL_SHIFT)) & INPUTMUX_DMAC1_OTRIG_SEL_DMAC1_OTRIG_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_DMAC1_OTRIG_SEL */
+#define INPUTMUX_DMAC1_OTRIG_SEL_COUNT (4U)
+
+/*! @name DMAC1_CHMUX_SEL - DMAC1 Channel mux select 0..DMAC1 Channel mux select 15 */
+/*! @{ */
+#define INPUTMUX_DMAC1_CHMUX_SEL_DMAC1_CHMUX_SEL_MASK (0x1U)
+#define INPUTMUX_DMAC1_CHMUX_SEL_DMAC1_CHMUX_SEL_SHIFT (0U)
+/*! DMAC1_CHMUX_SEL - DMAC1 Channel mux select
+ * 0b0..DMIC_CH0_DMA
+ * 0b1..FLEXCOM8_RX_DMA
+ */
+#define INPUTMUX_DMAC1_CHMUX_SEL_DMAC1_CHMUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_CHMUX_SEL_DMAC1_CHMUX_SEL_SHIFT)) & INPUTMUX_DMAC1_CHMUX_SEL_DMAC1_CHMUX_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_DMAC1_CHMUX_SEL */
+#define INPUTMUX_DMAC1_CHMUX_SEL_COUNT (16U)
+
+/*! @name CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL - CT32BIT Timer Capture Multiplexers */
+/*! @{ */
+#define INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL_CAPn_SEL_MASK (0x1FU)
+#define INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL_CAPn_SEL_SHIFT (0U)
+/*! CAPn_SEL - Counter Timer n, Capture Input m
+ * 0b00000..CT_INP0 (function must be selected in IOPCTL)
+ * 0b00001..CT_INP1 (function must be selected in IOPCTL)
+ * 0b00010..CT_INP2 (function must be selected in IOPCTL)
+ * 0b00011..CT_INP3 (function must be selected in IOPCTL)
+ * 0b00100..CT_INP4 (function must be selected in IOPCTL)
+ * 0b00101..CT_INP5 (function must be selected in IOPCTL)
+ * 0b00110..CT_INP6 (function must be selected in IOPCTL)
+ * 0b00111..CT_INP7 (function must be selected in IOPCTL)
+ * 0b01000..CT_INP8 (function must be selected in IOPCTL)
+ * 0b01001..CT_INP9 (function must be selected in IOPCTL)
+ * 0b01010..CT_INP10 (function must be selected in IOPCTL)
+ * 0b01011..CT_INP11 (function must be selected in IOPCTL)
+ * 0b01100..CT_INP12 (function must be selected in IOPCTL)
+ * 0b01101..CT_INP13 (function must be selected in IOPCTL)
+ * 0b01110..CT_INP14 (function must be selected in IOPCTL)
+ * 0b01111..CT_INP15 (function must be selected in IOPCTL)
+ * 0b10000..SHARED I2S0_WS
+ * 0b10001..SHARED I2S1_WS
+ * 0b10010..USB1_FRAME_TOGGLE (see USB Controller Chapter)
+ */
+#define INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL_CAPn_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL_CAPn_SEL_SHIFT)) & INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL_CAPn_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL */
+#define INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL_COUNT (5U)
+
+/* The count of INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL */
+#define INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL_COUNT2 (4U)
+
+/*! @name FMEASURE_CH_SEL - Frequency Measurement Input Channel Multiplexers */
+/*! @{ */
+#define INPUTMUX_FMEASURE_CH_SEL_FMEASURE_SEL_MASK (0x1FU)
+#define INPUTMUX_FMEASURE_CH_SEL_FMEASURE_SEL_SHIFT (0U)
+/*! FMEASURE_SEL - Frequency Measure Channel Selection
+ * 0b00000..OSC_CLK
+ * 0b00001..FRO_DIV16
+ * 0b00010..FRO_DIV1
+ * 0b00011..Low Power Oscillator Clock (LPOSC)
+ * 0b00100..RTC 32 kHz OSC
+ * 0b00101..Main SYSCLK
+ * 0b00110..FREQME_GPIO_CLK
+ * 0b00111..Reserved
+ * 0b01000..Reserved
+ * 0b01001..Reserved
+ * 0b01010..Reserved
+ * 0b01011..Clock Out
+ * 0b01100..Reserved
+ * 0b01101..Reserved
+ * 0b01110..Reserved
+ * 0b01111..Reserved
+ * 0b10000..Reserved
+ * 0b10001..Reserved
+ */
+#define INPUTMUX_FMEASURE_CH_SEL_FMEASURE_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FMEASURE_CH_SEL_FMEASURE_SEL_SHIFT)) & INPUTMUX_FMEASURE_CH_SEL_FMEASURE_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_FMEASURE_CH_SEL */
+#define INPUTMUX_FMEASURE_CH_SEL_COUNT (2U)
+
+/*! @name SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL - SMART_DMA trigger channel select */
+/*! @{ */
+#define INPUTMUX_SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL_SMART_DMA_IN_SEL_MASK (0x7FU)
+#define INPUTMUX_SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL_SMART_DMA_IN_SEL_SHIFT (0U)
+/*! SMART_DMA_IN_SEL - SMART_DMA Input(n) Selection
+ */
+#define INPUTMUX_SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL_SMART_DMA_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL_SMART_DMA_IN_SEL_SHIFT)) & INPUTMUX_SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL_SMART_DMA_IN_SEL_MASK)
+/*! @} */
+
+/* The count of INPUTMUX_SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL */
+#define INPUTMUX_SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL_COUNT (8U)
+
+/*! @name DMAC0_REQ_ENA0 - DMAC0 request enable 0 */
+/*! @{ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_RX_MASK (0x1U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_RX_SHIFT (0U)
+/*! FLEXCOMM0_RX - FLEXCOMM0 RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_TX_MASK (0x2U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_TX_SHIFT (1U)
+/*! FLEXCOMM0_TX - FLEXCOMM0 TX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_RX_MASK (0x4U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_RX_SHIFT (2U)
+/*! FLEXCOMM1_RX - FLEXCOMM1 RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_TX_MASK (0x8U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_TX_SHIFT (3U)
+/*! FLEXCOMM1_TX - FLEXCOMM1 TX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_RX_MASK (0x10U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_RX_SHIFT (4U)
+/*! FLEXCOMM2_RX - FLEXCOMM2 RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_TX_MASK (0x20U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_TX_SHIFT (5U)
+/*! FLEXCOMM2_TX - FLEXCOMM2 TX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_RX_MASK (0x40U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_RX_SHIFT (6U)
+/*! FLEXCOMM3_RX - FLEXCOMM3 RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_TX_MASK (0x80U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_TX_SHIFT (7U)
+/*! FLEXCOMM3_TX - FLEXCOMM3 TX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_RX_MASK (0x100U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_RX_SHIFT (8U)
+/*! FLEXCOMM4_RX - FLEXCOMM4 RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_TX_MASK (0x200U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_TX_SHIFT (9U)
+/*! FLEXCOMM4_TX - FLEXCOMM4 TX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_RX_MASK (0x400U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_RX_SHIFT (10U)
+/*! FLEXCOMM5_RX - FLEXCOMM5 RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_TX_MASK (0x800U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_TX_SHIFT (11U)
+/*! FLEXCOMM5_TX - FLEXCOMM5 TX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_RX_MASK (0x1000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_RX_SHIFT (12U)
+/*! FLEXCOMM6_RX - FLEXCOMM6 RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_TX_MASK (0x2000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_TX_SHIFT (13U)
+/*! FLEXCOMM6_TX - FLEXCOMM6 TX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_RX_MASK (0x4000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_RX_SHIFT (14U)
+/*! FLEXCOMM7_RX - FLEXCOMM7 RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_TX_MASK (0x8000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_TX_SHIFT (15U)
+/*! FLEXCOMM7_TX - FLEXCOMM7 TX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK (0x10000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT (16U)
+/*! DMIC0_CH0_FLEXCOMM8_RX_DMA - DMIC0 channel 0 / FLEXCOMM8 RX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK (0x20000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT (17U)
+/*! DMIC0_CH1_FLEXCOMM8_TX_DMA - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK (0x40000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT (18U)
+/*! DMIC0_CH2_FLEXCOMM9_RX_DMA - DMIC0 channel 2 / FLEXCOMM9 RX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK (0x80000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT (19U)
+/*! DMIC0_CH3_FLEXCOMM9_TX_DMA - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK (0x100000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT (20U)
+/*! DMIC0_CH4_FLEXCOMM10_RX_DMA - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK (0x200000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT (21U)
+/*! DMIC0_CH5_FLEXCOMM10_TX_DMA - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK (0x400000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT (22U)
+/*! DMIC0_CH6_FLEXCOMM13_RX_DMA - DMIC0 channel 6 / FLEXCOMM13 RX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK (0x800000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT (23U)
+/*! DMIC0_CH7_FLEXCOMM13_TX_DMA - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_I3C0_RX_MASK (0x1000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_I3C0_RX_SHIFT (24U)
+/*! I3C0_RX - I3C RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_I3C0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_I3C0_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_I3C0_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_I3C0_TX_MASK (0x2000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_I3C0_TX_SHIFT (25U)
+/*! I3C0_TX - I3C TX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_I3C0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_I3C0_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_I3C0_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_RX_MASK (0x4000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_RX_SHIFT (26U)
+/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_TX_MASK (0x8000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_TX_SHIFT (27U)
+/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_RX_MASK (0x10000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_RX_SHIFT (28U)
+/*! FLEXCOMM16_RX - FLEXCOMM16 RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_TX_MASK (0x20000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_TX_SHIFT (29U)
+/*! FLEXCOMM16_TX - FLEXCOMM16 TX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_I3C1_RX_MASK (0x40000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_I3C1_RX_SHIFT (30U)
+/*! I3C1_RX - I3C1_RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_I3C1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_I3C1_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_I3C1_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_I3C1_TX_MASK (0x80000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_I3C1_TX_SHIFT (31U)
+/*! I3C1_TX - I3C1_TX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_I3C1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_I3C1_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_I3C1_TX_MASK)
+/*! @} */
+
+/*! @name DMAC0_REQ_ENA1 - DMAC0 request enable 1 */
+/*! @{ */
+#define INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM11_RX_MASK (0x1U)
+#define INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM11_RX_SHIFT (0U)
+/*! FLEXCOMM11_RX - FLEXCOMM11_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM11_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM11_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM11_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM11_TX_MASK (0x2U)
+#define INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM11_TX_SHIFT (1U)
+/*! FLEXCOMM11_TX - FLEXCOMM11_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM11_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM11_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM11_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM12_RX_MASK (0x4U)
+#define INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM12_RX_SHIFT (2U)
+/*! FLEXCOMM12_RX - FLEXCOMM12_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM12_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM12_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM12_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM12_TX_MASK (0x8U)
+#define INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM12_TX_SHIFT (3U)
+/*! FLEXCOMM12_TX - FLEXCOMM12_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM12_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM12_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_FLEXCOMM12_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA1_HASHCRYPT_IN_MASK (0x10U)
+#define INPUTMUX_DMAC0_REQ_ENA1_HASHCRYPT_IN_SHIFT (4U)
+/*! HASHCRYPT_IN - HASHCRYPT_IN
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_REQ_ENA1_HASHCRYPT_IN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_HASHCRYPT_IN_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_HASHCRYPT_IN_MASK)
+/*! @} */
+
+/*! @name DMAC0_REQ_ENA0_SET - DMAC0 request enable set 0 */
+/*! @{ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_RX_MASK (0x1U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_RX_SHIFT (0U)
+/*! FLEXCOMM0_RX - FLEXCOMM0 RX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_TX_MASK (0x2U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_TX_SHIFT (1U)
+/*! FLEXCOMM0_TX - FLEXCOMM0 TX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_RX_MASK (0x4U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_RX_SHIFT (2U)
+/*! FLEXCOMM1_RX - FLEXCOMM1 RX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_TX_MASK (0x8U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_TX_SHIFT (3U)
+/*! FLEXCOMM1_TX - FLEXCOMM1 TX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_RX_MASK (0x10U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_RX_SHIFT (4U)
+/*! FLEXCOMM2_RX - FLEXCOMM2 RX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_TX_MASK (0x20U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_TX_SHIFT (5U)
+/*! FLEXCOMM2_TX - FLEXCOMM2 TX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_RX_MASK (0x40U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_RX_SHIFT (6U)
+/*! FLEXCOMM3_RX - FLEXCOMM3 RX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_TX_MASK (0x80U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_TX_SHIFT (7U)
+/*! FLEXCOMM3_TX - FLEXCOMM3 TX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_RX_MASK (0x100U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_RX_SHIFT (8U)
+/*! FLEXCOMM4_RX - FLEXCOMM4 RX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_TX_MASK (0x200U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_TX_SHIFT (9U)
+/*! FLEXCOMM4_TX - FLEXCOMM4 TX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_RX_MASK (0x400U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_RX_SHIFT (10U)
+/*! FLEXCOMM5_RX - FLEXCOMM5 RX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_TX_MASK (0x800U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_TX_SHIFT (11U)
+/*! FLEXCOMM5_TX - FLEXCOMM5 TX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_RX_MASK (0x1000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_RX_SHIFT (12U)
+/*! FLEXCOMM6_RX - FLEXCOMM6 RX enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_TX_MASK (0x2000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_TX_SHIFT (13U)
+/*! FLEXCOMM6_TX - FLEXCOMM6 TX enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_RX_MASK (0x4000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_RX_SHIFT (14U)
+/*! FLEXCOMM7_RX - FLEXCOMM7 RX enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_TX_MASK (0x8000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_TX_SHIFT (15U)
+/*! FLEXCOMM7_TX - FLEXCOMM7 TX enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK (0x10000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT (16U)
+/*! DMIC0_CH0_FLEXCOMM8_RX_DMA - DMIC0 channel 0 / FLEXCOMM8 RX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK (0x20000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT (17U)
+/*! DMIC0_CH1_FLEXCOMM8_TX_DMA - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK (0x40000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT (18U)
+/*! DMIC0_CH2_FLEXCOMM9_RX_DMA - DMIC0 channel 2 / FLEXCOMM9 RX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK (0x80000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT (19U)
+/*! DMIC0_CH3_FLEXCOMM9_TX_DMA - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK (0x100000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT (20U)
+/*! DMIC0_CH4_FLEXCOMM10_RX_DMA - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK (0x200000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT (21U)
+/*! DMIC0_CH5_FLEXCOMM10_TX_DMA - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK (0x400000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT (22U)
+/*! DMIC0_CH6_FLEXCOMM13_RX_DMA - DMIC0 channel 6 / FLEXCOMM10 RX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK (0x800000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT (23U)
+/*! DMIC0_CH7_FLEXCOMM13_TX_DMA - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH7_FLEXCOMM13_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_RX_MASK (0x1000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_RX_SHIFT (24U)
+/*! I3C0_RX - I3C RX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_TX_MASK (0x2000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_TX_SHIFT (25U)
+/*! I3C0_TX - I3C TX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_RX_MASK (0x4000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_RX_SHIFT (26U)
+/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_TX_MASK (0x8000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_TX_SHIFT (27U)
+/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_RX_MASK (0x10000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_RX_SHIFT (28U)
+/*! FLEXCOMM16_RX - FLEXCOMM16 RX enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_TX_MASK (0x20000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_TX_SHIFT (29U)
+/*! FLEXCOMM16_TX - FLEXCOMM16 RX enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_RX_MASK (0x40000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_RX_SHIFT (30U)
+/*! I3C1_RX - I3C1_RX enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_TX_MASK (0x80000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_TX_SHIFT (31U)
+/*! I3C1_TX - I3C1_TX enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_TX_MASK)
+/*! @} */
+
+/*! @name DMAC0_REQ_ENA1_SET - DMAC0 request enable set 1 */
+/*! @{ */
+#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM11_RX_MASK (0x1U)
+#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM11_RX_SHIFT (0U)
+/*! FLEXCOMM11_RX - FLEXCOMM11_RX
+ * 0b0..No Effect
+ * 0b1..Sets the ENA1 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM11_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM11_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM11_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM11_TX_MASK (0x2U)
+#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM11_TX_SHIFT (1U)
+/*! FLEXCOMM11_TX - FLEXCOMM11_TX
+ * 0b0..No Effect
+ * 0b1..Sets the ENA1 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM11_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM11_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM11_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM12_RX_MASK (0x4U)
+#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM12_RX_SHIFT (2U)
+/*! FLEXCOMM12_RX - FLEXCOMM12_RX
+ * 0b0..No Effect
+ * 0b1..Sets the ENA1 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM12_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM12_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM12_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM12_TX_MASK (0x8U)
+#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM12_TX_SHIFT (3U)
+/*! FLEXCOMM12_TX - FLEXCOMM12_TX
+ * 0b0..No Effect
+ * 0b1..Sets the ENA1 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM12_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM12_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXCOMM12_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA1_SET_HASHCRYPT_IN_MASK (0x10U)
+#define INPUTMUX_DMAC0_REQ_ENA1_SET_HASHCRYPT_IN_SHIFT (4U)
+/*! HASHCRYPT_IN - HASHCRYPT_IN
+ * 0b0..No Effect
+ * 0b1..Sets the ENA1 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA1_SET_HASHCRYPT_IN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_SET_HASHCRYPT_IN_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_SET_HASHCRYPT_IN_MASK)
+/*! @} */
+
+/*! @name DMAC0_REQ_ENA0_CLR - DMAC0 request enable clear 0 */
+/*! @{ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_RX_MASK (0x1U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_RX_SHIFT (0U)
+/*! FLEXCOMM0_RX - FLEXCOMM0 RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_TX_MASK (0x2U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_TX_SHIFT (1U)
+/*! FLEXCOMM0_TX - FLEXCOMM0 TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_RX_MASK (0x4U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_RX_SHIFT (2U)
+/*! FLEXCOMM1_RX - FLEXCOMM1 RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_TX_MASK (0x8U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_TX_SHIFT (3U)
+/*! FLEXCOMM1_TX - FLEXCOMM1 TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_RX_MASK (0x10U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_RX_SHIFT (4U)
+/*! FLEXCOMM2_RX - FLEXCOMM2 RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_TX_MASK (0x20U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_TX_SHIFT (5U)
+/*! FLEXCOMM2_TX - FLEXCOMM2 TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_RX_MASK (0x40U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_RX_SHIFT (6U)
+/*! FLEXCOMM3_RX - FLEXCOMM3 RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_TX_MASK (0x80U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_TX_SHIFT (7U)
+/*! FLEXCOMM3_TX - FLEXCOMM3 TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_RX_MASK (0x100U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_RX_SHIFT (8U)
+/*! FLEXCOMM4_RX - FLEXCOMM4 RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_TX_MASK (0x200U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_TX_SHIFT (9U)
+/*! FLEXCOMM4_TX - FLEXCOMM4 TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_RX_MASK (0x400U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_RX_SHIFT (10U)
+/*! FLEXCOMM5_RX - FLEXCOMM5 RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_TX_MASK (0x800U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_TX_SHIFT (11U)
+/*! FLEXCOMM5_TX - FLEXCOMM5 TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_RX_MASK (0x1000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_RX_SHIFT (12U)
+/*! FLEXCOMM6_RX - FLEXCOMM6 RX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_TX_MASK (0x2000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_TX_SHIFT (13U)
+/*! FLEXCOMM6_TX - FLEXCOMM6 TX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_RX_MASK (0x4000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_RX_SHIFT (14U)
+/*! FLEXCOMM7_RX - FLEXCOMM7 RX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_TX_MASK (0x8000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_TX_SHIFT (15U)
+/*! FLEXCOMM7_TX - FLEXCOMM7 TX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK (0x10000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT (16U)
+/*! DMIC0_CH0_FLEXCOMM8_RX_DMA - DMIC0 channel 0 / FLEXCOMM8 RX DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK (0x20000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT (17U)
+/*! DMIC0_CH1_FLEXCOMM8_TX_DMA - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK (0x40000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT (18U)
+/*! DMIC0_CH2_FLEXCOMM9_RX_DMA - DMIC0 channel 2 / FLEXCOMM9 RX DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK (0x80000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT (19U)
+/*! DMIC0_CH3_FLEXCOMM9_TX_DMA - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK (0x100000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT (20U)
+/*! DMIC0_CH4_FLEXCOMM10_RX_DMA - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK (0x200000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT (21U)
+/*! DMIC0_CH5_FLEXCOMM10_TX_DMA - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK (0x400000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT (22U)
+/*! DMIC0_CH6_FLEXCOMM13_RX_DMA - DMIC0 channel 6 / FLEXCOMM13 RX DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK (0x800000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT (23U)
+/*! DMIC0_CH7_FLEXCOMM13_TX_DMA - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_RX_MASK (0x1000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_RX_SHIFT (24U)
+/*! I3C0_RX - I3C RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_TX_MASK (0x2000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_TX_SHIFT (25U)
+/*! I3C0_TX - I3C TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_RX_MASK (0x4000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_RX_SHIFT (26U)
+/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_TX_MASK (0x8000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_TX_SHIFT (27U)
+/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_RX_MASK (0x10000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_RX_SHIFT (28U)
+/*! FLEXCOMM16_RX - FLEXCOMM16 RX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_TX_MASK (0x20000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_TX_SHIFT (29U)
+/*! FLEXCOMM16_TX - FLEXCOMM16 TX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_RX_MASK (0x40000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_RX_SHIFT (30U)
+/*! I3C1_RX - I3C1_RX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_TX_MASK (0x80000000U)
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_TX_SHIFT (31U)
+/*! I3C1_TX - I3C1_TX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_TX_MASK)
+/*! @} */
+
+/*! @name DMAC0_REQ_ENA1_CLR - DMAC0 request enable 1 clear */
+/*! @{ */
+#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM11_RX_MASK (0x1U)
+#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM11_RX_SHIFT (0U)
+/*! FLEXCOMM11_RX - FLEXCOMM11_RX
+ * 0b0..No effect
+ * 0b1..Clears the ENA1 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM11_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM11_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM11_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM11_TX_MASK (0x2U)
+#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM11_TX_SHIFT (1U)
+/*! FLEXCOMM11_TX - FLEXCOMM11_TX
+ * 0b0..No effect
+ * 0b1..Clears the ENA1 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM11_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM11_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM11_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM12_RX_MASK (0x4U)
+#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM12_RX_SHIFT (2U)
+/*! FLEXCOMM12_RX - FLEXCOMM12_RX
+ * 0b0..No effect
+ * 0b1..Clears the ENA1 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM12_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM12_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM12_RX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM12_TX_MASK (0x8U)
+#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM12_TX_SHIFT (3U)
+/*! FLEXCOMM12_TX - FLEXCOMM12_TX
+ * 0b0..No effect
+ * 0b1..Clears the ENA1 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM12_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM12_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXCOMM12_TX_MASK)
+#define INPUTMUX_DMAC0_REQ_ENA1_CLR_HASHCRYPT_IN_MASK (0x10U)
+#define INPUTMUX_DMAC0_REQ_ENA1_CLR_HASHCRYPT_IN_SHIFT (4U)
+/*! HASHCRYPT_IN - HASHCRYPT_IN
+ * 0b0..No effect
+ * 0b1..Clears the ENA1 Bit
+ */
+#define INPUTMUX_DMAC0_REQ_ENA1_CLR_HASHCRYPT_IN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_CLR_HASHCRYPT_IN_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_CLR_HASHCRYPT_IN_MASK)
+/*! @} */
+
+/*! @name DMAC1_REQ_ENA0 - DMAC1 request enable 0 */
+/*! @{ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_RX_MASK (0x1U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_RX_SHIFT (0U)
+/*! FLEXCOMM0_RX - FLEXCOMM0_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_TX_MASK (0x2U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_TX_SHIFT (1U)
+/*! FLEXCOMM0_TX - FLEXCOMM0_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_RX_MASK (0x4U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_RX_SHIFT (2U)
+/*! FLEXCOMM1_RX - FLEXCOMM1_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_TX_MASK (0x8U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_TX_SHIFT (3U)
+/*! FLEXCOMM1_TX - FLEXCOMM1_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_RX_MASK (0x10U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_RX_SHIFT (4U)
+/*! FLEXCOMM2_RX - FLEXCOMM2_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_TX_MASK (0x20U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_TX_SHIFT (5U)
+/*! FLEXCOMM2_TX - FLEXCOMM2_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_RX_MASK (0x40U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_RX_SHIFT (6U)
+/*! FLEXCOMM3_RX - FLEXCOMM3_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_TX_MASK (0x80U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_TX_SHIFT (7U)
+/*! FLEXCOMM3_TX - FLEXCOMM3_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_RX_MASK (0x100U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_RX_SHIFT (8U)
+/*! FLEXCOMM4_RX - FLEXCOMM4_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_TX_MASK (0x200U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_TX_SHIFT (9U)
+/*! FLEXCOMM4_TX - FLEXCOMM4_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_RX_MASK (0x400U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_RX_SHIFT (10U)
+/*! FLEXCOMM5_RX - FLEXCOMM5_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_TX_MASK (0x800U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_TX_SHIFT (11U)
+/*! FLEXCOMM5_TX - FLEXCOMM5_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_RX_MASK (0x1000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_RX_SHIFT (12U)
+/*! FLEXCOMM6_RX - FLEXCOMM6_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_TX_MASK (0x2000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_TX_SHIFT (13U)
+/*! FLEXCOMM6_TX - FLEXCOMM6_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_RX_MASK (0x4000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_RX_SHIFT (14U)
+/*! FLEXCOMM7_RX - FLEXCOMM7_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_TX_MASK (0x8000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_TX_SHIFT (15U)
+/*! FLEXCOMM7_TX - FLEXCOMM7_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK (0x10000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT (16U)
+/*! DMIC0_CH0_FLEXCOMM8_RX_DMA - DMIC0 channel 0 / FLEXCOMM8 RX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK (0x20000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT (17U)
+/*! DMIC0_CH1_FLEXCOMM8_TX_DMA - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK (0x40000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT (18U)
+/*! DMIC0_CH2_FLEXCOMM9_RX_DMA - DMIC0 channel 2/ FLEXCOMM9 RX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK (0x80000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT (19U)
+/*! DMIC0_CH3_FLEXCOMM9_TX_DMA - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK (0x100000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT (20U)
+/*! DMIC0_CH4_FLEXCOMM10_RX_DMA - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK (0x200000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT (21U)
+/*! DMIC0_CH5_FLEXCOMM10_TX_DMA - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK (0x400000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT (22U)
+/*! DMIC0_CH6_FLEXCOMM13_RX_DMA - DMIC0 channel 6 / FLEXCOMM13 RX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK (0x800000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT (23U)
+/*! DMIC0_CH7_FLEXCOMM13_TX_DMA - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_I3C0_RX_MASK (0x1000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_I3C0_RX_SHIFT (24U)
+/*! I3C0_RX - I3C RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_I3C0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_I3C0_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_I3C0_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_I3C0_TX_MASK (0x2000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_I3C0_TX_SHIFT (25U)
+/*! I3C0_TX - I3C TX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_I3C0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_I3C0_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_I3C0_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_RX_MASK (0x4000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_RX_SHIFT (26U)
+/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_TX_MASK (0x8000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_TX_SHIFT (27U)
+/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_RX_MASK (0x10000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_RX_SHIFT (28U)
+/*! FLEXCOMM16_RX - FLEXCOMM16 RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_TX_MASK (0x20000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_TX_SHIFT (29U)
+/*! FLEXCOMM16_TX - FLEXCOMM16 RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_I3C1_RX_MASK (0x40000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_I3C1_RX_SHIFT (30U)
+/*! I3C1_RX - I3C1_RX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_I3C1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_I3C1_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_I3C1_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_I3C1_TX_MASK (0x80000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_I3C1_TX_SHIFT (31U)
+/*! I3C1_TX - I3C1_TX enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_I3C1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_I3C1_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_I3C1_TX_MASK)
+/*! @} */
+
+/*! @name DMAC1_REQ_ENA1 - DMAC1 request enable 1 */
+/*! @{ */
+#define INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM11_RX_MASK (0x1U)
+#define INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM11_RX_SHIFT (0U)
+/*! FLEXCOMM11_RX - FLEXCOMM11_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM11_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM11_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM11_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM11_TX_MASK (0x2U)
+#define INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM11_TX_SHIFT (1U)
+/*! FLEXCOMM11_TX - FLEXCOMM11_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM11_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM11_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM11_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM12_RX_MASK (0x4U)
+#define INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM12_RX_SHIFT (2U)
+/*! FLEXCOMM12_RX - FLEXCOMM12_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM12_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM12_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM12_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM12_TX_MASK (0x8U)
+#define INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM12_TX_SHIFT (3U)
+/*! FLEXCOMM12_TX - FLEXCOMM12_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM12_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM12_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_FLEXCOMM12_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA1_HASHCRYPT_IN_MASK (0x10U)
+#define INPUTMUX_DMAC1_REQ_ENA1_HASHCRYPT_IN_SHIFT (4U)
+/*! HASHCRYPT_IN - HASHCRYPT_IN
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_REQ_ENA1_HASHCRYPT_IN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_HASHCRYPT_IN_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_HASHCRYPT_IN_MASK)
+/*! @} */
+
+/*! @name DMAC1_REQ_ENA0_SET - DMAC1 request enable set 0 */
+/*! @{ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_RX_MASK (0x1U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_RX_SHIFT (0U)
+/*! FLEXCOMM0_RX
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_TX_MASK (0x2U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_TX_SHIFT (1U)
+/*! FLEXCOMM0_TX
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_RX_MASK (0x4U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_RX_SHIFT (2U)
+/*! FLEXCOMM1_RX
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_TX_MASK (0x8U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_TX_SHIFT (3U)
+/*! FLEXCOMM1_TX
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_RX_MASK (0x10U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_RX_SHIFT (4U)
+/*! FLEXCOMM2_RX
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_TX_MASK (0x20U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_TX_SHIFT (5U)
+/*! FLEXCOMM2_TX
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_RX_MASK (0x40U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_RX_SHIFT (6U)
+/*! FLEXCOMM3_RX
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_TX_MASK (0x80U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_TX_SHIFT (7U)
+/*! FLEXCOMM3_TX
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_RX_MASK (0x100U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_RX_SHIFT (8U)
+/*! FLEXCOMM4_RX
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_TX_MASK (0x200U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_TX_SHIFT (9U)
+/*! FLEXCOMM4_TX
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_RX_MASK (0x400U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_RX_SHIFT (10U)
+/*! FLEXCOMM5_RX
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_TX_MASK (0x800U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_TX_SHIFT (11U)
+/*! FLEXCOMM5_TX
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_RX_MASK (0x1000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_RX_SHIFT (12U)
+/*! FLEXCOMM6_RX
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_TX_MASK (0x2000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_TX_SHIFT (13U)
+/*! FLEXCOMM6_TX - FLEXCOMM6 TX enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_RX_MASK (0x4000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_RX_SHIFT (14U)
+/*! FLEXCOMM7_RX - FLEXCOMM7 RX enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_TX_MASK (0x8000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_TX_SHIFT (15U)
+/*! FLEXCOMM7_TX - FLEXCOMM7 TX enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK (0x10000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT (16U)
+/*! DMIC0_CH0_FLEXCOMM8_RX_DMA - DMIC0 channel 0 / FLEXCOMM8 RX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK (0x20000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT (17U)
+/*! DMIC0_CH1_FLEXCOMM8_TX_DMA - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK (0x40000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT (18U)
+/*! DMIC0_CH2_FLEXCOMM9_RX_DMA - DMIC0 channel 2 / FLEXCOMM9 RX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK (0x80000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT (19U)
+/*! DMIC0_CH3_FLEXCOMM9_TX_DMA - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK (0x100000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT (20U)
+/*! DMIC0_CH4_FLEXCOMM10_RX_DMA - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK (0x200000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT (21U)
+/*! DMIC0_CH5_FLEXCOMM10_TX_DMA - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK (0x400000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT (22U)
+/*! DMIC0_CH6_FLEXCOMM13_RX_DMA - DMIC0 channel 6 / FLEXCOMM13 RX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK (0x800000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT (23U)
+/*! DMIC0_CH7_FLEXCOMM13_TX_DMA - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH7_FLEXCOMM13_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_RX_MASK (0x1000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_RX_SHIFT (24U)
+/*! I3C0_RX - I3C RX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_TX_MASK (0x2000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_TX_SHIFT (25U)
+/*! I3C0_TX - I3C TX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_RX_MASK (0x4000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_RX_SHIFT (26U)
+/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_TX_MASK (0x8000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_TX_SHIFT (27U)
+/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable set
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_RX_MASK (0x10000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_RX_SHIFT (28U)
+/*! FLEXCOMM16_RX - FLEXCOMM16 RX enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_TX_MASK (0x20000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_TX_SHIFT (29U)
+/*! FLEXCOMM16_TX - FLEXCOMM16 TX enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_RX_MASK (0x40000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_RX_SHIFT (30U)
+/*! I3C1_RX - I3C1_RX enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_TX_MASK (0x80000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_TX_SHIFT (31U)
+/*! I3C1_TX - I3C1_TX enable
+ * 0b0..No effect
+ * 0b1..Sets the ENA0 bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_TX_MASK)
+/*! @} */
+
+/*! @name DMAC1_REQ_ENA1_SET - DMAC1 request enable set 1 */
+/*! @{ */
+#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM11_RX_MASK (0x1U)
+#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM11_RX_SHIFT (0U)
+/*! FLEXCOMM11_RX - FLEXIO_SHFT_FLEXCOMM_RX
+ * 0b0..No Effect
+ * 0b1..Sets the ENA1 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM11_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM11_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM11_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM11_TX_MASK (0x2U)
+#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM11_TX_SHIFT (1U)
+/*! FLEXCOMM11_TX - FLEXIO_SHFT_FLEXCOMM_TX
+ * 0b0..No Effect
+ * 0b1..Sets the ENA1 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM11_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM11_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM11_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM12_RX_MASK (0x4U)
+#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM12_RX_SHIFT (2U)
+/*! FLEXCOMM12_RX - FLEXCOMM12_RX
+ * 0b0..No Effect
+ * 0b1..Sets the ENA1 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM12_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM12_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM12_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM12_TX_MASK (0x8U)
+#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM12_TX_SHIFT (3U)
+/*! FLEXCOMM12_TX - FLEXCOMM12_TX
+ * 0b0..No Effect
+ * 0b1..Sets the ENA1 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM12_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM12_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXCOMM12_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA1_SET_HASHCRYPT_IN_MASK (0x10U)
+#define INPUTMUX_DMAC1_REQ_ENA1_SET_HASHCRYPT_IN_SHIFT (4U)
+/*! HASHCRYPT_IN - HASHCRYPT_IN
+ * 0b0..No Effect
+ * 0b1..Sets the ENA1 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA1_SET_HASHCRYPT_IN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_SET_HASHCRYPT_IN_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_SET_HASHCRYPT_IN_MASK)
+/*! @} */
+
+/*! @name DMAC1_REQ_ENA0_CLR - DMAC1 request enable clear 0 */
+/*! @{ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_RX_MASK (0x1U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_RX_SHIFT (0U)
+/*! FLEXCOMM0_RX - FLEXCOMM0 RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_TX_MASK (0x2U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_TX_SHIFT (1U)
+/*! FLEXCOMM0_TX - FLEXCOMM0 TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_RX_MASK (0x4U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_RX_SHIFT (2U)
+/*! FLEXCOMM1_RX - FLEXCOMM1 RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_TX_MASK (0x8U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_TX_SHIFT (3U)
+/*! FLEXCOMM1_TX - FLEXCOMM1 TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_RX_MASK (0x10U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_RX_SHIFT (4U)
+/*! FLEXCOMM2_RX - FLEXCOMM2 RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_TX_MASK (0x20U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_TX_SHIFT (5U)
+/*! FLEXCOMM2_TX - FLEXCOMM2 TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_RX_MASK (0x40U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_RX_SHIFT (6U)
+/*! FLEXCOMM3_RX - FLEXCOMM3 RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_TX_MASK (0x80U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_TX_SHIFT (7U)
+/*! FLEXCOMM3_TX - FLEXCOMM3 TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_RX_MASK (0x100U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_RX_SHIFT (8U)
+/*! FLEXCOMM4_RX - FLEXCOMM4 RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_TX_MASK (0x200U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_TX_SHIFT (9U)
+/*! FLEXCOMM4_TX - FLEXCOMM4 TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_RX_MASK (0x400U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_RX_SHIFT (10U)
+/*! FLEXCOMM5_RX - FLEXCOMM5 RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_TX_MASK (0x800U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_TX_SHIFT (11U)
+/*! FLEXCOMM5_TX - FLEXCOMM5 TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_RX_MASK (0x1000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_RX_SHIFT (12U)
+/*! FLEXCOMM6_RX - FLEXCOMM6 RX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_TX_MASK (0x2000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_TX_SHIFT (13U)
+/*! FLEXCOMM6_TX - FLEXCOMM6 TX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_RX_MASK (0x4000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_RX_SHIFT (14U)
+/*! FLEXCOMM7_RX - FLEXCOMM7 RX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_TX_MASK (0x8000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_TX_SHIFT (15U)
+/*! FLEXCOMM7_TX - FLEXCOMM7 TX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK (0x10000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT (16U)
+/*! DMIC0_CH0_FLEXCOMM8_RX_DMA - DMIC0 channel 0 / FLEXCOMM8_RX_DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK (0x20000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT (17U)
+/*! DMIC0_CH1_FLEXCOMM8_TX_DMA - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK (0x40000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT (18U)
+/*! DMIC0_CH2_FLEXCOMM9_RX_DMA - DMIC0 channel 2 / FLEXCOMM9 RX DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK (0x80000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT (19U)
+/*! DMIC0_CH3_FLEXCOMM9_TX_DMA - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK (0x100000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT (20U)
+/*! DMIC0_CH4_FLEXCOMM10_RX_DMA - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK (0x200000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT (21U)
+/*! DMIC0_CH5_FLEXCOMM10_TX_DMA - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK (0x400000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT (22U)
+/*! DMIC0_CH6_FLEXCOMM13_RX_DMA - DMIC0 channel 6 / FLEXCOMM13 RX DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK (0x800000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT (23U)
+/*! DMIC0_CH7_FLEXCOMM13_TX_DMA - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_RX_MASK (0x1000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_RX_SHIFT (24U)
+/*! I3C0_RX - I3C RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_TX_MASK (0x2000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_TX_SHIFT (25U)
+/*! I3C0_TX - I3C TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_RX_MASK (0x4000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_RX_SHIFT (26U)
+/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_TX_MASK (0x8000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_TX_SHIFT (27U)
+/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable clear
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_RX_MASK (0x10000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_RX_SHIFT (28U)
+/*! FLEXCOMM16_RX - FLEXCOMM16 RX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_TX_MASK (0x20000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_TX_SHIFT (29U)
+/*! FLEXCOMM16_TX - FLEXCOMM16 TX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_RX_MASK (0x40000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_RX_SHIFT (30U)
+/*! I3C1_RX - I3C1_RX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_TX_MASK (0x80000000U)
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_TX_SHIFT (31U)
+/*! I3C1_TX - I3C1_TX enable
+ * 0b0..No effect
+ * 0b1..Clears the ENA0 bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_TX_MASK)
+/*! @} */
+
+/*! @name DMAC1_REQ_ENA1_CLR - DMAC1 request enable 1 clear */
+/*! @{ */
+#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM11_RX_MASK (0x1U)
+#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM11_RX_SHIFT (0U)
+/*! FLEXCOMM11_RX - FLEXCOMM11_RX
+ * 0b0..No effect
+ * 0b1..Clears the ENA1 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM11_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM11_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM11_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM11_TX_MASK (0x2U)
+#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM11_TX_SHIFT (1U)
+/*! FLEXCOMM11_TX - FLEXCOMM11_TX
+ * 0b0..No effect
+ * 0b1..Clears the ENA1 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM11_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM11_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM11_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM12_RX_MASK (0x4U)
+#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM12_RX_SHIFT (2U)
+/*! FLEXCOMM12_RX - FLEXCOMM12_RX
+ * 0b0..No effect
+ * 0b1..Clears the ENA1 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM12_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM12_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM12_RX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM12_TX_MASK (0x8U)
+#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM12_TX_SHIFT (3U)
+/*! FLEXCOMM12_TX - FLEXCOMM12_TX
+ * 0b0..No effect
+ * 0b1..Clears the ENA1 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM12_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM12_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXCOMM12_TX_MASK)
+#define INPUTMUX_DMAC1_REQ_ENA1_CLR_HASHCRYPT_IN_MASK (0x10U)
+#define INPUTMUX_DMAC1_REQ_ENA1_CLR_HASHCRYPT_IN_SHIFT (4U)
+/*! HASHCRYPT_IN - HASHCRYPT_IN
+ * 0b0..No effect
+ * 0b1..Clears the ENA1 Bit
+ */
+#define INPUTMUX_DMAC1_REQ_ENA1_CLR_HASHCRYPT_IN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_CLR_HASHCRYPT_IN_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_CLR_HASHCRYPT_IN_MASK)
+/*! @} */
+
+/*! @name DMAC0_ITRIG_ENA0 - DMAC0 Input Trigger Enable 0 */
+/*! @{ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT0_MASK (0x1U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT0_SHIFT (0U)
+/*! GPIO_INT0 - GPIO_INT0
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT1_MASK (0x2U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT1_SHIFT (1U)
+/*! GPIO_INT1 - GPIO_INT1
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT2_MASK (0x4U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT2_SHIFT (2U)
+/*! GPIO_INT2 - GPIO_INT2
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT2_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT2_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT3_MASK (0x8U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT3_SHIFT (3U)
+/*! GPIO_INT3 - GPIO_INT3
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT3_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT3_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M0_MASK (0x10U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M0_SHIFT (4U)
+/*! T0_DMAREQ_M0 - T0_DMAREQ_M0
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M1_MASK (0x20U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M1_SHIFT (5U)
+/*! T0_DMAREQ_M1 - T0_DMAREQ_M1
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M0_MASK (0x40U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M0_SHIFT (6U)
+/*! T1_DMAREQ_M0 - T1_DMAREQ_M0
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M1_MASK (0x80U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M1_SHIFT (7U)
+/*! T1_DMAREQ_M1 - T1_DMAREQ_M1
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M0_MASK (0x100U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M0_SHIFT (8U)
+/*! T2_DMAREQ_M0 - T2_DMAREQ_M0
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M1_MASK (0x200U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M1_SHIFT (9U)
+/*! T2_DMAREQ_M1 - T2_DMAREQ_M1
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M0_MASK (0x400U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M0_SHIFT (10U)
+/*! T3_DMAREQ_M0 - T3_DMAREQ_M0
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M1_MASK (0x800U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M1_SHIFT (11U)
+/*! T3_DMAREQ_M1 - T3_DMAREQ_M1
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M0_MASK (0x1000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M0_SHIFT (12U)
+/*! T4_DMAREQ_M0 - T4_DMAREQ_M0
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M1_MASK (0x2000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M1_SHIFT (13U)
+/*! T4_DMAREQ_M1 - T4_DMAREQ_M1
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_A_MASK (0x4000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_A_SHIFT (14U)
+/*! DMA_TRIGOUT_A - DMA_TRIGOUT_A
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_A(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_A_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_A_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_B_MASK (0x8000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_B_SHIFT (15U)
+/*! DMA_TRIGOUT_B - DMA_TRIGOUT_B
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_B(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_B_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_B_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_C_MASK (0x10000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_C_SHIFT (16U)
+/*! DMA_TRIGOUT_C - DMA_TRIGOUT_C
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_C(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_C_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_C_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_D_MASK (0x20000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_D_SHIFT (17U)
+/*! DMA_TRIGOUT_D - DMA_TRIGOUT_D
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_D(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_D_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_D_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ0_MASK (0x40000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ0_SHIFT (18U)
+/*! SCT_DMA_REQ0 - SCT_DMA_REQ0
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ1_MASK (0x80000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ1_SHIFT (19U)
+/*! SCT_DMA_REQ1 - SCT_DMA_REQ1
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_HASHCRYPT_OUT_MASK (0x100000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_HASHCRYPT_OUT_SHIFT (20U)
+/*! HASHCRYPT_OUT - HASHCRYPT_OUT
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_HASHCRYPT_OUT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_HASHCRYPT_OUT_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_HASHCRYPT_OUT_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_ACMP_MASK (0x200000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_ACMP_SHIFT (21U)
+/*! ACMP - ACMP
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_ACMP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_ACMP_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_ACMP_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_RX_MASK (0x400000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_RX_SHIFT (22U)
+/*! FLEXSPI0_RX - FlexSPI0_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_RX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_RX_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_TX_MASK (0x800000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_TX_SHIFT (23U)
+/*! FLEXSPI0_TX - FlexSPI0_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_TX_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_ADC_MASK (0x1000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_ADC_SHIFT (24U)
+/*! ADC - ADC
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_ADC(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_ADC_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_ADC_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_RX_MASK (0x2000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_RX_SHIFT (25U)
+/*! FLEXSPI1_RX - FlexSPI1_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_RX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_RX_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_MASK (0x4000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_SHIFT (26U)
+/*! FLEXSPI1_TX - FlexSPI1_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_MASK)
+/*! @} */
+
+/*! @name DMAC0_ITRIG_ENA0_SET - DMAC0 Input Trigger Enable 0 Set */
+/*! @{ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT0_MASK (0x1U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT0_SHIFT (0U)
+/*! GPIO_INT0 - GPIO_INT0 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT1_MASK (0x2U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT1_SHIFT (1U)
+/*! GPIO_INT1 - GPIO_INT1 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT2_MASK (0x4U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT2_SHIFT (2U)
+/*! GPIO_INT2 - GPIO_INT2 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT2_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT2_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT3_MASK (0x8U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT3_SHIFT (3U)
+/*! GPIO_INT3 - GPIO_INT3 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT3_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT3_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M0_MASK (0x10U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M0_SHIFT (4U)
+/*! T0_DMAREQ_M0 - T0_DMAREQ_M0 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M1_MASK (0x20U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M1_SHIFT (5U)
+/*! T0_DMAREQ_M1 - T0_DMAREQ_M1 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M0_MASK (0x40U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M0_SHIFT (6U)
+/*! T1_DMAREQ_M0 - T1_DMAREQ_M0 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M1_MASK (0x80U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M1_SHIFT (7U)
+/*! T1_DMAREQ_M1 - T1_DMAREQ_M1 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M0_MASK (0x100U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M0_SHIFT (8U)
+/*! T2_DMAREQ_M0 - T2_DMAREQ_M0 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M1_MASK (0x200U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M1_SHIFT (9U)
+/*! T2_DMAREQ_M1 - T2_DMAREQ_M1 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M0_MASK (0x400U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M0_SHIFT (10U)
+/*! T3_DMAREQ_M0 - T3_DMAREQ_M0 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M1_MASK (0x800U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M1_SHIFT (11U)
+/*! T3_DMAREQ_M1 - T3_DMAREQ_M1 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M0_MASK (0x1000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M0_SHIFT (12U)
+/*! T4_DMAREQ_M0 - T4_DMAREQ_M0 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M1_MASK (0x2000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M1_SHIFT (13U)
+/*! T4_DMAREQ_M1 - T4_DMAREQ_M1 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_MASK (0x4000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_SHIFT (14U)
+/*! SDMA0_TRIGOUT_A - SDMA0_TRIGOUT_Aset
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_MASK (0x8000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_SHIFT (15U)
+/*! SDMA0_TRIGOUT_B - SDMA0_TRIGOUT_B set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_MASK (0x10000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_SHIFT (16U)
+/*! SDMA0_TRIGOUT_C - SDMA0_TRIGOUT_C set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_MASK (0x20000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_SHIFT (17U)
+/*! SDMA0_TRIGOUT_D - SDMA0_TRIGOUT_D set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ0_MASK (0x40000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ0_SHIFT (18U)
+/*! SCT_DMA_REQ0 - SCT_DMA_REQ0 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ1_MASK (0x80000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ1_SHIFT (19U)
+/*! SCT_DMA_REQ1 - SCT_DMA_REQ1 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_HASHCRYPT_OUT_MASK (0x100000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_HASHCRYPT_OUT_SHIFT (20U)
+/*! HASHCRYPT_OUT - HASHCRYPT_OUT set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_HASHCRYPT_OUT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_HASHCRYPT_OUT_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_HASHCRYPT_OUT_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_ACMP_MASK (0x200000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_ACMP_SHIFT (21U)
+/*! ACMP - ACMP set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_ACMP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_ACMP_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_ACMP_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_RX_MASK (0x400000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_RX_SHIFT (22U)
+/*! FLEXSPI0_RX - FlexSPI0_RX set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_RX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_RX_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_TX_MASK (0x800000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_TX_SHIFT (23U)
+/*! FLEXSPI0_TX - FlexSPI0_TX set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_TX_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_ADC_MASK (0x1000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_ADC_SHIFT (24U)
+/*! ADC - ADC set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_ADC(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_ADC_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_ADC_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_RX_MASK (0x2000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_RX_SHIFT (25U)
+/*! FLEXSPI1_RX - FlexSPI1_RX set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_RX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_RX_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_TX_MASK (0x4000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_TX_SHIFT (26U)
+/*! FLEXSPI1_TX - FlexSPI1_TX set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_TX_MASK)
+/*! @} */
+
+/*! @name DMAC0_ITRIG_ENA0_CLR - DMAC0 Input Trigger Enable 0 Clear */
+/*! @{ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT0_MASK (0x1U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT0_SHIFT (0U)
+/*! GPIO_INT0 - GPIO_INT0 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT1_MASK (0x2U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT1_SHIFT (1U)
+/*! GPIO_INT1 - GPIO_INT1 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT2_MASK (0x4U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT2_SHIFT (2U)
+/*! GPIO_INT2 - GPIO_INT2 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT2_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT2_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT3_MASK (0x8U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT3_SHIFT (3U)
+/*! GPIO_INT3 - GPIO_INT3 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT3_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT3_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M0_MASK (0x10U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M0_SHIFT (4U)
+/*! T0_DMAREQ_M0 - T0_DMAREQ_M0 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M1_MASK (0x20U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M1_SHIFT (5U)
+/*! T0_DMAREQ_M1 - T0_DMAREQ_M1 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M0_MASK (0x40U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M0_SHIFT (6U)
+/*! T1_DMAREQ_M0 - T1_DMAREQ_M0 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M1_MASK (0x80U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M1_SHIFT (7U)
+/*! T1_DMAREQ_M1 - T1_DMAREQ_M1 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M0_MASK (0x100U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M0_SHIFT (8U)
+/*! T2_DMAREQ_M0 - T2_DMAREQ_M0 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M1_MASK (0x200U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M1_SHIFT (9U)
+/*! T2_DMAREQ_M1 - T2_DMAREQ_M1 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M0_MASK (0x400U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M0_SHIFT (10U)
+/*! T3_DMAREQ_M0 - T3_DMAREQ_M0 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M1_MASK (0x800U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M1_SHIFT (11U)
+/*! T3_DMAREQ_M1 - T3_DMAREQ_M1 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M0_MASK (0x1000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M0_SHIFT (12U)
+/*! T4_DMAREQ_M0 - T4_DMAREQ_M0 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M1_MASK (0x2000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M1_SHIFT (13U)
+/*! T4_DMAREQ_M1 - T4_DMAREQ_M1 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_MASK (0x4000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_SHIFT (14U)
+/*! SDMA0_TRIGOUT_A - SDMA0_TRIGOUT_A clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_MASK (0x8000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_SHIFT (15U)
+/*! SDMA0_TRIGOUT_B - SDMA0_TRIGOUT_B clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_MASK (0x10000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_SHIFT (16U)
+/*! SDMA0_TRIGOUT_C - SDMA0_TRIGOUT_C clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_MASK (0x20000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_SHIFT (17U)
+/*! SDMA0_TRIGOUT_D - SDMA0_TRIGOUT_D clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ0_MASK (0x40000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ0_SHIFT (18U)
+/*! SCT_DMA_REQ0 - SCT_DMA_REQ0 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ0_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ1_MASK (0x80000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ1_SHIFT (19U)
+/*! SCT_DMA_REQ1 - SCT_DMA_REQ1 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ1_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_HASHCRYPT_OUT_MASK (0x100000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_HASHCRYPT_OUT_SHIFT (20U)
+/*! HASHCRYPT_OUT - HASHCRYPT_OUT clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_HASHCRYPT_OUT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_HASHCRYPT_OUT_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_HASHCRYPT_OUT_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_MASK (0x200000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_SHIFT (21U)
+/*! ACMP - ACMP clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_RX_MASK (0x400000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_RX_SHIFT (22U)
+/*! FLEXSPI0_RX - FlexSPI0_RX clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_RX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_RX_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_TX_MASK (0x800000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_TX_SHIFT (23U)
+/*! FLEXSPI0_TX - FlexSPI0_TX clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_TX_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ADC_MASK (0x1000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ADC_SHIFT (24U)
+/*! ADC - ADC clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ADC(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ADC_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ADC_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_RX_MASK (0x2000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_RX_SHIFT (25U)
+/*! FLEXSPI1_RX - FlexSPI1_RX clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_RX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_RX_MASK)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_TX_MASK (0x4000000U)
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_TX_SHIFT (26U)
+/*! FLEXSPI1_TX - FlexSPI1_TX clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_TX_MASK)
+/*! @} */
+
+/*! @name DMAC1_ITRIG_ENA0 - DMAC1 Input Trigger Enable 0 */
+/*! @{ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT0_MASK (0x1U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT0_SHIFT (0U)
+/*! GPIO_INT0 - GPIO_INT0
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT1_MASK (0x2U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT1_SHIFT (1U)
+/*! GPIO_INT1 - GPIO_INT1
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT2_MASK (0x4U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT2_SHIFT (2U)
+/*! GPIO_INT2 - GPIO_INT2
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT2_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT2_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT3_MASK (0x8U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT3_SHIFT (3U)
+/*! GPIO_INT3 - GPIO_INT3
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT3_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT3_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M0_MASK (0x10U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M0_SHIFT (4U)
+/*! T0_DMAREQ_M0 - T0_DMAREQ_M0
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M1_MASK (0x20U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M1_SHIFT (5U)
+/*! T0_DMAREQ_M1 - T0_DMAREQ_M1
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M0_MASK (0x40U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M0_SHIFT (6U)
+/*! T1_DMAREQ_M0 - T1_DMAREQ_M0
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M1_MASK (0x80U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M1_SHIFT (7U)
+/*! T1_DMAREQ_M1 - T1_DMAREQ_M1
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M0_MASK (0x100U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M0_SHIFT (8U)
+/*! T2_DMAREQ_M0 - T2_DMAREQ_M0
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M1_MASK (0x200U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M1_SHIFT (9U)
+/*! T2_DMAREQ_M1 - T2_DMAREQ_M1
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M0_MASK (0x400U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M0_SHIFT (10U)
+/*! T3_DMAREQ_M0 - T3_DMAREQ_M0
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M1_MASK (0x800U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M1_SHIFT (11U)
+/*! T3_DMAREQ_M1 - T3_DMAREQ_M1
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M0_MASK (0x1000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M0_SHIFT (12U)
+/*! T4_DMAREQ_M0 - T4_DMAREQ_M0
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M1_MASK (0x2000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M1_SHIFT (13U)
+/*! T4_DMAREQ_M1 - T4_DMAREQ_M1
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_A_MASK (0x4000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_A_SHIFT (14U)
+/*! DMA_TRIGOUT_A - DMA_TRIGOUT_A
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_A(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_A_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_A_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_B_MASK (0x8000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_B_SHIFT (15U)
+/*! DMA_TRIGOUT_B - DMA_TRIGOUT_B
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_B(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_B_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_B_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_C_MASK (0x10000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_C_SHIFT (16U)
+/*! DMA_TRIGOUT_C - DMA_TRIGOUT_C
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_C(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_C_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_C_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_D_MASK (0x20000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_D_SHIFT (17U)
+/*! DMA_TRIGOUT_D - DMA_TRIGOUT_D
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_D(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_D_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_D_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ0_MASK (0x40000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ0_SHIFT (18U)
+/*! SCT_DMA_REQ0 - SCT_DMA_REQ0
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ1_MASK (0x80000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ1_SHIFT (19U)
+/*! SCT_DMA_REQ1 - SCT_DMA_REQ1
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_HASHCRYPT_OUT_MASK (0x100000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_HASHCRYPT_OUT_SHIFT (20U)
+/*! HASHCRYPT_OUT - HASHCRYPT_OUT
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_HASHCRYPT_OUT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_HASHCRYPT_OUT_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_HASHCRYPT_OUT_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_ACMP_MASK (0x200000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_ACMP_SHIFT (21U)
+/*! ACMP - ACMP
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_ACMP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_ACMP_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_ACMP_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_RX_MASK (0x400000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_RX_SHIFT (22U)
+/*! FLEXSPI0_RX - FlexSPI0_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_RX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_RX_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_TX_MASK (0x800000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_TX_SHIFT (23U)
+/*! FLEXSPI0_TX - FlexSPI0_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_TX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_TX_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_ADC_MASK (0x1000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_ADC_SHIFT (24U)
+/*! ADC - ADC
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_ADC(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_ADC_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_ADC_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_RX_MASK (0x2000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_RX_SHIFT (25U)
+/*! FLEXSPI1_RX - FlexSPI1_RX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_RX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_RX_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_TX_MASK (0x4000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_TX_SHIFT (26U)
+/*! FLEXSPI1_TX - FlexSPI1_TX
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_TX_MASK)
+/*! @} */
+
+/*! @name DMAC1_ITRIG_ENA0_SET - DMAC1 Input Trigger Enable 0 set */
+/*! @{ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT0_MASK (0x1U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT0_SHIFT (0U)
+/*! GPIO_INT0 - GPIO_INT0 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT1_MASK (0x2U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT1_SHIFT (1U)
+/*! GPIO_INT1 - GPIO_INT1 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT2_MASK (0x4U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT2_SHIFT (2U)
+/*! GPIO_INT2 - GPIO_INT2 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT2_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT2_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT3_MASK (0x8U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT3_SHIFT (3U)
+/*! GPIO_INT3 - GPIO_INT3 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT3_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT3_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M0_MASK (0x10U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M0_SHIFT (4U)
+/*! T0_DMAREQ_M0 - T0_DMAREQ_M0 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M1_MASK (0x20U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M1_SHIFT (5U)
+/*! T0_DMAREQ_M1 - T0_DMAREQ_M1 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M0_MASK (0x40U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M0_SHIFT (6U)
+/*! T1_DMAREQ_M0 - T1_DMAREQ_M0 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M1_MASK (0x80U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M1_SHIFT (7U)
+/*! T1_DMAREQ_M1 - T1_DMAREQ_M1 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M0_MASK (0x100U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M0_SHIFT (8U)
+/*! T2_DMAREQ_M0 - T2_DMAREQ_M0 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M1_MASK (0x200U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M1_SHIFT (9U)
+/*! T2_DMAREQ_M1 - T2_DMAREQ_M1 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M0_MASK (0x400U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M0_SHIFT (10U)
+/*! T3_DMAREQ_M0 - T3_DMAREQ_M0 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M1_MASK (0x800U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M1_SHIFT (11U)
+/*! T3_DMAREQ_M1 - T3_DMAREQ_M1 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M0_MASK (0x1000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M0_SHIFT (12U)
+/*! T4_DMAREQ_M0 - T4_DMAREQ_M0 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M1_MASK (0x2000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M1_SHIFT (13U)
+/*! T4_DMAREQ_M1 - T4_DMAREQ_M1 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_MASK (0x4000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_SHIFT (14U)
+/*! SDMA0_TRIGOUT_A - SDMA0_TRIGOUT_A set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_MASK (0x8000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_SHIFT (15U)
+/*! SDMA0_TRIGOUT_B - SDMA0_TRIGOUT_B set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_MASK (0x10000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_SHIFT (16U)
+/*! SDMA0_TRIGOUT_C - SDMA0_TRIGOUT_C set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_MASK (0x20000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_SHIFT (17U)
+/*! SDMA0_TRIGOUT_D - SDMA0_TRIGOUT_D set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ0_MASK (0x40000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ0_SHIFT (18U)
+/*! SCT_DMA_REQ0 - SCT_DMA_REQ0 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ1_MASK (0x80000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ1_SHIFT (19U)
+/*! SCT_DMA_REQ1 - SCT_DMA_REQ1 set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_HASHCRYPT_OUT_MASK (0x100000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_HASHCRYPT_OUT_SHIFT (20U)
+/*! HASHCRYPT_OUT - HASHCRYPT_OUT set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_HASHCRYPT_OUT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_HASHCRYPT_OUT_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_HASHCRYPT_OUT_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_ACMP_MASK (0x200000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_ACMP_SHIFT (21U)
+/*! ACMP - ACMP set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_ACMP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_ACMP_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_ACMP_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_RX_MASK (0x400000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_RX_SHIFT (22U)
+/*! FLEXSPI0_RX - FlexSPI0_RX set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_RX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_RX_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_TX_MASK (0x800000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_TX_SHIFT (23U)
+/*! FLEXSPI0_TX - FlexSPI0_TX set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_TX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_TX_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_ADC_MASK (0x1000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_ADC_SHIFT (24U)
+/*! ADC - ADC set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_ADC(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_ADC_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_ADC_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_RX_MASK (0x2000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_RX_SHIFT (25U)
+/*! FLEXSPI1_RX - FlexSPI1_RX set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_RX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_RX_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_TX_MASK (0x4000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_TX_SHIFT (26U)
+/*! FLEXSPI1_TX - FlexSPI1_TX set
+ * 0b0..No Effect
+ * 0b1..Sets the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_TX_MASK)
+/*! @} */
+
+/*! @name DMAC1_ITRIG_ENA0_CLR - DMAC1 Input Trigger Enable 0 clear */
+/*! @{ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT0_MASK (0x1U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT0_SHIFT (0U)
+/*! GPIO_INT0 - GPIO_INT0 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT1_MASK (0x2U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT1_SHIFT (1U)
+/*! GPIO_INT1 - GPIO_INT1 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT2_MASK (0x4U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT2_SHIFT (2U)
+/*! GPIO_INT2 - GPIO_INT2 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT2_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT2_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT3_MASK (0x8U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT3_SHIFT (3U)
+/*! GPIO_INT3 - GPIO_INT3 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT3_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT3_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M0_MASK (0x10U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M0_SHIFT (4U)
+/*! T0_DMAREQ_M0 - T0_DMAREQ_M0 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M1_MASK (0x20U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M1_SHIFT (5U)
+/*! T0_DMAREQ_M1 - T0_DMAREQ_M1 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M0_MASK (0x40U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M0_SHIFT (6U)
+/*! T1_DMAREQ_M0 - T1_DMAREQ_M0 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M1_MASK (0x80U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M1_SHIFT (7U)
+/*! T1_DMAREQ_M1 - T1_DMAREQ_M1 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M0_MASK (0x100U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M0_SHIFT (8U)
+/*! T2_DMAREQ_M0 - T2_DMAREQ_M0 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M1_MASK (0x200U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M1_SHIFT (9U)
+/*! T2_DMAREQ_M1 - T2_DMAREQ_M1 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M0_MASK (0x400U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M0_SHIFT (10U)
+/*! T3_DMAREQ_M0 - T3_DMAREQ_M0 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M1_MASK (0x800U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M1_SHIFT (11U)
+/*! T3_DMAREQ_M1 - T3_DMAREQ_M1 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M0_MASK (0x1000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M0_SHIFT (12U)
+/*! T4_DMAREQ_M0 - T4_DMAREQ_M0 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M1_MASK (0x2000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M1_SHIFT (13U)
+/*! T4_DMAREQ_M1 - T4_DMAREQ_M1 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_MASK (0x4000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_SHIFT (14U)
+/*! SDMA0_TRIGOUT_A - SDMA0_TRIGOUT_A clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_MASK (0x8000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_SHIFT (15U)
+/*! SDMA0_TRIGOUT_B - SDMA0_TRIGOUT_B clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_MASK (0x10000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_SHIFT (16U)
+/*! SDMA0_TRIGOUT_C - SDMA0_TRIGOUT_C clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_MASK (0x20000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_SHIFT (17U)
+/*! SDMA0_TRIGOUT_D - SDMA0_TRIGOUT_D clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ0_MASK (0x40000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ0_SHIFT (18U)
+/*! SCT_DMA_REQ0 - SCT_DMA_REQ0 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ0_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ1_MASK (0x80000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ1_SHIFT (19U)
+/*! SCT_DMA_REQ1 - SCT_DMA_REQ1 clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ1_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_HASHCRYPT_OUT_MASK (0x100000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_HASHCRYPT_OUT_SHIFT (20U)
+/*! HASHCRYPT_OUT - HASHCRYPT_OUTclear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_HASHCRYPT_OUT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_HASHCRYPT_OUT_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_HASHCRYPT_OUT_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ACMP_MASK (0x200000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ACMP_SHIFT (21U)
+/*! ACMP - ACMP clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ACMP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ACMP_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ACMP_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_RX_MASK (0x400000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_RX_SHIFT (22U)
+/*! FLEXSPI0_RX - FlexSPI0_RXclear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_RX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_RX_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_TX_MASK (0x800000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_TX_SHIFT (23U)
+/*! FLEXSPI0_TX - FlexSPI0_TX clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_TX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_TX_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ADC_MASK (0x1000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ADC_SHIFT (24U)
+/*! ADC - ADC clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ADC(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ADC_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ADC_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_RX_MASK (0x2000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_RX_SHIFT (25U)
+/*! FLEXSPI1_RX - FlexSPI1_RX clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_RX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_RX_MASK)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_TX_MASK (0x4000000U)
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_TX_SHIFT (26U)
+/*! FLEXSPI1_TX - FlexSPI1_TX clear
+ * 0b0..No Effect
+ * 0b1..Clears the ENA0 Bit
+ */
+#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_TX_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Register_Masks */
+
+
+/* INPUTMUX - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral INPUTMUX base address */
+ #define INPUTMUX_BASE (0x50026000u)
+ /** Peripheral INPUTMUX base address */
+ #define INPUTMUX_BASE_NS (0x40026000u)
+ /** Peripheral INPUTMUX base pointer */
+ #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)
+ /** Peripheral INPUTMUX base pointer */
+ #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS)
+ /** Array initializer of INPUTMUX peripheral base addresses */
+ #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE }
+ /** Array initializer of INPUTMUX peripheral base pointers */
+ #define INPUTMUX_BASE_PTRS { INPUTMUX }
+ /** Array initializer of INPUTMUX peripheral base addresses */
+ #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS }
+ /** Array initializer of INPUTMUX peripheral base pointers */
+ #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS }
+#else
+ /** Peripheral INPUTMUX base address */
+ #define INPUTMUX_BASE (0x40026000u)
+ /** Peripheral INPUTMUX base pointer */
+ #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)
+ /** Array initializer of INPUTMUX peripheral base addresses */
+ #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE }
+ /** Array initializer of INPUTMUX peripheral base pointers */
+ #define INPUTMUX_BASE_PTRS { INPUTMUX }
+#endif
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- IOPCTL Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IOPCTL_Peripheral_Access_Layer IOPCTL Peripheral Access Layer
+ * @{
+ */
+
+/** IOPCTL - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PIO[7][32]; /**< IOPCTL configuration, array offset: 0x0, array step: index*0x80, index2*0x4 */
+ uint8_t RESERVED_0[128];
+ __IO uint32_t FC15_I2C_SCL; /**< Flexcomm 15 SCL, offset: 0x400 */
+ __IO uint32_t FC15_I2C_SDA; /**< Flexcomm 15 SDA, offset: 0x404 */
+} IOPCTL_Type;
+
+/* ----------------------------------------------------------------------------
+ -- IOPCTL Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IOPCTL_Register_Masks IOPCTL Register Masks
+ * @{
+ */
+
+/*! @name PIO - IOPCTL configuration */
+/*! @{ */
+#define IOPCTL_PIO_FSEL_MASK (0xFU)
+#define IOPCTL_PIO_FSEL_SHIFT (0U)
+/*! FSEL - Function Selector (Digital Function)
+ * 0b0000..Function 0
+ * 0b0001..Function 1
+ * 0b0010..Function 2
+ * 0b0011..Function 3
+ * 0b0100..Function 4
+ * 0b0101..Function 5
+ * 0b0110..Function 6
+ * 0b0111..Function 7
+ * 0b1000..Function 8
+ * 0b1001..Function 9
+ * 0b1010..Function 10
+ * 0b1011..Function 11
+ * 0b1100..Function 12
+ * 0b1101..Function 13
+ * 0b1110..Function 14
+ * 0b1111..Function 15
+ */
+#define IOPCTL_PIO_FSEL(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_FSEL_SHIFT)) & IOPCTL_PIO_FSEL_MASK)
+#define IOPCTL_PIO_PUPDENA_MASK (0x10U)
+#define IOPCTL_PIO_PUPDENA_SHIFT (4U)
+/*! PUPDENA - Pullup / Pulldown Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define IOPCTL_PIO_PUPDENA(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_PUPDENA_SHIFT)) & IOPCTL_PIO_PUPDENA_MASK)
+#define IOPCTL_PIO_PUPDSEL_MASK (0x20U)
+#define IOPCTL_PIO_PUPDSEL_SHIFT (5U)
+/*! PUPDSEL - Pullup or Pulldown Selector
+ * 0b0..Pull-down
+ * 0b1..Pull-up
+ */
+#define IOPCTL_PIO_PUPDSEL(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_PUPDSEL_SHIFT)) & IOPCTL_PIO_PUPDSEL_MASK)
+#define IOPCTL_PIO_IBENA_MASK (0x40U)
+#define IOPCTL_PIO_IBENA_SHIFT (6U)
+/*! IBENA - Input Buffer Enable
+ * 0b0..Input buffer disabled
+ * 0b1..Input buffer enabled
+ */
+#define IOPCTL_PIO_IBENA(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_IBENA_SHIFT)) & IOPCTL_PIO_IBENA_MASK)
+#define IOPCTL_PIO_SLEWRATE_MASK (0x80U)
+#define IOPCTL_PIO_SLEWRATE_SHIFT (7U)
+/*! SLEWRATE - Slew Rate Control
+ * 0b0..Standard mode, output slew rate is not controlled.
+ * 0b1..Slow mode, output slew rate control is enabled, limiting the output rate change and maximum toggle
+ * frequency. See device datasheet for details.
+ */
+#define IOPCTL_PIO_SLEWRATE(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_SLEWRATE_SHIFT)) & IOPCTL_PIO_SLEWRATE_MASK)
+#define IOPCTL_PIO_FULLDRIVE_MASK (0x100U)
+#define IOPCTL_PIO_FULLDRIVE_SHIFT (8U)
+/*! FULLDRIVE - Drive Selector
+ * 0b0..Normal output drive
+ * 0b1..Full output drive, twice the drive of normal mode.
+ */
+#define IOPCTL_PIO_FULLDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_FULLDRIVE_SHIFT)) & IOPCTL_PIO_FULLDRIVE_MASK)
+#define IOPCTL_PIO_AMENA_MASK (0x200U)
+#define IOPCTL_PIO_AMENA_SHIFT (9U)
+/*! AMENA - Analog Mux Enable
+ * 0b0..Analog multiplexor disabled, required for digital pin function
+ * 0b1..Analog multiplexor enabled, required for analog pin function
+ */
+#define IOPCTL_PIO_AMENA(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_AMENA_SHIFT)) & IOPCTL_PIO_AMENA_MASK)
+#define IOPCTL_PIO_ODENA_MASK (0x400U)
+#define IOPCTL_PIO_ODENA_SHIFT (10U)
+/*! ODENA - Open-drain mode enable
+ * 0b0..Normal push-pull output
+ * 0b1..Simulated open-drain output (high drive disabled)
+ */
+#define IOPCTL_PIO_ODENA(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_ODENA_SHIFT)) & IOPCTL_PIO_ODENA_MASK)
+#define IOPCTL_PIO_IIENA_MASK (0x800U)
+#define IOPCTL_PIO_IIENA_SHIFT (11U)
+/*! IIENA - Input Invert Enable
+ * 0b0..Disabled, Input function is not inverted
+ * 0b1..Enabled, Input is function inverted
+ */
+#define IOPCTL_PIO_IIENA(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_IIENA_SHIFT)) & IOPCTL_PIO_IIENA_MASK)
+/*! @} */
+
+/* The count of IOPCTL_PIO */
+#define IOPCTL_PIO_COUNT (7U)
+
+/* The count of IOPCTL_PIO */
+#define IOPCTL_PIO_COUNT2 (32U)
+
+/*! @name FC15_I2C_SCL - Flexcomm 15 SCL */
+/*! @{ */
+#define IOPCTL_FC15_I2C_SCL_FSEL_MASK (0xFU)
+#define IOPCTL_FC15_I2C_SCL_FSEL_SHIFT (0U)
+/*! FSEL - Function Selector (Digital Function)
+ * 0b0000..Function 0
+ * 0b0001..Function 1
+ * 0b0010..Function 2
+ * 0b0011..Function 3
+ * 0b0100..Function 4
+ * 0b0101..Function 5
+ * 0b0110..Function 6
+ * 0b0111..Function 7
+ * 0b1000..Function 8
+ * 0b1001..Function 9
+ * 0b1010..Function 10
+ * 0b1011..Function 11
+ * 0b1100..Function 12
+ * 0b1101..Function 13
+ * 0b1110..Function 14
+ * 0b1111..Function 15
+ */
+#define IOPCTL_FC15_I2C_SCL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_FSEL_SHIFT)) & IOPCTL_FC15_I2C_SCL_FSEL_MASK)
+#define IOPCTL_FC15_I2C_SCL_PUPDENA_MASK (0x10U)
+#define IOPCTL_FC15_I2C_SCL_PUPDENA_SHIFT (4U)
+/*! PUPDENA - Pullup / Pulldown Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define IOPCTL_FC15_I2C_SCL_PUPDENA(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_PUPDENA_SHIFT)) & IOPCTL_FC15_I2C_SCL_PUPDENA_MASK)
+#define IOPCTL_FC15_I2C_SCL_PUPDSEL_MASK (0x20U)
+#define IOPCTL_FC15_I2C_SCL_PUPDSEL_SHIFT (5U)
+/*! PUPDSEL - Pullup or Pulldown Selector
+ * 0b0..Pull-down
+ * 0b1..Pull-up
+ */
+#define IOPCTL_FC15_I2C_SCL_PUPDSEL(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_PUPDSEL_SHIFT)) & IOPCTL_FC15_I2C_SCL_PUPDSEL_MASK)
+#define IOPCTL_FC15_I2C_SCL_IBENA_MASK (0x40U)
+#define IOPCTL_FC15_I2C_SCL_IBENA_SHIFT (6U)
+/*! IBENA - Input Buffer Enable
+ * 0b0..Input buffer disabled
+ * 0b1..Input buffer enabled
+ */
+#define IOPCTL_FC15_I2C_SCL_IBENA(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_IBENA_SHIFT)) & IOPCTL_FC15_I2C_SCL_IBENA_MASK)
+#define IOPCTL_FC15_I2C_SCL_SLEWRATE_MASK (0x80U)
+#define IOPCTL_FC15_I2C_SCL_SLEWRATE_SHIFT (7U)
+/*! SLEWRATE - Slew Rate Control
+ * 0b0..Standard mode, output slew rate is not controlled.
+ * 0b1..Slow mode, output slew rate control is enabled, limiting the output rate change and maximum toggle
+ * frequency. See device datasheet for details.
+ */
+#define IOPCTL_FC15_I2C_SCL_SLEWRATE(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_SLEWRATE_SHIFT)) & IOPCTL_FC15_I2C_SCL_SLEWRATE_MASK)
+#define IOPCTL_FC15_I2C_SCL_FULLDRIVE_MASK (0x100U)
+#define IOPCTL_FC15_I2C_SCL_FULLDRIVE_SHIFT (8U)
+/*! FULLDRIVE - Drive Selector
+ * 0b0..Normal output drive
+ * 0b1..Full output drive, twice the drive of normal mode.
+ */
+#define IOPCTL_FC15_I2C_SCL_FULLDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_FULLDRIVE_SHIFT)) & IOPCTL_FC15_I2C_SCL_FULLDRIVE_MASK)
+#define IOPCTL_FC15_I2C_SCL_AMENA_MASK (0x200U)
+#define IOPCTL_FC15_I2C_SCL_AMENA_SHIFT (9U)
+/*! AMENA - Analog Mux Enable
+ * 0b0..Analog multiplexor disabled, required for digital pin function
+ * 0b1..Analog multiplexor enabled, required for analog pin function
+ */
+#define IOPCTL_FC15_I2C_SCL_AMENA(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_AMENA_SHIFT)) & IOPCTL_FC15_I2C_SCL_AMENA_MASK)
+#define IOPCTL_FC15_I2C_SCL_ODENA_MASK (0x400U)
+#define IOPCTL_FC15_I2C_SCL_ODENA_SHIFT (10U)
+/*! ODENA - Open-drain mode enable
+ * 0b0..Normal push-pull output
+ * 0b1..Simulated open-drain output (high drive disabled)
+ */
+#define IOPCTL_FC15_I2C_SCL_ODENA(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_ODENA_SHIFT)) & IOPCTL_FC15_I2C_SCL_ODENA_MASK)
+#define IOPCTL_FC15_I2C_SCL_IIENA_MASK (0x800U)
+#define IOPCTL_FC15_I2C_SCL_IIENA_SHIFT (11U)
+/*! IIENA - Input Invert Enable
+ * 0b0..Disabled, Input function is not inverted
+ * 0b1..Enabled, Input is function inverted
+ */
+#define IOPCTL_FC15_I2C_SCL_IIENA(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_IIENA_SHIFT)) & IOPCTL_FC15_I2C_SCL_IIENA_MASK)
+/*! @} */
+
+/*! @name FC15_I2C_SDA - Flexcomm 15 SDA */
+/*! @{ */
+#define IOPCTL_FC15_I2C_SDA_FSEL_MASK (0xFU)
+#define IOPCTL_FC15_I2C_SDA_FSEL_SHIFT (0U)
+/*! FSEL - Function Selector (Digital Function)
+ * 0b0000..Function 0
+ * 0b0001..Function 1
+ * 0b0010..Function 2
+ * 0b0011..Function 3
+ * 0b0100..Function 4
+ * 0b0101..Function 5
+ * 0b0110..Function 6
+ * 0b0111..Function 7
+ * 0b1000..Function 8
+ * 0b1001..Function 9
+ * 0b1010..Function 10
+ * 0b1011..Function 11
+ * 0b1100..Function 12
+ * 0b1101..Function 13
+ * 0b1110..Function 14
+ * 0b1111..Function 15
+ */
+#define IOPCTL_FC15_I2C_SDA_FSEL(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_FSEL_SHIFT)) & IOPCTL_FC15_I2C_SDA_FSEL_MASK)
+#define IOPCTL_FC15_I2C_SDA_PUPDENA_MASK (0x10U)
+#define IOPCTL_FC15_I2C_SDA_PUPDENA_SHIFT (4U)
+/*! PUPDENA - Pullup / Pulldown Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define IOPCTL_FC15_I2C_SDA_PUPDENA(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_PUPDENA_SHIFT)) & IOPCTL_FC15_I2C_SDA_PUPDENA_MASK)
+#define IOPCTL_FC15_I2C_SDA_PUPDSEL_MASK (0x20U)
+#define IOPCTL_FC15_I2C_SDA_PUPDSEL_SHIFT (5U)
+/*! PUPDSEL - Pullup or Pulldown Selector
+ * 0b0..Pull-down
+ * 0b1..Pull-up
+ */
+#define IOPCTL_FC15_I2C_SDA_PUPDSEL(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_PUPDSEL_SHIFT)) & IOPCTL_FC15_I2C_SDA_PUPDSEL_MASK)
+#define IOPCTL_FC15_I2C_SDA_IBENA_MASK (0x40U)
+#define IOPCTL_FC15_I2C_SDA_IBENA_SHIFT (6U)
+/*! IBENA - Input Buffer Enable
+ * 0b0..Input buffer disabled
+ * 0b1..Input buffer enabled
+ */
+#define IOPCTL_FC15_I2C_SDA_IBENA(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_IBENA_SHIFT)) & IOPCTL_FC15_I2C_SDA_IBENA_MASK)
+#define IOPCTL_FC15_I2C_SDA_SLEWRATE_MASK (0x80U)
+#define IOPCTL_FC15_I2C_SDA_SLEWRATE_SHIFT (7U)
+/*! SLEWRATE - Slew Rate Control
+ * 0b0..Standard mode, output slew rate is not controlled.
+ * 0b1..Slow mode, output slew rate control is enabled, limiting the output rate change and maximum toggle
+ * frequency. See device datasheet for details.
+ */
+#define IOPCTL_FC15_I2C_SDA_SLEWRATE(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_SLEWRATE_SHIFT)) & IOPCTL_FC15_I2C_SDA_SLEWRATE_MASK)
+#define IOPCTL_FC15_I2C_SDA_FULLDRIVE_MASK (0x100U)
+#define IOPCTL_FC15_I2C_SDA_FULLDRIVE_SHIFT (8U)
+/*! FULLDRIVE - Drive Selector
+ * 0b0..Normal output drive
+ * 0b1..Full output drive, twice the drive of normal mode.
+ */
+#define IOPCTL_FC15_I2C_SDA_FULLDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_FULLDRIVE_SHIFT)) & IOPCTL_FC15_I2C_SDA_FULLDRIVE_MASK)
+#define IOPCTL_FC15_I2C_SDA_AMENA_MASK (0x200U)
+#define IOPCTL_FC15_I2C_SDA_AMENA_SHIFT (9U)
+/*! AMENA - Analog Mux Enable
+ * 0b0..Analog multiplexor disabled, required for digital pin function
+ * 0b1..Analog multiplexor enabled, required for analog pin function
+ */
+#define IOPCTL_FC15_I2C_SDA_AMENA(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_AMENA_SHIFT)) & IOPCTL_FC15_I2C_SDA_AMENA_MASK)
+#define IOPCTL_FC15_I2C_SDA_ODENA_MASK (0x400U)
+#define IOPCTL_FC15_I2C_SDA_ODENA_SHIFT (10U)
+/*! ODENA - Open-drain mode enable
+ * 0b0..Normal push-pull output
+ * 0b1..Simulated open-drain output (high drive disabled)
+ */
+#define IOPCTL_FC15_I2C_SDA_ODENA(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_ODENA_SHIFT)) & IOPCTL_FC15_I2C_SDA_ODENA_MASK)
+#define IOPCTL_FC15_I2C_SDA_IIENA_MASK (0x800U)
+#define IOPCTL_FC15_I2C_SDA_IIENA_SHIFT (11U)
+/*! IIENA - Input Invert Enable
+ * 0b0..Disabled, Input function is not inverted
+ * 0b1..Enabled, Input is function inverted
+ */
+#define IOPCTL_FC15_I2C_SDA_IIENA(x) (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_IIENA_SHIFT)) & IOPCTL_FC15_I2C_SDA_IIENA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group IOPCTL_Register_Masks */
+
+
+/* IOPCTL - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral IOPCTL base address */
+ #define IOPCTL_BASE (0x50004000u)
+ /** Peripheral IOPCTL base address */
+ #define IOPCTL_BASE_NS (0x40004000u)
+ /** Peripheral IOPCTL base pointer */
+ #define IOPCTL ((IOPCTL_Type *)IOPCTL_BASE)
+ /** Peripheral IOPCTL base pointer */
+ #define IOPCTL_NS ((IOPCTL_Type *)IOPCTL_BASE_NS)
+ /** Array initializer of IOPCTL peripheral base addresses */
+ #define IOPCTL_BASE_ADDRS { IOPCTL_BASE }
+ /** Array initializer of IOPCTL peripheral base pointers */
+ #define IOPCTL_BASE_PTRS { IOPCTL }
+ /** Array initializer of IOPCTL peripheral base addresses */
+ #define IOPCTL_BASE_ADDRS_NS { IOPCTL_BASE_NS }
+ /** Array initializer of IOPCTL peripheral base pointers */
+ #define IOPCTL_BASE_PTRS_NS { IOPCTL_NS }
+#else
+ /** Peripheral IOPCTL base address */
+ #define IOPCTL_BASE (0x40004000u)
+ /** Peripheral IOPCTL base pointer */
+ #define IOPCTL ((IOPCTL_Type *)IOPCTL_BASE)
+ /** Array initializer of IOPCTL peripheral base addresses */
+ #define IOPCTL_BASE_ADDRS { IOPCTL_BASE }
+ /** Array initializer of IOPCTL peripheral base pointers */
+ #define IOPCTL_BASE_PTRS { IOPCTL }
+#endif
+
+/*!
+ * @}
+ */ /* end of group IOPCTL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LCDIF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
+ * @{
+ */
+
+/** LCDIF - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[4672];
+ __IO uint32_t FRAMEBUFFERCONFIG0; /**< Frame buffer configuration0, offset: 0x1240 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t FRAMEBUFFERADDRESS0; /**< Starting address of the frame buffer, offset: 0x1260 */
+ uint8_t RESERVED_2[28];
+ __IO uint32_t FRAMEBUFFERSTRIDE0; /**< Stride of the frame buffer in bytes, offset: 0x1280 */
+ uint8_t RESERVED_3[220];
+ __IO uint32_t DISPLAYDITHERCONFIG0; /**< Configuration register for dithering, offset: 0x1360 */
+ uint8_t RESERVED_4[28];
+ __IO uint32_t DISPLAYDITHERTABLELOW0; /**< Dither table low, offset: 0x1380 */
+ uint8_t RESERVED_5[28];
+ __IO uint32_t DISPLAYDITHERTABLEHIGH0; /**< Dither table high, offset: 0x13A0 */
+ uint8_t RESERVED_6[28];
+ __IO uint32_t PANELCONFIG0; /**< Panel configuration, offset: 0x13C0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t PANELTIMING0; /**< Timing for hardware panel sequencing, offset: 0x13E0 */
+ uint8_t RESERVED_8[28];
+ __IO uint32_t HDISPLAY0; /**< Horizontal Total and Display End counters, offset: 0x1400 */
+ uint8_t RESERVED_9[28];
+ __IO uint32_t HSYNC0; /**< Horizontal Sync counters, offset: 0x1420 */
+ uint8_t RESERVED_10[92];
+ __IO uint32_t VDISPLAY0; /**< Vertical Total and Display End counters, offset: 0x1480 */
+ uint8_t RESERVED_11[28];
+ __IO uint32_t VSYNC0; /**< Vertical Sync counters, offset: 0x14A0 */
+ uint8_t RESERVED_12[28];
+ __I uint32_t DISPLAYCURRENTLOCATION0; /**< Current x,y location of display controller, offset: 0x14C0 */
+ uint8_t RESERVED_13[28];
+ __IO uint32_t GAMMAINDEX0; /**< Index into gamma table, offset: 0x14E0 */
+ uint8_t RESERVED_14[28];
+ __IO uint32_t GAMMADATA0; /**< Translation values for the gamma table, offset: 0x1500 */
+ uint8_t RESERVED_15[28];
+ __IO uint32_t CURSORCONFIG; /**< Configuration register for the cursor, offset: 0x1520 */
+ uint8_t RESERVED_16[12];
+ __IO uint32_t CURSORADDRESS; /**< Address of the cursor shape, offset: 0x1530 */
+ uint8_t RESERVED_17[12];
+ __IO uint32_t CURSORLOCATION; /**< Location of the cursor on the owning display, offset: 0x1540 */
+ uint8_t RESERVED_18[12];
+ __IO uint32_t CURSORBACKGROUND; /**< The background color for Masked cursors, offset: 0x1550 */
+ uint8_t RESERVED_19[12];
+ __IO uint32_t CURSORFOREGROUND; /**< The foreground color for Masked cursors, offset: 0x1560 */
+ uint8_t RESERVED_20[156];
+ __IO uint32_t DISPLAYINTR; /**< Display interrupt register, offset: 0x1600 */
+ uint8_t RESERVED_21[12];
+ __IO uint32_t DISPLAYINTRENABLE; /**< The interrupt enable register for display_0 (and display_1 if present), offset: 0x1610 */
+ uint8_t RESERVED_22[12];
+ __IO uint32_t DBICONFIG0; /**< Configuration register for DBI output, offset: 0x1620 */
+ uint8_t RESERVED_23[28];
+ __O uint32_t DBIIFRESET0; /**< Reset DBI interface to idle state, offset: 0x1640 */
+ uint8_t RESERVED_24[28];
+ __IO uint32_t DBIWRCHAR10; /**< DBI write AC characteristics definition register 1, offset: 0x1660 */
+ uint8_t RESERVED_25[28];
+ __IO uint32_t DBIWRCHAR20; /**< DBI write AC characteristics definition register 2, offset: 0x1680 */
+ uint8_t RESERVED_26[28];
+ __O uint32_t DBICMD0; /**< DBI Command in/out port, offset: 0x16A0 */
+ uint8_t RESERVED_27[28];
+ __IO uint32_t DPICONFIG0; /**< The configuration register for DPI output, offset: 0x16C0 */
+ uint8_t RESERVED_28[44];
+ __I uint32_t DCCHIPREV; /**< Revision for the LCDIF peripheral in BCD, offset: 0x16F0 */
+ uint8_t RESERVED_29[12];
+ __I uint32_t DCCHIPDATE; /**< Shows the release date for the IP in YYYYMMDD (year, month), offset: 0x1700 */
+ uint8_t RESERVED_30[28];
+ __I uint32_t DCCHIPPATCHREV; /**< Patch revision, offset: 0x1720 */
+ uint8_t RESERVED_31[28];
+ __IO uint32_t DCTILEINCFG0; /**< Tile input configuration, offset: 0x1740 */
+ uint8_t RESERVED_32[28];
+ __IO uint32_t DCTILEUVFRAMEBUFFERADR0; /**< UV frame buffer address when tile input, offset: 0x1760 */
+ uint8_t RESERVED_33[28];
+ __IO uint32_t DCTILEUVFRAMEBUFFERSTR0; /**< UV frame buffer stride when tile input, offset: 0x1780 */
+ uint8_t RESERVED_34[44];
+ __I uint32_t DCPRODUCTID; /**< Product ID, offset: 0x17B0 */
+ uint8_t RESERVED_35[108];
+ __IO uint32_t DEBUGCOUNTERSELECT0; /**< Debug counter select, offset: 0x1820 */
+ uint8_t RESERVED_36[28];
+ __IO uint32_t DEBUGCOUNTERVALUE0; /**< Debug counter value, offset: 0x1840 */
+} LCDIF_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LCDIF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCDIF_Register_Masks LCDIF Register Masks
+ * @{
+ */
+
+/*! @name FRAMEBUFFERCONFIG0 - Frame buffer configuration0 */
+/*! @{ */
+#define LCDIF_FRAMEBUFFERCONFIG0_FORMAT_MASK (0x7U)
+#define LCDIF_FRAMEBUFFERCONFIG0_FORMAT_SHIFT (0U)
+/*! FORMAT - The format of the frame buffer.
+ */
+#define LCDIF_FRAMEBUFFERCONFIG0_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_FORMAT_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_FORMAT_MASK)
+#define LCDIF_FRAMEBUFFERCONFIG0_MODE_MASK (0x10U)
+#define LCDIF_FRAMEBUFFERCONFIG0_MODE_SHIFT (4U)
+/*! MODE - Mode of the frame buffer.
+ * 0b0..LINEAR
+ * 0b1..TILE4x4 INPUT
+ */
+#define LCDIF_FRAMEBUFFERCONFIG0_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_MODE_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_MODE_MASK)
+#define LCDIF_FRAMEBUFFERCONFIG0_OUTPUT_MASK (0x100U)
+#define LCDIF_FRAMEBUFFERCONFIG0_OUTPUT_SHIFT (8U)
+/*! OUTPUT - When Output is enabled, pixels will be displayed. When Output is disabled, all pixels
+ * will be black. This allows a panel to have correct timing but without any pixels.
+ * 0b0..DISABLED
+ * 0b1..ENABLED
+ */
+#define LCDIF_FRAMEBUFFERCONFIG0_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_OUTPUT_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_OUTPUT_MASK)
+#define LCDIF_FRAMEBUFFERCONFIG0_SWITCHPANEL_MASK (0x200U)
+#define LCDIF_FRAMEBUFFERCONFIG0_SWITCHPANEL_SHIFT (9U)
+/*! SWITCHPANEL - Switch panel.
+ * 0b0..DISABLED
+ * 0b1..ENABLED
+ */
+#define LCDIF_FRAMEBUFFERCONFIG0_SWITCHPANEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_SWITCHPANEL_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_SWITCHPANEL_MASK)
+#define LCDIF_FRAMEBUFFERCONFIG0_GAMMA_MASK (0x1000U)
+#define LCDIF_FRAMEBUFFERCONFIG0_GAMMA_SHIFT (12U)
+/*! GAMMA
+ * 0b0..DISABLED
+ * 0b1..ENABLED
+ */
+#define LCDIF_FRAMEBUFFERCONFIG0_GAMMA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_GAMMA_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_GAMMA_MASK)
+#define LCDIF_FRAMEBUFFERCONFIG0_VALID_MASK (0x10000U)
+#define LCDIF_FRAMEBUFFERCONFIG0_VALID_SHIFT (16U)
+/*! VALID
+ * 0b0..WORKING
+ * 0b1..PENDING
+ */
+#define LCDIF_FRAMEBUFFERCONFIG0_VALID(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_VALID_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_VALID_MASK)
+#define LCDIF_FRAMEBUFFERCONFIG0_RESET_MASK (0x100000U)
+#define LCDIF_FRAMEBUFFERCONFIG0_RESET_SHIFT (20U)
+/*! RESET
+ * 0b0..For DBI, this field should be = 0.
+ * 0b1..Enable DPI Timing, start a DPI transfer.
+ */
+#define LCDIF_FRAMEBUFFERCONFIG0_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_RESET_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_RESET_MASK)
+#define LCDIF_FRAMEBUFFERCONFIG0_UNDERFLOW_MASK (0x1000000U)
+#define LCDIF_FRAMEBUFFERCONFIG0_UNDERFLOW_SHIFT (24U)
+/*! UNDERFLOW - Underflow.
+ * 0b0..Disable.
+ * 0b1..Enable.
+ */
+#define LCDIF_FRAMEBUFFERCONFIG0_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_UNDERFLOW_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_UNDERFLOW_MASK)
+#define LCDIF_FRAMEBUFFERCONFIG0_FLIP_IN_PROGRESS_MASK (0x10000000U)
+#define LCDIF_FRAMEBUFFERCONFIG0_FLIP_IN_PROGRESS_SHIFT (28U)
+/*! FLIP_IN_PROGRESS
+ * 0b0..DISABLED
+ * 0b1..ENABLED
+ */
+#define LCDIF_FRAMEBUFFERCONFIG0_FLIP_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_FLIP_IN_PROGRESS_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_FLIP_IN_PROGRESS_MASK)
+#define LCDIF_FRAMEBUFFERCONFIG0_BACK_PRESSURE_DISABLE_MASK (0x20000000U)
+#define LCDIF_FRAMEBUFFERCONFIG0_BACK_PRESSURE_DISABLE_SHIFT (29U)
+/*! BACK_PRESSURE_DISABLE - Disable back pressure.
+ * 0b0..Disable.
+ * 0b1..Enable.
+ */
+#define LCDIF_FRAMEBUFFERCONFIG0_BACK_PRESSURE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_BACK_PRESSURE_DISABLE_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_BACK_PRESSURE_DISABLE_MASK)
+/*! @} */
+
+/*! @name FRAMEBUFFERADDRESS0 - Starting address of the frame buffer */
+/*! @{ */
+#define LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_MASK (0x7FFFFFFFU)
+#define LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_SHIFT (0U)
+/*! ADDRESS - ADDRESS
+ */
+#define LCDIF_FRAMEBUFFERADDRESS0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_SHIFT)) & LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_MASK)
+#define LCDIF_FRAMEBUFFERADDRESS0_TYPE_MASK (0x80000000U)
+#define LCDIF_FRAMEBUFFERADDRESS0_TYPE_SHIFT (31U)
+/*! TYPE - System type.
+ * 0b0..System.
+ * 0b1..Virtual system.
+ */
+#define LCDIF_FRAMEBUFFERADDRESS0_TYPE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERADDRESS0_TYPE_SHIFT)) & LCDIF_FRAMEBUFFERADDRESS0_TYPE_MASK)
+/*! @} */
+
+/*! @name FRAMEBUFFERSTRIDE0 - Stride of the frame buffer in bytes */
+/*! @{ */
+#define LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_MASK (0x1FFFFU)
+#define LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_SHIFT (0U)
+/*! STRIDE - Number of bytes from start of one line to next line. This value needs to be 128 byte aligned.
+ */
+#define LCDIF_FRAMEBUFFERSTRIDE0_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_SHIFT)) & LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_MASK)
+/*! @} */
+
+/*! @name DISPLAYDITHERCONFIG0 - Configuration register for dithering */
+/*! @{ */
+#define LCDIF_DISPLAYDITHERCONFIG0_BLUE_SIZE_MASK (0xFU)
+#define LCDIF_DISPLAYDITHERCONFIG0_BLUE_SIZE_SHIFT (0U)
+/*! BLUE_SIZE - Number of important bits for the blue channel for the panel. Start counting from MSB.
+ */
+#define LCDIF_DISPLAYDITHERCONFIG0_BLUE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERCONFIG0_BLUE_SIZE_SHIFT)) & LCDIF_DISPLAYDITHERCONFIG0_BLUE_SIZE_MASK)
+#define LCDIF_DISPLAYDITHERCONFIG0_GREEN_SIZE_MASK (0xF00U)
+#define LCDIF_DISPLAYDITHERCONFIG0_GREEN_SIZE_SHIFT (8U)
+/*! GREEN_SIZE - Number of important bits for the green channel for the panel. Start counting from MSB.
+ */
+#define LCDIF_DISPLAYDITHERCONFIG0_GREEN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERCONFIG0_GREEN_SIZE_SHIFT)) & LCDIF_DISPLAYDITHERCONFIG0_GREEN_SIZE_MASK)
+#define LCDIF_DISPLAYDITHERCONFIG0_RED_SIZE_MASK (0xF0000U)
+#define LCDIF_DISPLAYDITHERCONFIG0_RED_SIZE_SHIFT (16U)
+/*! RED_SIZE - Number of important bits for the red channel for the panel. Start counting from MSB.
+ */
+#define LCDIF_DISPLAYDITHERCONFIG0_RED_SIZE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERCONFIG0_RED_SIZE_SHIFT)) & LCDIF_DISPLAYDITHERCONFIG0_RED_SIZE_MASK)
+#define LCDIF_DISPLAYDITHERCONFIG0_ENABLE_MASK (0x80000000U)
+#define LCDIF_DISPLAYDITHERCONFIG0_ENABLE_SHIFT (31U)
+/*! ENABLE - Enabling dithering allows R8G8B8 modes to show better on panels with less bits-per-pixel.
+ * 0b0..DISABLED
+ * 0b1..ENABLED
+ */
+#define LCDIF_DISPLAYDITHERCONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERCONFIG0_ENABLE_SHIFT)) & LCDIF_DISPLAYDITHERCONFIG0_ENABLE_MASK)
+/*! @} */
+
+/*! @name DISPLAYDITHERTABLELOW0 - Dither table low */
+/*! @{ */
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_MASK (0xFU)
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_SHIFT (0U)
+/*! Y0_X0 - Dither threshold value for x,y=0,0.
+ */
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_MASK)
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_MASK (0xF0U)
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_SHIFT (4U)
+/*! Y0_X1 - Dither threshold value for x,y=1,0.
+ */
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_MASK)
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_MASK (0xF00U)
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_SHIFT (8U)
+/*! Y0_X2 - Dither threshold value for x,y=2,0.
+ */
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_MASK)
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_MASK (0xF000U)
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_SHIFT (12U)
+/*! Y0_X3 - Dither threshold value for x,y=3,0.
+ */
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_MASK)
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_MASK (0xF0000U)
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_SHIFT (16U)
+/*! Y1_X0 - Dither threshold value for x,y=0,1.
+ */
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_MASK)
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_MASK (0xF00000U)
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_SHIFT (20U)
+/*! Y1_X1 - Dither threshold value for x,y=1,1.
+ */
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_MASK)
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_MASK (0xF000000U)
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_SHIFT (24U)
+/*! Y1_X2 - Dither threshold value for x,y=2,1.
+ */
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_MASK)
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_MASK (0xF0000000U)
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_SHIFT (28U)
+/*! Y1_X3 - Dither threshold value for x,y=3,1.
+ */
+#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_MASK)
+/*! @} */
+
+/*! @name DISPLAYDITHERTABLEHIGH0 - Dither table high */
+/*! @{ */
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_MASK (0xFU)
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_SHIFT (0U)
+/*! Y2_X0 - Dither threshold value for x,y=0,2.
+ */
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_MASK)
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_MASK (0xF0U)
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_SHIFT (4U)
+/*! Y2_X1 - Dither threshold value for x,y=1,2.
+ */
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_MASK)
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_MASK (0xF00U)
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_SHIFT (8U)
+/*! Y2_X2 - Dither threshold value for x,y=2,2.
+ */
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_MASK)
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_MASK (0xF000U)
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_SHIFT (12U)
+/*! Y2_X3 - Dither threshold value for x,y=3,2.
+ */
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_MASK)
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_MASK (0xF0000U)
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_SHIFT (16U)
+/*! Y3_X0 - Dither threshold value for x,y=0,3.
+ */
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_MASK)
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_MASK (0xF00000U)
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_SHIFT (20U)
+/*! Y3_X1 - Dither threshold value for x,y=1,3.
+ */
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_MASK)
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_MASK (0xF000000U)
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_SHIFT (24U)
+/*! Y3_X2 - Dither threshold value for x,y=2,3.
+ */
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_MASK)
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_MASK (0xF0000000U)
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_SHIFT (28U)
+/*! Y3_X3 - Dither threshold value for x,y=3,3.
+ */
+#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_MASK)
+/*! @} */
+
+/*! @name PANELCONFIG0 - Panel configuration */
+/*! @{ */
+#define LCDIF_PANELCONFIG0_DE_MASK (0x1U)
+#define LCDIF_PANELCONFIG0_DE_SHIFT (0U)
+/*! DE - Data Enable enabled/disabled.
+ * 0b0..DISABLED
+ * 0b1..ENABLED
+ */
+#define LCDIF_PANELCONFIG0_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_DE_SHIFT)) & LCDIF_PANELCONFIG0_DE_MASK)
+#define LCDIF_PANELCONFIG0_DE_POLARITY_MASK (0x2U)
+#define LCDIF_PANELCONFIG0_DE_POLARITY_SHIFT (1U)
+/*! DE_POLARITY - Data Enable polarity.
+ * 0b0..POSITIVE
+ * 0b1..NEGATIVE
+ */
+#define LCDIF_PANELCONFIG0_DE_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_DE_POLARITY_SHIFT)) & LCDIF_PANELCONFIG0_DE_POLARITY_MASK)
+#define LCDIF_PANELCONFIG0_DATA_POLARITY_MASK (0x20U)
+#define LCDIF_PANELCONFIG0_DATA_POLARITY_SHIFT (5U)
+/*! DATA_POLARITY - Data polarity.
+ * 0b0..POSITIVE
+ * 0b1..NEGATIVE
+ */
+#define LCDIF_PANELCONFIG0_DATA_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_DATA_POLARITY_SHIFT)) & LCDIF_PANELCONFIG0_DATA_POLARITY_MASK)
+#define LCDIF_PANELCONFIG0_CLOCK_MASK (0x100U)
+#define LCDIF_PANELCONFIG0_CLOCK_SHIFT (8U)
+/*! CLOCK - Clock enable/disable.
+ * 0b0..DISABLED
+ * 0b1..ENABLED
+ */
+#define LCDIF_PANELCONFIG0_CLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_CLOCK_SHIFT)) & LCDIF_PANELCONFIG0_CLOCK_MASK)
+#define LCDIF_PANELCONFIG0_CLOCK_POLARITY_MASK (0x200U)
+#define LCDIF_PANELCONFIG0_CLOCK_POLARITY_SHIFT (9U)
+/*! CLOCK_POLARITY - Clock polarity.
+ * 0b0..POSITIVE
+ * 0b1..NEGATIVE
+ */
+#define LCDIF_PANELCONFIG0_CLOCK_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_CLOCK_POLARITY_SHIFT)) & LCDIF_PANELCONFIG0_CLOCK_POLARITY_MASK)
+#define LCDIF_PANELCONFIG0_SEQUENCING_MASK (0x80000000U)
+#define LCDIF_PANELCONFIG0_SEQUENCING_SHIFT (31U)
+/*! SEQUENCING - Enable software or hardware panel sequencing.
+ * 0b0..HARDWARE
+ * 0b1..SOFTWARE
+ */
+#define LCDIF_PANELCONFIG0_SEQUENCING(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_SEQUENCING_SHIFT)) & LCDIF_PANELCONFIG0_SEQUENCING_MASK)
+/*! @} */
+
+/*! @name PANELTIMING0 - Timing for hardware panel sequencing */
+/*! @{ */
+#define LCDIF_PANELTIMING0_POWER_ENABLE_MASK (0xFU)
+#define LCDIF_PANELTIMING0_POWER_ENABLE_SHIFT (0U)
+/*! POWER_ENABLE - Number of VSYNCsto wait after power has been enabled.
+ */
+#define LCDIF_PANELTIMING0_POWER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_POWER_ENABLE_SHIFT)) & LCDIF_PANELTIMING0_POWER_ENABLE_MASK)
+#define LCDIF_PANELTIMING0_BACKLIGHT_ENABLE_MASK (0xF0U)
+#define LCDIF_PANELTIMING0_BACKLIGHT_ENABLE_SHIFT (4U)
+/*! BACKLIGHT_ENABLE - Number of VSYNCs to wait after backlight has been enabled.
+ */
+#define LCDIF_PANELTIMING0_BACKLIGHT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_BACKLIGHT_ENABLE_SHIFT)) & LCDIF_PANELTIMING0_BACKLIGHT_ENABLE_MASK)
+#define LCDIF_PANELTIMING0_CLOCK_ENABLE_MASK (0xF00U)
+#define LCDIF_PANELTIMING0_CLOCK_ENABLE_SHIFT (8U)
+/*! CLOCK_ENABLE - Number of VSYNCs to wait after clock has been enabled.
+ */
+#define LCDIF_PANELTIMING0_CLOCK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_CLOCK_ENABLE_SHIFT)) & LCDIF_PANELTIMING0_CLOCK_ENABLE_MASK)
+#define LCDIF_PANELTIMING0_DATA_ENABLE_MASK (0xF000U)
+#define LCDIF_PANELTIMING0_DATA_ENABLE_SHIFT (12U)
+/*! DATA_ENABLE - Number of VSYNCs to wait after data has been enabled.
+ */
+#define LCDIF_PANELTIMING0_DATA_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_DATA_ENABLE_SHIFT)) & LCDIF_PANELTIMING0_DATA_ENABLE_MASK)
+#define LCDIF_PANELTIMING0_DATA_DISABLE_MASK (0xF0000U)
+#define LCDIF_PANELTIMING0_DATA_DISABLE_SHIFT (16U)
+/*! DATA_DISABLE - Number of VSYNCs to wait after data has been disabled.
+ */
+#define LCDIF_PANELTIMING0_DATA_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_DATA_DISABLE_SHIFT)) & LCDIF_PANELTIMING0_DATA_DISABLE_MASK)
+#define LCDIF_PANELTIMING0_CLOCK_DISABLE_MASK (0xF00000U)
+#define LCDIF_PANELTIMING0_CLOCK_DISABLE_SHIFT (20U)
+/*! CLOCK_DISABLE - Number of VSYNCs to wait after clock has been disabled.
+ */
+#define LCDIF_PANELTIMING0_CLOCK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_CLOCK_DISABLE_SHIFT)) & LCDIF_PANELTIMING0_CLOCK_DISABLE_MASK)
+#define LCDIF_PANELTIMING0_BACKLIGHT_DISABLE_MASK (0xF000000U)
+#define LCDIF_PANELTIMING0_BACKLIGHT_DISABLE_SHIFT (24U)
+/*! BACKLIGHT_DISABLE - Number of VSYNCs to wait after backlight has been disabled.
+ */
+#define LCDIF_PANELTIMING0_BACKLIGHT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_BACKLIGHT_DISABLE_SHIFT)) & LCDIF_PANELTIMING0_BACKLIGHT_DISABLE_MASK)
+#define LCDIF_PANELTIMING0_POWER_DISABLE_MASK (0xF0000000U)
+#define LCDIF_PANELTIMING0_POWER_DISABLE_SHIFT (28U)
+/*! POWER_DISABLE - Number of VSYNCs to wait after power has been disabled.
+ */
+#define LCDIF_PANELTIMING0_POWER_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_POWER_DISABLE_SHIFT)) & LCDIF_PANELTIMING0_POWER_DISABLE_MASK)
+/*! @} */
+
+/*! @name HDISPLAY0 - Horizontal Total and Display End counters */
+/*! @{ */
+#define LCDIF_HDISPLAY0_DISPLAY_END_MASK (0x1FFFU)
+#define LCDIF_HDISPLAY0_DISPLAY_END_SHIFT (0U)
+/*! DISPLAY_END - Number of visible horizontal pixels.
+ */
+#define LCDIF_HDISPLAY0_DISPLAY_END(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_HDISPLAY0_DISPLAY_END_SHIFT)) & LCDIF_HDISPLAY0_DISPLAY_END_MASK)
+#define LCDIF_HDISPLAY0_TOTAL_MASK (0x1FFF0000U)
+#define LCDIF_HDISPLAY0_TOTAL_SHIFT (16U)
+/*! TOTAL - Total number of horizontal pixels.
+ */
+#define LCDIF_HDISPLAY0_TOTAL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_HDISPLAY0_TOTAL_SHIFT)) & LCDIF_HDISPLAY0_TOTAL_MASK)
+/*! @} */
+
+/*! @name HSYNC0 - Horizontal Sync counters */
+/*! @{ */
+#define LCDIF_HSYNC0_START_MASK (0x1FFFU)
+#define LCDIF_HSYNC0_START_SHIFT (0U)
+/*! START - Start of horizontal sync pulse.
+ */
+#define LCDIF_HSYNC0_START(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_START_SHIFT)) & LCDIF_HSYNC0_START_MASK)
+#define LCDIF_HSYNC0_END_MASK (0x1FFF0000U)
+#define LCDIF_HSYNC0_END_SHIFT (16U)
+/*! END - End of horizontal sync pulse.
+ */
+#define LCDIF_HSYNC0_END(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_END_SHIFT)) & LCDIF_HSYNC0_END_MASK)
+#define LCDIF_HSYNC0_PULSE_MASK (0x40000000U)
+#define LCDIF_HSYNC0_PULSE_SHIFT (30U)
+/*! PULSE - Horizontal sync pulse control.
+ * 0b0..DISABLED
+ * 0b1..ENABLED
+ */
+#define LCDIF_HSYNC0_PULSE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_PULSE_SHIFT)) & LCDIF_HSYNC0_PULSE_MASK)
+#define LCDIF_HSYNC0_POLARITY_MASK (0x80000000U)
+#define LCDIF_HSYNC0_POLARITY_SHIFT (31U)
+/*! POLARITY - Polarity of the horizontal sync pulse
+ * 0b0..POSITIVE
+ * 0b1..NEGATIVE
+ */
+#define LCDIF_HSYNC0_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_POLARITY_SHIFT)) & LCDIF_HSYNC0_POLARITY_MASK)
+/*! @} */
+
+/*! @name VDISPLAY0 - Vertical Total and Display End counters */
+/*! @{ */
+#define LCDIF_VDISPLAY0_DISPLAY_END_MASK (0xFFFU)
+#define LCDIF_VDISPLAY0_DISPLAY_END_SHIFT (0U)
+/*! DISPLAY_END - Number of visible vertical lines.
+ */
+#define LCDIF_VDISPLAY0_DISPLAY_END(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDISPLAY0_DISPLAY_END_SHIFT)) & LCDIF_VDISPLAY0_DISPLAY_END_MASK)
+#define LCDIF_VDISPLAY0_TOTAL_MASK (0xFFF0000U)
+#define LCDIF_VDISPLAY0_TOTAL_SHIFT (16U)
+/*! TOTAL - Total number of vertical lines.
+ */
+#define LCDIF_VDISPLAY0_TOTAL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDISPLAY0_TOTAL_SHIFT)) & LCDIF_VDISPLAY0_TOTAL_MASK)
+/*! @} */
+
+/*! @name VSYNC0 - Vertical Sync counters */
+/*! @{ */
+#define LCDIF_VSYNC0_START_MASK (0xFFFU)
+#define LCDIF_VSYNC0_START_SHIFT (0U)
+/*! START - Start of the vertical sync pulse.
+ */
+#define LCDIF_VSYNC0_START(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_START_SHIFT)) & LCDIF_VSYNC0_START_MASK)
+#define LCDIF_VSYNC0_END_MASK (0xFFF0000U)
+#define LCDIF_VSYNC0_END_SHIFT (16U)
+/*! END - End of the vertical sync pulse.
+ */
+#define LCDIF_VSYNC0_END(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_END_SHIFT)) & LCDIF_VSYNC0_END_MASK)
+#define LCDIF_VSYNC0_PULSE_MASK (0x40000000U)
+#define LCDIF_VSYNC0_PULSE_SHIFT (30U)
+/*! PULSE - Vertical sync pulse control.
+ * 0b0..DISABLED
+ * 0b1..ENABLED
+ */
+#define LCDIF_VSYNC0_PULSE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_PULSE_SHIFT)) & LCDIF_VSYNC0_PULSE_MASK)
+#define LCDIF_VSYNC0_POLARITY_MASK (0x80000000U)
+#define LCDIF_VSYNC0_POLARITY_SHIFT (31U)
+/*! POLARITY - Polarity of the vertical sync pulse.
+ * 0b0..POSITIVE
+ * 0b1..ACTIVE-LOW
+ */
+#define LCDIF_VSYNC0_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_POLARITY_SHIFT)) & LCDIF_VSYNC0_POLARITY_MASK)
+/*! @} */
+
+/*! @name DISPLAYCURRENTLOCATION0 - Current x,y location of display controller */
+/*! @{ */
+#define LCDIF_DISPLAYCURRENTLOCATION0_X_MASK (0xFFFFU)
+#define LCDIF_DISPLAYCURRENTLOCATION0_X_SHIFT (0U)
+/*! X - Current X location.
+ */
+#define LCDIF_DISPLAYCURRENTLOCATION0_X(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYCURRENTLOCATION0_X_SHIFT)) & LCDIF_DISPLAYCURRENTLOCATION0_X_MASK)
+#define LCDIF_DISPLAYCURRENTLOCATION0_Y_MASK (0xFFFF0000U)
+#define LCDIF_DISPLAYCURRENTLOCATION0_Y_SHIFT (16U)
+/*! Y - Current Y location.
+ */
+#define LCDIF_DISPLAYCURRENTLOCATION0_Y(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYCURRENTLOCATION0_Y_SHIFT)) & LCDIF_DISPLAYCURRENTLOCATION0_Y_MASK)
+/*! @} */
+
+/*! @name GAMMAINDEX0 - Index into gamma table */
+/*! @{ */
+#define LCDIF_GAMMAINDEX0_INDEX_MASK (0xFFU)
+#define LCDIF_GAMMAINDEX0_INDEX_SHIFT (0U)
+/*! INDEX - Index into gamma table.
+ */
+#define LCDIF_GAMMAINDEX0_INDEX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMAINDEX0_INDEX_SHIFT)) & LCDIF_GAMMAINDEX0_INDEX_MASK)
+/*! @} */
+
+/*! @name GAMMADATA0 - Translation values for the gamma table */
+/*! @{ */
+#define LCDIF_GAMMADATA0_BLUE_MASK (0xFFU)
+#define LCDIF_GAMMADATA0_BLUE_SHIFT (0U)
+/*! BLUE - Blue translation value.
+ */
+#define LCDIF_GAMMADATA0_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMADATA0_BLUE_SHIFT)) & LCDIF_GAMMADATA0_BLUE_MASK)
+#define LCDIF_GAMMADATA0_GREEN_MASK (0xFF00U)
+#define LCDIF_GAMMADATA0_GREEN_SHIFT (8U)
+/*! GREEN - Green translation value.
+ */
+#define LCDIF_GAMMADATA0_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMADATA0_GREEN_SHIFT)) & LCDIF_GAMMADATA0_GREEN_MASK)
+#define LCDIF_GAMMADATA0_RED_MASK (0xFF0000U)
+#define LCDIF_GAMMADATA0_RED_SHIFT (16U)
+/*! RED - Red translation value.
+ */
+#define LCDIF_GAMMADATA0_RED(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMADATA0_RED_SHIFT)) & LCDIF_GAMMADATA0_RED_MASK)
+/*! @} */
+
+/*! @name CURSORCONFIG - Configuration register for the cursor */
+/*! @{ */
+#define LCDIF_CURSORCONFIG_FORMAT_MASK (0x3U)
+#define LCDIF_CURSORCONFIG_FORMAT_SHIFT (0U)
+/*! FORMAT - Format of the cursor.
+ * 0b00..DISABLED
+ * 0b01..MASKED
+ * 0b10..A8R8G8B8
+ */
+#define LCDIF_CURSORCONFIG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_FORMAT_SHIFT)) & LCDIF_CURSORCONFIG_FORMAT_MASK)
+#define LCDIF_CURSORCONFIG_DISPLAY_MASK (0x10U)
+#define LCDIF_CURSORCONFIG_DISPLAY_SHIFT (4U)
+/*! DISPLAY - Display Controller owning the cursor.
+ * 0b0..DISPLAY0
+ * 0b1..DISPLAY1
+ */
+#define LCDIF_CURSORCONFIG_DISPLAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_DISPLAY_SHIFT)) & LCDIF_CURSORCONFIG_DISPLAY_MASK)
+#define LCDIF_CURSORCONFIG_HOT_SPOT_Y_MASK (0x1F00U)
+#define LCDIF_CURSORCONFIG_HOT_SPOT_Y_SHIFT (8U)
+/*! HOT_SPOT_Y - Vertical offset to cursor hotspot.
+ */
+#define LCDIF_CURSORCONFIG_HOT_SPOT_Y(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_HOT_SPOT_Y_SHIFT)) & LCDIF_CURSORCONFIG_HOT_SPOT_Y_MASK)
+#define LCDIF_CURSORCONFIG_HOT_SPOT_X_MASK (0x1F0000U)
+#define LCDIF_CURSORCONFIG_HOT_SPOT_X_SHIFT (16U)
+/*! HOT_SPOT_X - Horizontal offset to cursor hotspot.
+ */
+#define LCDIF_CURSORCONFIG_HOT_SPOT_X(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_HOT_SPOT_X_SHIFT)) & LCDIF_CURSORCONFIG_HOT_SPOT_X_MASK)
+#define LCDIF_CURSORCONFIG_FLIP_IN_PROGRESS_MASK (0x80000000U)
+#define LCDIF_CURSORCONFIG_FLIP_IN_PROGRESS_SHIFT (31U)
+/*! FLIP_IN_PROGRESS - When the cursor address gets written to, this bit gets set to one.
+ */
+#define LCDIF_CURSORCONFIG_FLIP_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_FLIP_IN_PROGRESS_SHIFT)) & LCDIF_CURSORCONFIG_FLIP_IN_PROGRESS_MASK)
+/*! @} */
+
+/*! @name CURSORADDRESS - Address of the cursor shape */
+/*! @{ */
+#define LCDIF_CURSORADDRESS_ADDRESS_MASK (0x7FFFFFFFU)
+#define LCDIF_CURSORADDRESS_ADDRESS_SHIFT (0U)
+/*! ADDRESS - ADDRESS
+ */
+#define LCDIF_CURSORADDRESS_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORADDRESS_ADDRESS_SHIFT)) & LCDIF_CURSORADDRESS_ADDRESS_MASK)
+#define LCDIF_CURSORADDRESS_TYPE_MASK (0x80000000U)
+#define LCDIF_CURSORADDRESS_TYPE_SHIFT (31U)
+/*! TYPE - System type.
+ * 0b0..System.
+ * 0b1..Virtual system.
+ */
+#define LCDIF_CURSORADDRESS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORADDRESS_TYPE_SHIFT)) & LCDIF_CURSORADDRESS_TYPE_MASK)
+/*! @} */
+
+/*! @name CURSORLOCATION - Location of the cursor on the owning display */
+/*! @{ */
+#define LCDIF_CURSORLOCATION_X_MASK (0x1FFFU)
+#define LCDIF_CURSORLOCATION_X_SHIFT (0U)
+/*! X - X location of cursor's hotspot.
+ */
+#define LCDIF_CURSORLOCATION_X(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORLOCATION_X_SHIFT)) & LCDIF_CURSORLOCATION_X_MASK)
+#define LCDIF_CURSORLOCATION_Y_MASK (0xFFF0000U)
+#define LCDIF_CURSORLOCATION_Y_SHIFT (16U)
+/*! Y - Y location of cursor's hotspot.
+ */
+#define LCDIF_CURSORLOCATION_Y(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORLOCATION_Y_SHIFT)) & LCDIF_CURSORLOCATION_Y_MASK)
+/*! @} */
+
+/*! @name CURSORBACKGROUND - The background color for Masked cursors */
+/*! @{ */
+#define LCDIF_CURSORBACKGROUND_BLUE_MASK (0xFFU)
+#define LCDIF_CURSORBACKGROUND_BLUE_SHIFT (0U)
+/*! BLUE - Blue value.
+ */
+#define LCDIF_CURSORBACKGROUND_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORBACKGROUND_BLUE_SHIFT)) & LCDIF_CURSORBACKGROUND_BLUE_MASK)
+#define LCDIF_CURSORBACKGROUND_GREEN_MASK (0xFF00U)
+#define LCDIF_CURSORBACKGROUND_GREEN_SHIFT (8U)
+/*! GREEN - Green value.
+ */
+#define LCDIF_CURSORBACKGROUND_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORBACKGROUND_GREEN_SHIFT)) & LCDIF_CURSORBACKGROUND_GREEN_MASK)
+#define LCDIF_CURSORBACKGROUND_RED_MASK (0xFF0000U)
+#define LCDIF_CURSORBACKGROUND_RED_SHIFT (16U)
+/*! RED - Red value.
+ */
+#define LCDIF_CURSORBACKGROUND_RED(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORBACKGROUND_RED_SHIFT)) & LCDIF_CURSORBACKGROUND_RED_MASK)
+/*! @} */
+
+/*! @name CURSORFOREGROUND - The foreground color for Masked cursors */
+/*! @{ */
+#define LCDIF_CURSORFOREGROUND_BLUE_MASK (0xFFU)
+#define LCDIF_CURSORFOREGROUND_BLUE_SHIFT (0U)
+/*! BLUE - Blue value.
+ */
+#define LCDIF_CURSORFOREGROUND_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORFOREGROUND_BLUE_SHIFT)) & LCDIF_CURSORFOREGROUND_BLUE_MASK)
+#define LCDIF_CURSORFOREGROUND_GREEN_MASK (0xFF00U)
+#define LCDIF_CURSORFOREGROUND_GREEN_SHIFT (8U)
+/*! GREEN - Green value.
+ */
+#define LCDIF_CURSORFOREGROUND_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORFOREGROUND_GREEN_SHIFT)) & LCDIF_CURSORFOREGROUND_GREEN_MASK)
+#define LCDIF_CURSORFOREGROUND_RED_MASK (0xFF0000U)
+#define LCDIF_CURSORFOREGROUND_RED_SHIFT (16U)
+/*! RED - Red value.
+ */
+#define LCDIF_CURSORFOREGROUND_RED(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORFOREGROUND_RED_SHIFT)) & LCDIF_CURSORFOREGROUND_RED_MASK)
+/*! @} */
+
+/*! @name DISPLAYINTR - Display interrupt register */
+/*! @{ */
+#define LCDIF_DISPLAYINTR_DISP0_MASK (0x1U)
+#define LCDIF_DISPLAYINTR_DISP0_SHIFT (0U)
+/*! DISP0 - Display0 interrupt
+ */
+#define LCDIF_DISPLAYINTR_DISP0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTR_DISP0_SHIFT)) & LCDIF_DISPLAYINTR_DISP0_MASK)
+/*! @} */
+
+/*! @name DISPLAYINTRENABLE - The interrupt enable register for display_0 (and display_1 if present) */
+/*! @{ */
+#define LCDIF_DISPLAYINTRENABLE_DISP0_MASK (0x1U)
+#define LCDIF_DISPLAYINTRENABLE_DISP0_SHIFT (0U)
+/*! DISP0 - Display0 interrupt enable
+ */
+#define LCDIF_DISPLAYINTRENABLE_DISP0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTRENABLE_DISP0_SHIFT)) & LCDIF_DISPLAYINTRENABLE_DISP0_MASK)
+/*! @} */
+
+/*! @name DBICONFIG0 - Configuration register for DBI output */
+/*! @{ */
+#define LCDIF_DBICONFIG0_DBI_DATA_FORMAT_MASK (0x3CU)
+#define LCDIF_DBICONFIG0_DBI_DATA_FORMAT_SHIFT (2U)
+/*! DBI_DATA_FORMAT - DBI interface data format.
+ */
+#define LCDIF_DBICONFIG0_DBI_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBI_DATA_FORMAT_SHIFT)) & LCDIF_DBICONFIG0_DBI_DATA_FORMAT_MASK)
+#define LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_MASK (0x40U)
+#define LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_SHIFT (6U)
+/*! BUS_OUTPUT_SEL - Output bus select.
+ * 0b0..DPI
+ * 0b1..DBI
+ */
+#define LCDIF_DBICONFIG0_BUS_OUTPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_SHIFT)) & LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_MASK)
+#define LCDIF_DBICONFIG0_DBIX_POLARITY_MASK (0x80U)
+#define LCDIF_DBICONFIG0_DBIX_POLARITY_SHIFT (7U)
+/*! DBIX_POLARITY - D/CX Pin polarity.
+ * 0b0..DEFAULT
+ * 0b1..REVERSE
+ */
+#define LCDIF_DBICONFIG0_DBIX_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBIX_POLARITY_SHIFT)) & LCDIF_DBICONFIG0_DBIX_POLARITY_MASK)
+#define LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_MASK (0xF00U)
+#define LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_SHIFT (8U)
+/*! DBI_AC_TIME_UNIT - Time unit for AC characteristics
+ */
+#define LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_SHIFT)) & LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_MASK)
+/*! @} */
+
+/*! @name DBIIFRESET0 - Reset DBI interface to idle state */
+/*! @{ */
+#define LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_MASK (0x1U)
+#define LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_SHIFT (0U)
+/*! DBI_IF_LEVEL_RESET - Reset DBI interface to idle state 1=RESET;
+ */
+#define LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_SHIFT)) & LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_MASK)
+/*! @} */
+
+/*! @name DBIWRCHAR10 - DBI write AC characteristics definition register 1 */
+/*! @{ */
+#define LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_MASK (0xFFU)
+#define LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_SHIFT (0U)
+/*! DBI_WR_PERIOD - Single write period duration.
+ */
+#define LCDIF_DBIWRCHAR10_DBI_WR_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_SHIFT)) & LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_MASK)
+#define LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_MASK (0xF00U)
+#define LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_SHIFT (8U)
+/*! DBI_WR_EOR_WR_ASSERT - Cycle number=Setting*(DbiAcTimeUnit+1).
+ */
+#define LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_SHIFT)) & LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_MASK)
+#define LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_MASK (0xF000U)
+#define LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_SHIFT (12U)
+/*! DBI_WR_CS_ASSERT - Cycle number=Setting*(DbiAcTimeUnit+1).
+ */
+#define LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_SHIFT)) & LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_MASK)
+/*! @} */
+
+/*! @name DBIWRCHAR20 - DBI write AC characteristics definition register 2 */
+/*! @{ */
+#define LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_MASK (0xFFU)
+#define LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_SHIFT (0U)
+/*! DBI_WR_EOR_WR_DE_ASRT - Cycle number=Setting*(DbiAcTimeUnit+1).
+ */
+#define LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_SHIFT)) & LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_MASK)
+#define LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_MASK (0xFF00U)
+#define LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_SHIFT (8U)
+/*! DBI_WR_CS_DE_ASRT - Cycle number=Setting*(DbiAcTimeUnit+1).
+ */
+#define LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_SHIFT)) & LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_MASK)
+/*! @} */
+
+/*! @name DBICMD0 - DBI Command in/out port */
+/*! @{ */
+#define LCDIF_DBICMD0_DBI_COMMAND_WORD_MASK (0xFFFFU)
+#define LCDIF_DBICMD0_DBI_COMMAND_WORD_SHIFT (0U)
+/*! DBI_COMMAND_WORD - The type of data contained in this word is specified using DBI_COMMANDFLAG[bits 31:30].
+ */
+#define LCDIF_DBICMD0_DBI_COMMAND_WORD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICMD0_DBI_COMMAND_WORD_SHIFT)) & LCDIF_DBICMD0_DBI_COMMAND_WORD_MASK)
+#define LCDIF_DBICMD0_DBI_COMMANDFLAG_MASK (0xC0000000U)
+#define LCDIF_DBICMD0_DBI_COMMANDFLAG_SHIFT (30U)
+/*! DBI_COMMANDFLAG - DBI command flag.
+ * 0b00..ADDRESS
+ * 0b01..WRITE_MEM_START
+ * 0b10..PARAMETER_OR_DATA
+ * 0b11..READ
+ */
+#define LCDIF_DBICMD0_DBI_COMMANDFLAG(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICMD0_DBI_COMMANDFLAG_SHIFT)) & LCDIF_DBICMD0_DBI_COMMANDFLAG_MASK)
+/*! @} */
+
+/*! @name DPICONFIG0 - The configuration register for DPI output */
+/*! @{ */
+#define LCDIF_DPICONFIG0_DPI_DATA_FORMAT_MASK (0x7U)
+#define LCDIF_DPICONFIG0_DPI_DATA_FORMAT_SHIFT (0U)
+/*! DPI_DATA_FORMAT - DPI interface data format.
+ * 0b000..D16CFG1
+ * 0b001..D16CFG2
+ * 0b010..D16CFG3
+ * 0b011..D18CFG1
+ * 0b100..D18CFG2
+ * 0b101..D24
+ * 0b110-0b111..-
+ */
+#define LCDIF_DPICONFIG0_DPI_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DPICONFIG0_DPI_DATA_FORMAT_SHIFT)) & LCDIF_DPICONFIG0_DPI_DATA_FORMAT_MASK)
+/*! @} */
+
+/*! @name DCCHIPREV - Revision for the LCDIF peripheral in BCD */
+/*! @{ */
+#define LCDIF_DCCHIPREV_REV_MASK (0xFFFFFFFFU)
+#define LCDIF_DCCHIPREV_REV_SHIFT (0U)
+/*! REV - Revision.
+ */
+#define LCDIF_DCCHIPREV_REV(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DCCHIPREV_REV_SHIFT)) & LCDIF_DCCHIPREV_REV_MASK)
+/*! @} */
+
+/*! @name DCCHIPDATE - Shows the release date for the IP in YYYYMMDD (year, month) */
+/*! @{ */
+#define LCDIF_DCCHIPDATE_DATE_MASK (0xFFFFFFFFU)
+#define LCDIF_DCCHIPDATE_DATE_SHIFT (0U)
+/*! DATE - Date.
+ */
+#define LCDIF_DCCHIPDATE_DATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DCCHIPDATE_DATE_SHIFT)) & LCDIF_DCCHIPDATE_DATE_MASK)
+/*! @} */
+
+/*! @name DCCHIPPATCHREV - Patch revision */
+/*! @{ */
+#define LCDIF_DCCHIPPATCHREV_PATCH_REV_MASK (0xFFFFFFFFU)
+#define LCDIF_DCCHIPPATCHREV_PATCH_REV_SHIFT (0U)
+/*! PATCH_REV - Patch revision.
+ */
+#define LCDIF_DCCHIPPATCHREV_PATCH_REV(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DCCHIPPATCHREV_PATCH_REV_SHIFT)) & LCDIF_DCCHIPPATCHREV_PATCH_REV_MASK)
+/*! @} */
+
+/*! @name DCTILEINCFG0 - Tile input configuration */
+/*! @{ */
+#define LCDIF_DCTILEINCFG0_TILE_FORMAT_MASK (0x3U)
+#define LCDIF_DCTILEINCFG0_TILE_FORMAT_SHIFT (0U)
+/*! TILE_FORMAT - Tile input data format 0 means non-tile input
+ */
+#define LCDIF_DCTILEINCFG0_TILE_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEINCFG0_TILE_FORMAT_SHIFT)) & LCDIF_DCTILEINCFG0_TILE_FORMAT_MASK)
+#define LCDIF_DCTILEINCFG0_YUV_STANDARD_MASK (0xCU)
+#define LCDIF_DCTILEINCFG0_YUV_STANDARD_SHIFT (2U)
+/*! YUV_STANDARD - YUV standard select.
+ * 0b00..BT601
+ * 0b01..BT709
+ */
+#define LCDIF_DCTILEINCFG0_YUV_STANDARD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEINCFG0_YUV_STANDARD_SHIFT)) & LCDIF_DCTILEINCFG0_YUV_STANDARD_MASK)
+#define LCDIF_DCTILEINCFG0_YUV2_RGB_EN_MASK (0x10U)
+#define LCDIF_DCTILEINCFG0_YUV2_RGB_EN_SHIFT (4U)
+/*! YUV2_RGB_EN - YUV2RGB module enable
+ * 0b0..DISABLED
+ * 0b1..ENABLED
+ */
+#define LCDIF_DCTILEINCFG0_YUV2_RGB_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEINCFG0_YUV2_RGB_EN_SHIFT)) & LCDIF_DCTILEINCFG0_YUV2_RGB_EN_MASK)
+#define LCDIF_DCTILEINCFG0_CFG_MODE_EN_MASK (0x20U)
+#define LCDIF_DCTILEINCFG0_CFG_MODE_EN_SHIFT (5U)
+/*! CFG_MODE_EN - Configuration mode enable.
+ * 0b0..DISABLED
+ * 0b1..ENABLED
+ */
+#define LCDIF_DCTILEINCFG0_CFG_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEINCFG0_CFG_MODE_EN_SHIFT)) & LCDIF_DCTILEINCFG0_CFG_MODE_EN_MASK)
+/*! @} */
+
+/*! @name DCTILEUVFRAMEBUFFERADR0 - UV frame buffer address when tile input */
+/*! @{ */
+#define LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_MASK (0xFFFFFFFFU)
+#define LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_SHIFT (0U)
+/*! ADDRESS - UV frame buffer address when tile input
+ */
+#define LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_SHIFT)) & LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_MASK)
+/*! @} */
+
+/*! @name DCTILEUVFRAMEBUFFERSTR0 - UV frame buffer stride when tile input */
+/*! @{ */
+#define LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_MASK (0xFFFFU)
+#define LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_SHIFT (0U)
+/*! STRIDE - UV frame buffer stride when tile input
+ */
+#define LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_SHIFT)) & LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_MASK)
+/*! @} */
+
+/*! @name DCPRODUCTID - Product ID */
+/*! @{ */
+#define LCDIF_DCPRODUCTID_PRODUCT_ID_MASK (0xFFFFFFFFU)
+#define LCDIF_DCPRODUCTID_PRODUCT_ID_SHIFT (0U)
+/*! PRODUCT_ID - Product ID
+ */
+#define LCDIF_DCPRODUCTID_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DCPRODUCTID_PRODUCT_ID_SHIFT)) & LCDIF_DCPRODUCTID_PRODUCT_ID_MASK)
+/*! @} */
+
+/*! @name DEBUGCOUNTERSELECT0 - Debug counter select */
+/*! @{ */
+#define LCDIF_DEBUGCOUNTERSELECT0_SELECT_MASK (0xFFU)
+#define LCDIF_DEBUGCOUNTERSELECT0_SELECT_SHIFT (0U)
+/*! SELECT - Write a value to this field to pick up from 0~255 counters.
+ */
+#define LCDIF_DEBUGCOUNTERSELECT0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DEBUGCOUNTERSELECT0_SELECT_SHIFT)) & LCDIF_DEBUGCOUNTERSELECT0_SELECT_MASK)
+/*! @} */
+
+/*! @name DEBUGCOUNTERVALUE0 - Debug counter value */
+/*! @{ */
+#define LCDIF_DEBUGCOUNTERVALUE0_VALUE_MASK (0xFFFFFFFFU)
+#define LCDIF_DEBUGCOUNTERVALUE0_VALUE_SHIFT (0U)
+/*! VALUE - Selected debug counter value
+ */
+#define LCDIF_DEBUGCOUNTERVALUE0_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DEBUGCOUNTERVALUE0_VALUE_SHIFT)) & LCDIF_DEBUGCOUNTERVALUE0_VALUE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LCDIF_Register_Masks */
+
+
+/* LCDIF - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral LCDIF base address */
+ #define LCDIF_BASE (0x50210000u)
+ /** Peripheral LCDIF base address */
+ #define LCDIF_BASE_NS (0x40210000u)
+ /** Peripheral LCDIF base pointer */
+ #define LCDIF ((LCDIF_Type *)LCDIF_BASE)
+ /** Peripheral LCDIF base pointer */
+ #define LCDIF_NS ((LCDIF_Type *)LCDIF_BASE_NS)
+ /** Array initializer of LCDIF peripheral base addresses */
+ #define LCDIF_BASE_ADDRS { LCDIF_BASE }
+ /** Array initializer of LCDIF peripheral base pointers */
+ #define LCDIF_BASE_PTRS { LCDIF }
+ /** Array initializer of LCDIF peripheral base addresses */
+ #define LCDIF_BASE_ADDRS_NS { LCDIF_BASE_NS }
+ /** Array initializer of LCDIF peripheral base pointers */
+ #define LCDIF_BASE_PTRS_NS { LCDIF_NS }
+#else
+ /** Peripheral LCDIF base address */
+ #define LCDIF_BASE (0x40210000u)
+ /** Peripheral LCDIF base pointer */
+ #define LCDIF ((LCDIF_Type *)LCDIF_BASE)
+ /** Array initializer of LCDIF peripheral base addresses */
+ #define LCDIF_BASE_ADDRS { LCDIF_BASE }
+ /** Array initializer of LCDIF peripheral base pointers */
+ #define LCDIF_BASE_PTRS { LCDIF }
+#endif
+/** Interrupt vectors for the LCDIF peripheral type */
+#define LCDIF_IRQ0_IRQS { LCDIF_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LCDIF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MIPI_DSI_HOST Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MIPI_DSI_HOST_Peripheral_Access_Layer MIPI_DSI_HOST Peripheral Access Layer
+ * @{
+ */
+
+/** MIPI_DSI_HOST - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t DSI_HOST_CFG_NUM_LANES; /**< , offset: 0x0 */
+ __IO uint32_t DSI_HOST_CFG_NONCONTINUOUS_CLK; /**< , offset: 0x4 */
+ __IO uint32_t DSI_HOST_CFG_T_PRE; /**< , offset: 0x8 */
+ __IO uint32_t DSI_HOST_CFG_T_POST; /**< , offset: 0xC */
+ __IO uint32_t DSI_HOST_CFG_TX_GAP; /**< , offset: 0x10 */
+ __IO uint32_t DSI_HOST_CFG_AUTOINSERT_EOTP; /**< , offset: 0x14 */
+ __IO uint32_t DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP; /**< , offset: 0x18 */
+ __IO uint32_t DSI_HOST_CFG_HTX_TO_COUNT; /**< , offset: 0x1C */
+ __IO uint32_t DSI_HOST_CFG_LRX_H_TO_COUNT; /**< , offset: 0x20 */
+ __IO uint32_t DSI_HOST_CFG_BTA_H_TO_COUNT; /**< , offset: 0x24 */
+ __IO uint32_t DSI_HOST_CFG_TWAKEUP; /**< , offset: 0x28 */
+ __I uint32_t DSI_HOST_CFG_STATUS_OUT; /**< , offset: 0x2C */
+ __I uint32_t DSI_HOST_RX_ERROR_STATUS; /**< , offset: 0x30 */
+ uint8_t RESERVED_0[204];
+ __IO uint32_t DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE; /**< , offset: 0x100 */
+ __IO uint32_t DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL; /**< , offset: 0x104 */
+ uint8_t RESERVED_1[248];
+ __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE; /**< , offset: 0x200 */
+ __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL; /**< , offset: 0x204 */
+ __IO uint32_t DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING; /**< , offset: 0x208 */
+ __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FORMAT; /**< , offset: 0x20C */
+ __IO uint32_t DSI_HOST_CFG_DPI_VSYNC_POLARITY; /**< , offset: 0x210 */
+ __IO uint32_t DSI_HOST_CFG_DPI_HSYNC_POLARITY; /**< , offset: 0x214 */
+ __IO uint32_t DSI_HOST_CFG_DPI_VIDEO_MODE; /**< , offset: 0x218 */
+ __IO uint32_t DSI_HOST_CFG_DPI_HFP; /**< , offset: 0x21C */
+ __IO uint32_t DSI_HOST_CFG_DPI_HBP; /**< , offset: 0x220 */
+ __IO uint32_t DSI_HOST_CFG_DPI_HSA; /**< , offset: 0x224 */
+ __IO uint32_t DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS; /**< , offset: 0x228 */
+ __IO uint32_t DSI_HOST_CFG_DPI_VBP; /**< , offset: 0x22C */
+ __IO uint32_t DSI_HOST_CFG_DPI_VFP; /**< , offset: 0x230 */
+ __IO uint32_t DSI_HOST_CFG_DPI_BLLP_MODE; /**< , offset: 0x234 */
+ __IO uint32_t DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP; /**< , offset: 0x238 */
+ __IO uint32_t DSI_HOST_CFG_DPI_VACTIVE; /**< , offset: 0x23C */
+ __IO uint32_t DSI_HOST_CFG_DPI_VC; /**< , offset: 0x240 */
+ uint8_t RESERVED_2[60];
+ __IO uint32_t DSI_HOST_TX_PAYLOAD; /**< , offset: 0x280 */
+ __IO uint32_t DSI_HOST_PKT_CONTROL; /**< , offset: 0x284 */
+ __IO uint32_t DSI_HOST_SEND_PACKET; /**< , offset: 0x288 */
+ __I uint32_t DSI_HOST_PKT_STATUS; /**< , offset: 0x28C */
+ __I uint32_t DSI_HOST_PKT_FIFO_WR_LEVEL; /**< , offset: 0x290 */
+ __I uint32_t DSI_HOST_PKT_FIFO_RD_LEVEL; /**< , offset: 0x294 */
+ __I uint32_t DSI_HOST_PKT_RX_PAYLOAD; /**< , offset: 0x298 */
+ __I uint32_t DSI_HOST_PKT_RX_PKT_HEADER; /**< , offset: 0x29C */
+ __I uint32_t DSI_HOST_IRQ_STATUS; /**< , offset: 0x2A0 */
+ __I uint32_t DSI_HOST_IRQ_STATUS2; /**< , offset: 0x2A4 */
+ __IO uint32_t DSI_HOST_IRQ_MASK; /**< , offset: 0x2A8 */
+ __IO uint32_t DSI_HOST_IRQ_MASK2; /**< , offset: 0x2AC */
+ uint8_t RESERVED_3[80];
+ __IO uint32_t DPHY_PD_DPHY; /**< , offset: 0x300 */
+ __IO uint32_t DPHY_M_PRG_HS_PREPARE; /**< , offset: 0x304 */
+ __IO uint32_t DPHY_MC_PRG_HS_PREPARE; /**< , offset: 0x308 */
+ __IO uint32_t DPHY_M_PRG_HS_ZERO; /**< , offset: 0x30C */
+ __IO uint32_t DPHY_MC_PRG_HS_ZERO; /**< , offset: 0x310 */
+ __IO uint32_t DPHY_M_PRG_HS_TRAIL; /**< , offset: 0x314 */
+ __IO uint32_t DPHY_MC_PRG_HS_TRAIL; /**< , offset: 0x318 */
+ __IO uint32_t DPHY_TST; /**< , offset: 0x31C */
+ __IO uint32_t DPHY_RTERM_SEL; /**< , offset: 0x320 */
+ __IO uint32_t DPHY_AUTO_PD_EN; /**< , offset: 0x324 */
+ __IO uint32_t DPHY_RXLPRP; /**< , offset: 0x328 */
+ __IO uint32_t DPHY_RXCDRP; /**< , offset: 0x32C */
+} MIPI_DSI_HOST_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MIPI_DSI_HOST Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MIPI_DSI_HOST_Register_Masks MIPI_DSI_HOST Register Masks
+ * @{
+ */
+
+/*! @name DSI_HOST_CFG_NUM_LANES - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK (0x3U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT (0U)
+/*! dsi_host_cfg_num_lanes - Sets the number of active lanes that are to be used for transmitting data.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_MASK (0xFFFFFFFCU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_SHIFT (2U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_NONCONTINUOUS_CLK - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK (0x1U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT (0U)
+/*! dsi_host_cfg_noncontinuous_clk - Sets the Host Controller into non-continuous MIPI clock mode.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_MASK (0xFFFFFFFEU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_SHIFT (1U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_T_PRE - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK (0x7FU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT (0U)
+/*! dsi_host_cfg_t_pre - Sets the number of byte clock periods ('clk_byte' input) that the
+ * controller will wait after enabling the clock lane for HS operation before enabling the data lanes for
+ * HS operation.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_MASK (0xFFFFFF80U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_SHIFT (7U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_T_POST - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK (0x7FU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT (0U)
+/*! dsi_host_cfg_t_post - Sets the number of byte clock periods ('clk_byte' input) to wait before
+ * putting the clock lane into LP mode after the data lanes have been detected to be in Stop State.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_MASK (0xFFFFFF80U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_SHIFT (7U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_TX_GAP - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK (0x7FU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT (0U)
+/*! dsi_host_cfg_tx_gap - Sets the number of byte clock periods ('clk_byte' input) that the
+ * controller will wait after the clock lane has been put into LP mode before enabling the clock lane for
+ * HS mode again.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_MASK (0xFFFFFF80U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_SHIFT (7U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_AUTOINSERT_EOTP - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK (0x1U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT (0U)
+/*! dsi_host_cfg_autoinsert_eotp - Enables the Host Controller to automatically insert an EoTp short packet when switching from HS to LP mode.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_MASK (0xFFFFFFFEU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_SHIFT (1U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK (0xFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT (0U)
+/*! dsi_host_cfg_extra_cmds_after_eotp - Configures the DSI Host Controller to send extra End Of Transmission Packets after the end of a packet.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_MASK (0xFFFFFF00U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_SHIFT (8U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_HTX_TO_COUNT - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK (0xFFFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT (0U)
+/*! dsi_host_cfg_htx_to_count - Sets the value of the DSI Host High Speed TX timeout count in
+ * clk_byte clock periods that once reached will initiate a timeout error and follow the recovery
+ * procedure documented in the DSI specification.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_MASK (0xFF000000U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_SHIFT (24U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_LRX_H_TO_COUNT - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK (0xFFFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT (0U)
+/*! dsi_host_cfg_lrx_h_to_count - Sets the value of the DSI Host low power RX timeout count in
+ * clk_byte clock periods that once reached will initiate a timeout error and follow the recovery
+ * procedure documented in the DSI specification.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_MASK (0xFF000000U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_SHIFT (24U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_BTA_H_TO_COUNT - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK (0xFFFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT (0U)
+/*! dsi_host_cfg_bta_h_to_count - Sets the value of the DSI Host Bus Turn Around (BTA) timeout in
+ * clk_byte clock periods that once reached will initiate a timeout error.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_MASK (0xFF000000U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_SHIFT (24U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_TWAKEUP - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK (0x7FFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT (0U)
+/*! dsi_host_cfg_twakeup - DPHY Twakeup timing parameter.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_MASK (0xFFF80000U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_SHIFT (19U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_STATUS_OUT - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_MASK (0xFFFFFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_SHIFT (0U)
+/*! dsi_host_cfg_status_out - Status Register
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_RX_ERROR_STATUS - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK (0x7FFU)
+#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT (0U)
+/*! dsi_host_rx_error_status - Status Register for Host receive error detection, ECC errors, CRC
+ * errors and for timeout indicators [0] ECC single bit error detected [1] ECC multi bit error
+ * detected [6:2] Errored bit position for single bit ECC error [7] CRC error detected [8] High Speed
+ * forward TX timeout detected [9] Reverse Low power data receive timeout detected [10] BTA
+ * timeout detected
+ */
+#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_MASK (0xFFFFF800U)
+#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_SHIFT (11U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dbi_pixel_payload_size_MASK (0xFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dbi_pixel_payload_size_SHIFT (0U)
+/*! dsi_host_cfg_dbi_pixel_payload_size - Maximum number of pixels that should be sent as one DSI packet.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dbi_pixel_payload_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dbi_pixel_payload_size_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dbi_pixel_payload_size_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_reserved_MASK (0xFFFF0000U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_reserved_SHIFT (16U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dbi_pixel_fifo_send_level_MASK (0xFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dbi_pixel_fifo_send_level_SHIFT (0U)
+/*! dsi_host_cfg_dbi_pixel_fifo_send_level - In order to optimize DSI utility, the DBI bridge buffers a cerntain number of DBI pixels before initiating a DSI packet.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dbi_pixel_fifo_send_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dbi_pixel_fifo_send_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dbi_pixel_fifo_send_level_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_reserved_MASK (0xFFFF0000U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_reserved_SHIFT (16U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK (0xFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT (0U)
+/*! dsi_host_cfg_dpi_pixel_payload_size - Maximum number of pixels that should be sent as one DSI packet.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_MASK (0xFFFF0000U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_SHIFT (16U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK (0xFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT (0U)
+/*! dsi_host_cfg_dpi_pixel_fifo_send_level - In order to optimize DSI utility, the DPI bridge buffers a cerntain number of DPI pixels before initiating a DSI packet.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_MASK (0xFFFF0000U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_SHIFT (16U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK (0x7U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT (0U)
+/*! dsi_host_cfg_dpi_interface_color_coding - Sets the distribution of RGB bits within the 24-bit d bus, as specified by the DPI specification.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_MASK (0xFFFFFFF8U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_SHIFT (3U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_PIXEL_FORMAT - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK (0x3U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT (0U)
+/*! dsi_host_cfg_dpi_pixel_format - Sets the DSI packet type of the pixels.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_MASK (0xFFFFFFFCU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_SHIFT (2U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_VSYNC_POLARITY - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK (0x1U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT (0U)
+/*! dsi_host_cfg_dpi_vsync_polarity - Sets polarity of dpi_vsync_input 0 - active low 1 - active high
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_MASK (0xFFFFFFFEU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_SHIFT (1U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_HSYNC_POLARITY - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK (0x1U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT (0U)
+/*! dsi_host_cfg_dpi_hsync_polarity - Sets polarity of dpi_hsync_input 0 - active low 1 - active high
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_MASK (0xFFFFFFFEU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_SHIFT (1U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_VIDEO_MODE - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK (0x3U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT (0U)
+/*! dsi_host_cfg_dpi_video_mode - Select DSI video mode that the host DPI module should generate packets for.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_MASK (0xFFFFFFFCU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_SHIFT (2U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_HFP - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK (0xFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT (0U)
+/*! dsi_host_cfg_dpi_hfp - Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_MASK (0xFFFF0000U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_SHIFT (16U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_HBP - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK (0xFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT (0U)
+/*! dsi_host_cfg_dpi_hbp - Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_MASK (0xFFFF0000U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_SHIFT (16U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_HSA - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK (0xFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT (0U)
+/*! dsi_host_cfg_dpi_hsa - Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_MASK (0xFFFF0000U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_SHIFT (16U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK (0x1U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT (0U)
+/*! dsi_host_cfg_dpi_enable_mult_pkts - Enable Multiple packets per video line.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_MASK (0xFFFFFFFEU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_SHIFT (1U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_VBP - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK (0xFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT (0U)
+/*! dsi_host_cfg_dpi_vbp - Sets the number of lines in the vertical back porch.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_MASK (0xFFFFFF00U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_SHIFT (8U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_VFP - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK (0xFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT (0U)
+/*! dsi_host_cfg_dpi_vfp - Sets the number of lines in the vertical front porch.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_MASK (0xFFFFFF00U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_SHIFT (8U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_BLLP_MODE - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK (0x1U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT (0U)
+/*! dsi_host_cfg_dpi_bllp_mode - Optimize bllp periods to Low Power mode when possible 0 - blanking
+ * packets are sent during BLLP periods 1 - LP mode is used for BLLP periods
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_MASK (0xFFFFFFFEU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_SHIFT (1U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK (0x1U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT (0U)
+/*! dsi_host_cfg_dpi_use_null_pkt_bllp - Selects type of blanking packet to be sent during bllp
+ * region 0 - Blanking packet used in bllp region 1 - Null packet used in bllp region
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_MASK (0xFFFFFFFEU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_SHIFT (1U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_VACTIVE - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK (0x3FFFU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT (0U)
+/*! dsi_host_cfg_dpi_vactive - Sets the number of lines in the vertical active aread.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_MASK (0xFFFFC000U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_SHIFT (14U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_CFG_DPI_VC - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK (0x3U)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT (0U)
+/*! dsi_host_cfg_dpi_vc - Sets the Virtual Channel (VC) of packets that will be sent to the receive packet interface.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_MASK (0xFFFFFFFCU)
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_SHIFT (2U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_TX_PAYLOAD - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK (0xFFFFFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT (0U)
+/*! dsi_host_tx_payload - Tx Payload data write register.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_PKT_CONTROL - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK (0x7FFFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT (0U)
+/*! dsi_host_pkt_control - Tx packet control register.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_MASK (0xF8000000U)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_SHIFT (27U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_SEND_PACKET - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK (0x1U)
+#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT (0U)
+/*! dsi_host_send_packet - Tx send packet, writing to this register causes the packet described in dsi_host_pkt_control to be sent.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_MASK (0xFFFFFFFEU)
+#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_SHIFT (1U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_PKT_STATUS - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK (0x1FFU)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT (0U)
+/*! dsi_host_pkt_status - Status of APB to packet interface [0] - state machine not idle [1] - Tx
+ * packet done [2] - dphy direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow
+ * [4] - tx fifo underflow [5] - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header
+ * has been received [8] - all rx packet payload data has been received
+ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_MASK (0xFFFFFE00U)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_SHIFT (9U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_PKT_FIFO_WR_LEVEL - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK (0xFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT (0U)
+/*! dsi_host_pkt_fifo_wr_level - Write level of APB to pkt interface fifo
+ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_MASK (0xFFFF0000U)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_SHIFT (16U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_PKT_FIFO_RD_LEVEL - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK (0xFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT (0U)
+/*! dsi_host_pkt_fifo_rd_level - Read level of APB to pkt interface fifo
+ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_MASK (0xFFFF0000U)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_SHIFT (16U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_PKT_RX_PAYLOAD - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK (0xFFFFFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT (0U)
+/*! dsi_host_pkt_rx_payload - APB to pkt interface rx payload read
+ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_PKT_RX_PKT_HEADER - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK (0xFFFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT (0U)
+/*! dsi_host_pkt_rx_pkt_header - APB to pkt interface rx packet header [15:0] word count [21:16] data type [23:22] Virtual Channel
+ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_MASK (0xFF000000U)
+#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_SHIFT (24U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_IRQ_STATUS - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK (0xFFFFFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT (0U)
+/*! dsi_host_irq_status - Status of APB to packet interface [0] - state machine not idle [1] - Tx
+ * packet done [2] - dphy direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow
+ * [4] - tx fifo underflow [5] - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header
+ * has been received [8] - all rx packet payload data has been received [28:9] - map directory to
+ * dsi host controller status_out port bit descriptions [29] - high speed tx timeout, host
+ * controller hs_tx_timeout port [30] - low power rx timeout, host controller lp_rx_timeout port [31] -
+ * host bta timeout, host controller host_bta_timeout port
+ */
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_IRQ_STATUS2 - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK (0x7U)
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT (0U)
+/*! dsi_host_irq_status2 - Status of APB to packet interface part 2, read part 2 first then dsi_host_irq_status.
+ */
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_MASK (0xFFFFFFF8U)
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_SHIFT (3U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_IRQ_MASK - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK (0xFFFFFFFFU)
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT (0U)
+/*! dsi_host_irq_mask - irq mask [0] - state machine not idle [1] - Tx packet done [2] - dphy
+ * direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow [4] - tx fifo underflow [5]
+ * - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header has been received [8] - all
+ * rx packet payload data has been received [28:9] - map directory to dsi host controller
+ * status_out port bit descriptions [29] - high speed tx timeout, host controller hs_tx_timeout port
+ * [30] - low power rx timeout, host controller lp_rx_timeout port [31] - host bta timeout, host
+ * controller host_bta_timeout port
+ */
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK)
+/*! @} */
+
+/*! @name DSI_HOST_IRQ_MASK2 - */
+/*! @{ */
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK (0x7U)
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT (0U)
+/*! dsi_host_irq_mask2 - irq mask 2 [0] - single bit ecc error [1] - multi bit ecc error [2] - crc error
+ */
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK)
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_MASK (0xFFFFFFF8U)
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_SHIFT (3U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_MASK)
+/*! @} */
+
+/*! @name DPHY_PD_DPHY - */
+/*! @{ */
+#define MIPI_DSI_HOST_DPHY_PD_DPHY_dphy_pd_dphy_MASK (0x1U)
+#define MIPI_DSI_HOST_DPHY_PD_DPHY_dphy_pd_dphy_SHIFT (0U)
+/*! dphy_pd_dphy - DPHY PD_DPHY input control, see DPHY datasheet
+ */
+#define MIPI_DSI_HOST_DPHY_PD_DPHY_dphy_pd_dphy(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_DPHY_dphy_pd_dphy_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_DPHY_dphy_pd_dphy_MASK)
+#define MIPI_DSI_HOST_DPHY_PD_DPHY_reserved_MASK (0xFFFFFFFEU)
+#define MIPI_DSI_HOST_DPHY_PD_DPHY_reserved_SHIFT (1U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DPHY_PD_DPHY_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_DPHY_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_DPHY_reserved_MASK)
+/*! @} */
+
+/*! @name DPHY_M_PRG_HS_PREPARE - */
+/*! @{ */
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK (0x3U)
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT (0U)
+/*! dphy_m_prg_hs_prepare - DPHY m_PRG_HS_PREPARE input, see DPHY datasheet
+ */
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK)
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_MASK (0xFFFFFFFCU)
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_SHIFT (2U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_MASK)
+/*! @} */
+
+/*! @name DPHY_MC_PRG_HS_PREPARE - */
+/*! @{ */
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK (0x1U)
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT (0U)
+/*! dphy_mc_prg_hs_prepare - DPHY mc_PRG_HS_PREPARE input, see DPHY datasheet
+ */
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK)
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_MASK (0xFFFFFFFEU)
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_SHIFT (1U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_MASK)
+/*! @} */
+
+/*! @name DPHY_M_PRG_HS_ZERO - */
+/*! @{ */
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK (0x1FU)
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT (0U)
+/*! dphy_m_prg_hs_zero - DPHY m_PRG_HS_ZERO input, see DPHY datasheet
+ */
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK)
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_MASK (0xFFFFFFE0U)
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_SHIFT (5U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_MASK)
+/*! @} */
+
+/*! @name DPHY_MC_PRG_HS_ZERO - */
+/*! @{ */
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK (0x3FU)
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT (0U)
+/*! dphy_mc_prg_hs_zero - DPHY mc_PRG_HS_ZERO input, see DPHY datasheet
+ */
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK)
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_MASK (0xFFFFFFC0U)
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_SHIFT (6U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_MASK)
+/*! @} */
+
+/*! @name DPHY_M_PRG_HS_TRAIL - */
+/*! @{ */
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK (0xFU)
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT (0U)
+/*! dphy_m_prg_hs_trail - DPHY m_PRG_HS_TRAIL input, see DPHY datasheet
+ */
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK)
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_MASK (0xFFFFFFF0U)
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_SHIFT (4U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_MASK)
+/*! @} */
+
+/*! @name DPHY_MC_PRG_HS_TRAIL - */
+/*! @{ */
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK (0xFU)
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT (0U)
+/*! dphy_mc_prg_hs_trail - DPHY mc_PRG_HS_TRAIL input, see DPHY datasheet
+ */
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK)
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_MASK (0xFFFFFFF0U)
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_SHIFT (4U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_MASK)
+/*! @} */
+
+/*! @name DPHY_TST - */
+/*! @{ */
+#define MIPI_DSI_HOST_DPHY_TST_dphy_tst_MASK (0x3FU)
+#define MIPI_DSI_HOST_DPHY_TST_dphy_tst_SHIFT (0U)
+/*! dphy_tst - DPHY TST input, see DPHY datasheet
+ */
+#define MIPI_DSI_HOST_DPHY_TST_dphy_tst(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TST_dphy_tst_SHIFT)) & MIPI_DSI_HOST_DPHY_TST_dphy_tst_MASK)
+#define MIPI_DSI_HOST_DPHY_TST_reserved_MASK (0xFFFFFFC0U)
+#define MIPI_DSI_HOST_DPHY_TST_reserved_SHIFT (6U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DPHY_TST_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TST_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_TST_reserved_MASK)
+/*! @} */
+
+/*! @name DPHY_RTERM_SEL - */
+/*! @{ */
+#define MIPI_DSI_HOST_DPHY_RTERM_SEL_dphy_rterm_sel_MASK (0x1U)
+#define MIPI_DSI_HOST_DPHY_RTERM_SEL_dphy_rterm_sel_SHIFT (0U)
+/*! dphy_rterm_sel - DPHY RTERM_SEL input, see DPHY datasheet
+ */
+#define MIPI_DSI_HOST_DPHY_RTERM_SEL_dphy_rterm_sel(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RTERM_SEL_dphy_rterm_sel_SHIFT)) & MIPI_DSI_HOST_DPHY_RTERM_SEL_dphy_rterm_sel_MASK)
+#define MIPI_DSI_HOST_DPHY_RTERM_SEL_reserved_MASK (0xFFFFFFFEU)
+#define MIPI_DSI_HOST_DPHY_RTERM_SEL_reserved_SHIFT (1U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DPHY_RTERM_SEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RTERM_SEL_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_RTERM_SEL_reserved_MASK)
+/*! @} */
+
+/*! @name DPHY_AUTO_PD_EN - */
+/*! @{ */
+#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK (0x1U)
+#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT (0U)
+/*! dphy_auto_pd_en - DPHY AUTO_PD_EN input, see DPHY datasheet
+ */
+#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT)) & MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK)
+#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_MASK (0xFFFFFFFEU)
+#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_SHIFT (1U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_MASK)
+/*! @} */
+
+/*! @name DPHY_RXLPRP - */
+/*! @{ */
+#define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_MASK (0x3U)
+#define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_SHIFT (0U)
+/*! dphy_rxlprp - DPHY RXLPRP input, see DPHY datasheet
+ */
+#define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_SHIFT)) & MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_MASK)
+#define MIPI_DSI_HOST_DPHY_RXLPRP_reserved_MASK (0xFFFFFFFCU)
+#define MIPI_DSI_HOST_DPHY_RXLPRP_reserved_SHIFT (2U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DPHY_RXLPRP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXLPRP_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_RXLPRP_reserved_MASK)
+/*! @} */
+
+/*! @name DPHY_RXCDRP - */
+/*! @{ */
+#define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_MASK (0x3U)
+#define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_SHIFT (0U)
+/*! dphy_rxcdrp - DPHY RXCDRP input, see DPHY datasheet
+ */
+#define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_SHIFT)) & MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_MASK)
+#define MIPI_DSI_HOST_DPHY_RXCDRP_reserved_MASK (0xFFFFFFFCU)
+#define MIPI_DSI_HOST_DPHY_RXCDRP_reserved_SHIFT (2U)
+/*! reserved - reserved
+ */
+#define MIPI_DSI_HOST_DPHY_RXCDRP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXCDRP_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_RXCDRP_reserved_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MIPI_DSI_HOST_Register_Masks */
+
+
+/* MIPI_DSI_HOST - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral MIPI_DSI_HOST base address */
+ #define MIPI_DSI_HOST_BASE (0x50031000u)
+ /** Peripheral MIPI_DSI_HOST base address */
+ #define MIPI_DSI_HOST_BASE_NS (0x40031000u)
+ /** Peripheral MIPI_DSI_HOST base pointer */
+ #define MIPI_DSI_HOST ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE)
+ /** Peripheral MIPI_DSI_HOST base pointer */
+ #define MIPI_DSI_HOST_NS ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE_NS)
+ /** Array initializer of MIPI_DSI_HOST peripheral base addresses */
+ #define MIPI_DSI_HOST_BASE_ADDRS { MIPI_DSI_HOST_BASE }
+ /** Array initializer of MIPI_DSI_HOST peripheral base pointers */
+ #define MIPI_DSI_HOST_BASE_PTRS { MIPI_DSI_HOST }
+ /** Array initializer of MIPI_DSI_HOST peripheral base addresses */
+ #define MIPI_DSI_HOST_BASE_ADDRS_NS { MIPI_DSI_HOST_BASE_NS }
+ /** Array initializer of MIPI_DSI_HOST peripheral base pointers */
+ #define MIPI_DSI_HOST_BASE_PTRS_NS { MIPI_DSI_HOST_NS }
+#else
+ /** Peripheral MIPI_DSI_HOST base address */
+ #define MIPI_DSI_HOST_BASE (0x40031000u)
+ /** Peripheral MIPI_DSI_HOST base pointer */
+ #define MIPI_DSI_HOST ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE)
+ /** Array initializer of MIPI_DSI_HOST peripheral base addresses */
+ #define MIPI_DSI_HOST_BASE_ADDRS { MIPI_DSI_HOST_BASE }
+ /** Array initializer of MIPI_DSI_HOST peripheral base pointers */
+ #define MIPI_DSI_HOST_BASE_PTRS { MIPI_DSI_HOST }
+#endif
+/** Interrupt vectors for the MIPI_DSI_HOST peripheral type */
+#define MIPI_DSI_HOST_IRQS { MIPI_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MIPI_DSI_HOST_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MRT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
+ * @{
+ */
+
+/** MRT - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x10 */
+ __IO uint32_t INTVAL; /**< Time Interval Value, array offset: 0x0, array step: 0x10 */
+ __I uint32_t TIMER; /**< Timer, array offset: 0x4, array step: 0x10 */
+ __IO uint32_t CTRL; /**< Control, array offset: 0x8, array step: 0x10 */
+ __IO uint32_t STAT; /**< Status, array offset: 0xC, array step: 0x10 */
+ } CHANNEL[4];
+ uint8_t RESERVED_0[176];
+ __IO uint32_t MODCFG; /**< Module Configuration, offset: 0xF0 */
+ __I uint32_t IDLE_CH; /**< Idle Channel, offset: 0xF4 */
+ __IO uint32_t IRQ_FLAG; /**< Global Interrupt Flag, offset: 0xF8 */
+ __I uint32_t ID_CODE; /**< Multi-Rate Timer ID code, offset: 0xFC */
+} MRT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MRT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Register_Masks MRT Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_INTVAL - Time Interval Value */
+/*! @{ */
+#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU)
+#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)
+/*! IVALUE - Time interval load value.
+ */
+#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
+#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)
+#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)
+/*! LOAD - Determines how the timer interval value (IVALUE -1) is loaded into the TIMER n register.
+ * 0b0..No force load.
+ * 0b1..Force load. T
+ */
+#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_INTVAL */
+#define MRT_CHANNEL_INTVAL_COUNT (4U)
+
+/*! @name CHANNEL_TIMER - Timer */
+/*! @{ */
+#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU)
+#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)
+/*! VALUE - Holds the current timer value of the down-counter.
+ */
+#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_TIMER */
+#define MRT_CHANNEL_TIMER_COUNT (4U)
+
+/*! @name CHANNEL_CTRL - Control */
+/*! @{ */
+#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)
+#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)
+/*! INTEN - Enable the TIMER n interrupt.
+ * 0b0..Disabled. TIMER n interrupt is disabled.
+ * 0b1..Enabled. TIMER n interrupt is enabled.
+ */
+#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
+#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)
+#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)
+/*! MODE - Selects the timer mode
+ * 0b00..Repeat interrupt mode
+ * 0b01..One-shot interrupt mode
+ * 0b10..One-shot stall mode
+ * 0b11..Reserved
+ */
+#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_CTRL */
+#define MRT_CHANNEL_CTRL_COUNT (4U)
+
+/*! @name CHANNEL_STAT - Status */
+/*! @{ */
+#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)
+#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)
+/*! INTFLAG - Monitors the interrupt flag
+ * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
+ * 0b1..Pending interrupt.
+ */
+#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
+#define MRT_CHANNEL_STAT_RUN_MASK (0x2U)
+#define MRT_CHANNEL_STAT_RUN_SHIFT (1U)
+/*! RUN - Indicates the state of TIMER n. RUN bit is read-only.
+ * 0b0..Idle state. TIMER n has stopped.
+ * 0b1..Running. TIMER n is running.
+ */
+#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
+#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U)
+#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U)
+/*! INUSE - Channel-In-Use flag
+ * 0b0..This timer channel is not in use.
+ * 0b1..This timer channel is in use. Writing a 1 to this bit clears the status.
+ */
+#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
+/*! @} */
+
+/* The count of MRT_CHANNEL_STAT */
+#define MRT_CHANNEL_STAT_COUNT (4U)
+
+/*! @name MODCFG - Module Configuration */
+/*! @{ */
+#define MRT_MODCFG_NOC_MASK (0xFU)
+#define MRT_MODCFG_NOC_SHIFT (0U)
+/*! NOC - Number Of Channels: identifies the number of channels in this MRT. (Minus 1 encoded)
+ */
+#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
+#define MRT_MODCFG_NOB_MASK (0x1F0U)
+#define MRT_MODCFG_NOB_SHIFT (4U)
+/*! NOB - Number Of Bits: identifies the number of timer bits in this MRT. (24 bits on this device)
+ */
+#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
+#define MRT_MODCFG_MULTITASK_MASK (0x80000000U)
+#define MRT_MODCFG_MULTITASK_SHIFT (31U)
+/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register.
+ * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset.
+ * 0b1..Multi-task mode
+ */
+#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
+/*! @} */
+
+/*! @name IDLE_CH - Idle Channel */
+/*! @{ */
+#define MRT_IDLE_CH_CHAN_MASK (0xF0U)
+#define MRT_IDLE_CH_CHAN_SHIFT (4U)
+/*! CHAN - Idle channel.
+ */
+#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
+/*! @} */
+
+/*! @name IRQ_FLAG - Global Interrupt Flag */
+/*! @{ */
+#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)
+#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)
+/*! GFLAG0 - Monitors the interrupt flag of TIMER0.
+ * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
+ * 0b1..Pending interrupt
+ */
+#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
+#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)
+#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)
+/*! GFLAG1 - Monitors the interrupt flag of TIMER1, and acts similarly to channel 0.
+ */
+#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
+#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)
+#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)
+/*! GFLAG2 - Monitors the interrupt flag of TIMER2, and acts similarly to channel 0.
+ */
+#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
+#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)
+#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)
+/*! GFLAG3 - Monitors the interrupt flag of TIMER3, and acts similarly to channel 0.
+ */
+#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
+/*! @} */
+
+/*! @name ID_CODE - Multi-Rate Timer ID code */
+/*! @{ */
+#define MRT_ID_CODE_ID_CODE_MASK (0xFFFFFFFFU)
+#define MRT_ID_CODE_ID_CODE_SHIFT (0U)
+/*! ID_CODE - Multi-Rate Timer ID code
+ */
+#define MRT_ID_CODE_ID_CODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_ID_CODE_ID_CODE_SHIFT)) & MRT_ID_CODE_ID_CODE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MRT_Register_Masks */
+
+
+/* MRT - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral MRT0 base address */
+ #define MRT0_BASE (0x5002D000u)
+ /** Peripheral MRT0 base address */
+ #define MRT0_BASE_NS (0x4002D000u)
+ /** Peripheral MRT0 base pointer */
+ #define MRT0 ((MRT_Type *)MRT0_BASE)
+ /** Peripheral MRT0 base pointer */
+ #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS)
+ /** Array initializer of MRT peripheral base addresses */
+ #define MRT_BASE_ADDRS { MRT0_BASE }
+ /** Array initializer of MRT peripheral base pointers */
+ #define MRT_BASE_PTRS { MRT0 }
+ /** Array initializer of MRT peripheral base addresses */
+ #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS }
+ /** Array initializer of MRT peripheral base pointers */
+ #define MRT_BASE_PTRS_NS { MRT0_NS }
+#else
+ /** Peripheral MRT0 base address */
+ #define MRT0_BASE (0x4002D000u)
+ /** Peripheral MRT0 base pointer */
+ #define MRT0 ((MRT_Type *)MRT0_BASE)
+ /** Array initializer of MRT peripheral base addresses */
+ #define MRT_BASE_ADDRS { MRT0_BASE }
+ /** Array initializer of MRT peripheral base pointers */
+ #define MRT_BASE_PTRS { MRT0 }
+#endif
+/** Interrupt vectors for the MRT peripheral type */
+#define MRT_IRQS { MRT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MRT_Peripheral_Access_Layer */
+
+/*!
+ * @brief Power mode definition.
+ */
+typedef enum _mu_power_mode
+{
+ kMU_PowerModeRun = 0x00U, /*!< Run mode. */
+ kMU_PowerModeWait = 0x01U, /*!< WAIT mode. */
+} mu_power_mode_t;
+
+
+/* ----------------------------------------------------------------------------
+ -- MU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
+ * @{
+ */
+
+/** MU - Register Layout Typedef */
+typedef struct {
+ __I uint32_t VER; /**< Version ID Register, offset: 0x0 */
+ __I uint32_t PAR; /**< Parameter Register, offset: 0x4 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t TR[4]; /**< Transmit Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[16];
+ __I uint32_t RR[4]; /**< Receive Register, array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_2[16];
+ __IO uint32_t SR; /**< Status Register, offset: 0x60 */
+ __IO uint32_t CR; /**< Control Register, offset: 0x64 */
+} MU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MU_Register_Masks MU Register Masks
+ * @{
+ */
+
+/*! @name VER - Version ID Register */
+/*! @{ */
+#define MU_VER_FEATURE_MASK (0xFFFFU)
+#define MU_VER_FEATURE_SHIFT (0U)
+/*! FEATURE - Feature Specification Number
+ * 0b000000000000x1xx..Core Control and Status Registers are implemented in both MUA and MUB.
+ * 0b000000000000xx1x..RAIP/RAIE register bits are implemented.
+ * 0b000000000000xxx0..Standard features implemented
+ */
+#define MU_VER_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK)
+#define MU_VER_MINOR_MASK (0xFF0000U)
+#define MU_VER_MINOR_SHIFT (16U)
+/*! MINOR - Minor Version Number
+ */
+#define MU_VER_MINOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK)
+#define MU_VER_MAJOR_MASK (0xFF000000U)
+#define MU_VER_MAJOR_SHIFT (24U)
+/*! MAJOR - Major Version Number
+ */
+#define MU_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK)
+/*! @} */
+
+/*! @name PAR - Parameter Register */
+/*! @{ */
+#define MU_PAR_PARAMETER_MASK (0xFFFFFFFFU)
+#define MU_PAR_PARAMETER_SHIFT (0U)
+/*! PARAMETER - This bitfield contains the parameter settings of MUA.
+ */
+#define MU_PAR_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_PARAMETER_SHIFT)) & MU_PAR_PARAMETER_MASK)
+/*! @} */
+
+/*! @name TR - Transmit Register */
+/*! @{ */
+#define MU_TR_DATA_MASK (0xFFFFFFFFU)
+#define MU_TR_DATA_SHIFT (0U)
+/*! DATA - DATA
+ */
+#define MU_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK)
+/*! @} */
+
+/* The count of MU_TR */
+#define MU_TR_COUNT (4U)
+
+/*! @name RR - Receive Register */
+/*! @{ */
+#define MU_RR_DATA_MASK (0xFFFFFFFFU)
+#define MU_RR_DATA_SHIFT (0U)
+/*! DATA - DATA
+ */
+#define MU_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK)
+/*! @} */
+
+/* The count of MU_RR */
+#define MU_RR_COUNT (4U)
+
+/*! @name SR - Status Register */
+/*! @{ */
+#define MU_SR_Fn_MASK (0x7U)
+#define MU_SR_Fn_SHIFT (0U)
+/*! Fn - Fn
+ * 0b000..Fn bit in the MUB CR register is written 0 (default).
+ * 0b001..Fn bit in the MUB CR register is written 1.
+ */
+#define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
+#define MU_SR_EP_MASK (0x10U)
+#define MU_SR_EP_SHIFT (4U)
+/*! EP - EP
+ * 0b0..The MUA side event is not pending (default).
+ * 0b1..The MUA side event is pending.
+ */
+#define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
+#define MU_SR_PM_MASK (0x60U)
+#define MU_SR_PM_SHIFT (5U)
+/*! PM - PM
+ * 0b00..The MUB processor is in Run Mode.
+ * 0b01..The MUB processor is in WAIT Mode.
+ * 0b10..The MUB processor is in STOP/VLPS Mode.
+ * 0b11..The MUB processor is in LLS/VLLS Mode.
+ */
+#define MU_SR_PM(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_PM_SHIFT)) & MU_SR_PM_MASK)
+#define MU_SR_RS_MASK (0x80U)
+#define MU_SR_RS_SHIFT (7U)
+/*! RS - RS
+ * 0b0..The MUB side of the MU is not in reset.
+ * 0b1..The MUB side of the MU is in reset.
+ */
+#define MU_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RS_SHIFT)) & MU_SR_RS_MASK)
+#define MU_SR_FUP_MASK (0x100U)
+#define MU_SR_FUP_SHIFT (8U)
+/*! FUP - FUP
+ * 0b0..No flags updated, initiated by the MUA, in progress (default)
+ * 0b1..MUA initiated flags update, processing
+ */
+#define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
+#define MU_SR_RDIP_MASK (0x200U)
+#define MU_SR_RDIP_SHIFT (9U)
+/*! RDIP - RDIP
+ * 0b0..Processor B-side did not exit reset
+ * 0b1..Processor B-side exited from reset
+ */
+#define MU_SR_RDIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RDIP_SHIFT)) & MU_SR_RDIP_MASK)
+#define MU_SR_RAIP_MASK (0x400U)
+#define MU_SR_RAIP_SHIFT (10U)
+/*! RAIP - RAIP
+ * 0b0..Processor B-side did not enter reset
+ * 0b1..Processor B-side entered reset
+ */
+#define MU_SR_RAIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RAIP_SHIFT)) & MU_SR_RAIP_MASK)
+#define MU_SR_TEn_MASK (0xF00000U)
+#define MU_SR_TEn_SHIFT (20U)
+/*! TEn - TEn
+ * 0b0000..MUA TRn register is not empty.
+ * 0b0001..MUA TRn register is empty (default).
+ */
+#define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
+#define MU_SR_RFn_MASK (0xF000000U)
+#define MU_SR_RFn_SHIFT (24U)
+/*! RFn - RFn
+ * 0b0000..MUA RRn register is not full (default).
+ * 0b0001..MUA RRn register has received data from MUB TRn register and is ready to be read by the MUA.
+ */
+#define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
+#define MU_SR_GIPn_MASK (0xF0000000U)
+#define MU_SR_GIPn_SHIFT (28U)
+/*! GIPn - GIPn
+ * 0b0000..MUA general purpose interrupt n is not pending. (default)
+ * 0b0001..MUA general purpose interrupt n is pending.
+ */
+#define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)
+/*! @} */
+
+/*! @name CR - Control Register */
+/*! @{ */
+#define MU_CR_Fn_MASK (0x7U)
+#define MU_CR_Fn_SHIFT (0U)
+/*! Fn - Fn
+ * 0b000..Clears the Fn bit in the SR register.
+ * 0b001..Sets the Fn bit in the SR register.
+ */
+#define MU_CR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK)
+#define MU_CR_MUR_MASK (0x20U)
+#define MU_CR_MUR_SHIFT (5U)
+/*! MUR - MUR
+ * 0b0..N/A. Self clearing bit (default).
+ * 0b1..Asserts the MU reset.
+ */
+#define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
+#define MU_CR_RDIE_MASK (0x40U)
+#define MU_CR_RDIE_SHIFT (6U)
+/*! RDIE - RDIE
+ * 0b0..Disables Processor A General Purpose Interrupt 3 request due to Processor B reset de-assertion.
+ * 0b1..Enables Processor A General Purpose Interrupt 3 request due to Processor B reset de-assertion.
+ */
+#define MU_CR_RDIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RDIE_SHIFT)) & MU_CR_RDIE_MASK)
+#define MU_CR_RAIE_MASK (0x1000U)
+#define MU_CR_RAIE_SHIFT (12U)
+/*! RAIE - RAIE
+ * 0b0..Disables Processor A General Purpose Interrupt 3 request due to Processor B reset assertion.
+ * 0b1..Enables Processor A General Purpose Interrupt 3 request due to Processor B reset assertion.
+ */
+#define MU_CR_RAIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RAIE_SHIFT)) & MU_CR_RAIE_MASK)
+#define MU_CR_GIRn_MASK (0xF0000U)
+#define MU_CR_GIRn_SHIFT (16U)
+/*! GIRn - GIRn
+ * 0b0000..MUA General Interrupt n is not requested to the MUB (default).
+ * 0b0001..MUA General Interrupt n is requested to the MUB.
+ */
+#define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
+#define MU_CR_TIEn_MASK (0xF00000U)
+#define MU_CR_TIEn_SHIFT (20U)
+/*! TIEn - TIEn
+ * 0b0000..Disables MUA Transmit Interrupt n. (default)
+ * 0b0001..Enables MUA Transmit Interrupt n.
+ */
+#define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
+#define MU_CR_RIEn_MASK (0xF000000U)
+#define MU_CR_RIEn_SHIFT (24U)
+/*! RIEn - RIEn
+ * 0b0000..Disables MUA Receive Interrupt n. (default)
+ * 0b0001..Enables MUA Receive Interrupt n.
+ */
+#define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
+#define MU_CR_GIEn_MASK (0xF0000000U)
+#define MU_CR_GIEn_SHIFT (28U)
+/*! GIEn - GIEn
+ * 0b0000..Disables MUA General Interrupt n. (default)
+ * 0b0001..Enables MUA General Interrupt n.
+ */
+#define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MU_Register_Masks */
+
+
+/* MU - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral MUA base address */
+ #define MUA_BASE (0x50110000u)
+ /** Peripheral MUA base address */
+ #define MUA_BASE_NS (0x40110000u)
+ /** Peripheral MUA base pointer */
+ #define MUA ((MU_Type *)MUA_BASE)
+ /** Peripheral MUA base pointer */
+ #define MUA_NS ((MU_Type *)MUA_BASE_NS)
+ /** Array initializer of MU peripheral base addresses */
+ #define MU_BASE_ADDRS { MUA_BASE }
+ /** Array initializer of MU peripheral base pointers */
+ #define MU_BASE_PTRS { MUA }
+ /** Array initializer of MU peripheral base addresses */
+ #define MU_BASE_ADDRS_NS { MUA_BASE_NS }
+ /** Array initializer of MU peripheral base pointers */
+ #define MU_BASE_PTRS_NS { MUA_NS }
+#else
+ /** Peripheral MUA base address */
+ #define MUA_BASE (0x40110000u)
+ /** Peripheral MUA base pointer */
+ #define MUA ((MU_Type *)MUA_BASE)
+ /** Array initializer of MU peripheral base addresses */
+ #define MU_BASE_ADDRS { MUA_BASE }
+ /** Array initializer of MU peripheral base pointers */
+ #define MU_BASE_PTRS { MUA }
+#endif
+/** Interrupt vectors for the MU peripheral type */
+#define MU_IRQS { MU_A_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OCOTP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
+ * @{
+ */
+
+/** OCOTP - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t OTP_SHADOW[496]; /**< OTP shadow register N, array offset: 0x0, array step: 0x4 */
+ uint8_t RESERVED_0[64];
+ __IO uint32_t OTP_CTRL; /**< Control/address register, offset: 0x800 */
+ __IO uint32_t OTP_PDN; /**< Power-down register, offset: 0x804 */
+ __IO uint32_t OTP_WRITE_DATA; /**< OTP programming data register, offset: 0x808 */
+ __IO uint32_t OTP_READ_CTRL; /**< OTP read start register, offset: 0x80C */
+ __I uint32_t OTP_READ_DATA; /**< OTP read data register, offset: 0x810 */
+ __IO uint32_t OTP_CLK_DIV; /**< OTP clock divider register, offset: 0x814 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t OTP_CRC_ADDR; /**< CRC address range register, offset: 0x81C */
+ __I uint32_t OTP_CRC_VALUE; /**< CRC result register, offset: 0x820 */
+ __IO uint32_t OTP_STATUS; /**< Status register, offset: 0x824 */
+ uint8_t RESERVED_2[4];
+ __I uint32_t OTP_VERSION; /**< VERSION ID register, offset: 0x82C */
+} OCOTP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OCOTP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OCOTP_Register_Masks OCOTP Register Masks
+ * @{
+ */
+
+/*! @name OTP_SHADOW - OTP shadow register N */
+/*! @{ */
+#define OCOTP_OTP_SHADOW_shadow_MASK (0xFFFFFFFFU)
+#define OCOTP_OTP_SHADOW_shadow_SHIFT (0U)
+/*! shadow - OTP shadow register
+ */
+#define OCOTP_OTP_SHADOW_shadow(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_SHADOW_shadow_SHIFT)) & OCOTP_OTP_SHADOW_shadow_MASK)
+/*! @} */
+
+/* The count of OCOTP_OTP_SHADOW */
+#define OCOTP_OTP_SHADOW_COUNT (496U)
+
+/*! @name OTP_CTRL - Control/address register */
+/*! @{ */
+#define OCOTP_OTP_CTRL_ADDR_MASK (0x1FFU)
+#define OCOTP_OTP_CTRL_ADDR_SHIFT (0U)
+/*! ADDR - OTP word address for read/programming
+ */
+#define OCOTP_OTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_ADDR_SHIFT)) & OCOTP_OTP_CTRL_ADDR_MASK)
+#define OCOTP_OTP_CTRL_RELOAD_SHADOWS_MASK (0x800U)
+#define OCOTP_OTP_CTRL_RELOAD_SHADOWS_SHIFT (11U)
+/*! RELOAD_SHADOWS - Set to force re-loading the shadow registers (HW/SW capability and LOCK). This
+ * operation will automatically set OTP_STATUS.BUSY. Once the shadow registers have been
+ * re-loaded, OTP_STATUS.BUSY and RELOAD_SHADOWS are automatically cleared by the controller
+ */
+#define OCOTP_OTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_OTP_CTRL_RELOAD_SHADOWS_MASK)
+#define OCOTP_OTP_CTRL_CRC_TEST_MASK (0x1000U)
+#define OCOTP_OTP_CTRL_CRC_TEST_SHIFT (12U)
+/*! CRC_TEST - Set to start CRC calculation. This operation will automatically set OTP_STATUS.BUSY.
+ * Once CRC is calculation done, OTP_STATUS.BUSY and CRC_TEST are automatically cleared by the
+ * controller
+ */
+#define OCOTP_OTP_CTRL_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_CRC_TEST_SHIFT)) & OCOTP_OTP_CTRL_CRC_TEST_MASK)
+#define OCOTP_OTP_CTRL_WORDLOCK_MASK (0x8000U)
+#define OCOTP_OTP_CTRL_WORDLOCK_SHIFT (15U)
+/*! WORDLOCK - Set to write-lock the fuse word when it's being programming. When programming with
+ * ECC mode, it recommends to set this bit.
+ */
+#define OCOTP_OTP_CTRL_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_WORDLOCK_SHIFT)) & OCOTP_OTP_CTRL_WORDLOCK_MASK)
+#define OCOTP_OTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)
+#define OCOTP_OTP_CTRL_WR_UNLOCK_SHIFT (16U)
+/*! WR_UNLOCK - Write 0x3E77 to enable OTP write accesses. NOTE: The write operation must be
+ * unlocked for each word by writing 0x3E77 to WR_UNLOCK field. Then writing to OTP_WRITE_DATA register
+ * will automatically start the programming procedure.
+ */
+#define OCOTP_OTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_OTP_CTRL_WR_UNLOCK_MASK)
+/*! @} */
+
+/*! @name OTP_PDN - Power-down register */
+/*! @{ */
+#define OCOTP_OTP_PDN_PDN_MASK (0x1U)
+#define OCOTP_OTP_PDN_PDN_SHIFT (0U)
+/*! PDN - This bit indicates the PDN value of OTP memory. Writing 1 to the bit to clear PDN. Writing
+ * 0 has no effect. Note: Software need to write 1 to this bit to shut off power of OTP memory
+ * after system power up. At the beginning of every fuse operation, the controller will
+ * automatically turn-on power to the OPT memory. After every fuse operation, software also need to write 1
+ * to this bit to shut off power to the OTP memory to reduce power consumption.
+ */
+#define OCOTP_OTP_PDN_PDN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_PDN_PDN_SHIFT)) & OCOTP_OTP_PDN_PDN_MASK)
+/*! @} */
+
+/*! @name OTP_WRITE_DATA - OTP programming data register */
+/*! @{ */
+#define OCOTP_OTP_WRITE_DATA_WRITE_DATA_MASK (0xFFFFFFFFU)
+#define OCOTP_OTP_WRITE_DATA_WRITE_DATA_SHIFT (0U)
+/*! WRITE_DATA - Fuse word programming data. After the write operation is unlocked in OTP_CTRL
+ * register, writing data to this register automatically start the programming procedure.
+ */
+#define OCOTP_OTP_WRITE_DATA_WRITE_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_WRITE_DATA_WRITE_DATA_SHIFT)) & OCOTP_OTP_WRITE_DATA_WRITE_DATA_MASK)
+/*! @} */
+
+/*! @name OTP_READ_CTRL - OTP read start register */
+/*! @{ */
+#define OCOTP_OTP_READ_CTRL_READ_MASK (0x1U)
+#define OCOTP_OTP_READ_CTRL_READ_SHIFT (0U)
+#define OCOTP_OTP_READ_CTRL_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_READ_CTRL_READ_SHIFT)) & OCOTP_OTP_READ_CTRL_READ_MASK)
+/*! @} */
+
+/*! @name OTP_READ_DATA - OTP read data register */
+/*! @{ */
+#define OCOTP_OTP_READ_DATA_READ_DATA_MASK (0xFFFFFFFFU)
+#define OCOTP_OTP_READ_DATA_READ_DATA_SHIFT (0U)
+/*! READ_DATA - Fuse word read data from read operation
+ */
+#define OCOTP_OTP_READ_DATA_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_READ_DATA_READ_DATA_SHIFT)) & OCOTP_OTP_READ_DATA_READ_DATA_MASK)
+/*! @} */
+
+/*! @name OTP_CLK_DIV - OTP clock divider register */
+/*! @{ */
+#define OCOTP_OTP_CLK_DIV_DIV_MASK (0xFU)
+#define OCOTP_OTP_CLK_DIV_DIV_SHIFT (0U)
+/*! DIV - Clock divider value by -1 encoding. It's used to generate the clock to OTP memory
+ * (otp_clk) with apb_clk. The maximum otp_clk frequency is 120Mhz. 0: Divide by 1
+ * 0b0000..Divide by 1
+ * 0b0001..Divide by 2
+ * 0b0010..Divide by 3
+ * 0b0011..Divide by 4
+ * 0b0100..Divide by 5
+ * 0b0101..Divide by 6
+ * 0b0110..Divide by 7
+ * 0b0111..Divide by 8
+ * 0b1000..Divide by 9
+ * 0b1001..Divide by 10
+ * 0b1010..Divide by 11
+ * 0b1011..Divide by 12
+ * 0b1100..Divide by 13
+ * 0b1101..Divide by 14
+ * 0b1110..Divide by 15
+ * 0b1111..Divide by 16
+ */
+#define OCOTP_OTP_CLK_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CLK_DIV_DIV_SHIFT)) & OCOTP_OTP_CLK_DIV_DIV_MASK)
+#define OCOTP_OTP_CLK_DIV_RESET_MASK (0x20000000U)
+#define OCOTP_OTP_CLK_DIV_RESET_SHIFT (29U)
+/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
+ * away rather than completing the previous count.
+ */
+#define OCOTP_OTP_CLK_DIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CLK_DIV_RESET_SHIFT)) & OCOTP_OTP_CLK_DIV_RESET_MASK)
+#define OCOTP_OTP_CLK_DIV_HALT_MASK (0x40000000U)
+#define OCOTP_OTP_CLK_DIV_HALT_SHIFT (30U)
+/*! HALT - Halts the divider counter. The intent is to allow the divider's clock source to be
+ * changed without the risk of a glitch at the output.
+ */
+#define OCOTP_OTP_CLK_DIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CLK_DIV_HALT_SHIFT)) & OCOTP_OTP_CLK_DIV_HALT_MASK)
+#define OCOTP_OTP_CLK_DIV_REQFLAG_MASK (0x80000000U)
+#define OCOTP_OTP_CLK_DIV_REQFLAG_SHIFT (31U)
+/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the change is complete.
+ */
+#define OCOTP_OTP_CLK_DIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CLK_DIV_REQFLAG_SHIFT)) & OCOTP_OTP_CLK_DIV_REQFLAG_MASK)
+/*! @} */
+
+/*! @name OTP_CRC_ADDR - CRC address range register */
+/*! @{ */
+#define OCOTP_OTP_CRC_ADDR_CRC_START_ADDR_MASK (0x1FFU)
+#define OCOTP_OTP_CRC_ADDR_CRC_START_ADDR_SHIFT (0U)
+/*! CRC_START_ADDR - CRC starting fuse word address
+ */
+#define OCOTP_OTP_CRC_ADDR_CRC_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_ADDR_CRC_START_ADDR_SHIFT)) & OCOTP_OTP_CRC_ADDR_CRC_START_ADDR_MASK)
+#define OCOTP_OTP_CRC_ADDR_CRC_END_ADDR_MASK (0x1FF000U)
+#define OCOTP_OTP_CRC_ADDR_CRC_END_ADDR_SHIFT (12U)
+/*! CRC_END_ADDR - CRC ending fuse word address
+ */
+#define OCOTP_OTP_CRC_ADDR_CRC_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_ADDR_CRC_END_ADDR_SHIFT)) & OCOTP_OTP_CRC_ADDR_CRC_END_ADDR_MASK)
+#define OCOTP_OTP_CRC_ADDR_CRC_REF_ADDR_MASK (0x7000000U)
+#define OCOTP_OTP_CRC_ADDR_CRC_REF_ADDR_SHIFT (24U)
+/*! CRC_REF_ADDR - Specify which of the 8 CRC reference value to use for CRC calculation. When the
+ * CRC result for the fuse data from CRC_START_ADDR to CRC_END_ADDR and this CRC reference value
+ * is 0, the CRC check passes.
+ */
+#define OCOTP_OTP_CRC_ADDR_CRC_REF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_ADDR_CRC_REF_ADDR_SHIFT)) & OCOTP_OTP_CRC_ADDR_CRC_REF_ADDR_MASK)
+/*! @} */
+
+/*! @name OTP_CRC_VALUE - CRC result register */
+/*! @{ */
+#define OCOTP_OTP_CRC_VALUE_CRC_VALUE_MASK (0xFFFFFFFFU)
+#define OCOTP_OTP_CRC_VALUE_CRC_VALUE_SHIFT (0U)
+/*! CRC_VALUE - The CRC result value. When it is locked, reading from it returns value 0xBADA_BADA
+ */
+#define OCOTP_OTP_CRC_VALUE_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_VALUE_CRC_VALUE_SHIFT)) & OCOTP_OTP_CRC_VALUE_CRC_VALUE_MASK)
+/*! @} */
+
+/*! @name OTP_STATUS - Status register */
+/*! @{ */
+#define OCOTP_OTP_STATUS_SEC_MASK (0x200U)
+#define OCOTP_OTP_STATUS_SEC_SHIFT (9U)
+/*! SEC - OTP Single Error Corrected status of ECC during read operation. Write 1 to clear.
+ */
+#define OCOTP_OTP_STATUS_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_SEC_SHIFT)) & OCOTP_OTP_STATUS_SEC_MASK)
+#define OCOTP_OTP_STATUS_DED_MASK (0x400U)
+#define OCOTP_OTP_STATUS_DED_SHIFT (10U)
+/*! DED - OTP Double Error Detection status of ECC during read operation. Write 1 to clear.
+ */
+#define OCOTP_OTP_STATUS_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_DED_SHIFT)) & OCOTP_OTP_STATUS_DED_MASK)
+#define OCOTP_OTP_STATUS_LOCKED_MASK (0x800U)
+#define OCOTP_OTP_STATUS_LOCKED_SHIFT (11U)
+/*! LOCKED - OTP LOCKED status during read/write operation. Write 1 to clear.
+ */
+#define OCOTP_OTP_STATUS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_LOCKED_SHIFT)) & OCOTP_OTP_STATUS_LOCKED_MASK)
+#define OCOTP_OTP_STATUS_PROGFAIL_MASK (0x1000U)
+#define OCOTP_OTP_STATUS_PROGFAIL_SHIFT (12U)
+/*! PROGFAIL - OTP PROGFAIL status. Write 1 to clear.
+ */
+#define OCOTP_OTP_STATUS_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_PROGFAIL_SHIFT)) & OCOTP_OTP_STATUS_PROGFAIL_MASK)
+#define OCOTP_OTP_STATUS_ACK_MASK (0x2000U)
+#define OCOTP_OTP_STATUS_ACK_SHIFT (13U)
+/*! ACK - OTP ACK value
+ */
+#define OCOTP_OTP_STATUS_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_ACK_SHIFT)) & OCOTP_OTP_STATUS_ACK_MASK)
+#define OCOTP_OTP_STATUS_PWOK_MASK (0x4000U)
+#define OCOTP_OTP_STATUS_PWOK_SHIFT (14U)
+/*! PWOK - OTP Power OK status. Indicate that power VDD are in the operating range.
+ */
+#define OCOTP_OTP_STATUS_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_PWOK_SHIFT)) & OCOTP_OTP_STATUS_PWOK_MASK)
+#define OCOTP_OTP_STATUS_SEC_RELOAD_MASK (0x100000U)
+#define OCOTP_OTP_STATUS_SEC_RELOAD_SHIFT (20U)
+/*! SEC_RELOAD - OTP Single Error Corrected status of ECC during reload process. Write 1 to clear.
+ */
+#define OCOTP_OTP_STATUS_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_SEC_RELOAD_SHIFT)) & OCOTP_OTP_STATUS_SEC_RELOAD_MASK)
+#define OCOTP_OTP_STATUS_DED_RELOAD_MASK (0x200000U)
+#define OCOTP_OTP_STATUS_DED_RELOAD_SHIFT (21U)
+/*! DED_RELOAD - OTP Double Error Detect status of ECC during reload process. Write 1 to clear.
+ */
+#define OCOTP_OTP_STATUS_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_DED_RELOAD_SHIFT)) & OCOTP_OTP_STATUS_DED_RELOAD_MASK)
+#define OCOTP_OTP_STATUS_BUSY_MASK (0x400000U)
+#define OCOTP_OTP_STATUS_BUSY_SHIFT (22U)
+/*! BUSY - OTP controller status bit. When active, no new write or read access to OTP (including
+ * RELOAD_SHADOWS) can be performed. Cleared by the controller when the access completes. After
+ * reset (or after setting RELOAD_SHADOWS), this bit is set by the controller and cleared after all
+ * the shadow registers are successfully loaded.
+ */
+#define OCOTP_OTP_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_BUSY_SHIFT)) & OCOTP_OTP_STATUS_BUSY_MASK)
+#define OCOTP_OTP_STATUS_ERROR_MASK (0x800000U)
+#define OCOTP_OTP_STATUS_ERROR_SHIFT (23U)
+/*! ERROR - Set by the controller when a read/write access to a locked region (OTP or shadow
+ * register) is requested. Writing 1 to clear it before any further access can be performed. This bit
+ * can only be set by the controller.
+ */
+#define OCOTP_OTP_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_ERROR_SHIFT)) & OCOTP_OTP_STATUS_ERROR_MASK)
+#define OCOTP_OTP_STATUS_CRC_FAIL_MASK (0x1000000U)
+#define OCOTP_OTP_STATUS_CRC_FAIL_SHIFT (24U)
+/*! CRC_FAIL - CRC failed when set by hardware for CRC operation. Write 1 to clear.
+ */
+#define OCOTP_OTP_STATUS_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_CRC_FAIL_SHIFT)) & OCOTP_OTP_STATUS_CRC_FAIL_MASK)
+#define OCOTP_OTP_STATUS_FUSE_LATCHED_MASK (0x2000000U)
+#define OCOTP_OTP_STATUS_FUSE_LATCHED_SHIFT (25U)
+/*! FUSE_LATCHED - Indicate all shadows registers have been loaded with their corresponding fuse
+ * words when set by the controller after reset.
+ */
+#define OCOTP_OTP_STATUS_FUSE_LATCHED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_FUSE_LATCHED_SHIFT)) & OCOTP_OTP_STATUS_FUSE_LATCHED_MASK)
+/*! @} */
+
+/*! @name OTP_VERSION - VERSION ID register */
+/*! @{ */
+#define OCOTP_OTP_VERSION_STEP_VER_MASK (0xFFFFU)
+#define OCOTP_OTP_VERSION_STEP_VER_SHIFT (0U)
+/*! STEP_VER - OTP controller step version
+ */
+#define OCOTP_OTP_VERSION_STEP_VER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_VERSION_STEP_VER_SHIFT)) & OCOTP_OTP_VERSION_STEP_VER_MASK)
+#define OCOTP_OTP_VERSION_MINOR_VER_MASK (0xFF0000U)
+#define OCOTP_OTP_VERSION_MINOR_VER_SHIFT (16U)
+/*! MINOR_VER - OTP controller minor version
+ */
+#define OCOTP_OTP_VERSION_MINOR_VER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_VERSION_MINOR_VER_SHIFT)) & OCOTP_OTP_VERSION_MINOR_VER_MASK)
+#define OCOTP_OTP_VERSION_MAJOR_VER_MASK (0xFF000000U)
+#define OCOTP_OTP_VERSION_MAJOR_VER_SHIFT (24U)
+/*! MAJOR_VER - OTP controller major version
+ */
+#define OCOTP_OTP_VERSION_MAJOR_VER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_VERSION_MAJOR_VER_SHIFT)) & OCOTP_OTP_VERSION_MAJOR_VER_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group OCOTP_Register_Masks */
+
+
+/* OCOTP - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral OCOTP0 base address */
+ #define OCOTP0_BASE (0x50130000u)
+ /** Peripheral OCOTP0 base address */
+ #define OCOTP0_BASE_NS (0x40130000u)
+ /** Peripheral OCOTP0 base pointer */
+ #define OCOTP0 ((OCOTP_Type *)OCOTP0_BASE)
+ /** Peripheral OCOTP0 base pointer */
+ #define OCOTP0_NS ((OCOTP_Type *)OCOTP0_BASE_NS)
+ /** Array initializer of OCOTP peripheral base addresses */
+ #define OCOTP_BASE_ADDRS { OCOTP0_BASE }
+ /** Array initializer of OCOTP peripheral base pointers */
+ #define OCOTP_BASE_PTRS { OCOTP0 }
+ /** Array initializer of OCOTP peripheral base addresses */
+ #define OCOTP_BASE_ADDRS_NS { OCOTP0_BASE_NS }
+ /** Array initializer of OCOTP peripheral base pointers */
+ #define OCOTP_BASE_PTRS_NS { OCOTP0_NS }
+#else
+ /** Peripheral OCOTP0 base address */
+ #define OCOTP0_BASE (0x40130000u)
+ /** Peripheral OCOTP0 base pointer */
+ #define OCOTP0 ((OCOTP_Type *)OCOTP0_BASE)
+ /** Array initializer of OCOTP peripheral base addresses */
+ #define OCOTP_BASE_ADDRS { OCOTP0_BASE }
+ /** Array initializer of OCOTP peripheral base pointers */
+ #define OCOTP_BASE_PTRS { OCOTP0 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group OCOTP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSTIMER Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer
+ * @{
+ */
+
+/** OSTIMER - Register Layout Typedef */
+typedef struct {
+ __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */
+ __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */
+ __I uint32_t CAPTURE_L; /**< Local Capture Low Register for CPU, offset: 0x8 */
+ __I uint32_t CAPTURE_H; /**< Local Capture High Register for CPU, offset: 0xC */
+ __IO uint32_t MATCH_L; /**< Local Match Low Register for CPU, offset: 0x10 */
+ __IO uint32_t MATCH_H; /**< Local Match High Register for CPU, offset: 0x14 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t OSEVENT_CTRL; /**< OS Event Timer Control Register for CPU, offset: 0x1C */
+} OSTIMER_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSTIMER Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks
+ * @{
+ */
+
+/*! @name EVTIMERL - EVTIMER Low Register */
+/*! @{ */
+#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)
+#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U)
+/*! EVTIMER_COUNT_VALUE - EVTimer Count value
+ */
+#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK)
+/*! @} */
+
+/*! @name EVTIMERH - EVTIMER High Register */
+/*! @{ */
+#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)
+#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U)
+/*! EVTIMER_COUNT_VALUE - EVTimer Count value
+ */
+#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK)
+/*! @} */
+
+/*! @name CAPTURE_L - Local Capture Low Register for CPU */
+/*! @{ */
+#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU)
+#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U)
+/*! CAPTURE_VALUE - EVTimer Capture value
+ */
+#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK)
+/*! @} */
+
+/*! @name CAPTURE_H - Local Capture High Register for CPU */
+/*! @{ */
+#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0xFFFFFFFFU)
+#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U)
+/*! CAPTURE_VALUE - EVTimer Capture value
+ */
+#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK)
+/*! @} */
+
+/*! @name MATCH_L - Local Match Low Register for CPU */
+/*! @{ */
+#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU)
+#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U)
+/*! MATCH_VALUE - EVTimer Match value
+ */
+#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK)
+/*! @} */
+
+/*! @name MATCH_H - Local Match High Register for CPU */
+/*! @{ */
+#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0xFFFFFFFFU)
+#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U)
+/*! MATCH_VALUE - EVTimer Match value
+ */
+#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK)
+/*! @} */
+
+/*! @name OSEVENT_CTRL - OS Event Timer Control Register for CPU */
+/*! @{ */
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U)
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U)
+/*! OSTIMER_INTRFLAG - Interrupt Flag
+ */
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK)
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U)
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U)
+/*! OSTIMER_INTENA - Interrupt/Wake-up Request
+ * 0b0..Interrupt/wake-up requests due to the OSTIMER_INTR flag are blocked.
+ * 0b1..An interrupt/wake-up request to the domain processor will be asserted when the OSTIMER_INTR flag is set.
+ */
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK)
+#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U)
+#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U)
+/*! MATCH_WR_RDY - EVTimer Match Write Ready
+ */
+#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group OSTIMER_Register_Masks */
+
+
+/* OSTIMER - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral OSTIMER0 base address */
+ #define OSTIMER0_BASE (0x50113000u)
+ /** Peripheral OSTIMER0 base address */
+ #define OSTIMER0_BASE_NS (0x40113000u)
+ /** Peripheral OSTIMER0 base pointer */
+ #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE)
+ /** Peripheral OSTIMER0 base pointer */
+ #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS)
+ /** Array initializer of OSTIMER peripheral base addresses */
+ #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE }
+ /** Array initializer of OSTIMER peripheral base pointers */
+ #define OSTIMER_BASE_PTRS { OSTIMER0 }
+ /** Array initializer of OSTIMER peripheral base addresses */
+ #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS }
+ /** Array initializer of OSTIMER peripheral base pointers */
+ #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS }
+#else
+ /** Peripheral OSTIMER0 base address */
+ #define OSTIMER0_BASE (0x40113000u)
+ /** Peripheral OSTIMER0 base pointer */
+ #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE)
+ /** Array initializer of OSTIMER peripheral base addresses */
+ #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE }
+ /** Array initializer of OSTIMER peripheral base pointers */
+ #define OSTIMER_BASE_PTRS { OSTIMER0 }
+#endif
+/** Interrupt vectors for the OSTIMER peripheral type */
+#define OSTIMER_IRQS { OS_EVENT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group OSTIMER_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OTFAD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OTFAD_Peripheral_Access_Layer OTFAD Peripheral Access Layer
+ * @{
+ */
+
+/** OTFAD - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[3072];
+ __IO uint32_t CR; /**< Control Register, offset: 0xC00 */
+ __I uint32_t SR; /**< Status Register, offset: 0xC04 */
+ uint8_t RESERVED_1[248];
+ struct { /* offset: 0xD00, array step: 0x40 */
+ __IO uint32_t KEY[4]; /**< AES Key Word, array offset: 0xD00, array step: index*0x40, index2*0x4 */
+ __IO uint32_t CTR[2]; /**< AES Counter Word, array offset: 0xD10, array step: index*0x40, index2*0x4 */
+ __IO uint32_t RGD_W0; /**< AES Region Descriptor Word0, array offset: 0xD18, array step: 0x40 */
+ __IO uint32_t RGD_W1; /**< AES Region Descriptor Word1, array offset: 0xD1C, array step: 0x40 */
+ uint8_t RESERVED_0[32];
+ } CTX[4];
+} OTFAD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OTFAD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OTFAD_Register_Masks OTFAD Register Masks
+ * @{
+ */
+
+/*! @name CR - Control Register */
+/*! @{ */
+#define OTFAD_CR_FLDM_MASK (0x8U)
+#define OTFAD_CR_FLDM_SHIFT (3U)
+/*! FLDM - Force Logically Disabled Mode
+ * 0b0..No effect on the operating mode.
+ * 0b1..Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode.
+ */
+#define OTFAD_CR_FLDM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)
+#define OTFAD_CR_RRAE_MASK (0x80U)
+#define OTFAD_CR_RRAE_SHIFT (7U)
+/*! RRAE - Restricted Register Access Enable
+ * 0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
+ * 0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
+ */
+#define OTFAD_CR_RRAE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)
+#define OTFAD_CR_GE_MASK (0x80000000U)
+#define OTFAD_CR_GE_SHIFT (31U)
+/*! GE - Global OTFAD Enable
+ * 0b0..OTFAD has decryption disabled. All data fetched by the FlexSPI bypasses OTFAD processing.
+ * 0b1..OTFAD has decryption enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.
+ */
+#define OTFAD_CR_GE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)
+/*! @} */
+
+/*! @name SR - Status Register */
+/*! @{ */
+#define OTFAD_SR_MDPCP_MASK (0x2U)
+#define OTFAD_SR_MDPCP_SHIFT (1U)
+/*! MDPCP - MDPC Present
+ */
+#define OTFAD_SR_MDPCP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK)
+#define OTFAD_SR_MODE_MASK (0xCU)
+#define OTFAD_SR_MODE_SHIFT (2U)
+/*! MODE - Operating Mode
+ * 0b00..Operating in Normal mode (NRM)
+ * 0b01..Unused (reserved)
+ * 0b10..Unused (reserved)
+ * 0b11..Operating in Logically Disabled Mode (LDM)
+ */
+#define OTFAD_SR_MODE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK)
+#define OTFAD_SR_NCTX_MASK (0xF0U)
+#define OTFAD_SR_NCTX_SHIFT (4U)
+/*! NCTX - Number of Contexts
+ */
+#define OTFAD_SR_NCTX(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK)
+#define OTFAD_SR_HRL_MASK (0xF000000U)
+#define OTFAD_SR_HRL_SHIFT (24U)
+/*! HRL - Hardware Revision Level
+ */
+#define OTFAD_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK)
+#define OTFAD_SR_RRAM_MASK (0x10000000U)
+#define OTFAD_SR_RRAM_SHIFT (28U)
+/*! RRAM - Restricted Register Access Mode
+ * 0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
+ * 0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
+ */
+#define OTFAD_SR_RRAM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
+#define OTFAD_SR_GEM_MASK (0x20000000U)
+#define OTFAD_SR_GEM_SHIFT (29U)
+/*! GEM - Global Enable Mode
+ * 0b0..OTFAD is disabled. All data fetched by the FlexSPI bypasses OTFAD processing.
+ * 0b1..OTFAD is enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.
+ */
+#define OTFAD_SR_GEM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK)
+/*! @} */
+
+/*! @name KEY - AES Key Word */
+/*! @{ */
+#define OTFAD_KEY_KEY_MASK (0xFFFFFFFFU)
+#define OTFAD_KEY_KEY_SHIFT (0U)
+/*! KEY - AES Key
+ */
+#define OTFAD_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_KEY_KEY_SHIFT)) & OTFAD_KEY_KEY_MASK)
+/*! @} */
+
+/* The count of OTFAD_KEY */
+#define OTFAD_KEY_COUNT (4U)
+
+/* The count of OTFAD_KEY */
+#define OTFAD_KEY_COUNT2 (4U)
+
+/*! @name CTR - AES Counter Word */
+/*! @{ */
+#define OTFAD_CTR_CTR_MASK (0xFFFFFFFFU)
+#define OTFAD_CTR_CTR_SHIFT (0U)
+/*! CTR - AES Counter
+ */
+#define OTFAD_CTR_CTR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTR_CTR_SHIFT)) & OTFAD_CTR_CTR_MASK)
+/*! @} */
+
+/* The count of OTFAD_CTR */
+#define OTFAD_CTR_COUNT (4U)
+
+/* The count of OTFAD_CTR */
+#define OTFAD_CTR_COUNT2 (2U)
+
+/*! @name RGD_W0 - AES Region Descriptor Word0 */
+/*! @{ */
+#define OTFAD_RGD_W0_SRTADDR_MASK (0xFFFFFC00U)
+#define OTFAD_RGD_W0_SRTADDR_SHIFT (10U)
+/*! SRTADDR - Start Address
+ */
+#define OTFAD_RGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W0_SRTADDR_SHIFT)) & OTFAD_RGD_W0_SRTADDR_MASK)
+/*! @} */
+
+/* The count of OTFAD_RGD_W0 */
+#define OTFAD_RGD_W0_COUNT (4U)
+
+/*! @name RGD_W1 - AES Region Descriptor Word1 */
+/*! @{ */
+#define OTFAD_RGD_W1_VLD_MASK (0x1U)
+#define OTFAD_RGD_W1_VLD_SHIFT (0U)
+/*! VLD - Valid
+ * 0b0..Context is invalid.
+ * 0b1..Context is valid.
+ */
+#define OTFAD_RGD_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_VLD_SHIFT)) & OTFAD_RGD_W1_VLD_MASK)
+#define OTFAD_RGD_W1_ADE_MASK (0x2U)
+#define OTFAD_RGD_W1_ADE_SHIFT (1U)
+/*! ADE - AES Decryption Enable.
+ * 0b0..Bypass the fetched data.
+ * 0b1..Perform the CTR-AES128 mode decryption on the fetched data.
+ */
+#define OTFAD_RGD_W1_ADE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ADE_SHIFT)) & OTFAD_RGD_W1_ADE_MASK)
+#define OTFAD_RGD_W1_RO_MASK (0x4U)
+#define OTFAD_RGD_W1_RO_SHIFT (2U)
+/*! RO - Read-Only
+ * 0b0..The context registers can be accessed normally (as defined by SR[RRAM]).
+ * 0b1..The context registers are read-only and accesses may be further restricted based on SR[RRAM].
+ */
+#define OTFAD_RGD_W1_RO(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_RO_SHIFT)) & OTFAD_RGD_W1_RO_MASK)
+#define OTFAD_RGD_W1_ENDADDR_MASK (0xFFFFFC00U)
+#define OTFAD_RGD_W1_ENDADDR_SHIFT (10U)
+/*! ENDADDR - End Address
+ */
+#define OTFAD_RGD_W1_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ENDADDR_SHIFT)) & OTFAD_RGD_W1_ENDADDR_MASK)
+/*! @} */
+
+/* The count of OTFAD_RGD_W1 */
+#define OTFAD_RGD_W1_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group OTFAD_Register_Masks */
+
+
+/* OTFAD - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral OTFAD0 base address */
+ #define OTFAD0_BASE (0x50134000u)
+ /** Peripheral OTFAD0 base address */
+ #define OTFAD0_BASE_NS (0x40134000u)
+ /** Peripheral OTFAD0 base pointer */
+ #define OTFAD0 ((OTFAD_Type *)OTFAD0_BASE)
+ /** Peripheral OTFAD0 base pointer */
+ #define OTFAD0_NS ((OTFAD_Type *)OTFAD0_BASE_NS)
+ /** Array initializer of OTFAD peripheral base addresses */
+ #define OTFAD_BASE_ADDRS { OTFAD0_BASE }
+ /** Array initializer of OTFAD peripheral base pointers */
+ #define OTFAD_BASE_PTRS { OTFAD0 }
+ /** Array initializer of OTFAD peripheral base addresses */
+ #define OTFAD_BASE_ADDRS_NS { OTFAD0_BASE_NS }
+ /** Array initializer of OTFAD peripheral base pointers */
+ #define OTFAD_BASE_PTRS_NS { OTFAD0_NS }
+#else
+ /** Peripheral OTFAD0 base address */
+ #define OTFAD0_BASE (0x40134000u)
+ /** Peripheral OTFAD0 base pointer */
+ #define OTFAD0 ((OTFAD_Type *)OTFAD0_BASE)
+ /** Array initializer of OTFAD peripheral base addresses */
+ #define OTFAD_BASE_ADDRS { OTFAD0_BASE }
+ /** Array initializer of OTFAD peripheral base pointers */
+ #define OTFAD_BASE_PTRS { OTFAD0 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group OTFAD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PINT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
+ * @{
+ */
+
+/** PINT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t ISEL; /**< Pin Interrupt Mode, offset: 0x0 */
+ __IO uint32_t IENR; /**< Pin Interrupt Level or Rising Edge Interrupt Enable, offset: 0x4 */
+ __O uint32_t SIENR; /**< Pin Interrupt Level or Rising Edge Interrupt Set, offset: 0x8 */
+ __IO uint32_t CIENR; /**< Pin Interrupt Level (Rising Edge Interrupt) Clear, offset: 0xC */
+ __IO uint32_t IENF; /**< Pin Interrupt Active Level or Falling Edge Interrupt Enable, offset: 0x10 */
+ __O uint32_t SIENF; /**< Pin Interrupt Active Level or Falling Edge Interrupt Set, offset: 0x14 */
+ __O uint32_t CIENF; /**< Pin Interrupt Active Level or Falling Edge Interrupt Clear, offset: 0x18 */
+ __IO uint32_t RISE; /**< Pin Interrupt Rising Edge, offset: 0x1C */
+ __IO uint32_t FALL; /**< Pin Interrupt Falling Edge, offset: 0x20 */
+ __IO uint32_t IST; /**< Pin Interrupt Status, offset: 0x24 */
+ __IO uint32_t PMCTRL; /**< Pattern Match Interrupt Control, offset: 0x28 */
+ __IO uint32_t PMSRC; /**< Pattern Match Interrupt Bit-Slice Source, offset: 0x2C */
+ __IO uint32_t PMCFG; /**< Pattern Match Interrupt Bit Slice Configuration, offset: 0x30 */
+} PINT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PINT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Register_Masks PINT Register Masks
+ * @{
+ */
+
+/*! @name ISEL - Pin Interrupt Mode */
+/*! @{ */
+#define PINT_ISEL_PMODE_MASK (0xFFU)
+#define PINT_ISEL_PMODE_SHIFT (0U)
+/*! PMODE - Interrupt mode
+ * 0b00000000..Edge-sensitive
+ * 0b00000001..Level-sensitive
+ */
+#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
+/*! @} */
+
+/*! @name IENR - Pin Interrupt Level or Rising Edge Interrupt Enable */
+/*! @{ */
+#define PINT_IENR_ENRL_MASK (0xFFU)
+#define PINT_IENR_ENRL_SHIFT (0U)
+/*! ENRL - Enable Interrupt
+ * 0b00000000..Disable rising edge or level interrupt
+ * 0b00000001..Enable rising edge or level interrupt
+ */
+#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
+/*! @} */
+
+/*! @name SIENR - Pin Interrupt Level or Rising Edge Interrupt Set */
+/*! @{ */
+#define PINT_SIENR_SETENRL_MASK (0xFFU)
+#define PINT_SIENR_SETENRL_SHIFT (0U)
+/*! SETENRL - Set bits in the IENR
+ * 0b00000000..No operation
+ * 0b00000001..Enable rising edge or level interrupt
+ */
+#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
+/*! @} */
+
+/*! @name CIENR - Pin Interrupt Level (Rising Edge Interrupt) Clear */
+/*! @{ */
+#define PINT_CIENR_CENRL_MASK (0xFFU)
+#define PINT_CIENR_CENRL_SHIFT (0U)
+/*! CENRL - Clear bits in the IENR
+ * 0b00000000..No operation
+ * 0b00000001..Disable rising edge or level interrupt
+ */
+#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
+/*! @} */
+
+/*! @name IENF - Pin Interrupt Active Level or Falling Edge Interrupt Enable */
+/*! @{ */
+#define PINT_IENF_ENAF_MASK (0xFFU)
+#define PINT_IENF_ENAF_SHIFT (0U)
+/*! ENAF - Enable Interrupt
+ * 0b00000000..Disable falling edge interrupt or set active interrupt level LOW
+ * 0b00000001..Enable falling edge interrupt enabled or set active interrupt level HIGH
+ */
+#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
+/*! @} */
+
+/*! @name SIENF - Pin Interrupt Active Level or Falling Edge Interrupt Set */
+/*! @{ */
+#define PINT_SIENF_SETENAF_MASK (0xFFU)
+#define PINT_SIENF_SETENAF_SHIFT (0U)
+/*! SETENAF - Set bits in the IENF
+ * 0b00000000..No operation
+ * 0b00000001..Select HIGH-active interrupt or enable falling edge interrupt
+ */
+#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
+/*! @} */
+
+/*! @name CIENF - Pin Interrupt Active Level or Falling Edge Interrupt Clear */
+/*! @{ */
+#define PINT_CIENF_CENAF_MASK (0xFFU)
+#define PINT_CIENF_CENAF_SHIFT (0U)
+/*! CENAF - Clear bits in the IENF
+ * 0b00000000..No operation
+ * 0b00000001..LOW-active interrupt selected or falling edge interrupt disabled
+ */
+#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
+/*! @} */
+
+/*! @name RISE - Pin Interrupt Rising Edge */
+/*! @{ */
+#define PINT_RISE_RDET_MASK (0xFFU)
+#define PINT_RISE_RDET_SHIFT (0U)
+/*! RDET - Rising edge detect
+ * 0b00000000..Read 0- No rising edge has been detected on this pin since Reset or the last time a one was written to this bit, Write 0- no operation
+ * 0b00000001..Read 1- a rising edge has been detected since Reset or the last time a one was written to this
+ * bit, Write 1- clear rising edge detection for this pin
+ */
+#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
+/*! @} */
+
+/*! @name FALL - Pin Interrupt Falling Edge */
+/*! @{ */
+#define PINT_FALL_FDET_MASK (0xFFU)
+#define PINT_FALL_FDET_SHIFT (0U)
+/*! FDET - Falling edge detect
+ * 0b00000000..Read 0- No falling edge has been detected on this pin since Reset or the last time a one was written to this bit, Write 0- no operation
+ * 0b00000001..Read 1- a falling edge has been detected since Reset or the last time a one was written to this
+ * bit, Write 1- clear falling edge detection for this bit
+ */
+#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
+/*! @} */
+
+/*! @name IST - Pin Interrupt Status */
+/*! @{ */
+#define PINT_IST_PSTAT_MASK (0xFFU)
+#define PINT_IST_PSTAT_SHIFT (0U)
+/*! PSTAT - Pin interrupt status
+ * 0b00000000..Read 0- interrupt is not being requested for this pin, Write 0- no operation.
+ * 0b00000001..Read 1- interrupt is being requested for this pin, Write 1 (edge-sensitive)- clear rising- and
+ * falling-edge detection for this pin, Write 1 (level-sensitive)- switch the active level for this pin
+ * (in the IENF register).
+ */
+#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
+/*! @} */
+
+/*! @name PMCTRL - Pattern Match Interrupt Control */
+/*! @{ */
+#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)
+#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)
+/*! SEL_PMATCH - Specifies whether the pin interrupts are controlled by the pin interrupt function or by the pattern match function.
+ * 0b0..Pin interrupt- interrupts are driven in response to the standard pin interrupt function.
+ * 0b1..Pattern match- interrupts are driven in response to pattern matches.
+ */
+#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
+#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)
+#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)
+/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output, when the specified boolean expression evaluates to true.
+ * 0b0..Disabled- RXEV output to the CPU is disabled.
+ * 0b1..Enabled- RXEV output to the CPU is enabled.
+ */
+#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
+#define PINT_PMCTRL_PMAT_MASK (0xFF000000U)
+#define PINT_PMCTRL_PMAT_SHIFT (24U)
+/*! PMAT - Pattern Matches
+ * 0b00000001..The corresponding product term is matched by the current state of the appropriate inputs.
+ */
+#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
+/*! @} */
+
+/*! @name PMSRC - Pattern Match Interrupt Bit-Slice Source */
+/*! @{ */
+#define PINT_PMSRC_SRC0_MASK (0x700U)
+#define PINT_PMSRC_SRC0_SHIFT (8U)
+/*! SRC0 - Selects the input source for bit slice 0
+ * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
+#define PINT_PMSRC_SRC1_MASK (0x3800U)
+#define PINT_PMSRC_SRC1_SHIFT (11U)
+/*! SRC1 - Selects the input source for bit slice 1
+ * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
+#define PINT_PMSRC_SRC2_MASK (0x1C000U)
+#define PINT_PMSRC_SRC2_SHIFT (14U)
+/*! SRC2 - Selects the input source for bit slice 2
+ * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
+#define PINT_PMSRC_SRC3_MASK (0xE0000U)
+#define PINT_PMSRC_SRC3_SHIFT (17U)
+/*! SRC3 - Selects the input source for bit slice 3
+ * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
+#define PINT_PMSRC_SRC4_MASK (0x700000U)
+#define PINT_PMSRC_SRC4_SHIFT (20U)
+/*! SRC4 - Selects the input source for bit slice 4
+ * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
+#define PINT_PMSRC_SRC5_MASK (0x3800000U)
+#define PINT_PMSRC_SRC5_SHIFT (23U)
+/*! SRC5 - Selects the input source for bit slice 5
+ * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
+#define PINT_PMSRC_SRC6_MASK (0x1C000000U)
+#define PINT_PMSRC_SRC6_SHIFT (26U)
+/*! SRC6 - Selects the input source for bit slice 6
+ * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
+#define PINT_PMSRC_SRC7_MASK (0xE0000000U)
+#define PINT_PMSRC_SRC7_SHIFT (29U)
+/*! SRC7 - Selects the input source for bit slice 7
+ * 0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
+ * 0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
+ * 0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
+ * 0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
+ * 0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
+ * 0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
+ * 0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
+ * 0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
+ */
+#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
+/*! @} */
+
+/*! @name PMCFG - Pattern Match Interrupt Bit Slice Configuration */
+/*! @{ */
+#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)
+#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)
+/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.
+ * 0b0..No effect. Slice 0 is not an endpoint.
+ * 0b1..Endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
+#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)
+#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)
+/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.
+ * 0b0..No effect. Slice 1 is not an endpoint.
+ * 0b1..Endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
+#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)
+#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)
+/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.
+ * 0b0..No effect. Slice 2 is not an endpoint.
+ * 0b1..Endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
+#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)
+#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)
+/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.
+ * 0b0..No effect. Slice 3 is not an endpoint.
+ * 0b1..Endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
+#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)
+#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)
+/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.
+ * 0b0..No effect. Slice 4 is not an endpoint.
+ * 0b1..Endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
+#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)
+#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)
+/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.
+ * 0b0..No effect. Slice 5 is not an endpoint.
+ * 0b1..Endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
+#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)
+#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)
+/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.
+ * 0b0..No effect. Slice 6 is not an endpoint.
+ * 0b1..Endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
+ */
+#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
+#define PINT_PMCFG_CFG0_MASK (0x700U)
+#define PINT_PMCFG_CFG0_SHIFT (8U)
+/*! CFG0 - Specifies the match contribution condition for bit slice 0.
+ * 0b000..Constant HIGH
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ * is only cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ * cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
+#define PINT_PMCFG_CFG1_MASK (0x3800U)
+#define PINT_PMCFG_CFG1_SHIFT (11U)
+/*! CFG1 - Specifies the match contribution condition for bit slice 1.
+ * 0b000..Constant HIGH
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ * is only cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ * cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
+#define PINT_PMCFG_CFG2_MASK (0x1C000U)
+#define PINT_PMCFG_CFG2_SHIFT (14U)
+/*! CFG2 - Specifies the match contribution condition for bit slice 2.
+ * 0b000..Constant HIGH
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ * is only cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ * cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
+#define PINT_PMCFG_CFG3_MASK (0xE0000U)
+#define PINT_PMCFG_CFG3_SHIFT (17U)
+/*! CFG3 - Specifies the match contribution condition for bit slice 3.
+ * 0b000..Constant HIGH
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ * is only cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ * cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
+#define PINT_PMCFG_CFG4_MASK (0x700000U)
+#define PINT_PMCFG_CFG4_SHIFT (20U)
+/*! CFG4 - Specifies the match contribution condition for bit slice 4.
+ * 0b000..Constant HIGH
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ * is only cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ * cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
+#define PINT_PMCFG_CFG5_MASK (0x3800000U)
+#define PINT_PMCFG_CFG5_SHIFT (23U)
+/*! CFG5 - Specifies the match contribution condition for bit slice 5.
+ * 0b000..Constant HIGH
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ * is only cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ * cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
+#define PINT_PMCFG_CFG6_MASK (0x1C000000U)
+#define PINT_PMCFG_CFG6_SHIFT (26U)
+/*! CFG6 - Specifies the match contribution condition for bit slice 6.
+ * 0b000..Constant HIGH
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ * is only cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ * cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
+#define PINT_PMCFG_CFG7_MASK (0xE0000000U)
+#define PINT_PMCFG_CFG7_SHIFT (29U)
+/*! CFG7 - Specifies the match contribution condition for bit slice 7.
+ * 0b000..Constant HIGH
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
+ * time the edge detection for this bit slice was cleared. This match condition is only cleared when the
+ * PMCFG or the PMSRC registers are written to.
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
+ * has occurred since the last time the edge detection for this bit slice was cleared. This match condition
+ * is only cleared when the PMCFG or the PMSRC registers are written to.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
+ * is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
+ * cleared after 1 clock cycle.
+ */
+#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PINT_Register_Masks */
+
+
+/* PINT - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral PINT base address */
+ #define PINT_BASE (0x50025000u)
+ /** Peripheral PINT base address */
+ #define PINT_BASE_NS (0x40025000u)
+ /** Peripheral PINT base pointer */
+ #define PINT ((PINT_Type *)PINT_BASE)
+ /** Peripheral PINT base pointer */
+ #define PINT_NS ((PINT_Type *)PINT_BASE_NS)
+ /** Array initializer of PINT peripheral base addresses */
+ #define PINT_BASE_ADDRS { PINT_BASE }
+ /** Array initializer of PINT peripheral base pointers */
+ #define PINT_BASE_PTRS { PINT }
+ /** Array initializer of PINT peripheral base addresses */
+ #define PINT_BASE_ADDRS_NS { PINT_BASE_NS }
+ /** Array initializer of PINT peripheral base pointers */
+ #define PINT_BASE_PTRS_NS { PINT_NS }
+#else
+ /** Peripheral PINT base address */
+ #define PINT_BASE (0x40025000u)
+ /** Peripheral PINT base pointer */
+ #define PINT ((PINT_Type *)PINT_BASE)
+ /** Array initializer of PINT peripheral base addresses */
+ #define PINT_BASE_ADDRS { PINT_BASE }
+ /** Array initializer of PINT peripheral base pointers */
+ #define PINT_BASE_PTRS { PINT }
+#endif
+/** Interrupt vectors for the PINT peripheral type */
+#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PINT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[4];
+ __I uint32_t STATUS; /**< Status, offset: 0x4 */
+ __IO uint32_t FLAGS; /**< Wakeup, Interrupt, Reset Flags, offset: 0x8 */
+ __IO uint32_t CTRL; /**< PMC control register, offset: 0xC */
+ __IO uint32_t RUNCTRL; /**< PMC controls used during run mode, offset: 0x10 */
+ __IO uint32_t SLEEPCTRL; /**< PMC controls used during deep sleep mode, offset: 0x14 */
+ __IO uint32_t LVDCORECTRL; /**< PMC Active vddcore LVD monitor trip adjust, offset: 0x18 */
+ uint8_t RESERVED_1[8];
+ __IO uint32_t AUTOWKUP; /**< PMC Automatic wakeup from deepsleep mode, offset: 0x24 */
+ __IO uint32_t PMICCFG; /**< PMIC Power Mode Select Control Configuration, offset: 0x28 */
+ __IO uint32_t PADVRANGE; /**< PMC GPIO VDDIO Range Selection Control, offset: 0x2C */
+ __IO uint32_t MEMSEQCTRL; /**< PMC Memory sequencer Control, offset: 0x30 */
+ uint8_t RESERVED_2[44];
+ __IO uint32_t TSENSOR; /**< PMC Temperature Sensor Control, offset: 0x60 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/*! @name STATUS - Status */
+/*! @{ */
+#define PMC_STATUS_ACTIVEFSM_MASK (0x1U)
+#define PMC_STATUS_ACTIVEFSM_SHIFT (0U)
+/*! ACTIVEFSM - General sequencer and finite state machine status
+ * 0b0..All PMC finite state machines are idle. OK to set APPLYCFG to trigger the PMC state machines.
+ * 0b1..One or more PMC finite state machines are active, do not set APPLYCFG or write to any PDRUNCFG or CTRL
+ * register values that are used by the PMC state machines.
+ */
+#define PMC_STATUS_ACTIVEFSM(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_ACTIVEFSM_SHIFT)) & PMC_STATUS_ACTIVEFSM_MASK)
+/*! @} */
+
+/*! @name FLAGS - Wakeup, Interrupt, Reset Flags */
+/*! @{ */
+#define PMC_FLAGS_PORCOREF_MASK (0x10000U)
+#define PMC_FLAGS_PORCOREF_SHIFT (16U)
+/*! PORCOREF - vddcore POR Flag
+ * 0b0..vddcore POR was not tripped since the last cleared.
+ * 0b1..POR triggered by the vddcore POR monitor. Write 1 to clear
+ */
+#define PMC_FLAGS_PORCOREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_PORCOREF_SHIFT)) & PMC_FLAGS_PORCOREF_MASK)
+#define PMC_FLAGS_POR1V8F_MASK (0x20000U)
+#define PMC_FLAGS_POR1V8F_SHIFT (17U)
+/*! POR1V8F - vdd1v8 power on reset flag
+ * 0b0..No vdd1v8 power on event detected since last cleared.
+ * 0b1..vdd1v8 power on detect caused a reset or deep power down wakeup. Write 1 to clear.
+ */
+#define PMC_FLAGS_POR1V8F(x) (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_POR1V8F_SHIFT)) & PMC_FLAGS_POR1V8F_MASK)
+#define PMC_FLAGS_PORAO18F_MASK (0x40000U)
+#define PMC_FLAGS_PORAO18F_SHIFT (18U)
+/*! PORAO18F - VDD_AO18 power on reset flag
+ * 0b0..No VDD_AO18 power on event detected since last cleared.
+ * 0b1..VDD_AO18 power on detect caused a reset. Write 1 to clear.
+ */
+#define PMC_FLAGS_PORAO18F(x) (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_PORAO18F_SHIFT)) & PMC_FLAGS_PORAO18F_MASK)
+#define PMC_FLAGS_LVDCOREF_MASK (0x100000U)
+#define PMC_FLAGS_LVDCOREF_SHIFT (20U)
+/*! LVDCOREF - vddcore Low-Voltage Detector Flag
+ * 0b0..vddcore LVD has not tripped since last clear
+ * 0b1..vddcore LVD tripped since last time this bit was cleared. Write 1 to clear
+ */
+#define PMC_FLAGS_LVDCOREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_LVDCOREF_SHIFT)) & PMC_FLAGS_LVDCOREF_MASK)
+#define PMC_FLAGS_HVDCOREF_MASK (0x400000U)
+#define PMC_FLAGS_HVDCOREF_SHIFT (22U)
+/*! HVDCOREF - vddcore High-Voltage Detector Flag
+ * 0b0..vddcore HVD has not tripped since last clear
+ * 0b1..vddcore HVD tripped since last time this bit was cleared. Write 1 to clear
+ */
+#define PMC_FLAGS_HVDCOREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_HVDCOREF_SHIFT)) & PMC_FLAGS_HVDCOREF_MASK)
+#define PMC_FLAGS_HVD1V8F_MASK (0x1000000U)
+#define PMC_FLAGS_HVD1V8F_SHIFT (24U)
+/*! HVD1V8F - vdd1v8 High-Voltage Detector Flag
+ * 0b0..vdd1v8 HVD has not tripped since last clear
+ * 0b1..vdd1v8 HVD tripped since last time this bit was cleared. Write 1 to clear
+ */
+#define PMC_FLAGS_HVD1V8F(x) (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_HVD1V8F_SHIFT)) & PMC_FLAGS_HVD1V8F_MASK)
+#define PMC_FLAGS_RTCF_MASK (0x8000000U)
+#define PMC_FLAGS_RTCF_SHIFT (27U)
+/*! RTCF - RTC Wakeup from deep powerdown mode flag
+ * 0b0..No RTC wakeup detected since last time flag was cleared.
+ * 0b1..RTC wakeup caused a deep powerdown wakeup. Write 1 to clear.
+ */
+#define PMC_FLAGS_RTCF(x) (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_RTCF_SHIFT)) & PMC_FLAGS_RTCF_MASK)
+#define PMC_FLAGS_AUTOWKF_MASK (0x10000000U)
+#define PMC_FLAGS_AUTOWKF_SHIFT (28U)
+/*! AUTOWKF - PMC Auto Wakeup Interrupt flag
+ * 0b0..No PMC Auto Wakeup Interrupt detected since last time cleared.
+ * 0b1..PMC Auto wakeup caused a deep sleep wakeup and interrupt. Write 1 to clear.
+ */
+#define PMC_FLAGS_AUTOWKF(x) (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_AUTOWKF_SHIFT)) & PMC_FLAGS_AUTOWKF_MASK)
+#define PMC_FLAGS_INTNPADF_MASK (0x20000000U)
+#define PMC_FLAGS_INTNPADF_SHIFT (29U)
+/*! INTNPADF - PMIC_IRQ_N Interrupt pin flag
+ * 0b0..No interrupt detected since flag last cleared.
+ * 0b1..Pad interrupt caused a wakeup or interrupt event since the last time this flag was cleared. Write 1 to clear.
+ */
+#define PMC_FLAGS_INTNPADF(x) (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_INTNPADF_SHIFT)) & PMC_FLAGS_INTNPADF_MASK)
+#define PMC_FLAGS_RESETNPADF_MASK (0x40000000U)
+#define PMC_FLAGS_RESETNPADF_SHIFT (30U)
+/*! RESETNPADF - Reset pad flag
+ * 0b0..No reset detected since last time this flag was cleared.
+ * 0b1..Reset pad wakeup caused a wakeup or reset event since the last time this bit was cleared. Write 1 to clear.
+ */
+#define PMC_FLAGS_RESETNPADF(x) (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_RESETNPADF_SHIFT)) & PMC_FLAGS_RESETNPADF_MASK)
+#define PMC_FLAGS_DEEPPDF_MASK (0x80000000U)
+#define PMC_FLAGS_DEEPPDF_SHIFT (31U)
+/*! DEEPPDF - Deep powerdown wakeup flag
+ * 0b0..No deep powerdown wakeup since last time flag was cleared.
+ * 0b1..Deep powerdown was entered since the last time this flag was cleared. Write 1 to clear
+ */
+#define PMC_FLAGS_DEEPPDF(x) (((uint32_t)(((uint32_t)(x)) << PMC_FLAGS_DEEPPDF_SHIFT)) & PMC_FLAGS_DEEPPDF_MASK)
+/*! @} */
+
+/*! @name CTRL - PMC control register */
+/*! @{ */
+#define PMC_CTRL_APPLYCFG_MASK (0x1U)
+#define PMC_CTRL_APPLYCFG_SHIFT (0U)
+/*! APPLYCFG - Apply updated PMC PDRUNCFG bits
+ * 0b0..Always reads 0. Write 0 has no effect
+ * 0b1..Write 1 = initiate update sequencing of PMC state machines
+ */
+#define PMC_CTRL_APPLYCFG(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_APPLYCFG_SHIFT)) & PMC_CTRL_APPLYCFG_MASK)
+#define PMC_CTRL_CLKDIVEN_MASK (0x2U)
+#define PMC_CTRL_CLKDIVEN_SHIFT (1U)
+/*! CLKDIVEN - Internal clock divider enable
+ * 0b0..16MHz clock selected
+ * 0b1..4MHz clock selected
+ */
+#define PMC_CTRL_CLKDIVEN(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_CLKDIVEN_SHIFT)) & PMC_CTRL_CLKDIVEN_MASK)
+#define PMC_CTRL_BUFEN_MASK (0x10U)
+#define PMC_CTRL_BUFEN_SHIFT (4U)
+/*! BUFEN - Enable analog buffer for references or ATX2
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define PMC_CTRL_BUFEN(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_BUFEN_SHIFT)) & PMC_CTRL_BUFEN_MASK)
+#define PMC_CTRL_OTPSWREN_MASK (0x40000U)
+#define PMC_CTRL_OTPSWREN_SHIFT (18U)
+/*! OTPSWREN - OTP Switch RBB enable
+ */
+#define PMC_CTRL_OTPSWREN(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_OTPSWREN_SHIFT)) & PMC_CTRL_OTPSWREN_MASK)
+#define PMC_CTRL_LVDCOREIE_MASK (0x100000U)
+#define PMC_CTRL_LVDCOREIE_SHIFT (20U)
+/*! LVDCOREIE - vddcore Low-Voltage Detector Interrupt Enable
+ * 0b0..vddcore LVD interrupt disabled
+ * 0b1..vddcore LVD causes interrupt and wakeup from deep sleep.
+ */
+#define PMC_CTRL_LVDCOREIE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_LVDCOREIE_SHIFT)) & PMC_CTRL_LVDCOREIE_MASK)
+#define PMC_CTRL_LVDCORERE_MASK (0x200000U)
+#define PMC_CTRL_LVDCORERE_SHIFT (21U)
+/*! LVDCORERE - vddcore Low-Voltage Detector Reset Enable
+ * 0b0..vddcore LVD reset disabled
+ * 0b1..vddcore LVD causes reset
+ */
+#define PMC_CTRL_LVDCORERE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_LVDCORERE_SHIFT)) & PMC_CTRL_LVDCORERE_MASK)
+#define PMC_CTRL_HVDCOREIE_MASK (0x400000U)
+#define PMC_CTRL_HVDCOREIE_SHIFT (22U)
+/*! HVDCOREIE - vddcore High-Voltage Detector Interrupt Enable
+ * 0b0..vddcore HVD interrupt disabled
+ * 0b1..vddcore HVD causes interrupt and wakeup from deep sleep.
+ */
+#define PMC_CTRL_HVDCOREIE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_HVDCOREIE_SHIFT)) & PMC_CTRL_HVDCOREIE_MASK)
+#define PMC_CTRL_HVDCORERE_MASK (0x800000U)
+#define PMC_CTRL_HVDCORERE_SHIFT (23U)
+/*! HVDCORERE - vddcore High-Voltage Detector Reset Enable
+ * 0b0..vddcore HVD reset disabled
+ * 0b1..vddcore HVD causes reset
+ */
+#define PMC_CTRL_HVDCORERE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_HVDCORERE_SHIFT)) & PMC_CTRL_HVDCORERE_MASK)
+#define PMC_CTRL_HVD1V8IE_MASK (0x1000000U)
+#define PMC_CTRL_HVD1V8IE_SHIFT (24U)
+/*! HVD1V8IE - vdd1v8 High-Voltage Detector Interrupt Enable
+ * 0b0..vdd1v8 HVD interrupt disabled
+ * 0b1..vdd1v8 HVD causes interrupt and wakeup from deep sleep or deep power down mode.
+ */
+#define PMC_CTRL_HVD1V8IE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_HVD1V8IE_SHIFT)) & PMC_CTRL_HVD1V8IE_MASK)
+#define PMC_CTRL_HVD1V8RE_MASK (0x2000000U)
+#define PMC_CTRL_HVD1V8RE_SHIFT (25U)
+/*! HVD1V8RE - vdd1v8 High-Voltage Detector Reset Enable
+ * 0b0..vdd1v8 HVD reset disabled
+ * 0b1..vdd1v8 HVD causes reset
+ */
+#define PMC_CTRL_HVD1V8RE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_HVD1V8RE_SHIFT)) & PMC_CTRL_HVD1V8RE_MASK)
+#define PMC_CTRL_AUTOWKEN_MASK (0x10000000U)
+#define PMC_CTRL_AUTOWKEN_SHIFT (28U)
+/*! AUTOWKEN - PMC automatic wakeup enable and interrupt enable
+ * 0b0..Auto wakeup interrupt and counter disabled
+ * 0b1..Auto wakeup interrupt generated when PMC sequencer finishes and AUTOWAKE counter = 0 after entering deep
+ * sleep mode (but not deep powerdown mode). Interrupt will wake up the M33.
+ */
+#define PMC_CTRL_AUTOWKEN(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_AUTOWKEN_SHIFT)) & PMC_CTRL_AUTOWKEN_MASK)
+#define PMC_CTRL_INTRPADEN_MASK (0x20000000U)
+#define PMC_CTRL_INTRPADEN_SHIFT (29U)
+/*! INTRPADEN - PMIC_IRQ_N enable
+ * 0b0..Interrupt pad low has no effect
+ * 0b1..Interrupt pad low triggers an interrupt and deep sleep wakeup or deep powerdown wakeup event.
+ */
+#define PMC_CTRL_INTRPADEN(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_INTRPADEN_SHIFT)) & PMC_CTRL_INTRPADEN_MASK)
+/*! @} */
+
+/*! @name RUNCTRL - PMC controls used during run mode */
+/*! @{ */
+#define PMC_RUNCTRL_CORELVL_MASK (0x3FU)
+#define PMC_RUNCTRL_CORELVL_SHIFT (0U)
+/*! CORELVL - Vddcore voltage value when using on-chip regulator and SYSCTL is in run mode.
+ * 0b000001..0.6V
+ * 0b010000..0.7V
+ * 0b010011..0.8V
+ * 0b100110..1.0V
+ * 0b110010..1.138V
+ */
+#define PMC_RUNCTRL_CORELVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RUNCTRL_CORELVL_SHIFT)) & PMC_RUNCTRL_CORELVL_MASK)
+/*! @} */
+
+/*! @name SLEEPCTRL - PMC controls used during deep sleep mode */
+/*! @{ */
+#define PMC_SLEEPCTRL_CORELVL_MASK (0x3FU)
+#define PMC_SLEEPCTRL_CORELVL_SHIFT (0U)
+/*! CORELVL - Vddcore voltage value when using on-chip regulator and SYSCTL is in sleep mode.
+ * 0b000000..0.595833V
+ * 0b100110..1.007498V = 0.595833 + 0x26 10.8333mV
+ * 0b110010..1.138V
+ */
+#define PMC_SLEEPCTRL_CORELVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SLEEPCTRL_CORELVL_SHIFT)) & PMC_SLEEPCTRL_CORELVL_MASK)
+/*! @} */
+
+/*! @name LVDCORECTRL - PMC Active vddcore LVD monitor trip adjust */
+/*! @{ */
+#define PMC_LVDCORECTRL_LVDCORELVL_MASK (0xFU)
+#define PMC_LVDCORECTRL_LVDCORELVL_SHIFT (0U)
+/*! LVDCORELVL - Vddcore LVD falling trip voltage, in steps of 15mV
+ * 0b0000..0.720V
+ * 0b0111..0.825V = 0.720V + 7 x 15mV
+ * 0b1111..0.945V
+ */
+#define PMC_LVDCORECTRL_LVDCORELVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_LVDCORECTRL_LVDCORELVL_SHIFT)) & PMC_LVDCORECTRL_LVDCORELVL_MASK)
+/*! @} */
+
+/*! @name AUTOWKUP - PMC Automatic wakeup from deepsleep mode */
+/*! @{ */
+#define PMC_AUTOWKUP_AUTOWKTIME_MASK (0xFFFFU)
+#define PMC_AUTOWKUP_AUTOWKTIME_SHIFT (0U)
+/*! AUTOWKTIME
+ * 0b0000111111111111..delay time = 0x0FFF/16MHz (example)
+ */
+#define PMC_AUTOWKUP_AUTOWKTIME(x) (((uint32_t)(((uint32_t)(x)) << PMC_AUTOWKUP_AUTOWKTIME_SHIFT)) & PMC_AUTOWKUP_AUTOWKTIME_MASK)
+/*! @} */
+
+/*! @name PMICCFG - PMIC Power Mode Select Control Configuration */
+/*! @{ */
+#define PMC_PMICCFG_VDDCOREM0_MASK (0x1U)
+#define PMC_PMICCFG_VDDCOREM0_SHIFT (0U)
+/*! VDDCOREM0 - vddcore state in PMIC mode 0
+ * 0b0..Off
+ * 0b1..Powered
+ */
+#define PMC_PMICCFG_VDDCOREM0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PMICCFG_VDDCOREM0_SHIFT)) & PMC_PMICCFG_VDDCOREM0_MASK)
+#define PMC_PMICCFG_VDDCOREM1_MASK (0x2U)
+#define PMC_PMICCFG_VDDCOREM1_SHIFT (1U)
+/*! VDDCOREM1 - vddcore state in PMIC mode 1
+ * 0b0..Off
+ * 0b1..Powered
+ */
+#define PMC_PMICCFG_VDDCOREM1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PMICCFG_VDDCOREM1_SHIFT)) & PMC_PMICCFG_VDDCOREM1_MASK)
+#define PMC_PMICCFG_VDDCOREM2_MASK (0x4U)
+#define PMC_PMICCFG_VDDCOREM2_SHIFT (2U)
+/*! VDDCOREM2 - vddcore state in PMIC mode 2
+ * 0b0..Off
+ * 0b1..Powered
+ */
+#define PMC_PMICCFG_VDDCOREM2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PMICCFG_VDDCOREM2_SHIFT)) & PMC_PMICCFG_VDDCOREM2_MASK)
+#define PMC_PMICCFG_VDDCOREM3_MASK (0x8U)
+#define PMC_PMICCFG_VDDCOREM3_SHIFT (3U)
+/*! VDDCOREM3 - vddcore state in PMIC mode 3
+ * 0b0..Off
+ * 0b1..Powered
+ */
+#define PMC_PMICCFG_VDDCOREM3(x) (((uint32_t)(((uint32_t)(x)) << PMC_PMICCFG_VDDCOREM3_SHIFT)) & PMC_PMICCFG_VDDCOREM3_MASK)
+#define PMC_PMICCFG_VDD1V8M0_MASK (0x10U)
+#define PMC_PMICCFG_VDD1V8M0_SHIFT (4U)
+/*! VDD1V8M0 - vdd1v8 state in PMIC mode 0
+ * 0b0..Off
+ * 0b1..Powered
+ */
+#define PMC_PMICCFG_VDD1V8M0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PMICCFG_VDD1V8M0_SHIFT)) & PMC_PMICCFG_VDD1V8M0_MASK)
+#define PMC_PMICCFG_VDD1V8M1_MASK (0x20U)
+#define PMC_PMICCFG_VDD1V8M1_SHIFT (5U)
+/*! VDD1V8M1 - vdd1v8 state in PMIC mode 1
+ * 0b0..Off
+ * 0b1..Powered
+ */
+#define PMC_PMICCFG_VDD1V8M1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PMICCFG_VDD1V8M1_SHIFT)) & PMC_PMICCFG_VDD1V8M1_MASK)
+#define PMC_PMICCFG_VDD1V8M2_MASK (0x40U)
+#define PMC_PMICCFG_VDD1V8M2_SHIFT (6U)
+/*! VDD1V8M2 - vdd1v8 state in PMIC mode 2
+ * 0b0..Off
+ * 0b1..Powered
+ */
+#define PMC_PMICCFG_VDD1V8M2(x) (((uint32_t)(((uint32_t)(x)) << PMC_PMICCFG_VDD1V8M2_SHIFT)) & PMC_PMICCFG_VDD1V8M2_MASK)
+#define PMC_PMICCFG_VDD1V8M3_MASK (0x80U)
+#define PMC_PMICCFG_VDD1V8M3_SHIFT (7U)
+/*! VDD1V8M3 - vdd1v8 state in PMIC mode 3
+ * 0b0..Off
+ * 0b1..Powered
+ */
+#define PMC_PMICCFG_VDD1V8M3(x) (((uint32_t)(((uint32_t)(x)) << PMC_PMICCFG_VDD1V8M3_SHIFT)) & PMC_PMICCFG_VDD1V8M3_MASK)
+/*! @} */
+
+/*! @name PADVRANGE - PMC GPIO VDDIO Range Selection Control */
+/*! @{ */
+#define PMC_PADVRANGE_VDDIO_0RANGE_MASK (0x3U)
+#define PMC_PADVRANGE_VDDIO_0RANGE_SHIFT (0U)
+/*! VDDIO_0RANGE - VDDIO_0RANGE
+ * 0b00..1.71 - 1.98V. Consumes static current to detect VDDIO_0 level It is recommended that the user change
+ * this value to 01 to reduce power consumption.
+ * 0b01..1.71 - 1.98V, vdde detector off
+ * 0b10..Not allowed
+ * 0b11..Not allowed (hardware translates to 10)
+ */
+#define PMC_PADVRANGE_VDDIO_0RANGE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PADVRANGE_VDDIO_0RANGE_SHIFT)) & PMC_PADVRANGE_VDDIO_0RANGE_MASK)
+#define PMC_PADVRANGE_VDDIO_1RANGE_MASK (0xCU)
+#define PMC_PADVRANGE_VDDIO_1RANGE_SHIFT (2U)
+/*! VDDIO_1RANGE - VDDIO1RANGE It is recommended that the user change this value to 01 to reduce power consumption.
+ * 0b00..1.71 - 1.98V. Continuous mode. Consumes static current to detect VDDIO_1 level It is recommended that
+ * the user change this value to 01 to reduce power consumption.
+ * 0b01..1.71 - 1.98V, vdde detector off
+ * 0b10..Not allowed
+ * 0b11..Not allowed (hardware translates to 00 = continuous mode)
+ */
+#define PMC_PADVRANGE_VDDIO_1RANGE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PADVRANGE_VDDIO_1RANGE_SHIFT)) & PMC_PADVRANGE_VDDIO_1RANGE_MASK)
+#define PMC_PADVRANGE_VDDIO_2RANGE_MASK (0x30U)
+#define PMC_PADVRANGE_VDDIO_2RANGE_SHIFT (4U)
+/*! VDDIO_2RANGE - VDDIO2RANGE
+ * 0b00..1.71 - 1.98V. Continuous mode. Consumes static current to detect VDDIO_2 level It is recommended that
+ * the user change this value to 01 to reduce power consumption.
+ * 0b01..1.71 - 1.98V, vdde detector off
+ * 0b10..Not allowed
+ * 0b11..Not allowed (hardware translates to 00 = continuous mode)
+ */
+#define PMC_PADVRANGE_VDDIO_2RANGE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PADVRANGE_VDDIO_2RANGE_SHIFT)) & PMC_PADVRANGE_VDDIO_2RANGE_MASK)
+#define PMC_PADVRANGE_VDDIO_3RANGE_MASK (0xC0U)
+#define PMC_PADVRANGE_VDDIO_3RANGE_SHIFT (6U)
+/*! VDDIO_3RANGE - VDDIO3RANGE
+ * 0b00..1.71 - 3.6V. Continuous mode. Consumes static current to detect VDDIO_3 level
+ * 0b01..1.71 - 1.98V, vdde detector off
+ * 0b10..3.00 - 3.6V, vdde detector off
+ * 0b11..Not allowed (hardware translates to 00 = continuous mode)
+ */
+#define PMC_PADVRANGE_VDDIO_3RANGE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PADVRANGE_VDDIO_3RANGE_SHIFT)) & PMC_PADVRANGE_VDDIO_3RANGE_MASK)
+#define PMC_PADVRANGE_VDDIO_4RANGE_MASK (0x300U)
+#define PMC_PADVRANGE_VDDIO_4RANGE_SHIFT (8U)
+/*! VDDIO_4RANGE - VDDIO4RANGE
+ * 0b00..1.71 - 1.98V. Continuous mode. Consumes static current to detect VDDIO_4 level It is recommended that
+ * the user change this value to 01 to reduce power consumption.
+ * 0b01..1.71 - 1.98V, vdde detector off
+ * 0b10..Not allowed
+ * 0b11..Not allowed (hardware translates to 00 = continuous mode)
+ */
+#define PMC_PADVRANGE_VDDIO_4RANGE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PADVRANGE_VDDIO_4RANGE_SHIFT)) & PMC_PADVRANGE_VDDIO_4RANGE_MASK)
+/*! @} */
+
+/*! @name MEMSEQCTRL - PMC Memory sequencer Control */
+/*! @{ */
+#define PMC_MEMSEQCTRL_MEMSEQNUM_MASK (0x3FU)
+#define PMC_MEMSEQCTRL_MEMSEQNUM_SHIFT (0U)
+/*! MEMSEQNUM
+ * 0b000000..For main system SRAM partitions, 1st array power then periphery power (400ns worst case delay)
+ * 0b000001..Turn on 1st memory partition at a time, periphery and array power.switches at the same time.
+ * 0b000101..Turn on 5th memory partitions in parallel, periphery and array.
+ * 0b111111..All memories are switched on/off at the same time
+ */
+#define PMC_MEMSEQCTRL_MEMSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << PMC_MEMSEQCTRL_MEMSEQNUM_SHIFT)) & PMC_MEMSEQCTRL_MEMSEQNUM_MASK)
+/*! @} */
+
+/*! @name TSENSOR - PMC Temperature Sensor Control */
+/*! @{ */
+#define PMC_TSENSOR_TSENSM_MASK (0xFU)
+#define PMC_TSENSOR_TSENSM_SHIFT (0U)
+/*! TSENSM - Temperature sensor mode select
+ */
+#define PMC_TSENSOR_TSENSM(x) (((uint32_t)(((uint32_t)(x)) << PMC_TSENSOR_TSENSM_SHIFT)) & PMC_TSENSOR_TSENSM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral PMC base address */
+ #define PMC_BASE (0x50135000u)
+ /** Peripheral PMC base address */
+ #define PMC_BASE_NS (0x40135000u)
+ /** Peripheral PMC base pointer */
+ #define PMC ((PMC_Type *)PMC_BASE)
+ /** Peripheral PMC base pointer */
+ #define PMC_NS ((PMC_Type *)PMC_BASE_NS)
+ /** Array initializer of PMC peripheral base addresses */
+ #define PMC_BASE_ADDRS { PMC_BASE }
+ /** Array initializer of PMC peripheral base pointers */
+ #define PMC_BASE_PTRS { PMC }
+ /** Array initializer of PMC peripheral base addresses */
+ #define PMC_BASE_ADDRS_NS { PMC_BASE_NS }
+ /** Array initializer of PMC peripheral base pointers */
+ #define PMC_BASE_PTRS_NS { PMC_NS }
+#else
+ /** Peripheral PMC base address */
+ #define PMC_BASE (0x40135000u)
+ /** Peripheral PMC base pointer */
+ #define PMC ((PMC_Type *)PMC_BASE)
+ /** Array initializer of PMC peripheral base addresses */
+ #define PMC_BASE_ADDRS { PMC_BASE }
+ /** Array initializer of PMC peripheral base pointers */
+ #define PMC_BASE_PTRS { PMC }
+#endif
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- POWERQUAD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer
+ * @{
+ */
+
+/** POWERQUAD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t OUTBASE; /**< Output Base, offset: 0x0 */
+ __IO uint32_t OUTFORMAT; /**< Output Format, offset: 0x4 */
+ __IO uint32_t TMPBASE; /**< Temporary Base, offset: 0x8 */
+ __IO uint32_t TMPFORMAT; /**< Temporary Format, offset: 0xC */
+ __IO uint32_t INABASE; /**< Input A Base, offset: 0x10 */
+ __IO uint32_t INAFORMAT; /**< Input A Format, offset: 0x14 */
+ __IO uint32_t INBBASE; /**< Input B Base, offset: 0x18 */
+ __IO uint32_t INBFORMAT; /**< Input B Format, offset: 0x1C */
+ uint8_t RESERVED_0[224];
+ __IO uint32_t CONTROL; /**< Control, offset: 0x100 */
+ __IO uint32_t LENGTH; /**< Length, offset: 0x104 */
+ __IO uint32_t CPPRE; /**< Coprocessor Pre-scale, offset: 0x108 */
+ __IO uint32_t MISC; /**< Miscellaneous, offset: 0x10C */
+ __IO uint32_t CURSORY; /**< Cursory, offset: 0x110 */
+ uint8_t RESERVED_1[108];
+ __IO uint32_t CORDIC_X; /**< Cordic input X, offset: 0x180 */
+ __IO uint32_t CORDIC_Y; /**< Cordic Input Y, offset: 0x184 */
+ __IO uint32_t CORDIC_Z; /**< Cordic Input Z, offset: 0x188 */
+ __IO uint32_t ERRSTAT; /**< Error Status, offset: 0x18C */
+ __IO uint32_t INTREN; /**< Interrupt Enable, offset: 0x190 */
+ __IO uint32_t EVENTEN; /**< Event Enable, offset: 0x194 */
+ __IO uint32_t INTRSTAT; /**< Interrupt Status, offset: 0x198 */
+ uint8_t RESERVED_2[100];
+ __IO uint32_t GPREG[16]; /**< General Purpose Register Bank n, array offset: 0x200, array step: 0x4 */
+ __IO uint32_t COMPREG[8]; /**< Compute Register Bank n, array offset: 0x240, array step: 0x4 */
+} POWERQUAD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- POWERQUAD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks
+ * @{
+ */
+
+/*! @name OUTBASE - Output Base */
+/*! @{ */
+#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU)
+#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U)
+/*! OUTBASE - Base address register for the output region
+ */
+#define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK)
+/*! @} */
+
+/*! @name OUTFORMAT - Output Format */
+/*! @{ */
+#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U)
+#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U)
+/*! OUT_FORMATINT - Output Internal Format
+ */
+#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK)
+#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U)
+#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U)
+/*! OUT_FORMATEXT - Output External Format
+ */
+#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK)
+#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U)
+#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U)
+/*! OUT_SCALER - Output Scaler Value
+ */
+#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK)
+/*! @} */
+
+/*! @name TMPBASE - Temporary Base */
+/*! @{ */
+#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU)
+#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U)
+/*! TMPBASE - Base address register for the temporary region
+ */
+#define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK)
+/*! @} */
+
+/*! @name TMPFORMAT - Temporary Format */
+/*! @{ */
+#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U)
+#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U)
+/*! TMP_FORMATINT - Temporary Internal Format
+ */
+#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK)
+#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U)
+#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U)
+/*! TMP_FORMATEXT - Temporary External Format
+ */
+#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK)
+#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U)
+#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U)
+/*! TMP_SCALER - Temporary Scaler Value
+ */
+#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK)
+/*! @} */
+
+/*! @name INABASE - Input A Base */
+/*! @{ */
+#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU)
+#define POWERQUAD_INABASE_INABASE_SHIFT (0U)
+/*! INABASE - Input A Base
+ */
+#define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK)
+/*! @} */
+
+/*! @name INAFORMAT - Input A Format */
+/*! @{ */
+#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U)
+#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U)
+/*! INA_FORMATINT - Input A Internal Format
+ */
+#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK)
+#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U)
+#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U)
+/*! INA_FORMATEXT - Input A External Format
+ */
+#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK)
+#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U)
+#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U)
+/*! INA_SCALER - Input A Scaler Value
+ */
+#define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK)
+/*! @} */
+
+/*! @name INBBASE - Input B Base */
+/*! @{ */
+#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU)
+#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U)
+/*! INBBASE - Input B Base
+ */
+#define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK)
+/*! @} */
+
+/*! @name INBFORMAT - Input B Format */
+/*! @{ */
+#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U)
+#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U)
+/*! INB_FORMATINT - Input B Internal Format
+ */
+#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK)
+#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U)
+#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U)
+/*! INB_FORMATEXT - Input B External Format
+ */
+#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK)
+#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U)
+#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U)
+/*! INB_SCALER - Input B Scaler Value
+ */
+#define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK)
+/*! @} */
+
+/*! @name CONTROL - Control */
+/*! @{ */
+#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU)
+#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U)
+/*! DECODE_OPCODE - Decode Opcode
+ */
+#define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK)
+#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U)
+#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U)
+/*! DECODE_MACHINE - Decode Machine
+ */
+#define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK)
+#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U)
+#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U)
+/*! INST_BUSY - Instruction Busy
+ */
+#define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK)
+/*! @} */
+
+/*! @name LENGTH - Length */
+/*! @{ */
+#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU)
+#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U)
+/*! INST_LENGTH - Instruction Length
+ */
+#define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK)
+/*! @} */
+
+/*! @name CPPRE - Coprocessor Pre-scale */
+/*! @{ */
+#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU)
+#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U)
+/*! CPPRE_IN - Input
+ */
+#define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK)
+#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U)
+#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U)
+/*! CPPRE_OUT - Output
+ */
+#define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK)
+#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U)
+#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U)
+/*! CPPRE_SAT - Saturation
+ * 0b0..No saturation
+ * 0b1..Forces sub-32 bit saturation
+ */
+#define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK)
+#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U)
+#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U)
+/*! CPPRE_SAT8 - Saturation 8
+ * 0b0..8 bits
+ * 0b1..16 bits
+ */
+#define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK)
+/*! @} */
+
+/*! @name MISC - Miscellaneous */
+/*! @{ */
+#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU)
+#define POWERQUAD_MISC_INST_MISC_SHIFT (0U)
+/*! INST_MISC - For Matrix : Used for scaling factor
+ */
+#define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK)
+/*! @} */
+
+/*! @name CURSORY - Cursory */
+/*! @{ */
+#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U)
+#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U)
+/*! CURSORY - Cursory Mode
+ * 0b0..Disable Cursory mode
+ * 0b1..Enable Cursory Mode
+ */
+#define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK)
+/*! @} */
+
+/*! @name CORDIC_X - Cordic input X */
+/*! @{ */
+#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU)
+#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U)
+/*! CORDIC_X - Cordic Input x
+ */
+#define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK)
+/*! @} */
+
+/*! @name CORDIC_Y - Cordic Input Y */
+/*! @{ */
+#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU)
+#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U)
+/*! CORDIC_Y - Cordic Input y
+ */
+#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK)
+/*! @} */
+
+/*! @name CORDIC_Z - Cordic Input Z */
+/*! @{ */
+#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU)
+#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U)
+/*! CORDIC_Z - Cordic Input z
+ */
+#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK)
+/*! @} */
+
+/*! @name ERRSTAT - Error Status */
+/*! @{ */
+#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U)
+#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U)
+/*! OVERFLOW - Floating Point Overflow
+ * 0b0..No Error
+ * 0b1..Error on Floating Point Overflow
+ */
+#define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK)
+#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U)
+#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U)
+/*! NAN - Floating Point NaN
+ * 0b0..No Error
+ * 0b1..Error on Floating Point NaN
+ */
+#define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK)
+#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U)
+#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U)
+/*! FIXEDOVERFLOW - Fixed Point Overflow
+ * 0b0..No Error
+ * 0b1..Error on Fixed Point Overflow
+ */
+#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK)
+#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U)
+#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U)
+/*! UNDERFLOW - Underflow
+ * 0b0..No Error
+ * 0b1..Error on Underflow
+ */
+#define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK)
+#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U)
+#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U)
+/*! BUSERROR - Bus Error
+ * 0b0..No Error
+ * 0b1..Error on Bus
+ */
+#define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK)
+/*! @} */
+
+/*! @name INTREN - Interrupt Enable */
+/*! @{ */
+#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U)
+#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U)
+/*! INTR_OFLOW - Interrupt Floating Point Overflow
+ * 0b0..Disable
+ * 0b1..Enable interrupt on floating point overflow
+ */
+#define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK)
+#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U)
+#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U)
+/*! INTR_NAN - Interrupt Floating Point NaN
+ * 0b0..Disable
+ * 0b1..Enable interrupt on floating point NaN
+ */
+#define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK)
+#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U)
+#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U)
+/*! INTR_FIXED - Interrupt on Fixed Point Overflow
+ * 0b0..Disable
+ * 0b1..Enable interrupt on fixed point overflow
+ */
+#define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK)
+#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U)
+#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U)
+/*! INTR_UFLOW - Interrupt on Subnormal Truncation
+ * 0b0..Disable
+ * 0b1..Enable interrupt on subnormal truncation
+ */
+#define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK)
+#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U)
+#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U)
+/*! INTR_BERR - Interrupt on AHBM Bus Error
+ * 0b0..Disable
+ * 0b1..Enable interrupt on AHBM Bus Error
+ */
+#define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK)
+#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U)
+#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U)
+/*! INTR_COMP - Interrupt on Instruction Completion
+ * 0b0..Disable
+ * 0b1..Enable interrupt on instruction completion
+ */
+#define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK)
+/*! @} */
+
+/*! @name EVENTEN - Event Enable */
+/*! @{ */
+#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U)
+#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U)
+/*! EVENT_OFLOW - Event Trigger on Floating Point Overflow
+ * 0b0..Disable
+ * 0b1..Enable event trigger on Floating point overflow
+ */
+#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK)
+#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U)
+#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U)
+/*! EVENT_NAN - Event Trigger on Floating Point NaN
+ * 0b0..Disable
+ * 0b1..Enable event trigger on floating point NaN
+ */
+#define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK)
+#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U)
+#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U)
+/*! EVENT_FIXED - Event Trigger on Fixed Point Overflow
+ * 0b0..Disable
+ * 0b1..Enable event trigger on fixed point overflow
+ */
+#define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK)
+#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U)
+#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U)
+/*! EVENT_UFLOW - Event Trigger on Subnormal Truncation
+ * 0b0..Disable
+ * 0b1..Enable event trigger on subnormal truncation
+ */
+#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK)
+#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U)
+#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U)
+/*! EVENT_BERR - Event Trigger on AHBM Bus Error
+ * 0b0..Disable
+ * 0b1..Enable event trigger on AHBM bus error
+ */
+#define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK)
+#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U)
+#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U)
+/*! EVENT_COMP - Event Trigger on Instruction Completion
+ * 0b0..Disable
+ * 0b1..Enable event trigger on instruction completion
+ */
+#define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK)
+/*! @} */
+
+/*! @name INTRSTAT - Interrupt Status */
+/*! @{ */
+#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U)
+#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U)
+/*! INTR_STAT - Interrupt Status
+ * 0b0..No new interrupt
+ * 0b1..Interrupt captured
+ */
+#define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK)
+/*! @} */
+
+/*! @name GPREG - General Purpose Register Bank n */
+/*! @{ */
+#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU)
+#define POWERQUAD_GPREG_GPREG_SHIFT (0U)
+/*! GPREG - General Purpose Register Bank
+ */
+#define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK)
+/*! @} */
+
+/* The count of POWERQUAD_GPREG */
+#define POWERQUAD_GPREG_COUNT (16U)
+
+/*! @name COMPREGS_COMPREG - Compute Register Bank n */
+/*! @{ */
+#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU)
+#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U)
+/*! COMPREG - Compute Register Bank
+ */
+#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK)
+/*! @} */
+
+/* The count of POWERQUAD_COMPREGS_COMPREG */
+#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U)
+
+
+/*!
+ * @}
+ */ /* end of group POWERQUAD_Register_Masks */
+
+
+/* POWERQUAD - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral POWERQUAD base address */
+ #define POWERQUAD_BASE (0x50200000u)
+ /** Peripheral POWERQUAD base address */
+ #define POWERQUAD_BASE_NS (0x40200000u)
+ /** Peripheral POWERQUAD base pointer */
+ #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE)
+ /** Peripheral POWERQUAD base pointer */
+ #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS)
+ /** Array initializer of POWERQUAD peripheral base addresses */
+ #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE }
+ /** Array initializer of POWERQUAD peripheral base pointers */
+ #define POWERQUAD_BASE_PTRS { POWERQUAD }
+ /** Array initializer of POWERQUAD peripheral base addresses */
+ #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS }
+ /** Array initializer of POWERQUAD peripheral base pointers */
+ #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS }
+#else
+ /** Peripheral POWERQUAD base address */
+ #define POWERQUAD_BASE (0x40200000u)
+ /** Peripheral POWERQUAD base pointer */
+ #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE)
+ /** Array initializer of POWERQUAD peripheral base addresses */
+ #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE }
+ /** Array initializer of POWERQUAD peripheral base pointers */
+ #define POWERQUAD_BASE_PTRS { POWERQUAD }
+#endif
+/** Interrupt vectors for the POWERQUAD peripheral type */
+#define POWERQUAD_IRQS { POWERQUAD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group POWERQUAD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PUF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer
+ * @{
+ */
+
+/** PUF - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< PUF Control, offset: 0x0 */
+ __IO uint32_t KEYINDEX; /**< PUF Key Index, offset: 0x4 */
+ __IO uint32_t KEYSIZE; /**< PUF Key Size, offset: 0x8 */
+ uint8_t RESERVED_0[20];
+ __I uint32_t STAT; /**< PUF Status, offset: 0x20 */
+ uint8_t RESERVED_1[4];
+ __I uint32_t ALLOW; /**< PUF Allow, offset: 0x28 */
+ uint8_t RESERVED_2[20];
+ __O uint32_t KEYINPUT; /**< PUF Key Input, offset: 0x40 */
+ __O uint32_t CODEINPUT; /**< PUF Code Input, offset: 0x44 */
+ __I uint32_t CODEOUTPUT; /**< PUF Code Output, offset: 0x48 */
+ uint8_t RESERVED_3[20];
+ __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index, offset: 0x60 */
+ __I uint32_t KEYOUTPUT; /**< PUF Key Output, offset: 0x64 */
+ uint8_t RESERVED_4[116];
+ __IO uint32_t IFSTAT; /**< PUF Interface Status and Clear, offset: 0xDC */
+ uint8_t RESERVED_5[32];
+ __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */
+ __IO uint32_t INTSTAT; /**< PUF Interrupt Status, offset: 0x104 */
+ __IO uint32_t PWRCTRL; /**< PUF Power Control, offset: 0x108 */
+ __IO uint32_t CFG; /**< PUF Configuration, offset: 0x10C */
+ uint8_t RESERVED_6[240];
+ __IO uint32_t KEYLOCK; /**< Key Lock, offset: 0x200 */
+ __IO uint32_t KEYENABLE; /**< Key Enable, offset: 0x204 */
+ __O uint32_t KEYRESET; /**< Key Reset, offset: 0x208 */
+ __IO uint32_t IDXBLK_L; /**< Index Block Low, offset: 0x20C */
+ __IO uint32_t IDXBLK_H_DP; /**< Index Block High Duplicate, offset: 0x210 */
+ __O uint32_t KEYMASK[4]; /**< Key Mask 0..Key Mask 3, array offset: 0x214, array step: 0x4 */
+ uint8_t RESERVED_7[48];
+ __IO uint32_t IDXBLK_H; /**< Index Block High, offset: 0x254 */
+ __IO uint32_t IDXBLK_L_DP; /**< Index Block Low Duplicate, offset: 0x258 */
+} PUF_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PUF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PUF_Register_Masks PUF Register Masks
+ * @{
+ */
+
+/*! @name CTRL - PUF Control */
+/*! @{ */
+#define PUF_CTRL_ZEROIZE_MASK (0x1U)
+#define PUF_CTRL_ZEROIZE_SHIFT (0U)
+/*! ZEROIZE - Zeroize
+ */
+#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK)
+#define PUF_CTRL_ENROLL_MASK (0x2U)
+#define PUF_CTRL_ENROLL_SHIFT (1U)
+/*! ENROLL - Enroll
+ */
+#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK)
+#define PUF_CTRL_START_MASK (0x4U)
+#define PUF_CTRL_START_SHIFT (2U)
+/*! START - Start
+ */
+#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK)
+#define PUF_CTRL_GENERATEKEY_MASK (0x8U)
+#define PUF_CTRL_GENERATEKEY_SHIFT (3U)
+/*! GENERATEKEY - Set Intrinsic Key
+ */
+#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK)
+#define PUF_CTRL_SETKEY_MASK (0x10U)
+#define PUF_CTRL_SETKEY_SHIFT (4U)
+/*! SETKEY - Set Key
+ */
+#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK)
+#define PUF_CTRL_GETKEY_MASK (0x40U)
+#define PUF_CTRL_GETKEY_SHIFT (6U)
+/*! GETKEY - Get Key
+ */
+#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK)
+/*! @} */
+
+/*! @name KEYINDEX - PUF Key Index */
+/*! @{ */
+#define PUF_KEYINDEX_KEYIDX_MASK (0xFU)
+#define PUF_KEYINDEX_KEYIDX_SHIFT (0U)
+/*! KEYIDX - Key index for Set Key operations
+ */
+#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK)
+/*! @} */
+
+/*! @name KEYSIZE - PUF Key Size */
+/*! @{ */
+#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU)
+#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U)
+/*! KEYSIZE - Key Size for Set Key operations
+ */
+#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK)
+/*! @} */
+
+/*! @name STAT - PUF Status */
+/*! @{ */
+#define PUF_STAT_BUSY_MASK (0x1U)
+#define PUF_STAT_BUSY_SHIFT (0U)
+/*! BUSY - Busy
+ */
+#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK)
+#define PUF_STAT_SUCCESS_MASK (0x2U)
+#define PUF_STAT_SUCCESS_SHIFT (1U)
+/*! SUCCESS - Success
+ */
+#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK)
+#define PUF_STAT_ERROR_MASK (0x4U)
+#define PUF_STAT_ERROR_SHIFT (2U)
+/*! ERROR - Error
+ */
+#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK)
+#define PUF_STAT_KEYINREQ_MASK (0x10U)
+#define PUF_STAT_KEYINREQ_SHIFT (4U)
+/*! KEYINREQ - Key In Request
+ */
+#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK)
+#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U)
+#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U)
+/*! KEYOUTAVAIL - Key Out Available
+ */
+#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK)
+#define PUF_STAT_CODEINREQ_MASK (0x40U)
+#define PUF_STAT_CODEINREQ_SHIFT (6U)
+/*! CODEINREQ - Code In Request
+ */
+#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK)
+#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U)
+#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U)
+/*! CODEOUTAVAIL - Code Out Available
+ */
+#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK)
+/*! @} */
+
+/*! @name ALLOW - PUF Allow */
+/*! @{ */
+#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U)
+#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U)
+/*! ALLOWENROLL - Allow Enroll
+ */
+#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK)
+#define PUF_ALLOW_ALLOWSTART_MASK (0x2U)
+#define PUF_ALLOW_ALLOWSTART_SHIFT (1U)
+/*! ALLOWSTART - Allow Start
+ */
+#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK)
+#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U)
+#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U)
+/*! ALLOWSETKEY - Allow Set Key
+ */
+#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK)
+#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U)
+#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U)
+/*! ALLOWGETKEY - Allow Get Key
+ */
+#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK)
+/*! @} */
+
+/*! @name KEYINPUT - PUF Key Input */
+/*! @{ */
+#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU)
+#define PUF_KEYINPUT_KEYIN_SHIFT (0U)
+/*! KEYIN - Key Input Data
+ */
+#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK)
+/*! @} */
+
+/*! @name CODEINPUT - PUF Code Input */
+/*! @{ */
+#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU)
+#define PUF_CODEINPUT_CODEIN_SHIFT (0U)
+/*! CODEIN - AC/KC Input Data
+ */
+#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK)
+/*! @} */
+
+/*! @name CODEOUTPUT - PUF Code Output */
+/*! @{ */
+#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU)
+#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U)
+/*! CODEOUT - AC/KC Output Data
+ */
+#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK)
+/*! @} */
+
+/*! @name KEYOUTINDEX - PUF Key Output Index */
+/*! @{ */
+#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU)
+#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U)
+/*! KEYOUTIDX - Key Output Index
+ */
+#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK)
+/*! @} */
+
+/*! @name KEYOUTPUT - PUF Key Output */
+/*! @{ */
+#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU)
+#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U)
+/*! KEYOUT - Key Output Data
+ */
+#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK)
+/*! @} */
+
+/*! @name IFSTAT - PUF Interface Status and Clear */
+/*! @{ */
+#define PUF_IFSTAT_ERROR_MASK (0x1U)
+#define PUF_IFSTAT_ERROR_SHIFT (0U)
+/*! ERROR - Error
+ */
+#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK)
+/*! @} */
+
+/*! @name INTEN - PUF Interrupt Enable */
+/*! @{ */
+#define PUF_INTEN_READYEN_MASK (0x1U)
+#define PUF_INTEN_READYEN_SHIFT (0U)
+/*! READYEN - Enable corresponding interrupt in STAT, which indicates that the initialization or a operation is completed.
+ */
+#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK)
+#define PUF_INTEN_SUCCESEN_MASK (0x2U)
+#define PUF_INTEN_SUCCESEN_SHIFT (1U)
+/*! SUCCESEN - Enable corresponding interrupt in STAT, which indicates last operation was successful.
+ */
+#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK)
+#define PUF_INTEN_ERROREN_MASK (0x4U)
+#define PUF_INTEN_ERROREN_SHIFT (2U)
+/*! ERROREN - Enable corresponding interrupt in STAT, which indicates that PUF is in the error state
+ * and no operations can be performed.
+ */
+#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK)
+#define PUF_INTEN_KEYINREQEN_MASK (0x10U)
+#define PUF_INTEN_KEYINREQEN_SHIFT (4U)
+/*! KEYINREQEN - Enable corresponding interrupt in STAT, which is request for next part of key.
+ */
+#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK)
+#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U)
+#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U)
+/*! KEYOUTAVAILEN - Enable corresponding interrupt in STAT, which is next part of key is available.
+ */
+#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK)
+#define PUF_INTEN_CODEINREQEN_MASK (0x40U)
+#define PUF_INTEN_CODEINREQEN_SHIFT (6U)
+/*! CODEINREQEN - Enable corresponding interrupt in STAT, which is request for next part of AC/KC.
+ */
+#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK)
+#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U)
+#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U)
+/*! CODEOUTAVAILEN - Enable corresponding interrupt in STAT, which is next part of AC/KC is available.
+ */
+#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK)
+/*! @} */
+
+/*! @name INTSTAT - PUF Interrupt Status */
+/*! @{ */
+#define PUF_INTSTAT_READY_MASK (0x1U)
+#define PUF_INTSTAT_READY_SHIFT (0U)
+/*! READY - Ready
+ */
+#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK)
+#define PUF_INTSTAT_SUCCESS_MASK (0x2U)
+#define PUF_INTSTAT_SUCCESS_SHIFT (1U)
+/*! SUCCESS - Success
+ */
+#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK)
+#define PUF_INTSTAT_ERROR_MASK (0x4U)
+#define PUF_INTSTAT_ERROR_SHIFT (2U)
+/*! ERROR - Error
+ */
+#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK)
+#define PUF_INTSTAT_KEYINREQ_MASK (0x10U)
+#define PUF_INTSTAT_KEYINREQ_SHIFT (4U)
+/*! KEYINREQ - Key In Request
+ */
+#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK)
+#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U)
+#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U)
+/*! KEYOUTAVAIL - Key Out Available
+ */
+#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK)
+#define PUF_INTSTAT_CODEINREQ_MASK (0x40U)
+#define PUF_INTSTAT_CODEINREQ_SHIFT (6U)
+/*! CODEINREQ - Code In Request
+ */
+#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK)
+#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U)
+#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U)
+/*! CODEOUTAVAIL - Code Out Available
+ */
+#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK)
+/*! @} */
+
+/*! @name PWRCTRL - PUF Power Control */
+/*! @{ */
+#define PUF_PWRCTRL_RAM_ON_MASK (0x1U)
+#define PUF_PWRCTRL_RAM_ON_SHIFT (0U)
+/*! RAM_ON - RAM Power On
+ * 0b0..Power Off
+ * 0b1..Power On
+ */
+#define PUF_PWRCTRL_RAM_ON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_ON_SHIFT)) & PUF_PWRCTRL_RAM_ON_MASK)
+#define PUF_PWRCTRL_CK_DIS_MASK (0x4U)
+#define PUF_PWRCTRL_CK_DIS_SHIFT (2U)
+/*! CK_DIS - PUF RAM Clock Disable
+ * 0b0..PUF RAM clock is disabled.
+ * 0b1..PUF RAM clock is enabled.
+ */
+#define PUF_PWRCTRL_CK_DIS(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_CK_DIS_SHIFT)) & PUF_PWRCTRL_CK_DIS_MASK)
+/*! @} */
+
+/*! @name CFG - PUF Configuration */
+/*! @{ */
+#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U)
+#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U)
+/*! BLOCKENROLL_SETKEY - Block Enroll and Set Key Operation
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK)
+#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U)
+#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U)
+/*! BLOCKKEYOUTPUT - Block Key Output Data
+ * 0b0..Disabled. BLOCKKEYOUTPUT is cleared on reset.
+ * 0b1..Enabled
+ */
+#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK)
+/*! @} */
+
+/*! @name KEYLOCK - Key Lock */
+/*! @{ */
+#define PUF_KEYLOCK_KEY0_MASK (0x3U)
+#define PUF_KEYLOCK_KEY0_SHIFT (0U)
+/*! KEY0 - Key 0
+ * 0b00, 0b01, 0b11..Write access to KEY0MASK, KEYENABLE[KEY0] and KEYRESET[KEY0] is NOT allowed.
+ * 0b10..Write access to KEY0MASK, KEYENABLE[KEY0] and KEYRESET[KEY0] is allowed.
+ */
+#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK)
+#define PUF_KEYLOCK_KEY1_MASK (0xCU)
+#define PUF_KEYLOCK_KEY1_SHIFT (2U)
+/*! KEY1 - Key 1
+ * 0b00, 0b01, 0b11..Write access to KEY1MASK, KEYENABLE[KEY1] and KEYRESET[KEY1] is NOT allowed.
+ * 0b10..Write access to KEY1MASK, KEYENABLE[KEY1] and KEYRESET[KEY1] is allowed.
+ */
+#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK)
+#define PUF_KEYLOCK_KEY2_MASK (0x30U)
+#define PUF_KEYLOCK_KEY2_SHIFT (4U)
+/*! KEY2 - Key 2
+ * 0b00, 0b01, 0b11..Write access to KEY2MASK, KEYENABLE[KEY2] and KEYRESET[KEY2] is NOT allowed.
+ * 0b10..Write access to KEY2MASK, KEYENABLE[KEY2] and KEYRESET[KEY2] is allowed.
+ */
+#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK)
+#define PUF_KEYLOCK_KEY3_MASK (0xC0U)
+#define PUF_KEYLOCK_KEY3_SHIFT (6U)
+/*! KEY3 - Key 3
+ * 0b00, 0b01, 0b11..Write access to KEY3MASK, KEYENABLE[KEY3] and KEYRESET[KEY3] is NOT allowed.
+ * 0b10..Write access to KEY3MASK, KEYENABLE[KEY3] and KEYRESET[KEY3] is allowed.
+ */
+#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK)
+/*! @} */
+
+/*! @name KEYENABLE - Key Enable */
+/*! @{ */
+#define PUF_KEYENABLE_KEY0_MASK (0x3U)
+#define PUF_KEYENABLE_KEY0_SHIFT (0U)
+/*! KEY0 - Key 0
+ * 0b00, 0b01, 0b11..Disabled
+ * 0b10..Enabled
+ */
+#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK)
+#define PUF_KEYENABLE_KEY1_MASK (0xCU)
+#define PUF_KEYENABLE_KEY1_SHIFT (2U)
+/*! KEY1 - Key 1
+ * 0b00, 0b01, 0b11..Data coming from the PUF Index 0 interface are NOT shifted in the KEY1 register.
+ * 0b10..Data coming from the PUF Index 0 interface are shifted in the KEY1 register.
+ */
+#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK)
+#define PUF_KEYENABLE_KEY2_MASK (0x30U)
+#define PUF_KEYENABLE_KEY2_SHIFT (4U)
+/*! KEY2 - Key 2
+ * 0b00, 0b01, 0b11..Data coming from the PUF Index 0 interface are NOT shifted in the KEY2 register.
+ * 0b10..Data coming from the PUF Index 0 interface are shifted in the KEY2 register.
+ */
+#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK)
+#define PUF_KEYENABLE_KEY3_MASK (0xC0U)
+#define PUF_KEYENABLE_KEY3_SHIFT (6U)
+/*! KEY3 - Key 3
+ * 0b00, 0b01, 0b11..Data coming from the PUF Index 0 interface are NOT shifted in the KEY3 register.
+ * 0b10..Data coming from the PUF Index 0 interface are shifted in the KEY3 register.
+ */
+#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK)
+/*! @} */
+
+/*! @name KEYRESET - Key Reset */
+/*! @{ */
+#define PUF_KEYRESET_KEY0_MASK (0x3U)
+#define PUF_KEYRESET_KEY0_SHIFT (0U)
+/*! KEY0 - Key 0
+ * 0b10..Reset KEY0 Hold register and SHIFT_STATUS[KEY0].
+ */
+#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK)
+#define PUF_KEYRESET_KEY1_MASK (0xCU)
+#define PUF_KEYRESET_KEY1_SHIFT (2U)
+/*! KEY1 - Key 1
+ * 0b10..Reset KEY1 Hold register and SHIFT_STATUS[KEY1].
+ */
+#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK)
+#define PUF_KEYRESET_KEY2_MASK (0x30U)
+#define PUF_KEYRESET_KEY2_SHIFT (4U)
+/*! KEY2 - Key 2
+ * 0b10..Reset KEY2 Hold register and SHIFT_STATUS[KEY2].
+ */
+#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK)
+#define PUF_KEYRESET_KEY3_MASK (0xC0U)
+#define PUF_KEYRESET_KEY3_SHIFT (6U)
+/*! KEY3 - Key 3
+ * 0b10..Reset KEY3 Hold register and SHIFT_STATUS[KEY3].
+ */
+#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK)
+/*! @} */
+
+/*! @name IDXBLK_L - Index Block Low */
+/*! @{ */
+#define PUF_IDXBLK_L_IDX1_MASK (0xCU)
+#define PUF_IDXBLK_L_IDX1_SHIFT (2U)
+/*! IDX1 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK)
+#define PUF_IDXBLK_L_IDX2_MASK (0x30U)
+#define PUF_IDXBLK_L_IDX2_SHIFT (4U)
+/*! IDX2 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK)
+#define PUF_IDXBLK_L_IDX3_MASK (0xC0U)
+#define PUF_IDXBLK_L_IDX3_SHIFT (6U)
+/*! IDX3 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK)
+#define PUF_IDXBLK_L_IDX4_MASK (0x300U)
+#define PUF_IDXBLK_L_IDX4_SHIFT (8U)
+/*! IDX4 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK)
+#define PUF_IDXBLK_L_IDX5_MASK (0xC00U)
+#define PUF_IDXBLK_L_IDX5_SHIFT (10U)
+/*! IDX5 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK)
+#define PUF_IDXBLK_L_IDX6_MASK (0x3000U)
+#define PUF_IDXBLK_L_IDX6_SHIFT (12U)
+/*! IDX6 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK)
+#define PUF_IDXBLK_L_IDX7_MASK (0xC000U)
+#define PUF_IDXBLK_L_IDX7_SHIFT (14U)
+/*! IDX7 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK)
+#define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U)
+#define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U)
+/*! LOCK_IDX - Lock Index
+ */
+#define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK)
+/*! @} */
+
+/*! @name IDXBLK_H_DP - Index Block High Duplicate */
+/*! @{ */
+#define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U)
+#define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U)
+/*! IDX8 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK)
+#define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU)
+#define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U)
+/*! IDX9 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
+#define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U)
+#define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U)
+/*! IDX10 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK)
+#define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U)
+#define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U)
+/*! IDX11 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK)
+#define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U)
+#define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U)
+/*! IDX12 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK)
+#define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U)
+#define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U)
+/*! IDX13 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK)
+#define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U)
+#define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U)
+/*! IDX14 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK)
+#define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U)
+#define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U)
+/*! IDX15 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK)
+/*! @} */
+
+/*! @name KEYMASK - Key Mask 0..Key Mask 3 */
+/*! @{ */
+#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU)
+#define PUF_KEYMASK_KEYMASK_SHIFT (0U)
+/*! KEYMASK - Key a Mask
+ */
+#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK)
+/*! @} */
+
+/* The count of PUF_KEYMASK */
+#define PUF_KEYMASK_COUNT (4U)
+
+/*! @name IDXBLK_H - Index Block High */
+/*! @{ */
+#define PUF_IDXBLK_H_IDX8_MASK (0x3U)
+#define PUF_IDXBLK_H_IDX8_SHIFT (0U)
+/*! IDX8 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK)
+#define PUF_IDXBLK_H_IDX9_MASK (0xCU)
+#define PUF_IDXBLK_H_IDX9_SHIFT (2U)
+/*! IDX9 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK)
+#define PUF_IDXBLK_H_IDX10_MASK (0x30U)
+#define PUF_IDXBLK_H_IDX10_SHIFT (4U)
+/*! IDX10 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK)
+#define PUF_IDXBLK_H_IDX11_MASK (0xC0U)
+#define PUF_IDXBLK_H_IDX11_SHIFT (6U)
+/*! IDX11 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK)
+#define PUF_IDXBLK_H_IDX12_MASK (0x300U)
+#define PUF_IDXBLK_H_IDX12_SHIFT (8U)
+/*! IDX12 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK)
+#define PUF_IDXBLK_H_IDX13_MASK (0xC00U)
+#define PUF_IDXBLK_H_IDX13_SHIFT (10U)
+/*! IDX13 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK)
+#define PUF_IDXBLK_H_IDX14_MASK (0x3000U)
+#define PUF_IDXBLK_H_IDX14_SHIFT (12U)
+/*! IDX14 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK)
+#define PUF_IDXBLK_H_IDX15_MASK (0xC000U)
+#define PUF_IDXBLK_H_IDX15_SHIFT (14U)
+/*! IDX15 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK)
+#define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U)
+#define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U)
+/*! LOCK_IDX - Lock Index
+ */
+#define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK)
+/*! @} */
+
+/*! @name IDXBLK_L_DP - Index Block Low Duplicate */
+/*! @{ */
+#define PUF_IDXBLK_L_DP_IDX0_MASK (0x3U)
+#define PUF_IDXBLK_L_DP_IDX0_SHIFT (0U)
+/*! IDX0 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_L_DP_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX0_SHIFT)) & PUF_IDXBLK_L_DP_IDX0_MASK)
+#define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU)
+#define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U)
+/*! IDX1 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK)
+#define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U)
+#define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U)
+/*! IDX2 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK)
+#define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U)
+#define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U)
+/*! IDX3 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK)
+#define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U)
+#define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U)
+/*! IDX4 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK)
+#define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U)
+#define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U)
+/*! IDX5 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
+#define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U)
+#define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U)
+/*! IDX6 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK)
+#define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U)
+#define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U)
+/*! IDX7 - Index n
+ * 0b10..PUF index is accessible.
+ * 0b01..PUF index is blocked.
+ * 0b00, 0b11..Reserved
+ */
+#define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PUF_Register_Masks */
+
+
+/* PUF - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral PUF base address */
+ #define PUF_BASE (0x50006000u)
+ /** Peripheral PUF base address */
+ #define PUF_BASE_NS (0x40006000u)
+ /** Peripheral PUF base pointer */
+ #define PUF ((PUF_Type *)PUF_BASE)
+ /** Peripheral PUF base pointer */
+ #define PUF_NS ((PUF_Type *)PUF_BASE_NS)
+ /** Array initializer of PUF peripheral base addresses */
+ #define PUF_BASE_ADDRS { PUF_BASE }
+ /** Array initializer of PUF peripheral base pointers */
+ #define PUF_BASE_PTRS { PUF }
+ /** Array initializer of PUF peripheral base addresses */
+ #define PUF_BASE_ADDRS_NS { PUF_BASE_NS }
+ /** Array initializer of PUF peripheral base pointers */
+ #define PUF_BASE_PTRS_NS { PUF_NS }
+#else
+ /** Peripheral PUF base address */
+ #define PUF_BASE (0x40006000u)
+ /** Peripheral PUF base pointer */
+ #define PUF ((PUF_Type *)PUF_BASE)
+ /** Array initializer of PUF peripheral base addresses */
+ #define PUF_BASE_ADDRS { PUF_BASE }
+ /** Array initializer of PUF peripheral base pointers */
+ #define PUF_BASE_PTRS { PUF }
+#endif
+
+/*!
+ * @}
+ */ /* end of group PUF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RSTCTL0 Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RSTCTL0_Peripheral_Access_Layer RSTCTL0 Peripheral Access Layer
+ * @{
+ */
+
+/** RSTCTL0 - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SYSRSTSTAT; /**< System Reset Status Register, offset: 0x0 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t PRSTCTL0; /**< Peripheral Reset Control Register 0, offset: 0x10 */
+ __IO uint32_t PRSTCTL1; /**< Peripheral Reset Control Register 1, offset: 0x14 */
+ __IO uint32_t PRSTCTL2; /**< Peripheral Reset Control Register 2, offset: 0x18 */
+ uint8_t RESERVED_1[36];
+ __O uint32_t PRSTCTL0_SET; /**< Peripheral Reset Control Register 0 SET, offset: 0x40 */
+ __O uint32_t PRSTCTL1_SET; /**< Peripheral Reset Control Register 1 SET, offset: 0x44 */
+ __O uint32_t PRSTCTL2_SET; /**< Peripheral Reset Control Register 2 SET, offset: 0x48 */
+ uint8_t RESERVED_2[36];
+ __O uint32_t PRSTCTL0_CLR; /**< Peripheral Reset Control Register 0 CLR, offset: 0x70 */
+ __O uint32_t PRSTCTL1_CLR; /**< Peripheral Reset Control Register 1 CLR, offset: 0x74 */
+ __O uint32_t PRSTCTL2_CLR; /**< Peripheral Reset Control Register 2 CLR, offset: 0x78 */
+} RSTCTL0_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RSTCTL0 Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RSTCTL0_Register_Masks RSTCTL0 Register Masks
+ * @{
+ */
+
+/*! @name SYSRSTSTAT - System Reset Status Register */
+/*! @{ */
+#define RSTCTL0_SYSRSTSTAT_VDD_POR_MASK (0x1U)
+#define RSTCTL0_SYSRSTSTAT_VDD_POR_SHIFT (0U)
+/*! VDD_POR - VDD Power-On Reset (POR) was detected
+ * 0b0..No VDD POR event is detected
+ * 0b1..VDD POR event was detected
+ */
+#define RSTCTL0_SYSRSTSTAT_VDD_POR(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_SYSRSTSTAT_VDD_POR_SHIFT)) & RSTCTL0_SYSRSTSTAT_VDD_POR_MASK)
+#define RSTCTL0_SYSRSTSTAT_PAD_RESET_MASK (0x10U)
+#define RSTCTL0_SYSRSTSTAT_PAD_RESET_SHIFT (4U)
+/*! PAD_RESET - RESETN pin reset was detected
+ * 0b0..No RESETN pin event is detected
+ * 0b1..RESETN pin event was detected. Write '1' to clear this bit
+ */
+#define RSTCTL0_SYSRSTSTAT_PAD_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_SYSRSTSTAT_PAD_RESET_SHIFT)) & RSTCTL0_SYSRSTSTAT_PAD_RESET_MASK)
+#define RSTCTL0_SYSRSTSTAT_ARM_RESET_MASK (0x20U)
+#define RSTCTL0_SYSRSTSTAT_ARM_RESET_SHIFT (5U)
+/*! ARM_RESET - ARM reset was detected
+ * 0b0..No ARM reset event is detected
+ * 0b1..ARM reset was detected. Write '1' to clear this bit
+ */
+#define RSTCTL0_SYSRSTSTAT_ARM_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_SYSRSTSTAT_ARM_RESET_SHIFT)) & RSTCTL0_SYSRSTSTAT_ARM_RESET_MASK)
+#define RSTCTL0_SYSRSTSTAT_WDT0_RESET_MASK (0x40U)
+#define RSTCTL0_SYSRSTSTAT_WDT0_RESET_SHIFT (6U)
+/*! WDT0_RESET - WatchDog Timer 0 reset was detected
+ * 0b0..No WDT0 reset event detected
+ * 0b1..WDT0 reset event detected. Write '1' to clear this bit
+ */
+#define RSTCTL0_SYSRSTSTAT_WDT0_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_SYSRSTSTAT_WDT0_RESET_SHIFT)) & RSTCTL0_SYSRSTSTAT_WDT0_RESET_MASK)
+#define RSTCTL0_SYSRSTSTAT_WDT1_RESET_MASK (0x80U)
+#define RSTCTL0_SYSRSTSTAT_WDT1_RESET_SHIFT (7U)
+/*! WDT1_RESET - WatchDog Timer 1 reset was detected
+ * 0b0..No WDT1 reset event detected
+ * 0b1..WDT1 reset event detected. Write '1' to clear this bit
+ */
+#define RSTCTL0_SYSRSTSTAT_WDT1_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_SYSRSTSTAT_WDT1_RESET_SHIFT)) & RSTCTL0_SYSRSTSTAT_WDT1_RESET_MASK)
+/*! @} */
+
+/*! @name PRSTCTL0 - Peripheral Reset Control Register 0 */
+/*! @{ */
+#define RSTCTL0_PRSTCTL0_DSP_MASK (0x2U)
+#define RSTCTL0_PRSTCTL0_DSP_SHIFT (1U)
+/*! DSP - Fusion F1 DSP reset control
+ * 0b0..Clear Reset
+ * 0b1..Set Reset
+ */
+#define RSTCTL0_PRSTCTL0_DSP(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_DSP_SHIFT)) & RSTCTL0_PRSTCTL0_DSP_MASK)
+#define RSTCTL0_PRSTCTL0_AXI_SWITCH_MASK (0x8U)
+#define RSTCTL0_PRSTCTL0_AXI_SWITCH_SHIFT (3U)
+/*! AXI_SWITCH - AXI Switch reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_AXI_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_AXI_SWITCH_SHIFT)) & RSTCTL0_PRSTCTL0_AXI_SWITCH_MASK)
+#define RSTCTL0_PRSTCTL0_POWERQUAD_MASK (0x100U)
+#define RSTCTL0_PRSTCTL0_POWERQUAD_SHIFT (8U)
+/*! POWERQUAD - POWERQUAD reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_POWERQUAD_SHIFT)) & RSTCTL0_PRSTCTL0_POWERQUAD_MASK)
+#define RSTCTL0_PRSTCTL0_CASPER_MASK (0x200U)
+#define RSTCTL0_PRSTCTL0_CASPER_SHIFT (9U)
+/*! CASPER - CASPER reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_CASPER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CASPER_SHIFT)) & RSTCTL0_PRSTCTL0_CASPER_MASK)
+#define RSTCTL0_PRSTCTL0_HASHCRYPT_MASK (0x400U)
+#define RSTCTL0_PRSTCTL0_HASHCRYPT_SHIFT (10U)
+/*! HASHCRYPT - Hash-Crypt reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_HASHCRYPT(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_HASHCRYPT_SHIFT)) & RSTCTL0_PRSTCTL0_HASHCRYPT_MASK)
+#define RSTCTL0_PRSTCTL0_PUF_MASK (0x800U)
+#define RSTCTL0_PRSTCTL0_PUF_SHIFT (11U)
+/*! PUF - PUF reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_PUF(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_PUF_SHIFT)) & RSTCTL0_PRSTCTL0_PUF_MASK)
+#define RSTCTL0_PRSTCTL0_RNG_MASK (0x1000U)
+#define RSTCTL0_PRSTCTL0_RNG_SHIFT (12U)
+/*! RNG - RNG reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_RNG(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_RNG_SHIFT)) & RSTCTL0_PRSTCTL0_RNG_MASK)
+#define RSTCTL0_PRSTCTL0_FLEXSPI0_OTFAD_MASK (0x10000U)
+#define RSTCTL0_PRSTCTL0_FLEXSPI0_OTFAD_SHIFT (16U)
+/*! FLEXSPI0_OTFAD - FLEXSPI0 and OTFAD reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_FLEXSPI0_OTFAD(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_FLEXSPI0_OTFAD_SHIFT)) & RSTCTL0_PRSTCTL0_FLEXSPI0_OTFAD_MASK)
+#define RSTCTL0_PRSTCTL0_FLEXSPI1_MASK (0x40000U)
+#define RSTCTL0_PRSTCTL0_FLEXSPI1_SHIFT (18U)
+/*! FLEXSPI1 - FLEXSPI1 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_FLEXSPI1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_FLEXSPI1_SHIFT)) & RSTCTL0_PRSTCTL0_FLEXSPI1_MASK)
+#define RSTCTL0_PRSTCTL0_USBHS_PHY_MASK (0x100000U)
+#define RSTCTL0_PRSTCTL0_USBHS_PHY_SHIFT (20U)
+/*! USBHS_PHY - USB PHY reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_USBHS_PHY(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_USBHS_PHY_SHIFT)) & RSTCTL0_PRSTCTL0_USBHS_PHY_MASK)
+#define RSTCTL0_PRSTCTL0_USBHS_DEVICE_MASK (0x200000U)
+#define RSTCTL0_PRSTCTL0_USBHS_DEVICE_SHIFT (21U)
+/*! USBHS_DEVICE - USB HS Device reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_USBHS_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_USBHS_DEVICE_SHIFT)) & RSTCTL0_PRSTCTL0_USBHS_DEVICE_MASK)
+#define RSTCTL0_PRSTCTL0_USBHS_HOST_MASK (0x400000U)
+#define RSTCTL0_PRSTCTL0_USBHS_HOST_SHIFT (22U)
+/*! USBHS_HOST - USB HOST reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_USBHS_HOST(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_USBHS_HOST_SHIFT)) & RSTCTL0_PRSTCTL0_USBHS_HOST_MASK)
+#define RSTCTL0_PRSTCTL0_USBHS_SRAM_MASK (0x800000U)
+#define RSTCTL0_PRSTCTL0_USBHS_SRAM_SHIFT (23U)
+/*! USBHS_SRAM - USB RAM reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_USBHS_SRAM(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_USBHS_SRAM_SHIFT)) & RSTCTL0_PRSTCTL0_USBHS_SRAM_MASK)
+#define RSTCTL0_PRSTCTL0_SCT_MASK (0x1000000U)
+#define RSTCTL0_PRSTCTL0_SCT_SHIFT (24U)
+/*! SCT - SC Timer reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_SCT(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SCT_SHIFT)) & RSTCTL0_PRSTCTL0_SCT_MASK)
+#define RSTCTL0_PRSTCTL0_GPU_MASK (0x4000000U)
+#define RSTCTL0_PRSTCTL0_GPU_SHIFT (26U)
+/*! GPU - GPU reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_GPU(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_GPU_SHIFT)) & RSTCTL0_PRSTCTL0_GPU_MASK)
+#define RSTCTL0_PRSTCTL0_DISPLAY_CONTROLLER_MASK (0x8000000U)
+#define RSTCTL0_PRSTCTL0_DISPLAY_CONTROLLER_SHIFT (27U)
+/*! DISPLAY_CONTROLLER - LCDIF Display Controller reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_DISPLAY_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_DISPLAY_CONTROLLER_SHIFT)) & RSTCTL0_PRSTCTL0_DISPLAY_CONTROLLER_MASK)
+#define RSTCTL0_PRSTCTL0_MIPI_DSI_CONTROLLER_MASK (0x10000000U)
+#define RSTCTL0_PRSTCTL0_MIPI_DSI_CONTROLLER_SHIFT (28U)
+/*! MIPI_DSI_CONTROLLER - MIPI Digital serial Interface controller reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_MIPI_DSI_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_MIPI_DSI_CONTROLLER_SHIFT)) & RSTCTL0_PRSTCTL0_MIPI_DSI_CONTROLLER_MASK)
+#define RSTCTL0_PRSTCTL0_MIPI_DSI_PHY_MASK (0x20000000U)
+#define RSTCTL0_PRSTCTL0_MIPI_DSI_PHY_SHIFT (29U)
+/*! MIPI_DSI_PHY - MIPI DSI PHY reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_MIPI_DSI_PHY(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_MIPI_DSI_PHY_SHIFT)) & RSTCTL0_PRSTCTL0_MIPI_DSI_PHY_MASK)
+#define RSTCTL0_PRSTCTL0_SMARTDMA_MASK (0x40000000U)
+#define RSTCTL0_PRSTCTL0_SMARTDMA_SHIFT (30U)
+/*! SMARTDMA - SMARTDMA Event/Algorithm handler reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL0_PRSTCTL0_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SMARTDMA_SHIFT)) & RSTCTL0_PRSTCTL0_SMARTDMA_MASK)
+/*! @} */
+
+/*! @name PRSTCTL1 - Peripheral Reset Control Register 1 */
+/*! @{ */
+#define RSTCTL0_PRSTCTL1_SDIO0_MASK (0x4U)
+#define RSTCTL0_PRSTCTL1_SDIO0_SHIFT (2U)
+/*! SDIO0 - SDIO0 reset control
+ * 0b0..Clear Reset
+ * 0b1..Set Reset
+ */
+#define RSTCTL0_PRSTCTL1_SDIO0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SDIO0_SHIFT)) & RSTCTL0_PRSTCTL1_SDIO0_MASK)
+#define RSTCTL0_PRSTCTL1_SDIO1_MASK (0x8U)
+#define RSTCTL0_PRSTCTL1_SDIO1_SHIFT (3U)
+/*! SDIO1 - SDIO1 reset control
+ * 0b0..Clear Reset
+ * 0b1..Set Reset
+ */
+#define RSTCTL0_PRSTCTL1_SDIO1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SDIO1_SHIFT)) & RSTCTL0_PRSTCTL1_SDIO1_MASK)
+#define RSTCTL0_PRSTCTL1_ACMP0_MASK (0x8000U)
+#define RSTCTL0_PRSTCTL1_ACMP0_SHIFT (15U)
+/*! ACMP0
+ * 0b0..Clear Reset
+ * 0b1..Set Reset
+ */
+#define RSTCTL0_PRSTCTL1_ACMP0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_ACMP0_SHIFT)) & RSTCTL0_PRSTCTL1_ACMP0_MASK)
+#define RSTCTL0_PRSTCTL1_ADC0_MASK (0x10000U)
+#define RSTCTL0_PRSTCTL1_ADC0_SHIFT (16U)
+/*! ADC0
+ * 0b0..Clear Reset
+ * 0b1..Set Reset
+ */
+#define RSTCTL0_PRSTCTL1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_ADC0_SHIFT)) & RSTCTL0_PRSTCTL1_ADC0_MASK)
+#define RSTCTL0_PRSTCTL1_SHSGPIO0_MASK (0x1000000U)
+#define RSTCTL0_PRSTCTL1_SHSGPIO0_SHIFT (24U)
+/*! SHSGPIO0 - Secure GPIO 0 reset control
+ * 0b0..Clear Reset
+ * 0b1..Set Reset
+ */
+#define RSTCTL0_PRSTCTL1_SHSGPIO0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SHSGPIO0_SHIFT)) & RSTCTL0_PRSTCTL1_SHSGPIO0_MASK)
+/*! @} */
+
+/*! @name PRSTCTL2 - Peripheral Reset Control Register 2 */
+/*! @{ */
+#define RSTCTL0_PRSTCTL2_UTICK0_MASK (0x1U)
+#define RSTCTL0_PRSTCTL2_UTICK0_SHIFT (0U)
+/*! UTICK0 - Micro-tick timer reset control
+ * 0b0..Clear Reset
+ * 0b1..Set Reset
+ */
+#define RSTCTL0_PRSTCTL2_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_UTICK0_SHIFT)) & RSTCTL0_PRSTCTL2_UTICK0_MASK)
+#define RSTCTL0_PRSTCTL2_WWDT0_MASK (0x2U)
+#define RSTCTL0_PRSTCTL2_WWDT0_SHIFT (1U)
+/*! WWDT0 - Watchdog timer reset control
+ * 0b0..Clear Reset
+ * 0b1..Set Reset
+ */
+#define RSTCTL0_PRSTCTL2_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_WWDT0_SHIFT)) & RSTCTL0_PRSTCTL2_WWDT0_MASK)
+/*! @} */
+
+/*! @name PRSTCTL0_SET - Peripheral Reset Control Register 0 SET */
+/*! @{ */
+#define RSTCTL0_PRSTCTL0_SET_DSP_MASK (0x2U)
+#define RSTCTL0_PRSTCTL0_SET_DSP_SHIFT (1U)
+/*! DSP - Fusion_ DSP reset set
+ * 0b0..No Effect
+ * 0b1..Sets the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_SET_DSP(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_DSP_SHIFT)) & RSTCTL0_PRSTCTL0_SET_DSP_MASK)
+#define RSTCTL0_PRSTCTL0_SET_AXI_SWITCH_MASK (0x8U)
+#define RSTCTL0_PRSTCTL0_SET_AXI_SWITCH_SHIFT (3U)
+/*! AXI_SWITCH - AXI SWITCH reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_AXI_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_AXI_SWITCH_SHIFT)) & RSTCTL0_PRSTCTL0_SET_AXI_SWITCH_MASK)
+#define RSTCTL0_PRSTCTL0_SET_POWERQUAD_MASK (0x100U)
+#define RSTCTL0_PRSTCTL0_SET_POWERQUAD_SHIFT (8U)
+/*! POWERQUAD - POWERQUAD reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_POWERQUAD_SHIFT)) & RSTCTL0_PRSTCTL0_SET_POWERQUAD_MASK)
+#define RSTCTL0_PRSTCTL0_SET_CASPER_MASK (0x200U)
+#define RSTCTL0_PRSTCTL0_SET_CASPER_SHIFT (9U)
+/*! CASPER - CASPER reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_CASPER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_CASPER_SHIFT)) & RSTCTL0_PRSTCTL0_SET_CASPER_MASK)
+#define RSTCTL0_PRSTCTL0_SET_HASHCRYPT_MASK (0x400U)
+#define RSTCTL0_PRSTCTL0_SET_HASHCRYPT_SHIFT (10U)
+/*! HASHCRYPT - HASHCRYPT reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_HASHCRYPT(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_HASHCRYPT_SHIFT)) & RSTCTL0_PRSTCTL0_SET_HASHCRYPT_MASK)
+#define RSTCTL0_PRSTCTL0_SET_PUF_MASK (0x800U)
+#define RSTCTL0_PRSTCTL0_SET_PUF_SHIFT (11U)
+/*! PUF - PUF reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_PUF(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_PUF_SHIFT)) & RSTCTL0_PRSTCTL0_SET_PUF_MASK)
+#define RSTCTL0_PRSTCTL0_SET_RNG_MASK (0x1000U)
+#define RSTCTL0_PRSTCTL0_SET_RNG_SHIFT (12U)
+/*! RNG - RNG reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_RNG(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_RNG_SHIFT)) & RSTCTL0_PRSTCTL0_SET_RNG_MASK)
+#define RSTCTL0_PRSTCTL0_SET_FLEXSPI0_OTFAD_MASK (0x10000U)
+#define RSTCTL0_PRSTCTL0_SET_FLEXSPI0_OTFAD_SHIFT (16U)
+/*! FLEXSPI0_OTFAD - FLEXSPI0 and OTFAD reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_FLEXSPI0_OTFAD(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_FLEXSPI0_OTFAD_SHIFT)) & RSTCTL0_PRSTCTL0_SET_FLEXSPI0_OTFAD_MASK)
+#define RSTCTL0_PRSTCTL0_SET_FLEXSPI1_MASK (0x40000U)
+#define RSTCTL0_PRSTCTL0_SET_FLEXSPI1_SHIFT (18U)
+/*! FLEXSPI1 - FLEXSPI1 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_FLEXSPI1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_FLEXSPI1_SHIFT)) & RSTCTL0_PRSTCTL0_SET_FLEXSPI1_MASK)
+#define RSTCTL0_PRSTCTL0_SET_USBHS_PHY_MASK (0x100000U)
+#define RSTCTL0_PRSTCTL0_SET_USBHS_PHY_SHIFT (20U)
+/*! USBHS_PHY - USB PHY reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_USBHS_PHY(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_USBHS_PHY_SHIFT)) & RSTCTL0_PRSTCTL0_SET_USBHS_PHY_MASK)
+#define RSTCTL0_PRSTCTL0_SET_USBHS_DEVICE_MASK (0x200000U)
+#define RSTCTL0_PRSTCTL0_SET_USBHS_DEVICE_SHIFT (21U)
+/*! USBHS_DEVICE - USB Device reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_USBHS_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_USBHS_DEVICE_SHIFT)) & RSTCTL0_PRSTCTL0_SET_USBHS_DEVICE_MASK)
+#define RSTCTL0_PRSTCTL0_SET_USBHS_HOST_MASK (0x400000U)
+#define RSTCTL0_PRSTCTL0_SET_USBHS_HOST_SHIFT (22U)
+/*! USBHS_HOST - USB HOST reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_USBHS_HOST(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_USBHS_HOST_SHIFT)) & RSTCTL0_PRSTCTL0_SET_USBHS_HOST_MASK)
+#define RSTCTL0_PRSTCTL0_SET_USBHS_SRAM_MASK (0x800000U)
+#define RSTCTL0_PRSTCTL0_SET_USBHS_SRAM_SHIFT (23U)
+/*! USBHS_SRAM - USBHS SRAM reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_USBHS_SRAM(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_USBHS_SRAM_SHIFT)) & RSTCTL0_PRSTCTL0_SET_USBHS_SRAM_MASK)
+#define RSTCTL0_PRSTCTL0_SET_SCT_MASK (0x1000000U)
+#define RSTCTL0_PRSTCTL0_SET_SCT_SHIFT (24U)
+/*! SCT - SC Timer reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_SCT(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_SCT_SHIFT)) & RSTCTL0_PRSTCTL0_SET_SCT_MASK)
+#define RSTCTL0_PRSTCTL0_SET_GPU_MASK (0x4000000U)
+#define RSTCTL0_PRSTCTL0_SET_GPU_SHIFT (26U)
+/*! GPU - GPU reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_GPU(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_GPU_SHIFT)) & RSTCTL0_PRSTCTL0_SET_GPU_MASK)
+#define RSTCTL0_PRSTCTL0_SET_DISPLAY_CONTROLLER_MASK (0x8000000U)
+#define RSTCTL0_PRSTCTL0_SET_DISPLAY_CONTROLLER_SHIFT (27U)
+/*! DISPLAY_CONTROLLER - LCDIF DISPLAY CONTROLLER reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_DISPLAY_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_DISPLAY_CONTROLLER_SHIFT)) & RSTCTL0_PRSTCTL0_SET_DISPLAY_CONTROLLER_MASK)
+#define RSTCTL0_PRSTCTL0_SET_MIPI_DSI_CONTROLLER_MASK (0x10000000U)
+#define RSTCTL0_PRSTCTL0_SET_MIPI_DSI_CONTROLLER_SHIFT (28U)
+/*! MIPI_DSI_CONTROLLER - MIPI DSI controller reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_MIPI_DSI_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_MIPI_DSI_CONTROLLER_SHIFT)) & RSTCTL0_PRSTCTL0_SET_MIPI_DSI_CONTROLLER_MASK)
+#define RSTCTL0_PRSTCTL0_SET_MIPI_DSI_PHY_MASK (0x20000000U)
+#define RSTCTL0_PRSTCTL0_SET_MIPI_DSI_PHY_SHIFT (29U)
+/*! MIPI_DSI_PHY - MIPI DSI PHY reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_MIPI_DSI_PHY(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_MIPI_DSI_PHY_SHIFT)) & RSTCTL0_PRSTCTL0_SET_MIPI_DSI_PHY_MASK)
+#define RSTCTL0_PRSTCTL0_SET_SMARTDMA_MASK (0x40000000U)
+#define RSTCTL0_PRSTCTL0_SET_SMARTDMA_SHIFT (30U)
+/*! SMARTDMA - SMARTDMA Event/Algorithm handler reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL0_PRSTCTL0_SET_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_SMARTDMA_SHIFT)) & RSTCTL0_PRSTCTL0_SET_SMARTDMA_MASK)
+/*! @} */
+
+/*! @name PRSTCTL1_SET - Peripheral Reset Control Register 1 SET */
+/*! @{ */
+#define RSTCTL0_PRSTCTL1_SET_SDIO0_MASK (0x4U)
+#define RSTCTL0_PRSTCTL1_SET_SDIO0_SHIFT (2U)
+/*! SDIO0 - SDIO0 reset set
+ * 0b0..No effect
+ * 0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_SET_SDIO0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_SDIO0_SHIFT)) & RSTCTL0_PRSTCTL1_SET_SDIO0_MASK)
+#define RSTCTL0_PRSTCTL1_SET_SDIO1_MASK (0x8U)
+#define RSTCTL0_PRSTCTL1_SET_SDIO1_SHIFT (3U)
+/*! SDIO1 - SDIO1 reset set
+ * 0b0..No effect
+ * 0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_SET_SDIO1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_SDIO1_SHIFT)) & RSTCTL0_PRSTCTL1_SET_SDIO1_MASK)
+#define RSTCTL0_PRSTCTL1_SET_ACMP0_MASK (0x8000U)
+#define RSTCTL0_PRSTCTL1_SET_ACMP0_SHIFT (15U)
+/*! ACMP0 - ACMP0 reset set
+ * 0b0..No effect
+ * 0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_SET_ACMP0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_ACMP0_SHIFT)) & RSTCTL0_PRSTCTL1_SET_ACMP0_MASK)
+#define RSTCTL0_PRSTCTL1_SET_ADC0_MASK (0x10000U)
+#define RSTCTL0_PRSTCTL1_SET_ADC0_SHIFT (16U)
+/*! ADC0 - ADC0 reset set
+ * 0b0..No effect
+ * 0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_SET_ADC0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_ADC0_SHIFT)) & RSTCTL0_PRSTCTL1_SET_ADC0_MASK)
+#define RSTCTL0_PRSTCTL1_SET_SHSGPIO0_MASK (0x1000000U)
+#define RSTCTL0_PRSTCTL1_SET_SHSGPIO0_SHIFT (24U)
+/*! SHSGPIO0 - SHSGPIO0 reset set
+ * 0b0..No effect
+ * 0b1..Sets the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_SET_SHSGPIO0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_SHSGPIO0_SHIFT)) & RSTCTL0_PRSTCTL1_SET_SHSGPIO0_MASK)
+/*! @} */
+
+/*! @name PRSTCTL2_SET - Peripheral Reset Control Register 2 SET */
+/*! @{ */
+#define RSTCTL0_PRSTCTL2_SET_UTICK0_MASK (0x1U)
+#define RSTCTL0_PRSTCTL2_SET_UTICK0_SHIFT (0U)
+/*! UTICK0 - Micro-tick timer 0 reset set
+ * 0b0..No effect
+ * 0b1..Sets the PRSTCTL2 Bit
+ */
+#define RSTCTL0_PRSTCTL2_SET_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_UTICK0_SHIFT)) & RSTCTL0_PRSTCTL2_SET_UTICK0_MASK)
+#define RSTCTL0_PRSTCTL2_SET_WWDT0_MASK (0x2U)
+#define RSTCTL0_PRSTCTL2_SET_WWDT0_SHIFT (1U)
+/*! WWDT0 - WWDT0 reset set
+ * 0b0..No effect
+ * 0b1..Sets the PRSTCTL2 Bit
+ */
+#define RSTCTL0_PRSTCTL2_SET_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_WWDT0_SHIFT)) & RSTCTL0_PRSTCTL2_SET_WWDT0_MASK)
+/*! @} */
+
+/*! @name PRSTCTL0_CLR - Peripheral Reset Control Register 0 CLR */
+/*! @{ */
+#define RSTCTL0_PRSTCTL0_CLR_DSP_MASK (0x2U)
+#define RSTCTL0_PRSTCTL0_CLR_DSP_SHIFT (1U)
+/*! DSP
+ * 0b0..No effect
+ * 0b1..Clears the PRSTCTL0 Bit
+ */
+#define RSTCTL0_PRSTCTL0_CLR_DSP(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_DSP_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_DSP_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_AXI_SWITCH_MASK (0x8U)
+#define RSTCTL0_PRSTCTL0_CLR_AXI_SWITCH_SHIFT (3U)
+/*! AXI_SWITCH - AXI SWITCH reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_AXI_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_AXI_SWITCH_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_AXI_SWITCH_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_POWERQUAD_MASK (0x100U)
+#define RSTCTL0_PRSTCTL0_CLR_POWERQUAD_SHIFT (8U)
+/*! POWERQUAD - POWERQUAD reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_POWERQUAD_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_POWERQUAD_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_CASPER_MASK (0x200U)
+#define RSTCTL0_PRSTCTL0_CLR_CASPER_SHIFT (9U)
+/*! CASPER - CASPER reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_CASPER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_CASPER_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_CASPER_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_HASHCRYPT_MASK (0x400U)
+#define RSTCTL0_PRSTCTL0_CLR_HASHCRYPT_SHIFT (10U)
+/*! HASHCRYPT - HASHCRYPT reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_HASHCRYPT(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_HASHCRYPT_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_HASHCRYPT_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_PUF_MASK (0x800U)
+#define RSTCTL0_PRSTCTL0_CLR_PUF_SHIFT (11U)
+/*! PUF - PUF reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_PUF(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_PUF_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_PUF_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_RNG_MASK (0x1000U)
+#define RSTCTL0_PRSTCTL0_CLR_RNG_SHIFT (12U)
+/*! RNG - RNG reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_RNG(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_RNG_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_RNG_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_FLEXSPI0_OTFAD_MASK (0x10000U)
+#define RSTCTL0_PRSTCTL0_CLR_FLEXSPI0_OTFAD_SHIFT (16U)
+/*! FLEXSPI0_OTFAD - FLEXSPI0 and OTFAD reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_FLEXSPI0_OTFAD(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_FLEXSPI0_OTFAD_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_FLEXSPI0_OTFAD_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_FLEXSPI1_MASK (0x40000U)
+#define RSTCTL0_PRSTCTL0_CLR_FLEXSPI1_SHIFT (18U)
+/*! FLEXSPI1 - FLEXSPI1 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_FLEXSPI1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_FLEXSPI1_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_FLEXSPI1_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_USBHS_PHY_MASK (0x100000U)
+#define RSTCTL0_PRSTCTL0_CLR_USBHS_PHY_SHIFT (20U)
+/*! USBHS_PHY - USB PHY reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_USBHS_PHY(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_USBHS_PHY_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_USBHS_PHY_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_USBHS_DEVICE_MASK (0x200000U)
+#define RSTCTL0_PRSTCTL0_CLR_USBHS_DEVICE_SHIFT (21U)
+/*! USBHS_DEVICE - USB DEVICE reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_USBHS_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_USBHS_DEVICE_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_USBHS_DEVICE_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_USBHS_HOST_MASK (0x400000U)
+#define RSTCTL0_PRSTCTL0_CLR_USBHS_HOST_SHIFT (22U)
+/*! USBHS_HOST - USB HOST reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_USBHS_HOST(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_USBHS_HOST_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_USBHS_HOST_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_USBHS_SRAM_MASK (0x800000U)
+#define RSTCTL0_PRSTCTL0_CLR_USBHS_SRAM_SHIFT (23U)
+/*! USBHS_SRAM - USBHS SRAM reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_USBHS_SRAM(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_USBHS_SRAM_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_USBHS_SRAM_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_SCT_MASK (0x1000000U)
+#define RSTCTL0_PRSTCTL0_CLR_SCT_SHIFT (24U)
+/*! SCT - SCT reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_SCT(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_SCT_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_SCT_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_GPU_MASK (0x4000000U)
+#define RSTCTL0_PRSTCTL0_CLR_GPU_SHIFT (26U)
+/*! GPU - GPU reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_GPU(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_GPU_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_GPU_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_DISPLAY_CONTROLLER_MASK (0x8000000U)
+#define RSTCTL0_PRSTCTL0_CLR_DISPLAY_CONTROLLER_SHIFT (27U)
+/*! DISPLAY_CONTROLLER - LCDIF DISPLAY CONTROLLER reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_DISPLAY_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_DISPLAY_CONTROLLER_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_DISPLAY_CONTROLLER_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_CONTROLLER_MASK (0x10000000U)
+#define RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_CONTROLLER_SHIFT (28U)
+/*! MIPI_DSI_CONTROLLER - MIPI DSI controller reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_CONTROLLER_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_CONTROLLER_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_PHY_MASK (0x20000000U)
+#define RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_PHY_SHIFT (29U)
+/*! MIPI_DSI_PHY - MIPI DSI PHY reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_PHY(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_PHY_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_PHY_MASK)
+#define RSTCTL0_PRSTCTL0_CLR_SMARTDMA_MASK (0x40000000U)
+#define RSTCTL0_PRSTCTL0_CLR_SMARTDMA_SHIFT (30U)
+/*! SMARTDMA - SMARTDMA Event/Algorithm handler reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL0_PRSTCTL0_CLR_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_SMARTDMA_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_SMARTDMA_MASK)
+/*! @} */
+
+/*! @name PRSTCTL1_CLR - Peripheral Reset Control Register 1 CLR */
+/*! @{ */
+#define RSTCTL0_PRSTCTL1_CLR_SDIO0_MASK (0x4U)
+#define RSTCTL0_PRSTCTL1_CLR_SDIO0_SHIFT (2U)
+/*! SDIO0 - SDIO0 reset clear
+ * 0b0..No effect
+ * 0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_CLR_SDIO0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_SDIO0_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_SDIO0_MASK)
+#define RSTCTL0_PRSTCTL1_CLR_SDIO1_MASK (0x8U)
+#define RSTCTL0_PRSTCTL1_CLR_SDIO1_SHIFT (3U)
+/*! SDIO1 - SDIO1 reset clear
+ * 0b0..No effect
+ * 0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_CLR_SDIO1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_SDIO1_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_SDIO1_MASK)
+#define RSTCTL0_PRSTCTL1_CLR_ACMP0_MASK (0x8000U)
+#define RSTCTL0_PRSTCTL1_CLR_ACMP0_SHIFT (15U)
+/*! ACMP0 - ACMP0 reset clear
+ * 0b0..No effect
+ * 0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_CLR_ACMP0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ACMP0_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ACMP0_MASK)
+#define RSTCTL0_PRSTCTL1_CLR_ADC0_MASK (0x10000U)
+#define RSTCTL0_PRSTCTL1_CLR_ADC0_SHIFT (16U)
+/*! ADC0 - ADC0 reset clear
+ * 0b0..No effect
+ * 0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_CLR_ADC0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ADC0_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ADC0_MASK)
+#define RSTCTL0_PRSTCTL1_CLR_SHSGPIO0_MASK (0x1000000U)
+#define RSTCTL0_PRSTCTL1_CLR_SHSGPIO0_SHIFT (24U)
+/*! SHSGPIO0 - Secure HSGPIO0 reset clear
+ * 0b0..No effect
+ * 0b1..Clears the PRSTCTL1 Bit
+ */
+#define RSTCTL0_PRSTCTL1_CLR_SHSGPIO0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_SHSGPIO0_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_SHSGPIO0_MASK)
+/*! @} */
+
+/*! @name PRSTCTL2_CLR - Peripheral Reset Control Register 2 CLR */
+/*! @{ */
+#define RSTCTL0_PRSTCTL2_CLR_UTICK0_MASK (0x1U)
+#define RSTCTL0_PRSTCTL2_CLR_UTICK0_SHIFT (0U)
+/*! UTICK0 - Micro-tick timer 0 reset clear
+ * 0b0..No effect
+ * 0b1..Clears the PRSTCTL2 Bit
+ */
+#define RSTCTL0_PRSTCTL2_CLR_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_UTICK0_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_UTICK0_MASK)
+#define RSTCTL0_PRSTCTL2_CLR_WWDT0_MASK (0x2U)
+#define RSTCTL0_PRSTCTL2_CLR_WWDT0_SHIFT (1U)
+/*! WWDT0 - WWDT0 reset clear
+ * 0b0..No effect
+ * 0b1..Clears the PRSTCTL2 Bit
+ */
+#define RSTCTL0_PRSTCTL2_CLR_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_WWDT0_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_WWDT0_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RSTCTL0_Register_Masks */
+
+
+/* RSTCTL0 - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral RSTCTL0 base address */
+ #define RSTCTL0_BASE (0x50000000u)
+ /** Peripheral RSTCTL0 base address */
+ #define RSTCTL0_BASE_NS (0x40000000u)
+ /** Peripheral RSTCTL0 base pointer */
+ #define RSTCTL0 ((RSTCTL0_Type *)RSTCTL0_BASE)
+ /** Peripheral RSTCTL0 base pointer */
+ #define RSTCTL0_NS ((RSTCTL0_Type *)RSTCTL0_BASE_NS)
+ /** Array initializer of RSTCTL0 peripheral base addresses */
+ #define RSTCTL0_BASE_ADDRS { RSTCTL0_BASE }
+ /** Array initializer of RSTCTL0 peripheral base pointers */
+ #define RSTCTL0_BASE_PTRS { RSTCTL0 }
+ /** Array initializer of RSTCTL0 peripheral base addresses */
+ #define RSTCTL0_BASE_ADDRS_NS { RSTCTL0_BASE_NS }
+ /** Array initializer of RSTCTL0 peripheral base pointers */
+ #define RSTCTL0_BASE_PTRS_NS { RSTCTL0_NS }
+#else
+ /** Peripheral RSTCTL0 base address */
+ #define RSTCTL0_BASE (0x40000000u)
+ /** Peripheral RSTCTL0 base pointer */
+ #define RSTCTL0 ((RSTCTL0_Type *)RSTCTL0_BASE)
+ /** Array initializer of RSTCTL0 peripheral base addresses */
+ #define RSTCTL0_BASE_ADDRS { RSTCTL0_BASE }
+ /** Array initializer of RSTCTL0 peripheral base pointers */
+ #define RSTCTL0_BASE_PTRS { RSTCTL0 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group RSTCTL0_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RSTCTL1 Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RSTCTL1_Peripheral_Access_Layer RSTCTL1 Peripheral Access Layer
+ * @{
+ */
+
+/** RSTCTL1 - Register Layout Typedef */
+typedef struct {
+ __I uint32_t SYSRSTSTAT; /**< System Reset Status Register, offset: 0x0 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t PRSTCTL0; /**< Peripheral Reset Control Register 0, offset: 0x10 */
+ __IO uint32_t PRSTCTL1; /**< Peripheral Reset Control Register 1, offset: 0x14 */
+ __IO uint32_t PRSTCTL2; /**< Peripheral Reset Control Register 2, offset: 0x18 */
+ uint8_t RESERVED_1[36];
+ __O uint32_t PRSTCTL0_SET; /**< Peripheral Reset Control Register 0 SET, offset: 0x40 */
+ __O uint32_t PRSTCTL1_SET; /**< Peripheral Reset Control Register 1 SET, offset: 0x44 */
+ __O uint32_t PRSTCTL2_SET; /**< Peripheral Reset Control Register 2 SET, offset: 0x48 */
+ uint8_t RESERVED_2[36];
+ __O uint32_t PRSTCTL0_CLR; /**< Peripheral Reset Control Register 0 CLR, offset: 0x70 */
+ __O uint32_t PRSTCTL1_CLR; /**< Peripheral Reset Control Register 1 CLR, offset: 0x74 */
+ __O uint32_t PRSTCTL2_CLR; /**< Peripheral Reset Control Register 2 CLR, offset: 0x78 */
+} RSTCTL1_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RSTCTL1 Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RSTCTL1_Register_Masks RSTCTL1 Register Masks
+ * @{
+ */
+
+/*! @name SYSRSTSTAT - System Reset Status Register */
+/*! @{ */
+#define RSTCTL1_SYSRSTSTAT_VDD_POR_MASK (0x1U)
+#define RSTCTL1_SYSRSTSTAT_VDD_POR_SHIFT (0U)
+/*! VDD_POR - VDD Power-On Reset (POR) was detected
+ * 0b0..No VDD POR event is detected
+ * 0b1..VDD POR event was detected
+ */
+#define RSTCTL1_SYSRSTSTAT_VDD_POR(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_SYSRSTSTAT_VDD_POR_SHIFT)) & RSTCTL1_SYSRSTSTAT_VDD_POR_MASK)
+#define RSTCTL1_SYSRSTSTAT_PAD_RESET_MASK (0x10U)
+#define RSTCTL1_SYSRSTSTAT_PAD_RESET_SHIFT (4U)
+/*! PAD_RESET - RESETN pin reset was detected
+ * 0b0..No RESETN pin event is detected
+ * 0b1..RESETN pin reset event was detected
+ */
+#define RSTCTL1_SYSRSTSTAT_PAD_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_SYSRSTSTAT_PAD_RESET_SHIFT)) & RSTCTL1_SYSRSTSTAT_PAD_RESET_MASK)
+#define RSTCTL1_SYSRSTSTAT_ARM_RESET_MASK (0x20U)
+#define RSTCTL1_SYSRSTSTAT_ARM_RESET_SHIFT (5U)
+/*! ARM_RESET - ARM reset was detected
+ * 0b0..No ARM reset event is detected
+ * 0b1..ARM reset was detected
+ */
+#define RSTCTL1_SYSRSTSTAT_ARM_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_SYSRSTSTAT_ARM_RESET_SHIFT)) & RSTCTL1_SYSRSTSTAT_ARM_RESET_MASK)
+#define RSTCTL1_SYSRSTSTAT_WDT0_RESET_MASK (0x40U)
+#define RSTCTL1_SYSRSTSTAT_WDT0_RESET_SHIFT (6U)
+/*! WDT0_RESET - WDT0 reset was detected
+ * 0b0..No WDT0 reset event is detected
+ * 0b1..WDT0 reset was detected
+ */
+#define RSTCTL1_SYSRSTSTAT_WDT0_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_SYSRSTSTAT_WDT0_RESET_SHIFT)) & RSTCTL1_SYSRSTSTAT_WDT0_RESET_MASK)
+#define RSTCTL1_SYSRSTSTAT_WDT1_RESET_MASK (0x80U)
+#define RSTCTL1_SYSRSTSTAT_WDT1_RESET_SHIFT (7U)
+/*! WDT1_RESET - WDT1 reset was detected
+ * 0b0..No WDT1 reset event is detected
+ * 0b1..WDT1 reset was detected
+ */
+#define RSTCTL1_SYSRSTSTAT_WDT1_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_SYSRSTSTAT_WDT1_RESET_SHIFT)) & RSTCTL1_SYSRSTSTAT_WDT1_RESET_MASK)
+/*! @} */
+
+/*! @name PRSTCTL0 - Peripheral Reset Control Register 0 */
+/*! @{ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM0_MASK (0x100U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM0_SHIFT (8U)
+/*! FLEXCOMM0 - Flexcomm0 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM0_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM0_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM1_MASK (0x200U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM1_SHIFT (9U)
+/*! FLEXCOMM1 - Flexcomm1 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM1_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM1_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM2_MASK (0x400U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM2_SHIFT (10U)
+/*! FLEXCOMM2 - Flexcomm2 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM2_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM2_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM3_MASK (0x800U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM3_SHIFT (11U)
+/*! FLEXCOMM3 - Flexcomm3 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM3_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM3_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM4_MASK (0x1000U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM4_SHIFT (12U)
+/*! FLEXCOMM4 - Flexcomm4 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM4_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM4_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM5_MASK (0x2000U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM5_SHIFT (13U)
+/*! FLEXCOMM5 - Flexcomm5 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM5_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM5_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM6_MASK (0x4000U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM6_SHIFT (14U)
+/*! FLEXCOMM6 - Flexcomm6 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM6_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM6_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM7_MASK (0x8000U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM7_SHIFT (15U)
+/*! FLEXCOMM7 - Flexcomm7 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM7_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM7_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM8_MASK (0x10000U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM8_SHIFT (16U)
+/*! FLEXCOMM8 - Flexcomm8 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM8_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM8_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM9_MASK (0x20000U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM9_SHIFT (17U)
+/*! FLEXCOMM9 - Flexcomm9 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM9_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM9_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM10_MASK (0x40000U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM10_SHIFT (18U)
+/*! FLEXCOMM10 - Flexcomm10 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM10_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM10_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM11_MASK (0x80000U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM11_SHIFT (19U)
+/*! FLEXCOMM11 - Flexcomm11 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM11(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM11_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM11_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM12_MASK (0x100000U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM12_SHIFT (20U)
+/*! FLEXCOMM12 - Flexcomm12 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM12(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM12_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM12_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM13_MASK (0x200000U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM13_SHIFT (21U)
+/*! FLEXCOMM13 - Flexcomm13 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM13(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM13_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM13_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM14_MASK (0x400000U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM14_SHIFT (22U)
+/*! FLEXCOMM14 - Flexcomm14 SPI0 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM14(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM14_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM14_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM15_I2C_MASK (0x800000U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM15_I2C_SHIFT (23U)
+/*! FLEXCOMM15_I2C - Flexcomm15 I2C reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM15_I2C(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM15_I2C_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM15_I2C_MASK)
+#define RSTCTL1_PRSTCTL0_DMIC0_MASK (0x1000000U)
+#define RSTCTL1_PRSTCTL0_DMIC0_SHIFT (24U)
+/*! DMIC0 - DMIC0 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_DMIC0_SHIFT)) & RSTCTL1_PRSTCTL0_DMIC0_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM16_MASK (0x2000000U)
+#define RSTCTL1_PRSTCTL0_FLEXCOMM16_SHIFT (25U)
+/*! FLEXCOMM16 - Flexcomm SPI reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXCOMM16(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM16_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM16_MASK)
+#define RSTCTL1_PRSTCTL0_OSEVENT_TIMER_MASK (0x8000000U)
+#define RSTCTL1_PRSTCTL0_OSEVENT_TIMER_SHIFT (27U)
+/*! OSEVENT_TIMER - OSEVENT Timer reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_OSEVENT_TIMER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_OSEVENT_TIMER_SHIFT)) & RSTCTL1_PRSTCTL0_OSEVENT_TIMER_MASK)
+#define RSTCTL1_PRSTCTL0_FLEXIO_MASK (0x20000000U)
+#define RSTCTL1_PRSTCTL0_FLEXIO_SHIFT (29U)
+/*! FLEXIO - FLEXIO reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL0_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXIO_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXIO_MASK)
+/*! @} */
+
+/*! @name PRSTCTL1 - Peripheral Reset Control Register 1 */
+/*! @{ */
+#define RSTCTL1_PRSTCTL1_HSGPIO0_MASK (0x1U)
+#define RSTCTL1_PRSTCTL1_HSGPIO0_SHIFT (0U)
+/*! HSGPIO0 - HSGPIO[7:0] reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL1_HSGPIO0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO0_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO0_MASK)
+#define RSTCTL1_PRSTCTL1_HSGPIO1_MASK (0x2U)
+#define RSTCTL1_PRSTCTL1_HSGPIO1_SHIFT (1U)
+/*! HSGPIO1 - HSGPIO[7:0] reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL1_HSGPIO1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO1_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO1_MASK)
+#define RSTCTL1_PRSTCTL1_HSGPIO2_MASK (0x4U)
+#define RSTCTL1_PRSTCTL1_HSGPIO2_SHIFT (2U)
+/*! HSGPIO2 - HSGPIO[7:0] reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL1_HSGPIO2(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO2_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO2_MASK)
+#define RSTCTL1_PRSTCTL1_HSGPIO3_MASK (0x8U)
+#define RSTCTL1_PRSTCTL1_HSGPIO3_SHIFT (3U)
+/*! HSGPIO3 - HSGPIO[7:0] reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL1_HSGPIO3(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO3_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO3_MASK)
+#define RSTCTL1_PRSTCTL1_HSGPIO4_MASK (0x10U)
+#define RSTCTL1_PRSTCTL1_HSGPIO4_SHIFT (4U)
+/*! HSGPIO4 - HSGPIO[7:0] reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL1_HSGPIO4(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO4_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO4_MASK)
+#define RSTCTL1_PRSTCTL1_HSGPIO5_MASK (0x20U)
+#define RSTCTL1_PRSTCTL1_HSGPIO5_SHIFT (5U)
+/*! HSGPIO5 - HSGPIO[7:0] reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL1_HSGPIO5(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO5_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO5_MASK)
+#define RSTCTL1_PRSTCTL1_HSGPIO6_MASK (0x40U)
+#define RSTCTL1_PRSTCTL1_HSGPIO6_SHIFT (6U)
+/*! HSGPIO6 - HSGPIO[7:0] reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL1_HSGPIO6(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO6_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO6_MASK)
+#define RSTCTL1_PRSTCTL1_HSGPIO7_MASK (0x80U)
+#define RSTCTL1_PRSTCTL1_HSGPIO7_SHIFT (7U)
+/*! HSGPIO7 - HSGPIO[7:0] reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL1_HSGPIO7(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO7_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO7_MASK)
+#define RSTCTL1_PRSTCTL1_CRC_MASK (0x10000U)
+#define RSTCTL1_PRSTCTL1_CRC_SHIFT (16U)
+/*! CRC - CRC reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL1_CRC(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CRC_SHIFT)) & RSTCTL1_PRSTCTL1_CRC_MASK)
+#define RSTCTL1_PRSTCTL1_DMAC0_MASK (0x800000U)
+#define RSTCTL1_PRSTCTL1_DMAC0_SHIFT (23U)
+/*! DMAC0 - DMAC reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL1_DMAC0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_DMAC0_SHIFT)) & RSTCTL1_PRSTCTL1_DMAC0_MASK)
+#define RSTCTL1_PRSTCTL1_DMAC1_MASK (0x1000000U)
+#define RSTCTL1_PRSTCTL1_DMAC1_SHIFT (24U)
+/*! DMAC1 - DMAC reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL1_DMAC1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_DMAC1_SHIFT)) & RSTCTL1_PRSTCTL1_DMAC1_MASK)
+#define RSTCTL1_PRSTCTL1_MU_MASK (0x10000000U)
+#define RSTCTL1_PRSTCTL1_MU_SHIFT (28U)
+/*! MU - MU reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL1_MU(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_MU_SHIFT)) & RSTCTL1_PRSTCTL1_MU_MASK)
+#define RSTCTL1_PRSTCTL1_SEMA_MASK (0x20000000U)
+#define RSTCTL1_PRSTCTL1_SEMA_SHIFT (29U)
+/*! SEMA - SEMA reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL1_SEMA(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SEMA_SHIFT)) & RSTCTL1_PRSTCTL1_SEMA_MASK)
+#define RSTCTL1_PRSTCTL1_FREQME_MASK (0x80000000U)
+#define RSTCTL1_PRSTCTL1_FREQME_SHIFT (31U)
+/*! FREQME - FREQME reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL1_FREQME(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_FREQME_SHIFT)) & RSTCTL1_PRSTCTL1_FREQME_MASK)
+/*! @} */
+
+/*! @name PRSTCTL2 - Peripheral Reset Control Register 2 */
+/*! @{ */
+#define RSTCTL1_PRSTCTL2_CT32BIT0_MASK (0x1U)
+#define RSTCTL1_PRSTCTL2_CT32BIT0_SHIFT (0U)
+/*! CT32BIT0
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL2_CT32BIT0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CT32BIT0_SHIFT)) & RSTCTL1_PRSTCTL2_CT32BIT0_MASK)
+#define RSTCTL1_PRSTCTL2_CT32BIT1_MASK (0x2U)
+#define RSTCTL1_PRSTCTL2_CT32BIT1_SHIFT (1U)
+/*! CT32BIT1
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL2_CT32BIT1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CT32BIT1_SHIFT)) & RSTCTL1_PRSTCTL2_CT32BIT1_MASK)
+#define RSTCTL1_PRSTCTL2_CT32BIT2_MASK (0x4U)
+#define RSTCTL1_PRSTCTL2_CT32BIT2_SHIFT (2U)
+/*! CT32BIT2
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL2_CT32BIT2(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CT32BIT2_SHIFT)) & RSTCTL1_PRSTCTL2_CT32BIT2_MASK)
+#define RSTCTL1_PRSTCTL2_CT32BIT3_MASK (0x8U)
+#define RSTCTL1_PRSTCTL2_CT32BIT3_SHIFT (3U)
+/*! CT32BIT3
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL2_CT32BIT3(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CT32BIT3_SHIFT)) & RSTCTL1_PRSTCTL2_CT32BIT3_MASK)
+#define RSTCTL1_PRSTCTL2_CT32BIT4_MASK (0x10U)
+#define RSTCTL1_PRSTCTL2_CT32BIT4_SHIFT (4U)
+/*! CT32BIT4
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL2_CT32BIT4(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CT32BIT4_SHIFT)) & RSTCTL1_PRSTCTL2_CT32BIT4_MASK)
+#define RSTCTL1_PRSTCTL2_MRT0_MASK (0x100U)
+#define RSTCTL1_PRSTCTL2_MRT0_SHIFT (8U)
+/*! MRT0 - MRT0 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL2_MRT0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_MRT0_SHIFT)) & RSTCTL1_PRSTCTL2_MRT0_MASK)
+#define RSTCTL1_PRSTCTL2_WWDT1_MASK (0x400U)
+#define RSTCTL1_PRSTCTL2_WWDT1_SHIFT (10U)
+/*! WWDT1 - WWDT1 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL2_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_WWDT1_SHIFT)) & RSTCTL1_PRSTCTL2_WWDT1_MASK)
+#define RSTCTL1_PRSTCTL2_I3C0_MASK (0x10000U)
+#define RSTCTL1_PRSTCTL2_I3C0_SHIFT (16U)
+/*! I3C0 - I3C0 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL2_I3C0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_I3C0_SHIFT)) & RSTCTL1_PRSTCTL2_I3C0_MASK)
+#define RSTCTL1_PRSTCTL2_I3C1_MASK (0x20000U)
+#define RSTCTL1_PRSTCTL2_I3C1_SHIFT (17U)
+/*! I3C1 - I3C1 reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL2_I3C1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_I3C1_SHIFT)) & RSTCTL1_PRSTCTL2_I3C1_MASK)
+#define RSTCTL1_PRSTCTL2_GPIOINTCTL_MASK (0x40000000U)
+#define RSTCTL1_PRSTCTL2_GPIOINTCTL_SHIFT (30U)
+/*! GPIOINTCTL - GPIOINTCTL reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL2_GPIOINTCTL(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_GPIOINTCTL_SHIFT)) & RSTCTL1_PRSTCTL2_GPIOINTCTL_MASK)
+#define RSTCTL1_PRSTCTL2_PIMCTL_MASK (0x80000000U)
+#define RSTCTL1_PRSTCTL2_PIMCTL_SHIFT (31U)
+/*! PIMCTL - INPUTMUX reset control
+ * 0b1..Set Reset
+ * 0b0..Clear Reset
+ */
+#define RSTCTL1_PRSTCTL2_PIMCTL(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_PIMCTL_SHIFT)) & RSTCTL1_PRSTCTL2_PIMCTL_MASK)
+/*! @} */
+
+/*! @name PRSTCTL0_SET - Peripheral Reset Control Register 0 SET */
+/*! @{ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM0_MASK (0x100U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM0_SHIFT (8U)
+/*! FLEXCOMM0 - Flexcomm0 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM0_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM0_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM1_MASK (0x200U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM1_SHIFT (9U)
+/*! FLEXCOMM1 - Flexcomm1 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM1_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM1_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM2_MASK (0x400U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM2_SHIFT (10U)
+/*! FLEXCOMM2 - Flexcomm2 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM2_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM2_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM3_MASK (0x800U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM3_SHIFT (11U)
+/*! FLEXCOMM3 - Flexcomm3 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM3_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM3_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM4_MASK (0x1000U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM4_SHIFT (12U)
+/*! FLEXCOMM4 - Flexcomm4 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM4_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM4_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM5_MASK (0x2000U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM5_SHIFT (13U)
+/*! FLEXCOMM5 - Flexcomm5 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM5_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM5_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM6_MASK (0x4000U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM6_SHIFT (14U)
+/*! FLEXCOMM6 - Flexcomm6 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM6_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM6_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM7_MASK (0x8000U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM7_SHIFT (15U)
+/*! FLEXCOMM7 - Flexcomm7 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM7_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM7_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM8_MASK (0x10000U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM8_SHIFT (16U)
+/*! FLEXCOMM8 - Flexcomm8 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM8_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM8_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM9_MASK (0x20000U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM9_SHIFT (17U)
+/*! FLEXCOMM9 - Flexcomm9 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM9_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM9_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM10_MASK (0x40000U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM10_SHIFT (18U)
+/*! FLEXCOMM10 - Flexcomm10 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM10_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM10_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM11_MASK (0x80000U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM11_SHIFT (19U)
+/*! FLEXCOMM11 - Flexcomm11 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM11(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM11_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM11_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM12_MASK (0x100000U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM12_SHIFT (20U)
+/*! FLEXCOMM12 - Flexcomm12 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM12(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM12_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM12_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM13_MASK (0x200000U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM13_SHIFT (21U)
+/*! FLEXCOMM13 - Flexcomm13 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM13(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM13_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM13_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM14_MASK (0x400000U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM14_SHIFT (22U)
+/*! FLEXCOMM14 - Flexcomm14 SPI0 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM14(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM14_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM14_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM15_I2C_MASK (0x800000U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM15_I2C_SHIFT (23U)
+/*! FLEXCOMM15_I2C - Flexcomm15 I2C reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM15_I2C(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM15_I2C_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM15_I2C_MASK)
+#define RSTCTL1_PRSTCTL0_SET_DMIC0_MASK (0x1000000U)
+#define RSTCTL1_PRSTCTL0_SET_DMIC0_SHIFT (24U)
+/*! DMIC0 - DMIC0 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_DMIC0_SHIFT)) & RSTCTL1_PRSTCTL0_SET_DMIC0_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM16_MASK (0x2000000U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM16_SHIFT (25U)
+/*! FLEXCOMM16 - Flexcomm16 SPI1 reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM16(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM16_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM16_MASK)
+#define RSTCTL1_PRSTCTL0_SET_OSEVENT_TIMER_MASK (0x8000000U)
+#define RSTCTL1_PRSTCTL0_SET_OSEVENT_TIMER_SHIFT (27U)
+/*! OSEVENT_TIMER - OSEVENT Timer reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_OSEVENT_TIMER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_OSEVENT_TIMER_SHIFT)) & RSTCTL1_PRSTCTL0_SET_OSEVENT_TIMER_MASK)
+#define RSTCTL1_PRSTCTL0_SET_FLEXIO_MASK (0x20000000U)
+#define RSTCTL1_PRSTCTL0_SET_FLEXIO_SHIFT (29U)
+/*! FLEXIO - FEXIO reset set
+ * 0b1..Sets the PRSTCTL0 Bit
+ * 0b0..No Effect
+ */
+#define RSTCTL1_PRSTCTL0_SET_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXIO_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXIO_MASK)
+/*! @} */
+
+/*! @name PRSTCTL1_SET - Peripheral Reset Control Register 1 SET */
+/*! @{ */
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO0_MASK (0x1U)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO0_SHIFT (0U)
+/*! HSGPIO0 - HSGPIO0 reset set
+ * 0b1..Sets the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO0_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO0_MASK)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO1_MASK (0x2U)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO1_SHIFT (1U)
+/*! HSGPIO1 - HSGPIO1 reset set
+ * 0b1..Sets the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO1_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO1_MASK)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO2_MASK (0x4U)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO2_SHIFT (2U)
+/*! HSGPIO2 - HSGPIO2 reset set
+ * 0b1..Sets the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO2(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO2_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO2_MASK)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO3_MASK (0x8U)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO3_SHIFT (3U)
+/*! HSGPIO3 - HSGPIO3 reset set
+ * 0b1..Sets the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO3(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO3_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO3_MASK)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO4_MASK (0x10U)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO4_SHIFT (4U)
+/*! HSGPIO4 - HSGPIO4 reset set
+ * 0b1..Sets the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO4(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO4_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO4_MASK)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO5_MASK (0x20U)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO5_SHIFT (5U)
+/*! HSGPIO5 - HSGPIO5 reset set
+ * 0b1..Sets the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO5(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO5_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO5_MASK)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO6_MASK (0x40U)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO6_SHIFT (6U)
+/*! HSGPIO6 - HSGPIO6 reset set
+ * 0b1..Sets the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO6(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO6_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO6_MASK)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO7_MASK (0x80U)
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO7_SHIFT (7U)
+/*! HSGPIO7 - HSGPIO7 reset set
+ * 0b1..Sets the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_SET_HSGPIO7(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO7_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO7_MASK)
+#define RSTCTL1_PRSTCTL1_SET_CRC_MASK (0x10000U)
+#define RSTCTL1_PRSTCTL1_SET_CRC_SHIFT (16U)
+/*! CRC - CRC reset set
+ * 0b1..Sets the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_SET_CRC(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_CRC_SHIFT)) & RSTCTL1_PRSTCTL1_SET_CRC_MASK)
+#define RSTCTL1_PRSTCTL1_SET_DMAC0_MASK (0x800000U)
+#define RSTCTL1_PRSTCTL1_SET_DMAC0_SHIFT (23U)
+/*! DMAC0 - DMAC0 reset set
+ * 0b1..Sets the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_SET_DMAC0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_DMAC0_SHIFT)) & RSTCTL1_PRSTCTL1_SET_DMAC0_MASK)
+#define RSTCTL1_PRSTCTL1_SET_DMAC1_MASK (0x1000000U)
+#define RSTCTL1_PRSTCTL1_SET_DMAC1_SHIFT (24U)
+/*! DMAC1 - DMAC1 reset set
+ * 0b1..Sets the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_SET_DMAC1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_DMAC1_SHIFT)) & RSTCTL1_PRSTCTL1_SET_DMAC1_MASK)
+#define RSTCTL1_PRSTCTL1_SET_MU_MASK (0x10000000U)
+#define RSTCTL1_PRSTCTL1_SET_MU_SHIFT (28U)
+/*! MU - MU reset set
+ * 0b1..Sets the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_SET_MU(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_MU_SHIFT)) & RSTCTL1_PRSTCTL1_SET_MU_MASK)
+#define RSTCTL1_PRSTCTL1_SET_SEMA_MASK (0x20000000U)
+#define RSTCTL1_PRSTCTL1_SET_SEMA_SHIFT (29U)
+/*! SEMA - SEMA reset set
+ * 0b1..Sets the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_SET_SEMA(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_SEMA_SHIFT)) & RSTCTL1_PRSTCTL1_SET_SEMA_MASK)
+#define RSTCTL1_PRSTCTL1_SET_FREQME_MASK (0x80000000U)
+#define RSTCTL1_PRSTCTL1_SET_FREQME_SHIFT (31U)
+/*! FREQME - FREQME reset set
+ * 0b1..Sets the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_SET_FREQME(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_FREQME_SHIFT)) & RSTCTL1_PRSTCTL1_SET_FREQME_MASK)
+/*! @} */
+
+/*! @name PRSTCTL2_SET - Peripheral Reset Control Register 2 SET */
+/*! @{ */
+#define RSTCTL1_PRSTCTL2_SET_CT32BIT0_MASK (0x1U)
+#define RSTCTL1_PRSTCTL2_SET_CT32BIT0_SHIFT (0U)
+/*! CT32BIT0 - CT32BIT0 reset set
+ * 0b1..Sets the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_SET_CT32BIT0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_CT32BIT0_SHIFT)) & RSTCTL1_PRSTCTL2_SET_CT32BIT0_MASK)
+#define RSTCTL1_PRSTCTL2_SET_CT32BIT1_MASK (0x2U)
+#define RSTCTL1_PRSTCTL2_SET_CT32BIT1_SHIFT (1U)
+/*! CT32BIT1 - CT32BIT1 reset set
+ * 0b1..Sets the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_SET_CT32BIT1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_CT32BIT1_SHIFT)) & RSTCTL1_PRSTCTL2_SET_CT32BIT1_MASK)
+#define RSTCTL1_PRSTCTL2_SET_CT32BIT2_MASK (0x4U)
+#define RSTCTL1_PRSTCTL2_SET_CT32BIT2_SHIFT (2U)
+/*! CT32BIT2 - CT32BIT2 reset set
+ * 0b1..Sets the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_SET_CT32BIT2(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_CT32BIT2_SHIFT)) & RSTCTL1_PRSTCTL2_SET_CT32BIT2_MASK)
+#define RSTCTL1_PRSTCTL2_SET_CT32BIT3_MASK (0x8U)
+#define RSTCTL1_PRSTCTL2_SET_CT32BIT3_SHIFT (3U)
+/*! CT32BIT3 - CT32BIT3 reset set
+ * 0b1..Sets the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_SET_CT32BIT3(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_CT32BIT3_SHIFT)) & RSTCTL1_PRSTCTL2_SET_CT32BIT3_MASK)
+#define RSTCTL1_PRSTCTL2_SET_CT32BIT4_MASK (0x10U)
+#define RSTCTL1_PRSTCTL2_SET_CT32BIT4_SHIFT (4U)
+/*! CT32BIT4 - CT32BIT4 reset set
+ * 0b1..Sets the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_SET_CT32BIT4(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_CT32BIT4_SHIFT)) & RSTCTL1_PRSTCTL2_SET_CT32BIT4_MASK)
+#define RSTCTL1_PRSTCTL2_SET_MRT0_MASK (0x100U)
+#define RSTCTL1_PRSTCTL2_SET_MRT0_SHIFT (8U)
+/*! MRT0 - MRT0 reset set
+ * 0b1..Sets the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_SET_MRT0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_MRT0_SHIFT)) & RSTCTL1_PRSTCTL2_SET_MRT0_MASK)
+#define RSTCTL1_PRSTCTL2_SET_WWDT1_MASK (0x400U)
+#define RSTCTL1_PRSTCTL2_SET_WWDT1_SHIFT (10U)
+/*! WWDT1 - WWDT1 reset set
+ * 0b1..Sets the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_SET_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_WWDT1_SHIFT)) & RSTCTL1_PRSTCTL2_SET_WWDT1_MASK)
+#define RSTCTL1_PRSTCTL2_SET_I3C0_MASK (0x10000U)
+#define RSTCTL1_PRSTCTL2_SET_I3C0_SHIFT (16U)
+/*! I3C0 - I3C0 reset set
+ * 0b1..Sets the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_SET_I3C0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_I3C0_SHIFT)) & RSTCTL1_PRSTCTL2_SET_I3C0_MASK)
+#define RSTCTL1_PRSTCTL2_SET_I3C1_MASK (0x20000U)
+#define RSTCTL1_PRSTCTL2_SET_I3C1_SHIFT (17U)
+/*! I3C1 - I3C1 reset set
+ * 0b1..Sets the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_SET_I3C1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_I3C1_SHIFT)) & RSTCTL1_PRSTCTL2_SET_I3C1_MASK)
+#define RSTCTL1_PRSTCTL2_SET_GPIOINTCTL_MASK (0x40000000U)
+#define RSTCTL1_PRSTCTL2_SET_GPIOINTCTL_SHIFT (30U)
+/*! GPIOINTCTL - GPIOINTCTL reset set
+ * 0b1..Sets the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_SET_GPIOINTCTL(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_GPIOINTCTL_SHIFT)) & RSTCTL1_PRSTCTL2_SET_GPIOINTCTL_MASK)
+#define RSTCTL1_PRSTCTL2_SET_PIMCTL_MASK (0x80000000U)
+#define RSTCTL1_PRSTCTL2_SET_PIMCTL_SHIFT (31U)
+/*! PIMCTL - PIMCTL reset set
+ * 0b1..Sets the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_SET_PIMCTL(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_PIMCTL_SHIFT)) & RSTCTL1_PRSTCTL2_SET_PIMCTL_MASK)
+/*! @} */
+
+/*! @name PRSTCTL0_CLR - Peripheral Reset Control Register 0 CLR */
+/*! @{ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM0_MASK (0x100U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM0_SHIFT (8U)
+/*! FLEXCOMM0 - Flexcomm0 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM0_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM0_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM1_MASK (0x200U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM1_SHIFT (9U)
+/*! FLEXCOMM1 - Flexcomm1 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM1_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM1_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM2_MASK (0x400U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM2_SHIFT (10U)
+/*! FLEXCOMM2 - Flexcomm2 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM2_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM2_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM3_MASK (0x800U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM3_SHIFT (11U)
+/*! FLEXCOMM3 - Flexcomm3 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM3_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM3_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM4_MASK (0x1000U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM4_SHIFT (12U)
+/*! FLEXCOMM4 - Flexcomm4 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM4_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM4_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM5_MASK (0x2000U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM5_SHIFT (13U)
+/*! FLEXCOMM5 - Flexcomm5 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM5_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM5_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM6_MASK (0x4000U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM6_SHIFT (14U)
+/*! FLEXCOMM6 - Flexcomm6 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM6_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM6_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM7_MASK (0x8000U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM7_SHIFT (15U)
+/*! FLEXCOMM7 - Flexcomm7 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM7_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM7_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM8_MASK (0x10000U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM8_SHIFT (16U)
+/*! FLEXCOMM8 - Flexcomm8 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM8_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM8_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM9_MASK (0x20000U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM9_SHIFT (17U)
+/*! FLEXCOMM9 - Flexcomm9 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM9_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM9_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM10_MASK (0x40000U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM10_SHIFT (18U)
+/*! FLEXCOMM10 - Flexcomm10 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM10_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM10_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM11_MASK (0x80000U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM11_SHIFT (19U)
+/*! FLEXCOMM11 - Flexcomm11 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM11(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM11_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM11_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM12_MASK (0x100000U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM12_SHIFT (20U)
+/*! FLEXCOMM12 - Flexcomm12 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM12(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM12_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM12_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM13_MASK (0x200000U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM13_SHIFT (21U)
+/*! FLEXCOMM13 - Flexcomm13 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM13(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM13_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM13_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM14_MASK (0x400000U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM14_SHIFT (22U)
+/*! FLEXCOMM14 - FLexcomm SPI0 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM14(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM14_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM14_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM15_I2C_MASK (0x800000U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM15_I2C_SHIFT (23U)
+/*! FLEXCOMM15_I2C - Flexcomm I2C reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM15_I2C(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM15_I2C_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM15_I2C_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_DMIC0_MASK (0x1000000U)
+#define RSTCTL1_PRSTCTL0_CLR_DMIC0_SHIFT (24U)
+/*! DMIC0 - DMIC0 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_DMIC0_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_DMIC0_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM16_MASK (0x2000000U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM16_SHIFT (25U)
+/*! FLEXCOMM16 - Flexcomm SPI1 reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM16(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM16_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM16_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_OSEVENT_TIMER_MASK (0x8000000U)
+#define RSTCTL1_PRSTCTL0_CLR_OSEVENT_TIMER_SHIFT (27U)
+/*! OSEVENT_TIMER - OSEVENT Timer reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_OSEVENT_TIMER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_OSEVENT_TIMER_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_OSEVENT_TIMER_MASK)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXIO_MASK (0x20000000U)
+#define RSTCTL1_PRSTCTL0_CLR_FLEXIO_SHIFT (29U)
+/*! FLEXIO - FLEXIO reset clear
+ * 0b1..Clears the PRSTCTL0 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL0_CLR_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXIO_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXIO_MASK)
+/*! @} */
+
+/*! @name PRSTCTL1_CLR - Peripheral Reset Control Register 1 CLR */
+/*! @{ */
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO0_MASK (0x1U)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO0_SHIFT (0U)
+/*! HSGPIO0 - HSGPIO0 reset clear
+ * 0b1..Clears the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO0_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO0_MASK)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO1_MASK (0x2U)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO1_SHIFT (1U)
+/*! HSGPIO1 - HSGPIO1 reset clear
+ * 0b1..Clears the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO1_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO1_MASK)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO2_MASK (0x4U)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO2_SHIFT (2U)
+/*! HSGPIO2 - HSGPIO2 reset clear
+ * 0b1..Clears the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO2(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO2_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO2_MASK)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO3_MASK (0x8U)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO3_SHIFT (3U)
+/*! HSGPIO3 - HSGPIO3 reset clear
+ * 0b1..Clears the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO3(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO3_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO3_MASK)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO4_MASK (0x10U)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO4_SHIFT (4U)
+/*! HSGPIO4 - HSGPIO4 reset clear
+ * 0b1..Clears the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO4(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO4_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO4_MASK)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO5_MASK (0x20U)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO5_SHIFT (5U)
+/*! HSGPIO5 - HSGPIO5 reset clear
+ * 0b1..Clears the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO5(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO5_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO5_MASK)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO6_MASK (0x40U)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO6_SHIFT (6U)
+/*! HSGPIO6 - HSGPIO6 reset clear
+ * 0b1..Clears the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO6(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO6_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO6_MASK)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO7_MASK (0x80U)
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO7_SHIFT (7U)
+/*! HSGPIO7 - HSGPIO7 reset clear
+ * 0b1..Clears the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_CLR_HSGPIO7(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO7_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO7_MASK)
+#define RSTCTL1_PRSTCTL1_CLR_CRC_MASK (0x10000U)
+#define RSTCTL1_PRSTCTL1_CLR_CRC_SHIFT (16U)
+/*! CRC - CRC reset clear
+ * 0b1..Clears the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_CLR_CRC(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_CRC_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_CRC_MASK)
+#define RSTCTL1_PRSTCTL1_CLR_DMAC0_MASK (0x800000U)
+#define RSTCTL1_PRSTCTL1_CLR_DMAC0_SHIFT (23U)
+/*! DMAC0 - DMAC0 reset clear
+ * 0b1..Clears the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_CLR_DMAC0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_DMAC0_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_DMAC0_MASK)
+#define RSTCTL1_PRSTCTL1_CLR_DMAC1_MASK (0x1000000U)
+#define RSTCTL1_PRSTCTL1_CLR_DMAC1_SHIFT (24U)
+/*! DMAC1 - DMAC1 reset clear
+ * 0b1..Clears the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_CLR_DMAC1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_DMAC1_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_DMAC1_MASK)
+#define RSTCTL1_PRSTCTL1_CLR_MU_MASK (0x10000000U)
+#define RSTCTL1_PRSTCTL1_CLR_MU_SHIFT (28U)
+/*! MU - MU reset clear
+ * 0b1..Clears the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_CLR_MU(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_MU_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_MU_MASK)
+#define RSTCTL1_PRSTCTL1_CLR_SEMA_MASK (0x20000000U)
+#define RSTCTL1_PRSTCTL1_CLR_SEMA_SHIFT (29U)
+/*! SEMA - SMEA reset clear
+ * 0b1..Clears the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_CLR_SEMA(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_SEMA_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_SEMA_MASK)
+#define RSTCTL1_PRSTCTL1_CLR_FREQME_MASK (0x80000000U)
+#define RSTCTL1_PRSTCTL1_CLR_FREQME_SHIFT (31U)
+/*! FREQME - FREQME reset clear
+ * 0b1..Clears the PRSTCTL1 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL1_CLR_FREQME(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_FREQME_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_FREQME_MASK)
+/*! @} */
+
+/*! @name PRSTCTL2_CLR - Peripheral Reset Control Register 2 CLR */
+/*! @{ */
+#define RSTCTL1_PRSTCTL2_CLR_CT32BIT0_MASK (0x1U)
+#define RSTCTL1_PRSTCTL2_CLR_CT32BIT0_SHIFT (0U)
+/*! CT32BIT0 - CT32BIT0 reset clear
+ * 0b1..Clears the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_CLR_CT32BIT0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_CT32BIT0_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_CT32BIT0_MASK)
+#define RSTCTL1_PRSTCTL2_CLR_CT32BIT1_MASK (0x2U)
+#define RSTCTL1_PRSTCTL2_CLR_CT32BIT1_SHIFT (1U)
+/*! CT32BIT1 - CT32BIT1 reset clear
+ * 0b1..Clears the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_CLR_CT32BIT1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_CT32BIT1_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_CT32BIT1_MASK)
+#define RSTCTL1_PRSTCTL2_CLR_CT32BIT2_MASK (0x4U)
+#define RSTCTL1_PRSTCTL2_CLR_CT32BIT2_SHIFT (2U)
+/*! CT32BIT2 - CT32BIT2 reset clear
+ * 0b1..Clears the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_CLR_CT32BIT2(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_CT32BIT2_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_CT32BIT2_MASK)
+#define RSTCTL1_PRSTCTL2_CLR_CT32BIT3_MASK (0x8U)
+#define RSTCTL1_PRSTCTL2_CLR_CT32BIT3_SHIFT (3U)
+/*! CT32BIT3 - CT32BIT3 reset clear
+ * 0b1..Clears the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_CLR_CT32BIT3(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_CT32BIT3_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_CT32BIT3_MASK)
+#define RSTCTL1_PRSTCTL2_CLR_CT32BIT4_MASK (0x10U)
+#define RSTCTL1_PRSTCTL2_CLR_CT32BIT4_SHIFT (4U)
+/*! CT32BIT4 - CT32BIT4 reset clear
+ * 0b1..Clears the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_CLR_CT32BIT4(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_CT32BIT4_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_CT32BIT4_MASK)
+#define RSTCTL1_PRSTCTL2_CLR_MRT0_MASK (0x100U)
+#define RSTCTL1_PRSTCTL2_CLR_MRT0_SHIFT (8U)
+/*! MRT0 - MRT0 reset clear
+ * 0b1..Clears the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_CLR_MRT0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_MRT0_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_MRT0_MASK)
+#define RSTCTL1_PRSTCTL2_CLR_WWDT1_MASK (0x400U)
+#define RSTCTL1_PRSTCTL2_CLR_WWDT1_SHIFT (10U)
+/*! WWDT1 - WWDT1 reset clear
+ * 0b1..Clears the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_CLR_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_WWDT1_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_WWDT1_MASK)
+#define RSTCTL1_PRSTCTL2_CLR_I3C0_MASK (0x10000U)
+#define RSTCTL1_PRSTCTL2_CLR_I3C0_SHIFT (16U)
+/*! I3C0 - I3C[1:0] reset clear
+ * 0b1..Clears the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_CLR_I3C0(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_I3C0_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_I3C0_MASK)
+#define RSTCTL1_PRSTCTL2_CLR_I3C1_MASK (0x20000U)
+#define RSTCTL1_PRSTCTL2_CLR_I3C1_SHIFT (17U)
+/*! I3C1 - I3C[1:0] reset clear
+ * 0b1..Clears the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_CLR_I3C1(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_I3C1_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_I3C1_MASK)
+#define RSTCTL1_PRSTCTL2_CLR_GPIOINTCTL_MASK (0x40000000U)
+#define RSTCTL1_PRSTCTL2_CLR_GPIOINTCTL_SHIFT (30U)
+/*! GPIOINTCTL - GPIOINTCTL reset clear
+ * 0b1..Clears the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_CLR_GPIOINTCTL(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_GPIOINTCTL_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_GPIOINTCTL_MASK)
+#define RSTCTL1_PRSTCTL2_CLR_PIMCTL_MASK (0x80000000U)
+#define RSTCTL1_PRSTCTL2_CLR_PIMCTL_SHIFT (31U)
+/*! PIMCTL
+ * 0b1..Clears the PRSTCTL2 Bit
+ * 0b0..No effect
+ */
+#define RSTCTL1_PRSTCTL2_CLR_PIMCTL(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_PIMCTL_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_PIMCTL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RSTCTL1_Register_Masks */
+
+
+/* RSTCTL1 - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral RSTCTL1 base address */
+ #define RSTCTL1_BASE (0x50020000u)
+ /** Peripheral RSTCTL1 base address */
+ #define RSTCTL1_BASE_NS (0x40020000u)
+ /** Peripheral RSTCTL1 base pointer */
+ #define RSTCTL1 ((RSTCTL1_Type *)RSTCTL1_BASE)
+ /** Peripheral RSTCTL1 base pointer */
+ #define RSTCTL1_NS ((RSTCTL1_Type *)RSTCTL1_BASE_NS)
+ /** Array initializer of RSTCTL1 peripheral base addresses */
+ #define RSTCTL1_BASE_ADDRS { RSTCTL1_BASE }
+ /** Array initializer of RSTCTL1 peripheral base pointers */
+ #define RSTCTL1_BASE_PTRS { RSTCTL1 }
+ /** Array initializer of RSTCTL1 peripheral base addresses */
+ #define RSTCTL1_BASE_ADDRS_NS { RSTCTL1_BASE_NS }
+ /** Array initializer of RSTCTL1 peripheral base pointers */
+ #define RSTCTL1_BASE_PTRS_NS { RSTCTL1_NS }
+#else
+ /** Peripheral RSTCTL1 base address */
+ #define RSTCTL1_BASE (0x40020000u)
+ /** Peripheral RSTCTL1 base pointer */
+ #define RSTCTL1 ((RSTCTL1_Type *)RSTCTL1_BASE)
+ /** Array initializer of RSTCTL1 peripheral base addresses */
+ #define RSTCTL1_BASE_ADDRS { RSTCTL1_BASE }
+ /** Array initializer of RSTCTL1 peripheral base pointers */
+ #define RSTCTL1_BASE_PTRS { RSTCTL1 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group RSTCTL1_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< RTC Control, offset: 0x0 */
+ __IO uint32_t MATCH; /**< RTC Match, offset: 0x4 */
+ __IO uint32_t COUNT; /**< RTC Counter, offset: 0x8 */
+ __IO uint32_t WAKE; /**< High-resolution/Wake-up Timer Control, offset: 0xC */
+ __I uint32_t SUBSEC; /**< RTC Sub-second Counter, offset: 0x10 */
+ uint8_t RESERVED_0[44];
+ __IO uint32_t GPREG[8]; /**< General Purpose, array offset: 0x40, array step: 0x4 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - RTC Control */
+/*! @{ */
+#define RTC_CTRL_SWRESET_MASK (0x1U)
+#define RTC_CTRL_SWRESET_SHIFT (0U)
+/*! SWRESET - Software Reset Control
+ * 0b0..Not in reset. The RTC is not held in reset. Clear SWRESET before configuring or initiating any operation of the RTC.
+ * 0b1..In reset
+ */
+#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
+#define RTC_CTRL_ALARM1HZ_MASK (0x4U)
+#define RTC_CTRL_ALARM1HZ_SHIFT (2U)
+/*! ALARM1HZ - RTC 1 Hz Timer Alarm Flag Status
+ * 0b0..No match. No match condition has occurred on the 1 Hz RTC timer. Writing a 0 has no effect.
+ * 0b1..Match
+ */
+#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
+#define RTC_CTRL_WAKE1KHZ_MASK (0x8U)
+#define RTC_CTRL_WAKE1KHZ_SHIFT (3U)
+/*! WAKE1KHZ - RTC 1 kHz Timer Wake-up Flag Status
+ * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.
+ * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up
+ * interrupt request RTC-WAKE which can also wake up the device from any low power mode. Write 1 to clear.
+ */
+#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
+#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U)
+#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U)
+/*! ALARMDPD_EN - RTC 1 Hz Timer Alarm Enable for Deep Power-down
+ * 0b0..Disable. A match on the 1 Hz RTC timer does not bring the device out of Deep Power-down mode.
+ * 0b1..Enable. A match on the 1 Hz RTC timer brings the device out of Deep Power-down mode.
+ */
+#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
+#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U)
+#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U)
+/*! WAKEDPD_EN - RTC 1 kHz Timer Wake-up Enable for Deep Power-down
+ * 0b0..Disable. A match on the 1 kHz RTC timer does not bring the device out of Deep Power-down mode.
+ * 0b1..Enable. A match on the 1 kHz RTC timer brings the device out of Deep Power-down mode.
+ */
+#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
+#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U)
+#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U)
+/*! RTC1KHZ_EN - RTC 1 kHz Clock Enable
+ * 0b0..Disable. A match on the 1 kHz RTC timer does not bring the device out of Deep Power-down mode.
+ * 0b1..Enable. The 1 kHz RTC timer is enabled.
+ */
+#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
+#define RTC_CTRL_RTC_EN_MASK (0x80U)
+#define RTC_CTRL_RTC_EN_SHIFT (7U)
+/*! RTC_EN - RTC enable
+ * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. RTC_EN should be
+ * 0 when writing to load a value in the RTC counter (COUNT) register .
+ * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. The first clock to the RTC counter
+ * occurs 1 s after RTC_EN is set. To also enable the high-resolution, 1 kHz clock, set CTRL[RTC1KHZ_EN] = 1.
+ */
+#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
+#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U)
+#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U)
+/*! RTC_OSC_PD - The RTC Oscillator Enable
+ * 0b0..Enable. The RTC oscillator is enabled. RTC_OSC_PD must be cleared for the RTC module to function.
+ * 0b1..Shut Off. The RTC operation is disabled. The RTC oscillator is shut-off to limit power consumption.
+ */
+#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
+#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U)
+#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U)
+/*! RTC_SUBSEC_ENA - 32-KHz Sub-second Counter Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK)
+#define RTC_CTRL_RTC_OSC_loadcap_MASK (0xF0000000U)
+#define RTC_CTRL_RTC_OSC_loadcap_SHIFT (28U)
+/*! RTC_OSC_loadcap - Capacitive Load Selection
+ */
+#define RTC_CTRL_RTC_OSC_loadcap(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_loadcap_SHIFT)) & RTC_CTRL_RTC_OSC_loadcap_MASK)
+/*! @} */
+
+/*! @name MATCH - RTC Match */
+/*! @{ */
+#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU)
+#define RTC_MATCH_MATVAL_SHIFT (0U)
+/*! MATVAL - Match Value
+ */
+#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
+/*! @} */
+
+/*! @name COUNT - RTC Counter */
+/*! @{ */
+#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU)
+#define RTC_COUNT_VAL_SHIFT (0U)
+/*! VAL - Value
+ */
+#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
+/*! @} */
+
+/*! @name WAKE - High-resolution/Wake-up Timer Control */
+/*! @{ */
+#define RTC_WAKE_VAL_MASK (0xFFFFU)
+#define RTC_WAKE_VAL_SHIFT (0U)
+/*! VAL - Value
+ */
+#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
+/*! @} */
+
+/*! @name SUBSEC - RTC Sub-second Counter */
+/*! @{ */
+#define RTC_SUBSEC_RTC_SUBSEC_MASK (0x7FFFU)
+#define RTC_SUBSEC_RTC_SUBSEC_SHIFT (0U)
+/*! RTC_SUBSEC - RTC Sub-second Counter
+ */
+#define RTC_SUBSEC_RTC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_RTC_SUBSEC_SHIFT)) & RTC_SUBSEC_RTC_SUBSEC_MASK)
+/*! @} */
+
+/*! @name GPREG - General Purpose */
+/*! @{ */
+#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU)
+#define RTC_GPREG_GPDATA_SHIFT (0U)
+/*! GPDATA - General Purpose Data
+ */
+#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)
+/*! @} */
+
+/* The count of RTC_GPREG */
+#define RTC_GPREG_COUNT (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral RTC base address */
+ #define RTC_BASE (0x50030000u)
+ /** Peripheral RTC base address */
+ #define RTC_BASE_NS (0x40030000u)
+ /** Peripheral RTC base pointer */
+ #define RTC ((RTC_Type *)RTC_BASE)
+ /** Peripheral RTC base pointer */
+ #define RTC_NS ((RTC_Type *)RTC_BASE_NS)
+ /** Array initializer of RTC peripheral base addresses */
+ #define RTC_BASE_ADDRS { RTC_BASE }
+ /** Array initializer of RTC peripheral base pointers */
+ #define RTC_BASE_PTRS { RTC }
+ /** Array initializer of RTC peripheral base addresses */
+ #define RTC_BASE_ADDRS_NS { RTC_BASE_NS }
+ /** Array initializer of RTC peripheral base pointers */
+ #define RTC_BASE_PTRS_NS { RTC_NS }
+#else
+ /** Peripheral RTC base address */
+ #define RTC_BASE (0x40030000u)
+ /** Peripheral RTC base pointer */
+ #define RTC ((RTC_Type *)RTC_BASE)
+ /** Array initializer of RTC peripheral base addresses */
+ #define RTC_BASE_ADDRS { RTC_BASE }
+ /** Array initializer of RTC peripheral base pointers */
+ #define RTC_BASE_PTRS { RTC }
+#endif
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS { RTC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SCT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
+ * @{
+ */
+
+/** SCT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CONFIG; /**< SCTimer Configuration, offset: 0x0 */
+ union { /* offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */
+ __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */
+ } CTRL_ACCESS16BIT;
+ __IO uint32_t CTRL; /**< SCT Control, offset: 0x4 */
+ };
+ union { /* offset: 0x8 */
+ struct { /* offset: 0x8 */
+ __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */
+ __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */
+ } LIMIT_ACCESS16BIT;
+ __IO uint32_t LIMIT; /**< SCT Limit Event Select, offset: 0x8 */
+ };
+ union { /* offset: 0xC */
+ struct { /* offset: 0xC */
+ __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */
+ __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */
+ } HALT_ACCESS16BIT;
+ __IO uint32_t HALT; /**< Halt Event Select, offset: 0xC */
+ };
+ union { /* offset: 0x10 */
+ struct { /* offset: 0x10 */
+ __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */
+ __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */
+ } STOP_ACCESS16BIT;
+ __IO uint32_t STOP; /**< Stop Event Select, offset: 0x10 */
+ };
+ union { /* offset: 0x14 */
+ struct { /* offset: 0x14 */
+ __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */
+ __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */
+ } START_ACCESS16BIT;
+ __IO uint32_t START; /**< Start Event Select, offset: 0x14 */
+ };
+ uint8_t RESERVED_0[40];
+ union { /* offset: 0x40 */
+ struct { /* offset: 0x40 */
+ __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */
+ __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */
+ } COUNT_ACCESS16BIT;
+ __IO uint32_t COUNT; /**< Counter, offset: 0x40 */
+ };
+ union { /* offset: 0x44 */
+ struct { /* offset: 0x44 */
+ __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */
+ __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */
+ } STATE_ACCESS16BIT;
+ __IO uint32_t STATE; /**< State, offset: 0x44 */
+ };
+ __I uint32_t INPUT; /**< Input, offset: 0x48 */
+ union { /* offset: 0x4C */
+ struct { /* offset: 0x4C */
+ __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */
+ __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */
+ } REGMODE_ACCESS16BIT;
+ __IO uint32_t REGMODE; /**< Match/Capture Mode, offset: 0x4C */
+ };
+ __IO uint32_t OUTPUT; /**< Output, offset: 0x50 */
+ __IO uint32_t OUTPUTDIRCTRL; /**< Output Counter Direction Control, offset: 0x54 */
+ __IO uint32_t RES; /**< Output Conflict Resolution, offset: 0x58 */
+ __IO uint32_t DMAREQ0; /**< DMA Request 0, offset: 0x5C */
+ __IO uint32_t DMAREQ1; /**< DMA Request 1, offset: 0x60 */
+ uint8_t RESERVED_1[140];
+ __IO uint32_t EVEN; /**< Event Interrupt Enable, offset: 0xF0 */
+ __IO uint32_t EVFLAG; /**< Event Flag, offset: 0xF4 */
+ __IO uint32_t CONEN; /**< Conflict Interrupt Enable, offset: 0xF8 */
+ __IO uint32_t CONFLAG; /**< Conflict Flag, offset: 0xFC */
+ union { /* offset: 0x100 */
+ union { /* offset: 0x100, array step: 0x4 */
+ struct { /* offset: 0x100, array step: 0x4 */
+ __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */
+ __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */
+ } CAP_ACCESS16BIT[16];
+ __IO uint32_t CAP[16]; /**< Capture Value, array offset: 0x100, array step: 0x4 */
+ };
+ union { /* offset: 0x100, array step: 0x4 */
+ struct { /* offset: 0x100, array step: 0x4 */
+ __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */
+ __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */
+ } MATCH_ACCESS16BIT[16];
+ __IO uint32_t MATCH[16]; /**< Match Value, array offset: 0x100, array step: 0x4 */
+ };
+ };
+ uint8_t RESERVED_2[192];
+ union { /* offset: 0x200 */
+ union { /* offset: 0x200, array step: 0x4 */
+ struct { /* offset: 0x200, array step: 0x4 */
+ __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */
+ __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */
+ } CAPCTRL_ACCESS16BIT[16];
+ __IO uint32_t CAPCTRL[16]; /**< Capture Control, array offset: 0x200, array step: 0x4 */
+ };
+ union { /* offset: 0x200, array step: 0x4 */
+ struct { /* offset: 0x200, array step: 0x4 */
+ __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */
+ __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */
+ } MATCHREL_ACCESS16BIT[16];
+ __IO uint32_t MATCHREL[16]; /**< Match Reload Value, array offset: 0x200, array step: 0x4 */
+ };
+ };
+ uint8_t RESERVED_3[192];
+ struct { /* offset: 0x300, array step: 0x8 */
+ __IO uint32_t STATE; /**< Event n State, array offset: 0x300, array step: 0x8 */
+ __IO uint32_t CTRL; /**< Event n Control, array offset: 0x304, array step: 0x8 */
+ } EV[16];
+ uint8_t RESERVED_4[384];
+ struct { /* offset: 0x500, array step: 0x8 */
+ __IO uint32_t SET; /**< Output n Set, array offset: 0x500, array step: 0x8 */
+ __IO uint32_t CLR; /**< Output n Clear, array offset: 0x504, array step: 0x8 */
+ } OUT[10];
+} SCT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SCT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Register_Masks SCT Register Masks
+ * @{
+ */
+
+/*! @name CONFIG - SCTimer Configuration */
+/*! @{ */
+#define SCT_CONFIG_UNIFY_MASK (0x1U)
+#define SCT_CONFIG_UNIFY_SHIFT (0U)
+/*! UNIFY - SCT Operation
+ * 0b0..Dual counter. The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
+ * 0b1..Unified counter. The SCT operates as a unified 32-bit counter.
+ */
+#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
+#define SCT_CONFIG_CLKMODE_MASK (0x6U)
+#define SCT_CONFIG_CLKMODE_SHIFT (1U)
+/*! CLKMODE - SCT Clock Mode
+ * 0b00..System Clock Mode. The system clock clocks the entire SCT module including all counters and counter prescalers.
+ * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are
+ * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The
+ * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the
+ * high-performance, sampled-clock mode.
+ * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including all
+ * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the
+ * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
+ * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL
+ * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system
+ * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than
+ * the system clock.
+ */
+#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
+#define SCT_CONFIG_CKSEL_MASK (0x78U)
+#define SCT_CONFIG_CKSEL_SHIFT (3U)
+/*! CKSEL - SCT Clock Select. The specific functionality of the designated input/edge is dependent
+ * on the CLKMODE bit selection in this register.
+ * 0b0000..Rising edges on input 0
+ * 0b0001..Falling edges on input 0
+ * 0b0010..Rising edges on input 1
+ * 0b0011..Falling edges on input 1
+ * 0b0100..Rising edges on input 2
+ * 0b0101..Falling edges on input 2
+ * 0b0110..Rising edges on input 3
+ * 0b0111..Falling edges on input 3
+ * 0b1000..Rising edges on input 4
+ * 0b1001..Falling edges on input 4
+ * 0b1010..Rising edges on input 5
+ * 0b1011..Falling edges on input 5
+ * 0b1100..Rising edges on input 6
+ * 0b1101..Falling edges on input 6
+ * 0b1110..Rising edges on input 7
+ * 0b1111..Falling edges on input 7
+ */
+#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
+#define SCT_CONFIG_NORELOAD_L_MASK (0x80U)
+#define SCT_CONFIG_NORELOAD_L_SHIFT (7U)
+/*! NORELOAD_L - No Reload Lower Match
+ * 0b0..Reload. The default setting.
+ * 0b1..No Reload. Prevents the lower match registers from being reloaded from their respective reload registers.
+ */
+#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)
+#define SCT_CONFIG_NORELOAD_H_MASK (0x100U)
+#define SCT_CONFIG_NORELOAD_H_SHIFT (8U)
+/*! NORELOAD_H - No Reload Higher Match
+ * 0b0..Reload. The default setting.
+ * 0b1..No Reload. Prevents the higher match registers from being reloaded from their respective reload registers.
+ */
+#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
+#define SCT_CONFIG_INSYNC_MASK (0x1FE00U)
+#define SCT_CONFIG_INSYNC_SHIFT (9U)
+/*! INSYNC - Input Synchronization
+ */
+#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
+#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U)
+#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U)
+/*! AUTOLIMIT_L - Auto Limit Lower
+ * 0b0..Disable.
+ * 0b1..Enable. A match on match register 0 is the LIMIT condition. No need to define an associated event.
+ */
+#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
+#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U)
+#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U)
+/*! AUTOLIMIT_H - Auto Limit Higher
+ * 0b0..Disable.
+ * 0b1..Enable. A match on match register 0 is the LIMIT condition. No need to define an associated event.
+ */
+#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
+/*! @} */
+
+/*! @name CTRLL - SCT_CTRLL register */
+/*! @{ */
+#define SCT_CTRLL_DOWN_L_MASK (0x1U)
+#define SCT_CTRLL_DOWN_L_SHIFT (0U)
+/*! DOWN_L - Down Counter Low
+ * 0b0..Up. The L or unified counter is counting up.
+ * 0b1..Down. The L or unified counter is counting down.
+ */
+#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK)
+#define SCT_CTRLL_STOP_L_MASK (0x2U)
+#define SCT_CTRLL_STOP_L_SHIFT (1U)
+/*! STOP_L - Stop Counter Low
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK)
+#define SCT_CTRLL_HALT_L_MASK (0x4U)
+#define SCT_CTRLL_HALT_L_SHIFT (2U)
+/*! HALT_L - Halt Counter Low
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK)
+#define SCT_CTRLL_CLRCTR_L_MASK (0x8U)
+#define SCT_CTRLL_CLRCTR_L_SHIFT (3U)
+/*! CLRCTR_L - Clear Counter Low
+ */
+#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK)
+#define SCT_CTRLL_BIDIR_L_MASK (0x10U)
+#define SCT_CTRLL_BIDIR_L_SHIFT (4U)
+/*! BIDIR_L - Bidirectional Select Low
+ * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
+ * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK)
+#define SCT_CTRLL_PRE_L_MASK (0x1FE0U)
+#define SCT_CTRLL_PRE_L_SHIFT (5U)
+/*! PRE_L - Prescaler for Low Counter
+ */
+#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK)
+/*! @} */
+
+/*! @name CTRLH - SCT_CTRLH register */
+/*! @{ */
+#define SCT_CTRLH_DOWN_H_MASK (0x1U)
+#define SCT_CTRLH_DOWN_H_SHIFT (0U)
+/*! DOWN_H - Down Counter High
+ * 0b0..Up. The H counter is counting up.
+ * 0b1..Down. The H counter is counting down.
+ */
+#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK)
+#define SCT_CTRLH_STOP_H_MASK (0x2U)
+#define SCT_CTRLH_STOP_H_SHIFT (1U)
+/*! STOP_H - Stop Counter High
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK)
+#define SCT_CTRLH_HALT_H_MASK (0x4U)
+#define SCT_CTRLH_HALT_H_SHIFT (2U)
+/*! HALT_H - Halt Counter High
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK)
+#define SCT_CTRLH_CLRCTR_H_MASK (0x8U)
+#define SCT_CTRLH_CLRCTR_H_SHIFT (3U)
+/*! CLRCTR_H - Clear Counter High
+ */
+#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK)
+#define SCT_CTRLH_BIDIR_H_MASK (0x10U)
+#define SCT_CTRLH_BIDIR_H_SHIFT (4U)
+/*! BIDIR_H - Bidirectional Select High
+ * 0b0..Up. The H counter counts up to its limit condition, then is cleared to zero.
+ * 0b1..Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK)
+#define SCT_CTRLH_PRE_H_MASK (0x1FE0U)
+#define SCT_CTRLH_PRE_H_SHIFT (5U)
+/*! PRE_H - Prescaler for High Counter
+ */
+#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK)
+/*! @} */
+
+/*! @name CTRL - SCT Control */
+/*! @{ */
+#define SCT_CTRL_DOWN_L_MASK (0x1U)
+#define SCT_CTRL_DOWN_L_SHIFT (0U)
+/*! DOWN_L - Down Counter Low
+ * 0b0..Up. The L or unified counter is counting up.
+ * 0b1..Down. The L or unified counter is counting down.
+ */
+#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
+#define SCT_CTRL_STOP_L_MASK (0x2U)
+#define SCT_CTRL_STOP_L_SHIFT (1U)
+/*! STOP_L - Stop Counter Low
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
+#define SCT_CTRL_HALT_L_MASK (0x4U)
+#define SCT_CTRL_HALT_L_SHIFT (2U)
+/*! HALT_L - Halt Counter Low
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
+#define SCT_CTRL_CLRCTR_L_MASK (0x8U)
+#define SCT_CTRL_CLRCTR_L_SHIFT (3U)
+/*! CLRCTR_L - Clear Counter Low
+ */
+#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
+#define SCT_CTRL_BIDIR_L_MASK (0x10U)
+#define SCT_CTRL_BIDIR_L_SHIFT (4U)
+/*! BIDIR_L - Bidirectional Select Low
+ * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
+ * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
+#define SCT_CTRL_PRE_L_MASK (0x1FE0U)
+#define SCT_CTRL_PRE_L_SHIFT (5U)
+/*! PRE_L - Prescaler for Low Counter
+ */
+#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
+#define SCT_CTRL_DOWN_H_MASK (0x10000U)
+#define SCT_CTRL_DOWN_H_SHIFT (16U)
+/*! DOWN_H - Down Counter High
+ * 0b0..Up. The H counter is counting up.
+ * 0b1..Down. The H counter is counting down.
+ */
+#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
+#define SCT_CTRL_STOP_H_MASK (0x20000U)
+#define SCT_CTRL_STOP_H_SHIFT (17U)
+/*! STOP_H - Stop Counter High
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
+#define SCT_CTRL_HALT_H_MASK (0x40000U)
+#define SCT_CTRL_HALT_H_SHIFT (18U)
+/*! HALT_H - Halt Counter High
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
+#define SCT_CTRL_CLRCTR_H_MASK (0x80000U)
+#define SCT_CTRL_CLRCTR_H_SHIFT (19U)
+/*! CLRCTR_H - Clear Counter High
+ */
+#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
+#define SCT_CTRL_BIDIR_H_MASK (0x100000U)
+#define SCT_CTRL_BIDIR_H_SHIFT (20U)
+/*! BIDIR_H - Bidirectional Select High
+ * 0b0..Up. The H counter counts up to its limit condition, then is cleared to zero.
+ * 0b1..Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
+#define SCT_CTRL_PRE_H_MASK (0x1FE00000U)
+#define SCT_CTRL_PRE_H_SHIFT (21U)
+/*! PRE_H - Prescaler for High Counter
+ */
+#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
+/*! @} */
+
+/*! @name LIMITL - SCT_LIMITL register */
+/*! @{ */
+#define SCT_LIMITL_LIMITL_MASK (0xFFFFU)
+#define SCT_LIMITL_LIMITL_SHIFT (0U)
+#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK)
+/*! @} */
+
+/*! @name LIMITH - SCT_LIMITH register */
+/*! @{ */
+#define SCT_LIMITH_LIMITH_MASK (0xFFFFU)
+#define SCT_LIMITH_LIMITH_SHIFT (0U)
+#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK)
+/*! @} */
+
+/*! @name LIMIT - SCT Limit Event Select */
+/*! @{ */
+#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU)
+#define SCT_LIMIT_LIMMSK_L_SHIFT (0U)
+/*! LIMMSK_L - Limit Event Counter Low
+ */
+#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
+#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U)
+#define SCT_LIMIT_LIMMSK_H_SHIFT (16U)
+/*! LIMMSK_H - Limit Event Counter High
+ */
+#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
+/*! @} */
+
+/*! @name HALTL - SCT_HALTL register */
+/*! @{ */
+#define SCT_HALTL_HALTL_MASK (0xFFFFU)
+#define SCT_HALTL_HALTL_SHIFT (0U)
+#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK)
+/*! @} */
+
+/*! @name HALTH - SCT_HALTH register */
+/*! @{ */
+#define SCT_HALTH_HALTH_MASK (0xFFFFU)
+#define SCT_HALTH_HALTH_SHIFT (0U)
+#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK)
+/*! @} */
+
+/*! @name HALT - Halt Event Select */
+/*! @{ */
+#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU)
+#define SCT_HALT_HALTMSK_L_SHIFT (0U)
+/*! HALTMSK_L - Halt Event Low
+ */
+#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
+#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U)
+#define SCT_HALT_HALTMSK_H_SHIFT (16U)
+/*! HALTMSK_H - Halt Event High
+ */
+#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
+/*! @} */
+
+/*! @name STOPL - SCT_STOPL register */
+/*! @{ */
+#define SCT_STOPL_STOPL_MASK (0xFFFFU)
+#define SCT_STOPL_STOPL_SHIFT (0U)
+#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK)
+/*! @} */
+
+/*! @name STOPH - SCT_STOPH register */
+/*! @{ */
+#define SCT_STOPH_STOPH_MASK (0xFFFFU)
+#define SCT_STOPH_STOPH_SHIFT (0U)
+#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK)
+/*! @} */
+
+/*! @name STOP - Stop Event Select */
+/*! @{ */
+#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU)
+#define SCT_STOP_STOPMSK_L_SHIFT (0U)
+/*! STOPMSK_L - Stop Event Low
+ */
+#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
+#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U)
+#define SCT_STOP_STOPMSK_H_SHIFT (16U)
+/*! STOPMSK_H - Stop Event High
+ */
+#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
+/*! @} */
+
+/*! @name STARTL - SCT_STARTL register */
+/*! @{ */
+#define SCT_STARTL_STARTL_MASK (0xFFFFU)
+#define SCT_STARTL_STARTL_SHIFT (0U)
+#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK)
+/*! @} */
+
+/*! @name STARTH - SCT_STARTH register */
+/*! @{ */
+#define SCT_STARTH_STARTH_MASK (0xFFFFU)
+#define SCT_STARTH_STARTH_SHIFT (0U)
+#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK)
+/*! @} */
+
+/*! @name START - Start Event Select */
+/*! @{ */
+#define SCT_START_STARTMSK_L_MASK (0xFFFFU)
+#define SCT_START_STARTMSK_L_SHIFT (0U)
+/*! STARTMSK_L - If bit n is one, event n clears the CTRL[STOP_L] = 0 (event 0 = bit 0, event 1 =
+ * bit 1, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
+#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U)
+#define SCT_START_STARTMSK_H_SHIFT (16U)
+/*! STARTMSK_H - If bit n is one, event n clears the CTRL[STOP_H] = 0 (event 0 = bit 16, event 1 =
+ * bit 17, etc.). The number of bits = number of events in this SCT.
+ */
+#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
+/*! @} */
+
+/*! @name COUNTL - SCT_COUNTL register */
+/*! @{ */
+#define SCT_COUNTL_COUNTL_MASK (0xFFFFU)
+#define SCT_COUNTL_COUNTL_SHIFT (0U)
+#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK)
+/*! @} */
+
+/*! @name COUNTH - SCT_COUNTH register */
+/*! @{ */
+#define SCT_COUNTH_COUNTH_MASK (0xFFFFU)
+#define SCT_COUNTH_COUNTH_SHIFT (0U)
+#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK)
+/*! @} */
+
+/*! @name COUNT - Counter */
+/*! @{ */
+#define SCT_COUNT_CTR_L_MASK (0xFFFFU)
+#define SCT_COUNT_CTR_L_SHIFT (0U)
+/*! CTR_L - Counter Low
+ */
+#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
+#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U)
+#define SCT_COUNT_CTR_H_SHIFT (16U)
+/*! CTR_H - Counter High
+ */
+#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
+/*! @} */
+
+/*! @name STATEL - SCT_STATEL register */
+/*! @{ */
+#define SCT_STATEL_STATEL_MASK (0xFFFFU)
+#define SCT_STATEL_STATEL_SHIFT (0U)
+#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK)
+/*! @} */
+
+/*! @name STATEH - SCT_STATEH register */
+/*! @{ */
+#define SCT_STATEH_STATEH_MASK (0xFFFFU)
+#define SCT_STATEH_STATEH_SHIFT (0U)
+#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK)
+/*! @} */
+
+/*! @name STATE - State */
+/*! @{ */
+#define SCT_STATE_STATE_L_MASK (0x1FU)
+#define SCT_STATE_STATE_L_SHIFT (0U)
+/*! STATE_L - State variable
+ */
+#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
+#define SCT_STATE_STATE_H_MASK (0x1F0000U)
+#define SCT_STATE_STATE_H_SHIFT (16U)
+/*! STATE_H - State variable
+ */
+#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
+/*! @} */
+
+/*! @name INPUT - Input */
+/*! @{ */
+#define SCT_INPUT_AIN0_MASK (0x1U)
+#define SCT_INPUT_AIN0_SHIFT (0U)
+/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
+#define SCT_INPUT_AIN1_MASK (0x2U)
+#define SCT_INPUT_AIN1_SHIFT (1U)
+/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
+#define SCT_INPUT_AIN2_MASK (0x4U)
+#define SCT_INPUT_AIN2_SHIFT (2U)
+/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
+#define SCT_INPUT_AIN3_MASK (0x8U)
+#define SCT_INPUT_AIN3_SHIFT (3U)
+/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
+#define SCT_INPUT_AIN4_MASK (0x10U)
+#define SCT_INPUT_AIN4_SHIFT (4U)
+/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
+#define SCT_INPUT_AIN5_MASK (0x20U)
+#define SCT_INPUT_AIN5_SHIFT (5U)
+/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
+#define SCT_INPUT_AIN6_MASK (0x40U)
+#define SCT_INPUT_AIN6_SHIFT (6U)
+/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
+#define SCT_INPUT_AIN7_MASK (0x80U)
+#define SCT_INPUT_AIN7_SHIFT (7U)
+/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
+#define SCT_INPUT_AIN8_MASK (0x100U)
+#define SCT_INPUT_AIN8_SHIFT (8U)
+/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
+#define SCT_INPUT_AIN9_MASK (0x200U)
+#define SCT_INPUT_AIN9_SHIFT (9U)
+/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
+#define SCT_INPUT_AIN10_MASK (0x400U)
+#define SCT_INPUT_AIN10_SHIFT (10U)
+/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
+#define SCT_INPUT_AIN11_MASK (0x800U)
+#define SCT_INPUT_AIN11_SHIFT (11U)
+/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
+#define SCT_INPUT_AIN12_MASK (0x1000U)
+#define SCT_INPUT_AIN12_SHIFT (12U)
+/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
+#define SCT_INPUT_AIN13_MASK (0x2000U)
+#define SCT_INPUT_AIN13_SHIFT (13U)
+/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
+#define SCT_INPUT_AIN14_MASK (0x4000U)
+#define SCT_INPUT_AIN14_SHIFT (14U)
+/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
+#define SCT_INPUT_AIN15_MASK (0x8000U)
+#define SCT_INPUT_AIN15_SHIFT (15U)
+/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge.
+ */
+#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
+#define SCT_INPUT_SIN0_MASK (0x10000U)
+#define SCT_INPUT_SIN0_SHIFT (16U)
+/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
+#define SCT_INPUT_SIN1_MASK (0x20000U)
+#define SCT_INPUT_SIN1_SHIFT (17U)
+/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
+#define SCT_INPUT_SIN2_MASK (0x40000U)
+#define SCT_INPUT_SIN2_SHIFT (18U)
+/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
+#define SCT_INPUT_SIN3_MASK (0x80000U)
+#define SCT_INPUT_SIN3_SHIFT (19U)
+/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
+#define SCT_INPUT_SIN4_MASK (0x100000U)
+#define SCT_INPUT_SIN4_SHIFT (20U)
+/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
+#define SCT_INPUT_SIN5_MASK (0x200000U)
+#define SCT_INPUT_SIN5_SHIFT (21U)
+/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
+#define SCT_INPUT_SIN6_MASK (0x400000U)
+#define SCT_INPUT_SIN6_SHIFT (22U)
+/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
+#define SCT_INPUT_SIN7_MASK (0x800000U)
+#define SCT_INPUT_SIN7_SHIFT (23U)
+/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
+#define SCT_INPUT_SIN8_MASK (0x1000000U)
+#define SCT_INPUT_SIN8_SHIFT (24U)
+/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
+#define SCT_INPUT_SIN9_MASK (0x2000000U)
+#define SCT_INPUT_SIN9_SHIFT (25U)
+/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
+#define SCT_INPUT_SIN10_MASK (0x4000000U)
+#define SCT_INPUT_SIN10_SHIFT (26U)
+/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
+#define SCT_INPUT_SIN11_MASK (0x8000000U)
+#define SCT_INPUT_SIN11_SHIFT (27U)
+/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
+#define SCT_INPUT_SIN12_MASK (0x10000000U)
+#define SCT_INPUT_SIN12_SHIFT (28U)
+/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
+#define SCT_INPUT_SIN13_MASK (0x20000000U)
+#define SCT_INPUT_SIN13_SHIFT (29U)
+/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
+#define SCT_INPUT_SIN14_MASK (0x40000000U)
+#define SCT_INPUT_SIN14_SHIFT (30U)
+/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
+#define SCT_INPUT_SIN15_MASK (0x80000000U)
+#define SCT_INPUT_SIN15_SHIFT (31U)
+/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC.
+ */
+#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
+/*! @} */
+
+/*! @name REGMODEL - SCT_REGMODEL register */
+/*! @{ */
+#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU)
+#define SCT_REGMODEL_REGMODEL_SHIFT (0U)
+/*! REGMODEL
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK)
+#define SCT_REGMODEL_REGMOD_L_MASK (0xFFFFU)
+#define SCT_REGMODEL_REGMOD_L_SHIFT (0U)
+/*! REGMOD_L
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODEL_REGMOD_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMOD_L_SHIFT)) & SCT_REGMODEL_REGMOD_L_MASK)
+#define SCT_REGMODEL_REGMOD_H_MASK (0xFFFF0000U)
+#define SCT_REGMODEL_REGMOD_H_SHIFT (16U)
+/*! REGMOD_H
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODEL_REGMOD_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMOD_H_SHIFT)) & SCT_REGMODEL_REGMOD_H_MASK)
+/*! @} */
+
+/*! @name REGMODEH - SCT_REGMODEH register */
+/*! @{ */
+#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU)
+#define SCT_REGMODEH_REGMODEH_SHIFT (0U)
+/*! REGMODEH
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK)
+#define SCT_REGMODEH_REGMOD_L_MASK (0xFFFFU)
+#define SCT_REGMODEH_REGMOD_L_SHIFT (0U)
+/*! REGMOD_L
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODEH_REGMOD_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMOD_L_SHIFT)) & SCT_REGMODEH_REGMOD_L_MASK)
+#define SCT_REGMODEH_REGMOD_H_MASK (0xFFFF0000U)
+#define SCT_REGMODEH_REGMOD_H_SHIFT (16U)
+/*! REGMOD_H
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODEH_REGMOD_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMOD_H_SHIFT)) & SCT_REGMODEH_REGMOD_H_MASK)
+/*! @} */
+
+/*! @name REGMODE - Match/Capture Mode */
+/*! @{ */
+#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU)
+#define SCT_REGMODE_REGMOD_L_SHIFT (0U)
+/*! REGMOD_L
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
+#define SCT_REGMODE_REGMOD_L0_MASK (0x1U)
+#define SCT_REGMODE_REGMOD_L0_SHIFT (0U)
+/*! REGMOD_L0 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L0(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L0_SHIFT)) & SCT_REGMODE_REGMOD_L0_MASK)
+#define SCT_REGMODE_REGMOD_L1_MASK (0x2U)
+#define SCT_REGMODE_REGMOD_L1_SHIFT (1U)
+/*! REGMOD_L1 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L1(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L1_SHIFT)) & SCT_REGMODE_REGMOD_L1_MASK)
+#define SCT_REGMODE_REGMOD_L2_MASK (0x4U)
+#define SCT_REGMODE_REGMOD_L2_SHIFT (2U)
+/*! REGMOD_L2 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L2(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L2_SHIFT)) & SCT_REGMODE_REGMOD_L2_MASK)
+#define SCT_REGMODE_REGMOD_L3_MASK (0x8U)
+#define SCT_REGMODE_REGMOD_L3_SHIFT (3U)
+/*! REGMOD_L3 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L3(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L3_SHIFT)) & SCT_REGMODE_REGMOD_L3_MASK)
+#define SCT_REGMODE_REGMOD_L4_MASK (0x10U)
+#define SCT_REGMODE_REGMOD_L4_SHIFT (4U)
+/*! REGMOD_L4 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L4(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L4_SHIFT)) & SCT_REGMODE_REGMOD_L4_MASK)
+#define SCT_REGMODE_REGMOD_L5_MASK (0x20U)
+#define SCT_REGMODE_REGMOD_L5_SHIFT (5U)
+/*! REGMOD_L5 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L5(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L5_SHIFT)) & SCT_REGMODE_REGMOD_L5_MASK)
+#define SCT_REGMODE_REGMOD_L6_MASK (0x40U)
+#define SCT_REGMODE_REGMOD_L6_SHIFT (6U)
+/*! REGMOD_L6 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L6(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L6_SHIFT)) & SCT_REGMODE_REGMOD_L6_MASK)
+#define SCT_REGMODE_REGMOD_L7_MASK (0x80U)
+#define SCT_REGMODE_REGMOD_L7_SHIFT (7U)
+/*! REGMOD_L7 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L7(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L7_SHIFT)) & SCT_REGMODE_REGMOD_L7_MASK)
+#define SCT_REGMODE_REGMOD_L8_MASK (0x100U)
+#define SCT_REGMODE_REGMOD_L8_SHIFT (8U)
+/*! REGMOD_L8 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L8(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L8_SHIFT)) & SCT_REGMODE_REGMOD_L8_MASK)
+#define SCT_REGMODE_REGMOD_L9_MASK (0x200U)
+#define SCT_REGMODE_REGMOD_L9_SHIFT (9U)
+/*! REGMOD_L9 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L9(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L9_SHIFT)) & SCT_REGMODE_REGMOD_L9_MASK)
+#define SCT_REGMODE_REGMOD_L10_MASK (0x400U)
+#define SCT_REGMODE_REGMOD_L10_SHIFT (10U)
+/*! REGMOD_L10 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L10(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L10_SHIFT)) & SCT_REGMODE_REGMOD_L10_MASK)
+#define SCT_REGMODE_REGMOD_L11_MASK (0x800U)
+#define SCT_REGMODE_REGMOD_L11_SHIFT (11U)
+/*! REGMOD_L11 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L11(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L11_SHIFT)) & SCT_REGMODE_REGMOD_L11_MASK)
+#define SCT_REGMODE_REGMOD_L12_MASK (0x1000U)
+#define SCT_REGMODE_REGMOD_L12_SHIFT (12U)
+/*! REGMOD_L12 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L12(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L12_SHIFT)) & SCT_REGMODE_REGMOD_L12_MASK)
+#define SCT_REGMODE_REGMOD_L13_MASK (0x2000U)
+#define SCT_REGMODE_REGMOD_L13_SHIFT (13U)
+/*! REGMOD_L13 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L13(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L13_SHIFT)) & SCT_REGMODE_REGMOD_L13_MASK)
+#define SCT_REGMODE_REGMOD_L14_MASK (0x4000U)
+#define SCT_REGMODE_REGMOD_L14_SHIFT (14U)
+/*! REGMOD_L14 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L14(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L14_SHIFT)) & SCT_REGMODE_REGMOD_L14_MASK)
+#define SCT_REGMODE_REGMOD_L15_MASK (0x8000U)
+#define SCT_REGMODE_REGMOD_L15_SHIFT (15U)
+/*! REGMOD_L15 - Register Mode Low n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_L15(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L15_SHIFT)) & SCT_REGMODE_REGMOD_L15_MASK)
+#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U)
+#define SCT_REGMODE_REGMOD_H_SHIFT (16U)
+/*! REGMOD_H
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
+#define SCT_REGMODE_REGMOD_H0_MASK (0x10000U)
+#define SCT_REGMODE_REGMOD_H0_SHIFT (16U)
+/*! REGMOD_H0 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H0(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H0_SHIFT)) & SCT_REGMODE_REGMOD_H0_MASK)
+#define SCT_REGMODE_REGMOD_H1_MASK (0x20000U)
+#define SCT_REGMODE_REGMOD_H1_SHIFT (17U)
+/*! REGMOD_H1 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H1(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H1_SHIFT)) & SCT_REGMODE_REGMOD_H1_MASK)
+#define SCT_REGMODE_REGMOD_H2_MASK (0x40000U)
+#define SCT_REGMODE_REGMOD_H2_SHIFT (18U)
+/*! REGMOD_H2 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H2(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H2_SHIFT)) & SCT_REGMODE_REGMOD_H2_MASK)
+#define SCT_REGMODE_REGMOD_H3_MASK (0x80000U)
+#define SCT_REGMODE_REGMOD_H3_SHIFT (19U)
+/*! REGMOD_H3 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H3(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H3_SHIFT)) & SCT_REGMODE_REGMOD_H3_MASK)
+#define SCT_REGMODE_REGMOD_H4_MASK (0x100000U)
+#define SCT_REGMODE_REGMOD_H4_SHIFT (20U)
+/*! REGMOD_H4 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H4(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H4_SHIFT)) & SCT_REGMODE_REGMOD_H4_MASK)
+#define SCT_REGMODE_REGMOD_H5_MASK (0x200000U)
+#define SCT_REGMODE_REGMOD_H5_SHIFT (21U)
+/*! REGMOD_H5 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H5(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H5_SHIFT)) & SCT_REGMODE_REGMOD_H5_MASK)
+#define SCT_REGMODE_REGMOD_H6_MASK (0x400000U)
+#define SCT_REGMODE_REGMOD_H6_SHIFT (22U)
+/*! REGMOD_H6 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H6(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H6_SHIFT)) & SCT_REGMODE_REGMOD_H6_MASK)
+#define SCT_REGMODE_REGMOD_H7_MASK (0x800000U)
+#define SCT_REGMODE_REGMOD_H7_SHIFT (23U)
+/*! REGMOD_H7 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H7(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H7_SHIFT)) & SCT_REGMODE_REGMOD_H7_MASK)
+#define SCT_REGMODE_REGMOD_H8_MASK (0x1000000U)
+#define SCT_REGMODE_REGMOD_H8_SHIFT (24U)
+/*! REGMOD_H8 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H8(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H8_SHIFT)) & SCT_REGMODE_REGMOD_H8_MASK)
+#define SCT_REGMODE_REGMOD_H9_MASK (0x2000000U)
+#define SCT_REGMODE_REGMOD_H9_SHIFT (25U)
+/*! REGMOD_H9 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H9(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H9_SHIFT)) & SCT_REGMODE_REGMOD_H9_MASK)
+#define SCT_REGMODE_REGMOD_H10_MASK (0x4000000U)
+#define SCT_REGMODE_REGMOD_H10_SHIFT (26U)
+/*! REGMOD_H10 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H10(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H10_SHIFT)) & SCT_REGMODE_REGMOD_H10_MASK)
+#define SCT_REGMODE_REGMOD_H11_MASK (0x8000000U)
+#define SCT_REGMODE_REGMOD_H11_SHIFT (27U)
+/*! REGMOD_H11 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H11(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H11_SHIFT)) & SCT_REGMODE_REGMOD_H11_MASK)
+#define SCT_REGMODE_REGMOD_H12_MASK (0x10000000U)
+#define SCT_REGMODE_REGMOD_H12_SHIFT (28U)
+/*! REGMOD_H12 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H12(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H12_SHIFT)) & SCT_REGMODE_REGMOD_H12_MASK)
+#define SCT_REGMODE_REGMOD_H13_MASK (0x20000000U)
+#define SCT_REGMODE_REGMOD_H13_SHIFT (29U)
+/*! REGMOD_H13 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H13(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H13_SHIFT)) & SCT_REGMODE_REGMOD_H13_MASK)
+#define SCT_REGMODE_REGMOD_H14_MASK (0x40000000U)
+#define SCT_REGMODE_REGMOD_H14_SHIFT (30U)
+/*! REGMOD_H14 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H14(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H14_SHIFT)) & SCT_REGMODE_REGMOD_H14_MASK)
+#define SCT_REGMODE_REGMOD_H15_MASK (0x80000000U)
+#define SCT_REGMODE_REGMOD_H15_SHIFT (31U)
+/*! REGMOD_H15 - Register Mode High n
+ * 0b0..Match. Register n operates as a match register
+ * 0b1..Capture. Register n operates as a capture register
+ */
+#define SCT_REGMODE_REGMOD_H15(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H15_SHIFT)) & SCT_REGMODE_REGMOD_H15_MASK)
+/*! @} */
+
+/*! @name OUTPUT - Output */
+/*! @{ */
+#define SCT_OUTPUT_OUT0_MASK (0x1U)
+#define SCT_OUTPUT_OUT0_SHIFT (0U)
+/*! OUT0 - Output n
+ * 0b0..Writing a 0 forces the corresponding output low
+ * 0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT0_SHIFT)) & SCT_OUTPUT_OUT0_MASK)
+#define SCT_OUTPUT_OUT1_MASK (0x2U)
+#define SCT_OUTPUT_OUT1_SHIFT (1U)
+/*! OUT1 - Output n
+ * 0b0..Writing a 0 forces the corresponding output low
+ * 0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT1_SHIFT)) & SCT_OUTPUT_OUT1_MASK)
+#define SCT_OUTPUT_OUT2_MASK (0x4U)
+#define SCT_OUTPUT_OUT2_SHIFT (2U)
+/*! OUT2 - Output n
+ * 0b0..Writing a 0 forces the corresponding output low
+ * 0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT2_SHIFT)) & SCT_OUTPUT_OUT2_MASK)
+#define SCT_OUTPUT_OUT3_MASK (0x8U)
+#define SCT_OUTPUT_OUT3_SHIFT (3U)
+/*! OUT3 - Output n
+ * 0b0..Writing a 0 forces the corresponding output low
+ * 0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT3_SHIFT)) & SCT_OUTPUT_OUT3_MASK)
+#define SCT_OUTPUT_OUT4_MASK (0x10U)
+#define SCT_OUTPUT_OUT4_SHIFT (4U)
+/*! OUT4 - Output n
+ * 0b0..Writing a 0 forces the corresponding output low
+ * 0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT4_SHIFT)) & SCT_OUTPUT_OUT4_MASK)
+#define SCT_OUTPUT_OUT5_MASK (0x20U)
+#define SCT_OUTPUT_OUT5_SHIFT (5U)
+/*! OUT5 - Output n
+ * 0b0..Writing a 0 forces the corresponding output low
+ * 0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT5_SHIFT)) & SCT_OUTPUT_OUT5_MASK)
+#define SCT_OUTPUT_OUT6_MASK (0x40U)
+#define SCT_OUTPUT_OUT6_SHIFT (6U)
+/*! OUT6 - Output n
+ * 0b0..Writing a 0 forces the corresponding output low
+ * 0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT6_SHIFT)) & SCT_OUTPUT_OUT6_MASK)
+#define SCT_OUTPUT_OUT7_MASK (0x80U)
+#define SCT_OUTPUT_OUT7_SHIFT (7U)
+/*! OUT7 - Output n
+ * 0b0..Writing a 0 forces the corresponding output low
+ * 0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT7_SHIFT)) & SCT_OUTPUT_OUT7_MASK)
+#define SCT_OUTPUT_OUT8_MASK (0x100U)
+#define SCT_OUTPUT_OUT8_SHIFT (8U)
+/*! OUT8 - Output n
+ * 0b0..Writing a 0 forces the corresponding output low
+ * 0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT8_SHIFT)) & SCT_OUTPUT_OUT8_MASK)
+#define SCT_OUTPUT_OUT9_MASK (0x200U)
+#define SCT_OUTPUT_OUT9_SHIFT (9U)
+/*! OUT9 - Output n
+ * 0b0..Writing a 0 forces the corresponding output low
+ * 0b1..Writing a 1 forces the corresponding output high
+ */
+#define SCT_OUTPUT_OUT9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT9_SHIFT)) & SCT_OUTPUT_OUT9_MASK)
+/*! @} */
+
+/*! @name OUTPUTDIRCTRL - Output Counter Direction Control */
+/*! @{ */
+#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U)
+#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U)
+/*! SETCLR0 - Set/Clear Operation on Output n
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ * 0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U)
+/*! SETCLR1 - Set/Clear Operation on Output n
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ * 0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U)
+/*! SETCLR2 - Set/Clear Operation on Output n
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ * 0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U)
+/*! SETCLR3 - Set/Clear Operation on Output n
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ * 0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U)
+/*! SETCLR4 - Set/Clear Operation on Output n
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ * 0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U)
+/*! SETCLR5 - Set/Clear Operation on Output n
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ * 0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U)
+/*! SETCLR6 - Set/Clear Operation on Output n
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ * 0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U)
+/*! SETCLR7 - Set/Clear Operation on Output n
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ * 0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U)
+/*! SETCLR8 - Set/Clear Operation on Output n
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ * 0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U)
+/*! SETCLR9 - Set/Clear Operation on Output n
+ * 0b00..Set and clear do not depend on the direction of any counter.
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
+ * 0b11..Reserved. Do not program this value.
+ */
+#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
+/*! @} */
+
+/*! @name RES - Output Conflict Resolution */
+/*! @{ */
+#define SCT_RES_O0RES_MASK (0x3U)
+#define SCT_RES_O0RES_SHIFT (0U)
+/*! O0RES - Effect of simultaneous set and clear on output n
+ * 0b00..No change
+ * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b11..Toggle output
+ */
+#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
+#define SCT_RES_O1RES_MASK (0xCU)
+#define SCT_RES_O1RES_SHIFT (2U)
+/*! O1RES - Effect of simultaneous set and clear on output n
+ * 0b00..No change
+ * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b11..Toggle output
+ */
+#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
+#define SCT_RES_O2RES_MASK (0x30U)
+#define SCT_RES_O2RES_SHIFT (4U)
+/*! O2RES - Effect of simultaneous set and clear on output n
+ * 0b00..No change
+ * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b11..Toggle output
+ */
+#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
+#define SCT_RES_O3RES_MASK (0xC0U)
+#define SCT_RES_O3RES_SHIFT (6U)
+/*! O3RES - Effect of simultaneous set and clear on output n
+ * 0b00..No change
+ * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b11..Toggle output
+ */
+#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
+#define SCT_RES_O4RES_MASK (0x300U)
+#define SCT_RES_O4RES_SHIFT (8U)
+/*! O4RES - Effect of simultaneous set and clear on output n
+ * 0b00..No change
+ * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b11..Toggle output
+ */
+#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
+#define SCT_RES_O5RES_MASK (0xC00U)
+#define SCT_RES_O5RES_SHIFT (10U)
+/*! O5RES - Effect of simultaneous set and clear on output n
+ * 0b00..No change
+ * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b11..Toggle output
+ */
+#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
+#define SCT_RES_O6RES_MASK (0x3000U)
+#define SCT_RES_O6RES_SHIFT (12U)
+/*! O6RES - Effect of simultaneous set and clear on output n
+ * 0b00..No change
+ * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b11..Toggle output
+ */
+#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
+#define SCT_RES_O7RES_MASK (0xC000U)
+#define SCT_RES_O7RES_SHIFT (14U)
+/*! O7RES - Effect of simultaneous set and clear on output n
+ * 0b00..No change
+ * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b11..Toggle output
+ */
+#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
+#define SCT_RES_O8RES_MASK (0x30000U)
+#define SCT_RES_O8RES_SHIFT (16U)
+/*! O8RES - Effect of simultaneous set and clear on output n
+ * 0b00..No change
+ * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b11..Toggle output
+ */
+#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
+#define SCT_RES_O9RES_MASK (0xC0000U)
+#define SCT_RES_O9RES_SHIFT (18U)
+/*! O9RES - Effect of simultaneous set and clear on output n
+ * 0b00..No change
+ * 0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
+ * 0b11..Toggle output
+ */
+#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
+/*! @} */
+
+/*! @name DMAREQ0 - DMA Request 0 */
+/*! @{ */
+#define SCT_DMAREQ0_DEV_0_MASK (0x1U)
+#define SCT_DMAREQ0_DEV_0_SHIFT (0U)
+/*! DEV_0 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK)
+#define SCT_DMAREQ0_DEV_1_MASK (0x2U)
+#define SCT_DMAREQ0_DEV_1_SHIFT (1U)
+/*! DEV_1 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_1_SHIFT)) & SCT_DMAREQ0_DEV_1_MASK)
+#define SCT_DMAREQ0_DEV_2_MASK (0x4U)
+#define SCT_DMAREQ0_DEV_2_SHIFT (2U)
+/*! DEV_2 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_2(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_2_SHIFT)) & SCT_DMAREQ0_DEV_2_MASK)
+#define SCT_DMAREQ0_DEV_3_MASK (0x8U)
+#define SCT_DMAREQ0_DEV_3_SHIFT (3U)
+/*! DEV_3 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_3(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_3_SHIFT)) & SCT_DMAREQ0_DEV_3_MASK)
+#define SCT_DMAREQ0_DEV_4_MASK (0x10U)
+#define SCT_DMAREQ0_DEV_4_SHIFT (4U)
+/*! DEV_4 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_4(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_4_SHIFT)) & SCT_DMAREQ0_DEV_4_MASK)
+#define SCT_DMAREQ0_DEV_5_MASK (0x20U)
+#define SCT_DMAREQ0_DEV_5_SHIFT (5U)
+/*! DEV_5 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_5(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_5_SHIFT)) & SCT_DMAREQ0_DEV_5_MASK)
+#define SCT_DMAREQ0_DEV_6_MASK (0x40U)
+#define SCT_DMAREQ0_DEV_6_SHIFT (6U)
+/*! DEV_6 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_6(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_6_SHIFT)) & SCT_DMAREQ0_DEV_6_MASK)
+#define SCT_DMAREQ0_DEV_7_MASK (0x80U)
+#define SCT_DMAREQ0_DEV_7_SHIFT (7U)
+/*! DEV_7 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_7(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_7_SHIFT)) & SCT_DMAREQ0_DEV_7_MASK)
+#define SCT_DMAREQ0_DEV_8_MASK (0x100U)
+#define SCT_DMAREQ0_DEV_8_SHIFT (8U)
+/*! DEV_8 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_8(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_8_SHIFT)) & SCT_DMAREQ0_DEV_8_MASK)
+#define SCT_DMAREQ0_DEV_9_MASK (0x200U)
+#define SCT_DMAREQ0_DEV_9_SHIFT (9U)
+/*! DEV_9 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_9(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_9_SHIFT)) & SCT_DMAREQ0_DEV_9_MASK)
+#define SCT_DMAREQ0_DEV_10_MASK (0x400U)
+#define SCT_DMAREQ0_DEV_10_SHIFT (10U)
+/*! DEV_10 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_10(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_10_SHIFT)) & SCT_DMAREQ0_DEV_10_MASK)
+#define SCT_DMAREQ0_DEV_11_MASK (0x800U)
+#define SCT_DMAREQ0_DEV_11_SHIFT (11U)
+/*! DEV_11 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_11(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_11_SHIFT)) & SCT_DMAREQ0_DEV_11_MASK)
+#define SCT_DMAREQ0_DEV_12_MASK (0x1000U)
+#define SCT_DMAREQ0_DEV_12_SHIFT (12U)
+/*! DEV_12 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_12(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_12_SHIFT)) & SCT_DMAREQ0_DEV_12_MASK)
+#define SCT_DMAREQ0_DEV_13_MASK (0x2000U)
+#define SCT_DMAREQ0_DEV_13_SHIFT (13U)
+/*! DEV_13 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_13(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_13_SHIFT)) & SCT_DMAREQ0_DEV_13_MASK)
+#define SCT_DMAREQ0_DEV_14_MASK (0x4000U)
+#define SCT_DMAREQ0_DEV_14_SHIFT (14U)
+/*! DEV_14 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_14(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_14_SHIFT)) & SCT_DMAREQ0_DEV_14_MASK)
+#define SCT_DMAREQ0_DEV_15_MASK (0x8000U)
+#define SCT_DMAREQ0_DEV_15_SHIFT (15U)
+/*! DEV_15 - DMA Request Event n
+ */
+#define SCT_DMAREQ0_DEV_15(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_15_SHIFT)) & SCT_DMAREQ0_DEV_15_MASK)
+#define SCT_DMAREQ0_DRL0_MASK (0x40000000U)
+#define SCT_DMAREQ0_DRL0_SHIFT (30U)
+/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.
+ */
+#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK)
+#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U)
+#define SCT_DMAREQ0_DRQ0_SHIFT (31U)
+/*! DRQ0 - DMA Request 0 State
+ */
+#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK)
+/*! @} */
+
+/*! @name DMAREQ1 - DMA Request 1 */
+/*! @{ */
+#define SCT_DMAREQ1_DEV_0_MASK (0x1U)
+#define SCT_DMAREQ1_DEV_0_SHIFT (0U)
+/*! DEV_0 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_0_SHIFT)) & SCT_DMAREQ1_DEV_0_MASK)
+#define SCT_DMAREQ1_DEV_1_MASK (0x2U)
+#define SCT_DMAREQ1_DEV_1_SHIFT (1U)
+/*! DEV_1 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK)
+#define SCT_DMAREQ1_DEV_2_MASK (0x4U)
+#define SCT_DMAREQ1_DEV_2_SHIFT (2U)
+/*! DEV_2 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_2(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_2_SHIFT)) & SCT_DMAREQ1_DEV_2_MASK)
+#define SCT_DMAREQ1_DEV_3_MASK (0x8U)
+#define SCT_DMAREQ1_DEV_3_SHIFT (3U)
+/*! DEV_3 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_3(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_3_SHIFT)) & SCT_DMAREQ1_DEV_3_MASK)
+#define SCT_DMAREQ1_DEV_4_MASK (0x10U)
+#define SCT_DMAREQ1_DEV_4_SHIFT (4U)
+/*! DEV_4 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_4(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_4_SHIFT)) & SCT_DMAREQ1_DEV_4_MASK)
+#define SCT_DMAREQ1_DEV_5_MASK (0x20U)
+#define SCT_DMAREQ1_DEV_5_SHIFT (5U)
+/*! DEV_5 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_5(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_5_SHIFT)) & SCT_DMAREQ1_DEV_5_MASK)
+#define SCT_DMAREQ1_DEV_6_MASK (0x40U)
+#define SCT_DMAREQ1_DEV_6_SHIFT (6U)
+/*! DEV_6 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_6(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_6_SHIFT)) & SCT_DMAREQ1_DEV_6_MASK)
+#define SCT_DMAREQ1_DEV_7_MASK (0x80U)
+#define SCT_DMAREQ1_DEV_7_SHIFT (7U)
+/*! DEV_7 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_7(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_7_SHIFT)) & SCT_DMAREQ1_DEV_7_MASK)
+#define SCT_DMAREQ1_DEV_8_MASK (0x100U)
+#define SCT_DMAREQ1_DEV_8_SHIFT (8U)
+/*! DEV_8 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_8(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_8_SHIFT)) & SCT_DMAREQ1_DEV_8_MASK)
+#define SCT_DMAREQ1_DEV_9_MASK (0x200U)
+#define SCT_DMAREQ1_DEV_9_SHIFT (9U)
+/*! DEV_9 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_9(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_9_SHIFT)) & SCT_DMAREQ1_DEV_9_MASK)
+#define SCT_DMAREQ1_DEV_10_MASK (0x400U)
+#define SCT_DMAREQ1_DEV_10_SHIFT (10U)
+/*! DEV_10 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_10(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_10_SHIFT)) & SCT_DMAREQ1_DEV_10_MASK)
+#define SCT_DMAREQ1_DEV_11_MASK (0x800U)
+#define SCT_DMAREQ1_DEV_11_SHIFT (11U)
+/*! DEV_11 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_11(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_11_SHIFT)) & SCT_DMAREQ1_DEV_11_MASK)
+#define SCT_DMAREQ1_DEV_12_MASK (0x1000U)
+#define SCT_DMAREQ1_DEV_12_SHIFT (12U)
+/*! DEV_12 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_12(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_12_SHIFT)) & SCT_DMAREQ1_DEV_12_MASK)
+#define SCT_DMAREQ1_DEV_13_MASK (0x2000U)
+#define SCT_DMAREQ1_DEV_13_SHIFT (13U)
+/*! DEV_13 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_13(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_13_SHIFT)) & SCT_DMAREQ1_DEV_13_MASK)
+#define SCT_DMAREQ1_DEV_14_MASK (0x4000U)
+#define SCT_DMAREQ1_DEV_14_SHIFT (14U)
+/*! DEV_14 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_14(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_14_SHIFT)) & SCT_DMAREQ1_DEV_14_MASK)
+#define SCT_DMAREQ1_DEV_15_MASK (0x8000U)
+#define SCT_DMAREQ1_DEV_15_SHIFT (15U)
+/*! DEV_15 - DMA Request Event n
+ */
+#define SCT_DMAREQ1_DEV_15(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_15_SHIFT)) & SCT_DMAREQ1_DEV_15_MASK)
+#define SCT_DMAREQ1_DRL1_MASK (0x40000000U)
+#define SCT_DMAREQ1_DRL1_SHIFT (30U)
+/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
+ */
+#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK)
+#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U)
+#define SCT_DMAREQ1_DRQ1_SHIFT (31U)
+/*! DRQ1 - DMA Request 1 State
+ */
+#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK)
+/*! @} */
+
+/*! @name EVEN - Event Interrupt Enable */
+/*! @{ */
+#define SCT_EVEN_IEN0_MASK (0x1U)
+#define SCT_EVEN_IEN0_SHIFT (0U)
+/*! IEN0 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN0_SHIFT)) & SCT_EVEN_IEN0_MASK)
+#define SCT_EVEN_IEN1_MASK (0x2U)
+#define SCT_EVEN_IEN1_SHIFT (1U)
+/*! IEN1 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN1_SHIFT)) & SCT_EVEN_IEN1_MASK)
+#define SCT_EVEN_IEN2_MASK (0x4U)
+#define SCT_EVEN_IEN2_SHIFT (2U)
+/*! IEN2 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN2_SHIFT)) & SCT_EVEN_IEN2_MASK)
+#define SCT_EVEN_IEN3_MASK (0x8U)
+#define SCT_EVEN_IEN3_SHIFT (3U)
+/*! IEN3 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN3_SHIFT)) & SCT_EVEN_IEN3_MASK)
+#define SCT_EVEN_IEN4_MASK (0x10U)
+#define SCT_EVEN_IEN4_SHIFT (4U)
+/*! IEN4 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN4_SHIFT)) & SCT_EVEN_IEN4_MASK)
+#define SCT_EVEN_IEN5_MASK (0x20U)
+#define SCT_EVEN_IEN5_SHIFT (5U)
+/*! IEN5 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN5_SHIFT)) & SCT_EVEN_IEN5_MASK)
+#define SCT_EVEN_IEN6_MASK (0x40U)
+#define SCT_EVEN_IEN6_SHIFT (6U)
+/*! IEN6 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN6_SHIFT)) & SCT_EVEN_IEN6_MASK)
+#define SCT_EVEN_IEN7_MASK (0x80U)
+#define SCT_EVEN_IEN7_SHIFT (7U)
+/*! IEN7 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN7_SHIFT)) & SCT_EVEN_IEN7_MASK)
+#define SCT_EVEN_IEN8_MASK (0x100U)
+#define SCT_EVEN_IEN8_SHIFT (8U)
+/*! IEN8 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN8_SHIFT)) & SCT_EVEN_IEN8_MASK)
+#define SCT_EVEN_IEN9_MASK (0x200U)
+#define SCT_EVEN_IEN9_SHIFT (9U)
+/*! IEN9 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN9_SHIFT)) & SCT_EVEN_IEN9_MASK)
+#define SCT_EVEN_IEN10_MASK (0x400U)
+#define SCT_EVEN_IEN10_SHIFT (10U)
+/*! IEN10 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN10_SHIFT)) & SCT_EVEN_IEN10_MASK)
+#define SCT_EVEN_IEN11_MASK (0x800U)
+#define SCT_EVEN_IEN11_SHIFT (11U)
+/*! IEN11 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN11_SHIFT)) & SCT_EVEN_IEN11_MASK)
+#define SCT_EVEN_IEN12_MASK (0x1000U)
+#define SCT_EVEN_IEN12_SHIFT (12U)
+/*! IEN12 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN12_SHIFT)) & SCT_EVEN_IEN12_MASK)
+#define SCT_EVEN_IEN13_MASK (0x2000U)
+#define SCT_EVEN_IEN13_SHIFT (13U)
+/*! IEN13 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN13_SHIFT)) & SCT_EVEN_IEN13_MASK)
+#define SCT_EVEN_IEN14_MASK (0x4000U)
+#define SCT_EVEN_IEN14_SHIFT (14U)
+/*! IEN14 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN14_SHIFT)) & SCT_EVEN_IEN14_MASK)
+#define SCT_EVEN_IEN15_MASK (0x8000U)
+#define SCT_EVEN_IEN15_SHIFT (15U)
+/*! IEN15 - Event Interrupt Enable n
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define SCT_EVEN_IEN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN15_SHIFT)) & SCT_EVEN_IEN15_MASK)
+/*! @} */
+
+/*! @name EVFLAG - Event Flag */
+/*! @{ */
+#define SCT_EVFLAG_FLAG0_MASK (0x1U)
+#define SCT_EVFLAG_FLAG0_SHIFT (0U)
+/*! FLAG0 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG0_SHIFT)) & SCT_EVFLAG_FLAG0_MASK)
+#define SCT_EVFLAG_FLAG1_MASK (0x2U)
+#define SCT_EVFLAG_FLAG1_SHIFT (1U)
+/*! FLAG1 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG1_SHIFT)) & SCT_EVFLAG_FLAG1_MASK)
+#define SCT_EVFLAG_FLAG2_MASK (0x4U)
+#define SCT_EVFLAG_FLAG2_SHIFT (2U)
+/*! FLAG2 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG2_SHIFT)) & SCT_EVFLAG_FLAG2_MASK)
+#define SCT_EVFLAG_FLAG3_MASK (0x8U)
+#define SCT_EVFLAG_FLAG3_SHIFT (3U)
+/*! FLAG3 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG3_SHIFT)) & SCT_EVFLAG_FLAG3_MASK)
+#define SCT_EVFLAG_FLAG4_MASK (0x10U)
+#define SCT_EVFLAG_FLAG4_SHIFT (4U)
+/*! FLAG4 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG4_SHIFT)) & SCT_EVFLAG_FLAG4_MASK)
+#define SCT_EVFLAG_FLAG5_MASK (0x20U)
+#define SCT_EVFLAG_FLAG5_SHIFT (5U)
+/*! FLAG5 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG5_SHIFT)) & SCT_EVFLAG_FLAG5_MASK)
+#define SCT_EVFLAG_FLAG6_MASK (0x40U)
+#define SCT_EVFLAG_FLAG6_SHIFT (6U)
+/*! FLAG6 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG6_SHIFT)) & SCT_EVFLAG_FLAG6_MASK)
+#define SCT_EVFLAG_FLAG7_MASK (0x80U)
+#define SCT_EVFLAG_FLAG7_SHIFT (7U)
+/*! FLAG7 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG7_SHIFT)) & SCT_EVFLAG_FLAG7_MASK)
+#define SCT_EVFLAG_FLAG8_MASK (0x100U)
+#define SCT_EVFLAG_FLAG8_SHIFT (8U)
+/*! FLAG8 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG8(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG8_SHIFT)) & SCT_EVFLAG_FLAG8_MASK)
+#define SCT_EVFLAG_FLAG9_MASK (0x200U)
+#define SCT_EVFLAG_FLAG9_SHIFT (9U)
+/*! FLAG9 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG9(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG9_SHIFT)) & SCT_EVFLAG_FLAG9_MASK)
+#define SCT_EVFLAG_FLAG10_MASK (0x400U)
+#define SCT_EVFLAG_FLAG10_SHIFT (10U)
+/*! FLAG10 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG10(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG10_SHIFT)) & SCT_EVFLAG_FLAG10_MASK)
+#define SCT_EVFLAG_FLAG11_MASK (0x800U)
+#define SCT_EVFLAG_FLAG11_SHIFT (11U)
+/*! FLAG11 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG11(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG11_SHIFT)) & SCT_EVFLAG_FLAG11_MASK)
+#define SCT_EVFLAG_FLAG12_MASK (0x1000U)
+#define SCT_EVFLAG_FLAG12_SHIFT (12U)
+/*! FLAG12 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG12(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG12_SHIFT)) & SCT_EVFLAG_FLAG12_MASK)
+#define SCT_EVFLAG_FLAG13_MASK (0x2000U)
+#define SCT_EVFLAG_FLAG13_SHIFT (13U)
+/*! FLAG13 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG13(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG13_SHIFT)) & SCT_EVFLAG_FLAG13_MASK)
+#define SCT_EVFLAG_FLAG14_MASK (0x4000U)
+#define SCT_EVFLAG_FLAG14_SHIFT (14U)
+/*! FLAG14 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG14(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG14_SHIFT)) & SCT_EVFLAG_FLAG14_MASK)
+#define SCT_EVFLAG_FLAG15_MASK (0x8000U)
+#define SCT_EVFLAG_FLAG15_SHIFT (15U)
+/*! FLAG15 - Event Flag n
+ * 0b0..No Flag
+ * 0b1..Event n Flag
+ */
+#define SCT_EVFLAG_FLAG15(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG15_SHIFT)) & SCT_EVFLAG_FLAG15_MASK)
+/*! @} */
+
+/*! @name CONEN - Conflict Interrupt Enable */
+/*! @{ */
+#define SCT_CONEN_NCEN0_MASK (0x1U)
+#define SCT_CONEN_NCEN0_SHIFT (0U)
+/*! NCEN0 - No Change Conflict Event/Interrupt Enable
+ * 0b0..No interrupt
+ * 0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN0_SHIFT)) & SCT_CONEN_NCEN0_MASK)
+#define SCT_CONEN_NCEN1_MASK (0x2U)
+#define SCT_CONEN_NCEN1_SHIFT (1U)
+/*! NCEN1 - No Change Conflict Event/Interrupt Enable
+ * 0b0..No interrupt
+ * 0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN1_SHIFT)) & SCT_CONEN_NCEN1_MASK)
+#define SCT_CONEN_NCEN2_MASK (0x4U)
+#define SCT_CONEN_NCEN2_SHIFT (2U)
+/*! NCEN2 - No Change Conflict Event/Interrupt Enable
+ * 0b0..No interrupt
+ * 0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN2_SHIFT)) & SCT_CONEN_NCEN2_MASK)
+#define SCT_CONEN_NCEN3_MASK (0x8U)
+#define SCT_CONEN_NCEN3_SHIFT (3U)
+/*! NCEN3 - No Change Conflict Event/Interrupt Enable
+ * 0b0..No interrupt
+ * 0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN3_SHIFT)) & SCT_CONEN_NCEN3_MASK)
+#define SCT_CONEN_NCEN4_MASK (0x10U)
+#define SCT_CONEN_NCEN4_SHIFT (4U)
+/*! NCEN4 - No Change Conflict Event/Interrupt Enable
+ * 0b0..No interrupt
+ * 0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN4_SHIFT)) & SCT_CONEN_NCEN4_MASK)
+#define SCT_CONEN_NCEN5_MASK (0x20U)
+#define SCT_CONEN_NCEN5_SHIFT (5U)
+/*! NCEN5 - No Change Conflict Event/Interrupt Enable
+ * 0b0..No interrupt
+ * 0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN5_SHIFT)) & SCT_CONEN_NCEN5_MASK)
+#define SCT_CONEN_NCEN6_MASK (0x40U)
+#define SCT_CONEN_NCEN6_SHIFT (6U)
+/*! NCEN6 - No Change Conflict Event/Interrupt Enable
+ * 0b0..No interrupt
+ * 0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN6_SHIFT)) & SCT_CONEN_NCEN6_MASK)
+#define SCT_CONEN_NCEN7_MASK (0x80U)
+#define SCT_CONEN_NCEN7_SHIFT (7U)
+/*! NCEN7 - No Change Conflict Event/Interrupt Enable
+ * 0b0..No interrupt
+ * 0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN7_SHIFT)) & SCT_CONEN_NCEN7_MASK)
+#define SCT_CONEN_NCEN8_MASK (0x100U)
+#define SCT_CONEN_NCEN8_SHIFT (8U)
+/*! NCEN8 - No Change Conflict Event/Interrupt Enable
+ * 0b0..No interrupt
+ * 0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN8_SHIFT)) & SCT_CONEN_NCEN8_MASK)
+#define SCT_CONEN_NCEN9_MASK (0x200U)
+#define SCT_CONEN_NCEN9_SHIFT (9U)
+/*! NCEN9 - No Change Conflict Event/Interrupt Enable
+ * 0b0..No interrupt
+ * 0b1..Interrupt
+ */
+#define SCT_CONEN_NCEN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN9_SHIFT)) & SCT_CONEN_NCEN9_MASK)
+/*! @} */
+
+/*! @name CONFLAG - Conflict Flag */
+/*! @{ */
+#define SCT_CONFLAG_NCFLAG0_MASK (0x1U)
+#define SCT_CONFLAG_NCFLAG0_SHIFT (0U)
+/*! NCFLAG0 - No Change Conflict Event Flag
+ * 0b0..No Conflict Event
+ * 0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG0(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG0_SHIFT)) & SCT_CONFLAG_NCFLAG0_MASK)
+#define SCT_CONFLAG_NCFLAG1_MASK (0x2U)
+#define SCT_CONFLAG_NCFLAG1_SHIFT (1U)
+/*! NCFLAG1 - No Change Conflict Event Flag
+ * 0b0..No Conflict Event
+ * 0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG1(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG1_SHIFT)) & SCT_CONFLAG_NCFLAG1_MASK)
+#define SCT_CONFLAG_NCFLAG2_MASK (0x4U)
+#define SCT_CONFLAG_NCFLAG2_SHIFT (2U)
+/*! NCFLAG2 - No Change Conflict Event Flag
+ * 0b0..No Conflict Event
+ * 0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG2(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG2_SHIFT)) & SCT_CONFLAG_NCFLAG2_MASK)
+#define SCT_CONFLAG_NCFLAG3_MASK (0x8U)
+#define SCT_CONFLAG_NCFLAG3_SHIFT (3U)
+/*! NCFLAG3 - No Change Conflict Event Flag
+ * 0b0..No Conflict Event
+ * 0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG3(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG3_SHIFT)) & SCT_CONFLAG_NCFLAG3_MASK)
+#define SCT_CONFLAG_NCFLAG4_MASK (0x10U)
+#define SCT_CONFLAG_NCFLAG4_SHIFT (4U)
+/*! NCFLAG4 - No Change Conflict Event Flag
+ * 0b0..No Conflict Event
+ * 0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG4(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG4_SHIFT)) & SCT_CONFLAG_NCFLAG4_MASK)
+#define SCT_CONFLAG_NCFLAG5_MASK (0x20U)
+#define SCT_CONFLAG_NCFLAG5_SHIFT (5U)
+/*! NCFLAG5 - No Change Conflict Event Flag
+ * 0b0..No Conflict Event
+ * 0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG5(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG5_SHIFT)) & SCT_CONFLAG_NCFLAG5_MASK)
+#define SCT_CONFLAG_NCFLAG6_MASK (0x40U)
+#define SCT_CONFLAG_NCFLAG6_SHIFT (6U)
+/*! NCFLAG6 - No Change Conflict Event Flag
+ * 0b0..No Conflict Event
+ * 0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG6(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG6_SHIFT)) & SCT_CONFLAG_NCFLAG6_MASK)
+#define SCT_CONFLAG_NCFLAG7_MASK (0x80U)
+#define SCT_CONFLAG_NCFLAG7_SHIFT (7U)
+/*! NCFLAG7 - No Change Conflict Event Flag
+ * 0b0..No Conflict Event
+ * 0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG7(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG7_SHIFT)) & SCT_CONFLAG_NCFLAG7_MASK)
+#define SCT_CONFLAG_NCFLAG8_MASK (0x100U)
+#define SCT_CONFLAG_NCFLAG8_SHIFT (8U)
+/*! NCFLAG8 - No Change Conflict Event Flag
+ * 0b0..No Conflict Event
+ * 0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG8(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG8_SHIFT)) & SCT_CONFLAG_NCFLAG8_MASK)
+#define SCT_CONFLAG_NCFLAG9_MASK (0x200U)
+#define SCT_CONFLAG_NCFLAG9_SHIFT (9U)
+/*! NCFLAG9 - No Change Conflict Event Flag
+ * 0b0..No Conflict Event
+ * 0b1..A No Change Conflict Event occured
+ */
+#define SCT_CONFLAG_NCFLAG9(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG9_SHIFT)) & SCT_CONFLAG_NCFLAG9_MASK)
+#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U)
+#define SCT_CONFLAG_BUSERRL_SHIFT (30U)
+/*! BUSERRL - Bus Error Low/Unified
+ */
+#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
+#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U)
+#define SCT_CONFLAG_BUSERRH_SHIFT (31U)
+/*! BUSERRH - Bus Error High
+ */
+#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
+/*! @} */
+
+/*! @name CAPL - SCT_CAPL register */
+/*! @{ */
+#define SCT_CAPL_CAPL_MASK (0xFFFFU)
+#define SCT_CAPL_CAPL_SHIFT (0U)
+#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK)
+/*! @} */
+
+/* The count of SCT_CAPL */
+#define SCT_CAPL_COUNT (16U)
+
+/*! @name CAPH - SCT_CAPH register */
+/*! @{ */
+#define SCT_CAPH_CAPH_MASK (0xFFFFU)
+#define SCT_CAPH_CAPH_SHIFT (0U)
+#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK)
+/*! @} */
+
+/* The count of SCT_CAPH */
+#define SCT_CAPH_COUNT (16U)
+
+/*! @name CAP - Capture Value */
+/*! @{ */
+#define SCT_CAP_CAPn_L_MASK (0xFFFFU)
+#define SCT_CAP_CAPn_L_SHIFT (0U)
+/*! CAPn_L - Capture n Low
+ */
+#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK)
+#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U)
+#define SCT_CAP_CAPn_H_SHIFT (16U)
+/*! CAPn_H - Capture n High
+ */
+#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK)
+/*! @} */
+
+/* The count of SCT_CAP */
+#define SCT_CAP_COUNT (16U)
+
+/*! @name MATCHL - SCT_MATCHL register */
+/*! @{ */
+#define SCT_MATCHL_MATCHL_MASK (0xFFFFU)
+#define SCT_MATCHL_MATCHL_SHIFT (0U)
+#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHL */
+#define SCT_MATCHL_COUNT (16U)
+
+/*! @name MATCHH - SCT_MATCHH register */
+/*! @{ */
+#define SCT_MATCHH_MATCHH_MASK (0xFFFFU)
+#define SCT_MATCHH_MATCHH_SHIFT (0U)
+#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHH */
+#define SCT_MATCHH_COUNT (16U)
+
+/*! @name MATCH - Match Value */
+/*! @{ */
+#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU)
+#define SCT_MATCH_MATCHn_L_SHIFT (0U)
+/*! MATCHn_L - Match n Low
+ */
+#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK)
+#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U)
+#define SCT_MATCH_MATCHn_H_SHIFT (16U)
+/*! MATCHn_H - Match n High
+ */
+#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK)
+/*! @} */
+
+/* The count of SCT_MATCH */
+#define SCT_MATCH_COUNT (16U)
+
+/*! @name CAPCTRLL - SCT_CAPCTRLL register */
+/*! @{ */
+#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU)
+#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U)
+#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK)
+/*! @} */
+
+/* The count of SCT_CAPCTRLL */
+#define SCT_CAPCTRLL_COUNT (16U)
+
+/*! @name CAPCTRLH - SCT_CAPCTRLH register */
+/*! @{ */
+#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU)
+#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U)
+#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK)
+/*! @} */
+
+/* The count of SCT_CAPCTRLH */
+#define SCT_CAPCTRLH_COUNT (16U)
+
+/*! @name CAPCTRL - Capture Control */
+/*! @{ */
+#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU)
+#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U)
+/*! CAPCONn_L - Capture Control n Low
+ */
+#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK)
+#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U)
+#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U)
+/*! CAPCONn_H - Capture Control n High
+ */
+#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK)
+/*! @} */
+
+/* The count of SCT_CAPCTRL */
+#define SCT_CAPCTRL_COUNT (16U)
+
+/*! @name MATCHRELL - SCT_MATCHRELL register */
+/*! @{ */
+#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU)
+#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U)
+#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHRELL */
+#define SCT_MATCHRELL_COUNT (16U)
+
+/*! @name MATCHRELH - SCT_MATCHRELH register */
+/*! @{ */
+#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU)
+#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U)
+#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHRELH */
+#define SCT_MATCHRELH_COUNT (16U)
+
+/*! @name MATCHREL - Match Reload Value */
+/*! @{ */
+#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU)
+#define SCT_MATCHREL_RELOADn_L_SHIFT (0U)
+/*! RELOADn_L - Reload n Low
+ */
+#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK)
+#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U)
+#define SCT_MATCHREL_RELOADn_H_SHIFT (16U)
+/*! RELOADn_H - Reload n High
+ */
+#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHREL */
+#define SCT_MATCHREL_COUNT (16U)
+
+/*! @name EV_STATE - Event n State */
+/*! @{ */
+#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFFFFFU)
+#define SCT_EV_STATE_STATEMSKn_SHIFT (0U)
+/*! STATEMSKn - Event State Mask n
+ */
+#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK)
+/*! @} */
+
+/* The count of SCT_EV_STATE */
+#define SCT_EV_STATE_COUNT (16U)
+
+/*! @name EV_CTRL - Event n Control */
+/*! @{ */
+#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU)
+#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U)
+/*! MATCHSEL - Match Select
+ */
+#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)
+#define SCT_EV_CTRL_HEVENT_MASK (0x10U)
+#define SCT_EV_CTRL_HEVENT_SHIFT (4U)
+/*! HEVENT - High Event
+ * 0b0..Low Counter
+ * 0b1..High Counter
+ */
+#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)
+#define SCT_EV_CTRL_OUTSEL_MASK (0x20U)
+#define SCT_EV_CTRL_OUTSEL_SHIFT (5U)
+/*! OUTSEL - Input/Output Select
+ * 0b0..Selects the inputs selected by IOSEL.
+ * 0b1..Selects the outputs selected by IOSEL.
+ */
+#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)
+#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U)
+#define SCT_EV_CTRL_IOSEL_SHIFT (6U)
+/*! IOSEL - Input/Output Signal Select
+ */
+#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK)
+#define SCT_EV_CTRL_IOCOND_MASK (0xC00U)
+#define SCT_EV_CTRL_IOCOND_SHIFT (10U)
+/*! IOCOND - Input/Output Condition
+ * 0b00..Low
+ * 0b01..Rise
+ * 0b10..Fall
+ * 0b11..High
+ */
+#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK)
+#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U)
+#define SCT_EV_CTRL_COMBMODE_SHIFT (12U)
+/*! COMBMODE - Combination Mode
+ * 0b00..OR. The event occurs when either the specified match or I/O condition occurs.
+ * 0b01..MATCH. Uses the specified match only.
+ * 0b10..IO. Uses the specified I/O condition only.
+ * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously.
+ */
+#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK)
+#define SCT_EV_CTRL_STATELD_MASK (0x4000U)
+#define SCT_EV_CTRL_STATELD_SHIFT (14U)
+/*! STATELD - State Load
+ * 0b0..Add. STATEV value is added into STATE (the carry-out is ignored).
+ * 0b1..Load. STATEV value is loaded into STATE.
+ */
+#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK)
+#define SCT_EV_CTRL_STATEV_MASK (0xF8000U)
+#define SCT_EV_CTRL_STATEV_SHIFT (15U)
+/*! STATEV - State Value
+ */
+#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK)
+#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U)
+#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U)
+/*! MATCHMEM - Match Mem
+ */
+#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK)
+#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U)
+#define SCT_EV_CTRL_DIRECTION_SHIFT (21U)
+/*! DIRECTION - Direction
+ * 0b00..Direction independent. This event is triggered regardless of the count direction.
+ * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1.
+ * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1.
+ * 0b11..Reserved
+ */
+#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK)
+/*! @} */
+
+/* The count of SCT_EV_CTRL */
+#define SCT_EV_CTRL_COUNT (16U)
+
+/*! @name OUT_SET - Output n Set */
+/*! @{ */
+#define SCT_OUT_SET_SET_MASK (0xFFFFU)
+#define SCT_OUT_SET_SET_SHIFT (0U)
+/*! SET - Set
+ */
+#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
+/*! @} */
+
+/* The count of SCT_OUT_SET */
+#define SCT_OUT_SET_COUNT (10U)
+
+/*! @name OUT_CLR - Output n Clear */
+/*! @{ */
+#define SCT_OUT_CLR_CLR_MASK (0xFFFFU)
+#define SCT_OUT_CLR_CLR_SHIFT (0U)
+/*! CLR - Clear
+ */
+#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
+/*! @} */
+
+/* The count of SCT_OUT_CLR */
+#define SCT_OUT_CLR_COUNT (10U)
+
+
+/*!
+ * @}
+ */ /* end of group SCT_Register_Masks */
+
+
+/* SCT - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral SCT0 base address */
+ #define SCT0_BASE (0x50146000u)
+ /** Peripheral SCT0 base address */
+ #define SCT0_BASE_NS (0x40146000u)
+ /** Peripheral SCT0 base pointer */
+ #define SCT0 ((SCT_Type *)SCT0_BASE)
+ /** Peripheral SCT0 base pointer */
+ #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS)
+ /** Array initializer of SCT peripheral base addresses */
+ #define SCT_BASE_ADDRS { SCT0_BASE }
+ /** Array initializer of SCT peripheral base pointers */
+ #define SCT_BASE_PTRS { SCT0 }
+ /** Array initializer of SCT peripheral base addresses */
+ #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS }
+ /** Array initializer of SCT peripheral base pointers */
+ #define SCT_BASE_PTRS_NS { SCT0_NS }
+#else
+ /** Peripheral SCT0 base address */
+ #define SCT0_BASE (0x40146000u)
+ /** Peripheral SCT0 base pointer */
+ #define SCT0 ((SCT_Type *)SCT0_BASE)
+ /** Array initializer of SCT peripheral base addresses */
+ #define SCT_BASE_ADDRS { SCT0_BASE }
+ /** Array initializer of SCT peripheral base pointers */
+ #define SCT_BASE_PTRS { SCT0 }
+#endif
+/** Interrupt vectors for the SCT peripheral type */
+#define SCT_IRQS { SCT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SCT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SEMA42 Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer
+ * @{
+ */
+
+/** SEMA42 - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t GATE3; /**< Gate Register, offset: 0x0 */
+ __IO uint8_t GATE2; /**< Gate Register, offset: 0x1 */
+ __IO uint8_t GATE1; /**< Gate Register, offset: 0x2 */
+ __IO uint8_t GATE0; /**< Gate Register, offset: 0x3 */
+ __IO uint8_t GATE7; /**< Gate Register, offset: 0x4 */
+ __IO uint8_t GATE6; /**< Gate Register, offset: 0x5 */
+ __IO uint8_t GATE5; /**< Gate Register, offset: 0x6 */
+ __IO uint8_t GATE4; /**< Gate Register, offset: 0x7 */
+ __IO uint8_t GATE11; /**< Gate Register, offset: 0x8 */
+ __IO uint8_t GATE10; /**< Gate Register, offset: 0x9 */
+ __IO uint8_t GATE9; /**< Gate Register, offset: 0xA */
+ __IO uint8_t GATE8; /**< Gate Register, offset: 0xB */
+ __IO uint8_t GATE15; /**< Gate Register, offset: 0xC */
+ __IO uint8_t GATE14; /**< Gate Register, offset: 0xD */
+ __IO uint8_t GATE13; /**< Gate Register, offset: 0xE */
+ __IO uint8_t GATE12; /**< Gate Register, offset: 0xF */
+ uint8_t RESERVED_0[50];
+ union { /* offset: 0x42 */
+ __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */
+ __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */
+ };
+} SEMA42_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SEMA42 Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks
+ * @{
+ */
+
+/*! @name GATE3 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE3_GTFSM_MASK (0xFU)
+#define SEMA42_GATE3_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE3_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE2 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE2_GTFSM_MASK (0xFU)
+#define SEMA42_GATE2_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE2_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE1 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE1_GTFSM_MASK (0xFU)
+#define SEMA42_GATE1_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE1_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE0 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE0_GTFSM_MASK (0xFU)
+#define SEMA42_GATE0_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE0_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE7 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE7_GTFSM_MASK (0xFU)
+#define SEMA42_GATE7_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE7_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE6 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE6_GTFSM_MASK (0xFU)
+#define SEMA42_GATE6_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE6_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE5 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE5_GTFSM_MASK (0xFU)
+#define SEMA42_GATE5_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE5_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE4 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE4_GTFSM_MASK (0xFU)
+#define SEMA42_GATE4_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE4_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE11 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE11_GTFSM_MASK (0xFU)
+#define SEMA42_GATE11_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE10 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE10_GTFSM_MASK (0xFU)
+#define SEMA42_GATE10_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE9 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE9_GTFSM_MASK (0xFU)
+#define SEMA42_GATE9_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE9_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE8 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE8_GTFSM_MASK (0xFU)
+#define SEMA42_GATE8_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE8_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE15 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE15_GTFSM_MASK (0xFU)
+#define SEMA42_GATE15_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE14 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE14_GTFSM_MASK (0xFU)
+#define SEMA42_GATE14_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE13 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE13_GTFSM_MASK (0xFU)
+#define SEMA42_GATE13_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE12 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE12_GTFSM_MASK (0xFU)
+#define SEMA42_GATE12_GTFSM_SHIFT (0U)
+/*! GTFSM - Gate finite state machine
+ * 0b0000..The gate is unlocked (free).
+ * 0b0001..Domain 0 locked the gate.
+ * 0b0010..Domain 1 locked the gate.
+ * 0b0011..Domain 2 locked the gate.
+ * 0b0100..Domain 3 locked the gate.
+ * 0b0101..Domain 4 locked the gate.
+ * 0b0110..Domain 5 locked the gate.
+ * 0b0111..Domain 6 locked the gate.
+ * 0b1000..Domain 7 locked the gate.
+ * 0b1001..Domain 8 locked the gate.
+ * 0b1010..Domain 9 locked the gate.
+ * 0b1011..Domain 10 locked the gate.
+ * 0b1100..Domain 11 locked the gate.
+ * 0b1101..Domain 12 locked the gate.
+ * 0b1110..Domain 13 locked the gate.
+ * 0b1111..Domain 14 locked the gate.
+ */
+#define SEMA42_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK)
+/*! @} */
+
+/*! @name RSTGT_R - Reset Gate Read */
+/*! @{ */
+#define SEMA42_RSTGT_R_RSTGTN_MASK (0xFFU)
+#define SEMA42_RSTGT_R_RSTGTN_SHIFT (0U)
+/*! RSTGTN - Reset gate number
+ */
+#define SEMA42_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK)
+#define SEMA42_RSTGT_R_RSTGMS_MASK (0xF00U)
+#define SEMA42_RSTGT_R_RSTGMS_SHIFT (8U)
+/*! RSTGMS - Reset gate domain
+ */
+#define SEMA42_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK)
+#define SEMA42_RSTGT_R_RSTGSM_MASK (0x3000U)
+#define SEMA42_RSTGT_R_RSTGSM_SHIFT (12U)
+/*! RSTGSM - Reset gate finite state machine
+ * 0b00..Idle, waiting for the first data pattern write.
+ * 0b01..Waiting for the second data pattern write
+ * 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed,
+ * this machine returns to the idle (waiting for first data pattern write) state.
+ * 0b11..This state encoding is never used and therefore reserved.
+ */
+#define SEMA42_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK)
+#define SEMA42_RSTGT_R_ROZ_MASK (0xC000U)
+#define SEMA42_RSTGT_R_ROZ_SHIFT (14U)
+/*! ROZ - ROZ
+ */
+#define SEMA42_RSTGT_R_ROZ(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_ROZ_SHIFT)) & SEMA42_RSTGT_R_ROZ_MASK)
+/*! @} */
+
+/*! @name RSTGT_W - Reset Gate Write */
+/*! @{ */
+#define SEMA42_RSTGT_W_RSTGTN_MASK (0xFFU)
+#define SEMA42_RSTGT_W_RSTGTN_SHIFT (0U)
+/*! RSTGTN - Reset gate number
+ */
+#define SEMA42_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK)
+#define SEMA42_RSTGT_W_RSTGDP_MASK (0xFF00U)
+#define SEMA42_RSTGT_W_RSTGDP_SHIFT (8U)
+/*! RSTGDP - Reset gate data pattern
+ */
+#define SEMA42_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SEMA42_Register_Masks */
+
+
+/* SEMA42 - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral SEMA42 base address */
+ #define SEMA42_BASE (0x50112000u)
+ /** Peripheral SEMA42 base address */
+ #define SEMA42_BASE_NS (0x40112000u)
+ /** Peripheral SEMA42 base pointer */
+ #define SEMA42 ((SEMA42_Type *)SEMA42_BASE)
+ /** Peripheral SEMA42 base pointer */
+ #define SEMA42_NS ((SEMA42_Type *)SEMA42_BASE_NS)
+ /** Array initializer of SEMA42 peripheral base addresses */
+ #define SEMA42_BASE_ADDRS { SEMA42_BASE }
+ /** Array initializer of SEMA42 peripheral base pointers */
+ #define SEMA42_BASE_PTRS { SEMA42 }
+ /** Array initializer of SEMA42 peripheral base addresses */
+ #define SEMA42_BASE_ADDRS_NS { SEMA42_BASE_NS }
+ /** Array initializer of SEMA42 peripheral base pointers */
+ #define SEMA42_BASE_PTRS_NS { SEMA42_NS }
+#else
+ /** Peripheral SEMA42 base address */
+ #define SEMA42_BASE (0x40112000u)
+ /** Peripheral SEMA42 base pointer */
+ #define SEMA42 ((SEMA42_Type *)SEMA42_BASE)
+ /** Array initializer of SEMA42 peripheral base addresses */
+ #define SEMA42_BASE_ADDRS { SEMA42_BASE }
+ /** Array initializer of SEMA42 peripheral base pointers */
+ #define SEMA42_BASE_PTRS { SEMA42 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group SEMA42_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[1024];
+ __IO uint32_t CFG; /**< Configuration Register, offset: 0x400 */
+ __IO uint32_t DLY; /**< Delay Register, offset: 0x404 */
+ __IO uint32_t STAT; /**< Status Register, offset: 0x408 */
+ __IO uint32_t INTENSET; /**< Interrupt Enable Register, offset: 0x40C */
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear Register, offset: 0x410 */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t DIV; /**< Clock Divider Register, offset: 0x424 */
+ __I uint32_t INTSTAT; /**< Interrupt Status Register, offset: 0x428 */
+ uint8_t RESERVED_2[2516];
+ __IO uint32_t FIFOCFG; /**< FIFO Configuration Register, offset: 0xE00 */
+ __IO uint32_t FIFOSTAT; /**< FIFO Status Register, offset: 0xE04 */
+ __IO uint32_t FIFOTRIG; /**< FIFO Trigger Register, offset: 0xE08 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t FIFOINTENSET; /**< FIFO Interrupt Enable Register, offset: 0xE10 */
+ __IO uint32_t FIFOINTENCLR; /**< FIFO Interrupt Enable Clear Register, offset: 0xE14 */
+ __I uint32_t FIFOINTSTAT; /**< FIFO Interrupt Status Register, offset: 0xE18 */
+ uint8_t RESERVED_4[4];
+ __O uint32_t FIFOWR; /**< FIFO Write Data Register, offset: 0xE20 */
+ uint8_t RESERVED_5[12];
+ __I uint32_t FIFORD; /**< FIFO Read Data Register, offset: 0xE30 */
+ uint8_t RESERVED_6[12];
+ __I uint32_t FIFORDNOPOP; /**< FIFO Data Read with no FIFO Pop Register, offset: 0xE40 */
+ uint8_t RESERVED_7[4];
+ __I uint32_t FIFOSIZE; /**< FIFO Size Register, offset: 0xE48 */
+ uint8_t RESERVED_8[432];
+ __I uint32_t ID; /**< Peripheral Identification Register, offset: 0xFFC */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name CFG - Configuration Register */
+/*! @{ */
+#define SPI_CFG_ENABLE_MASK (0x1U)
+#define SPI_CFG_ENABLE_SHIFT (0U)
+/*! ENABLE - SPI Enable
+ * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset.
+ * 0b1..Enabled. The SPI is enabled for operation.
+ */
+#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
+#define SPI_CFG_MASTER_MASK (0x4U)
+#define SPI_CFG_MASTER_SHIFT (2U)
+/*! MASTER - Master Mode Select
+ * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs; MISO is an output.
+ * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs; MISO is an input.
+ */
+#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
+#define SPI_CFG_LSBF_MASK (0x8U)
+#define SPI_CFG_LSBF_SHIFT (3U)
+/*! LSBF - LSB First Mode Enable
+ * 0b0..Standard. Data is transmitted and received in standard MSB-first order.
+ * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first).
+ */
+#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
+#define SPI_CFG_CPHA_MASK (0x10U)
+#define SPI_CFG_CPHA_SHIFT (4U)
+/*! CPHA - Clock Phase Select
+ * 0b0..Change
+ * 0b1..Capture
+ */
+#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
+#define SPI_CFG_CPOL_MASK (0x20U)
+#define SPI_CFG_CPOL_SHIFT (5U)
+/*! CPOL - Clock Polarity Select
+ * 0b0..Low. The rest state of the clock (between transfers) is low.
+ * 0b1..High. The rest state of the clock (between transfers) is high.
+ */
+#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
+#define SPI_CFG_LOOP_MASK (0x80U)
+#define SPI_CFG_LOOP_SHIFT (7U)
+/*! LOOP - Loopback Mode Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
+#define SPI_CFG_SPOL0_MASK (0x100U)
+#define SPI_CFG_SPOL0_SHIFT (8U)
+/*! SPOL0 - SSEL0 Polarity Select
+ * 0b0..Low. The SSEL0 pin is active low.
+ * 0b1..High. The SSEL0 pin is active high.
+ */
+#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
+#define SPI_CFG_SPOL1_MASK (0x200U)
+#define SPI_CFG_SPOL1_SHIFT (9U)
+/*! SPOL1 - SSEL1 Polarity Select
+ * 0b0..Low. The SSEL1 pin is active low.
+ * 0b1..High. The SSEL1 pin is active high.
+ */
+#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
+#define SPI_CFG_SPOL2_MASK (0x400U)
+#define SPI_CFG_SPOL2_SHIFT (10U)
+/*! SPOL2 - SSEL2 Polarity Select
+ * 0b0..Low. The SSEL2 pin is active low.
+ * 0b1..High. The SSEL2 pin is active high.
+ */
+#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
+#define SPI_CFG_SPOL3_MASK (0x800U)
+#define SPI_CFG_SPOL3_SHIFT (11U)
+/*! SPOL3 - SSEL3 Polarity Select
+ * 0b0..Low. The SSEL3 pin is active low.
+ * 0b1..High. The SSEL3 pin is active high.
+ */
+#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
+/*! @} */
+
+/*! @name DLY - Delay Register */
+/*! @{ */
+#define SPI_DLY_PRE_DELAY_MASK (0xFU)
+#define SPI_DLY_PRE_DELAY_SHIFT (0U)
+/*! PRE_DELAY - Pre-Delay
+ * 0b0000..No additional time is inserted
+ * 0b0001..1 SPI clock time is inserted
+ * 0b0010..2 SPI clock times are inserted
+ * 0b1111..15 SPI clock times are inserted
+ */
+#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
+#define SPI_DLY_POST_DELAY_MASK (0xF0U)
+#define SPI_DLY_POST_DELAY_SHIFT (4U)
+/*! POST_DELAY - Post-Delay
+ * 0b0000..No additional time is inserted
+ * 0b0001..1 SPI clock time is inserted
+ * 0b0010..2 SPI clock times are inserted
+ * 0b1111..15 SPI clock times are inserted
+ */
+#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
+#define SPI_DLY_FRAME_DELAY_MASK (0xF00U)
+#define SPI_DLY_FRAME_DELAY_SHIFT (8U)
+/*! FRAME_DELAY - Frame Delay
+ * 0b0000..No additional time is inserted
+ * 0b0001..1 SPI clock time is inserted
+ * 0b0010..2 SPI clock times are inserted
+ * 0b1111..15 SPI clock times are inserted
+ */
+#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
+#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U)
+#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U)
+/*! TRANSFER_DELAY - Transfer Delay
+ * 0b0000..The minimum time that SSEL is deasserted is 1 SPI clock time (zero-added time)
+ * 0b0001..The minimum time that SSEL is deasserted is 2 SPI clock times
+ * 0b0010..The minimum time that SSEL is deasserted is 3 SPI clock times
+ * 0b1111..The minimum time that SSEL is deasserted is 16 SPI clock times
+ */
+#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
+/*! @} */
+
+/*! @name STAT - Status Register */
+/*! @{ */
+#define SPI_STAT_SSA_MASK (0x10U)
+#define SPI_STAT_SSA_SHIFT (4U)
+/*! SSA - Slave Select Assert
+ */
+#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
+#define SPI_STAT_SSD_MASK (0x20U)
+#define SPI_STAT_SSD_SHIFT (5U)
+/*! SSD - Slave Select Deassert
+ */
+#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
+#define SPI_STAT_STALLED_MASK (0x40U)
+#define SPI_STAT_STALLED_SHIFT (6U)
+/*! STALLED - Stalled Status Flag
+ */
+#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
+#define SPI_STAT_ENDTRANSFER_MASK (0x80U)
+#define SPI_STAT_ENDTRANSFER_SHIFT (7U)
+/*! ENDTRANSFER - End Transfer Control
+ */
+#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
+#define SPI_STAT_MSTIDLE_MASK (0x100U)
+#define SPI_STAT_MSTIDLE_SHIFT (8U)
+/*! MSTIDLE - Master Idle Status Flag
+ */
+#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
+/*! @} */
+
+/*! @name INTENSET - Interrupt Enable Register */
+/*! @{ */
+#define SPI_INTENSET_SSAEN_MASK (0x10U)
+#define SPI_INTENSET_SSAEN_SHIFT (4U)
+/*! SSAEN - Slave Select Assert Interrupt Enable
+ * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
+ * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
+ */
+#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
+#define SPI_INTENSET_SSDEN_MASK (0x20U)
+#define SPI_INTENSET_SSDEN_SHIFT (5U)
+/*! SSDEN - Slave Select Deassert Interrupt Enable
+ * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
+ * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
+ */
+#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
+#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U)
+#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U)
+/*! MSTIDLEEN - Master Idle Interrupt Enable
+ * 0b0..No interrupt will be generated when the SPI master function is idle.
+ * 0b1..An interrupt will be generated when the SPI master function is fully idle.
+ */
+#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
+/*! @} */
+
+/*! @name INTENCLR - Interrupt Enable Clear Register */
+/*! @{ */
+#define SPI_INTENCLR_SSAEN_MASK (0x10U)
+#define SPI_INTENCLR_SSAEN_SHIFT (4U)
+/*! SSAEN - Slave Select Assert Interrupt Enable
+ * 0b0..No effect
+ * 0b1..Clear the Slave Select Assert Interrupt Enable bit (INTENSET[SSAEN])
+ */
+#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
+#define SPI_INTENCLR_SSDEN_MASK (0x20U)
+#define SPI_INTENCLR_SSDEN_SHIFT (5U)
+/*! SSDEN - Slave Select Deassert Interrupt Enable
+ * 0b0..No effect
+ * 0b1..Clear the Slave Select Deassert Interrupt Enable bit (INTENSET[SSDEN])
+ */
+#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
+#define SPI_INTENCLR_MSTIDLE_MASK (0x100U)
+#define SPI_INTENCLR_MSTIDLE_SHIFT (8U)
+/*! MSTIDLE - Master Idle Interrupt Enable
+ * 0b0..No effect
+ * 0b1..Clear the Master Idle Interrupt Enable bit (INTENSET[MSTIDLE])
+ */
+#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
+/*! @} */
+
+/*! @name DIV - Clock Divider Register */
+/*! @{ */
+#define SPI_DIV_DIVVAL_MASK (0xFFFFU)
+#define SPI_DIV_DIVVAL_SHIFT (0U)
+/*! DIVVAL - Rate Divider Value
+ */
+#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt Status Register */
+/*! @{ */
+#define SPI_INTSTAT_SSA_MASK (0x10U)
+#define SPI_INTSTAT_SSA_SHIFT (4U)
+/*! SSA - Slave Select Assert Interrupt
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
+#define SPI_INTSTAT_SSD_MASK (0x20U)
+#define SPI_INTSTAT_SSD_SHIFT (5U)
+/*! SSD - Slave Select Deassert Interrupt
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
+#define SPI_INTSTAT_MSTIDLE_MASK (0x100U)
+#define SPI_INTSTAT_MSTIDLE_SHIFT (8U)
+/*! MSTIDLE - Master Idle Status Flag Interrupt
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
+/*! @} */
+
+/*! @name FIFOCFG - FIFO Configuration Register */
+/*! @{ */
+#define SPI_FIFOCFG_ENABLETX_MASK (0x1U)
+#define SPI_FIFOCFG_ENABLETX_SHIFT (0U)
+/*! ENABLETX - Enable the Transmit FIFO
+ * 0b0..The transmit FIFO is not enabled
+ * 0b1..The transmit FIFO is enabled
+ */
+#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
+#define SPI_FIFOCFG_ENABLERX_MASK (0x2U)
+#define SPI_FIFOCFG_ENABLERX_SHIFT (1U)
+/*! ENABLERX - Enable the Receive FIFO
+ * 0b0..The receive FIFO is not enabled
+ * 0b1..The receive FIFO is enabled
+ */
+#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
+#define SPI_FIFOCFG_SIZE_MASK (0x30U)
+#define SPI_FIFOCFG_SIZE_SHIFT (4U)
+/*! SIZE - FIFO Size Configuration
+ * 0b00..FIFO is configured as 16 entries of 8 bits.
+ * 0b01..FIFO is configured as 8 entries of 16 bits.
+ * 0b10..Not used
+ * 0b11..Not used
+ */
+#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
+#define SPI_FIFOCFG_DMATX_MASK (0x1000U)
+#define SPI_FIFOCFG_DMATX_SHIFT (12U)
+/*! DMATX - DMA Configuration for Transmit
+ * 0b0..DMA is not used for the transmit function
+ * 0b1..Issues DMA request for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
+#define SPI_FIFOCFG_DMARX_MASK (0x2000U)
+#define SPI_FIFOCFG_DMARX_SHIFT (13U)
+/*! DMARX - DMA Configuration for Receive
+ * 0b0..DMA is not used for the receive function.
+ * 0b1..Issues a DMA request for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
+#define SPI_FIFOCFG_WAKETX_MASK (0x4000U)
+#define SPI_FIFOCFG_WAKETX_SHIFT (14U)
+/*! WAKETX - Wake-up for Transmit FIFO Level
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes
+ * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
+ * FIFOTRIG, even when the TXLVL interrupt is not enabled.
+ */
+#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
+#define SPI_FIFOCFG_WAKERX_MASK (0x8000U)
+#define SPI_FIFOCFG_WAKERX_SHIFT (15U)
+/*! WAKERX - Wake-up for Receive FIFO Level
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.
+ * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by
+ * FIFOTRIG[RXLVL], even when the RXLVL interrupt is not enabled.
+ */
+#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
+#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U)
+#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U)
+/*! EMPTYTX - Empty Command for the Transmit FIFO
+ * 0b0..No effect
+ * 0b1..The TX FIFO is emptied
+ */
+#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
+#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U)
+#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U)
+/*! EMPTYRX - Empty Command for the Receive FIFO
+ * 0b0..No effect
+ * 0b1..The RX FIFO is emptied
+ */
+#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
+#define SPI_FIFOCFG_POPDBG_MASK (0x40000U)
+#define SPI_FIFOCFG_POPDBG_SHIFT (18U)
+/*! POPDBG - Pop FIFO for Debug Reads
+ * 0b0..Debug reads of the FIFO do not pop the FIFO
+ * 0b1..A debug read will cause the FIFO to pop
+ */
+#define SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK)
+/*! @} */
+
+/*! @name FIFOSTAT - FIFO Status Register */
+/*! @{ */
+#define SPI_FIFOSTAT_TXERR_MASK (0x1U)
+#define SPI_FIFOSTAT_TXERR_SHIFT (0U)
+/*! TXERR - TX FIFO Error
+ * 0b0..A transmit FIFO error has not occurred.
+ * 0b1..A transmit FIFO error has occurred. This error could be an overflow caused by pushing data into a full
+ * FIFO, or by an underflow if the FIFO is empty when data is needed.
+ */
+#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
+#define SPI_FIFOSTAT_RXERR_MASK (0x2U)
+#define SPI_FIFOSTAT_RXERR_SHIFT (1U)
+/*! RXERR - RX FIFO Error
+ * 0b0..A receive FIFO overflow has not occurred
+ * 0b1..A receive FIFO overflow has occurred, caused by software or DMA not emptying the FIFO fast enough
+ */
+#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
+#define SPI_FIFOSTAT_PERINT_MASK (0x8U)
+#define SPI_FIFOSTAT_PERINT_SHIFT (3U)
+/*! PERINT - Peripheral Interrupt
+ * 0b0..The peripheral function has not asserted an interrupt
+ * 0b1..Indicates that the peripheral function has asserted an interrupt. More information can be found by
+ * reading the peripheral's status register (STAT).
+ */
+#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
+#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U)
+#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U)
+/*! TXEMPTY - Transmit FIFO Empty
+ * 0b0..The transmit FIFO is not empty
+ * 0b1..The transmit FIFO is empty, although the peripheral may still be processing the last piece of data.
+ */
+#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
+#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U)
+#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U)
+/*! TXNOTFULL - Transmit FIFO is Not Full
+ * 0b0..The transmit FIFO is full and another write would cause it to overflow
+ * 0b1..The transmit FIFO is not full, so more data can be written
+ */
+#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
+#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
+#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
+/*! RXNOTEMPTY - Receive FIFO is Not Empty
+ * 0b0..When 0, the receive FIFO is empty
+ * 0b1..When 1, the receive FIFO is not empty, so data can be read
+ */
+#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
+#define SPI_FIFOSTAT_RXFULL_MASK (0x80U)
+#define SPI_FIFOSTAT_RXFULL_SHIFT (7U)
+/*! RXFULL - Receive FIFO is Full
+ * 0b0..The receive FIFO is not full
+ * 0b1..The receive FIFO is full. To prevent the peripheral from causing an overflow, data should be read out.
+ */
+#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
+#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U)
+#define SPI_FIFOSTAT_TXLVL_SHIFT (8U)
+/*! TXLVL - Transmit FIFO Current Level
+ */
+#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
+#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U)
+#define SPI_FIFOSTAT_RXLVL_SHIFT (16U)
+/*! RXLVL - Receive FIFO Current Level
+ */
+#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOTRIG - FIFO Trigger Register */
+/*! @{ */
+#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U)
+#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U)
+/*! TXLVLENA - Transmit FIFO Level Trigger Enable
+ * 0b0..Transmit FIFO level does not generate a FIFO level trigger
+ * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the FIFOTRIG[TXLVL] field.
+ */
+#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
+#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U)
+#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U)
+/*! RXLVLENA - Receive FIFO Level Trigger Enable
+ * 0b0..Receive FIFO level does not generate a FIFO level trigger
+ * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the FIFOTRIG[RXLVL] field.
+ */
+#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
+#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U)
+#define SPI_FIFOTRIG_TXLVL_SHIFT (8U)
+/*! TXLVL - Transmit FIFO Level Trigger Point
+ * 0b0000..Trigger when the TX FIFO becomes empty
+ * 0b0001..Trigger when the TX FIFO level decreases to 1 entry
+ * 0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full)
+ */
+#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
+#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U)
+#define SPI_FIFOTRIG_RXLVL_SHIFT (16U)
+/*! RXLVL - Receive FIFO Level Trigger Point
+ * 0b0000..Trigger when the RX FIFO has received 1 entry (is no longer empty)
+ * 0b0001..Trigger when the RX FIFO has received 2 entries
+ * 0b1111..Trigger when the RX FIFO has received 16 entries (has become full)
+ */
+#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENSET - FIFO Interrupt Enable Register */
+/*! @{ */
+#define SPI_FIFOINTENSET_TXERR_MASK (0x1U)
+#define SPI_FIFOINTENSET_TXERR_SHIFT (0U)
+/*! TXERR - TX Error Interrupt Enable
+ * 0b0..No interrupt will be generated for a transmit error
+ * 0b1..An interrupt will be generated when a transmit error occurs
+ */
+#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
+#define SPI_FIFOINTENSET_RXERR_MASK (0x2U)
+#define SPI_FIFOINTENSET_RXERR_SHIFT (1U)
+/*! RXERR - Receive Error Interrupt Enable
+ * 0b0..No interrupt will be generated for a receive error
+ * 0b1..An interrupt will be generated when a receive error occurs
+ */
+#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
+#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U)
+#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U)
+/*! TXLVL - Transmit FIFO Level Interrupt Enable
+ * 0b0..No interrupt will be generated based on the TX FIFO level
+ * 0b1..If FIFOTRIG[TXLVLENA]=1, then an interrupt will be generated when the TX FIFO level decreases to the level specified by FIFOTRIG[TXLVL]
+ */
+#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
+#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U)
+#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U)
+/*! RXLVL - Receive FIFO Level Interrupt Enable
+ * 0b0..No interrupt will be generated based on the RX FIFO level
+ * 0b1..If FIFOTRIG[RXLVLENA]=1, then an interrupt will be generated when the RX FIFO level increases to the level specified by FIFOTRIG[RXLVL]
+ */
+#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear Register */
+/*! @{ */
+#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U)
+#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U)
+/*! TXERR - TX Error Interrupt Enable
+ * 0b0..No effect
+ * 0b1..Clear the TX Error Interrupt Enable bit FIFOINTENSET[TXERR]
+ */
+#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
+#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U)
+#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U)
+/*! RXERR - Receive Error Interrupt Enable
+ * 0b0..No effect
+ * 0b1..Clear the Receive Error Interrupt Enable bit FIFOINTENSET[RXERR]
+ */
+#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
+#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U)
+#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U)
+/*! TXLVL - Transmit FIFO Level Interrupt Enable
+ * 0b0..No effect
+ * 0b1..Clear the Transmit FIFO Level Interrupt Enable bit FIFOINTENSET[TXLVL]
+ */
+#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
+#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U)
+#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U)
+/*! RXLVL - Receive FIFO Level Interrupt Enable
+ * 0b0..No effect
+ * 0b1..Clear the Receive FIFO Level Interrupt Enable bit FIFOINTENSET[RXLVL]
+ */
+#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTSTAT - FIFO Interrupt Status Register */
+/*! @{ */
+#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U)
+#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U)
+/*! TXERR - TX FIFO Error Interrupt Status
+ * 0b0..Not pending
+ * 0b1..Pending
+ */
+#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
+#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U)
+#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U)
+/*! RXERR - RX FIFO Error Interrupt Status
+ * 0b0..Not pending
+ * 0b1..Pending
+ */
+#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
+#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U)
+#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U)
+/*! TXLVL - Transmit FIFO Level Interrupt Status
+ * 0b0..Not pending
+ * 0b1..Pending
+ */
+#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
+#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U)
+#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U)
+/*! RXLVL - Receive FIFO Level Interrupt Status
+ * 0b0..Not pending
+ * 0b1..Pending
+ */
+#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
+#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U)
+#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U)
+/*! PERINT - Peripheral Interrupt Status
+ * 0b0..Not pending
+ * 0b1..Pending
+ */
+#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
+/*! @} */
+
+/*! @name FIFOWR - FIFO Write Data Register */
+/*! @{ */
+#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU)
+#define SPI_FIFOWR_TXDATA_SHIFT (0U)
+/*! TXDATA - Transmit Data to the FIFO
+ */
+#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
+#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U)
+#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U)
+/*! TXSSEL0_N - Transmit Slave Select 0
+ * 0b0..SSEL0 is asserted
+ * 0b1..SSEL0 is not asserted
+ */
+#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
+#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U)
+#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U)
+/*! TXSSEL1_N - Transmit Slave Select 1
+ * 0b0..SSEL1 is asserted
+ * 0b1..SSEL1 is not asserted
+ */
+#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
+#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U)
+#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U)
+/*! TXSSEL2_N - Transmit Slave Select 2
+ * 0b0..SSEL2 is asserted
+ * 0b1..SSEL2 is not asserted
+ */
+#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
+#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U)
+#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U)
+/*! TXSSEL3_N - Transmit Slave Select 3
+ * 0b0..SSEL3 is asserted
+ * 0b1..SSEL3 is not asserted
+ */
+#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
+#define SPI_FIFOWR_EOT_MASK (0x100000U)
+#define SPI_FIFOWR_EOT_SHIFT (20U)
+/*! EOT - End of Transfer
+ * 0b0..SSEL is not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
+ * 0b1..SSEL is deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
+ */
+#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
+#define SPI_FIFOWR_EOF_MASK (0x200000U)
+#define SPI_FIFOWR_EOF_SHIFT (21U)
+/*! EOF - End of Frame
+ * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame.
+ * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be
+ * inserted before subsequent data is transmitted.
+ */
+#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
+#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U)
+#define SPI_FIFOWR_RXIGNORE_SHIFT (22U)
+/*! RXIGNORE - Receive Ignore
+ * 0b0..Read received data. Received data must be read, to allow transmission to proceed. SPI transmit will halt
+ * when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not
+ * read before new data is received.
+ * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received
+ * data. No receiver flags are generated.
+ */
+#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
+#define SPI_FIFOWR_TXIGNORE_MASK (0x800000U)
+#define SPI_FIFOWR_TXIGNORE_SHIFT (23U)
+/*! TXIGNORE - Transmit Ignore
+ * 0b0..Write transmit data
+ * 0b1..Ignore transmit data
+ */
+#define SPI_FIFOWR_TXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXIGNORE_SHIFT)) & SPI_FIFOWR_TXIGNORE_MASK)
+#define SPI_FIFOWR_LEN_MASK (0xF000000U)
+#define SPI_FIFOWR_LEN_SHIFT (24U)
+/*! LEN - Data Length
+ * 0b0000..Reserved
+ * 0b0001..Reserved
+ * 0b0010..Reserved
+ * 0b0011..Data transfer is 4 bits in length
+ * 0b0100..Data transfer is 5 bits in length
+ * 0b1111..Data transfer is 16 bits in length
+ */
+#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
+/*! @} */
+
+/*! @name FIFORD - FIFO Read Data Register */
+/*! @{ */
+#define SPI_FIFORD_RXDATA_MASK (0xFFFFU)
+#define SPI_FIFORD_RXDATA_SHIFT (0U)
+/*! RXDATA - Received Data from the FIFO
+ */
+#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
+#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U)
+#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U)
+/*! RXSSEL0_N - Slave Select 0 for Receive
+ * 0b0..Slave Select 0 is active
+ * 0b1..Slave Select 0 is not active
+ */
+#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
+#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U)
+#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U)
+/*! RXSSEL1_N - Slave Select 1 for Receive
+ * 0b0..Slave Select 1 is active
+ * 0b1..Slave Select 1 is not active
+ */
+#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
+#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U)
+#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U)
+/*! RXSSEL2_N - Slave Select 2 for Receive
+ * 0b0..Slave Select 2 is active
+ * 0b1..Slave Select 2 is not active
+ */
+#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
+#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U)
+#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U)
+/*! RXSSEL3_N - Slave Select 3 for Receive
+ * 0b0..Slave Select 3 is active
+ * 0b1..Slave Select 3 is not active
+ */
+#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
+#define SPI_FIFORD_SOT_MASK (0x100000U)
+#define SPI_FIFORD_SOT_SHIFT (20U)
+/*! SOT - Start of Transfer Flag
+ * 0b0..This is not the 1st data after the SSELs went from deasserted to asserted
+ * 0b1..This is the 1st data after the SSELs went from deasserted to asserted (i.e., any previous transfer has
+ * ended). This information can be used to identify the 1st piece of data in cases where the transfer length is
+ * greater than 16 bits.
+ */
+#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
+/*! @} */
+
+/*! @name FIFORDNOPOP - FIFO Data Read with no FIFO Pop Register */
+/*! @{ */
+#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU)
+#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U)
+/*! RXDATA - Received Data from the FIFO
+ */
+#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U)
+/*! RXSSEL0_N - Slave Select 0 for Receive
+ * 0b0..Not selected
+ * 0b1..Selected
+ */
+#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U)
+/*! RXSSEL1_N - Slave Select 1 for Receive
+ * 0b0..Not selected
+ * 0b1..Selected
+ */
+#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U)
+/*! RXSSEL2_N - Slave Select 2 for Receive
+ * 0b0..Not selected
+ * 0b1..Selected
+ */
+#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U)
+/*! RXSSEL3_N - Slave Select 3 for Receive
+ * 0b0..Not selected
+ * 0b1..Selected
+ */
+#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
+#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U)
+#define SPI_FIFORDNOPOP_SOT_SHIFT (20U)
+/*! SOT - Start of Transfer Flag
+ * 0b0..Not active
+ * 0b1..Active
+ */
+#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
+/*! @} */
+
+/*! @name FIFOSIZE - FIFO Size Register */
+/*! @{ */
+#define SPI_FIFOSIZE_FIFOSIZE_MASK (0x1FU)
+#define SPI_FIFOSIZE_FIFOSIZE_SHIFT (0U)
+/*! FIFOSIZE - FIFO Size
+ */
+#define SPI_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK)
+/*! @} */
+
+/*! @name ID - Peripheral Identification Register */
+/*! @{ */
+#define SPI_ID_APERTURE_MASK (0xFFU)
+#define SPI_ID_APERTURE_SHIFT (0U)
+/*! APERTURE - Aperture
+ */
+#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)
+#define SPI_ID_MINOR_REV_MASK (0xF00U)
+#define SPI_ID_MINOR_REV_SHIFT (8U)
+/*! MINOR_REV - Minor revision of module implementation
+ */
+#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)
+#define SPI_ID_MAJOR_REV_MASK (0xF000U)
+#define SPI_ID_MAJOR_REV_SHIFT (12U)
+/*! MAJOR_REV - Major revision of module implementation
+ */
+#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)
+#define SPI_ID_ID_MASK (0xFFFF0000U)
+#define SPI_ID_ID_SHIFT (16U)
+/*! ID - Module identifier for the selected function
+ */
+#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral SPI0 base address */
+ #define SPI0_BASE (0x50106000u)
+ /** Peripheral SPI0 base address */
+ #define SPI0_BASE_NS (0x40106000u)
+ /** Peripheral SPI0 base pointer */
+ #define SPI0 ((SPI_Type *)SPI0_BASE)
+ /** Peripheral SPI0 base pointer */
+ #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS)
+ /** Peripheral SPI1 base address */
+ #define SPI1_BASE (0x50107000u)
+ /** Peripheral SPI1 base address */
+ #define SPI1_BASE_NS (0x40107000u)
+ /** Peripheral SPI1 base pointer */
+ #define SPI1 ((SPI_Type *)SPI1_BASE)
+ /** Peripheral SPI1 base pointer */
+ #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS)
+ /** Peripheral SPI2 base address */
+ #define SPI2_BASE (0x50108000u)
+ /** Peripheral SPI2 base address */
+ #define SPI2_BASE_NS (0x40108000u)
+ /** Peripheral SPI2 base pointer */
+ #define SPI2 ((SPI_Type *)SPI2_BASE)
+ /** Peripheral SPI2 base pointer */
+ #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS)
+ /** Peripheral SPI3 base address */
+ #define SPI3_BASE (0x50109000u)
+ /** Peripheral SPI3 base address */
+ #define SPI3_BASE_NS (0x40109000u)
+ /** Peripheral SPI3 base pointer */
+ #define SPI3 ((SPI_Type *)SPI3_BASE)
+ /** Peripheral SPI3 base pointer */
+ #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS)
+ /** Peripheral SPI4 base address */
+ #define SPI4_BASE (0x50122000u)
+ /** Peripheral SPI4 base address */
+ #define SPI4_BASE_NS (0x40122000u)
+ /** Peripheral SPI4 base pointer */
+ #define SPI4 ((SPI_Type *)SPI4_BASE)
+ /** Peripheral SPI4 base pointer */
+ #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS)
+ /** Peripheral SPI5 base address */
+ #define SPI5_BASE (0x50123000u)
+ /** Peripheral SPI5 base address */
+ #define SPI5_BASE_NS (0x40123000u)
+ /** Peripheral SPI5 base pointer */
+ #define SPI5 ((SPI_Type *)SPI5_BASE)
+ /** Peripheral SPI5 base pointer */
+ #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS)
+ /** Peripheral SPI6 base address */
+ #define SPI6_BASE (0x50124000u)
+ /** Peripheral SPI6 base address */
+ #define SPI6_BASE_NS (0x40124000u)
+ /** Peripheral SPI6 base pointer */
+ #define SPI6 ((SPI_Type *)SPI6_BASE)
+ /** Peripheral SPI6 base pointer */
+ #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS)
+ /** Peripheral SPI7 base address */
+ #define SPI7_BASE (0x50125000u)
+ /** Peripheral SPI7 base address */
+ #define SPI7_BASE_NS (0x40125000u)
+ /** Peripheral SPI7 base pointer */
+ #define SPI7 ((SPI_Type *)SPI7_BASE)
+ /** Peripheral SPI7 base pointer */
+ #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS)
+ /** Peripheral SPI8 base address */
+ #define SPI8_BASE (0x50209000u)
+ /** Peripheral SPI8 base address */
+ #define SPI8_BASE_NS (0x40209000u)
+ /** Peripheral SPI8 base pointer */
+ #define SPI8 ((SPI_Type *)SPI8_BASE)
+ /** Peripheral SPI8 base pointer */
+ #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS)
+ /** Peripheral SPI9 base address */
+ #define SPI9_BASE (0x5020A000u)
+ /** Peripheral SPI9 base address */
+ #define SPI9_BASE_NS (0x4020A000u)
+ /** Peripheral SPI9 base pointer */
+ #define SPI9 ((SPI_Type *)SPI9_BASE)
+ /** Peripheral SPI9 base pointer */
+ #define SPI9_NS ((SPI_Type *)SPI9_BASE_NS)
+ /** Peripheral SPI10 base address */
+ #define SPI10_BASE (0x5020B000u)
+ /** Peripheral SPI10 base address */
+ #define SPI10_BASE_NS (0x4020B000u)
+ /** Peripheral SPI10 base pointer */
+ #define SPI10 ((SPI_Type *)SPI10_BASE)
+ /** Peripheral SPI10 base pointer */
+ #define SPI10_NS ((SPI_Type *)SPI10_BASE_NS)
+ /** Peripheral SPI11 base address */
+ #define SPI11_BASE (0x5020C000u)
+ /** Peripheral SPI11 base address */
+ #define SPI11_BASE_NS (0x4020C000u)
+ /** Peripheral SPI11 base pointer */
+ #define SPI11 ((SPI_Type *)SPI11_BASE)
+ /** Peripheral SPI11 base pointer */
+ #define SPI11_NS ((SPI_Type *)SPI11_BASE_NS)
+ /** Peripheral SPI12 base address */
+ #define SPI12_BASE (0x5020D000u)
+ /** Peripheral SPI12 base address */
+ #define SPI12_BASE_NS (0x4020D000u)
+ /** Peripheral SPI12 base pointer */
+ #define SPI12 ((SPI_Type *)SPI12_BASE)
+ /** Peripheral SPI12 base pointer */
+ #define SPI12_NS ((SPI_Type *)SPI12_BASE_NS)
+ /** Peripheral SPI13 base address */
+ #define SPI13_BASE (0x5020E000u)
+ /** Peripheral SPI13 base address */
+ #define SPI13_BASE_NS (0x4020E000u)
+ /** Peripheral SPI13 base pointer */
+ #define SPI13 ((SPI_Type *)SPI13_BASE)
+ /** Peripheral SPI13 base pointer */
+ #define SPI13_NS ((SPI_Type *)SPI13_BASE_NS)
+ /** Peripheral SPI14 base address */
+ #define SPI14_BASE (0x50126000u)
+ /** Peripheral SPI14 base address */
+ #define SPI14_BASE_NS (0x40126000u)
+ /** Peripheral SPI14 base pointer */
+ #define SPI14 ((SPI_Type *)SPI14_BASE)
+ /** Peripheral SPI14 base pointer */
+ #define SPI14_NS ((SPI_Type *)SPI14_BASE_NS)
+ /** Peripheral SPI16 base address */
+ #define SPI16_BASE (0x50128000u)
+ /** Peripheral SPI16 base address */
+ #define SPI16_BASE_NS (0x40128000u)
+ /** Peripheral SPI16 base pointer */
+ #define SPI16 ((SPI_Type *)SPI16_BASE)
+ /** Peripheral SPI16 base pointer */
+ #define SPI16_NS ((SPI_Type *)SPI16_BASE_NS)
+ /** Array initializer of SPI peripheral base addresses */
+ #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE, SPI10_BASE, SPI11_BASE, SPI12_BASE, SPI13_BASE, SPI14_BASE, SPI16_BASE }
+ /** Array initializer of SPI peripheral base pointers */
+ #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9, SPI10, SPI11, SPI12, SPI13, SPI14, SPI16 }
+ /** Array initializer of SPI peripheral base addresses */
+ #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS, SPI9_BASE_NS, SPI10_BASE_NS, SPI11_BASE_NS, SPI12_BASE_NS, SPI13_BASE_NS, SPI14_BASE_NS, SPI16_BASE_NS }
+ /** Array initializer of SPI peripheral base pointers */
+ #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS, SPI9_NS, SPI10_NS, SPI11_NS, SPI12_NS, SPI13_NS, SPI14_NS, SPI16_NS }
+#else
+ /** Peripheral SPI0 base address */
+ #define SPI0_BASE (0x40106000u)
+ /** Peripheral SPI0 base pointer */
+ #define SPI0 ((SPI_Type *)SPI0_BASE)
+ /** Peripheral SPI1 base address */
+ #define SPI1_BASE (0x40107000u)
+ /** Peripheral SPI1 base pointer */
+ #define SPI1 ((SPI_Type *)SPI1_BASE)
+ /** Peripheral SPI2 base address */
+ #define SPI2_BASE (0x40108000u)
+ /** Peripheral SPI2 base pointer */
+ #define SPI2 ((SPI_Type *)SPI2_BASE)
+ /** Peripheral SPI3 base address */
+ #define SPI3_BASE (0x40109000u)
+ /** Peripheral SPI3 base pointer */
+ #define SPI3 ((SPI_Type *)SPI3_BASE)
+ /** Peripheral SPI4 base address */
+ #define SPI4_BASE (0x40122000u)
+ /** Peripheral SPI4 base pointer */
+ #define SPI4 ((SPI_Type *)SPI4_BASE)
+ /** Peripheral SPI5 base address */
+ #define SPI5_BASE (0x40123000u)
+ /** Peripheral SPI5 base pointer */
+ #define SPI5 ((SPI_Type *)SPI5_BASE)
+ /** Peripheral SPI6 base address */
+ #define SPI6_BASE (0x40124000u)
+ /** Peripheral SPI6 base pointer */
+ #define SPI6 ((SPI_Type *)SPI6_BASE)
+ /** Peripheral SPI7 base address */
+ #define SPI7_BASE (0x40125000u)
+ /** Peripheral SPI7 base pointer */
+ #define SPI7 ((SPI_Type *)SPI7_BASE)
+ /** Peripheral SPI8 base address */
+ #define SPI8_BASE (0x40209000u)
+ /** Peripheral SPI8 base pointer */
+ #define SPI8 ((SPI_Type *)SPI8_BASE)
+ /** Peripheral SPI9 base address */
+ #define SPI9_BASE (0x4020A000u)
+ /** Peripheral SPI9 base pointer */
+ #define SPI9 ((SPI_Type *)SPI9_BASE)
+ /** Peripheral SPI10 base address */
+ #define SPI10_BASE (0x4020B000u)
+ /** Peripheral SPI10 base pointer */
+ #define SPI10 ((SPI_Type *)SPI10_BASE)
+ /** Peripheral SPI11 base address */
+ #define SPI11_BASE (0x4020C000u)
+ /** Peripheral SPI11 base pointer */
+ #define SPI11 ((SPI_Type *)SPI11_BASE)
+ /** Peripheral SPI12 base address */
+ #define SPI12_BASE (0x4020D000u)
+ /** Peripheral SPI12 base pointer */
+ #define SPI12 ((SPI_Type *)SPI12_BASE)
+ /** Peripheral SPI13 base address */
+ #define SPI13_BASE (0x4020E000u)
+ /** Peripheral SPI13 base pointer */
+ #define SPI13 ((SPI_Type *)SPI13_BASE)
+ /** Peripheral SPI14 base address */
+ #define SPI14_BASE (0x40126000u)
+ /** Peripheral SPI14 base pointer */
+ #define SPI14 ((SPI_Type *)SPI14_BASE)
+ /** Peripheral SPI16 base address */
+ #define SPI16_BASE (0x40128000u)
+ /** Peripheral SPI16 base pointer */
+ #define SPI16 ((SPI_Type *)SPI16_BASE)
+ /** Array initializer of SPI peripheral base addresses */
+ #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE, SPI10_BASE, SPI11_BASE, SPI12_BASE, SPI13_BASE, SPI14_BASE, SPI16_BASE }
+ /** Array initializer of SPI peripheral base pointers */
+ #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9, SPI10, SPI11, SPI12, SPI13, SPI14, SPI16 }
+#endif
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn, FLEXCOMM11_IRQn, FLEXCOMM12_IRQn, FLEXCOMM13_IRQn, FLEXCOMM14_IRQn, FLEXCOMM16_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SYSCTL0 Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCTL0_Peripheral_Access_Layer SYSCTL0 Peripheral Access Layer
+ * @{
+ */
+
+/** SYSCTL0 - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[4];
+ __IO uint32_t DSP_VECT_REMAP; /**< DSP Vector Remap, offset: 0x4 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t DSPSTALL; /**< DSP Stall Control, offset: 0xC */
+ __IO uint32_t AHBMATRIXPRIOR; /**< AHB MAX Priority, offset: 0x10 */
+ uint8_t RESERVED_2[12];
+ __IO uint32_t AHBBRIDGEBUFFER[2]; /**< AHB Buffer, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t BOOTROM_LCKOUT; /**< BOOT ROM lockout, offset: 0x2C */
+ __IO uint32_t M33NMISRCSEL; /**< M33 NMI source selection, offset: 0x30 */
+ __IO uint32_t SYSTEM_STICK_CALIB; /**< System secure tick calibration, offset: 0x34 */
+ __IO uint32_t SYSTEM_NSTICK_CALIB; /**< System non-secure tick calibration, offset: 0x38 */
+ uint8_t RESERVED_4[36];
+ __IO uint32_t PRODUCT_ID; /**< Product ID, offset: 0x60 */
+ __I uint32_t SILICONREV_ID; /**< Silicon Revision ID, offset: 0x64 */
+ __I uint32_t JTAG_ID; /**< JTAG ID, offset: 0x68 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t NSGPIO_PSYNC; /**< Non-secure GPIO PSYNC, offset: 0x70 */
+ __IO uint32_t SGPIO_PSYNC; /**< Secure GPIO PSYNC, offset: 0x74 */
+ uint8_t RESERVED_6[8];
+ __IO uint32_t AUTOCLKGATEOVERRIDE0; /**< Auto clock gate override 0, offset: 0x80 */
+ __IO uint32_t AUTOCLKGATEOVERRIDE1; /**< Auto clock gate override 1, offset: 0x84 */
+ uint8_t RESERVED_7[24];
+ __IO uint32_t CLKGATEOVERRIDE0; /**< Clock gate override 0, offset: 0xA0 */
+ uint8_t RESERVED_8[88];
+ __IO uint32_t AHB_SRAM_ACCESS_DISABLE; /**< AHB SRAM access disable, offset: 0xFC */
+ __IO uint32_t AXI_SRAM_ACCESS_DISABLE; /**< AXI SRAM access disable, offset: 0x100 */
+ __IO uint32_t DSP_SRAM_ACCESS_DISABLE; /**< DSP SRAM access disable, offset: 0x104 */
+ uint8_t RESERVED_9[8];
+ __IO uint32_t PQ_MEM_CTRL; /**< Power-Quad Memory Control, offset: 0x110 */
+ __IO uint32_t FLEXSPI0_MEM_CTRL; /**< FlexSPI0 Memory Control, offset: 0x114 */
+ __IO uint32_t USBHS_MEM_CTRL; /**< USBHS Memory Control, offset: 0x118 */
+ __IO uint32_t USDHC0_MEM_CTRL; /**< USDHC0 Memory Control, offset: 0x11C */
+ __IO uint32_t USDHC1_MEM_CTRL; /**< USDHC1 Memory Control, offset: 0x120 */
+ __IO uint32_t CASPER_MEM_CTRL; /**< CASPER Memory Control, offset: 0x124 */
+ __IO uint32_t ROM_MEM_CTRL; /**< ROM Memory Control, offset: 0x128 */
+ __IO uint32_t FLEXSPI1_MEM_CTRL; /**< FlexSPI1 Memory Control, offset: 0x12C */
+ __IO uint32_t GPU_MEM_CTRL; /**< GPU Memory Control, offset: 0x130 */
+ __IO uint32_t MIPI_MEM_CTRL; /**< MIPI Memory Control, offset: 0x134 */
+ __IO uint32_t DCN_MEM_CTRL; /**< LCDIF Memory Control, offset: 0x138 */
+ __IO uint32_t SMARTDMA_MEM_CTRL; /**< SMARTDMA Memory Control, offset: 0x13C */
+ uint8_t RESERVED_10[704];
+ __IO uint32_t MIPI_DSI_CTRL; /**< MIPI DSI Control, offset: 0x400 */
+ uint8_t RESERVED_11[8];
+ __IO uint32_t USB0CLKCTRL; /**< USB Clock Control, offset: 0x40C */
+ __I uint32_t USB0CLKSTAT; /**< USB Clock Status, offset: 0x410 */
+ __IO uint32_t USBPHYPLL0LOCKTIMEDIV2; /**< USB PHY PLL0 lock time division, offset: 0x414 */
+ uint8_t RESERVED_12[488];
+ __IO uint32_t PDSLEEPCFG0; /**< Sleep configuration 0, offset: 0x600 */
+ __IO uint32_t PDSLEEPCFG1; /**< Sleep configuration 1, offset: 0x604 */
+ __IO uint32_t PDSLEEPCFG2; /**< Sleep configuration 2, offset: 0x608 */
+ __IO uint32_t PDSLEEPCFG3; /**< Sleep configuration 3, offset: 0x60C */
+ __IO uint32_t PDRUNCFG0; /**< Run configuration 0, offset: 0x610 */
+ __IO uint32_t PDRUNCFG1; /**< Run configuration 1, offset: 0x614 */
+ __IO uint32_t PDRUNCFG2; /**< Run configuration 2, offset: 0x618 */
+ __IO uint32_t PDRUNCFG3; /**< Run configuration 3, offset: 0x61C */
+ __O uint32_t PDRUNCFG0_SET; /**< Run configuration 0 set, offset: 0x620 */
+ __O uint32_t PDRUNCFG1_SET; /**< Run configuration 1 set, offset: 0x624 */
+ __O uint32_t PDRUNCFG2_SET; /**< Run configuration 2 set, offset: 0x628 */
+ __O uint32_t PDRUNCFG3_SET; /**< Run configuration 3 set, offset: 0x62C */
+ __O uint32_t PDRUNCFG0_CLR; /**< Run configuration 0 clear, offset: 0x630 */
+ __O uint32_t PDRUNCFG1_CLR; /**< Run configuration 1 clear, offset: 0x634 */
+ __IO uint32_t PDRUNCFG2_CLR; /**< Run configuration 2 clear, offset: 0x638 */
+ __IO uint32_t PDRUNCFG3_CLR; /**< Run configuration 3 clear, offset: 0x63C */
+ uint8_t RESERVED_13[32];
+ __IO uint32_t PDWAKECFG; /**< PD Wake Configuration, offset: 0x660 */
+ uint8_t RESERVED_14[28];
+ __IO uint32_t STARTEN0; /**< Start Enable 0, offset: 0x680 */
+ __IO uint32_t STARTEN1; /**< Start Enable 1, offset: 0x684 */
+ __IO uint32_t STARTEN2; /**< Start Enable 2, offset: 0x688 */
+ uint8_t RESERVED_15[20];
+ __IO uint32_t STARTEN0_SET; /**< Start Enable 0 Set, offset: 0x6A0 */
+ __IO uint32_t STARTEN1_SET; /**< Start Enable 1 Set, offset: 0x6A4 */
+ __IO uint32_t STARTEN2_SET; /**< Start Enable 2, offset: 0x6A8 */
+ uint8_t RESERVED_16[20];
+ __IO uint32_t STARTEN0_CLR; /**< Start Enable 0 clear, offset: 0x6C0 */
+ __IO uint32_t STARTEN1_CLR; /**< Start Enable 1 clear, offset: 0x6C4 */
+ __IO uint32_t STARTEN2_CLR; /**< Start Enable 2, offset: 0x6C8 */
+ uint8_t RESERVED_17[68];
+ __IO uint32_t MAINCLKSAFETY; /**< Main Clock Safety, offset: 0x710 */
+ uint8_t RESERVED_18[108];
+ __IO uint32_t HWWAKE; /**< Hardware Wake, offset: 0x780 */
+ uint8_t RESERVED_19[1672];
+ __IO uint32_t TEMPSENSORCTL; /**< Temperature Sensor Control, offset: 0xE0C */
+ uint8_t RESERVED_20[48];
+ __IO uint32_t BOOTSTATELOCK; /**< Boot State Lock, offset: 0xE40 */
+ uint8_t RESERVED_21[12];
+ __IO uint32_t BOOTSTATESEED[8]; /**< Boot State Seed, array offset: 0xE50, array step: 0x4 */
+ __IO uint32_t BOOTSTATEHMAC[8]; /**< HMAC of boot state used for attestation., array offset: 0xE70, array step: 0x4 */
+ uint8_t RESERVED_22[96];
+ __IO uint32_t FLEXSPI0PADCTL; /**< FLEXSPI0 Pad Control, offset: 0xEF0 */
+ __IO uint32_t FLEXSPI1PADCTL; /**< FLEXSPI1 Pad Control, offset: 0xEF4 */
+ __IO uint32_t SDIO0PADCTL; /**< SDIO0 Pad Control, offset: 0xEF8 */
+ __IO uint32_t SDIO1PADCTL; /**< SDIO1 Pad Control, offset: 0xEFC */
+ __IO uint32_t DICEHWREGN; /**< Compound Device Identifier (CDI), offset: 0xF00 */
+ uint8_t RESERVED_23[76];
+ __IO uint32_t UUID[4]; /**< UUID, array offset: 0xF50, array step: 0x4 */
+ uint8_t RESERVED_24[32];
+ __IO uint32_t AESKEY_SRCSEL; /**< AES Key Source Select, offset: 0xF80 */
+ __IO uint32_t OTFADKEY_SRCSEL; /**< OTFAD Key Source Select, offset: 0xF84 */
+ __IO uint32_t HASHHWKEYDISABLE; /**< HASH Hardware Key Disable, offset: 0xF88 */
+ uint8_t RESERVED_25[20];
+ __IO uint32_t DBG_LOCKEN; /**< Debug Lock Enable, offset: 0xFA0 */
+ __IO uint32_t DBG_FEATURES; /**< Debug Features, offset: 0xFA4 */
+ __IO uint32_t DBG_FEATURES_DP; /**< Debug Features Duplicate, offset: 0xFA8 */
+ uint8_t RESERVED_26[8];
+ __IO uint32_t CS_PROTCPU0; /**< Code Security for CPU0, offset: 0xFB4 */
+ __IO uint32_t CS_PROTCPU1; /**< Code Security for CPU1, offset: 0xFB8 */
+ uint8_t RESERVED_27[4];
+ __IO uint32_t DBG_AUTH_SCRATCH; /**< Debug authorization scratch, offset: 0xFC0 */
+ uint8_t RESERVED_28[12];
+ __IO uint32_t KEY_BLOCK; /**< Key block, offset: 0xFD0 */
+} SYSCTL0_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SYSCTL0 Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCTL0_Register_Masks SYSCTL0 Register Masks
+ * @{
+ */
+
+/*! @name DSP_VECT_REMAP - DSP Vector Remap */
+/*! @{ */
+#define SYSCTL0_DSP_VECT_REMAP_DSP_VECT_REMAP_MASK (0xFFFU)
+#define SYSCTL0_DSP_VECT_REMAP_DSP_VECT_REMAP_SHIFT (0U)
+/*! DSP_VECT_REMAP - DSP_VECT_REMAP
+ */
+#define SYSCTL0_DSP_VECT_REMAP_DSP_VECT_REMAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_VECT_REMAP_DSP_VECT_REMAP_SHIFT)) & SYSCTL0_DSP_VECT_REMAP_DSP_VECT_REMAP_MASK)
+#define SYSCTL0_DSP_VECT_REMAP_STATVECSELECT_MASK (0x1000U)
+#define SYSCTL0_DSP_VECT_REMAP_STATVECSELECT_SHIFT (12U)
+/*! STATVECSELECT - Static Vector Select
+ * 0b0..Selects the primary static vector base address on Fusion DSP (0x0000_0000)
+ * 0b1..Selects the alternate static vector base address on Fusion DSP (0x0040_0000)
+ */
+#define SYSCTL0_DSP_VECT_REMAP_STATVECSELECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_VECT_REMAP_STATVECSELECT_SHIFT)) & SYSCTL0_DSP_VECT_REMAP_STATVECSELECT_MASK)
+/*! @} */
+
+/*! @name DSPSTALL - DSP Stall Control */
+/*! @{ */
+#define SYSCTL0_DSPSTALL_DSPSTALL_MASK (0x1U)
+#define SYSCTL0_DSPSTALL_DSPSTALL_SHIFT (0U)
+/*! DSPSTALL - DSPSTALL
+ * 0b0..Run(Normal mode)
+ * 0b1..Stall mode
+ */
+#define SYSCTL0_DSPSTALL_DSPSTALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSPSTALL_DSPSTALL_SHIFT)) & SYSCTL0_DSPSTALL_DSPSTALL_MASK)
+/*! @} */
+
+/*! @name AHBMATRIXPRIOR - AHB MAX Priority */
+/*! @{ */
+#define SYSCTL0_AHBMATRIXPRIOR_M0_MASK (0x3U)
+#define SYSCTL0_AHBMATRIXPRIOR_M0_SHIFT (0U)
+/*! M0 - Master 0 Priority
+ */
+#define SYSCTL0_AHBMATRIXPRIOR_M0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M0_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M0_MASK)
+#define SYSCTL0_AHBMATRIXPRIOR_M1_MASK (0xCU)
+#define SYSCTL0_AHBMATRIXPRIOR_M1_SHIFT (2U)
+/*! M1 - Master 1 Priority
+ */
+#define SYSCTL0_AHBMATRIXPRIOR_M1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M1_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M1_MASK)
+#define SYSCTL0_AHBMATRIXPRIOR_M2_MASK (0x30U)
+#define SYSCTL0_AHBMATRIXPRIOR_M2_SHIFT (4U)
+/*! M2 - Master 2 Priority
+ */
+#define SYSCTL0_AHBMATRIXPRIOR_M2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M2_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M2_MASK)
+#define SYSCTL0_AHBMATRIXPRIOR_M3_MASK (0xC0U)
+#define SYSCTL0_AHBMATRIXPRIOR_M3_SHIFT (6U)
+/*! M3 - Master 3 Priority
+ */
+#define SYSCTL0_AHBMATRIXPRIOR_M3(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M3_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M3_MASK)
+#define SYSCTL0_AHBMATRIXPRIOR_M4_MASK (0x300U)
+#define SYSCTL0_AHBMATRIXPRIOR_M4_SHIFT (8U)
+/*! M4 - Master 4 Priority
+ */
+#define SYSCTL0_AHBMATRIXPRIOR_M4(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M4_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M4_MASK)
+#define SYSCTL0_AHBMATRIXPRIOR_M5_MASK (0xC00U)
+#define SYSCTL0_AHBMATRIXPRIOR_M5_SHIFT (10U)
+/*! M5 - Master 5 Priority
+ */
+#define SYSCTL0_AHBMATRIXPRIOR_M5(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M5_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M5_MASK)
+#define SYSCTL0_AHBMATRIXPRIOR_M6_MASK (0x3000U)
+#define SYSCTL0_AHBMATRIXPRIOR_M6_SHIFT (12U)
+/*! M6 - Master 6 Priority
+ */
+#define SYSCTL0_AHBMATRIXPRIOR_M6(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M6_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M6_MASK)
+#define SYSCTL0_AHBMATRIXPRIOR_M7_MASK (0xC000U)
+#define SYSCTL0_AHBMATRIXPRIOR_M7_SHIFT (14U)
+/*! M7 - Master 7 Priority
+ */
+#define SYSCTL0_AHBMATRIXPRIOR_M7(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M7_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M7_MASK)
+#define SYSCTL0_AHBMATRIXPRIOR_M8_MASK (0x30000U)
+#define SYSCTL0_AHBMATRIXPRIOR_M8_SHIFT (16U)
+/*! M8 - Master 8 Priority
+ */
+#define SYSCTL0_AHBMATRIXPRIOR_M8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M8_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M8_MASK)
+#define SYSCTL0_AHBMATRIXPRIOR_M9_MASK (0xC0000U)
+#define SYSCTL0_AHBMATRIXPRIOR_M9_SHIFT (18U)
+/*! M9 - Master 9 Priority
+ */
+#define SYSCTL0_AHBMATRIXPRIOR_M9(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M9_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M9_MASK)
+#define SYSCTL0_AHBMATRIXPRIOR_M10_MASK (0x300000U)
+#define SYSCTL0_AHBMATRIXPRIOR_M10_SHIFT (20U)
+/*! M10 - Master 10 Priority
+ */
+#define SYSCTL0_AHBMATRIXPRIOR_M10(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M10_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M10_MASK)
+#define SYSCTL0_AHBMATRIXPRIOR_M11_MASK (0xC00000U)
+#define SYSCTL0_AHBMATRIXPRIOR_M11_SHIFT (22U)
+/*! M11 - Master 10 Priority
+ */
+#define SYSCTL0_AHBMATRIXPRIOR_M11(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M11_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M11_MASK)
+/*! @} */
+
+/*! @name AHBBRIDGEBUFFER - AHB Buffer */
+/*! @{ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE0_MASK (0x1U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE0_SHIFT (0U)
+/*! SLAVE0 - SLAVE0 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE0_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE0_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE1_MASK (0x2U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE1_SHIFT (1U)
+/*! SLAVE1 - SLAVE1 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE1_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE1_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE2_MASK (0x4U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE2_SHIFT (2U)
+/*! SLAVE2 - SLAVE2 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE2_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE2_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE3_MASK (0x8U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE3_SHIFT (3U)
+/*! SLAVE3 - SLAVE3 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE3(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE3_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE3_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE4_MASK (0x10U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE4_SHIFT (4U)
+/*! SLAVE4 - SLAVE4 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE4(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE4_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE4_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE5_MASK (0x20U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE5_SHIFT (5U)
+/*! SLAVE5 - SLAVE5 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE5(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE5_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE5_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE6_MASK (0x40U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE6_SHIFT (6U)
+/*! SLAVE6 - SLAVE6 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE6(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE6_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE6_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE7_MASK (0x80U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE7_SHIFT (7U)
+/*! SLAVE7 - SLAVE7 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE7(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE7_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE7_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE8_MASK (0x100U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE8_SHIFT (8U)
+/*! SLAVE8 - SLAVE8 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE8_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE8_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE9_MASK (0x200U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE9_SHIFT (9U)
+/*! SLAVE9 - SLAVE9 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE9(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE9_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE9_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE10_MASK (0x400U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE10_SHIFT (10U)
+/*! SLAVE10 - SLAVE10 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE10(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE10_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE10_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE11_MASK (0x800U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE11_SHIFT (11U)
+/*! SLAVE11 - SLAVE11 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE11(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE11_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE11_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE12_MASK (0x1000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE12_SHIFT (12U)
+/*! SLAVE12 - SLAVE12 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE12(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE12_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE12_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE13_MASK (0x2000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE13_SHIFT (13U)
+/*! SLAVE13 - SLAVE13 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE13(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE13_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE13_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE14_MASK (0x4000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE14_SHIFT (14U)
+/*! SLAVE14 - SLAVE14 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE14(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE14_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE14_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE15_MASK (0x8000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE15_SHIFT (15U)
+/*! SLAVE15 - SLAVE15 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE15(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE15_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE15_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE16_MASK (0x10000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE16_SHIFT (16U)
+/*! SLAVE16 - SLAVE16 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE16(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE16_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE16_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE17_MASK (0x20000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE17_SHIFT (17U)
+/*! SLAVE17 - SLAVE17 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE17(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE17_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE17_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE18_MASK (0x40000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE18_SHIFT (18U)
+/*! SLAVE18 - SLAVE18 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE18(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE18_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE18_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE19_MASK (0x80000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE19_SHIFT (19U)
+/*! SLAVE19 - SLAVE19 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE19(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE19_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE19_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE20_MASK (0x100000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE20_SHIFT (20U)
+/*! SLAVE20 - SLAVE20 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE20(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE20_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE20_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE21_MASK (0x200000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE21_SHIFT (21U)
+/*! SLAVE21 - SLAVE21 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE21(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE21_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE21_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE22_MASK (0x400000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE22_SHIFT (22U)
+/*! SLAVE22 - SLAVE22 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE22(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE22_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE22_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE23_MASK (0x800000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE23_SHIFT (23U)
+/*! SLAVE23 - SLAVE23 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE23(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE23_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE23_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE24_MASK (0x1000000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE24_SHIFT (24U)
+/*! SLAVE24 - SLAVE24 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE24(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE24_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE24_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE25_MASK (0x2000000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE25_SHIFT (25U)
+/*! SLAVE25 - SLAVE25 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE25(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE25_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE25_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE26_MASK (0x4000000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE26_SHIFT (26U)
+/*! SLAVE26 - SLAVE26 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE26(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE26_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE26_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE27_MASK (0x8000000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE27_SHIFT (27U)
+/*! SLAVE27 - SLAVE27 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE27(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE27_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE27_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE28_MASK (0x10000000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE28_SHIFT (28U)
+/*! SLAVE28 - SLAVE28 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE28(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE28_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE28_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE29_MASK (0x20000000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE29_SHIFT (29U)
+/*! SLAVE29 - SLAVE29 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE29(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE29_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE29_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE30_MASK (0x40000000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE30_SHIFT (30U)
+/*! SLAVE30 - SLAVE30 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE30(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE30_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE30_MASK)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE31_MASK (0x80000000U)
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE31_SHIFT (31U)
+/*! SLAVE31 - SLAVE31 buffering
+ * 0b0..No Buffering
+ * 0b1..Buffering
+ */
+#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE31(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE31_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE31_MASK)
+/*! @} */
+
+/* The count of SYSCTL0_AHBBRIDGEBUFFER */
+#define SYSCTL0_AHBBRIDGEBUFFER_COUNT (2U)
+
+/*! @name BOOTROM_LCKOUT - BOOT ROM lockout */
+/*! @{ */
+#define SYSCTL0_BOOTROM_LCKOUT_READ_LCKOUT_SPACE_MASK (0x1FFFFU)
+#define SYSCTL0_BOOTROM_LCKOUT_READ_LCKOUT_SPACE_SHIFT (0U)
+/*! READ_LCKOUT_SPACE - Read Lockout
+ */
+#define SYSCTL0_BOOTROM_LCKOUT_READ_LCKOUT_SPACE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_BOOTROM_LCKOUT_READ_LCKOUT_SPACE_SHIFT)) & SYSCTL0_BOOTROM_LCKOUT_READ_LCKOUT_SPACE_MASK)
+#define SYSCTL0_BOOTROM_LCKOUT_WRITE_LOCK_MASK (0xC0000000U)
+#define SYSCTL0_BOOTROM_LCKOUT_WRITE_LOCK_SHIFT (30U)
+/*! WRITE_LOCK - Self Write Disable
+ * 0b00..Write disable
+ * 0b01..Write disable
+ * 0b11..Write disable
+ * 0b10..Write enable
+ */
+#define SYSCTL0_BOOTROM_LCKOUT_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_BOOTROM_LCKOUT_WRITE_LOCK_SHIFT)) & SYSCTL0_BOOTROM_LCKOUT_WRITE_LOCK_MASK)
+/*! @} */
+
+/*! @name M33NMISRCSEL - M33 NMI source selection */
+/*! @{ */
+#define SYSCTL0_M33NMISRCSEL_NMISRCSEL_MASK (0x7FU)
+#define SYSCTL0_M33NMISRCSEL_NMISRCSEL_SHIFT (0U)
+/*! NMISRCSEL - Selects one of the M33 interrupt sources as the NMI source interrupt.
+ */
+#define SYSCTL0_M33NMISRCSEL_NMISRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_M33NMISRCSEL_NMISRCSEL_SHIFT)) & SYSCTL0_M33NMISRCSEL_NMISRCSEL_MASK)
+#define SYSCTL0_M33NMISRCSEL_NMI_ENABLE_MASK (0x80000000U)
+#define SYSCTL0_M33NMISRCSEL_NMI_ENABLE_SHIFT (31U)
+/*! NMI_Enable
+ * 0b0..Disable NMI interrupt
+ * 0b1..Enable NMI interrupt
+ */
+#define SYSCTL0_M33NMISRCSEL_NMI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_M33NMISRCSEL_NMI_ENABLE_SHIFT)) & SYSCTL0_M33NMISRCSEL_NMI_ENABLE_MASK)
+/*! @} */
+
+/*! @name SYSTEM_STICK_CALIB - System secure tick calibration */
+/*! @{ */
+#define SYSCTL0_SYSTEM_STICK_CALIB_SYSTEM_STICK_CALIB_MASK (0x7FFFFFFU)
+#define SYSCTL0_SYSTEM_STICK_CALIB_SYSTEM_STICK_CALIB_SHIFT (0U)
+/*! SYSTEM_STICK_CALIB - M33 secure tick calibration
+ */
+#define SYSCTL0_SYSTEM_STICK_CALIB_SYSTEM_STICK_CALIB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SYSTEM_STICK_CALIB_SYSTEM_STICK_CALIB_SHIFT)) & SYSCTL0_SYSTEM_STICK_CALIB_SYSTEM_STICK_CALIB_MASK)
+/*! @} */
+
+/*! @name SYSTEM_NSTICK_CALIB - System non-secure tick calibration */
+/*! @{ */
+#define SYSCTL0_SYSTEM_NSTICK_CALIB_SYSTEM_NSTICK_CALIB_MASK (0x7FFFFFFU)
+#define SYSCTL0_SYSTEM_NSTICK_CALIB_SYSTEM_NSTICK_CALIB_SHIFT (0U)
+/*! SYSTEM_NSTICK_CALIB - M33 non secure tick calibration
+ */
+#define SYSCTL0_SYSTEM_NSTICK_CALIB_SYSTEM_NSTICK_CALIB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SYSTEM_NSTICK_CALIB_SYSTEM_NSTICK_CALIB_SHIFT)) & SYSCTL0_SYSTEM_NSTICK_CALIB_SYSTEM_NSTICK_CALIB_MASK)
+/*! @} */
+
+/*! @name PRODUCT_ID - Product ID */
+/*! @{ */
+#define SYSCTL0_PRODUCT_ID_PRODUCT_ID_MASK (0xFFFFU)
+#define SYSCTL0_PRODUCT_ID_PRODUCT_ID_SHIFT (0U)
+/*! PRODUCT_ID - PRODUCT ID
+ */
+#define SYSCTL0_PRODUCT_ID_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PRODUCT_ID_PRODUCT_ID_SHIFT)) & SYSCTL0_PRODUCT_ID_PRODUCT_ID_MASK)
+/*! @} */
+
+/*! @name SILICONREV_ID - Silicon Revision ID */
+/*! @{ */
+#define SYSCTL0_SILICONREV_ID_MINOR_MASK (0xFU)
+#define SYSCTL0_SILICONREV_ID_MINOR_SHIFT (0U)
+/*! MINOR - MINOR
+ */
+#define SYSCTL0_SILICONREV_ID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SILICONREV_ID_MINOR_SHIFT)) & SYSCTL0_SILICONREV_ID_MINOR_MASK)
+#define SYSCTL0_SILICONREV_ID_MAJOR_MASK (0xF0000U)
+#define SYSCTL0_SILICONREV_ID_MAJOR_SHIFT (16U)
+/*! MAJOR - MAJOR
+ */
+#define SYSCTL0_SILICONREV_ID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SILICONREV_ID_MAJOR_SHIFT)) & SYSCTL0_SILICONREV_ID_MAJOR_MASK)
+/*! @} */
+
+/*! @name JTAG_ID - JTAG ID */
+/*! @{ */
+#define SYSCTL0_JTAG_ID_FIXBIT_MASK (0x1U)
+#define SYSCTL0_JTAG_ID_FIXBIT_SHIFT (0U)
+/*! FIXBIT - JTAG ID fix bit.
+ */
+#define SYSCTL0_JTAG_ID_FIXBIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_JTAG_ID_FIXBIT_SHIFT)) & SYSCTL0_JTAG_ID_FIXBIT_MASK)
+#define SYSCTL0_JTAG_ID_MANU_MASK (0xFFEU)
+#define SYSCTL0_JTAG_ID_MANU_SHIFT (1U)
+/*! MANU - JTAG ID Manufacturer
+ */
+#define SYSCTL0_JTAG_ID_MANU(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_JTAG_ID_MANU_SHIFT)) & SYSCTL0_JTAG_ID_MANU_MASK)
+#define SYSCTL0_JTAG_ID_PRODUCT_ID_MASK (0xFFFF000U)
+#define SYSCTL0_JTAG_ID_PRODUCT_ID_SHIFT (12U)
+/*! PRODUCT_ID - JTAG ID Product ID as defined in the Product ID register
+ */
+#define SYSCTL0_JTAG_ID_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_JTAG_ID_PRODUCT_ID_SHIFT)) & SYSCTL0_JTAG_ID_PRODUCT_ID_MASK)
+#define SYSCTL0_JTAG_ID_CHIPREV_MASK (0xF0000000U)
+#define SYSCTL0_JTAG_ID_CHIPREV_SHIFT (28U)
+/*! CHIPREV - JTAG ID 4-Bit Chip Silicon Revision
+ */
+#define SYSCTL0_JTAG_ID_CHIPREV(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_JTAG_ID_CHIPREV_SHIFT)) & SYSCTL0_JTAG_ID_CHIPREV_MASK)
+/*! @} */
+
+/*! @name NSGPIO_PSYNC - Non-secure GPIO PSYNC */
+/*! @{ */
+#define SYSCTL0_NSGPIO_PSYNC_PSYNC_MASK (0x1U)
+#define SYSCTL0_NSGPIO_PSYNC_PSYNC_SHIFT (0U)
+/*! PSYNC - Synchronization Stage Setting:
+ */
+#define SYSCTL0_NSGPIO_PSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_NSGPIO_PSYNC_PSYNC_SHIFT)) & SYSCTL0_NSGPIO_PSYNC_PSYNC_MASK)
+/*! @} */
+
+/*! @name SGPIO_PSYNC - Secure GPIO PSYNC */
+/*! @{ */
+#define SYSCTL0_SGPIO_PSYNC_PSYNC_MASK (0x1U)
+#define SYSCTL0_SGPIO_PSYNC_PSYNC_SHIFT (0U)
+/*! PSYNC - Synchronization Stage Setting:
+ * 0b0..2-Stage Sync
+ * 0b1..1-Stage Sync
+ */
+#define SYSCTL0_SGPIO_PSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SGPIO_PSYNC_PSYNC_SHIFT)) & SYSCTL0_SGPIO_PSYNC_PSYNC_MASK)
+/*! @} */
+
+/*! @name AUTOCLKGATEOVERRIDE0 - Auto clock gate override 0 */
+/*! @{ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB0_MASK (0x1U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB0_SHIFT (0U)
+/*! AHB2APB0 - AHB2APB0
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB0_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB0_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB1_MASK (0x2U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB1_SHIFT (1U)
+/*! AHB2APB1 - AHB2APB1
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB1_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB1_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_CRC_ENGINE_MASK (0x4U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_CRC_ENGINE_SHIFT (2U)
+/*! CRC_ENGINE - CRC_ENGINE
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_CRC_ENGINE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_CRC_ENGINE_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_CRC_ENGINE_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_CASPER_MASK (0x8U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_CASPER_SHIFT (3U)
+/*! CASPER - CASPER
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_CASPER_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_CASPER_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC0_MASK (0x10U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC0_SHIFT (4U)
+/*! DMAC0 - DMAC0
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC0_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC0_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC1_MASK (0x20U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC1_SHIFT (5U)
+/*! DMAC1 - DMAC1
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC1_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC1_MASK)
+/*! @} */
+
+/*! @name AUTOCLKGATEOVERRIDE1 - Auto clock gate override 1 */
+/*! @{ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM0_IF_MASK (0x1U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM0_IF_SHIFT (0U)
+/*! SRAM0_IF - SRAM0_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM0_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM0_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM0_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM1_IF_MASK (0x2U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM1_IF_SHIFT (1U)
+/*! SRAM1_IF - SRAM1_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM1_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM1_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM1_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM2_IF_MASK (0x4U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM2_IF_SHIFT (2U)
+/*! SRAM2_IF - SRAM2_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM2_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM2_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM2_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM3_IF_MASK (0x8U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM3_IF_SHIFT (3U)
+/*! SRAM3_IF - SRAM3_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM3_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM3_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM3_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM4_IF_MASK (0x10U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM4_IF_SHIFT (4U)
+/*! SRAM4_IF - SRAM4_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM4_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM4_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM4_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM5_IF_MASK (0x20U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM5_IF_SHIFT (5U)
+/*! SRAM5_IF - SRAM5_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM5_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM5_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM5_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM6_IF_MASK (0x40U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM6_IF_SHIFT (6U)
+/*! SRAM6_IF - SRAM6_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM6_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM6_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM6_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM7_IF_MASK (0x80U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM7_IF_SHIFT (7U)
+/*! SRAM7_IF - SRAM7_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM7_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM7_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM7_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM8_IF_MASK (0x100U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM8_IF_SHIFT (8U)
+/*! SRAM8_IF - SRAM8_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM8_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM8_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM8_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM9_IF_MASK (0x200U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM9_IF_SHIFT (9U)
+/*! SRAM9_IF - SRAM9_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM9_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM9_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM9_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM10_IF_MASK (0x400U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM10_IF_SHIFT (10U)
+/*! SRAM10_IF - SRAM10_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM10_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM10_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM10_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM11_IF_MASK (0x800U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM11_IF_SHIFT (11U)
+/*! SRAM11_IF - SRAM11_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM11_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM11_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM11_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM12_IF_MASK (0x1000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM12_IF_SHIFT (12U)
+/*! SRAM12_IF - SRAM12_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM12_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM12_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM12_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM13_IF_MASK (0x2000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM13_IF_SHIFT (13U)
+/*! SRAM13_IF - SRAM13_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM13_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM13_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM13_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM14_IF_MASK (0x4000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM14_IF_SHIFT (14U)
+/*! SRAM14_IF - SRAM14_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM14_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM14_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM14_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM15_IF_MASK (0x8000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM15_IF_SHIFT (15U)
+/*! SRAM15_IF - SRAM15_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM15_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM15_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM15_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM16_IF_MASK (0x10000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM16_IF_SHIFT (16U)
+/*! SRAM16_IF - SRAM16_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM16_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM16_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM16_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM17_IF_MASK (0x20000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM17_IF_SHIFT (17U)
+/*! SRAM17_IF - SRAM17_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM17_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM17_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM17_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM18_IF_MASK (0x40000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM18_IF_SHIFT (18U)
+/*! SRAM18_IF - SRAM18_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM18_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM18_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM18_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM19_IF_MASK (0x80000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM19_IF_SHIFT (19U)
+/*! SRAM19_IF - SRAM19_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM19_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM19_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM19_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM20_IF_MASK (0x100000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM20_IF_SHIFT (20U)
+/*! SRAM20_IF - SRAM20_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM20_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM20_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM20_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM21_IF_MASK (0x200000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM21_IF_SHIFT (21U)
+/*! SRAM21_IF - SRAM21_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM21_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM21_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM21_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM22_IF_MASK (0x400000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM22_IF_SHIFT (22U)
+/*! SRAM22_IF - SRAM22_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM22_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM22_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM22_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM23_IF_MASK (0x800000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM23_IF_SHIFT (23U)
+/*! SRAM23_IF - SRAM23_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM23_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM23_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM23_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM24_IF_MASK (0x1000000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM24_IF_SHIFT (24U)
+/*! SRAM24_IF - SRAM24_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM24_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM24_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM24_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM25_IF_MASK (0x2000000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM25_IF_SHIFT (25U)
+/*! SRAM25_IF - SRAM25_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM25_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM25_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM25_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM26_IF_MASK (0x4000000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM26_IF_SHIFT (26U)
+/*! SRAM26_IF - SRAM26_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM26_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM26_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM26_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM27_IF_MASK (0x8000000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM27_IF_SHIFT (27U)
+/*! SRAM27_IF - SRAM27_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM27_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM27_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM27_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM28_IF_MASK (0x10000000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM28_IF_SHIFT (28U)
+/*! SRAM28_IF - SRAM28_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM28_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM28_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM28_IF_MASK)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM29_IF_MASK (0x20000000U)
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM29_IF_SHIFT (29U)
+/*! SRAM29_IF - SRAM29_IF
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM29_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM29_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM29_IF_MASK)
+/*! @} */
+
+/*! @name CLKGATEOVERRIDE0 - Clock gate override 0 */
+/*! @{ */
+#define SYSCTL0_CLKGATEOVERRIDE0_SDIO0_MASK (0x1U)
+#define SYSCTL0_CLKGATEOVERRIDE0_SDIO0_SHIFT (0U)
+/*! SDIO0 - SDIO0
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_CLKGATEOVERRIDE0_SDIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLKGATEOVERRIDE0_SDIO0_SHIFT)) & SYSCTL0_CLKGATEOVERRIDE0_SDIO0_MASK)
+#define SYSCTL0_CLKGATEOVERRIDE0_SDIO1_MASK (0x2U)
+#define SYSCTL0_CLKGATEOVERRIDE0_SDIO1_SHIFT (1U)
+/*! SDIO1 - SDIO1
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_CLKGATEOVERRIDE0_SDIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLKGATEOVERRIDE0_SDIO1_SHIFT)) & SYSCTL0_CLKGATEOVERRIDE0_SDIO1_MASK)
+#define SYSCTL0_CLKGATEOVERRIDE0_USBPHY_MASK (0x4U)
+#define SYSCTL0_CLKGATEOVERRIDE0_USBPHY_SHIFT (2U)
+/*! USBPHY - USBPHY
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_CLKGATEOVERRIDE0_USBPHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLKGATEOVERRIDE0_USBPHY_SHIFT)) & SYSCTL0_CLKGATEOVERRIDE0_USBPHY_MASK)
+#define SYSCTL0_CLKGATEOVERRIDE0_ADC_MASK (0x8U)
+#define SYSCTL0_CLKGATEOVERRIDE0_ADC_SHIFT (3U)
+/*! ADC - ADC
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_CLKGATEOVERRIDE0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLKGATEOVERRIDE0_ADC_SHIFT)) & SYSCTL0_CLKGATEOVERRIDE0_ADC_MASK)
+#define SYSCTL0_CLKGATEOVERRIDE0_MU_MASK (0x10U)
+#define SYSCTL0_CLKGATEOVERRIDE0_MU_SHIFT (4U)
+/*! MU - MU
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_CLKGATEOVERRIDE0_MU(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLKGATEOVERRIDE0_MU_SHIFT)) & SYSCTL0_CLKGATEOVERRIDE0_MU_MASK)
+#define SYSCTL0_CLKGATEOVERRIDE0_ACMP_MASK (0x20U)
+#define SYSCTL0_CLKGATEOVERRIDE0_ACMP_SHIFT (5U)
+/*! ACMP - ACMP
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_CLKGATEOVERRIDE0_ACMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLKGATEOVERRIDE0_ACMP_SHIFT)) & SYSCTL0_CLKGATEOVERRIDE0_ACMP_MASK)
+#define SYSCTL0_CLKGATEOVERRIDE0_PMC_MASK (0x40U)
+#define SYSCTL0_CLKGATEOVERRIDE0_PMC_SHIFT (6U)
+/*! PMC - PMC
+ * 0b0..Enable clock gating
+ * 0b1..Continuous Clocking
+ */
+#define SYSCTL0_CLKGATEOVERRIDE0_PMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLKGATEOVERRIDE0_PMC_SHIFT)) & SYSCTL0_CLKGATEOVERRIDE0_PMC_MASK)
+/*! @} */
+
+/*! @name AHB_SRAM_ACCESS_DISABLE - AHB SRAM access disable */
+/*! @{ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM00_IF_MASK (0x1U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM00_IF_SHIFT (0U)
+/*! SRAM00_IF - Control AHB access to SRAM partition 0
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM00_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM00_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM00_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM01_IF_MASK (0x2U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM01_IF_SHIFT (1U)
+/*! SRAM01_IF - Control AHB access to SRAM partition 1
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM01_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM01_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM01_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM02_IF_MASK (0x4U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM02_IF_SHIFT (2U)
+/*! SRAM02_IF - Control AHB access to SRAM partition 2
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM02_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM02_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM02_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM03_IF_MASK (0x8U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM03_IF_SHIFT (3U)
+/*! SRAM03_IF - Control AHB access to SRAM partition 3
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM03_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM03_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM03_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM04_IF_MASK (0x10U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM04_IF_SHIFT (4U)
+/*! SRAM04_IF - Control AHB access to SRAM partition 4
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM04_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM04_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM04_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM05_IF_MASK (0x20U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM05_IF_SHIFT (5U)
+/*! SRAM05_IF - Control AHB access to SRAM partition 5
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM05_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM05_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM05_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM06_IF_MASK (0x40U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM06_IF_SHIFT (6U)
+/*! SRAM06_IF - Control AHB access to SRAM partition 6
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM06_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM06_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM06_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM07_IF_MASK (0x80U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM07_IF_SHIFT (7U)
+/*! SRAM07_IF - Control AHB access to SRAM partition 7
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM07_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM07_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM07_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM08_IF_MASK (0x100U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM08_IF_SHIFT (8U)
+/*! SRAM08_IF - Control AHB access to SRAM partition 8
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM08_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM08_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM08_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM09_IF_MASK (0x200U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM09_IF_SHIFT (9U)
+/*! SRAM09_IF - Control AHB access to SRAM partition 9
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM09_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM09_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM09_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM010_IF_MASK (0x400U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM010_IF_SHIFT (10U)
+/*! SRAM010_IF - Control AHB access to SRAM partition 10
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM010_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM010_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM010_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM011_IF_MASK (0x800U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM011_IF_SHIFT (11U)
+/*! SRAM011_IF - Control AHB access to SRAM partition 11
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM011_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM011_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM011_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM012_IF_MASK (0x1000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM012_IF_SHIFT (12U)
+/*! SRAM012_IF - Control AHB access to SRAM partition 12
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM012_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM012_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM012_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM013_IF_MASK (0x2000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM013_IF_SHIFT (13U)
+/*! SRAM013_IF - Control AHB access to SRAM partition 13
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM013_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM013_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM013_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM014_IF_MASK (0x4000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM014_IF_SHIFT (14U)
+/*! SRAM014_IF - Control AHB access to SRAM partition 14
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM014_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM014_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM014_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM015_IF_MASK (0x8000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM015_IF_SHIFT (15U)
+/*! SRAM015_IF - Control AHB access to SRAM partition 15
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM015_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM015_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM015_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM016_IF_MASK (0x10000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM016_IF_SHIFT (16U)
+/*! SRAM016_IF - Control AHB access to SRAM partition 16
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM016_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM016_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM016_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM017_IF_MASK (0x20000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM017_IF_SHIFT (17U)
+/*! SRAM017_IF - Control AHB access to SRAM partition 17
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM017_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM017_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM017_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM018_IF_MASK (0x40000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM018_IF_SHIFT (18U)
+/*! SRAM018_IF - Control AHB access to SRAM partition 18
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM018_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM018_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM018_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM019_IF_MASK (0x80000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM019_IF_SHIFT (19U)
+/*! SRAM019_IF - Control AHB access to SRAM partition 19
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM019_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM019_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM019_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM020_IF_MASK (0x100000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM020_IF_SHIFT (20U)
+/*! SRAM020_IF - Control AHB access to SRAM partition 20
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM020_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM020_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM020_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM021_IF_MASK (0x200000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM021_IF_SHIFT (21U)
+/*! SRAM021_IF - Control AHB access to SRAM partition 21
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM021_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM021_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM021_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM022_IF_MASK (0x400000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM022_IF_SHIFT (22U)
+/*! SRAM022_IF - Control AHB access to SRAM partition 22
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM022_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM022_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM022_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM023_IF_MASK (0x800000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM023_IF_SHIFT (23U)
+/*! SRAM023_IF - Control AHB access to SRAM partition 23
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM023_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM023_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM023_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM024_IF_MASK (0x1000000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM024_IF_SHIFT (24U)
+/*! SRAM024_IF - Control AHB access to SRAM partition 24
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM024_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM024_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM024_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM025_IF_MASK (0x2000000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM025_IF_SHIFT (25U)
+/*! SRAM025_IF - Control AHB access to SRAM partition 25
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM025_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM025_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM025_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM026_IF_MASK (0x4000000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM026_IF_SHIFT (26U)
+/*! SRAM026_IF - Control AHB access to SRAM partition 26
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM026_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM026_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM026_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM027_IF_MASK (0x8000000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM027_IF_SHIFT (27U)
+/*! SRAM027_IF - Control AHB access to SRAM partition 27
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM027_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM027_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM027_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM028_IF_MASK (0x10000000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM028_IF_SHIFT (28U)
+/*! SRAM028_IF - Control AHB access to SRAM partition 28
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM028_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM028_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM028_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM029_IF_MASK (0x20000000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM029_IF_SHIFT (29U)
+/*! SRAM029_IF - Control AHB access to SRAM partition 29
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM029_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM029_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM029_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM030_IF_MASK (0x40000000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM030_IF_SHIFT (30U)
+/*! SRAM030_IF - Control AHB access to SRAM partition 30
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM030_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM030_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM030_IF_MASK)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM031_IF_MASK (0x80000000U)
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM031_IF_SHIFT (31U)
+/*! SRAM031_IF - Control AHB access to SRAM partition 31
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM031_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM031_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM031_IF_MASK)
+/*! @} */
+
+/*! @name AXI_SRAM_ACCESS_DISABLE - AXI SRAM access disable */
+/*! @{ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM00_IF_MASK (0x1U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM00_IF_SHIFT (0U)
+/*! SRAM00_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM00_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM00_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM00_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM01_IF_MASK (0x2U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM01_IF_SHIFT (1U)
+/*! SRAM01_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM01_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM01_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM01_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM02_IF_MASK (0x4U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM02_IF_SHIFT (2U)
+/*! SRAM02_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM02_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM02_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM02_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM03_IF_MASK (0x8U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM03_IF_SHIFT (3U)
+/*! SRAM03_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM03_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM03_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM03_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM04_IF_MASK (0x10U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM04_IF_SHIFT (4U)
+/*! SRAM04_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM04_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM04_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM04_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM05_IF_MASK (0x20U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM05_IF_SHIFT (5U)
+/*! SRAM05_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM05_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM05_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM05_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM06_IF_MASK (0x40U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM06_IF_SHIFT (6U)
+/*! SRAM06_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM06_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM06_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM06_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM07_IF_MASK (0x80U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM07_IF_SHIFT (7U)
+/*! SRAM07_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM07_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM07_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM07_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM08_IF_MASK (0x100U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM08_IF_SHIFT (8U)
+/*! SRAM08_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM08_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM08_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM08_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM09_IF_MASK (0x200U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM09_IF_SHIFT (9U)
+/*! SRAM09_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM09_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM09_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM09_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM010_IF_MASK (0x400U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM010_IF_SHIFT (10U)
+/*! SRAM010_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM010_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM010_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM010_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM011_IF_MASK (0x800U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM011_IF_SHIFT (11U)
+/*! SRAM011_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM011_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM011_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM011_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM012_IF_MASK (0x1000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM012_IF_SHIFT (12U)
+/*! SRAM012_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM012_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM012_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM012_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM013_IF_MASK (0x2000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM013_IF_SHIFT (13U)
+/*! SRAM013_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM013_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM013_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM013_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM014_IF_MASK (0x4000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM014_IF_SHIFT (14U)
+/*! SRAM014_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM014_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM014_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM014_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM015_IF_MASK (0x8000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM015_IF_SHIFT (15U)
+/*! SRAM015_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM015_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM015_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM015_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM016_IF_MASK (0x10000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM016_IF_SHIFT (16U)
+/*! SRAM016_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM016_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM016_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM016_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM017_IF_MASK (0x20000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM017_IF_SHIFT (17U)
+/*! SRAM017_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM017_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM017_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM017_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM018_IF_MASK (0x40000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM018_IF_SHIFT (18U)
+/*! SRAM018_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM018_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM018_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM018_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM019_IF_MASK (0x80000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM019_IF_SHIFT (19U)
+/*! SRAM019_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM019_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM019_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM019_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM020_IF_MASK (0x100000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM020_IF_SHIFT (20U)
+/*! SRAM020_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM020_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM020_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM020_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM021_IF_MASK (0x200000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM021_IF_SHIFT (21U)
+/*! SRAM021_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM021_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM021_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM021_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM022_IF_MASK (0x400000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM022_IF_SHIFT (22U)
+/*! SRAM022_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM022_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM022_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM022_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM023_IF_MASK (0x800000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM023_IF_SHIFT (23U)
+/*! SRAM023_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM023_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM023_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM023_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM024_IF_MASK (0x1000000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM024_IF_SHIFT (24U)
+/*! SRAM024_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM024_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM024_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM024_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM025_IF_MASK (0x2000000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM025_IF_SHIFT (25U)
+/*! SRAM025_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM025_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM025_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM025_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM026_IF_MASK (0x4000000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM026_IF_SHIFT (26U)
+/*! SRAM026_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM026_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM026_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM026_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM027_IF_MASK (0x8000000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM027_IF_SHIFT (27U)
+/*! SRAM027_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM027_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM027_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM027_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM028_IF_MASK (0x10000000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM028_IF_SHIFT (28U)
+/*! SRAM028_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM028_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM028_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM028_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM029_IF_MASK (0x20000000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM029_IF_SHIFT (29U)
+/*! SRAM029_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM029_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM029_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM029_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM030_IF_MASK (0x40000000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM030_IF_SHIFT (30U)
+/*! SRAM030_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM030_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM030_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM030_IF_MASK)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM031_IF_MASK (0x80000000U)
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM031_IF_SHIFT (31U)
+/*! SRAM031_IF - Control AXI access to SRAM partition
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM031_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM031_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM031_IF_MASK)
+/*! @} */
+
+/*! @name DSP_SRAM_ACCESS_DISABLE - DSP SRAM access disable */
+/*! @{ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM0_IF_MASK (0x1U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM0_IF_SHIFT (0U)
+/*! SRAM0_IF - SRAM0_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM0_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM0_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM0_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM1_IF_MASK (0x2U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM1_IF_SHIFT (1U)
+/*! SRAM1_IF - SRAM1_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM1_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM1_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM1_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM2_IF_MASK (0x4U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM2_IF_SHIFT (2U)
+/*! SRAM2_IF - SRAM2_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM2_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM2_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM2_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM3_IF_MASK (0x8U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM3_IF_SHIFT (3U)
+/*! SRAM3_IF - SRAM3_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM3_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM3_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM3_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM4_IF_MASK (0x10U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM4_IF_SHIFT (4U)
+/*! SRAM4_IF - SRAM4_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM4_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM4_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM4_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM5_IF_MASK (0x20U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM5_IF_SHIFT (5U)
+/*! SRAM5_IF - SRAM5_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM5_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM5_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM5_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM6_IF_MASK (0x40U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM6_IF_SHIFT (6U)
+/*! SRAM6_IF - SRAM6_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM6_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM6_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM6_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM7_IF_MASK (0x80U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM7_IF_SHIFT (7U)
+/*! SRAM7_IF - SRAM7_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM7_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM7_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM7_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM8_IF_MASK (0x100U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM8_IF_SHIFT (8U)
+/*! SRAM8_IF - SRAM8_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM8_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM8_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM8_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM9_IF_MASK (0x200U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM9_IF_SHIFT (9U)
+/*! SRAM9_IF - SRAM9_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM9_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM9_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM9_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM10_IF_MASK (0x400U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM10_IF_SHIFT (10U)
+/*! SRAM10_IF - SRAM10_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM10_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM10_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM10_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM11_IF_MASK (0x800U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM11_IF_SHIFT (11U)
+/*! SRAM11_IF - SRAM11_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM11_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM11_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM11_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM12_IF_MASK (0x1000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM12_IF_SHIFT (12U)
+/*! SRAM12_IF - SRAM12_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM12_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM12_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM12_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM13_IF_MASK (0x2000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM13_IF_SHIFT (13U)
+/*! SRAM13_IF - SRAM13_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM13_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM13_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM13_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM14_IF_MASK (0x4000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM14_IF_SHIFT (14U)
+/*! SRAM14_IF - SRAM14_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM14_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM14_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM14_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM15_IF_MASK (0x8000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM15_IF_SHIFT (15U)
+/*! SRAM15_IF - SRAM15_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM15_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM15_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM15_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM16_IF_MASK (0x10000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM16_IF_SHIFT (16U)
+/*! SRAM16_IF - SRAM16_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM16_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM16_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM16_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM17_IF_MASK (0x20000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM17_IF_SHIFT (17U)
+/*! SRAM17_IF - SRAM17_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM17_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM17_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM17_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM18_IF_MASK (0x40000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM18_IF_SHIFT (18U)
+/*! SRAM18_IF - SRAM18_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM18_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM18_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM18_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM19_IF_MASK (0x80000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM19_IF_SHIFT (19U)
+/*! SRAM19_IF - SRAM19_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM19_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM19_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM19_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM20_IF_MASK (0x100000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM20_IF_SHIFT (20U)
+/*! SRAM20_IF - SRAM20_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM20_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM20_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM20_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM21_IF_MASK (0x200000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM21_IF_SHIFT (21U)
+/*! SRAM21_IF - SRAM21_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM21_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM21_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM21_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM22_IF_MASK (0x400000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM22_IF_SHIFT (22U)
+/*! SRAM22_IF - SRAM22_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM22_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM22_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM22_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM23_IF_MASK (0x800000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM23_IF_SHIFT (23U)
+/*! SRAM23_IF - SRAM23_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM23_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM23_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM23_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM24_IF_MASK (0x1000000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM24_IF_SHIFT (24U)
+/*! SRAM24_IF - SRAM24_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM24_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM24_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM24_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM25_IF_MASK (0x2000000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM25_IF_SHIFT (25U)
+/*! SRAM25_IF - SRAM25_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM25_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM25_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM25_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM26_IF_MASK (0x4000000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM26_IF_SHIFT (26U)
+/*! SRAM26_IF - SRAM26_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM26_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM26_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM26_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM27_IF_MASK (0x8000000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM27_IF_SHIFT (27U)
+/*! SRAM27_IF - SRAM27_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM27_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM27_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM27_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM28_IF_MASK (0x10000000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM28_IF_SHIFT (28U)
+/*! SRAM28_IF - SRAM28_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM28_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM28_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM28_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM29_IF_MASK (0x20000000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM29_IF_SHIFT (29U)
+/*! SRAM29_IF - SRAM29_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM29_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM29_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM29_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM30_IF_MASK (0x40000000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM30_IF_SHIFT (30U)
+/*! SRAM30_IF - SRAM30_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM30_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM30_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM30_IF_MASK)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM31_IF_MASK (0x80000000U)
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM31_IF_SHIFT (31U)
+/*! SRAM31_IF - SRAM31_IF
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM31_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM31_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM31_IF_MASK)
+/*! @} */
+
+/*! @name PQ_MEM_CTRL - Power-Quad Memory Control */
+/*! @{ */
+#define SYSCTL0_PQ_MEM_CTRL_SRAM_IG_MASK (0x1U)
+#define SYSCTL0_PQ_MEM_CTRL_SRAM_IG_SHIFT (0U)
+/*! SRAM_IG - SRAM Input Gate - Blocks the read input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_PQ_MEM_CTRL_SRAM_IG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PQ_MEM_CTRL_SRAM_IG_SHIFT)) & SYSCTL0_PQ_MEM_CTRL_SRAM_IG_MASK)
+#define SYSCTL0_PQ_MEM_CTRL_SRAM_STDBY_MASK (0x2U)
+#define SYSCTL0_PQ_MEM_CTRL_SRAM_STDBY_SHIFT (1U)
+/*! SRAM_STDBY - SRAM Standby - Powers the driver to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_PQ_MEM_CTRL_SRAM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PQ_MEM_CTRL_SRAM_STDBY_SHIFT)) & SYSCTL0_PQ_MEM_CTRL_SRAM_STDBY_MASK)
+/*! @} */
+
+/*! @name FLEXSPI0_MEM_CTRL - FlexSPI0 Memory Control */
+/*! @{ */
+#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_RIG_MASK (0x1U)
+#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_RIG_SHIFT (0U)
+/*! MEM_RIG - Memory Read Input Gate - Blocks the read input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_RIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_RIG_MASK)
+#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_WIG_MASK (0x2U)
+#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_WIG_SHIFT (1U)
+/*! MEM_WIG - Memory Write Input Gate - Blocks the write input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_WIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_WIG_MASK)
+#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_STDBY_MASK (0x4U)
+#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_STDBY_SHIFT (2U)
+/*! MEM_STDBY - Memory Standby - Powers the driver to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_STDBY_MASK)
+/*! @} */
+
+/*! @name USBHS_MEM_CTRL - USBHS Memory Control */
+/*! @{ */
+#define SYSCTL0_USBHS_MEM_CTRL_MEM_IG_MASK (0x1U)
+#define SYSCTL0_USBHS_MEM_CTRL_MEM_IG_SHIFT (0U)
+/*! MEM_IG - Memory Input Gate - Blocks the write input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_USBHS_MEM_CTRL_MEM_IG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USBHS_MEM_CTRL_MEM_IG_SHIFT)) & SYSCTL0_USBHS_MEM_CTRL_MEM_IG_MASK)
+#define SYSCTL0_USBHS_MEM_CTRL_MEM_STDBY_MASK (0x2U)
+#define SYSCTL0_USBHS_MEM_CTRL_MEM_STDBY_SHIFT (1U)
+/*! MEM_STDBY - Memory Standby - Powers the driver to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_USBHS_MEM_CTRL_MEM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USBHS_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_USBHS_MEM_CTRL_MEM_STDBY_MASK)
+/*! @} */
+
+/*! @name USDHC0_MEM_CTRL - USDHC0 Memory Control */
+/*! @{ */
+#define SYSCTL0_USDHC0_MEM_CTRL_MEM_RIG_MASK (0x1U)
+#define SYSCTL0_USDHC0_MEM_CTRL_MEM_RIG_SHIFT (0U)
+/*! MEM_RIG - Memory Read Input Gate - Blocks the read input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_USDHC0_MEM_CTRL_MEM_RIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USDHC0_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCTL0_USDHC0_MEM_CTRL_MEM_RIG_MASK)
+#define SYSCTL0_USDHC0_MEM_CTRL_MEM_WIG_MASK (0x2U)
+#define SYSCTL0_USDHC0_MEM_CTRL_MEM_WIG_SHIFT (1U)
+/*! MEM_WIG - Memory Write Input Gate - Blocks the write input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_USDHC0_MEM_CTRL_MEM_WIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USDHC0_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCTL0_USDHC0_MEM_CTRL_MEM_WIG_MASK)
+#define SYSCTL0_USDHC0_MEM_CTRL_MEM_STDBY_MASK (0x4U)
+#define SYSCTL0_USDHC0_MEM_CTRL_MEM_STDBY_SHIFT (2U)
+/*! MEM_STDBY - Memory Standby - Powers the driver to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_USDHC0_MEM_CTRL_MEM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USDHC0_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_USDHC0_MEM_CTRL_MEM_STDBY_MASK)
+/*! @} */
+
+/*! @name USDHC1_MEM_CTRL - USDHC1 Memory Control */
+/*! @{ */
+#define SYSCTL0_USDHC1_MEM_CTRL_MEM_RIG_MASK (0x1U)
+#define SYSCTL0_USDHC1_MEM_CTRL_MEM_RIG_SHIFT (0U)
+/*! MEM_RIG - Memory Read Input Gate - Blocks the read input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_USDHC1_MEM_CTRL_MEM_RIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USDHC1_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCTL0_USDHC1_MEM_CTRL_MEM_RIG_MASK)
+#define SYSCTL0_USDHC1_MEM_CTRL_MEM_WIG_MASK (0x2U)
+#define SYSCTL0_USDHC1_MEM_CTRL_MEM_WIG_SHIFT (1U)
+/*! MEM_WIG - Memory Write Input Gate - Blocks the write input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_USDHC1_MEM_CTRL_MEM_WIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USDHC1_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCTL0_USDHC1_MEM_CTRL_MEM_WIG_MASK)
+#define SYSCTL0_USDHC1_MEM_CTRL_MEM_STDBY_MASK (0x4U)
+#define SYSCTL0_USDHC1_MEM_CTRL_MEM_STDBY_SHIFT (2U)
+/*! MEM_STDBY - Memory Standby - Powers the driver to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_USDHC1_MEM_CTRL_MEM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USDHC1_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_USDHC1_MEM_CTRL_MEM_STDBY_MASK)
+/*! @} */
+
+/*! @name CASPER_MEM_CTRL - CASPER Memory Control */
+/*! @{ */
+#define SYSCTL0_CASPER_MEM_CTRL_MEM_IG_MASK (0x1U)
+#define SYSCTL0_CASPER_MEM_CTRL_MEM_IG_SHIFT (0U)
+/*! MEM_IG - Auto Input Gate Control Disable
+ * 0b0..Input Gate is controlled by auto clock gating signal.
+ * 0b1..Input Gate Is forced low.
+ */
+#define SYSCTL0_CASPER_MEM_CTRL_MEM_IG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CASPER_MEM_CTRL_MEM_IG_SHIFT)) & SYSCTL0_CASPER_MEM_CTRL_MEM_IG_MASK)
+#define SYSCTL0_CASPER_MEM_CTRL_MEM_STDBY_MASK (0x2U)
+#define SYSCTL0_CASPER_MEM_CTRL_MEM_STDBY_SHIFT (1U)
+/*! MEM_STDBY - Auto Standby Control Disable
+ * 0b0..STDBY is controlled by auto clock gating signal.
+ * 0b1..STDBY Is forced low.
+ */
+#define SYSCTL0_CASPER_MEM_CTRL_MEM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CASPER_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_CASPER_MEM_CTRL_MEM_STDBY_MASK)
+/*! @} */
+
+/*! @name ROM_MEM_CTRL - ROM Memory Control */
+/*! @{ */
+#define SYSCTL0_ROM_MEM_CTRL_MEM_IG_MASK (0x1U)
+#define SYSCTL0_ROM_MEM_CTRL_MEM_IG_SHIFT (0U)
+/*! MEM_IG - Memory Input Gate - Blocks the write input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_ROM_MEM_CTRL_MEM_IG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_ROM_MEM_CTRL_MEM_IG_SHIFT)) & SYSCTL0_ROM_MEM_CTRL_MEM_IG_MASK)
+#define SYSCTL0_ROM_MEM_CTRL_MEM_STDBY_MASK (0x2U)
+#define SYSCTL0_ROM_MEM_CTRL_MEM_STDBY_SHIFT (1U)
+/*! MEM_STDBY - Memory Standby - Powers the driver to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_ROM_MEM_CTRL_MEM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_ROM_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_ROM_MEM_CTRL_MEM_STDBY_MASK)
+#define SYSCTL0_ROM_MEM_CTRL_MEM_LS_MASK (0x4U)
+#define SYSCTL0_ROM_MEM_CTRL_MEM_LS_SHIFT (2U)
+/*! MEM_LS - MEM LS
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_ROM_MEM_CTRL_MEM_LS(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_ROM_MEM_CTRL_MEM_LS_SHIFT)) & SYSCTL0_ROM_MEM_CTRL_MEM_LS_MASK)
+/*! @} */
+
+/*! @name FLEXSPI1_MEM_CTRL - FlexSPI1 Memory Control */
+/*! @{ */
+#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_RIG_MASK (0x1U)
+#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_RIG_SHIFT (0U)
+/*! MEM_RIG - Memory Read Input Gate - Blocks the read input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_RIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_RIG_MASK)
+#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_WIG_MASK (0x2U)
+#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_WIG_SHIFT (1U)
+/*! MEM_WIG - Memory Write Input Gate - Blocks the write input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_WIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_WIG_MASK)
+#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_STDBY_MASK (0x4U)
+#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_STDBY_SHIFT (2U)
+/*! MEM_STDBY - Memory Standby - Powers the driver to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_STDBY_MASK)
+/*! @} */
+
+/*! @name GPU_MEM_CTRL - GPU Memory Control */
+/*! @{ */
+#define SYSCTL0_GPU_MEM_CTRL_MEM_RIG_MASK (0x1U)
+#define SYSCTL0_GPU_MEM_CTRL_MEM_RIG_SHIFT (0U)
+/*! MEM_RIG - Memory Read Input Gate - Blocks the read input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_GPU_MEM_CTRL_MEM_RIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_GPU_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCTL0_GPU_MEM_CTRL_MEM_RIG_MASK)
+#define SYSCTL0_GPU_MEM_CTRL_MEM_WIG_MASK (0x2U)
+#define SYSCTL0_GPU_MEM_CTRL_MEM_WIG_SHIFT (1U)
+/*! MEM_WIG - Memory Write Input Gate - Blocks the write input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_GPU_MEM_CTRL_MEM_WIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_GPU_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCTL0_GPU_MEM_CTRL_MEM_WIG_MASK)
+#define SYSCTL0_GPU_MEM_CTRL_MEM_STDBY_MASK (0x4U)
+#define SYSCTL0_GPU_MEM_CTRL_MEM_STDBY_SHIFT (2U)
+/*! MEM_STDBY - Memory Standby - Powers the driver to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_GPU_MEM_CTRL_MEM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_GPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_GPU_MEM_CTRL_MEM_STDBY_MASK)
+/*! @} */
+
+/*! @name MIPI_MEM_CTRL - MIPI Memory Control */
+/*! @{ */
+#define SYSCTL0_MIPI_MEM_CTRL_MEM_RIG_MASK (0x1U)
+#define SYSCTL0_MIPI_MEM_CTRL_MEM_RIG_SHIFT (0U)
+/*! MEM_RIG - Memory Read Input Gate - Blocks the read input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_MIPI_MEM_CTRL_MEM_RIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCTL0_MIPI_MEM_CTRL_MEM_RIG_MASK)
+#define SYSCTL0_MIPI_MEM_CTRL_MEM_WIG_MASK (0x2U)
+#define SYSCTL0_MIPI_MEM_CTRL_MEM_WIG_SHIFT (1U)
+/*! MEM_WIG - Memory Write Input Gate - Blocks the write input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_MIPI_MEM_CTRL_MEM_WIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCTL0_MIPI_MEM_CTRL_MEM_WIG_MASK)
+#define SYSCTL0_MIPI_MEM_CTRL_MEM_STDBY_MASK (0x4U)
+#define SYSCTL0_MIPI_MEM_CTRL_MEM_STDBY_SHIFT (2U)
+/*! MEM_STDBY - Memory Standby - Powers the driver to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_MIPI_MEM_CTRL_MEM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_MIPI_MEM_CTRL_MEM_STDBY_MASK)
+/*! @} */
+
+/*! @name DCN_MEM_CTRL - LCDIF Memory Control */
+/*! @{ */
+#define SYSCTL0_DCN_MEM_CTRL_MEM_RIG_MASK (0x1U)
+#define SYSCTL0_DCN_MEM_CTRL_MEM_RIG_SHIFT (0U)
+/*! MEM_RIG - Memory Read Input Gate - Blocks the read input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DCN_MEM_CTRL_MEM_RIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DCN_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCTL0_DCN_MEM_CTRL_MEM_RIG_MASK)
+#define SYSCTL0_DCN_MEM_CTRL_MEM_WIG_MASK (0x2U)
+#define SYSCTL0_DCN_MEM_CTRL_MEM_WIG_SHIFT (1U)
+/*! MEM_WIG - Memory Write Input Gate - Blocks the write input signals to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DCN_MEM_CTRL_MEM_WIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DCN_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCTL0_DCN_MEM_CTRL_MEM_WIG_MASK)
+#define SYSCTL0_DCN_MEM_CTRL_MEM_STDBY_MASK (0x4U)
+#define SYSCTL0_DCN_MEM_CTRL_MEM_STDBY_SHIFT (2U)
+/*! MEM_STDBY - Memory Standby - Powers the driver to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_DCN_MEM_CTRL_MEM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DCN_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_DCN_MEM_CTRL_MEM_STDBY_MASK)
+/*! @} */
+
+/*! @name SMARTDMA_MEM_CTRL - SMARTDMA Memory Control */
+/*! @{ */
+#define SYSCTL0_SMARTDMA_MEM_CTRL_MEM_IG_MASK (0x1U)
+#define SYSCTL0_SMARTDMA_MEM_CTRL_MEM_IG_SHIFT (0U)
+/*! MEM_IG - Memory Input Gate
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_SMARTDMA_MEM_CTRL_MEM_IG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SMARTDMA_MEM_CTRL_MEM_IG_SHIFT)) & SYSCTL0_SMARTDMA_MEM_CTRL_MEM_IG_MASK)
+#define SYSCTL0_SMARTDMA_MEM_CTRL_MEM_STDBY_MASK (0x2U)
+#define SYSCTL0_SMARTDMA_MEM_CTRL_MEM_STDBY_SHIFT (1U)
+/*! MEM_STDBY - Memory Standby - Powers the driver to dual-port memory
+ * 0b0..Enable
+ * 0b1..Disable
+ */
+#define SYSCTL0_SMARTDMA_MEM_CTRL_MEM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SMARTDMA_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_SMARTDMA_MEM_CTRL_MEM_STDBY_MASK)
+/*! @} */
+
+/*! @name MIPI_DSI_CTRL - MIPI DSI Control */
+/*! @{ */
+#define SYSCTL0_MIPI_DSI_CTRL_DSI_SD_MASK (0x1U)
+#define SYSCTL0_MIPI_DSI_CTRL_DSI_SD_SHIFT (0U)
+/*! DSI_SD - DSI Shutdown Control.
+ * 0b0..Shutdown command not to be sent to the Type-4 display (default).
+ * 0b1..Shutdown command to be sent to the Type-4 display
+ */
+#define SYSCTL0_MIPI_DSI_CTRL_DSI_SD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_DSI_CTRL_DSI_SD_SHIFT)) & SYSCTL0_MIPI_DSI_CTRL_DSI_SD_MASK)
+#define SYSCTL0_MIPI_DSI_CTRL_DSI_CM_MASK (0x2U)
+#define SYSCTL0_MIPI_DSI_CTRL_DSI_CM_SHIFT (1U)
+/*! DSI_CM - DSI Color Mode Control.
+ * 0b0..Normal mode (full color) (default)
+ * 0b1..Low color mode (8-bit)
+ */
+#define SYSCTL0_MIPI_DSI_CTRL_DSI_CM(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_DSI_CTRL_DSI_CM_SHIFT)) & SYSCTL0_MIPI_DSI_CTRL_DSI_CM_MASK)
+#define SYSCTL0_MIPI_DSI_CTRL_DSI_TX_ACTIVE_MASK (0x4U)
+#define SYSCTL0_MIPI_DSI_CTRL_DSI_TX_ACTIVE_SHIFT (2U)
+/*! DSI_TX_ACTIVE - DSI TX ACTIVE
+ */
+#define SYSCTL0_MIPI_DSI_CTRL_DSI_TX_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_DSI_CTRL_DSI_TX_ACTIVE_SHIFT)) & SYSCTL0_MIPI_DSI_CTRL_DSI_TX_ACTIVE_MASK)
+/*! @} */
+
+/*! @name USB0CLKCTRL - USB Clock Control */
+/*! @{ */
+#define SYSCTL0_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U)
+#define SYSCTL0_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U)
+/*! AP_FS_DEV_CLK - USB0 Device need clock signal control
+ * 0b0..Under hardware control
+ * 0b1..Forced high
+ */
+#define SYSCTL0_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCTL0_USB0CLKCTRL_AP_FS_DEV_CLK_MASK)
+#define SYSCTL0_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U)
+#define SYSCTL0_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U)
+/*! POL_FS_DEV_CLK - USB0 Device need clock polarity for triggering the USB0 wake-up interrupt
+ * 0b0..Falling edge of device need_clock triggers wake-up
+ * 0b1..Rising edge of device need_clock triggers wake-up
+ */
+#define SYSCTL0_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCTL0_USB0CLKCTRL_POL_FS_DEV_CLK_MASK)
+#define SYSCTL0_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U)
+#define SYSCTL0_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U)
+/*! AP_FS_HOST_CLK - USB0 Host need clock signal control
+ * 0b0..Under hardware control
+ * 0b1..Forced high
+ */
+#define SYSCTL0_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCTL0_USB0CLKCTRL_AP_FS_HOST_CLK_MASK)
+#define SYSCTL0_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U)
+#define SYSCTL0_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
+/*! POL_FS_HOST_CLK - USB0 HOST need clock polarity for triggering the USB0 wake-up interrupt
+ * 0b0..Falling edge of host need_clock triggers wake-up
+ * 0b1..Rising edge of host need_clock triggers wake-up
+ */
+#define SYSCTL0_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCTL0_USB0CLKCTRL_POL_FS_HOST_CLK_MASK)
+#define SYSCTL0_USB0CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U)
+#define SYSCTL0_USB0CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U)
+/*! HS_DEV_WAKEUP_N - External user wake-up signal for device mode
+ * 0b0..Forces USB0 PHY to wake-up
+ * 0b1..Normal USB0 PHY behavior
+ */
+#define SYSCTL0_USB0CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USB0CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCTL0_USB0CLKCTRL_HS_DEV_WAKEUP_N_MASK)
+/*! @} */
+
+/*! @name USB0CLKSTAT - USB Clock Status */
+/*! @{ */
+#define SYSCTL0_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U)
+#define SYSCTL0_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)
+/*! DEV_NEED_CLKST - USB0 Device USB0_NEEDCLK signal status
+ * 0b0..Low
+ * 0b1..High
+ */
+#define SYSCTL0_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCTL0_USB0CLKSTAT_DEV_NEED_CLKST_MASK)
+#define SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)
+#define SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
+/*! HOST_NEED_CLKST - USB0 Device Host USB0_NEEDCLK signal status
+ * 0b0..Low
+ * 0b1..High
+ */
+#define SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK)
+/*! @} */
+
+/*! @name USBPHYPLL0LOCKTIMEDIV2 - USB PHY PLL0 lock time division */
+/*! @{ */
+#define SYSCTL0_USBPHYPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK (0xFFFFU)
+#define SYSCTL0_USBPHYPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT (0U)
+/*! LOCKTIMEDIV2 - USBPHYPLL0 Lock Time
+ */
+#define SYSCTL0_USBPHYPLL0LOCKTIMEDIV2_LOCKTIMEDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USBPHYPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT)) & SYSCTL0_USBPHYPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK)
+/*! @} */
+
+/*! @name PDSLEEPCFG0 - Sleep configuration 0 */
+/*! @{ */
+#define SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF_MASK (0x1U)
+#define SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF_SHIFT (0U)
+/*! MAINCLK_SHUTOFF - Main clock shut off
+ * 0b0..Clocks enabled
+ * 0b1..Clocks disabled
+ */
+#define SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF_SHIFT)) & SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF_MASK)
+#define SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_MASK (0x2U)
+#define SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_SHIFT (1U)
+/*! PMIC_MODE0 - PMIC_MODE0 device pin
+ * 0b0..Set mode to 0
+ * 0b1..Set mode to 1
+ */
+#define SYSCTL0_PDSLEEPCFG0_PMIC_MODE0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_SHIFT)) & SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_MASK)
+#define SYSCTL0_PDSLEEPCFG0_PMIC_MODE1_MASK (0x4U)
+#define SYSCTL0_PDSLEEPCFG0_PMIC_MODE1_SHIFT (2U)
+/*! PMIC_MODE1 - PMIC_MODE1 device pin
+ * 0b0..Set mode to 0
+ * 0b1..Set mode to 1
+ */
+#define SYSCTL0_PDSLEEPCFG0_PMIC_MODE1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_PMIC_MODE1_SHIFT)) & SYSCTL0_PDSLEEPCFG0_PMIC_MODE1_MASK)
+#define SYSCTL0_PDSLEEPCFG0_DEEP_PD_MASK (0x8U)
+#define SYSCTL0_PDSLEEPCFG0_DEEP_PD_SHIFT (3U)
+/*! DEEP_PD - Deep power-down mode
+ * 0b0..VDDCORE supply remains on during WFI (deep_sleep mode)
+ * 0b1..VDDCORE powered-off during WFI (deep_powerdown mode)
+ */
+#define SYSCTL0_PDSLEEPCFG0_DEEP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_DEEP_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_DEEP_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_VDDCOREREG_LP_MASK (0x10U)
+#define SYSCTL0_PDSLEEPCFG0_VDDCOREREG_LP_SHIFT (4U)
+/*! VDDCOREREG_LP - Vddcore regulator mode
+ * 0b0..HP mode
+ * 0b1..LP mode
+ */
+#define SYSCTL0_PDSLEEPCFG0_VDDCOREREG_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_VDDCOREREG_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_VDDCOREREG_LP_MASK)
+#define SYSCTL0_PDSLEEPCFG0_PMCREF_LP_MASK (0x40U)
+#define SYSCTL0_PDSLEEPCFG0_PMCREF_LP_SHIFT (6U)
+/*! PMCREF_LP - Internal PMC references LP mode
+ * 0b0..HP mode
+ * 0b1..LP mode
+ */
+#define SYSCTL0_PDSLEEPCFG0_PMCREF_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_PMCREF_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_PMCREF_LP_MASK)
+#define SYSCTL0_PDSLEEPCFG0_HVD1V8_PD_MASK (0x80U)
+#define SYSCTL0_PDSLEEPCFG0_HVD1V8_PD_SHIFT (7U)
+/*! HVD1V8_PD - HVD
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_HVD1V8_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HVD1V8_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HVD1V8_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_PORCORE_LP_MASK (0x100U)
+#define SYSCTL0_PDSLEEPCFG0_PORCORE_LP_SHIFT (8U)
+/*! PORCORE_LP - LVD
+ * 0b0..HP mode
+ * 0b1..LP mode
+ */
+#define SYSCTL0_PDSLEEPCFG0_PORCORE_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_PORCORE_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_PORCORE_LP_MASK)
+#define SYSCTL0_PDSLEEPCFG0_LVDCORE_LP_MASK (0x200U)
+#define SYSCTL0_PDSLEEPCFG0_LVDCORE_LP_SHIFT (9U)
+/*! LVDCORE_LP - LVD
+ * 0b0..HP mode
+ * 0b1..LP mode
+ */
+#define SYSCTL0_PDSLEEPCFG0_LVDCORE_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_LVDCORE_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_LVDCORE_LP_MASK)
+#define SYSCTL0_PDSLEEPCFG0_HVDCORE_PD_MASK (0x400U)
+#define SYSCTL0_PDSLEEPCFG0_HVDCORE_PD_SHIFT (10U)
+/*! HVDCORE_PD - HVD
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_HVDCORE_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HVDCORE_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HVDCORE_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_RBB_PD_MASK (0x800U)
+#define SYSCTL0_PDSLEEPCFG0_RBB_PD_SHIFT (11U)
+/*! RBB_PD - Reverse body-bias
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_RBB_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_RBB_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_RBB_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_FBB_PD_MASK (0x1000U)
+#define SYSCTL0_PDSLEEPCFG0_FBB_PD_SHIFT (12U)
+/*! FBB_PD - Forward body-bias
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_FBB_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_FBB_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_FBB_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_SYSXTAL_PD_MASK (0x2000U)
+#define SYSCTL0_PDSLEEPCFG0_SYSXTAL_PD_SHIFT (13U)
+/*! SYSXTAL_PD - Main crystal oscillator
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_SYSXTAL_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_SYSXTAL_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_SYSXTAL_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_LPOSC_PD_MASK (0x4000U)
+#define SYSCTL0_PDSLEEPCFG0_LPOSC_PD_SHIFT (14U)
+/*! LPOSC_PD - 1 MHz Low-Power oscillator
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_LPOSC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_LPOSC_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_LPOSC_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_RBBSRAM_PD_MASK (0x8000U)
+#define SYSCTL0_PDSLEEPCFG0_RBBSRAM_PD_SHIFT (15U)
+/*! RBBSRAM_PD - RBBSRAM
+ * 0b0..Enables SRAM Reverse Body Bias
+ * 0b1..Disables SRAM Reverse Body Bias
+ */
+#define SYSCTL0_PDSLEEPCFG0_RBBSRAM_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_RBBSRAM_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_RBBSRAM_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_FFRO_PD_MASK (0x10000U)
+#define SYSCTL0_PDSLEEPCFG0_FFRO_PD_SHIFT (16U)
+/*! FFRO_PD - FRO 192/96 MHz internal oscillator
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_FFRO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_FFRO_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_FFRO_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_SYSPLLLDO_PD_MASK (0x20000U)
+#define SYSCTL0_PDSLEEPCFG0_SYSPLLLDO_PD_SHIFT (17U)
+/*! SYSPLLLDO_PD - System PLL internal regulator
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_SYSPLLLDO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_SYSPLLLDO_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_SYSPLLLDO_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_SYSPLLANA_PD_MASK (0x40000U)
+#define SYSCTL0_PDSLEEPCFG0_SYSPLLANA_PD_SHIFT (18U)
+/*! SYSPLLANA_PD - System PLL analog functions
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_SYSPLLANA_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_SYSPLLANA_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_SYSPLLANA_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_AUDPLLLDO_PD_MASK (0x80000U)
+#define SYSCTL0_PDSLEEPCFG0_AUDPLLLDO_PD_SHIFT (19U)
+/*! AUDPLLLDO_PD - Audio PLL internal regulator
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_AUDPLLLDO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_AUDPLLLDO_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_AUDPLLLDO_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_AUDPLLANA_PD_MASK (0x100000U)
+#define SYSCTL0_PDSLEEPCFG0_AUDPLLANA_PD_SHIFT (20U)
+/*! AUDPLLANA_PD - Audio PLL analog functions
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_AUDPLLANA_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_AUDPLLANA_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_AUDPLLANA_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_ADC_PD_MASK (0x200000U)
+#define SYSCTL0_PDSLEEPCFG0_ADC_PD_SHIFT (21U)
+/*! ADC_PD - ADC analog functions
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_ADC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_ADC_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_ADC_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_ADC_LP_MASK (0x400000U)
+#define SYSCTL0_PDSLEEPCFG0_ADC_LP_SHIFT (22U)
+/*! ADC_LP - ADC low power mode
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_ADC_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_ADC_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_ADC_LP_MASK)
+#define SYSCTL0_PDSLEEPCFG0_ADC_TEMPSNS_PD_MASK (0x800000U)
+#define SYSCTL0_PDSLEEPCFG0_ADC_TEMPSNS_PD_SHIFT (23U)
+/*! ADC_TEMPSNS_PD - ADC temperature sensor
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_ADC_TEMPSNS_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_ADC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_ADC_TEMPSNS_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_PMC_TEMPSNS_PD_MASK (0x1000000U)
+#define SYSCTL0_PDSLEEPCFG0_PMC_TEMPSNS_PD_SHIFT (24U)
+/*! PMC_TEMPSNS_PD - PMC temperature sensor
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_PMC_TEMPSNS_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_PMC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_PMC_TEMPSNS_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_ACMP_PD_MASK (0x2000000U)
+#define SYSCTL0_PDSLEEPCFG0_ACMP_PD_SHIFT (25U)
+/*! ACMP_PD - Analog comparator
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG0_ACMP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_ACMP_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_ACMP_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_VDET_LP_MASK (0x4000000U)
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_VDET_LP_SHIFT (26U)
+/*! HSPAD_FSPI0_VDET_LP - High speed pad voltage detect sleep mode
+ * 0b0..High speed pad vdet in normal mode
+ * 0b1..High speed pad vdet in sleep mode
+ */
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_VDET_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_VDET_LP_MASK)
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_REF_PD_MASK (0x8000000U)
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_REF_PD_SHIFT (27U)
+/*! HSPAD_FSPI0_REF_PD - High speed pad sleep mode
+ * 0b0..High speed pad refs in normal mode
+ * 0b1..High speed pad refs in sleep mode
+ */
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_REF_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_REF_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_VDET_LP_MASK (0x10000000U)
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_VDET_LP_SHIFT (28U)
+/*! HSPAD_SDIO0_VDET_LP - High Speed Pad VDET
+ * 0b0..Normal mode
+ * 0b1..Sleep mode
+ */
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_VDET_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_VDET_LP_MASK)
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_REF_PD_MASK (0x20000000U)
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_REF_PD_SHIFT (29U)
+/*! HSPAD_SDIO0_REF_PD - High Speed Pad VREF
+ * 0b0..Enabled
+ * 0b1..Disabled
+ */
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_REF_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_REF_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_VDET_LP_MASK (0x40000000U)
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_VDET_LP_SHIFT (30U)
+/*! HSPAD_FSPI1_VDET_LP - Hi speed pad voltage detect sleep mode
+ * 0b0..High speed pad vdet in normal mode
+ * 0b1..High speed pad vdet in normal mode
+ */
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_VDET_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_VDET_LP_MASK)
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_REF_PD_MASK (0x80000000U)
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_REF_PD_SHIFT (31U)
+/*! HSPAD_FSPI1_REF_PD - Hi speed pad sleep mode
+ * 0b0..High speed pad refs in normal mode
+ * 0b1..High speed pad refs in sleep mode
+ */
+#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_REF_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_REF_PD_MASK)
+/*! @} */
+
+/*! @name PDSLEEPCFG1 - Sleep configuration 1 */
+/*! @{ */
+#define SYSCTL0_PDSLEEPCFG1_PQ_SRAM_PPD_MASK (0x2U)
+#define SYSCTL0_PDSLEEPCFG1_PQ_SRAM_PPD_SHIFT (1U)
+/*! PQ_SRAM_PPD - Periphery power for PowerQuad RAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_PQ_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_PQ_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_PQ_SRAM_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_APD_MASK (0x4U)
+#define SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_APD_SHIFT (2U)
+/*! FLEXSPI0_SRAM_APD - Array power for FLEXSPI0 RAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_PPD_MASK (0x8U)
+#define SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_PPD_SHIFT (3U)
+/*! FLEXSPI0_SRAM_PPD - Periphery power for FLEXSPI0 RAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_APD_MASK (0x10U)
+#define SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_APD_SHIFT (4U)
+/*! FLEXSPI1_SRAM_APD - Array power for FLEXSPI1 RAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_PPD_MASK (0x20U)
+#define SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_PPD_SHIFT (5U)
+/*! FLEXSPI1_SRAM_PPD - Periphery power for FLEXSPI1 RAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_APD_MASK (0x40U)
+#define SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_APD_SHIFT (6U)
+/*! USBHS_SRAM_APD - Array power for USB RAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_PPD_MASK (0x80U)
+#define SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_PPD_SHIFT (7U)
+/*! USBHS_SRAM_PPD - Periphery power for USB RAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_APD_MASK (0x100U)
+#define SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_APD_SHIFT (8U)
+/*! USDHC0_SRAM_APD - Array power for uSDHC0 (SD/MMC/SDIO interface) RAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_PPD_MASK (0x200U)
+#define SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_PPD_SHIFT (9U)
+/*! USDHC0_SRAM_PPD - Periphery power for uSDHC0 (SD/MMC/SDIO interface) RAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_APD_MASK (0x400U)
+#define SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_APD_SHIFT (10U)
+/*! USDHC1_SRAM_APD - Array power for Casper RAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_PPD_MASK (0x800U)
+#define SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_PPD_SHIFT (11U)
+/*! USDHC1_SRAM_PPD - Periphery power for uSDHC1 (SD/MMC/SDIO interface) RAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_CASPER_SRAM_PPD_MASK (0x2000U)
+#define SYSCTL0_PDSLEEPCFG1_CASPER_SRAM_PPD_SHIFT (13U)
+/*! CASPER_SRAM_PPD - Periphery power for Casper RAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_CASPER_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_CASPER_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_CASPER_SRAM_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_GPU_SRAM_APD_MASK (0x4000U)
+#define SYSCTL0_PDSLEEPCFG1_GPU_SRAM_APD_SHIFT (14U)
+/*! GPU_SRAM_APD - Array Power for GPU SRAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_GPU_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_GPU_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_GPU_SRAM_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_GPU_SRAM_PPD_MASK (0x8000U)
+#define SYSCTL0_PDSLEEPCFG1_GPU_SRAM_PPD_SHIFT (15U)
+/*! GPU_SRAM_PPD - Periphery Power for GPU SRAM
+ * 0b0..Enable
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG1_GPU_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_GPU_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_GPU_SRAM_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_APD_MASK (0x10000U)
+#define SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_APD_SHIFT (16U)
+/*! SMARTDMA_SRAM_APD - Array Power for SMARTDMA SRAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_PPD_MASK (0x20000U)
+#define SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_PPD_SHIFT (17U)
+/*! SMARTDMA_SRAM_PPD - Periphery Power for SMARTDMA SRAM
+ * 0b0..Enable
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_APD_MASK (0x40000U)
+#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_APD_SHIFT (18U)
+/*! MIPIDSI_SRAM_APD - Array Power for MIPIDSI SRAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_PPD_MASK (0x80000U)
+#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_PPD_SHIFT (19U)
+/*! MIPIDSI_SRAM_PPD - Periphery Power for MIPIDSI SRAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_APD_MASK (0x100000U)
+#define SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_APD_SHIFT (20U)
+/*! LCDIF_SRAM_APD - Array Power for LCDIF SRAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_PPD_MASK (0x200000U)
+#define SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_PPD_SHIFT (21U)
+/*! LCDIF_SRAM_PPD - Periphery Power for LCDIF SRAM
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_DSP_PD_MASK (0x2000000U)
+#define SYSCTL0_PDSLEEPCFG1_DSP_PD_SHIFT (25U)
+/*! DSP_PD - DSP
+ * 0b0..DSP not power gated
+ * 0b1..DSP power gated
+ */
+#define SYSCTL0_PDSLEEPCFG1_DSP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_DSP_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_DSP_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_PD_MASK (0x4000000U)
+#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_PD_SHIFT (26U)
+/*! MIPIDSI_PD - MIPIDSI
+ * 0b0..MIPI DSI not power gated
+ * 0b1..MIPI DSI power gated
+ */
+#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_MIPIDSI_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_MIPIDSI_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_OTP_PD_MASK (0x8000000U)
+#define SYSCTL0_PDSLEEPCFG1_OTP_PD_SHIFT (27U)
+/*! OTP_PD - OTP
+ * 0b0..Powered
+ * 0b1..Not Powered
+ */
+#define SYSCTL0_PDSLEEPCFG1_OTP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_OTP_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_OTP_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_ROM_PD_MASK (0x10000000U)
+#define SYSCTL0_PDSLEEPCFG1_ROM_PD_SHIFT (28U)
+/*! ROM_PD - ROM
+ * 0b0..ROM Powered
+ * 0b1..ROM not Powered
+ */
+#define SYSCTL0_PDSLEEPCFG1_ROM_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_ROM_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_ROM_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_VDET_LP_MASK (0x20000000U)
+#define SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_VDET_LP_SHIFT (29U)
+/*! HSPAD_SDIO1_VDET_LP - High speed pad SDIO1 voltage detect sleep mode
+ * 0b0..Normal mode
+ * 0b1..Sleep mode
+ */
+#define SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_VDET_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_VDET_LP_MASK)
+#define SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_REF_PD_MASK (0x40000000U)
+#define SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_REF_PD_SHIFT (30U)
+/*! HSPAD_SDIO1_REF_PD - High speed pad SDIO1 sleep mode
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_REF_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_REF_PD_MASK)
+#define SYSCTL0_PDSLEEPCFG1_SRAM_SLEEP_MASK (0x80000000U)
+#define SYSCTL0_PDSLEEPCFG1_SRAM_SLEEP_SHIFT (31U)
+/*! SRAM_SLEEP - SRAM sleep mode
+ * 0b0..RAM Normal mode
+ * 0b1..RAM Sleep mode. Needed when vddcore can be < 0.850V to ensure contents retained. Memories not accessible in this mode.
+ */
+#define SYSCTL0_PDSLEEPCFG1_SRAM_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_SRAM_SLEEP_SHIFT)) & SYSCTL0_PDSLEEPCFG1_SRAM_SLEEP_MASK)
+/*! @} */
+
+/*! @name PDSLEEPCFG2 - Sleep configuration 2 */
+/*! @{ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF0_APD_MASK (0x1U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF0_APD_SHIFT (0U)
+/*! SRAM_IF0_APD - Array power for RAM interface 0
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF0_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF0_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF0_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF1_APD_MASK (0x2U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF1_APD_SHIFT (1U)
+/*! SRAM_IF1_APD - Array power for RAM interface 1
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF1_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF1_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF1_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF2_APD_MASK (0x4U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF2_APD_SHIFT (2U)
+/*! SRAM_IF2_APD - Array power for RAM interface 2
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF2_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF2_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF2_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF3_APD_MASK (0x8U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF3_APD_SHIFT (3U)
+/*! SRAM_IF3_APD - Array power for RAM interface 3
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF3_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF3_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF3_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF4_APD_MASK (0x10U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF4_APD_SHIFT (4U)
+/*! SRAM_IF4_APD - Array power for RAM interface 4
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF4_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF4_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF4_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF5_APD_MASK (0x20U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF5_APD_SHIFT (5U)
+/*! SRAM_IF5_APD - Array power for RAM interface 5
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF5_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF5_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF5_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF6_APD_MASK (0x40U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF6_APD_SHIFT (6U)
+/*! SRAM_IF6_APD - Array power for RAM interface 6
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF6_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF6_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF6_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF7_APD_MASK (0x80U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF7_APD_SHIFT (7U)
+/*! SRAM_IF7_APD - Array power for RAM interface 7
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF7_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF7_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF7_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF8_APD_MASK (0x100U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF8_APD_SHIFT (8U)
+/*! SRAM_IF8_APD - Array power for RAM interface 8
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF8_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF8_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF8_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF9_APD_MASK (0x200U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF9_APD_SHIFT (9U)
+/*! SRAM_IF9_APD - Array power for RAM interface 9
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF9_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF9_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF9_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF10_APD_MASK (0x400U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF10_APD_SHIFT (10U)
+/*! SRAM_IF10_APD - Array power for RAM interface 10
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF10_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF10_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF10_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF11_APD_MASK (0x800U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF11_APD_SHIFT (11U)
+/*! SRAM_IF11_APD - Array power for RAM interface 11
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF11_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF11_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF11_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF12_APD_MASK (0x1000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF12_APD_SHIFT (12U)
+/*! SRAM_IF12_APD - Array power for RAM interface 12
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF12_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF12_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF12_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF13_APD_MASK (0x2000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF13_APD_SHIFT (13U)
+/*! SRAM_IF13_APD - Array power for RAM interface 13
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF13_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF13_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF13_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF14_APD_MASK (0x4000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF14_APD_SHIFT (14U)
+/*! SRAM_IF14_APD - Array power for RAM interface 14
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF14_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF14_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF14_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF15_APD_MASK (0x8000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF15_APD_SHIFT (15U)
+/*! SRAM_IF15_APD - Array power for RAM interface 15
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF15_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF15_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF15_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF16_APD_MASK (0x10000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF16_APD_SHIFT (16U)
+/*! SRAM_IF16_APD - Array power for RAM interface 16
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF16_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF16_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF16_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF17_APD_MASK (0x20000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF17_APD_SHIFT (17U)
+/*! SRAM_IF17_APD - Array power for RAM interface 17
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF17_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF17_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF17_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF18_APD_MASK (0x40000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF18_APD_SHIFT (18U)
+/*! SRAM_IF18_APD - Array power for RAM interface 18
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF18_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF18_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF18_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF19_APD_MASK (0x80000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF19_APD_SHIFT (19U)
+/*! SRAM_IF19_APD - Array power for RAM interface 19
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF19_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF19_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF19_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF20_APD_MASK (0x100000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF20_APD_SHIFT (20U)
+/*! SRAM_IF20_APD - Array power for RAM interface 20
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF20_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF20_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF20_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF21_APD_MASK (0x200000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF21_APD_SHIFT (21U)
+/*! SRAM_IF21_APD - Array power for RAM interface 21
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF21_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF21_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF21_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF22_APD_MASK (0x400000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF22_APD_SHIFT (22U)
+/*! SRAM_IF22_APD - Array power for RAM interface 22
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF22_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF22_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF22_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF23_APD_MASK (0x800000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF23_APD_SHIFT (23U)
+/*! SRAM_IF23_APD - Array power for RAM interface 23
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF23_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF23_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF23_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF24_APD_MASK (0x1000000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF24_APD_SHIFT (24U)
+/*! SRAM_IF24_APD - Array power for RAM interface 24
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF24_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF24_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF24_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF25_APD_MASK (0x2000000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF25_APD_SHIFT (25U)
+/*! SRAM_IF25_APD - Array power for RAM interface 25
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF25_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF25_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF25_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF26_APD_MASK (0x4000000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF26_APD_SHIFT (26U)
+/*! SRAM_IF26_APD - Array power for RAM interface 26
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF26_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF26_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF26_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF27_APD_MASK (0x8000000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF27_APD_SHIFT (27U)
+/*! SRAM_IF27_APD - Array power for RAM interface 27
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF27_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF27_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF27_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF28_APD_MASK (0x10000000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF28_APD_SHIFT (28U)
+/*! SRAM_IF28_APD - Array power for RAM interface 28
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF28_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF28_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF28_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF29_APD_MASK (0x20000000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF29_APD_SHIFT (29U)
+/*! SRAM_IF29_APD - Array power for RAM interface 29
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF29_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF29_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF29_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF30_APD_MASK (0x40000000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF30_APD_SHIFT (30U)
+/*! SRAM_IF30_APD - Array power for RAM interface 30
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF30_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF30_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF30_APD_MASK)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF31_APD_MASK (0x80000000U)
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF31_APD_SHIFT (31U)
+/*! SRAM_IF31_APD - Array power for RAM interface 31
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG2_SRAM_IF31_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF31_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF31_APD_MASK)
+/*! @} */
+
+/*! @name PDSLEEPCFG3 - Sleep configuration 3 */
+/*! @{ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF0_PPD_MASK (0x1U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF0_PPD_SHIFT (0U)
+/*! SRAM_IF0_PPD - Periphery power for RAM interface 0
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF0_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF0_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF0_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF1_PPD_MASK (0x2U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF1_PPD_SHIFT (1U)
+/*! SRAM_IF1_PPD - Periphery power for RAM interface 1
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF1_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF1_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF1_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF2_PPD_MASK (0x4U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF2_PPD_SHIFT (2U)
+/*! SRAM_IF2_PPD - Periphery power for RAM interface 2
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF2_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF2_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF2_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF3_PPD_MASK (0x8U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF3_PPD_SHIFT (3U)
+/*! SRAM_IF3_PPD - Periphery power for RAM interface 3
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF3_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF3_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF3_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF4_PPD_MASK (0x10U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF4_PPD_SHIFT (4U)
+/*! SRAM_IF4_PPD - Periphery power for RAM interface 4
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF4_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF4_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF4_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF5_PPD_MASK (0x20U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF5_PPD_SHIFT (5U)
+/*! SRAM_IF5_PPD - Periphery power for RAM interface 5
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF5_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF5_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF5_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF6_PPD_MASK (0x40U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF6_PPD_SHIFT (6U)
+/*! SRAM_IF6_PPD - Periphery power for RAM interface 6
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF6_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF6_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF6_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF7_PPD_MASK (0x80U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF7_PPD_SHIFT (7U)
+/*! SRAM_IF7_PPD - Periphery power for RAM interface 7
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF7_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF7_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF7_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF8_PPD_MASK (0x100U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF8_PPD_SHIFT (8U)
+/*! SRAM_IF8_PPD - Periphery power for RAM interface 8
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF8_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF8_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF8_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF9_PPD_MASK (0x200U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF9_PPD_SHIFT (9U)
+/*! SRAM_IF9_PPD - Periphery power for RAM interface 9
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF9_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF9_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF9_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF10_PPD_MASK (0x400U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF10_PPD_SHIFT (10U)
+/*! SRAM_IF10_PPD - Periphery power for RAM interface 10
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF10_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF10_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF10_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF11_PPD_MASK (0x800U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF11_PPD_SHIFT (11U)
+/*! SRAM_IF11_PPD - Periphery power for RAM interface 11
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF11_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF11_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF11_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF12_PPD_MASK (0x1000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF12_PPD_SHIFT (12U)
+/*! SRAM_IF12_PPD - Periphery power for RAM interface 12
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF12_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF12_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF12_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF13_PPD_MASK (0x2000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF13_PPD_SHIFT (13U)
+/*! SRAM_IF13_PPD - Periphery power for RAM interface 13
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF13_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF13_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF13_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF14_PPD_MASK (0x4000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF14_PPD_SHIFT (14U)
+/*! SRAM_IF14_PPD - Periphery power for RAM interface 14
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF14_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF14_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF14_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF15_PPD_MASK (0x8000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF15_PPD_SHIFT (15U)
+/*! SRAM_IF15_PPD - Periphery power for RAM interface 15
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF15_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF15_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF15_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF16_PPD_MASK (0x10000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF16_PPD_SHIFT (16U)
+/*! SRAM_IF16_PPD - Periphery power for RAM interface 16
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF16_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF16_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF16_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF17_PPD_MASK (0x20000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF17_PPD_SHIFT (17U)
+/*! SRAM_IF17_PPD - Periphery power for RAM interface 17
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF17_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF17_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF17_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF18_PPD_MASK (0x40000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF18_PPD_SHIFT (18U)
+/*! SRAM_IF18_PPD - Periphery power for RAM interface 18
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF18_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF18_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF18_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF19_PPD_MASK (0x80000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF19_PPD_SHIFT (19U)
+/*! SRAM_IF19_PPD - Periphery power for RAM interface 19
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF19_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF19_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF19_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF20_PPD_MASK (0x100000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF20_PPD_SHIFT (20U)
+/*! SRAM_IF20_PPD - Periphery power for RAM interface 20
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF20_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF20_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF20_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF21_PPD_MASK (0x200000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF21_PPD_SHIFT (21U)
+/*! SRAM_IF21_PPD - Periphery power for RAM interface 21
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF21_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF21_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF21_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF22_PPD_MASK (0x400000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF22_PPD_SHIFT (22U)
+/*! SRAM_IF22_PPD - Periphery power for RAM interface 22
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF22_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF22_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF22_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF23_PPD_MASK (0x800000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF23_PPD_SHIFT (23U)
+/*! SRAM_IF23_PPD - Periphery power for RAM interface 23
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF23_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF23_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF23_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF24_PPD_MASK (0x1000000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF24_PPD_SHIFT (24U)
+/*! SRAM_IF24_PPD - Periphery power for RAM interface 24
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF24_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF24_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF24_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF25_PPD_MASK (0x2000000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF25_PPD_SHIFT (25U)
+/*! SRAM_IF25_PPD - Periphery power for RAM interface 25
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF25_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF25_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF25_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF26_PPD_MASK (0x4000000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF26_PPD_SHIFT (26U)
+/*! SRAM_IF26_PPD - Periphery power for RAM interface 26
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF26_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF26_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF26_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF27_PPD_MASK (0x8000000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF27_PPD_SHIFT (27U)
+/*! SRAM_IF27_PPD - Periphery power for RAM interface 27
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF27_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF27_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF27_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF28_PPD_MASK (0x10000000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF28_PPD_SHIFT (28U)
+/*! SRAM_IF28_PPD - Periphery power for RAM interface 28
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF28_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF28_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF28_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF29_PPD_MASK (0x20000000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF29_PPD_SHIFT (29U)
+/*! SRAM_IF29_PPD - Periphery power for RAM interface 29
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF29_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF29_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF29_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF30_PPD_MASK (0x40000000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF30_PPD_SHIFT (30U)
+/*! SRAM_IF30_PPD - Periphery power for RAM interface 30
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF30_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF30_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF30_PPD_MASK)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF31_PPD_MASK (0x80000000U)
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF31_PPD_SHIFT (31U)
+/*! SRAM_IF31_PPD - Periphery power for RAM interface 31
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDSLEEPCFG3_SRAM_IF31_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF31_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF31_PPD_MASK)
+/*! @} */
+
+/*! @name PDRUNCFG0 - Run configuration 0 */
+/*! @{ */
+#define SYSCTL0_PDRUNCFG0_MAINCLK_SHUTOFF_MASK (0x1U)
+#define SYSCTL0_PDRUNCFG0_MAINCLK_SHUTOFF_SHIFT (0U)
+/*! MAINCLK_SHUTOFF - Main clock shut off
+ * 0b0..Clocks enabled
+ * 0b1..Clocks gated
+ */
+#define SYSCTL0_PDRUNCFG0_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_MAINCLK_SHUTOFF_SHIFT)) & SYSCTL0_PDRUNCFG0_MAINCLK_SHUTOFF_MASK)
+#define SYSCTL0_PDRUNCFG0_PMIC_MODE0_MASK (0x2U)
+#define SYSCTL0_PDRUNCFG0_PMIC_MODE0_SHIFT (1U)
+/*! PMIC_MODE0 - PMIC_MODE0 device pin
+ * 0b0..Set mode to 0
+ * 0b1..Set mode to 1
+ */
+#define SYSCTL0_PDRUNCFG0_PMIC_MODE0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_PMIC_MODE0_SHIFT)) & SYSCTL0_PDRUNCFG0_PMIC_MODE0_MASK)
+#define SYSCTL0_PDRUNCFG0_PMIC_MODE1_MASK (0x4U)
+#define SYSCTL0_PDRUNCFG0_PMIC_MODE1_SHIFT (2U)
+/*! PMIC_MODE1 - PMIC_MODE1 device pin
+ * 0b0..Set mode to 0
+ * 0b1..Set mode to 1
+ */
+#define SYSCTL0_PDRUNCFG0_PMIC_MODE1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_PMIC_MODE1_SHIFT)) & SYSCTL0_PDRUNCFG0_PMIC_MODE1_MASK)
+#define SYSCTL0_PDRUNCFG0_DEEP_PD_MASK (0x8U)
+#define SYSCTL0_PDRUNCFG0_DEEP_PD_SHIFT (3U)
+/*! DEEP_PD - Deep power-down mode
+ * 0b0..VDDCORE supply remains on during WFI (deep_sleep mode)
+ * 0b1..VDDCORE powered-off during WFI (deep_powerdown mode)
+ */
+#define SYSCTL0_PDRUNCFG0_DEEP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_DEEP_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_DEEP_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_VDDCOREREG_LP_MASK (0x10U)
+#define SYSCTL0_PDRUNCFG0_VDDCOREREG_LP_SHIFT (4U)
+/*! VDDCOREREG_LP - Vddcore regulator mode
+ * 0b0..HP mode
+ * 0b1..LP mode
+ */
+#define SYSCTL0_PDRUNCFG0_VDDCOREREG_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_VDDCOREREG_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_VDDCOREREG_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_PMCREF_LP_MASK (0x40U)
+#define SYSCTL0_PDRUNCFG0_PMCREF_LP_SHIFT (6U)
+/*! PMCREF_LP - Internal PMC references LP mode
+ * 0b0..HP mode
+ * 0b1..LP mode
+ */
+#define SYSCTL0_PDRUNCFG0_PMCREF_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_PMCREF_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_PMCREF_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_HVD1V8_PD_MASK (0x80U)
+#define SYSCTL0_PDRUNCFG0_HVD1V8_PD_SHIFT (7U)
+/*! HVD1V8_PD - HVD
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_HVD1V8_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HVD1V8_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_HVD1V8_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_PORCORE_LP_MASK (0x100U)
+#define SYSCTL0_PDRUNCFG0_PORCORE_LP_SHIFT (8U)
+/*! PORCORE_LP - LVD
+ * 0b0..HP mode
+ * 0b1..LP mode
+ */
+#define SYSCTL0_PDRUNCFG0_PORCORE_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_PORCORE_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_PORCORE_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_LVDCORE_LP_MASK (0x200U)
+#define SYSCTL0_PDRUNCFG0_LVDCORE_LP_SHIFT (9U)
+/*! LVDCORE_LP - LVD
+ * 0b0..HP mode
+ * 0b1..LP mode
+ */
+#define SYSCTL0_PDRUNCFG0_LVDCORE_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_LVDCORE_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_LVDCORE_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_HVDCORE_PD_MASK (0x400U)
+#define SYSCTL0_PDRUNCFG0_HVDCORE_PD_SHIFT (10U)
+/*! HVDCORE_PD - HVD
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_HVDCORE_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HVDCORE_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_HVDCORE_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_RBB_PD_MASK (0x800U)
+#define SYSCTL0_PDRUNCFG0_RBB_PD_SHIFT (11U)
+/*! RBB_PD - Reverse body-bias
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_RBB_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_RBB_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_RBB_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_FBB_PD_MASK (0x1000U)
+#define SYSCTL0_PDRUNCFG0_FBB_PD_SHIFT (12U)
+/*! FBB_PD - Forward body-bias
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_FBB_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_FBB_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_FBB_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SYSXTAL_PD_MASK (0x2000U)
+#define SYSCTL0_PDRUNCFG0_SYSXTAL_PD_SHIFT (13U)
+/*! SYSXTAL_PD - Main crystal oscillator
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_SYSXTAL_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SYSXTAL_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SYSXTAL_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_LPOSC_PD_MASK (0x4000U)
+#define SYSCTL0_PDRUNCFG0_LPOSC_PD_SHIFT (14U)
+/*! LPOSC_PD - 1 MHz Low-Power oscillator
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_LPOSC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_LPOSC_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_LPOSC_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_RBBSRAM_PD_MASK (0x8000U)
+#define SYSCTL0_PDRUNCFG0_RBBSRAM_PD_SHIFT (15U)
+/*! RBBSRAM_PD - Reverse body-bias SRAM
+ * 0b0..Enables SRAM Reverse Body Bias
+ * 0b1..Disables SRAM Reverse Body Bias
+ */
+#define SYSCTL0_PDRUNCFG0_RBBSRAM_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_RBBSRAM_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_RBBSRAM_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_FFRO_PD_MASK (0x10000U)
+#define SYSCTL0_PDRUNCFG0_FFRO_PD_SHIFT (16U)
+/*! FFRO_PD - FFRO 192/96 MHz internal oscillator
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_FFRO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_FFRO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_FFRO_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK (0x20000U)
+#define SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_SHIFT (17U)
+/*! SYSPLLLDO_PD - System PLL internal regulator
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK (0x40000U)
+#define SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_SHIFT (18U)
+/*! SYSPLLANA_PD - System PLL analog functions
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_SYSPLLANA_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK (0x80000U)
+#define SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_SHIFT (19U)
+/*! AUDPLLLDO_PD - Audio PLL internal regulator
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK (0x100000U)
+#define SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_SHIFT (20U)
+/*! AUDPLLANA_PD - Audio PLL analog functions
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_AUDPLLANA_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_ADC_PD_MASK (0x200000U)
+#define SYSCTL0_PDRUNCFG0_ADC_PD_SHIFT (21U)
+/*! ADC_PD - ADC analog functions
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_ADC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_ADC_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_ADC_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_ADC_LP_MASK (0x400000U)
+#define SYSCTL0_PDRUNCFG0_ADC_LP_SHIFT (22U)
+/*! ADC_LP - ADC low power mode
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_ADC_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_ADC_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_ADC_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_ADC_TEMPSNS_PD_MASK (0x800000U)
+#define SYSCTL0_PDRUNCFG0_ADC_TEMPSNS_PD_SHIFT (23U)
+/*! ADC_TEMPSNS_PD - ADC temperature sensor
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_ADC_TEMPSNS_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_ADC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_ADC_TEMPSNS_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_PMC_TEMPSNS_PD_MASK (0x1000000U)
+#define SYSCTL0_PDRUNCFG0_PMC_TEMPSNS_PD_SHIFT (24U)
+/*! PMC_TEMPSNS_PD - PMC temperature sensor
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_PMC_TEMPSNS_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_PMC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_PMC_TEMPSNS_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_ACMP_PD_MASK (0x2000000U)
+#define SYSCTL0_PDRUNCFG0_ACMP_PD_SHIFT (25U)
+/*! ACMP_PD - Analog comparator
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG0_ACMP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_ACMP_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_ACMP_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_VDET_LP_MASK (0x4000000U)
+#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_VDET_LP_SHIFT (26U)
+/*! HSPAD_FSPI0_VDET_LP - Hi-speed pad voltage detect sleep mode
+ * 0b0..High speed pad vdet in normal mode
+ * 0b1..High speed pad vdet in sleep mode
+ */
+#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_VDET_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_REF_PD_MASK (0x8000000U)
+#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_REF_PD_SHIFT (27U)
+/*! HSPAD_FSPI0_REF_PD - Hi-speed pad sleep mode
+ * 0b0..High speed pad refs in normal mode
+ * 0b1..High speed pad refs in sleep mode
+ */
+#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_REF_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_VDET_LP_MASK (0x10000000U)
+#define SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_VDET_LP_SHIFT (28U)
+/*! HSPAD_SDIO0_VDET_LP - High Speed Pad VDET
+ * 0b0..Normal mode
+ * 0b1..Sleep mode
+ */
+#define SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_VDET_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_REF_PD_MASK (0x20000000U)
+#define SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_REF_PD_SHIFT (29U)
+/*! HSPAD_SDIO0_REF_PD - High Speed Pad VREF
+ * 0b0..Enabled
+ * 0b1..Disabled
+ */
+#define SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_REF_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_VDET_LP_MASK (0x40000000U)
+#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_VDET_LP_SHIFT (30U)
+/*! HSPAD_FSPI1_VDET_LP - Hi speed pad voltage detect sleep mode
+ * 0b0..High speed pad vdet in normal mode
+ * 0b1..High speed pad vdet in normal mode
+ */
+#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_VDET_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_REF_PD_MASK (0x80000000U)
+#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_REF_PD_SHIFT (31U)
+/*! HSPAD_FSPI1_REF_PD - Hi speed pad sleep mode
+ * 0b0..High speed pad refs in normal mode
+ * 0b1..High speed pad refs in sleep mode
+ */
+#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_REF_PD_MASK)
+/*! @} */
+
+/*! @name PDRUNCFG1 - Run configuration 1 */
+/*! @{ */
+#define SYSCTL0_PDRUNCFG1_PQ_SRAM_PPD_MASK (0x2U)
+#define SYSCTL0_PDRUNCFG1_PQ_SRAM_PPD_SHIFT (1U)
+/*! PQ_SRAM_PPD - Power Quad SRAM Periphery Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG1_PQ_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_PQ_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_PQ_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_APD_MASK (0x4U)
+#define SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_APD_SHIFT (2U)
+/*! FLEXSPI0_SRAM_APD - FLEXSPI0 SRAM Array Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_PPD_MASK (0x8U)
+#define SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_PPD_SHIFT (3U)
+/*! FLEXSPI0_SRAM_PPD - FLEXSPI0 SRAM Periphery Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_MASK (0x10U)
+#define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_SHIFT (4U)
+/*! FLEXSPI1_SRAM_APD - FLEXSPI1 SRAM Array Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_PPD_MASK (0x20U)
+#define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_PPD_SHIFT (5U)
+/*! FLEXSPI1_SRAM_PPD - FLEXSPI1 SRAM Periphery Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_USBHS_SRAM_APD_MASK (0x40U)
+#define SYSCTL0_PDRUNCFG1_USBHS_SRAM_APD_SHIFT (6U)
+/*! USBHS_SRAM_APD - USBHS SRAM Array Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG1_USBHS_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_USBHS_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_USBHS_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_USBHS_SRAM_PPD_MASK (0x80U)
+#define SYSCTL0_PDRUNCFG1_USBHS_SRAM_PPD_SHIFT (7U)
+/*! USBHS_SRAM_PPD - USBHS SRAM Periphery Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG1_USBHS_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_USBHS_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_USBHS_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_USDHC0_SRAM_APD_MASK (0x100U)
+#define SYSCTL0_PDRUNCFG1_USDHC0_SRAM_APD_SHIFT (8U)
+/*! USDHC0_SRAM_APD - USDHC0 SRAM Array Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG1_USDHC0_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_USDHC0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_USDHC0_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_USDHC0_SRAM_PPD_MASK (0x200U)
+#define SYSCTL0_PDRUNCFG1_USDHC0_SRAM_PPD_SHIFT (9U)
+/*! USDHC0_SRAM_PPD - USDHC0 SRAM_ Periphery Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG1_USDHC0_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_USDHC0_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_USDHC0_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_USDHC1_SRAM_APD_MASK (0x400U)
+#define SYSCTL0_PDRUNCFG1_USDHC1_SRAM_APD_SHIFT (10U)
+/*! USDHC1_SRAM_APD - USDHC1 SRAM Array Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG1_USDHC1_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_USDHC1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_USDHC1_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_USDHC1_SRAM_PPD_MASK (0x800U)
+#define SYSCTL0_PDRUNCFG1_USDHC1_SRAM_PPD_SHIFT (11U)
+/*! USDHC1_SRAM_PPD - USDHC1 SRAM Periphery Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG1_USDHC1_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_USDHC1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_USDHC1_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_CASPER_SRAM_PPD_MASK (0x2000U)
+#define SYSCTL0_PDRUNCFG1_CASPER_SRAM_PPD_SHIFT (13U)
+/*! CASPER_SRAM_PPD - CASPER SRAM Periphery Power
+ * 0b0..Enable
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG1_CASPER_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CASPER_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CASPER_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_GPU_SRAM_APD_MASK (0x4000U)
+#define SYSCTL0_PDRUNCFG1_GPU_SRAM_APD_SHIFT (14U)
+/*! GPU_SRAM_APD - GPU Array Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG1_GPU_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_GPU_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_GPU_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_GPU_SRAM_PPD_MASK (0x8000U)
+#define SYSCTL0_PDRUNCFG1_GPU_SRAM_PPD_SHIFT (15U)
+/*! GPU_SRAM_PPD - GPU Periphery Power
+ * 0b0..Enable
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG1_GPU_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_GPU_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_GPU_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_APD_MASK (0x10000U)
+#define SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_APD_SHIFT (16U)
+/*! SMARTDMA_SRAM_APD - SMARTDMA SRAM Array Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_PPD_MASK (0x20000U)
+#define SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_PPD_SHIFT (17U)
+/*! SMARTDMA_SRAM_PPD - SMARTDMA SRAM Periphery Power
+ * 0b0..Enable
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_APD_MASK (0x40000U)
+#define SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_APD_SHIFT (18U)
+/*! MIPIDSI_SRAM_APD - MIPIDSI SRAM Array Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_PPD_MASK (0x80000U)
+#define SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_PPD_SHIFT (19U)
+/*! MIPIDSI_SRAM_PPD - MIPIDSI SRAM Periphery Power
+ * 0b0..Enable
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_LCDIF_SRAM_APD_MASK (0x100000U)
+#define SYSCTL0_PDRUNCFG1_LCDIF_SRAM_APD_SHIFT (20U)
+/*! LCDIF_SRAM_APD - LCDIF SRAM Array Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG1_LCDIF_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_LCDIF_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_LCDIF_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_LCDIF_SRAM_PPD_MASK (0x200000U)
+#define SYSCTL0_PDRUNCFG1_LCDIF_SRAM_PPD_SHIFT (21U)
+/*! LCDIF_SRAM_PPD - LCDIF SRAM Periphery Power
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG1_LCDIF_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_LCDIF_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_LCDIF_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_DSP_PD_MASK (0x2000000U)
+#define SYSCTL0_PDRUNCFG1_DSP_PD_SHIFT (25U)
+/*! DSP_PD - DSP
+ * 0b0..DSP not power gated
+ * 0b1..DSP power gated
+ */
+#define SYSCTL0_PDRUNCFG1_DSP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_DSP_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_DSP_PD_MASK)
+#define SYSCTL0_PDRUNCFG1_MIPIDSI_PD_MASK (0x4000000U)
+#define SYSCTL0_PDRUNCFG1_MIPIDSI_PD_SHIFT (26U)
+/*! MIPIDSI_PD - MIPIDSI
+ * 0b0..MIPI DSI not power gated
+ * 0b1..MIPI DSI power gated
+ */
+#define SYSCTL0_PDRUNCFG1_MIPIDSI_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_MIPIDSI_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_MIPIDSI_PD_MASK)
+#define SYSCTL0_PDRUNCFG1_OTP_PD_MASK (0x8000000U)
+#define SYSCTL0_PDRUNCFG1_OTP_PD_SHIFT (27U)
+/*! OTP_PD - OTP
+ * 0b0..Powered
+ * 0b1..Not Powered
+ */
+#define SYSCTL0_PDRUNCFG1_OTP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_OTP_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_OTP_PD_MASK)
+#define SYSCTL0_PDRUNCFG1_ROM_PD_MASK (0x10000000U)
+#define SYSCTL0_PDRUNCFG1_ROM_PD_SHIFT (28U)
+/*! ROM_PD - Array periphery power for ROM
+ * 0b0..ROM Powered
+ * 0b1..ROM not Powered
+ */
+#define SYSCTL0_PDRUNCFG1_ROM_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_ROM_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_ROM_PD_MASK)
+#define SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_VDET_LP_MASK (0x20000000U)
+#define SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_VDET_LP_SHIFT (29U)
+/*! HSPAD_SDIO1_VDET_LP - High speed pad SDIO1 voltage detect sleep mode
+ * 0b0..Normal mode
+ * 0b1..Sleep mode
+ */
+#define SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_VDET_LP_MASK)
+#define SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_REF_PD_MASK (0x40000000U)
+#define SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_REF_PD_SHIFT (30U)
+/*! HSPAD_SDIO1_REF_PD - High speed pad SDIO1 sleep mode
+ * 0b0..Enabled
+ * 0b1..Powerdown
+ */
+#define SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_REF_PD_MASK)
+#define SYSCTL0_PDRUNCFG1_SRAM_SLEEP_MASK (0x80000000U)
+#define SYSCTL0_PDRUNCFG1_SRAM_SLEEP_SHIFT (31U)
+/*! SRAM_SLEEP - SRAM sleep mode
+ * 0b0..RAM Normal mode
+ * 0b1..RAM Sleep mode. Needed when vddcore can be < 0.850V to ensure contents retained. Memories not accessible in this mode.
+ */
+#define SYSCTL0_PDRUNCFG1_SRAM_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SRAM_SLEEP_SHIFT)) & SYSCTL0_PDRUNCFG1_SRAM_SLEEP_MASK)
+/*! @} */
+
+/*! @name PDRUNCFG2 - Run configuration 2 */
+/*! @{ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF0_APD_MASK (0x1U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF0_APD_SHIFT (0U)
+/*! SRAM_IF0_APD - Array Power for RAM interface 0
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF0_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF0_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF0_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF1_APD_MASK (0x2U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF1_APD_SHIFT (1U)
+/*! SRAM_IF1_APD - Array Power for RAM interface 1
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF1_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF1_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF1_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF2_APD_MASK (0x4U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF2_APD_SHIFT (2U)
+/*! SRAM_IF2_APD - Array Power for RAM interface 2
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF2_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF2_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF2_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF3_APD_MASK (0x8U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF3_APD_SHIFT (3U)
+/*! SRAM_IF3_APD - Array Power for RAM interface 3
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF3_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF3_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF3_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF4_APD_MASK (0x10U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF4_APD_SHIFT (4U)
+/*! SRAM_IF4_APD - Array Power for RAM interface 4
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF4_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF4_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF4_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF5_APD_MASK (0x20U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF5_APD_SHIFT (5U)
+/*! SRAM_IF5_APD - Array Power for RAM interface 5
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF5_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF5_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF5_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF6_APD_MASK (0x40U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF6_APD_SHIFT (6U)
+/*! SRAM_IF6_APD - Array Power for RAM interface 6
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF6_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF6_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF6_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF7_APD_MASK (0x80U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF7_APD_SHIFT (7U)
+/*! SRAM_IF7_APD - Array Power for RAM interface 7
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF7_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF7_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF7_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF8_APD_MASK (0x100U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF8_APD_SHIFT (8U)
+/*! SRAM_IF8_APD - Array Power for RAM interface 8
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF8_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF8_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF8_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF9_APD_MASK (0x200U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF9_APD_SHIFT (9U)
+/*! SRAM_IF9_APD - Array Power for RAM interface 9
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF9_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF9_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF9_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF10_APD_MASK (0x400U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF10_APD_SHIFT (10U)
+/*! SRAM_IF10_APD - Array Power for RAM interface 10
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF10_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF10_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF10_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF11_APD_MASK (0x800U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF11_APD_SHIFT (11U)
+/*! SRAM_IF11_APD - Array Power for RAM interface 11
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF11_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF11_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF11_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF12_APD_MASK (0x1000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF12_APD_SHIFT (12U)
+/*! SRAM_IF12_APD - Array Power for RAM interface 12
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF12_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF12_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF12_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF13_APD_MASK (0x2000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF13_APD_SHIFT (13U)
+/*! SRAM_IF13_APD - Array Power for RAM interface 13
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF13_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF13_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF13_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF14_APD_MASK (0x4000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF14_APD_SHIFT (14U)
+/*! SRAM_IF14_APD - Array Power for RAM interface 14
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF14_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF14_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF14_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF15_APD_MASK (0x8000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF15_APD_SHIFT (15U)
+/*! SRAM_IF15_APD - Array Power for RAM interface 15
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF15_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF15_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF15_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF16_APD_MASK (0x10000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF16_APD_SHIFT (16U)
+/*! SRAM_IF16_APD - Array Power for RAM interface 16
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF16_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF16_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF16_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF17_APD_MASK (0x20000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF17_APD_SHIFT (17U)
+/*! SRAM_IF17_APD - Array Power for RAM interface 17
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF17_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF17_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF17_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF18_APD_MASK (0x40000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF18_APD_SHIFT (18U)
+/*! SRAM_IF18_APD - Array Power for RAM interface 18
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF18_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF18_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF18_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF19_APD_MASK (0x80000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF19_APD_SHIFT (19U)
+/*! SRAM_IF19_APD - Array Power for RAM interface 19
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF19_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF19_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF19_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF20_APD_MASK (0x100000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF20_APD_SHIFT (20U)
+/*! SRAM_IF20_APD - Array Power for RAM interface 20
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF20_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF20_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF20_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF21_APD_MASK (0x200000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF21_APD_SHIFT (21U)
+/*! SRAM_IF21_APD - Array Power for RAM interface 21
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF21_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF21_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF21_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF22_APD_MASK (0x400000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF22_APD_SHIFT (22U)
+/*! SRAM_IF22_APD - Array Power for RAM interface 22
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF22_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF22_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF22_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF23_APD_MASK (0x800000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF23_APD_SHIFT (23U)
+/*! SRAM_IF23_APD - Array Power for RAM interface 23
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF23_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF23_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF23_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF24_APD_MASK (0x1000000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF24_APD_SHIFT (24U)
+/*! SRAM_IF24_APD - Array Power for RAM interface 24
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF24_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF24_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF24_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF25_APD_MASK (0x2000000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF25_APD_SHIFT (25U)
+/*! SRAM_IF25_APD - Array Power for RAM interface 25
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF25_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF25_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF25_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF26_APD_MASK (0x4000000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF26_APD_SHIFT (26U)
+/*! SRAM_IF26_APD - Array Power for RAM interface 26
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF26_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF26_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF26_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF27_APD_MASK (0x8000000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF27_APD_SHIFT (27U)
+/*! SRAM_IF27_APD - Array Power for RAM interface 27
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF27_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF27_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF27_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF28_APD_MASK (0x10000000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF28_APD_SHIFT (28U)
+/*! SRAM_IF28_APD - Array Power for RAM interface 28
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF28_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF28_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF28_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF29_APD_MASK (0x20000000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF29_APD_SHIFT (29U)
+/*! SRAM_IF29_APD - Array Power for RAM interface 29
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF29_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF29_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF29_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF30_APD_MASK (0x40000000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF30_APD_SHIFT (30U)
+/*! SRAM_IF30_APD - Array Power for RAM interface 30
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF30_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF30_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF30_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF31_APD_MASK (0x80000000U)
+#define SYSCTL0_PDRUNCFG2_SRAM_IF31_APD_SHIFT (31U)
+/*! SRAM_IF31_APD - Array Power for RAM interface 31
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG2_SRAM_IF31_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF31_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF31_APD_MASK)
+/*! @} */
+
+/*! @name PDRUNCFG3 - Run configuration 3 */
+/*! @{ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF0_PPD_MASK (0x1U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF0_PPD_SHIFT (0U)
+/*! SRAM_IF0_PPD - Periphery power for RAM interface 0.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF0_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF0_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF0_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF1_PPD_MASK (0x2U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF1_PPD_SHIFT (1U)
+/*! SRAM_IF1_PPD - Periphery power for RAM interface 1.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF1_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF1_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF1_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF2_PPD_MASK (0x4U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF2_PPD_SHIFT (2U)
+/*! SRAM_IF2_PPD - Periphery power for RAM interface 2.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF2_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF2_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF2_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF3_PPD_MASK (0x8U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF3_PPD_SHIFT (3U)
+/*! SRAM_IF3_PPD - Periphery power for RAM interface 3.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF3_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF3_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF3_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF4_PPD_MASK (0x10U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF4_PPD_SHIFT (4U)
+/*! SRAM_IF4_PPD - Periphery power for RAM interface 4.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF4_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF4_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF4_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF5_PPD_MASK (0x20U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF5_PPD_SHIFT (5U)
+/*! SRAM_IF5_PPD - Periphery power for RAM interface 5.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF5_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF5_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF5_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF6_PPD_MASK (0x40U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF6_PPD_SHIFT (6U)
+/*! SRAM_IF6_PPD - Periphery power for RAM interface 6.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF6_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF6_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF6_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF7_PPD_MASK (0x80U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF7_PPD_SHIFT (7U)
+/*! SRAM_IF7_PPD - Periphery power for RAM interface 7.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF7_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF7_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF7_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF8_PPD_MASK (0x100U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF8_PPD_SHIFT (8U)
+/*! SRAM_IF8_PPD - Periphery power for RAM interface 8.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF8_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF8_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF8_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF9_PPD_MASK (0x200U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF9_PPD_SHIFT (9U)
+/*! SRAM_IF9_PPD - Periphery power for RAM interface 9.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF9_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF9_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF9_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF10_PPD_MASK (0x400U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF10_PPD_SHIFT (10U)
+/*! SRAM_IF10_PPD - Periphery power for RAM interface 10.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF10_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF10_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF10_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF11_PPD_MASK (0x800U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF11_PPD_SHIFT (11U)
+/*! SRAM_IF11_PPD - Periphery power for RAM interface 11.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF11_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF11_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF11_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF12_PPD_MASK (0x1000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF12_PPD_SHIFT (12U)
+/*! SRAM_IF12_PPD - Periphery power for RAM interface 12.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF12_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF12_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF12_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF13_PPD_MASK (0x2000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF13_PPD_SHIFT (13U)
+/*! SRAM_IF13_PPD - Periphery power for RAM interface 13.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF13_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF13_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF13_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF14_PPD_MASK (0x4000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF14_PPD_SHIFT (14U)
+/*! SRAM_IF14_PPD - Periphery power for RAM interface 14.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF14_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF14_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF14_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF15_PPD_MASK (0x8000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF15_PPD_SHIFT (15U)
+/*! SRAM_IF15_PPD - Periphery power for RAM interface 15.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF15_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF15_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF15_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF16_PPD_MASK (0x10000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF16_PPD_SHIFT (16U)
+/*! SRAM_IF16_PPD - Periphery power for RAM interface 16.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF16_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF16_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF16_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF17_PPD_MASK (0x20000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF17_PPD_SHIFT (17U)
+/*! SRAM_IF17_PPD - Periphery power for RAM interface 17.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF17_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF17_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF17_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF18_PPD_MASK (0x40000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF18_PPD_SHIFT (18U)
+/*! SRAM_IF18_PPD - Periphery power for RAM interface 18.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF18_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF18_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF18_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF19_PPD_MASK (0x80000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF19_PPD_SHIFT (19U)
+/*! SRAM_IF19_PPD - Periphery power for RAM interface 19.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF19_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF19_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF19_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF20_PPD_MASK (0x100000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF20_PPD_SHIFT (20U)
+/*! SRAM_IF20_PPD - Periphery power for RAM interface 20.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF20_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF20_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF20_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF21_PPD_MASK (0x200000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF21_PPD_SHIFT (21U)
+/*! SRAM_IF21_PPD - Periphery power for RAM interface 21.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF21_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF21_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF21_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF22_PPD_MASK (0x400000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF22_PPD_SHIFT (22U)
+/*! SRAM_IF22_PPD - Periphery power for RAM interface 22.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF22_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF22_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF22_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF23_PPD_MASK (0x800000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF23_PPD_SHIFT (23U)
+/*! SRAM_IF23_PPD - Periphery power for RAM interface 23.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF23_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF23_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF23_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF24_PPD_MASK (0x1000000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF24_PPD_SHIFT (24U)
+/*! SRAM_IF24_PPD - Periphery power for RAM interface 24.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF24_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF24_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF24_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF25_PPD_MASK (0x2000000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF25_PPD_SHIFT (25U)
+/*! SRAM_IF25_PPD - Periphery power for RAM interface 25.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF25_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF25_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF25_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF26_PPD_MASK (0x4000000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF26_PPD_SHIFT (26U)
+/*! SRAM_IF26_PPD - Periphery power for RAM interface 26.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF26_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF26_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF26_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF27_PPD_MASK (0x8000000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF27_PPD_SHIFT (27U)
+/*! SRAM_IF27_PPD - Periphery power for RAM interface 27.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF27_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF27_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF27_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF28_PPD_MASK (0x10000000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF28_PPD_SHIFT (28U)
+/*! SRAM_IF28_PPD - Periphery power for RAM interface 28.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF28_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF28_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF28_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF29_PPD_MASK (0x20000000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF29_PPD_SHIFT (29U)
+/*! SRAM_IF29_PPD - Periphery power for RAM interface 29.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF29_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF29_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF29_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF30_PPD_MASK (0x40000000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF30_PPD_SHIFT (30U)
+/*! SRAM_IF30_PPD - Periphery power for RAM interface 30.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF30_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF30_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF30_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF31_PPD_MASK (0x80000000U)
+#define SYSCTL0_PDRUNCFG3_SRAM_IF31_PPD_SHIFT (31U)
+/*! SRAM_IF31_PPD - Periphery power for RAM interface 31.
+ * 0b0..Power down disabled or Powered ON
+ * 0b1..Power down enabled or Powered OFF
+ */
+#define SYSCTL0_PDRUNCFG3_SRAM_IF31_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF31_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF31_PPD_MASK)
+/*! @} */
+
+/*! @name PDRUNCFG0_SET - Run configuration 0 set */
+/*! @{ */
+#define SYSCTL0_PDRUNCFG0_SET_MAINCLK_SHUTOFF_MASK (0x1U)
+#define SYSCTL0_PDRUNCFG0_SET_MAINCLK_SHUTOFF_SHIFT (0U)
+/*! MAINCLK_SHUTOFF - Main clock shut off
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_MAINCLK_SHUTOFF_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_MAINCLK_SHUTOFF_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_PMIC_MODE0_MASK (0x2U)
+#define SYSCTL0_PDRUNCFG0_SET_PMIC_MODE0_SHIFT (1U)
+/*! PMIC_MODE0 - PMIC_MODE0 pin
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_PMIC_MODE0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_PMIC_MODE0_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_PMIC_MODE0_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_PMIC_MODE1_MASK (0x4U)
+#define SYSCTL0_PDRUNCFG0_SET_PMIC_MODE1_SHIFT (2U)
+/*! PMIC_MODE1 - PMIC_MODE1 pin
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_PMIC_MODE1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_PMIC_MODE1_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_PMIC_MODE1_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_DEEP_PD_MASK (0x8U)
+#define SYSCTL0_PDRUNCFG0_SET_DEEP_PD_SHIFT (3U)
+/*! DEEP_PD - Deep power-down mode
+ * 0b0..VDDCORE supply remains on during WFI (deep_sleep mode)
+ * 0b1..VDDCORE powered-off during WFI (deep_powerdown mode)
+ */
+#define SYSCTL0_PDRUNCFG0_SET_DEEP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_DEEP_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_DEEP_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_VDDCOREREG_LP_MASK (0x10U)
+#define SYSCTL0_PDRUNCFG0_SET_VDDCOREREG_LP_SHIFT (4U)
+/*! VDDCOREREG_LP - Vddcore regulator mode when using on-chip regulator
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_VDDCOREREG_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_VDDCOREREG_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_VDDCOREREG_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_PMCREF_LP_MASK (0x40U)
+#define SYSCTL0_PDRUNCFG0_SET_PMCREF_LP_SHIFT (6U)
+/*! PMCREF_LP - Internal PMC references LP mode
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_PMCREF_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_PMCREF_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_PMCREF_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_HVD1V8_PD_MASK (0x80U)
+#define SYSCTL0_PDRUNCFG0_SET_HVD1V8_PD_SHIFT (7U)
+/*! HVD1V8_PD - HVD
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_HVD1V8_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HVD1V8_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HVD1V8_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_PORCORE_LP_MASK (0x100U)
+#define SYSCTL0_PDRUNCFG0_SET_PORCORE_LP_SHIFT (8U)
+/*! PORCORE_LP - Internal PMC references LP mode
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_PORCORE_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_PORCORE_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_PORCORE_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_LVDCORE_LP_MASK (0x200U)
+#define SYSCTL0_PDRUNCFG0_SET_LVDCORE_LP_SHIFT (9U)
+/*! LVDCORE_LP - LVD
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_LVDCORE_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_LVDCORE_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_LVDCORE_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_HVDCORE_PD_MASK (0x400U)
+#define SYSCTL0_PDRUNCFG0_SET_HVDCORE_PD_SHIFT (10U)
+/*! HVDCORE_PD - HVD
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_HVDCORE_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HVDCORE_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HVDCORE_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_RBB_PD_MASK (0x800U)
+#define SYSCTL0_PDRUNCFG0_SET_RBB_PD_SHIFT (11U)
+/*! RBB_PD - Reverse body-bias
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_RBB_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_RBB_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_RBB_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_FBB_PD_MASK (0x1000U)
+#define SYSCTL0_PDRUNCFG0_SET_FBB_PD_SHIFT (12U)
+/*! FBB_PD - Forward body-bias
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_FBB_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_FBB_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_FBB_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_SYSXTAL_PD_MASK (0x2000U)
+#define SYSCTL0_PDRUNCFG0_SET_SYSXTAL_PD_SHIFT (13U)
+/*! SYSXTAL_PD - Main crystal oscillator
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_SYSXTAL_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_SYSXTAL_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_SYSXTAL_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_LPOSC_PD_MASK (0x4000U)
+#define SYSCTL0_PDRUNCFG0_SET_LPOSC_PD_SHIFT (14U)
+/*! LPOSC_PD - 1 MHz Low-Power oscillator
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_LPOSC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_LPOSC_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_LPOSC_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_RBBSRAM_PD_MASK (0x8000U)
+#define SYSCTL0_PDRUNCFG0_SET_RBBSRAM_PD_SHIFT (15U)
+/*! RBBSRAM_PD - Reverse body-bias SRAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_RBBSRAM_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_RBBSRAM_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_RBBSRAM_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_FFRO_PD_MASK (0x10000U)
+#define SYSCTL0_PDRUNCFG0_SET_FFRO_PD_SHIFT (16U)
+/*! FFRO_PD - FFRO 19296 MHz internal oscillator
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_FFRO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_FFRO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_FFRO_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_SYSPLLLDO_PD_MASK (0x20000U)
+#define SYSCTL0_PDRUNCFG0_SET_SYSPLLLDO_PD_SHIFT (17U)
+/*! SYSPLLLDO_PD - System PLL internal regulator
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_SYSPLLLDO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_SYSPLLLDO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_SYSPLLLDO_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_SYSPLLANA_PD_MASK (0x40000U)
+#define SYSCTL0_PDRUNCFG0_SET_SYSPLLANA_PD_SHIFT (18U)
+/*! SYSPLLANA_PD - System PLL analog functions
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_SYSPLLANA_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_SYSPLLANA_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_SYSPLLANA_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_AUDPLLLDO_PD_MASK (0x80000U)
+#define SYSCTL0_PDRUNCFG0_SET_AUDPLLLDO_PD_SHIFT (19U)
+/*! AUDPLLLDO_PD - Audio PLL internal regulator
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_AUDPLLLDO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_AUDPLLLDO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_AUDPLLLDO_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_AUDPLLANA_PD_MASK (0x100000U)
+#define SYSCTL0_PDRUNCFG0_SET_AUDPLLANA_PD_SHIFT (20U)
+/*! AUDPLLANA_PD - Audio PLL analog functions
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_AUDPLLANA_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_AUDPLLANA_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_AUDPLLANA_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_ADC_PD_MASK (0x200000U)
+#define SYSCTL0_PDRUNCFG0_SET_ADC_PD_SHIFT (21U)
+/*! ADC_PD - ADC analog functions
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_ADC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_ADC_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_ADC_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_ADC_LP_MASK (0x400000U)
+#define SYSCTL0_PDRUNCFG0_SET_ADC_LP_SHIFT (22U)
+/*! ADC_LP - ADC low power mode
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_ADC_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_ADC_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_ADC_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_ADC_TEMPSNS_PD_MASK (0x800000U)
+#define SYSCTL0_PDRUNCFG0_SET_ADC_TEMPSNS_PD_SHIFT (23U)
+/*! ADC_TEMPSNS_PD - ADC temperature sensor
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_ADC_TEMPSNS_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_ADC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_ADC_TEMPSNS_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_PMC_TEMPSNS_PD_MASK (0x1000000U)
+#define SYSCTL0_PDRUNCFG0_SET_PMC_TEMPSNS_PD_SHIFT (24U)
+/*! PMC_TEMPSNS_PD - PMC temperature sensor
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_PMC_TEMPSNS_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_PMC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_PMC_TEMPSNS_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_ACMP_PD_MASK (0x2000000U)
+#define SYSCTL0_PDRUNCFG0_SET_ACMP_PD_SHIFT (25U)
+/*! ACMP_PD - Analog comparator
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_ACMP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_ACMP_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_ACMP_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_VDET_LP_MASK (0x4000000U)
+#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_VDET_LP_SHIFT (26U)
+/*! HSPAD_FSPI0_VDET_LP - High speed pad voltage detect sleep mode
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_VDET_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_REF_PD_MASK (0x8000000U)
+#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_REF_PD_SHIFT (27U)
+/*! HSPAD_FSPI0_REF_PD - High speed pad FSPI0 voltage detect sleep mode
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_REF_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_HSPADVDET_LP_MASK (0x10000000U)
+#define SYSCTL0_PDRUNCFG0_SET_HSPADVDET_LP_SHIFT (28U)
+/*! HSPADVDET_LP - High speed pad FSPI0 voltage detect sleep mode
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_HSPADVDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HSPADVDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HSPADVDET_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_HSPADREF_PD_MASK (0x20000000U)
+#define SYSCTL0_PDRUNCFG0_SET_HSPADREF_PD_SHIFT (29U)
+/*! HSPADREF_PD - High speed pad sleep mode
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_HSPADREF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HSPADREF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HSPADREF_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_VDET_LP_MASK (0x40000000U)
+#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_VDET_LP_SHIFT (30U)
+/*! HSPAD_FSPI1_VDET_LP - High speed pad FSPI1 voltage detect sleep mode
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_VDET_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_REF_PD_MASK (0x80000000U)
+#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_REF_PD_SHIFT (31U)
+/*! HSPAD_FSPI1_REF_PD - High speed pad FSPI1 sleep mode
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_REF_PD_MASK)
+/*! @} */
+
+/*! @name PDRUNCFG1_SET - Run configuration 1 set */
+/*! @{ */
+#define SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_APD_MASK (0x1U)
+#define SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_APD_SHIFT (0U)
+/*! PQ_SRAM_APD - Array power for PowerQuad RAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_PPD_MASK (0x2U)
+#define SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_PPD_SHIFT (1U)
+/*! PQ_SRAM_PPD - Periphery power for PowerQuad RAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_APD_MASK (0x4U)
+#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_APD_SHIFT (2U)
+/*! FLEXSPI0_SRAM_APD - Array power for FLEXSPI0
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_PPD_MASK (0x8U)
+#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_PPD_SHIFT (3U)
+/*! FLEXSPI0_SRAM_PPD - Periphery power for FLEXSPI0
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_APD_MASK (0x10U)
+#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_APD_SHIFT (4U)
+/*! FLEXSPI1_SRAM_APD - Array power for FLEXSPI1
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_MASK (0x20U)
+#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_SHIFT (5U)
+/*! FLEXSPI1_SRAM_PPD - Periphery power for FLEXSPI1
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_APD_MASK (0x40U)
+#define SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_APD_SHIFT (6U)
+/*! USBHS_SRAM_APD - Array power for USB RAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_PPD_MASK (0x80U)
+#define SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_PPD_SHIFT (7U)
+/*! USBHS_SRAM_PPD - Periphery power for USB RAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_APD_MASK (0x100U)
+#define SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_APD_SHIFT (8U)
+/*! USDHC0_SRAM_APD - Array power for uSDHC0 (SD/MMC/SDIO interface) RAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_PPD_MASK (0x200U)
+#define SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_PPD_SHIFT (9U)
+/*! USDHC0_SRAM_PPD - Periphery power for uSDHC0 (SD/MMC/SDIO interface) RAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_APD_MASK (0x400U)
+#define SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_APD_SHIFT (10U)
+/*! USDHC1_SRAM_APD - Array power for uSDHC1 (SD/MMC/SDIO interface) RAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_PPD_MASK (0x800U)
+#define SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_PPD_SHIFT (11U)
+/*! USDHC1_SRAM_PPD - Periphery power for uSDHC1 (SD/MMC/SDIO interface) RAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_CASPER_SRAM_PPD_MASK (0x2000U)
+#define SYSCTL0_PDRUNCFG1_SET_CASPER_SRAM_PPD_SHIFT (13U)
+/*! CASPER_SRAM_PPD - Periphery power for Casper RAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_CASPER_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_CASPER_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_CASPER_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_MASK (0x4000U)
+#define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_SHIFT (14U)
+/*! GPU_SRAM_APD - Array power for GPU SRAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_MASK (0x8000U)
+#define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_SHIFT (15U)
+/*! GPU_SRAM_PPD - Periphery power for GPU SRAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_APD_MASK (0x10000U)
+#define SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_APD_SHIFT (16U)
+/*! SMARTDMA_SRAM_APD - Array power for SMARTDMA SRAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_PPD_MASK (0x20000U)
+#define SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_PPD_SHIFT (17U)
+/*! SMARTDMA_SRAM_PPD - Periphery power for SMARTDMA SRAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_APD_MASK (0x40000U)
+#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_APD_SHIFT (18U)
+/*! MIPIDSI_SRAM_APD - Array power for MIPIDSI SRAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_PPD_MASK (0x80000U)
+#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_PPD_SHIFT (19U)
+/*! MIPIDSI_SRAM_PPD - Periphery power for MIPIDSI SRAM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_APD_MASK (0x100000U)
+#define SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_APD_SHIFT (20U)
+/*! LCDIF_SRAM_APD - Array power for LCDIF
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_PPD_MASK (0x200000U)
+#define SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_PPD_SHIFT (21U)
+/*! LCDIF_SRAM_PPD - Periphery power for LCDIF
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_DSP_PD_MASK (0x2000000U)
+#define SYSCTL0_PDRUNCFG1_SET_DSP_PD_SHIFT (25U)
+/*! DSP_PD - Array and periphery power for DSP
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_DSP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_DSP_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_DSP_PD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_PD_MASK (0x4000000U)
+#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_PD_SHIFT (26U)
+/*! MIPIDSI_PD - Array and periphery power for MIPIDSI
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_MIPIDSI_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_MIPIDSI_PD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_OTP_PD_MASK (0x8000000U)
+#define SYSCTL0_PDRUNCFG1_SET_OTP_PD_SHIFT (27U)
+/*! OTP_PD - Array and periphery power for OTP
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_OTP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_OTP_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_OTP_PD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_ROM_PD_MASK (0x10000000U)
+#define SYSCTL0_PDRUNCFG1_SET_ROM_PD_SHIFT (28U)
+/*! ROM_PD - Array and periphery power for ROM
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_ROM_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_ROM_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_ROM_PD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_VDET_LP_MASK (0x20000000U)
+#define SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_VDET_LP_SHIFT (29U)
+/*! HSPAD_SDIO1_VDET_LP - High speed pad voltage detect sleep mode
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_VDET_LP_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_REF_PD_MASK (0x40000000U)
+#define SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_REF_PD_SHIFT (30U)
+/*! HSPAD_SDIO1_REF_PD - High speed pad sleep mode
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_REF_PD_MASK)
+#define SYSCTL0_PDRUNCFG1_SET_SRAM_SLEEP_MASK (0x80000000U)
+#define SYSCTL0_PDRUNCFG1_SET_SRAM_SLEEP_SHIFT (31U)
+/*! SRAM_SLEEP - SRAM sleep mode
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_SET_SRAM_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_SRAM_SLEEP_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_SRAM_SLEEP_MASK)
+/*! @} */
+
+/*! @name PDRUNCFG2_SET - Run configuration 2 set */
+/*! @{ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF0_APD_MASK (0x1U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF0_APD_SHIFT (0U)
+/*! SRAM_IF0_APD - Array power for SRAM interface 0.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF0_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF0_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF0_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF1_APD_MASK (0x2U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF1_APD_SHIFT (1U)
+/*! SRAM_IF1_APD - Array power for SRAM interface 1.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF1_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF1_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF1_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF2_APD_MASK (0x4U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF2_APD_SHIFT (2U)
+/*! SRAM_IF2_APD - Array power for SRAM interface 2.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF2_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF2_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF2_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF3_APD_MASK (0x8U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF3_APD_SHIFT (3U)
+/*! SRAM_IF3_APD - Array power for SRAM interface 3.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF3_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF3_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF3_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF4_APD_MASK (0x10U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF4_APD_SHIFT (4U)
+/*! SRAM_IF4_APD - Array power for SRAM interface 4.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF4_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF4_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF4_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF5_APD_MASK (0x20U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF5_APD_SHIFT (5U)
+/*! SRAM_IF5_APD - Array power for SRAM interface 5.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF5_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF5_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF5_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF6_APD_MASK (0x40U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF6_APD_SHIFT (6U)
+/*! SRAM_IF6_APD - Array power for SRAM interface 6.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF6_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF6_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF6_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF7_APD_MASK (0x80U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF7_APD_SHIFT (7U)
+/*! SRAM_IF7_APD - Array power for SRAM interface 7.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF7_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF7_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF7_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF8_APD_MASK (0x100U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF8_APD_SHIFT (8U)
+/*! SRAM_IF8_APD - Array power for SRAM interface 8.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF8_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF8_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF8_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF9_APD_MASK (0x200U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF9_APD_SHIFT (9U)
+/*! SRAM_IF9_APD - Array power for SRAM interface 9.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF9_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF9_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF9_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF10_APD_MASK (0x400U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF10_APD_SHIFT (10U)
+/*! SRAM_IF10_APD - Array power for SRAM interface 10.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF10_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF10_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF10_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF11_APD_MASK (0x800U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF11_APD_SHIFT (11U)
+/*! SRAM_IF11_APD - Array power for SRAM interface 11.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF11_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF11_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF11_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF12_APD_MASK (0x1000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF12_APD_SHIFT (12U)
+/*! SRAM_IF12_APD - Array power for SRAM interface 12.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF12_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF12_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF12_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF13_APD_MASK (0x2000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF13_APD_SHIFT (13U)
+/*! SRAM_IF13_APD - Array power for SRAM interface 13.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF13_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF13_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF13_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF14_APD_MASK (0x4000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF14_APD_SHIFT (14U)
+/*! SRAM_IF14_APD - Array power for SRAM interface 14.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF14_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF14_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF14_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF15_APD_MASK (0x8000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF15_APD_SHIFT (15U)
+/*! SRAM_IF15_APD - Array power for SRAM interface 15.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF15_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF15_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF15_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF16_APD_MASK (0x10000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF16_APD_SHIFT (16U)
+/*! SRAM_IF16_APD - Array power for SRAM interface 16.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF16_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF16_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF16_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF17_APD_MASK (0x20000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF17_APD_SHIFT (17U)
+/*! SRAM_IF17_APD - Array power for SRAM interface 17.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF17_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF17_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF17_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF18_APD_MASK (0x40000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF18_APD_SHIFT (18U)
+/*! SRAM_IF18_APD - Array power for SRAM interface 18.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF18_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF18_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF18_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF19_APD_MASK (0x80000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF19_APD_SHIFT (19U)
+/*! SRAM_IF19_APD - Array power for SRAM interface 19.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF19_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF19_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF19_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF20_APD_MASK (0x100000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF20_APD_SHIFT (20U)
+/*! SRAM_IF20_APD - Array power for SRAM interface 20.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF20_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF20_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF20_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF21_APD_MASK (0x200000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF21_APD_SHIFT (21U)
+/*! SRAM_IF21_APD - Array power for SRAM interface 21.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF21_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF21_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF21_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF22_APD_MASK (0x400000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF22_APD_SHIFT (22U)
+/*! SRAM_IF22_APD - Array power for SRAM interface 22.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF22_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF22_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF22_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF23_APD_MASK (0x800000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF23_APD_SHIFT (23U)
+/*! SRAM_IF23_APD - Array power for SRAM interface 23.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF23_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF23_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF23_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF24_APD_MASK (0x1000000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF24_APD_SHIFT (24U)
+/*! SRAM_IF24_APD - Array power for SRAM interface 24.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF24_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF24_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF24_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF25_APD_MASK (0x2000000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF25_APD_SHIFT (25U)
+/*! SRAM_IF25_APD - Array power for SRAM interface 25.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF25_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF25_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF25_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF26_APD_MASK (0x4000000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF26_APD_SHIFT (26U)
+/*! SRAM_IF26_APD - Array power for SRAM interface 26.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF26_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF26_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF26_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF27_APD_MASK (0x8000000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF27_APD_SHIFT (27U)
+/*! SRAM_IF27_APD - Array power for SRAM interface 27.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF27_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF27_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF27_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF28_APD_MASK (0x10000000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF28_APD_SHIFT (28U)
+/*! SRAM_IF28_APD - Array power for SRAM interface 28.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF28_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF28_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF28_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF29_APD_MASK (0x20000000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF29_APD_SHIFT (29U)
+/*! SRAM_IF29_APD - Array power for SRAM interface 29.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF29_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF29_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF29_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF30_APD_MASK (0x40000000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF30_APD_SHIFT (30U)
+/*! SRAM_IF30_APD - Array power for SRAM interface 30.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF30_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF30_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF30_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF31_APD_MASK (0x80000000U)
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF31_APD_SHIFT (31U)
+/*! SRAM_IF31_APD - Array power for SRAM interface 31.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF31_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF31_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF31_APD_MASK)
+/*! @} */
+
+/*! @name PDRUNCFG3_SET - Run configuration 3 set */
+/*! @{ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF0_PPD_MASK (0x1U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF0_PPD_SHIFT (0U)
+/*! SRAM_IF0_PPD - Periphery power for RAM interface 0.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF0_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF0_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF0_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF1_PPD_MASK (0x2U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF1_PPD_SHIFT (1U)
+/*! SRAM_IF1_PPD - Periphery power for RAM interface 1.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF1_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF1_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF1_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF2_PPD_MASK (0x4U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF2_PPD_SHIFT (2U)
+/*! SRAM_IF2_PPD - Periphery power for RAM interface 2.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF2_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF2_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF2_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF3_PPD_MASK (0x8U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF3_PPD_SHIFT (3U)
+/*! SRAM_IF3_PPD - Periphery power for RAM interface 3.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF3_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF3_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF3_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF4_PPD_MASK (0x10U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF4_PPD_SHIFT (4U)
+/*! SRAM_IF4_PPD - Periphery power for RAM interface 4.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF4_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF4_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF4_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF5_PPD_MASK (0x20U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF5_PPD_SHIFT (5U)
+/*! SRAM_IF5_PPD - Periphery power for RAM interface 5.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF5_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF5_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF5_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF6_PPD_MASK (0x40U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF6_PPD_SHIFT (6U)
+/*! SRAM_IF6_PPD - Periphery power for RAM interface 6.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF6_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF6_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF6_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF7_PPD_MASK (0x80U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF7_PPD_SHIFT (7U)
+/*! SRAM_IF7_PPD - Periphery power for RAM interface 7.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF7_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF7_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF7_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF8_PPD_MASK (0x100U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF8_PPD_SHIFT (8U)
+/*! SRAM_IF8_PPD - Periphery power for RAM interface 8.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF8_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF8_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF8_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF9_PPD_MASK (0x200U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF9_PPD_SHIFT (9U)
+/*! SRAM_IF9_PPD - Periphery power for RAM interface 9.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF9_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF9_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF9_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF10_PPD_MASK (0x400U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF10_PPD_SHIFT (10U)
+/*! SRAM_IF10_PPD - Periphery power for RAM interface 10.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF10_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF10_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF10_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF11_PPD_MASK (0x800U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF11_PPD_SHIFT (11U)
+/*! SRAM_IF11_PPD - Periphery power for RAM interface 11.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF11_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF11_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF11_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF12_PPD_MASK (0x1000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF12_PPD_SHIFT (12U)
+/*! SRAM_IF12_PPD - Periphery power for RAM interface 12.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF12_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF12_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF12_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF13_PPD_MASK (0x2000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF13_PPD_SHIFT (13U)
+/*! SRAM_IF13_PPD - Periphery power for RAM interface 13.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF13_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF13_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF13_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF14_PPD_MASK (0x4000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF14_PPD_SHIFT (14U)
+/*! SRAM_IF14_PPD - Periphery power for RAM interface 14.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF14_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF14_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF14_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF15_PPD_MASK (0x8000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF15_PPD_SHIFT (15U)
+/*! SRAM_IF15_PPD - Periphery power for RAM interface 15.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF15_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF15_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF15_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF16_PPD_MASK (0x10000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF16_PPD_SHIFT (16U)
+/*! SRAM_IF16_PPD - Periphery power for RAM interface 16.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF16_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF16_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF16_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF17_PPD_MASK (0x20000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF17_PPD_SHIFT (17U)
+/*! SRAM_IF17_PPD - Periphery power for RAM interface 17.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF17_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF17_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF17_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF18_PPD_MASK (0x40000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF18_PPD_SHIFT (18U)
+/*! SRAM_IF18_PPD - Periphery power for RAM interface 18.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF18_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF18_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF18_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF19_PPD_MASK (0x80000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF19_PPD_SHIFT (19U)
+/*! SRAM_IF19_PPD - Periphery power for RAM interface 19.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF19_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF19_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF19_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF20_PPD_MASK (0x100000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF20_PPD_SHIFT (20U)
+/*! SRAM_IF20_PPD - Periphery power for RAM interface 20.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF20_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF20_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF20_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF21_PPD_MASK (0x200000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF21_PPD_SHIFT (21U)
+/*! SRAM_IF21_PPD - Periphery power for RAM interface 21.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF21_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF21_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF21_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF22_PPD_MASK (0x400000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF22_PPD_SHIFT (22U)
+/*! SRAM_IF22_PPD - Periphery power for RAM interface 22.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF22_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF22_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF22_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF23_PPD_MASK (0x800000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF23_PPD_SHIFT (23U)
+/*! SRAM_IF23_PPD - Periphery power for RAM interface 23.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF23_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF23_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF23_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF24_PPD_MASK (0x1000000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF24_PPD_SHIFT (24U)
+/*! SRAM_IF24_PPD - Periphery power for RAM interface 24.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF24_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF24_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF24_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF25_PPD_MASK (0x2000000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF25_PPD_SHIFT (25U)
+/*! SRAM_IF25_PPD - Periphery power for RAM interface 25.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF25_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF25_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF25_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF26_PPD_MASK (0x4000000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF26_PPD_SHIFT (26U)
+/*! SRAM_IF26_PPD - Periphery power for RAM interface 26.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF26_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF26_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF26_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF27_PPD_MASK (0x8000000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF27_PPD_SHIFT (27U)
+/*! SRAM_IF27_PPD - Periphery power for RAM interface 27.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF27_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF27_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF27_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF28_PPD_MASK (0x10000000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF28_PPD_SHIFT (28U)
+/*! SRAM_IF28_PPD - Periphery power for RAM interface 28.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF28_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF28_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF28_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF29_PPD_MASK (0x20000000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF29_PPD_SHIFT (29U)
+/*! SRAM_IF29_PPD - Periphery power for RAM interface 29.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF29_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF29_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF29_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF30_PPD_MASK (0x40000000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF30_PPD_SHIFT (30U)
+/*! SRAM_IF30_PPD - Periphery power for RAM interface 30.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF30_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF30_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF30_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF31_PPD_MASK (0x80000000U)
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF31_PPD_SHIFT (31U)
+/*! SRAM_IF31_PPD - Periphery power for RAM interface 31.
+ * 0b0..No effect
+ * 0b1..Sets the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF31_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF31_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF31_PPD_MASK)
+/*! @} */
+
+/*! @name PDRUNCFG0_CLR - Run configuration 0 clear */
+/*! @{ */
+#define SYSCTL0_PDRUNCFG0_CLR_MAINCLK_SHUTOFF_MASK (0x1U)
+#define SYSCTL0_PDRUNCFG0_CLR_MAINCLK_SHUTOFF_SHIFT (0U)
+/*! MAINCLK_SHUTOFF - Main clock shut off
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_MAINCLK_SHUTOFF_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_MAINCLK_SHUTOFF_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE0_MASK (0x2U)
+#define SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE0_SHIFT (1U)
+/*! PMIC_MODE0 - PMIC_MODE0 device pin
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE0_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE0_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE1_MASK (0x4U)
+#define SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE1_SHIFT (2U)
+/*! PMIC_MODE1 - PMIC_MODE1 device pin
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE1_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE1_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_DEEP_PD_MASK (0x8U)
+#define SYSCTL0_PDRUNCFG0_CLR_DEEP_PD_SHIFT (3U)
+/*! DEEP_PD - Deep power-down mode
+ * 0b0..VDDCORE supply remains on during WFI (deep_sleep mode)
+ * 0b1..VDDCORE powered-off during WFI (deep_powerdown mode)
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_DEEP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_DEEP_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_DEEP_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_VDDCOREREG_LP_MASK (0x10U)
+#define SYSCTL0_PDRUNCFG0_CLR_VDDCOREREG_LP_SHIFT (4U)
+/*! VDDCOREREG_LP - Vddcore regulator mode when using on-chip regulator
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_VDDCOREREG_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_VDDCOREREG_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_VDDCOREREG_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_PMCREF_LP_MASK (0x40U)
+#define SYSCTL0_PDRUNCFG0_CLR_PMCREF_LP_SHIFT (6U)
+/*! PMCREF_LP - Internal PMC references LP mode
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_PMCREF_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_PMCREF_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_PMCREF_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_HVD1V8_PD_MASK (0x80U)
+#define SYSCTL0_PDRUNCFG0_CLR_HVD1V8_PD_SHIFT (7U)
+/*! HVD1V8_PD - HVD
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_HVD1V8_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HVD1V8_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HVD1V8_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_PORCORE_LP_MASK (0x100U)
+#define SYSCTL0_PDRUNCFG0_CLR_PORCORE_LP_SHIFT (8U)
+/*! PORCORE_LP - LVD
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_PORCORE_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_PORCORE_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_PORCORE_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_LVDCORE_LP_MASK (0x200U)
+#define SYSCTL0_PDRUNCFG0_CLR_LVDCORE_LP_SHIFT (9U)
+/*! LVDCORE_LP - LVD
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_LVDCORE_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_LVDCORE_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_LVDCORE_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_HVDCORE_PD_MASK (0x400U)
+#define SYSCTL0_PDRUNCFG0_CLR_HVDCORE_PD_SHIFT (10U)
+/*! HVDCORE_PD - HVD
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_HVDCORE_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HVDCORE_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HVDCORE_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_RBB_PD_MASK (0x800U)
+#define SYSCTL0_PDRUNCFG0_CLR_RBB_PD_SHIFT (11U)
+/*! RBB_PD - Reverse body-bias
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_RBB_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_RBB_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_RBB_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_FBB_PD_MASK (0x1000U)
+#define SYSCTL0_PDRUNCFG0_CLR_FBB_PD_SHIFT (12U)
+/*! FBB_PD - Forward body-bias
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_FBB_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_FBB_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_FBB_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_SYSXTAL_PD_MASK (0x2000U)
+#define SYSCTL0_PDRUNCFG0_CLR_SYSXTAL_PD_SHIFT (13U)
+/*! SYSXTAL_PD - Main crystal oscillator
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_SYSXTAL_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_SYSXTAL_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_SYSXTAL_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_LPOSC_PD_MASK (0x4000U)
+#define SYSCTL0_PDRUNCFG0_CLR_LPOSC_PD_SHIFT (14U)
+/*! LPOSC_PD - 1 MHz Low-Power oscillator
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_LPOSC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_LPOSC_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_LPOSC_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_RBBSRAM_PD_MASK (0x8000U)
+#define SYSCTL0_PDRUNCFG0_CLR_RBBSRAM_PD_SHIFT (15U)
+/*! RBBSRAM_PD - Reverse body-bias SRAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_RBBSRAM_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_RBBSRAM_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_RBBSRAM_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_FFRO_PD_MASK (0x10000U)
+#define SYSCTL0_PDRUNCFG0_CLR_FFRO_PD_SHIFT (16U)
+/*! FFRO_PD - FRO 16 MHz internal oscillator
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_FFRO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_FFRO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_FFRO_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_SYSPLLLDO_PD_MASK (0x20000U)
+#define SYSCTL0_PDRUNCFG0_CLR_SYSPLLLDO_PD_SHIFT (17U)
+/*! SYSPLLLDO_PD - System PLL internal regulator
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_SYSPLLLDO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_SYSPLLLDO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_SYSPLLLDO_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_SYSPLLANA_PD_MASK (0x40000U)
+#define SYSCTL0_PDRUNCFG0_CLR_SYSPLLANA_PD_SHIFT (18U)
+/*! SYSPLLANA_PD - System PLL analog functions
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_SYSPLLANA_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_SYSPLLANA_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_SYSPLLANA_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_AUDPLLLDO_PD_MASK (0x80000U)
+#define SYSCTL0_PDRUNCFG0_CLR_AUDPLLLDO_PD_SHIFT (19U)
+/*! AUDPLLLDO_PD - Audio PLL internal regulator
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_AUDPLLLDO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_AUDPLLLDO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_AUDPLLLDO_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_AUDPLLANA_PD_MASK (0x100000U)
+#define SYSCTL0_PDRUNCFG0_CLR_AUDPLLANA_PD_SHIFT (20U)
+/*! AUDPLLANA_PD - Audio PLL analog functions
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_AUDPLLANA_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_AUDPLLANA_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_AUDPLLANA_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_ADC_PD_MASK (0x200000U)
+#define SYSCTL0_PDRUNCFG0_CLR_ADC_PD_SHIFT (21U)
+/*! ADC_PD - ADC analog functions
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_ADC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_ADC_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_ADC_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_ADC_LP_MASK (0x400000U)
+#define SYSCTL0_PDRUNCFG0_CLR_ADC_LP_SHIFT (22U)
+/*! ADC_LP - ADC low power mode
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_ADC_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_ADC_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_ADC_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_ADC_TEMPSNS_PD_MASK (0x800000U)
+#define SYSCTL0_PDRUNCFG0_CLR_ADC_TEMPSNS_PD_SHIFT (23U)
+/*! ADC_TEMPSNS_PD - ADC temperature sensor
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_ADC_TEMPSNS_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_ADC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_ADC_TEMPSNS_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_PMC_TEMPSNS_PD_MASK (0x1000000U)
+#define SYSCTL0_PDRUNCFG0_CLR_PMC_TEMPSNS_PD_SHIFT (24U)
+/*! PMC_TEMPSNS_PD - PMC temperature sensor
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_PMC_TEMPSNS_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_PMC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_PMC_TEMPSNS_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_ACMP_PD_MASK (0x2000000U)
+#define SYSCTL0_PDRUNCFG0_CLR_ACMP_PD_SHIFT (25U)
+/*! ACMP_PD - Analog comparator
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_ACMP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_ACMP_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_ACMP_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_VDET_LP_MASK (0x4000000U)
+#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_VDET_LP_SHIFT (26U)
+/*! HSPAD_FSPI0_VDET_LP - High speed pad FSPI0 voltage detect sleep mode
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_VDET_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_REF_PD_MASK (0x8000000U)
+#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_REF_PD_SHIFT (27U)
+/*! HSPAD_FSPI0_REF_PD - High speed pad FSPIO0 sleep mode
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_REF_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_HSPADVDET_LP_MASK (0x10000000U)
+#define SYSCTL0_PDRUNCFG0_CLR_HSPADVDET_LP_SHIFT (28U)
+/*! HSPADVDET_LP - High speed pad voltage detect sleep mode
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_HSPADVDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HSPADVDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HSPADVDET_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_HSPADREF_PD_MASK (0x20000000U)
+#define SYSCTL0_PDRUNCFG0_CLR_HSPADREF_PD_SHIFT (29U)
+/*! HSPADREF_PD - High speed pad sleep mode
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_HSPADREF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HSPADREF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HSPADREF_PD_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_VDET_LP_MASK (0x40000000U)
+#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_VDET_LP_SHIFT (30U)
+/*! HSPAD_FSPI1_VDET_LP - High speed pad FSPI1 voltage detect sleep mode
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_VDET_LP_MASK)
+#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_REF_PD_MASK (0x80000000U)
+#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_REF_PD_SHIFT (31U)
+/*! HSPAD_FSPI1_REF_PD - High speed pad FSPIO1 sleep mode
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG0 Bit
+ */
+#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_REF_PD_MASK)
+/*! @} */
+
+/*! @name PDRUNCFG1_CLR - Run configuration 1 clear */
+/*! @{ */
+#define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK (0x1U)
+#define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_SHIFT (0U)
+/*! PQ_SRAM_APD - Array power for PowerQuad RAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_PPD_MASK (0x2U)
+#define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_PPD_SHIFT (1U)
+/*! PQ_SRAM_PPD - Periphery power for PowerQuad RAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_MASK (0x4U)
+#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_SHIFT (2U)
+/*! FLEXSPI0_SRAM_APD - Array power for FlexSPI0
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_PPD_MASK (0x8U)
+#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_PPD_SHIFT (3U)
+/*! FLEXSPI0_SRAM_PPD - Periphery power for FlexSPI0
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_MASK (0x10U)
+#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_SHIFT (4U)
+/*! FLEXSPI1_SRAM_APD - Array power for FlexSPI1
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_PPD_MASK (0x20U)
+#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_PPD_SHIFT (5U)
+/*! FLEXSPI1_SRAM_PPD - Periphery power for FlexSPI1
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_APD_MASK (0x40U)
+#define SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_APD_SHIFT (6U)
+/*! USBHS_SRAM_APD - Array power for USB RAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_PPD_MASK (0x80U)
+#define SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_PPD_SHIFT (7U)
+/*! USBHS_SRAM_PPD - Periphery power for USB RAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_APD_MASK (0x100U)
+#define SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_APD_SHIFT (8U)
+/*! USDHC0_SRAM_APD - Array power for uSDHC0 (SD/MMC/SDIO interface) RAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_PPD_MASK (0x200U)
+#define SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_PPD_SHIFT (9U)
+/*! USDHC0_SRAM_PPD - Periphery power for uSDHC0 (SD/MMC/SDIO interface) RAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_APD_MASK (0x400U)
+#define SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_APD_SHIFT (10U)
+/*! USDHC1_SRAM_APD - Array power for uSDHC1 (SD/MMC/SDIO interface) RAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_PPD_MASK (0x800U)
+#define SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_PPD_SHIFT (11U)
+/*! USDHC1_SRAM_PPD - Periphery power for uSDHC1 (SD/MMC/SDIO interface) RAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_CASPER_SRAM_PPD_MASK (0x2000U)
+#define SYSCTL0_PDRUNCFG1_CLR_CASPER_SRAM_PPD_SHIFT (13U)
+/*! CASPER_SRAM_PPD - Periphery power for Casper RAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_CASPER_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_CASPER_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_CASPER_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_APD_MASK (0x4000U)
+#define SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_APD_SHIFT (14U)
+/*! GPU_SRAM_APD - Array power for GPU SRAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_PPD_MASK (0x8000U)
+#define SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_PPD_SHIFT (15U)
+/*! GPU_SRAM_PPD - Periphery power for GPU RAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_APD_MASK (0x10000U)
+#define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_APD_SHIFT (16U)
+/*! SMARTDMA_SRAM_APD - Array power for SMARTDMA SRAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_MASK (0x20000U)
+#define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_SHIFT (17U)
+/*! SMARTDMA_SRAM_PPD - Periphery power for SMARTDMA SRAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_APD_MASK (0x40000U)
+#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_APD_SHIFT (18U)
+/*! MIPIDSI_SRAM_APD - Array power for MIPIDSI SRAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_PPD_MASK (0x80000U)
+#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_PPD_SHIFT (19U)
+/*! MIPIDSI_SRAM_PPD - Periphery power for MIPIDSI SRAM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_APD_MASK (0x100000U)
+#define SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_APD_SHIFT (20U)
+/*! LCDIF_SRAM_APD - Array power for LCDIF
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_APD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_PPD_MASK (0x200000U)
+#define SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_PPD_SHIFT (21U)
+/*! LCDIF_SRAM_PPD - Periphery power for LCDIF
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_PPD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_DSP_PD_MASK (0x2000000U)
+#define SYSCTL0_PDRUNCFG1_CLR_DSP_PD_SHIFT (25U)
+/*! DSP_PD - Array and periphery power for DSP
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_DSP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_DSP_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_DSP_PD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_PD_MASK (0x4000000U)
+#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_PD_SHIFT (26U)
+/*! MIPIDSI_PD - Array and periphery power for MIPIDSI
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_PD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_OTP_PD_MASK (0x8000000U)
+#define SYSCTL0_PDRUNCFG1_CLR_OTP_PD_SHIFT (27U)
+/*! OTP_PD - Array and periphery power for OTP
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_OTP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_OTP_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_OTP_PD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_ROM_PD_MASK (0x10000000U)
+#define SYSCTL0_PDRUNCFG1_CLR_ROM_PD_SHIFT (28U)
+/*! ROM_PD - Array and periphery power for ROM
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_ROM_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_ROM_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_ROM_PD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_VDET_LP_MASK (0x20000000U)
+#define SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_VDET_LP_SHIFT (29U)
+/*! HSPAD_SDIO1_VDET_LP - High speed pad voltage detect sleep mode
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_VDET_LP_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_REF_PD_MASK (0x40000000U)
+#define SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_REF_PD_SHIFT (30U)
+/*! HSPAD_SDIO1_REF_PD - High speed pad sleep mode
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_REF_PD_MASK)
+#define SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK (0x80000000U)
+#define SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_SHIFT (31U)
+/*! SRAM_SLEEP - SRAM sleep mode
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG1 Bit
+ */
+#define SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK)
+/*! @} */
+
+/*! @name PDRUNCFG2_CLR - Run configuration 2 clear */
+/*! @{ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF0_APD_MASK (0x1U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF0_APD_SHIFT (0U)
+/*! SRAM_IF0_APD - Array power for RAM interface 0
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF0_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF0_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF0_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF1_APD_MASK (0x2U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF1_APD_SHIFT (1U)
+/*! SRAM_IF1_APD - Array power for RAM interface 1
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF1_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF1_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF1_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF2_APD_MASK (0x4U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF2_APD_SHIFT (2U)
+/*! SRAM_IF2_APD - Array power for RAM interface 2
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF2_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF2_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF2_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF3_APD_MASK (0x8U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF3_APD_SHIFT (3U)
+/*! SRAM_IF3_APD - Array power for RAM interface 3
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF3_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF3_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF3_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK (0x10U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_SHIFT (4U)
+/*! SRAM_IF4_APD - Array power for RAM interface 4
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF5_APD_MASK (0x20U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF5_APD_SHIFT (5U)
+/*! SRAM_IF5_APD - Array power for RAM interface 5
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF5_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF5_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF5_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF6_APD_MASK (0x40U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF6_APD_SHIFT (6U)
+/*! SRAM_IF6_APD - Array power for RAM interface 6
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF6_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF6_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF6_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF7_APD_MASK (0x80U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF7_APD_SHIFT (7U)
+/*! SRAM_IF7_APD - Array power for RAM interface 7
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF7_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF7_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF7_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF8_APD_MASK (0x100U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF8_APD_SHIFT (8U)
+/*! SRAM_IF8_APD - Array power for RAM interface 8
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF8_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF8_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF8_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF9_APD_MASK (0x200U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF9_APD_SHIFT (9U)
+/*! SRAM_IF9_APD - Array power for RAM interface 9
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF9_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF9_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF9_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF10_APD_MASK (0x400U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF10_APD_SHIFT (10U)
+/*! SRAM_IF10_APD - Array power for RAM interface 10
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF10_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF10_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF10_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF11_APD_MASK (0x800U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF11_APD_SHIFT (11U)
+/*! SRAM_IF11_APD - Array power for RAM interface 11
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF11_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF11_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF11_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF12_APD_MASK (0x1000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF12_APD_SHIFT (12U)
+/*! SRAM_IF12_APD - Array power for RAM interface 12
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF12_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF12_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF12_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF13_APD_MASK (0x2000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF13_APD_SHIFT (13U)
+/*! SRAM_IF13_APD - Array power for RAM interface 13
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF13_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF13_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF13_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF14_APD_MASK (0x4000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF14_APD_SHIFT (14U)
+/*! SRAM_IF14_APD - Array power for RAM interface 14
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF14_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF14_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF14_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF15_APD_MASK (0x8000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF15_APD_SHIFT (15U)
+/*! SRAM_IF15_APD - Array power for RAM interface 15
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF15_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF15_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF15_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF16_APD_MASK (0x10000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF16_APD_SHIFT (16U)
+/*! SRAM_IF16_APD - Array power for RAM interface 16
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF16_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF16_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF16_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF17_APD_MASK (0x20000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF17_APD_SHIFT (17U)
+/*! SRAM_IF17_APD - Array power for RAM interface 17
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF17_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF17_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF17_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF18_APD_MASK (0x40000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF18_APD_SHIFT (18U)
+/*! SRAM_IF18_APD - Array power for RAM interface 18
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF18_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF18_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF18_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF19_APD_MASK (0x80000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF19_APD_SHIFT (19U)
+/*! SRAM_IF19_APD - Array power for RAM interface 19
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF19_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF19_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF19_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF20_APD_MASK (0x100000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF20_APD_SHIFT (20U)
+/*! SRAM_IF20_APD - Array power for RAM interface 20
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF20_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF20_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF20_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF21_APD_MASK (0x200000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF21_APD_SHIFT (21U)
+/*! SRAM_IF21_APD - Array power for RAM interface 21
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF21_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF21_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF21_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF22_APD_MASK (0x400000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF22_APD_SHIFT (22U)
+/*! SRAM_IF22_APD - Array power for RAM interface 22
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF22_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF22_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF22_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF23_APD_MASK (0x800000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF23_APD_SHIFT (23U)
+/*! SRAM_IF23_APD - Array power for RAM interface 23
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF23_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF23_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF23_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF24_APD_MASK (0x1000000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF24_APD_SHIFT (24U)
+/*! SRAM_IF24_APD - Array power for RAM interface 24
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF24_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF24_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF24_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF25_APD_MASK (0x2000000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF25_APD_SHIFT (25U)
+/*! SRAM_IF25_APD - Array power for RAM interface 25
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF25_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF25_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF25_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF26_APD_MASK (0x4000000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF26_APD_SHIFT (26U)
+/*! SRAM_IF26_APD - Array power for RAM interface 26
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF26_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF26_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF26_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF27_APD_MASK (0x8000000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF27_APD_SHIFT (27U)
+/*! SRAM_IF27_APD - Array power for RAM interface 27
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF27_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF27_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF27_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF28_APD_MASK (0x10000000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF28_APD_SHIFT (28U)
+/*! SRAM_IF28_APD - Array power for RAM interface 28
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF28_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF28_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF28_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF29_APD_MASK (0x20000000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF29_APD_SHIFT (29U)
+/*! SRAM_IF29_APD - Array power for RAM interface 29
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF29_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF29_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF29_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF30_APD_MASK (0x40000000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF30_APD_SHIFT (30U)
+/*! SRAM_IF30_APD - Array power for RAM interface 30
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF30_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF30_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF30_APD_MASK)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF31_APD_MASK (0x80000000U)
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF31_APD_SHIFT (31U)
+/*! SRAM_IF31_APD - Array power for RAM interface 31
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG2 Bit
+ */
+#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF31_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF31_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF31_APD_MASK)
+/*! @} */
+
+/*! @name PDRUNCFG3_CLR - Run configuration 3 clear */
+/*! @{ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF0_PPD_MASK (0x1U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF0_PPD_SHIFT (0U)
+/*! SRAM_IF0_PPD - Periphery power for RAM interface 0
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF0_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF0_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF0_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF1_PPD_MASK (0x2U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF1_PPD_SHIFT (1U)
+/*! SRAM_IF1_PPD - Periphery power for RAM interface 1
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF1_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF1_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF1_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF2_PPD_MASK (0x4U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF2_PPD_SHIFT (2U)
+/*! SRAM_IF2_PPD - Periphery power for RAM interface 2
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF2_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF2_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF2_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF3_PPD_MASK (0x8U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF3_PPD_SHIFT (3U)
+/*! SRAM_IF3_PPD - Periphery power for RAM interface 3
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF3_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF3_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF3_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF4_PPD_MASK (0x10U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF4_PPD_SHIFT (4U)
+/*! SRAM_IF4_PPD - Periphery power for RAM interface 4
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF4_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF4_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF4_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF5_PPD_MASK (0x20U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF5_PPD_SHIFT (5U)
+/*! SRAM_IF5_PPD - Periphery power for RAM interface 5
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF5_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF5_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF5_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF6_PPD_MASK (0x40U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF6_PPD_SHIFT (6U)
+/*! SRAM_IF6_PPD - Periphery power for RAM interface 6
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF6_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF6_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF6_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF7_PPD_MASK (0x80U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF7_PPD_SHIFT (7U)
+/*! SRAM_IF7_PPD - Periphery power for RAM interface 7
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF7_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF7_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF7_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF8_PPD_MASK (0x100U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF8_PPD_SHIFT (8U)
+/*! SRAM_IF8_PPD - Periphery power for RAM interface 8
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF8_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF8_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF8_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF9_PPD_MASK (0x200U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF9_PPD_SHIFT (9U)
+/*! SRAM_IF9_PPD - Periphery power for RAM interface 9
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF9_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF9_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF9_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF10_PPD_MASK (0x400U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF10_PPD_SHIFT (10U)
+/*! SRAM_IF10_PPD - Periphery power for RAM interface 10
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF10_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF10_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF10_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF11_PPD_MASK (0x800U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF11_PPD_SHIFT (11U)
+/*! SRAM_IF11_PPD - Periphery power for RAM interface 11
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF11_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF11_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF11_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF12_PPD_MASK (0x1000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF12_PPD_SHIFT (12U)
+/*! SRAM_IF12_PPD - Periphery power for RAM interface 12
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF12_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF12_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF12_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF13_PPD_MASK (0x2000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF13_PPD_SHIFT (13U)
+/*! SRAM_IF13_PPD - Periphery power for RAM interface 13
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF13_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF13_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF13_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF14_PPD_MASK (0x4000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF14_PPD_SHIFT (14U)
+/*! SRAM_IF14_PPD - Periphery power for RAM interface 14
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF14_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF14_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF14_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF15_PPD_MASK (0x8000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF15_PPD_SHIFT (15U)
+/*! SRAM_IF15_PPD - Periphery power for RAM interface 15
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF15_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF15_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF15_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF16_PPD_MASK (0x10000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF16_PPD_SHIFT (16U)
+/*! SRAM_IF16_PPD - Periphery power for RAM interface 16
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF16_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF16_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF16_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF17_PPD_MASK (0x20000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF17_PPD_SHIFT (17U)
+/*! SRAM_IF17_PPD - Periphery power for RAM interface 17
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF17_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF17_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF17_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF18_PPD_MASK (0x40000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF18_PPD_SHIFT (18U)
+/*! SRAM_IF18_PPD - Periphery power for RAM interface 18
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF18_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF18_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF18_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF19_PPD_MASK (0x80000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF19_PPD_SHIFT (19U)
+/*! SRAM_IF19_PPD - Periphery power for RAM interface 19
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF19_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF19_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF19_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF20_PPD_MASK (0x100000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF20_PPD_SHIFT (20U)
+/*! SRAM_IF20_PPD - Periphery power for RAM interface 20
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF20_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF20_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF20_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF21_PPD_MASK (0x200000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF21_PPD_SHIFT (21U)
+/*! SRAM_IF21_PPD - Periphery power for RAM interface 21
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF21_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF21_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF21_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF22_PPD_MASK (0x400000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF22_PPD_SHIFT (22U)
+/*! SRAM_IF22_PPD - Periphery power for RAM interface 22
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF22_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF22_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF22_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF23_PPD_MASK (0x800000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF23_PPD_SHIFT (23U)
+/*! SRAM_IF23_PPD - Periphery power for RAM interface 23
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF23_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF23_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF23_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF24_PPD_MASK (0x1000000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF24_PPD_SHIFT (24U)
+/*! SRAM_IF24_PPD - Periphery power for RAM interface 24
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF24_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF24_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF24_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF25_PPD_MASK (0x2000000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF25_PPD_SHIFT (25U)
+/*! SRAM_IF25_PPD - Periphery power for RAM interface 25
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF25_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF25_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF25_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF26_PPD_MASK (0x4000000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF26_PPD_SHIFT (26U)
+/*! SRAM_IF26_PPD - Periphery power for RAM interface 26
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF26_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF26_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF26_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF27_PPD_MASK (0x8000000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF27_PPD_SHIFT (27U)
+/*! SRAM_IF27_PPD - Periphery power for RAM interface 27
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF27_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF27_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF27_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF28_PPD_MASK (0x10000000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF28_PPD_SHIFT (28U)
+/*! SRAM_IF28_PPD - Periphery power for RAM interface 28
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF28_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF28_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF28_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF29_PPD_MASK (0x20000000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF29_PPD_SHIFT (29U)
+/*! SRAM_IF29_PPD - Periphery power for RAM interface 29
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF29_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF29_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF29_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF30_PPD_MASK (0x40000000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF30_PPD_SHIFT (30U)
+/*! SRAM_IF30_PPD - Periphery power for RAM interface 30
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF30_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF30_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF30_PPD_MASK)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF31_PPD_MASK (0x80000000U)
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF31_PPD_SHIFT (31U)
+/*! SRAM_IF31_PPD - Periphery power for RAM interface 31
+ * 0b0..No effect
+ * 0b1..Clears the PDRUNCFG3 Bit
+ */
+#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF31_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF31_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF31_PPD_MASK)
+/*! @} */
+
+/*! @name PDWAKECFG - PD Wake Configuration */
+/*! @{ */
+#define SYSCTL0_PDWAKECFG_RBBKEEPST_MASK (0x1U)
+#define SYSCTL0_PDWAKECFG_RBBKEEPST_SHIFT (0U)
+/*! RBBKEEPST - RBB mode on wakeup
+ * 0b0..Use value of RBB_PD in PDRUNCFG on wakeup.
+ * 0b1..Copy PDSLEEPCFG RBB_PD value to PDRUNCFG RBB_PD on wakeup to keep RBB state.
+ */
+#define SYSCTL0_PDWAKECFG_RBBKEEPST(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDWAKECFG_RBBKEEPST_SHIFT)) & SYSCTL0_PDWAKECFG_RBBKEEPST_MASK)
+#define SYSCTL0_PDWAKECFG_FBBKEEPST_MASK (0x2U)
+#define SYSCTL0_PDWAKECFG_FBBKEEPST_SHIFT (1U)
+/*! FBBKEEPST - FBB mode on wakeup
+ * 0b0..Use value of FBB_PD in PDRUNCFG on wakeup
+ * 0b1..Copy PDSLEEPCFG FBB_PD value to PDRUNCFG FBB_PD on wakeup to keep FBB state
+ */
+#define SYSCTL0_PDWAKECFG_FBBKEEPST(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDWAKECFG_FBBKEEPST_SHIFT)) & SYSCTL0_PDWAKECFG_FBBKEEPST_MASK)
+#define SYSCTL0_PDWAKECFG_RBBSRAMKEEPST_MASK (0x4U)
+#define SYSCTL0_PDWAKECFG_RBBSRAMKEEPST_SHIFT (2U)
+/*! RBBSRAMKEEPST - RBB SRAM mode on wakeup
+ * 0b0..Use value of RBBSRAM_PD in PDRUNCFG on wakeup
+ * 0b1..Copy PDSLEEPCFG RBBSRAM_PD value to PDRUNCFG RBBSRAM_PD on wakeupto keep RBB state
+ */
+#define SYSCTL0_PDWAKECFG_RBBSRAMKEEPST(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDWAKECFG_RBBSRAMKEEPST_SHIFT)) & SYSCTL0_PDWAKECFG_RBBSRAMKEEPST_MASK)
+#define SYSCTL0_PDWAKECFG_MIPIPDKEEPST_MASK (0x8U)
+#define SYSCTL0_PDWAKECFG_MIPIPDKEEPST_SHIFT (3U)
+/*! MIPIPDKEEPST - MIPI_PD value on wakeup
+ * 0b0..Use value of MIPI_PD in PDRUNCFG on wakeup
+ * 0b1..Copy PDSLEEPCFG MIPI_PD value to PDRUNCFG MIPI_PD on wakeupto keep MIPI state
+ */
+#define SYSCTL0_PDWAKECFG_MIPIPDKEEPST(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDWAKECFG_MIPIPDKEEPST_SHIFT)) & SYSCTL0_PDWAKECFG_MIPIPDKEEPST_MASK)
+#define SYSCTL0_PDWAKECFG_DSPPDKEEPST_MASK (0x10U)
+#define SYSCTL0_PDWAKECFG_DSPPDKEEPST_SHIFT (4U)
+/*! DSPPDKEEPST - DSP_PD value on wakeup
+ * 0b0..Use value of DSP_PD in PDRUNCFG on wakeup
+ * 0b1..Copy PDSLEEPCFG DSP_PD value to PDRUNCFG DSP_PD on wakeupto keep DSP state
+ */
+#define SYSCTL0_PDWAKECFG_DSPPDKEEPST(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDWAKECFG_DSPPDKEEPST_SHIFT)) & SYSCTL0_PDWAKECFG_DSPPDKEEPST_MASK)
+#define SYSCTL0_PDWAKECFG_OTPPDKEEPST_MASK (0x20U)
+#define SYSCTL0_PDWAKECFG_OTPPDKEEPST_SHIFT (5U)
+/*! OTPPDKEEPST - OTP_PD value on wakeup
+ * 0b0..Use value of OTP_PD in PDRUNCFG on wakeup
+ * 0b1..Copy PDSLEEPCFG OTP_PD value to PDRUNCFG OTP_PD on wakeupto keep OTP state
+ */
+#define SYSCTL0_PDWAKECFG_OTPPDKEEPST(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDWAKECFG_OTPPDKEEPST_SHIFT)) & SYSCTL0_PDWAKECFG_OTPPDKEEPST_MASK)
+/*! @} */
+
+/*! @name STARTEN0 - Start Enable 0 */
+/*! @{ */
+#define SYSCTL0_STARTEN0_WDT0_MASK (0x1U)
+#define SYSCTL0_STARTEN0_WDT0_SHIFT (0U)
+/*! WDT0 - Watchdog timer 0 wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_WDT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_WDT0_SHIFT)) & SYSCTL0_STARTEN0_WDT0_MASK)
+#define SYSCTL0_STARTEN0_DMAC0_MASK (0x2U)
+#define SYSCTL0_STARTEN0_DMAC0_SHIFT (1U)
+/*! DMAC0 - DMA controller 0 wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_DMAC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_DMAC0_SHIFT)) & SYSCTL0_STARTEN0_DMAC0_MASK)
+#define SYSCTL0_STARTEN0_GPIO_INTA_MASK (0x4U)
+#define SYSCTL0_STARTEN0_GPIO_INTA_SHIFT (2U)
+/*! GPIO_INTA - Non-secure GPIO interrupt A wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_GPIO_INTA(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_GPIO_INTA_SHIFT)) & SYSCTL0_STARTEN0_GPIO_INTA_MASK)
+#define SYSCTL0_STARTEN0_GPIO_INTB_MASK (0x8U)
+#define SYSCTL0_STARTEN0_GPIO_INTB_SHIFT (3U)
+/*! GPIO_INTB - Non-secure GPIO interrupt B wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_GPIO_INTB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_GPIO_INTB_SHIFT)) & SYSCTL0_STARTEN0_GPIO_INTB_MASK)
+#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ0_MASK (0x10U)
+#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ0_SHIFT (4U)
+/*! GPIO_INT0_IRQ0 - GPIO pin interrupt 0 wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_GPIO_INT0_IRQ0_SHIFT)) & SYSCTL0_STARTEN0_GPIO_INT0_IRQ0_MASK)
+#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ1_MASK (0x20U)
+#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ1_SHIFT (5U)
+/*! GPIO_INT0_IRQ1 - GPIO pin interrupt 1 wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_GPIO_INT0_IRQ1_SHIFT)) & SYSCTL0_STARTEN0_GPIO_INT0_IRQ1_MASK)
+#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ2_MASK (0x40U)
+#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ2_SHIFT (6U)
+/*! GPIO_INT0_IRQ2 - GPIO pin interrupt 2 wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_GPIO_INT0_IRQ2_SHIFT)) & SYSCTL0_STARTEN0_GPIO_INT0_IRQ2_MASK)
+#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ3_MASK (0x80U)
+#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ3_SHIFT (7U)
+/*! GPIO_INT0_IRQ3 - GPIO pin interrupt 3 wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_GPIO_INT0_IRQ3_SHIFT)) & SYSCTL0_STARTEN0_GPIO_INT0_IRQ3_MASK)
+#define SYSCTL0_STARTEN0_UTICK0_MASK (0x100U)
+#define SYSCTL0_STARTEN0_UTICK0_SHIFT (8U)
+/*! UTICK0 - UTICK wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_UTICK0_SHIFT)) & SYSCTL0_STARTEN0_UTICK0_MASK)
+#define SYSCTL0_STARTEN0_MRT0_MASK (0x200U)
+#define SYSCTL0_STARTEN0_MRT0_SHIFT (9U)
+/*! MRT0 - MRT wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_MRT0_SHIFT)) & SYSCTL0_STARTEN0_MRT0_MASK)
+#define SYSCTL0_STARTEN0_CT32BIT0_MASK (0x400U)
+#define SYSCTL0_STARTEN0_CT32BIT0_SHIFT (10U)
+/*! CT32BIT0 - CTIMER 0 wake-up
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_CT32BIT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CT32BIT0_SHIFT)) & SYSCTL0_STARTEN0_CT32BIT0_MASK)
+#define SYSCTL0_STARTEN0_CT32BIT1_MASK (0x800U)
+#define SYSCTL0_STARTEN0_CT32BIT1_SHIFT (11U)
+/*! CT32BIT1 - CTIMER 1 wake-up
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_CT32BIT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CT32BIT1_SHIFT)) & SYSCTL0_STARTEN0_CT32BIT1_MASK)
+#define SYSCTL0_STARTEN0_SCT0_MASK (0x1000U)
+#define SYSCTL0_STARTEN0_SCT0_SHIFT (12U)
+/*! SCT0 - SCTimer/PWM wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SCT0_SHIFT)) & SYSCTL0_STARTEN0_SCT0_MASK)
+#define SYSCTL0_STARTEN0_CT32BIT3_MASK (0x2000U)
+#define SYSCTL0_STARTEN0_CT32BIT3_SHIFT (13U)
+/*! CT32BIT3 - CTIMER 3 wake-up
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_CT32BIT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CT32BIT3_SHIFT)) & SYSCTL0_STARTEN0_CT32BIT3_MASK)
+#define SYSCTL0_STARTEN0_FLEXCOMM0_MASK (0x4000U)
+#define SYSCTL0_STARTEN0_FLEXCOMM0_SHIFT (14U)
+/*! FLEXCOMM0 - Flexcomm 0 peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM0_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM0_MASK)
+#define SYSCTL0_STARTEN0_FLEXCOMM1_MASK (0x8000U)
+#define SYSCTL0_STARTEN0_FLEXCOMM1_SHIFT (15U)
+/*! FLEXCOMM1 - Flexcomm 1 peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM1_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM1_MASK)
+#define SYSCTL0_STARTEN0_FLEXCOMM2_MASK (0x10000U)
+#define SYSCTL0_STARTEN0_FLEXCOMM2_SHIFT (16U)
+/*! FLEXCOMM2 - Flexcomm 2 peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM2_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM2_MASK)
+#define SYSCTL0_STARTEN0_FLEXCOMM3_MASK (0x20000U)
+#define SYSCTL0_STARTEN0_FLEXCOMM3_SHIFT (17U)
+/*! FLEXCOMM3 - Flexcomm 3 peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM3_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM3_MASK)
+#define SYSCTL0_STARTEN0_FLEXCOMM4_MASK (0x40000U)
+#define SYSCTL0_STARTEN0_FLEXCOMM4_SHIFT (18U)
+/*! FLEXCOMM4 - Flexcomm 4 peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM4_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM4_MASK)
+#define SYSCTL0_STARTEN0_FLEXCOMM5_MASK (0x80000U)
+#define SYSCTL0_STARTEN0_FLEXCOMM5_SHIFT (19U)
+/*! FLEXCOMM5 - Flexcomm 5 peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM5_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM5_MASK)
+#define SYSCTL0_STARTEN0_FLEXCOMM14_MASK (0x100000U)
+#define SYSCTL0_STARTEN0_FLEXCOMM14_SHIFT (20U)
+/*! FLEXCOMM14 - Flexcomm 14 (High Speed SPI) peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_FLEXCOMM14(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM14_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM14_MASK)
+#define SYSCTL0_STARTEN0_FLEXCOMM15_MASK (0x200000U)
+#define SYSCTL0_STARTEN0_FLEXCOMM15_SHIFT (21U)
+/*! FLEXCOMM15 - Flexcomm 15 (PMIC I2C) peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_FLEXCOMM15(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM15_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM15_MASK)
+#define SYSCTL0_STARTEN0_ADC0_MASK (0x400000U)
+#define SYSCTL0_STARTEN0_ADC0_SHIFT (22U)
+/*! ADC0 - ADC wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_ADC0_SHIFT)) & SYSCTL0_STARTEN0_ADC0_MASK)
+#define SYSCTL0_STARTEN0_ACMP_MASK (0x1000000U)
+#define SYSCTL0_STARTEN0_ACMP_SHIFT (24U)
+/*! ACMP - ACMP wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_ACMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_ACMP_SHIFT)) & SYSCTL0_STARTEN0_ACMP_MASK)
+#define SYSCTL0_STARTEN0_DMIC0_MASK (0x2000000U)
+#define SYSCTL0_STARTEN0_DMIC0_SHIFT (25U)
+/*! DMIC0 - DMIC wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_DMIC0_SHIFT)) & SYSCTL0_STARTEN0_DMIC0_MASK)
+#define SYSCTL0_STARTEN0_HYPERVISOR_MASK (0x8000000U)
+#define SYSCTL0_STARTEN0_HYPERVISOR_SHIFT (27U)
+/*! HYPERVISOR - Hypervisor interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_HYPERVISOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_HYPERVISOR_SHIFT)) & SYSCTL0_STARTEN0_HYPERVISOR_MASK)
+#define SYSCTL0_STARTEN0_SECUREVIOLATION_MASK (0x10000000U)
+#define SYSCTL0_STARTEN0_SECUREVIOLATION_SHIFT (28U)
+/*! SECUREVIOLATION - Secure Violation wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_SECUREVIOLATION(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SECUREVIOLATION_SHIFT)) & SYSCTL0_STARTEN0_SECUREVIOLATION_MASK)
+#define SYSCTL0_STARTEN0_HWVAD0_MASK (0x20000000U)
+#define SYSCTL0_STARTEN0_HWVAD0_SHIFT (29U)
+/*! HWVAD0 - Hardware VAD wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_HWVAD0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_HWVAD0_SHIFT)) & SYSCTL0_STARTEN0_HWVAD0_MASK)
+#define SYSCTL0_STARTEN0_PMC_MASK (0x40000000U)
+#define SYSCTL0_STARTEN0_PMC_SHIFT (30U)
+/*! PMC - PMC wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_PMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_PMC_SHIFT)) & SYSCTL0_STARTEN0_PMC_MASK)
+#define SYSCTL0_STARTEN0_RNG_MASK (0x80000000U)
+#define SYSCTL0_STARTEN0_RNG_SHIFT (31U)
+/*! RNG - RNG wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN0_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_RNG_SHIFT)) & SYSCTL0_STARTEN0_RNG_MASK)
+/*! @} */
+
+/*! @name STARTEN1 - Start Enable 1 */
+/*! @{ */
+#define SYSCTL0_STARTEN1_RTC_LITE0_WAKEUP_MASK (0x1U)
+#define SYSCTL0_STARTEN1_RTC_LITE0_WAKEUP_SHIFT (0U)
+/*! RTC_LITE0_WAKEUP - RTC wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_RTC_LITE0_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_RTC_LITE0_WAKEUP_SHIFT)) & SYSCTL0_STARTEN1_RTC_LITE0_WAKEUP_MASK)
+#define SYSCTL0_STARTEN1_DSP_TIE_EXPSTATE1_MASK (0x2U)
+#define SYSCTL0_STARTEN1_DSP_TIE_EXPSTATE1_SHIFT (1U)
+/*! DSP_TIE_EXPSTATE1 - DSP wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding STARTEN1 bit
+ */
+#define SYSCTL0_STARTEN1_DSP_TIE_EXPSTATE1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_DSP_TIE_EXPSTATE1_SHIFT)) & SYSCTL0_STARTEN1_DSP_TIE_EXPSTATE1_MASK)
+#define SYSCTL0_STARTEN1_MU_MASK (0x4U)
+#define SYSCTL0_STARTEN1_MU_SHIFT (2U)
+/*! MU - Message Unit wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_MU(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_MU_SHIFT)) & SYSCTL0_STARTEN1_MU_MASK)
+#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ4_MASK (0x8U)
+#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ4_SHIFT (3U)
+/*! GPIO_INT0_IRQ4 - GPIO pin interrupt 4 wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_GPIO_INT0_IRQ4_SHIFT)) & SYSCTL0_STARTEN1_GPIO_INT0_IRQ4_MASK)
+#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ5_MASK (0x10U)
+#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ5_SHIFT (4U)
+/*! GPIO_INT0_IRQ5 - GPIO pin interrupt 5 wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_GPIO_INT0_IRQ5_SHIFT)) & SYSCTL0_STARTEN1_GPIO_INT0_IRQ5_MASK)
+#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ6_MASK (0x20U)
+#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ6_SHIFT (5U)
+/*! GPIO_INT0_IRQ6 - GPIO pin interrupt 6 wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_GPIO_INT0_IRQ6_SHIFT)) & SYSCTL0_STARTEN1_GPIO_INT0_IRQ6_MASK)
+#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ7_MASK (0x40U)
+#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ7_SHIFT (6U)
+/*! GPIO_INT0_IRQ7 - GPIO pin interrupt 7 wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_GPIO_INT0_IRQ7_SHIFT)) & SYSCTL0_STARTEN1_GPIO_INT0_IRQ7_MASK)
+#define SYSCTL0_STARTEN1_CT32BIT2_MASK (0x80U)
+#define SYSCTL0_STARTEN1_CT32BIT2_SHIFT (7U)
+/*! CT32BIT2 - CTIMER 2 wake-up
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_CT32BIT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CT32BIT2_SHIFT)) & SYSCTL0_STARTEN1_CT32BIT2_MASK)
+#define SYSCTL0_STARTEN1_CT32BIT4_MASK (0x100U)
+#define SYSCTL0_STARTEN1_CT32BIT4_SHIFT (8U)
+/*! CT32BIT4 - CTIMER 4 wake-up
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_CT32BIT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CT32BIT4_SHIFT)) & SYSCTL0_STARTEN1_CT32BIT4_MASK)
+#define SYSCTL0_STARTEN1_OS_EVENT_TIMER_WU_MASK (0x200U)
+#define SYSCTL0_STARTEN1_OS_EVENT_TIMER_WU_SHIFT (9U)
+/*! OS_EVENT_TIMER_WU - OS Event Timer wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_OS_EVENT_TIMER_WU(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_OS_EVENT_TIMER_WU_SHIFT)) & SYSCTL0_STARTEN1_OS_EVENT_TIMER_WU_MASK)
+#define SYSCTL0_STARTEN1_FLEXSPI_MASK (0x400U)
+#define SYSCTL0_STARTEN1_FLEXSPI_SHIFT (10U)
+/*! FLEXSPI - Quad/octal SPI wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_FLEXSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_FLEXSPI_SHIFT)) & SYSCTL0_STARTEN1_FLEXSPI_MASK)
+#define SYSCTL0_STARTEN1_FLEXCOMM6_MASK (0x800U)
+#define SYSCTL0_STARTEN1_FLEXCOMM6_SHIFT (11U)
+/*! FLEXCOMM6 - FLEXCOMM 6 peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_FLEXCOMM6_SHIFT)) & SYSCTL0_STARTEN1_FLEXCOMM6_MASK)
+#define SYSCTL0_STARTEN1_FLEXCOMM7_MASK (0x1000U)
+#define SYSCTL0_STARTEN1_FLEXCOMM7_SHIFT (12U)
+/*! FLEXCOMM7 - FLEXCOMM 7 peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_FLEXCOMM7_SHIFT)) & SYSCTL0_STARTEN1_FLEXCOMM7_MASK)
+#define SYSCTL0_STARTEN1_SDIO0_MASK (0x2000U)
+#define SYSCTL0_STARTEN1_SDIO0_SHIFT (13U)
+/*! SDIO0 - SDIO0 wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_SDIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SDIO0_SHIFT)) & SYSCTL0_STARTEN1_SDIO0_MASK)
+#define SYSCTL0_STARTEN1_SDIO1_MASK (0x4000U)
+#define SYSCTL0_STARTEN1_SDIO1_SHIFT (14U)
+/*! SDIO1 - SDIO0 wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_SDIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SDIO1_SHIFT)) & SYSCTL0_STARTEN1_SDIO1_MASK)
+#define SYSCTL0_STARTEN1_SGPIO_INTA_MASK (0x8000U)
+#define SYSCTL0_STARTEN1_SGPIO_INTA_SHIFT (15U)
+/*! SGPIO_INTA - Secure GPIO interrupt A wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_SGPIO_INTA(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SGPIO_INTA_SHIFT)) & SYSCTL0_STARTEN1_SGPIO_INTA_MASK)
+#define SYSCTL0_STARTEN1_SGPIO_INTB_MASK (0x10000U)
+#define SYSCTL0_STARTEN1_SGPIO_INTB_SHIFT (16U)
+/*! SGPIO_INTB - Secure GPIO interrupt B wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_SGPIO_INTB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SGPIO_INTB_SHIFT)) & SYSCTL0_STARTEN1_SGPIO_INTB_MASK)
+#define SYSCTL0_STARTEN1_USB0_NEEDCLK_MASK (0x80000U)
+#define SYSCTL0_STARTEN1_USB0_NEEDCLK_SHIFT (19U)
+/*! USB0_NEEDCLK - USB activity wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_USB0_NEEDCLK_SHIFT)) & SYSCTL0_STARTEN1_USB0_NEEDCLK_MASK)
+#define SYSCTL0_STARTEN1_USB_PHYDCD_MASK (0x200000U)
+#define SYSCTL0_STARTEN1_USB_PHYDCD_SHIFT (21U)
+/*! USB_PHYDCD - USB PHY DCD interrupt wake-up
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_USB_PHYDCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_USB_PHYDCD_SHIFT)) & SYSCTL0_STARTEN1_USB_PHYDCD_MASK)
+#define SYSCTL0_STARTEN1_DMAC1_MASK (0x400000U)
+#define SYSCTL0_STARTEN1_DMAC1_SHIFT (22U)
+/*! DMAC1 - DMA controller 1 wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_DMAC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_DMAC1_SHIFT)) & SYSCTL0_STARTEN1_DMAC1_MASK)
+#define SYSCTL0_STARTEN1_PUF_MASK (0x800000U)
+#define SYSCTL0_STARTEN1_PUF_SHIFT (23U)
+/*! PUF - PUF wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_PUF_SHIFT)) & SYSCTL0_STARTEN1_PUF_MASK)
+#define SYSCTL0_STARTEN1_POWERQUAD_MASK (0x1000000U)
+#define SYSCTL0_STARTEN1_POWERQUAD_SHIFT (24U)
+/*! POWERQUAD - POWERQUAD co-processor wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_POWERQUAD_SHIFT)) & SYSCTL0_STARTEN1_POWERQUAD_MASK)
+#define SYSCTL0_STARTEN1_CASPER_MASK (0x2000000U)
+#define SYSCTL0_STARTEN1_CASPER_SHIFT (25U)
+/*! CASPER - CASPER co-processor wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CASPER_SHIFT)) & SYSCTL0_STARTEN1_CASPER_MASK)
+#define SYSCTL0_STARTEN1_PMIC_MASK (0x4000000U)
+#define SYSCTL0_STARTEN1_PMIC_SHIFT (26U)
+/*! PMIC - Wake-up from on-chip PMC or off-chip PMIC.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_PMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_PMIC_SHIFT)) & SYSCTL0_STARTEN1_PMIC_MASK)
+#define SYSCTL0_STARTEN1_SHA_MASK (0x8000000U)
+#define SYSCTL0_STARTEN1_SHA_SHIFT (27U)
+/*! SHA - Hash-AES wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SHA_SHIFT)) & SYSCTL0_STARTEN1_SHA_MASK)
+#define SYSCTL0_STARTEN1_FLEXCOMM8_MASK (0x10000000U)
+#define SYSCTL0_STARTEN1_FLEXCOMM8_SHIFT (28U)
+/*! FLEXCOMM8 - FLEXCOMM 8 peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_FLEXCOMM8_SHIFT)) & SYSCTL0_STARTEN1_FLEXCOMM8_MASK)
+#define SYSCTL0_STARTEN1_FLEXCOMM9_MASK (0x20000000U)
+#define SYSCTL0_STARTEN1_FLEXCOMM9_SHIFT (29U)
+/*! FLEXCOMM9 - FLEXCOMM 9 peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_FLEXCOMM9_SHIFT)) & SYSCTL0_STARTEN1_FLEXCOMM9_MASK)
+#define SYSCTL0_STARTEN1_FLEXCOMM10_MASK (0x40000000U)
+#define SYSCTL0_STARTEN1_FLEXCOMM10_SHIFT (30U)
+/*! FLEXCOMM10 - FLEXCOMM 10 peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_FLEXCOMM10_SHIFT)) & SYSCTL0_STARTEN1_FLEXCOMM10_MASK)
+#define SYSCTL0_STARTEN1_FLEXCOMM11_MASK (0x80000000U)
+#define SYSCTL0_STARTEN1_FLEXCOMM11_SHIFT (31U)
+/*! FLEXCOMM11 - FLEXCOMM 11 peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_FLEXCOMM11(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_FLEXCOMM11_SHIFT)) & SYSCTL0_STARTEN1_FLEXCOMM11_MASK)
+/*! @} */
+
+/*! @name STARTEN2 - Start Enable 2 */
+/*! @{ */
+#define SYSCTL0_STARTEN2_FLEXCOMM12_MASK (0x1U)
+#define SYSCTL0_STARTEN2_FLEXCOMM12_SHIFT (0U)
+/*! FLEXCOMM12 - FlexComm 12 peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN2_FLEXCOMM12(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN2_FLEXCOMM12_SHIFT)) & SYSCTL0_STARTEN2_FLEXCOMM12_MASK)
+#define SYSCTL0_STARTEN2_FLEXCOMM13_MASK (0x2U)
+#define SYSCTL0_STARTEN2_FLEXCOMM13_SHIFT (1U)
+/*! FLEXCOMM13 - FlexComm 13 peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN2_FLEXCOMM13(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN2_FLEXCOMM13_SHIFT)) & SYSCTL0_STARTEN2_FLEXCOMM13_MASK)
+#define SYSCTL0_STARTEN2_FLEXCOMM16_MASK (0x4U)
+#define SYSCTL0_STARTEN2_FLEXCOMM16_SHIFT (2U)
+/*! FLEXCOMM16 - FlexComm 16 peripheral interrupt wake-up.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN2_FLEXCOMM16(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN2_FLEXCOMM16_SHIFT)) & SYSCTL0_STARTEN2_FLEXCOMM16_MASK)
+/*! @} */
+
+/*! @name STARTEN0_SET - Start Enable 0 Set */
+/*! @{ */
+#define SYSCTL0_STARTEN0_SET_WDT0_MASK (0x1U)
+#define SYSCTL0_STARTEN0_SET_WDT0_SHIFT (0U)
+/*! WDT0 - Watchdog timer 0 wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_WDT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_WDT0_SHIFT)) & SYSCTL0_STARTEN0_SET_WDT0_MASK)
+#define SYSCTL0_STARTEN0_SET_DMAC0_MASK (0x2U)
+#define SYSCTL0_STARTEN0_SET_DMAC0_SHIFT (1U)
+/*! DMAC0 - DMA controller 0 wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_DMAC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_DMAC0_SHIFT)) & SYSCTL0_STARTEN0_SET_DMAC0_MASK)
+#define SYSCTL0_STARTEN0_SET_GPIO_INTA_MASK (0x4U)
+#define SYSCTL0_STARTEN0_SET_GPIO_INTA_SHIFT (2U)
+/*! GPIO_INTA - Non-secure GPIO interrupt A wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_GPIO_INTA(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_GPIO_INTA_SHIFT)) & SYSCTL0_STARTEN0_SET_GPIO_INTA_MASK)
+#define SYSCTL0_STARTEN0_SET_GPIO_INTB_MASK (0x8U)
+#define SYSCTL0_STARTEN0_SET_GPIO_INTB_SHIFT (3U)
+/*! GPIO_INTB - Non-secure GPIO interrupt B wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_GPIO_INTB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_GPIO_INTB_SHIFT)) & SYSCTL0_STARTEN0_SET_GPIO_INTB_MASK)
+#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ0_MASK (0x10U)
+#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ0_SHIFT (4U)
+/*! GPIO_INT0_IRQ0 - GPIO pin interrupt 0 wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ0_SHIFT)) & SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ0_MASK)
+#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ1_MASK (0x20U)
+#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ1_SHIFT (5U)
+/*! GPIO_INT0_IRQ1 - GPIO pin interrupt 1 wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ1_SHIFT)) & SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ1_MASK)
+#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ2_MASK (0x40U)
+#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ2_SHIFT (6U)
+/*! GPIO_INT0_IRQ2 - GPIO pin interrupt 2 wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ2_SHIFT)) & SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ2_MASK)
+#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ3_MASK (0x80U)
+#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ3_SHIFT (7U)
+/*! GPIO_INT0_IRQ3 - GPIO pin interrupt 3 wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ3_SHIFT)) & SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ3_MASK)
+#define SYSCTL0_STARTEN0_SET_UTICK0_MASK (0x100U)
+#define SYSCTL0_STARTEN0_SET_UTICK0_SHIFT (8U)
+/*! UTICK0 - UTICK wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_UTICK0_SHIFT)) & SYSCTL0_STARTEN0_SET_UTICK0_MASK)
+#define SYSCTL0_STARTEN0_SET_MRT0_MASK (0x200U)
+#define SYSCTL0_STARTEN0_SET_MRT0_SHIFT (9U)
+/*! MRT0 - MRT wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_MRT0_SHIFT)) & SYSCTL0_STARTEN0_SET_MRT0_MASK)
+#define SYSCTL0_STARTEN0_SET_CT32BIT0_MASK (0x400U)
+#define SYSCTL0_STARTEN0_SET_CT32BIT0_SHIFT (10U)
+/*! CT32BIT0 - CTIMER 0 wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_CT32BIT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_CT32BIT0_SHIFT)) & SYSCTL0_STARTEN0_SET_CT32BIT0_MASK)
+#define SYSCTL0_STARTEN0_SET_CT32BIT1_MASK (0x800U)
+#define SYSCTL0_STARTEN0_SET_CT32BIT1_SHIFT (11U)
+/*! CT32BIT1 - CTIMER 1 wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_CT32BIT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_CT32BIT1_SHIFT)) & SYSCTL0_STARTEN0_SET_CT32BIT1_MASK)
+#define SYSCTL0_STARTEN0_SET_SCT0_MASK (0x1000U)
+#define SYSCTL0_STARTEN0_SET_SCT0_SHIFT (12U)
+/*! SCT0 - SCTimer/PWM wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_SCT0_SHIFT)) & SYSCTL0_STARTEN0_SET_SCT0_MASK)
+#define SYSCTL0_STARTEN0_SET_CT32BIT3_MASK (0x2000U)
+#define SYSCTL0_STARTEN0_SET_CT32BIT3_SHIFT (13U)
+/*! CT32BIT3 - CTIMER 3 wake-up
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_CT32BIT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_CT32BIT3_SHIFT)) & SYSCTL0_STARTEN0_SET_CT32BIT3_MASK)
+#define SYSCTL0_STARTEN0_SET_FLEXCOMM14_MASK (0x100000U)
+#define SYSCTL0_STARTEN0_SET_FLEXCOMM14_SHIFT (20U)
+/*! FLEXCOMM14 - FlexComm 14 (High Speed SPI) peripheral interrupt wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_FLEXCOMM14(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_FLEXCOMM14_SHIFT)) & SYSCTL0_STARTEN0_SET_FLEXCOMM14_MASK)
+#define SYSCTL0_STARTEN0_SET_FLEXCOMM15_MASK (0x200000U)
+#define SYSCTL0_STARTEN0_SET_FLEXCOMM15_SHIFT (21U)
+/*! FLEXCOMM15 - FlexComm 15 (PMIC I2C) peripheral interrupt wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_FLEXCOMM15(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_FLEXCOMM15_SHIFT)) & SYSCTL0_STARTEN0_SET_FLEXCOMM15_MASK)
+#define SYSCTL0_STARTEN0_SET_ADC0_MASK (0x400000U)
+#define SYSCTL0_STARTEN0_SET_ADC0_SHIFT (22U)
+/*! ADC0 - ADC wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_ADC0_SHIFT)) & SYSCTL0_STARTEN0_SET_ADC0_MASK)
+#define SYSCTL0_STARTEN0_SET_ACMP_MASK (0x1000000U)
+#define SYSCTL0_STARTEN0_SET_ACMP_SHIFT (24U)
+/*! ACMP - ACMP wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_ACMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_ACMP_SHIFT)) & SYSCTL0_STARTEN0_SET_ACMP_MASK)
+#define SYSCTL0_STARTEN0_SET_DMIC0_MASK (0x2000000U)
+#define SYSCTL0_STARTEN0_SET_DMIC0_SHIFT (25U)
+/*! DMIC0 - DMIC wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_DMIC0_SHIFT)) & SYSCTL0_STARTEN0_SET_DMIC0_MASK)
+#define SYSCTL0_STARTEN0_SET_HYPERVISOR_MASK (0x8000000U)
+#define SYSCTL0_STARTEN0_SET_HYPERVISOR_SHIFT (27U)
+/*! HYPERVISOR - Hypervisor interrupt wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_HYPERVISOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_HYPERVISOR_SHIFT)) & SYSCTL0_STARTEN0_SET_HYPERVISOR_MASK)
+#define SYSCTL0_STARTEN0_SET_SECUREVIOLATION_MASK (0x10000000U)
+#define SYSCTL0_STARTEN0_SET_SECUREVIOLATION_SHIFT (28U)
+/*! SECUREVIOLATION - Secure Violation wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_SECUREVIOLATION(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_SECUREVIOLATION_SHIFT)) & SYSCTL0_STARTEN0_SET_SECUREVIOLATION_MASK)
+#define SYSCTL0_STARTEN0_SET_HWVAD0_MASK (0x20000000U)
+#define SYSCTL0_STARTEN0_SET_HWVAD0_SHIFT (29U)
+/*! HWVAD0 - Hardware VAD wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_HWVAD0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_HWVAD0_SHIFT)) & SYSCTL0_STARTEN0_SET_HWVAD0_MASK)
+#define SYSCTL0_STARTEN0_SET_PMC_MASK (0x40000000U)
+#define SYSCTL0_STARTEN0_SET_PMC_SHIFT (30U)
+/*! PMC - PMC wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_PMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_PMC_SHIFT)) & SYSCTL0_STARTEN0_SET_PMC_MASK)
+#define SYSCTL0_STARTEN0_SET_RNG_MASK (0x80000000U)
+#define SYSCTL0_STARTEN0_SET_RNG_SHIFT (31U)
+/*! RNG - RNG wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_SET_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_RNG_SHIFT)) & SYSCTL0_STARTEN0_SET_RNG_MASK)
+/*! @} */
+
+/*! @name STARTEN1_SET - Start Enable 1 Set */
+/*! @{ */
+#define SYSCTL0_STARTEN1_SET_RTC_LITE0_WAKEUP_MASK (0x1U)
+#define SYSCTL0_STARTEN1_SET_RTC_LITE0_WAKEUP_SHIFT (0U)
+/*! RTC_LITE0_WAKEUP - RTC wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_RTC_LITE0_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_RTC_LITE0_WAKEUP_SHIFT)) & SYSCTL0_STARTEN1_SET_RTC_LITE0_WAKEUP_MASK)
+#define SYSCTL0_STARTEN1_SET_DSP_TIE_EXPSTATE1_MASK (0x2U)
+#define SYSCTL0_STARTEN1_SET_DSP_TIE_EXPSTATE1_SHIFT (1U)
+/*! DSP_TIE_EXPSTATE1 - DSP wake-up
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define SYSCTL0_STARTEN1_SET_DSP_TIE_EXPSTATE1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_DSP_TIE_EXPSTATE1_SHIFT)) & SYSCTL0_STARTEN1_SET_DSP_TIE_EXPSTATE1_MASK)
+#define SYSCTL0_STARTEN1_SET_MU_MASK (0x4U)
+#define SYSCTL0_STARTEN1_SET_MU_SHIFT (2U)
+/*! MU - Message Unit wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_MU(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_MU_SHIFT)) & SYSCTL0_STARTEN1_SET_MU_MASK)
+#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ4_MASK (0x8U)
+#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ4_SHIFT (3U)
+/*! GPIO_INT0_IRQ4 - Message Unit wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ4_SHIFT)) & SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ4_MASK)
+#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ5_MASK (0x10U)
+#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ5_SHIFT (4U)
+/*! GPIO_INT0_IRQ5 - GPIO pin interrupt 5 wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ5_SHIFT)) & SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ5_MASK)
+#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ6_MASK (0x20U)
+#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ6_SHIFT (5U)
+/*! GPIO_INT0_IRQ6 - GPIO pin interrupt 6 wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ6_SHIFT)) & SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ6_MASK)
+#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ7_MASK (0x40U)
+#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ7_SHIFT (6U)
+/*! GPIO_INT0_IRQ7 - GPIO pin interrupt 7 wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ7_SHIFT)) & SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ7_MASK)
+#define SYSCTL0_STARTEN1_SET_CT32BIT2_MASK (0x80U)
+#define SYSCTL0_STARTEN1_SET_CT32BIT2_SHIFT (7U)
+/*! CT32BIT2 - CTIMER 2 wake-up
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_CT32BIT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_CT32BIT2_SHIFT)) & SYSCTL0_STARTEN1_SET_CT32BIT2_MASK)
+#define SYSCTL0_STARTEN1_SET_CT32BIT4_MASK (0x100U)
+#define SYSCTL0_STARTEN1_SET_CT32BIT4_SHIFT (8U)
+/*! CT32BIT4 - CTIMER 4 wake-up
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_CT32BIT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_CT32BIT4_SHIFT)) & SYSCTL0_STARTEN1_SET_CT32BIT4_MASK)
+#define SYSCTL0_STARTEN1_SET_OS_EVENT_TIMER_WU_MASK (0x200U)
+#define SYSCTL0_STARTEN1_SET_OS_EVENT_TIMER_WU_SHIFT (9U)
+/*! OS_EVENT_TIMER_WU - OS Event Timer wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_OS_EVENT_TIMER_WU(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_OS_EVENT_TIMER_WU_SHIFT)) & SYSCTL0_STARTEN1_SET_OS_EVENT_TIMER_WU_MASK)
+#define SYSCTL0_STARTEN1_SET_FLEXSPI_MASK (0x400U)
+#define SYSCTL0_STARTEN1_SET_FLEXSPI_SHIFT (10U)
+/*! FLEXSPI - Quad/octal SPI wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_FLEXSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_FLEXSPI_SHIFT)) & SYSCTL0_STARTEN1_SET_FLEXSPI_MASK)
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM6_MASK (0x800U)
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM6_SHIFT (11U)
+/*! FLEXCOMM6 - FLEXCOMM6 wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_FLEXCOMM6_SHIFT)) & SYSCTL0_STARTEN1_SET_FLEXCOMM6_MASK)
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM7_MASK (0x1000U)
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM7_SHIFT (12U)
+/*! FLEXCOMM7 - FLEXCOMM7 wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_FLEXCOMM7_SHIFT)) & SYSCTL0_STARTEN1_SET_FLEXCOMM7_MASK)
+#define SYSCTL0_STARTEN1_SET_SDIO0_MASK (0x2000U)
+#define SYSCTL0_STARTEN1_SET_SDIO0_SHIFT (13U)
+/*! SDIO0 - SDIO0 wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_SDIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_SDIO0_SHIFT)) & SYSCTL0_STARTEN1_SET_SDIO0_MASK)
+#define SYSCTL0_STARTEN1_SET_SDIO1_MASK (0x4000U)
+#define SYSCTL0_STARTEN1_SET_SDIO1_SHIFT (14U)
+/*! SDIO1 - SDIO01 wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_SDIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_SDIO1_SHIFT)) & SYSCTL0_STARTEN1_SET_SDIO1_MASK)
+#define SYSCTL0_STARTEN1_SET_SGPIO_INTA_MASK (0x8000U)
+#define SYSCTL0_STARTEN1_SET_SGPIO_INTA_SHIFT (15U)
+/*! SGPIO_INTA - Secure GPIO interrupt A wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_SGPIO_INTA(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_SGPIO_INTA_SHIFT)) & SYSCTL0_STARTEN1_SET_SGPIO_INTA_MASK)
+#define SYSCTL0_STARTEN1_SET_SGPIO_INTB_MASK (0x10000U)
+#define SYSCTL0_STARTEN1_SET_SGPIO_INTB_SHIFT (16U)
+/*! SGPIO_INTB - Secure GPIO interrupt B wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_SGPIO_INTB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_SGPIO_INTB_SHIFT)) & SYSCTL0_STARTEN1_SET_SGPIO_INTB_MASK)
+#define SYSCTL0_STARTEN1_SET_USB0_NEEDCLK_MASK (0x80000U)
+#define SYSCTL0_STARTEN1_SET_USB0_NEEDCLK_SHIFT (19U)
+/*! USB0_NEEDCLK - USB activity wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_USB0_NEEDCLK_SHIFT)) & SYSCTL0_STARTEN1_SET_USB0_NEEDCLK_MASK)
+#define SYSCTL0_STARTEN1_SET_USB_PHYDCD_MASK (0x200000U)
+#define SYSCTL0_STARTEN1_SET_USB_PHYDCD_SHIFT (21U)
+/*! USB_PHYDCD - USB PHY DCD interrupt wake-up
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_USB_PHYDCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_USB_PHYDCD_SHIFT)) & SYSCTL0_STARTEN1_SET_USB_PHYDCD_MASK)
+#define SYSCTL0_STARTEN1_SET_DMAC1_MASK (0x400000U)
+#define SYSCTL0_STARTEN1_SET_DMAC1_SHIFT (22U)
+/*! DMAC1 - DMA controller 1 wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_DMAC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_DMAC1_SHIFT)) & SYSCTL0_STARTEN1_SET_DMAC1_MASK)
+#define SYSCTL0_STARTEN1_SET_PUF_MASK (0x800000U)
+#define SYSCTL0_STARTEN1_SET_PUF_SHIFT (23U)
+/*! PUF - PUF wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_PUF_SHIFT)) & SYSCTL0_STARTEN1_SET_PUF_MASK)
+#define SYSCTL0_STARTEN1_SET_POWERQUAD_MASK (0x1000000U)
+#define SYSCTL0_STARTEN1_SET_POWERQUAD_SHIFT (24U)
+/*! POWERQUAD - POWERQUAD co-processor wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_POWERQUAD_SHIFT)) & SYSCTL0_STARTEN1_SET_POWERQUAD_MASK)
+#define SYSCTL0_STARTEN1_SET_CASPER_MASK (0x2000000U)
+#define SYSCTL0_STARTEN1_SET_CASPER_SHIFT (25U)
+/*! CASPER - CASPER co-processor wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_CASPER_SHIFT)) & SYSCTL0_STARTEN1_SET_CASPER_MASK)
+#define SYSCTL0_STARTEN1_SET_PMIC_MASK (0x4000000U)
+#define SYSCTL0_STARTEN1_SET_PMIC_SHIFT (26U)
+/*! PMIC - Wake-up from on-chip PMC or off-chip PMIC.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_PMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_PMIC_SHIFT)) & SYSCTL0_STARTEN1_SET_PMIC_MASK)
+#define SYSCTL0_STARTEN1_SET_SHA_MASK (0x8000000U)
+#define SYSCTL0_STARTEN1_SET_SHA_SHIFT (27U)
+/*! SHA - Hash-AES wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_SHA_SHIFT)) & SYSCTL0_STARTEN1_SET_SHA_MASK)
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM8_MASK (0x10000000U)
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM8_SHIFT (28U)
+/*! FLEXCOMM8 - FLEXCOMM 8 peripheral interrupt wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_FLEXCOMM8_SHIFT)) & SYSCTL0_STARTEN1_SET_FLEXCOMM8_MASK)
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM9_MASK (0x20000000U)
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM9_SHIFT (29U)
+/*! FLEXCOMM9 - FLEXCOMM 9 peripheral interrupt wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_FLEXCOMM9_SHIFT)) & SYSCTL0_STARTEN1_SET_FLEXCOMM9_MASK)
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM10_MASK (0x40000000U)
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM10_SHIFT (30U)
+/*! FLEXCOMM10 - FLEXCOMM 10 peripheral interrupt wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_FLEXCOMM10_SHIFT)) & SYSCTL0_STARTEN1_SET_FLEXCOMM10_MASK)
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM11_MASK (0x80000000U)
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM11_SHIFT (31U)
+/*! FLEXCOMM11 - FLEXCOMM 11 peripheral interrupt wake-up.
+ * 0b0..No Effect
+ * 0b1..Sets the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_SET_FLEXCOMM11(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_FLEXCOMM11_SHIFT)) & SYSCTL0_STARTEN1_SET_FLEXCOMM11_MASK)
+/*! @} */
+
+/*! @name STARTEN2_SET - Start Enable 2 */
+/*! @{ */
+#define SYSCTL0_STARTEN2_SET_FLEXCOMMC12_MASK (0x1U)
+#define SYSCTL0_STARTEN2_SET_FLEXCOMMC12_SHIFT (0U)
+/*! FLEXCOMMC12 - FlexComm 12 interrupt wake-up
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN2 bit
+ */
+#define SYSCTL0_STARTEN2_SET_FLEXCOMMC12(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN2_SET_FLEXCOMMC12_SHIFT)) & SYSCTL0_STARTEN2_SET_FLEXCOMMC12_MASK)
+#define SYSCTL0_STARTEN2_SET_FLEXCOMM13_MASK (0x2U)
+#define SYSCTL0_STARTEN2_SET_FLEXCOMM13_SHIFT (1U)
+/*! FLEXCOMM13 - FlexComm 13 interrupt wake-up
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN2 bit
+ */
+#define SYSCTL0_STARTEN2_SET_FLEXCOMM13(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN2_SET_FLEXCOMM13_SHIFT)) & SYSCTL0_STARTEN2_SET_FLEXCOMM13_MASK)
+#define SYSCTL0_STARTEN2_SET_FLEXCOMM16_MASK (0x4U)
+#define SYSCTL0_STARTEN2_SET_FLEXCOMM16_SHIFT (2U)
+/*! FLEXCOMM16 - FlexComm16 interrupt wake-up
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN2 bit
+ */
+#define SYSCTL0_STARTEN2_SET_FLEXCOMM16(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN2_SET_FLEXCOMM16_SHIFT)) & SYSCTL0_STARTEN2_SET_FLEXCOMM16_MASK)
+/*! @} */
+
+/*! @name STARTEN0_CLR - Start Enable 0 clear */
+/*! @{ */
+#define SYSCTL0_STARTEN0_CLR_WDT0_MASK (0x1U)
+#define SYSCTL0_STARTEN0_CLR_WDT0_SHIFT (0U)
+/*! WDT0 - Watchdog timer 0 wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_WDT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_WDT0_SHIFT)) & SYSCTL0_STARTEN0_CLR_WDT0_MASK)
+#define SYSCTL0_STARTEN0_CLR_DMAC0_MASK (0x2U)
+#define SYSCTL0_STARTEN0_CLR_DMAC0_SHIFT (1U)
+/*! DMAC0 - DMA controller 0 wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_DMAC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_DMAC0_SHIFT)) & SYSCTL0_STARTEN0_CLR_DMAC0_MASK)
+#define SYSCTL0_STARTEN0_CLR_GPIO_INTA_MASK (0x4U)
+#define SYSCTL0_STARTEN0_CLR_GPIO_INTA_SHIFT (2U)
+/*! GPIO_INTA - Non-secure GPIO interrupt A wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_GPIO_INTA(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_GPIO_INTA_SHIFT)) & SYSCTL0_STARTEN0_CLR_GPIO_INTA_MASK)
+#define SYSCTL0_STARTEN0_CLR_GPIO_INTB_MASK (0x8U)
+#define SYSCTL0_STARTEN0_CLR_GPIO_INTB_SHIFT (3U)
+/*! GPIO_INTB - Non-secure GPIO interrupt B wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_GPIO_INTB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_GPIO_INTB_SHIFT)) & SYSCTL0_STARTEN0_CLR_GPIO_INTB_MASK)
+#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ0_MASK (0x10U)
+#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ0_SHIFT (4U)
+/*! GPIO_INT0_IRQ0 - GPIO pin interrupt 0 wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ0_SHIFT)) & SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ0_MASK)
+#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ1_MASK (0x20U)
+#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ1_SHIFT (5U)
+/*! GPIO_INT0_IRQ1 - GPIO pin interrupt 1 wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ1_SHIFT)) & SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ1_MASK)
+#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ2_MASK (0x40U)
+#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ2_SHIFT (6U)
+/*! GPIO_INT0_IRQ2 - GPIO pin interrupt 2 wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ2_SHIFT)) & SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ2_MASK)
+#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ3_MASK (0x80U)
+#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ3_SHIFT (7U)
+/*! GPIO_INT0_IRQ3 - GPIO pin interrupt 3 wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ3_SHIFT)) & SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ3_MASK)
+#define SYSCTL0_STARTEN0_CLR_UTICK0_MASK (0x100U)
+#define SYSCTL0_STARTEN0_CLR_UTICK0_SHIFT (8U)
+/*! UTICK0 - UTICK wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_UTICK0_SHIFT)) & SYSCTL0_STARTEN0_CLR_UTICK0_MASK)
+#define SYSCTL0_STARTEN0_CLR_MRT0_MASK (0x200U)
+#define SYSCTL0_STARTEN0_CLR_MRT0_SHIFT (9U)
+/*! MRT0 - MRT wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_MRT0_SHIFT)) & SYSCTL0_STARTEN0_CLR_MRT0_MASK)
+#define SYSCTL0_STARTEN0_CLR_CT32BIT0_MASK (0x400U)
+#define SYSCTL0_STARTEN0_CLR_CT32BIT0_SHIFT (10U)
+/*! CT32BIT0 - CTIMER 0 wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_CT32BIT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_CT32BIT0_SHIFT)) & SYSCTL0_STARTEN0_CLR_CT32BIT0_MASK)
+#define SYSCTL0_STARTEN0_CLR_CT32BIT1_MASK (0x800U)
+#define SYSCTL0_STARTEN0_CLR_CT32BIT1_SHIFT (11U)
+/*! CT32BIT1 - CTIMER 1 wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_CT32BIT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_CT32BIT1_SHIFT)) & SYSCTL0_STARTEN0_CLR_CT32BIT1_MASK)
+#define SYSCTL0_STARTEN0_CLR_SCT0_MASK (0x1000U)
+#define SYSCTL0_STARTEN0_CLR_SCT0_SHIFT (12U)
+/*! SCT0 - SCTimer/PWM wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_SCT0_SHIFT)) & SYSCTL0_STARTEN0_CLR_SCT0_MASK)
+#define SYSCTL0_STARTEN0_CLR_CT32BIT3_MASK (0x2000U)
+#define SYSCTL0_STARTEN0_CLR_CT32BIT3_SHIFT (13U)
+/*! CT32BIT3 - CTIMER 3 wake-up
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_CT32BIT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_CT32BIT3_SHIFT)) & SYSCTL0_STARTEN0_CLR_CT32BIT3_MASK)
+#define SYSCTL0_STARTEN0_CLR_FLEXCOMM14_MASK (0x100000U)
+#define SYSCTL0_STARTEN0_CLR_FLEXCOMM14_SHIFT (20U)
+/*! FLEXCOMM14 - FlexComm 14 (High Speed SPI) peripheral interrupt wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_FLEXCOMM14(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_FLEXCOMM14_SHIFT)) & SYSCTL0_STARTEN0_CLR_FLEXCOMM14_MASK)
+#define SYSCTL0_STARTEN0_CLR_FLEXCOMM15_MASK (0x200000U)
+#define SYSCTL0_STARTEN0_CLR_FLEXCOMM15_SHIFT (21U)
+/*! FLEXCOMM15 - FlexComm 15 (PMIC I2C) peripheral interrupt wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_FLEXCOMM15(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_FLEXCOMM15_SHIFT)) & SYSCTL0_STARTEN0_CLR_FLEXCOMM15_MASK)
+#define SYSCTL0_STARTEN0_CLR_ADC0_MASK (0x400000U)
+#define SYSCTL0_STARTEN0_CLR_ADC0_SHIFT (22U)
+/*! ADC0 - ADC wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_ADC0_SHIFT)) & SYSCTL0_STARTEN0_CLR_ADC0_MASK)
+#define SYSCTL0_STARTEN0_CLR_ACMP_MASK (0x1000000U)
+#define SYSCTL0_STARTEN0_CLR_ACMP_SHIFT (24U)
+/*! ACMP - ACMP wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_ACMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_ACMP_SHIFT)) & SYSCTL0_STARTEN0_CLR_ACMP_MASK)
+#define SYSCTL0_STARTEN0_CLR_DMIC0_MASK (0x2000000U)
+#define SYSCTL0_STARTEN0_CLR_DMIC0_SHIFT (25U)
+/*! DMIC0 - DMIC wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_DMIC0_SHIFT)) & SYSCTL0_STARTEN0_CLR_DMIC0_MASK)
+#define SYSCTL0_STARTEN0_CLR_HYPERVISOR_MASK (0x8000000U)
+#define SYSCTL0_STARTEN0_CLR_HYPERVISOR_SHIFT (27U)
+/*! HYPERVISOR - Hypervisor interrupt wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_HYPERVISOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_HYPERVISOR_SHIFT)) & SYSCTL0_STARTEN0_CLR_HYPERVISOR_MASK)
+#define SYSCTL0_STARTEN0_CLR_SECUREVIOLATION_MASK (0x10000000U)
+#define SYSCTL0_STARTEN0_CLR_SECUREVIOLATION_SHIFT (28U)
+/*! SECUREVIOLATION - Secure Violation wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_SECUREVIOLATION(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_SECUREVIOLATION_SHIFT)) & SYSCTL0_STARTEN0_CLR_SECUREVIOLATION_MASK)
+#define SYSCTL0_STARTEN0_CLR_HWVAD0_MASK (0x20000000U)
+#define SYSCTL0_STARTEN0_CLR_HWVAD0_SHIFT (29U)
+/*! HWVAD0 - Hardware VAD wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_HWVAD0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_HWVAD0_SHIFT)) & SYSCTL0_STARTEN0_CLR_HWVAD0_MASK)
+#define SYSCTL0_STARTEN0_CLR_PMC_MASK (0x40000000U)
+#define SYSCTL0_STARTEN0_CLR_PMC_SHIFT (30U)
+/*! PMC - PMC wake-up.
+ * 0b0..No effect
+ * 0b1..Sets the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_PMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_PMC_SHIFT)) & SYSCTL0_STARTEN0_CLR_PMC_MASK)
+#define SYSCTL0_STARTEN0_CLR_RNG_MASK (0x80000000U)
+#define SYSCTL0_STARTEN0_CLR_RNG_SHIFT (31U)
+/*! RNG - RNG wake-up.
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN0 Bit
+ */
+#define SYSCTL0_STARTEN0_CLR_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_RNG_SHIFT)) & SYSCTL0_STARTEN0_CLR_RNG_MASK)
+/*! @} */
+
+/*! @name STARTEN1_CLR - Start Enable 1 clear */
+/*! @{ */
+#define SYSCTL0_STARTEN1_CLR_RTC_LITE0_WAKEUP_MASK (0x1U)
+#define SYSCTL0_STARTEN1_CLR_RTC_LITE0_WAKEUP_SHIFT (0U)
+/*! RTC_LITE0_WAKEUP - RTC wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_RTC_LITE0_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_RTC_LITE0_WAKEUP_SHIFT)) & SYSCTL0_STARTEN1_CLR_RTC_LITE0_WAKEUP_MASK)
+#define SYSCTL0_STARTEN1_CLR_MU_MASK (0x4U)
+#define SYSCTL0_STARTEN1_CLR_MU_SHIFT (2U)
+/*! MU - Message Unit wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_MU(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_MU_SHIFT)) & SYSCTL0_STARTEN1_CLR_MU_MASK)
+#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ4_MASK (0x8U)
+#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ4_SHIFT (3U)
+/*! GPIO_INT0_IRQ4 - Message Unit wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ4_SHIFT)) & SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ4_MASK)
+#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ5_MASK (0x10U)
+#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ5_SHIFT (4U)
+/*! GPIO_INT0_IRQ5 - GPIO pin interrupt 5 wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ5_SHIFT)) & SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ5_MASK)
+#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ6_MASK (0x20U)
+#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ6_SHIFT (5U)
+/*! GPIO_INT0_IRQ6 - GPIO pin interrupt 6 wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ6_SHIFT)) & SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ6_MASK)
+#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ7_MASK (0x40U)
+#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ7_SHIFT (6U)
+/*! GPIO_INT0_IRQ7 - GPIO pin interrupt 7 wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ7_SHIFT)) & SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ7_MASK)
+#define SYSCTL0_STARTEN1_CLR_CT32BIT2_MASK (0x80U)
+#define SYSCTL0_STARTEN1_CLR_CT32BIT2_SHIFT (7U)
+/*! CT32BIT2 - CTIMER 2 wake-up
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_CT32BIT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_CT32BIT2_SHIFT)) & SYSCTL0_STARTEN1_CLR_CT32BIT2_MASK)
+#define SYSCTL0_STARTEN1_CLR_CT32BIT4_MASK (0x100U)
+#define SYSCTL0_STARTEN1_CLR_CT32BIT4_SHIFT (8U)
+/*! CT32BIT4 - CTIMER 4 wake-up
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_CT32BIT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_CT32BIT4_SHIFT)) & SYSCTL0_STARTEN1_CLR_CT32BIT4_MASK)
+#define SYSCTL0_STARTEN1_CLR_OS_EVENT_TIMER_WU_MASK (0x200U)
+#define SYSCTL0_STARTEN1_CLR_OS_EVENT_TIMER_WU_SHIFT (9U)
+/*! OS_EVENT_TIMER_WU - OS Event Timer wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_OS_EVENT_TIMER_WU(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_OS_EVENT_TIMER_WU_SHIFT)) & SYSCTL0_STARTEN1_CLR_OS_EVENT_TIMER_WU_MASK)
+#define SYSCTL0_STARTEN1_CLR_FLEXSPI_MASK (0x400U)
+#define SYSCTL0_STARTEN1_CLR_FLEXSPI_SHIFT (10U)
+/*! FLEXSPI - Quad/octal SPI wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_FLEXSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_FLEXSPI_SHIFT)) & SYSCTL0_STARTEN1_CLR_FLEXSPI_MASK)
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM6_MASK (0x800U)
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM6_SHIFT (11U)
+/*! FLEXCOMM6 - FLEXCOMM6 wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_FLEXCOMM6_SHIFT)) & SYSCTL0_STARTEN1_CLR_FLEXCOMM6_MASK)
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM7_MASK (0x1000U)
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM7_SHIFT (12U)
+/*! FLEXCOMM7 - FLEXCOMM7 wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_FLEXCOMM7_SHIFT)) & SYSCTL0_STARTEN1_CLR_FLEXCOMM7_MASK)
+#define SYSCTL0_STARTEN1_CLR_SDIO0_MASK (0x2000U)
+#define SYSCTL0_STARTEN1_CLR_SDIO0_SHIFT (13U)
+/*! SDIO0 - SDIO0 wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_SDIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_SDIO0_SHIFT)) & SYSCTL0_STARTEN1_CLR_SDIO0_MASK)
+#define SYSCTL0_STARTEN1_CLR_SDIO1_MASK (0x4000U)
+#define SYSCTL0_STARTEN1_CLR_SDIO1_SHIFT (14U)
+/*! SDIO1 - SDIO01 wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_SDIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_SDIO1_SHIFT)) & SYSCTL0_STARTEN1_CLR_SDIO1_MASK)
+#define SYSCTL0_STARTEN1_CLR_SGPIO_INTA_MASK (0x8000U)
+#define SYSCTL0_STARTEN1_CLR_SGPIO_INTA_SHIFT (15U)
+/*! SGPIO_INTA - Secure GPIO interrupt A wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_SGPIO_INTA(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_SGPIO_INTA_SHIFT)) & SYSCTL0_STARTEN1_CLR_SGPIO_INTA_MASK)
+#define SYSCTL0_STARTEN1_CLR_SGPIO_INTB_MASK (0x10000U)
+#define SYSCTL0_STARTEN1_CLR_SGPIO_INTB_SHIFT (16U)
+/*! SGPIO_INTB - Secure GPIO interrupt B wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_SGPIO_INTB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_SGPIO_INTB_SHIFT)) & SYSCTL0_STARTEN1_CLR_SGPIO_INTB_MASK)
+#define SYSCTL0_STARTEN1_CLR_USB0_NEEDCLK_MASK (0x80000U)
+#define SYSCTL0_STARTEN1_CLR_USB0_NEEDCLK_SHIFT (19U)
+/*! USB0_NEEDCLK - USB activity wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_USB0_NEEDCLK_SHIFT)) & SYSCTL0_STARTEN1_CLR_USB0_NEEDCLK_MASK)
+#define SYSCTL0_STARTEN1_CLR_USB_PHYDCD_MASK (0x200000U)
+#define SYSCTL0_STARTEN1_CLR_USB_PHYDCD_SHIFT (21U)
+/*! USB_PHYDCD - USB PHY DCD interrupt wake-up
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_USB_PHYDCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_USB_PHYDCD_SHIFT)) & SYSCTL0_STARTEN1_CLR_USB_PHYDCD_MASK)
+#define SYSCTL0_STARTEN1_CLR_DMAC1_MASK (0x400000U)
+#define SYSCTL0_STARTEN1_CLR_DMAC1_SHIFT (22U)
+/*! DMAC1 - DMA controller 1 wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_DMAC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_DMAC1_SHIFT)) & SYSCTL0_STARTEN1_CLR_DMAC1_MASK)
+#define SYSCTL0_STARTEN1_CLR_PUF_MASK (0x800000U)
+#define SYSCTL0_STARTEN1_CLR_PUF_SHIFT (23U)
+/*! PUF - PUF wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_PUF_SHIFT)) & SYSCTL0_STARTEN1_CLR_PUF_MASK)
+#define SYSCTL0_STARTEN1_CLR_POWERQUAD_MASK (0x1000000U)
+#define SYSCTL0_STARTEN1_CLR_POWERQUAD_SHIFT (24U)
+/*! POWERQUAD - POWERQUAD co-processor wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_POWERQUAD_SHIFT)) & SYSCTL0_STARTEN1_CLR_POWERQUAD_MASK)
+#define SYSCTL0_STARTEN1_CLR_CASPER_MASK (0x2000000U)
+#define SYSCTL0_STARTEN1_CLR_CASPER_SHIFT (25U)
+/*! CASPER - CASPER co-processor wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_CASPER_SHIFT)) & SYSCTL0_STARTEN1_CLR_CASPER_MASK)
+#define SYSCTL0_STARTEN1_CLR_PMIC_MASK (0x4000000U)
+#define SYSCTL0_STARTEN1_CLR_PMIC_SHIFT (26U)
+/*! PMIC - Wake-up from on-chip PMC or off-chip PMIC.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_PMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_PMIC_SHIFT)) & SYSCTL0_STARTEN1_CLR_PMIC_MASK)
+#define SYSCTL0_STARTEN1_CLR_SHA_MASK (0x8000000U)
+#define SYSCTL0_STARTEN1_CLR_SHA_SHIFT (27U)
+/*! SHA - Hash-AES wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_SHA_SHIFT)) & SYSCTL0_STARTEN1_CLR_SHA_MASK)
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM8_MASK (0x10000000U)
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM8_SHIFT (28U)
+/*! FLEXCOMM8 - FLEXCOMM 8 peripheral interrupt wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_FLEXCOMM8_SHIFT)) & SYSCTL0_STARTEN1_CLR_FLEXCOMM8_MASK)
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM9_MASK (0x20000000U)
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM9_SHIFT (29U)
+/*! FLEXCOMM9 - FLEXCOMM 9 peripheral interrupt wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_FLEXCOMM9_SHIFT)) & SYSCTL0_STARTEN1_CLR_FLEXCOMM9_MASK)
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM10_MASK (0x40000000U)
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM10_SHIFT (30U)
+/*! FLEXCOMM10 - FLEXCOMM 10 peripheral interrupt wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM10(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_FLEXCOMM10_SHIFT)) & SYSCTL0_STARTEN1_CLR_FLEXCOMM10_MASK)
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM11_MASK (0x80000000U)
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM11_SHIFT (31U)
+/*! FLEXCOMM11 - FLEXCOMM 11 peripheral interrupt wake-up.
+ * 0b0..No Effect
+ * 0b1..Clears the STARTEN1 Bit
+ */
+#define SYSCTL0_STARTEN1_CLR_FLEXCOMM11(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_FLEXCOMM11_SHIFT)) & SYSCTL0_STARTEN1_CLR_FLEXCOMM11_MASK)
+/*! @} */
+
+/*! @name STARTEN2_CLR - Start Enable 2 */
+/*! @{ */
+#define SYSCTL0_STARTEN2_CLR_FLEXCOMM12_MASK (0x1U)
+#define SYSCTL0_STARTEN2_CLR_FLEXCOMM12_SHIFT (0U)
+/*! FLEXCOMM12 - FlexComm 12 interrupt wake-up
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN2 bit
+ */
+#define SYSCTL0_STARTEN2_CLR_FLEXCOMM12(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN2_CLR_FLEXCOMM12_SHIFT)) & SYSCTL0_STARTEN2_CLR_FLEXCOMM12_MASK)
+#define SYSCTL0_STARTEN2_CLR_FLEXCOMM13_MASK (0x2U)
+#define SYSCTL0_STARTEN2_CLR_FLEXCOMM13_SHIFT (1U)
+/*! FLEXCOMM13 - FlexComm 13 interrupt wake-up
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN2 bit
+ */
+#define SYSCTL0_STARTEN2_CLR_FLEXCOMM13(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN2_CLR_FLEXCOMM13_SHIFT)) & SYSCTL0_STARTEN2_CLR_FLEXCOMM13_MASK)
+#define SYSCTL0_STARTEN2_CLR_FLEXCOMM16_MASK (0x4U)
+#define SYSCTL0_STARTEN2_CLR_FLEXCOMM16_SHIFT (2U)
+/*! FLEXCOMM16 - FlexComm 16 interrupt wake-up
+ * 0b0..No effect
+ * 0b1..Clears the STARTEN2 bit
+ */
+#define SYSCTL0_STARTEN2_CLR_FLEXCOMM16(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN2_CLR_FLEXCOMM16_SHIFT)) & SYSCTL0_STARTEN2_CLR_FLEXCOMM16_MASK)
+/*! @} */
+
+/*! @name MAINCLKSAFETY - Main Clock Safety */
+/*! @{ */
+#define SYSCTL0_MAINCLKSAFETY_DELAY_MASK (0xFFFFU)
+#define SYSCTL0_MAINCLKSAFETY_DELAY_SHIFT (0U)
+/*! DELAY - Main Clock turn on delay for Deep Sleep wake up
+ */
+#define SYSCTL0_MAINCLKSAFETY_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MAINCLKSAFETY_DELAY_SHIFT)) & SYSCTL0_MAINCLKSAFETY_DELAY_MASK)
+/*! @} */
+
+/*! @name HWWAKE - Hardware Wake */
+/*! @{ */
+#define SYSCTL0_HWWAKE_FORCEWAKE_MASK (0x1U)
+#define SYSCTL0_HWWAKE_FORCEWAKE_SHIFT (0U)
+/*! FORCEWAKE - Force peripheral clocking to stay on during deep-sleep mode.
+ */
+#define SYSCTL0_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWWAKE_FORCEWAKE_SHIFT)) & SYSCTL0_HWWAKE_FORCEWAKE_MASK)
+#define SYSCTL0_HWWAKE_FCWAKE_MASK (0x2U)
+#define SYSCTL0_HWWAKE_FCWAKE_SHIFT (1U)
+/*! FCWAKE - Wake for FlexComm Interfaces.
+ */
+#define SYSCTL0_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWWAKE_FCWAKE_SHIFT)) & SYSCTL0_HWWAKE_FCWAKE_MASK)
+#define SYSCTL0_HWWAKE_DMICWAKE_MASK (0x4U)
+#define SYSCTL0_HWWAKE_DMICWAKE_SHIFT (2U)
+/*! DMICWAKE - Wake for Digital Microphone.
+ */
+#define SYSCTL0_HWWAKE_DMICWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWWAKE_DMICWAKE_SHIFT)) & SYSCTL0_HWWAKE_DMICWAKE_MASK)
+#define SYSCTL0_HWWAKE_DMAC0WAKE_MASK (0x8U)
+#define SYSCTL0_HWWAKE_DMAC0WAKE_SHIFT (3U)
+/*! DMAC0WAKE - Wake for DMAC0.
+ */
+#define SYSCTL0_HWWAKE_DMAC0WAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWWAKE_DMAC0WAKE_SHIFT)) & SYSCTL0_HWWAKE_DMAC0WAKE_MASK)
+#define SYSCTL0_HWWAKE_DMAC1WAKE_MASK (0x10U)
+#define SYSCTL0_HWWAKE_DMAC1WAKE_SHIFT (4U)
+/*! DMAC1WAKE - Wake for DMAC1.
+ */
+#define SYSCTL0_HWWAKE_DMAC1WAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWWAKE_DMAC1WAKE_SHIFT)) & SYSCTL0_HWWAKE_DMAC1WAKE_MASK)
+/*! @} */
+
+/*! @name TEMPSENSORCTL - Temperature Sensor Control */
+/*! @{ */
+#define SYSCTL0_TEMPSENSORCTL_TSSRC_MASK (0x1U)
+#define SYSCTL0_TEMPSENSORCTL_TSSRC_SHIFT (0U)
+/*! TSSRC - Temperature Sensor Source
+ * 0b0..ADC Built-in Temperature Sensor
+ * 0b1..PMC Temperature Sensor
+ */
+#define SYSCTL0_TEMPSENSORCTL_TSSRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_TEMPSENSORCTL_TSSRC_SHIFT)) & SYSCTL0_TEMPSENSORCTL_TSSRC_MASK)
+/*! @} */
+
+/*! @name BOOTSTATELOCK - Boot State Lock */
+/*! @{ */
+#define SYSCTL0_BOOTSTATELOCK_BOOTSTATESEEDLOCK_MASK (0x1U)
+#define SYSCTL0_BOOTSTATELOCK_BOOTSTATESEEDLOCK_SHIFT (0U)
+/*! BOOTSTATESEEDLOCK - Boot State Seed Lockout
+ * 0b0..BOOTSTATESEED[0:7] can be changed
+ * 0b1..BOOTSTATESEED[0:7] cannot be changed
+ */
+#define SYSCTL0_BOOTSTATELOCK_BOOTSTATESEEDLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_BOOTSTATELOCK_BOOTSTATESEEDLOCK_SHIFT)) & SYSCTL0_BOOTSTATELOCK_BOOTSTATESEEDLOCK_MASK)
+#define SYSCTL0_BOOTSTATELOCK_BOOTSTATEHMACLOCK_MASK (0x2U)
+#define SYSCTL0_BOOTSTATELOCK_BOOTSTATEHMACLOCK_SHIFT (1U)
+/*! BOOTSTATEHMACLOCK - Boot State HMA Lockout
+ * 0b0..BOOTSTATEHMAC[0:7] can be changed
+ * 0b1..BOOTSTATEHMAC[0:7] cannot be changed
+ */
+#define SYSCTL0_BOOTSTATELOCK_BOOTSTATEHMACLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_BOOTSTATELOCK_BOOTSTATEHMACLOCK_SHIFT)) & SYSCTL0_BOOTSTATELOCK_BOOTSTATEHMACLOCK_MASK)
+/*! @} */
+
+/*! @name BOOTSTATESEED - Boot State Seed */
+/*! @{ */
+#define SYSCTL0_BOOTSTATESEED_BOOTSTATESEED_MASK (0xFFFFFFFFU)
+#define SYSCTL0_BOOTSTATESEED_BOOTSTATESEED_SHIFT (0U)
+/*! BOOTSTATESEED - BOOTSTATESEED[0:7]
+ */
+#define SYSCTL0_BOOTSTATESEED_BOOTSTATESEED(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_BOOTSTATESEED_BOOTSTATESEED_SHIFT)) & SYSCTL0_BOOTSTATESEED_BOOTSTATESEED_MASK)
+/*! @} */
+
+/* The count of SYSCTL0_BOOTSTATESEED */
+#define SYSCTL0_BOOTSTATESEED_COUNT (8U)
+
+/*! @name BOOTSTATEHMAC - HMAC of boot state used for attestation. */
+/*! @{ */
+#define SYSCTL0_BOOTSTATEHMAC_BOOTSTATEHMAC_MASK (0xFFFFFFFFU)
+#define SYSCTL0_BOOTSTATEHMAC_BOOTSTATEHMAC_SHIFT (0U)
+/*! BOOTSTATEHMAC - BOOTSTATEHMAC[0:7]
+ */
+#define SYSCTL0_BOOTSTATEHMAC_BOOTSTATEHMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_BOOTSTATEHMAC_BOOTSTATEHMAC_SHIFT)) & SYSCTL0_BOOTSTATEHMAC_BOOTSTATEHMAC_MASK)
+/*! @} */
+
+/* The count of SYSCTL0_BOOTSTATEHMAC */
+#define SYSCTL0_BOOTSTATEHMAC_COUNT (8U)
+
+/*! @name FLEXSPI0PADCTL - FLEXSPI0 Pad Control */
+/*! @{ */
+#define SYSCTL0_FLEXSPI0PADCTL_RASRCN_3_0_MASK (0xFU)
+#define SYSCTL0_FLEXSPI0PADCTL_RASRCN_3_0_SHIFT (0U)
+/*! RASRCN_3_0 - Drives FLEXSPI0 Pad Compensation Circuit
+ */
+#define SYSCTL0_FLEXSPI0PADCTL_RASRCN_3_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_RASRCN_3_0_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_RASRCN_3_0_MASK)
+#define SYSCTL0_FLEXSPI0PADCTL_RASRCP_3_0_MASK (0xF0U)
+#define SYSCTL0_FLEXSPI0PADCTL_RASRCP_3_0_SHIFT (4U)
+/*! RASRCP_3_0 - Drives FLEXSPI0 Pad Compensation Circuit
+ */
+#define SYSCTL0_FLEXSPI0PADCTL_RASRCP_3_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_RASRCP_3_0_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_RASRCP_3_0_MASK)
+#define SYSCTL0_FLEXSPI0PADCTL_FASTFRZ_MASK (0x100U)
+#define SYSCTL0_FLEXSPI0PADCTL_FASTFRZ_SHIFT (8U)
+/*! FASTFRZ - Drives FLEXSPI0 Pad Compensation Circuit
+ */
+#define SYSCTL0_FLEXSPI0PADCTL_FASTFRZ(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_FASTFRZ_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_FASTFRZ_MASK)
+#define SYSCTL0_FLEXSPI0PADCTL_FREEZE_MASK (0x200U)
+#define SYSCTL0_FLEXSPI0PADCTL_FREEZE_SHIFT (9U)
+/*! FREEZE - Drives FLEXSPI0 Pad Compensation Circuit
+ */
+#define SYSCTL0_FLEXSPI0PADCTL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_FREEZE_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_FREEZE_MASK)
+#define SYSCTL0_FLEXSPI0PADCTL_COMPTQ_MASK (0x400U)
+#define SYSCTL0_FLEXSPI0PADCTL_COMPTQ_SHIFT (10U)
+/*! COMPTQ - Drives FLEXSPI0 Pad Compensation Circuit
+ */
+#define SYSCTL0_FLEXSPI0PADCTL_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_COMPTQ_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_COMPTQ_MASK)
+#define SYSCTL0_FLEXSPI0PADCTL_COMPEN_MASK (0x800U)
+#define SYSCTL0_FLEXSPI0PADCTL_COMPEN_SHIFT (11U)
+/*! COMPEN - Drives FLEXSPI0 Pad Compensation Circuit
+ */
+#define SYSCTL0_FLEXSPI0PADCTL_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_COMPEN_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_COMPEN_MASK)
+#define SYSCTL0_FLEXSPI0PADCTL_NASRCN_MASK (0xF0000U)
+#define SYSCTL0_FLEXSPI0PADCTL_NASRCN_SHIFT (16U)
+/*! NASRCN - FLEXSPI0 Pad Compensation Circuit Status
+ */
+#define SYSCTL0_FLEXSPI0PADCTL_NASRCN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_NASRCN_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_NASRCN_MASK)
+#define SYSCTL0_FLEXSPI0PADCTL_NASRCP_MASK (0xF00000U)
+#define SYSCTL0_FLEXSPI0PADCTL_NASRCP_SHIFT (20U)
+/*! NASRCP - FLEXSPI0 Pad Compensation Circuit Status
+ */
+#define SYSCTL0_FLEXSPI0PADCTL_NASRCP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_NASRCP_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_NASRCP_MASK)
+#define SYSCTL0_FLEXSPI0PADCTL_COMPOK_MASK (0x1000000U)
+#define SYSCTL0_FLEXSPI0PADCTL_COMPOK_SHIFT (24U)
+/*! COMPOK - FLEXSPI0 Pad Compensation Circuit Status
+ */
+#define SYSCTL0_FLEXSPI0PADCTL_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_COMPOK_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_COMPOK_MASK)
+/*! @} */
+
+/*! @name FLEXSPI1PADCTL - FLEXSPI1 Pad Control */
+/*! @{ */
+#define SYSCTL0_FLEXSPI1PADCTL_RASRCN_3_0_MASK (0xFU)
+#define SYSCTL0_FLEXSPI1PADCTL_RASRCN_3_0_SHIFT (0U)
+/*! RASRCN_3_0 - Drives FLEXSPI1 Pad Compensation Circuit
+ */
+#define SYSCTL0_FLEXSPI1PADCTL_RASRCN_3_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_RASRCN_3_0_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_RASRCN_3_0_MASK)
+#define SYSCTL0_FLEXSPI1PADCTL_RASRCP_3_0_MASK (0xF0U)
+#define SYSCTL0_FLEXSPI1PADCTL_RASRCP_3_0_SHIFT (4U)
+/*! RASRCP_3_0 - Drives FLEXSPI1 Pad Compensation Circuit
+ */
+#define SYSCTL0_FLEXSPI1PADCTL_RASRCP_3_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_RASRCP_3_0_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_RASRCP_3_0_MASK)
+#define SYSCTL0_FLEXSPI1PADCTL_FASTFRZ_MASK (0x100U)
+#define SYSCTL0_FLEXSPI1PADCTL_FASTFRZ_SHIFT (8U)
+/*! FASTFRZ - Drives FLEXSPI1 Pad Compensation Circuit
+ */
+#define SYSCTL0_FLEXSPI1PADCTL_FASTFRZ(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_FASTFRZ_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_FASTFRZ_MASK)
+#define SYSCTL0_FLEXSPI1PADCTL_FREEZE_MASK (0x200U)
+#define SYSCTL0_FLEXSPI1PADCTL_FREEZE_SHIFT (9U)
+/*! FREEZE - Drives FLEXSPI1 Pad Compensation Circuit
+ */
+#define SYSCTL0_FLEXSPI1PADCTL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_FREEZE_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_FREEZE_MASK)
+#define SYSCTL0_FLEXSPI1PADCTL_COMPTQ_MASK (0x400U)
+#define SYSCTL0_FLEXSPI1PADCTL_COMPTQ_SHIFT (10U)
+/*! COMPTQ - Drives FLEXSPI1 Pad Compensation Circuit
+ */
+#define SYSCTL0_FLEXSPI1PADCTL_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_COMPTQ_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_COMPTQ_MASK)
+#define SYSCTL0_FLEXSPI1PADCTL_COMPEN_MASK (0x800U)
+#define SYSCTL0_FLEXSPI1PADCTL_COMPEN_SHIFT (11U)
+/*! COMPEN - Drives FLEXSPI1 Pad Compensation Circuit
+ */
+#define SYSCTL0_FLEXSPI1PADCTL_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_COMPEN_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_COMPEN_MASK)
+#define SYSCTL0_FLEXSPI1PADCTL_NASRCN_3_0_MASK (0xF0000U)
+#define SYSCTL0_FLEXSPI1PADCTL_NASRCN_3_0_SHIFT (16U)
+/*! NASRCN_3_0 - FLEXSPI1 Pad Compensation Circuit Status
+ */
+#define SYSCTL0_FLEXSPI1PADCTL_NASRCN_3_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_NASRCN_3_0_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_NASRCN_3_0_MASK)
+#define SYSCTL0_FLEXSPI1PADCTL_NASRCP_3_0_MASK (0xF00000U)
+#define SYSCTL0_FLEXSPI1PADCTL_NASRCP_3_0_SHIFT (20U)
+/*! NASRCP_3_0 - FLEXSPI1 Pad Compensation Circuit Status
+ */
+#define SYSCTL0_FLEXSPI1PADCTL_NASRCP_3_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_NASRCP_3_0_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_NASRCP_3_0_MASK)
+#define SYSCTL0_FLEXSPI1PADCTL_COMPOK_MASK (0x1000000U)
+#define SYSCTL0_FLEXSPI1PADCTL_COMPOK_SHIFT (24U)
+/*! COMPOK - FLEXSPI1 Pad Compensation Circuit Status
+ */
+#define SYSCTL0_FLEXSPI1PADCTL_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_COMPOK_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_COMPOK_MASK)
+/*! @} */
+
+/*! @name SDIO0PADCTL - SDIO0 Pad Control */
+/*! @{ */
+#define SYSCTL0_SDIO0PADCTL_RASRCN_MASK (0xFU)
+#define SYSCTL0_SDIO0PADCTL_RASRCN_SHIFT (0U)
+/*! RASRCN - Drives SDIO0 Pad Compensation Circuit
+ */
+#define SYSCTL0_SDIO0PADCTL_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_RASRCN_SHIFT)) & SYSCTL0_SDIO0PADCTL_RASRCN_MASK)
+#define SYSCTL0_SDIO0PADCTL_RASRCP_MASK (0xF0U)
+#define SYSCTL0_SDIO0PADCTL_RASRCP_SHIFT (4U)
+/*! RASRCP - Drives SDIO0 Pad Compensation Circuit
+ */
+#define SYSCTL0_SDIO0PADCTL_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_RASRCP_SHIFT)) & SYSCTL0_SDIO0PADCTL_RASRCP_MASK)
+#define SYSCTL0_SDIO0PADCTL_FASTFRZ_MASK (0x100U)
+#define SYSCTL0_SDIO0PADCTL_FASTFRZ_SHIFT (8U)
+/*! FASTFRZ - Drives SDIO0 Pad Compensation Circuit
+ */
+#define SYSCTL0_SDIO0PADCTL_FASTFRZ(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_FASTFRZ_SHIFT)) & SYSCTL0_SDIO0PADCTL_FASTFRZ_MASK)
+#define SYSCTL0_SDIO0PADCTL_FREEZE_MASK (0x200U)
+#define SYSCTL0_SDIO0PADCTL_FREEZE_SHIFT (9U)
+/*! FREEZE - Drives SDIO0 Pad Compensation Circuit
+ */
+#define SYSCTL0_SDIO0PADCTL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_FREEZE_SHIFT)) & SYSCTL0_SDIO0PADCTL_FREEZE_MASK)
+#define SYSCTL0_SDIO0PADCTL_COMPTQ_MASK (0x400U)
+#define SYSCTL0_SDIO0PADCTL_COMPTQ_SHIFT (10U)
+/*! COMPTQ - Drives SDIO0 Pad Compensation Circuit
+ */
+#define SYSCTL0_SDIO0PADCTL_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_COMPTQ_SHIFT)) & SYSCTL0_SDIO0PADCTL_COMPTQ_MASK)
+#define SYSCTL0_SDIO0PADCTL_COMPEN_MASK (0x800U)
+#define SYSCTL0_SDIO0PADCTL_COMPEN_SHIFT (11U)
+/*! COMPEN - Drives SDIO0 Pad Compensation Circuit
+ */
+#define SYSCTL0_SDIO0PADCTL_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_COMPEN_SHIFT)) & SYSCTL0_SDIO0PADCTL_COMPEN_MASK)
+#define SYSCTL0_SDIO0PADCTL_NASRCN_MASK (0xF0000U)
+#define SYSCTL0_SDIO0PADCTL_NASRCN_SHIFT (16U)
+/*! NASRCN - SDIO0 Pad Compensation Circuit Status
+ */
+#define SYSCTL0_SDIO0PADCTL_NASRCN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_NASRCN_SHIFT)) & SYSCTL0_SDIO0PADCTL_NASRCN_MASK)
+#define SYSCTL0_SDIO0PADCTL_NASRCP_MASK (0xF00000U)
+#define SYSCTL0_SDIO0PADCTL_NASRCP_SHIFT (20U)
+/*! NASRCP - SDIO0 Pad Compensation Circuit Status
+ */
+#define SYSCTL0_SDIO0PADCTL_NASRCP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_NASRCP_SHIFT)) & SYSCTL0_SDIO0PADCTL_NASRCP_MASK)
+#define SYSCTL0_SDIO0PADCTL_COMPOK_MASK (0x1000000U)
+#define SYSCTL0_SDIO0PADCTL_COMPOK_SHIFT (24U)
+/*! COMPOK - SDIO0 Pad Compensation Circuit Status
+ */
+#define SYSCTL0_SDIO0PADCTL_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_COMPOK_SHIFT)) & SYSCTL0_SDIO0PADCTL_COMPOK_MASK)
+/*! @} */
+
+/*! @name SDIO1PADCTL - SDIO1 Pad Control */
+/*! @{ */
+#define SYSCTL0_SDIO1PADCTL_RASRCN_MASK (0xFU)
+#define SYSCTL0_SDIO1PADCTL_RASRCN_SHIFT (0U)
+/*! RASRCN - Drives SDIO1 Pad Compensation Circuit
+ */
+#define SYSCTL0_SDIO1PADCTL_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_RASRCN_SHIFT)) & SYSCTL0_SDIO1PADCTL_RASRCN_MASK)
+#define SYSCTL0_SDIO1PADCTL_RASRCP_MASK (0xF0U)
+#define SYSCTL0_SDIO1PADCTL_RASRCP_SHIFT (4U)
+/*! RASRCP - Drives SDIO1 Pad Compensation Circuit
+ */
+#define SYSCTL0_SDIO1PADCTL_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_RASRCP_SHIFT)) & SYSCTL0_SDIO1PADCTL_RASRCP_MASK)
+#define SYSCTL0_SDIO1PADCTL_FASTFRZ_MASK (0x100U)
+#define SYSCTL0_SDIO1PADCTL_FASTFRZ_SHIFT (8U)
+/*! FASTFRZ - Drives SDIO1 Pad Compensation Circuit
+ */
+#define SYSCTL0_SDIO1PADCTL_FASTFRZ(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_FASTFRZ_SHIFT)) & SYSCTL0_SDIO1PADCTL_FASTFRZ_MASK)
+#define SYSCTL0_SDIO1PADCTL_FREEZE_MASK (0x200U)
+#define SYSCTL0_SDIO1PADCTL_FREEZE_SHIFT (9U)
+/*! FREEZE - Drives SDIO1 Pad Compensation Circuit
+ */
+#define SYSCTL0_SDIO1PADCTL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_FREEZE_SHIFT)) & SYSCTL0_SDIO1PADCTL_FREEZE_MASK)
+#define SYSCTL0_SDIO1PADCTL_COMPTQ_MASK (0x400U)
+#define SYSCTL0_SDIO1PADCTL_COMPTQ_SHIFT (10U)
+/*! COMPTQ - Drives SDIO1 Pad Compensation Circuit
+ */
+#define SYSCTL0_SDIO1PADCTL_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_COMPTQ_SHIFT)) & SYSCTL0_SDIO1PADCTL_COMPTQ_MASK)
+#define SYSCTL0_SDIO1PADCTL_COMPEN_MASK (0x800U)
+#define SYSCTL0_SDIO1PADCTL_COMPEN_SHIFT (11U)
+/*! COMPEN - Drives SDIO1 Pad Compensation Circuit
+ */
+#define SYSCTL0_SDIO1PADCTL_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_COMPEN_SHIFT)) & SYSCTL0_SDIO1PADCTL_COMPEN_MASK)
+#define SYSCTL0_SDIO1PADCTL_NASRCN_MASK (0xF0000U)
+#define SYSCTL0_SDIO1PADCTL_NASRCN_SHIFT (16U)
+/*! NASRCN - SDIO1 Pad Compensation Circuit Status
+ */
+#define SYSCTL0_SDIO1PADCTL_NASRCN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_NASRCN_SHIFT)) & SYSCTL0_SDIO1PADCTL_NASRCN_MASK)
+#define SYSCTL0_SDIO1PADCTL_NASRCP_MASK (0xF00000U)
+#define SYSCTL0_SDIO1PADCTL_NASRCP_SHIFT (20U)
+/*! NASRCP - SDIO1 Pad Compensation Circuit Status
+ */
+#define SYSCTL0_SDIO1PADCTL_NASRCP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_NASRCP_SHIFT)) & SYSCTL0_SDIO1PADCTL_NASRCP_MASK)
+#define SYSCTL0_SDIO1PADCTL_COMPOK_MASK (0x1000000U)
+#define SYSCTL0_SDIO1PADCTL_COMPOK_SHIFT (24U)
+/*! COMPOK - SDIO1 Pad Compensation Circuit Status
+ */
+#define SYSCTL0_SDIO1PADCTL_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_COMPOK_SHIFT)) & SYSCTL0_SDIO1PADCTL_COMPOK_MASK)
+/*! @} */
+
+/*! @name DICEHWREGN - Compound Device Identifier (CDI) */
+/*! @{ */
+#define SYSCTL0_DICEHWREGN_DICEHWREGN_MASK (0xFFFFFFFFU)
+#define SYSCTL0_DICEHWREGN_DICEHWREGN_SHIFT (0U)
+/*! DICEHWREGN - DICE General Purpose 32-Bit Data Register
+ */
+#define SYSCTL0_DICEHWREGN_DICEHWREGN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DICEHWREGN_DICEHWREGN_SHIFT)) & SYSCTL0_DICEHWREGN_DICEHWREGN_MASK)
+/*! @} */
+
+/*! @name UUID - UUID */
+/*! @{ */
+#define SYSCTL0_UUID_UUIDN_MASK (0xFFFFFFFFU)
+#define SYSCTL0_UUID_UUIDN_SHIFT (0U)
+/*! UUIDN - UUIDn 32-Bit Data Register
+ */
+#define SYSCTL0_UUID_UUIDN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_UUID_UUIDN_SHIFT)) & SYSCTL0_UUID_UUIDN_MASK)
+/*! @} */
+
+/* The count of SYSCTL0_UUID */
+#define SYSCTL0_UUID_COUNT (4U)
+
+/*! @name AESKEY_SRCSEL - AES Key Source Select */
+/*! @{ */
+#define SYSCTL0_AESKEY_SRCSEL_AESKEY_SRCSEL_MASK (0x3U)
+#define SYSCTL0_AESKEY_SRCSEL_AESKEY_SRCSEL_SHIFT (0U)
+/*! AESKEY_SRCSEL - AES Key Source Select
+ * 0b00..PUF
+ * 0b01..PUF
+ * 0b10..OTP
+ * 0b11..PUF
+ */
+#define SYSCTL0_AESKEY_SRCSEL_AESKEY_SRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AESKEY_SRCSEL_AESKEY_SRCSEL_SHIFT)) & SYSCTL0_AESKEY_SRCSEL_AESKEY_SRCSEL_MASK)
+/*! @} */
+
+/*! @name OTFADKEY_SRCSEL - OTFAD Key Source Select */
+/*! @{ */
+#define SYSCTL0_OTFADKEY_SRCSEL_OTFADKEY_SRCSEL_MASK (0x3U)
+#define SYSCTL0_OTFADKEY_SRCSEL_OTFADKEY_SRCSEL_SHIFT (0U)
+/*! OTFADKEY_SRCSEL - OTFAD Key Source Select
+ * 0b00..PUF
+ * 0b01..PUF
+ * 0b10..OTP
+ * 0b11..PUF
+ */
+#define SYSCTL0_OTFADKEY_SRCSEL_OTFADKEY_SRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_OTFADKEY_SRCSEL_OTFADKEY_SRCSEL_SHIFT)) & SYSCTL0_OTFADKEY_SRCSEL_OTFADKEY_SRCSEL_MASK)
+/*! @} */
+
+/*! @name HASHHWKEYDISABLE - HASH Hardware Key Disable */
+/*! @{ */
+#define SYSCTL0_HASHHWKEYDISABLE_HASHHWKEYDISABLE_MASK (0xFFFFFFFFU)
+#define SYSCTL0_HASHHWKEYDISABLE_HASHHWKEYDISABLE_SHIFT (0U)
+/*! HASHHWKEYDISABLE - HASH Hardware Key Disable
+ */
+#define SYSCTL0_HASHHWKEYDISABLE_HASHHWKEYDISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HASHHWKEYDISABLE_HASHHWKEYDISABLE_SHIFT)) & SYSCTL0_HASHHWKEYDISABLE_HASHHWKEYDISABLE_MASK)
+/*! @} */
+
+/*! @name DBG_LOCKEN - Debug Lock Enable */
+/*! @{ */
+#define SYSCTL0_DBG_LOCKEN_DBG_LOCKEN_MASK (0xFU)
+#define SYSCTL0_DBG_LOCKEN_DBG_LOCKEN_SHIFT (0U)
+/*! DBG_LOCKEN - Debug Write Lock the following registers
+ */
+#define SYSCTL0_DBG_LOCKEN_DBG_LOCKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_LOCKEN_DBG_LOCKEN_SHIFT)) & SYSCTL0_DBG_LOCKEN_DBG_LOCKEN_MASK)
+/*! @} */
+
+/*! @name DBG_FEATURES - Debug Features */
+/*! @{ */
+#define SYSCTL0_DBG_FEATURES_DBGEN1_MASK (0x3U)
+#define SYSCTL0_DBG_FEATURES_DBGEN1_SHIFT (0U)
+/*! DBGEN1 - CM33 Debug Enable Control
+ * 0b10..Enabled
+ * 0b01..Disabled
+ * 0b00..Disabled
+ * 0b11..Disabled
+ */
+#define SYSCTL0_DBG_FEATURES_DBGEN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_DBGEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_DBGEN1_MASK)
+#define SYSCTL0_DBG_FEATURES_NIDEN1_MASK (0xCU)
+#define SYSCTL0_DBG_FEATURES_NIDEN1_SHIFT (2U)
+/*! NIDEN1 - CM33 NID Enable Control
+ * 0b10..Enabled
+ * 0b01..Disabled
+ * 0b00..Disabled
+ * 0b11..Disabled
+ */
+#define SYSCTL0_DBG_FEATURES_NIDEN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_NIDEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_NIDEN1_MASK)
+#define SYSCTL0_DBG_FEATURES_SPIDEN1_MASK (0x30U)
+#define SYSCTL0_DBG_FEATURES_SPIDEN1_SHIFT (4U)
+/*! SPIDEN1 - CM33 SPID Enable Control
+ * 0b10..Enabled
+ * 0b01..Disabled
+ * 0b00..Disabled
+ * 0b11..Disabled
+ */
+#define SYSCTL0_DBG_FEATURES_SPIDEN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_SPIDEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_SPIDEN1_MASK)
+#define SYSCTL0_DBG_FEATURES_SPNIDEN1_MASK (0xC0U)
+#define SYSCTL0_DBG_FEATURES_SPNIDEN1_SHIFT (6U)
+/*! SPNIDEN1 - CM33 SPNIDEN Enable Control
+ * 0b10..Enabled
+ * 0b01..Disabled
+ * 0b00..Disabled
+ * 0b11..Disabled
+ */
+#define SYSCTL0_DBG_FEATURES_SPNIDEN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_SPNIDEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_SPNIDEN1_MASK)
+/*! @} */
+
+/*! @name DBG_FEATURES_DP - Debug Features Duplicate */
+/*! @{ */
+#define SYSCTL0_DBG_FEATURES_DP_DBGEN1_MASK (0x3U)
+#define SYSCTL0_DBG_FEATURES_DP_DBGEN1_SHIFT (0U)
+/*! DBGEN1 - CM33 Debug Enable Control
+ * 0b10..Enabled
+ * 0b01..Disabled
+ * 0b00..Disabled
+ * 0b11..Disabled
+ */
+#define SYSCTL0_DBG_FEATURES_DP_DBGEN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_DP_DBGEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_DP_DBGEN1_MASK)
+#define SYSCTL0_DBG_FEATURES_DP_NIDEN1_MASK (0xCU)
+#define SYSCTL0_DBG_FEATURES_DP_NIDEN1_SHIFT (2U)
+/*! NIDEN1 - CM33 NID Enable Control
+ * 0b10..Enabled
+ * 0b01..Disabled
+ * 0b00..Disabled
+ * 0b11..Disabled
+ */
+#define SYSCTL0_DBG_FEATURES_DP_NIDEN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_DP_NIDEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_DP_NIDEN1_MASK)
+#define SYSCTL0_DBG_FEATURES_DP_SPIDEN1_MASK (0x30U)
+#define SYSCTL0_DBG_FEATURES_DP_SPIDEN1_SHIFT (4U)
+/*! SPIDEN1 - CM33 SPID Enable Control
+ * 0b10..Enabled
+ * 0b01..Disabled
+ * 0b00..Disabled
+ * 0b11..Disabled
+ */
+#define SYSCTL0_DBG_FEATURES_DP_SPIDEN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_DP_SPIDEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_DP_SPIDEN1_MASK)
+#define SYSCTL0_DBG_FEATURES_DP_SPNIDEN1_MASK (0xC0U)
+#define SYSCTL0_DBG_FEATURES_DP_SPNIDEN1_SHIFT (6U)
+/*! SPNIDEN1 - CM33 SPNIDEN Enable Control
+ * 0b10..Enabled
+ * 0b01..Disabled
+ * 0b00..Disabled
+ * 0b11..Disabled
+ */
+#define SYSCTL0_DBG_FEATURES_DP_SPNIDEN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_DP_SPNIDEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_DP_SPNIDEN1_MASK)
+/*! @} */
+
+/*! @name CS_PROTCPU0 - Code Security for CPU0 */
+/*! @{ */
+#define SYSCTL0_CS_PROTCPU0_CS_PROTCPU0_MASK (0xFFFFFFFFU)
+#define SYSCTL0_CS_PROTCPU0_CS_PROTCPU0_SHIFT (0U)
+/*! CS_PROTCPU0 - Controls M33 AP Enable
+ */
+#define SYSCTL0_CS_PROTCPU0_CS_PROTCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CS_PROTCPU0_CS_PROTCPU0_SHIFT)) & SYSCTL0_CS_PROTCPU0_CS_PROTCPU0_MASK)
+/*! @} */
+
+/*! @name CS_PROTCPU1 - Code Security for CPU1 */
+/*! @{ */
+#define SYSCTL0_CS_PROTCPU1_CS_PROTCPU1_MASK (0xFFFFFFFFU)
+#define SYSCTL0_CS_PROTCPU1_CS_PROTCPU1_SHIFT (0U)
+/*! CS_PROTCPU1 - Controls AP Enable
+ */
+#define SYSCTL0_CS_PROTCPU1_CS_PROTCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CS_PROTCPU1_CS_PROTCPU1_SHIFT)) & SYSCTL0_CS_PROTCPU1_CS_PROTCPU1_MASK)
+/*! @} */
+
+/*! @name DBG_AUTH_SCRATCH - Debug authorization scratch */
+/*! @{ */
+#define SYSCTL0_DBG_AUTH_SCRATCH_DBG_AUTH_SCRATCH_MASK (0xFFFFFFFFU)
+#define SYSCTL0_DBG_AUTH_SCRATCH_DBG_AUTH_SCRATCH_SHIFT (0U)
+/*! DBG_AUTH_SCRATCH - Debug authorization scratch register for S/W.
+ */
+#define SYSCTL0_DBG_AUTH_SCRATCH_DBG_AUTH_SCRATCH(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_AUTH_SCRATCH_DBG_AUTH_SCRATCH_SHIFT)) & SYSCTL0_DBG_AUTH_SCRATCH_DBG_AUTH_SCRATCH_MASK)
+/*! @} */
+
+/*! @name KEY_BLOCK - Key block */
+/*! @{ */
+#define SYSCTL0_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU)
+#define SYSCTL0_KEY_BLOCK_KEY_BLOCK_SHIFT (0U)
+/*! KEY_BLOCK - PUF key and data output
+ */
+#define SYSCTL0_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCTL0_KEY_BLOCK_KEY_BLOCK_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SYSCTL0_Register_Masks */
+
+
+/* SYSCTL0 - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral SYSCTL0 base address */
+ #define SYSCTL0_BASE (0x50002000u)
+ /** Peripheral SYSCTL0 base address */
+ #define SYSCTL0_BASE_NS (0x40002000u)
+ /** Peripheral SYSCTL0 base pointer */
+ #define SYSCTL0 ((SYSCTL0_Type *)SYSCTL0_BASE)
+ /** Peripheral SYSCTL0 base pointer */
+ #define SYSCTL0_NS ((SYSCTL0_Type *)SYSCTL0_BASE_NS)
+ /** Array initializer of SYSCTL0 peripheral base addresses */
+ #define SYSCTL0_BASE_ADDRS { SYSCTL0_BASE }
+ /** Array initializer of SYSCTL0 peripheral base pointers */
+ #define SYSCTL0_BASE_PTRS { SYSCTL0 }
+ /** Array initializer of SYSCTL0 peripheral base addresses */
+ #define SYSCTL0_BASE_ADDRS_NS { SYSCTL0_BASE_NS }
+ /** Array initializer of SYSCTL0 peripheral base pointers */
+ #define SYSCTL0_BASE_PTRS_NS { SYSCTL0_NS }
+#else
+ /** Peripheral SYSCTL0 base address */
+ #define SYSCTL0_BASE (0x40002000u)
+ /** Peripheral SYSCTL0 base pointer */
+ #define SYSCTL0 ((SYSCTL0_Type *)SYSCTL0_BASE)
+ /** Array initializer of SYSCTL0 peripheral base addresses */
+ #define SYSCTL0_BASE_ADDRS { SYSCTL0_BASE }
+ /** Array initializer of SYSCTL0 peripheral base pointers */
+ #define SYSCTL0_BASE_PTRS { SYSCTL0 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group SYSCTL0_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SYSCTL1 Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCTL1_Peripheral_Access_Layer SYSCTL1 Peripheral Access Layer
+ * @{
+ */
+
+/** SYSCTL1 - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t UPDATELCKOUT; /**< Update Clock Lockout, offset: 0x0 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t MCLKPINDIR; /**< MCLK direction control, offset: 0x10 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t DSPNMISRCSEL; /**< DSP NMI source selection, offset: 0x30 */
+ uint8_t RESERVED_2[12];
+ __IO uint32_t FCCTRLSEL[14]; /**< Flexcomm control selection, array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_3[8];
+ __IO uint32_t SHAREDCTRLSET[2]; /**< Shared control set, array offset: 0x80, array step: 0x4 */
+ uint8_t RESERVED_4[376];
+ __O uint32_t RXEVPULSEGEN; /**< RX Event Pulse Generator, offset: 0x200 */
+} SYSCTL1_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SYSCTL1 Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCTL1_Register_Masks SYSCTL1 Register Masks
+ * @{
+ */
+
+/*! @name UPDATELCKOUT - Update Clock Lockout */
+/*! @{ */
+#define SYSCTL1_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U)
+#define SYSCTL1_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U)
+/*! UPDATELCKOUT - Update Clock Lockout
+ * 0b0..Normal Mode
+ * 0b1..Protected Mode. Cannot be written to. Currently this register does not lock anything
+ */
+#define SYSCTL1_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL1_UPDATELCKOUT_UPDATELCKOUT_MASK)
+/*! @} */
+
+/*! @name MCLKPINDIR - MCLK direction control */
+/*! @{ */
+#define SYSCTL1_MCLKPINDIR_MCLKPINDIR_MASK (0x1U)
+#define SYSCTL1_MCLKPINDIR_MCLKPINDIR_SHIFT (0U)
+/*! MCLKPINDIR - MCLK direction control
+ * 0b0..I2S MCLK is in input direction
+ * 0b1..I2S MCLK is in the output direction
+ */
+#define SYSCTL1_MCLKPINDIR_MCLKPINDIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_MCLKPINDIR_MCLKPINDIR_SHIFT)) & SYSCTL1_MCLKPINDIR_MCLKPINDIR_MASK)
+/*! @} */
+
+/*! @name DSPNMISRCSEL - DSP NMI source selection */
+/*! @{ */
+#define SYSCTL1_DSPNMISRCSEL_NMISRCSEL_MASK (0x1FU)
+#define SYSCTL1_DSPNMISRCSEL_NMISRCSEL_SHIFT (0U)
+/*! NMISRCSEL - DSP NMI source selection
+ */
+#define SYSCTL1_DSPNMISRCSEL_NMISRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_DSPNMISRCSEL_NMISRCSEL_SHIFT)) & SYSCTL1_DSPNMISRCSEL_NMISRCSEL_MASK)
+#define SYSCTL1_DSPNMISRCSEL_NMIEN_MASK (0x80000000U)
+#define SYSCTL1_DSPNMISRCSEL_NMIEN_SHIFT (31U)
+/*! NMIEN - NMI Enable
+ * 0b0..Disable NMI Interrupt
+ * 0b1..Enable NMI Interrupt
+ */
+#define SYSCTL1_DSPNMISRCSEL_NMIEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_DSPNMISRCSEL_NMIEN_SHIFT)) & SYSCTL1_DSPNMISRCSEL_NMIEN_MASK)
+/*! @} */
+
+/*! @name FCCTRLSEL - Flexcomm control selection */
+/*! @{ */
+#define SYSCTL1_FCCTRLSEL_SCKINSEL_MASK (0x3U)
+#define SYSCTL1_FCCTRLSEL_SCKINSEL_SHIFT (0U)
+/*! SCKINSEL - SCK IN Select
+ * 0b00..Original FLEXCOMM I2S signals
+ * 0b01..Shared Set0 I2S signals
+ * 0b10..Shared Set1 I2S signals
+ * 0b11..Reserved
+ */
+#define SYSCTL1_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL1_FCCTRLSEL_SCKINSEL_MASK)
+#define SYSCTL1_FCCTRLSEL_WSINSEL_MASK (0x300U)
+#define SYSCTL1_FCCTRLSEL_WSINSEL_SHIFT (8U)
+/*! WSINSEL - SCK IN Select
+ * 0b00..Original FLEXCOMM I2S signals
+ * 0b01..Shared Set0 I2S signals
+ * 0b10..Shared Set1 I2S signals
+ * 0b11..Reserved
+ */
+#define SYSCTL1_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL1_FCCTRLSEL_WSINSEL_MASK)
+#define SYSCTL1_FCCTRLSEL_DATAINSEL_MASK (0x30000U)
+#define SYSCTL1_FCCTRLSEL_DATAINSEL_SHIFT (16U)
+/*! DATAINSEL - DATA IN Select
+ * 0b00..Original FLEXCOMM I2S signals
+ * 0b01..Shared Set0 I2S signals
+ * 0b10..Shared Set1 I2S signals
+ * 0b11..Reserved
+ */
+#define SYSCTL1_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL1_FCCTRLSEL_DATAINSEL_MASK)
+#define SYSCTL1_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U)
+#define SYSCTL1_FCCTRLSEL_DATAOUTSEL_SHIFT (24U)
+/*! DATAOUTSEL - DATA OUT Select
+ * 0b00..Original FLEXCOMM I2S signals
+ * 0b01..Shared Set0 I2S signals
+ * 0b10..Shared Set1 I2S signals
+ * 0b11..Reserved
+ */
+#define SYSCTL1_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL1_FCCTRLSEL_DATAOUTSEL_MASK)
+/*! @} */
+
+/* The count of SYSCTL1_FCCTRLSEL */
+#define SYSCTL1_FCCTRLSEL_COUNT (14U)
+
+/*! @name SHAREDCTRLSET - Shared control set */
+/*! @{ */
+#define SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U)
+#define SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U)
+/*! SHAREDSCKSEL - Shared SCK Select
+ * 0b000..FLEXCOMM0
+ * 0b001..FLEXCOMM1
+ * 0b010..FLEXCOMM2
+ * 0b011..FLEXCOMM3
+ * 0b100..FLEXCOMM4
+ * 0b101..FLEXCOMM5
+ * 0b110..FLEXCOMM6
+ * 0b111..FLEXCOMM7
+ */
+#define SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL_MASK)
+#define SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U)
+#define SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U)
+/*! SHAREDWSSEL - Shared WS Select:
+ * 0b000..FLEXCOMM0
+ * 0b001..FLEXCOMM1
+ * 0b010..FLEXCOMM2
+ * 0b011..FLEXCOMM3
+ * 0b100..FLEXCOMM4
+ * 0b101..FLEXCOMM5
+ * 0b110..FLEXCOMM6
+ * 0b111..FLEXCOMM7
+ */
+#define SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL_MASK)
+#define SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U)
+#define SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U)
+/*! SHAREDDATASEL - Shared DATA Select:
+ * 0b000..FLEXCOMM0
+ * 0b001..FLEXCOMM1
+ * 0b010..FLEXCOMM2
+ * 0b011..FLEXCOMM3
+ * 0b100..FLEXCOMM4
+ * 0b101..FLEXCOMM5
+ * 0b110..FLEXCOMM6
+ * 0b111..FLEXCOMM7
+ */
+#define SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL_MASK)
+#define SYSCTL1_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U)
+#define SYSCTL1_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U)
+/*! FC0DATAOUTEN - FLEXCOMM0 DATAOUT Output Enable:
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define SYSCTL1_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC0DATAOUTEN_MASK)
+#define SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U)
+#define SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U)
+/*! FC1DATAOUTEN - FLEXCOMM1 DATAOUT Output Enable:
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN_MASK)
+#define SYSCTL1_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U)
+#define SYSCTL1_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U)
+/*! FC2DATAOUTEN - FLEXCOMM2 DATAOUT Output Enable:
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define SYSCTL1_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC2DATAOUTEN_MASK)
+#define SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN_MASK (0x80000U)
+#define SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT (19U)
+/*! FC3DATAOUTEN - FLEXCOMM3 DATAOUT Output Enable:
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN_MASK)
+#define SYSCTL1_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U)
+#define SYSCTL1_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U)
+/*! FC4DATAOUTEN - FLEXCOMM4 DATAOUT Output Enable:
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define SYSCTL1_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC4DATAOUTEN_MASK)
+#define SYSCTL1_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U)
+#define SYSCTL1_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U)
+/*! FC5DATAOUTEN - FLEXCOMM5 DATAOUT Output Enable:
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define SYSCTL1_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC5DATAOUTEN_MASK)
+#define SYSCTL1_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U)
+#define SYSCTL1_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U)
+/*! FC6DATAOUTEN - FLEXCOMM6 DATAOUT Output Enable:
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define SYSCTL1_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC6DATAOUTEN_MASK)
+#define SYSCTL1_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U)
+#define SYSCTL1_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U)
+/*! FC7DATAOUTEN - FLEXCOMM7 DATAOUT Output Enable:
+ * 0b0..Input
+ * 0b1..Output
+ */
+#define SYSCTL1_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC7DATAOUTEN_MASK)
+/*! @} */
+
+/* The count of SYSCTL1_SHAREDCTRLSET */
+#define SYSCTL1_SHAREDCTRLSET_COUNT (2U)
+
+/*! @name RXEVPULSEGEN - RX Event Pulse Generator */
+/*! @{ */
+#define SYSCTL1_RXEVPULSEGEN_RXEVPULSEGEN_MASK (0x1U)
+#define SYSCTL1_RXEVPULSEGEN_RXEVPULSEGEN_SHIFT (0U)
+/*! RXEVPULSEGEN - RX Event Pulse Generator
+ * 0b0..No effect
+ * 0b1..Pulse RXEV High for one PSCLK cycle
+ */
+#define SYSCTL1_RXEVPULSEGEN_RXEVPULSEGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_RXEVPULSEGEN_RXEVPULSEGEN_SHIFT)) & SYSCTL1_RXEVPULSEGEN_RXEVPULSEGEN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SYSCTL1_Register_Masks */
+
+
+/* SYSCTL1 - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral SYSCTL1 base address */
+ #define SYSCTL1_BASE (0x50022000u)
+ /** Peripheral SYSCTL1 base address */
+ #define SYSCTL1_BASE_NS (0x40022000u)
+ /** Peripheral SYSCTL1 base pointer */
+ #define SYSCTL1 ((SYSCTL1_Type *)SYSCTL1_BASE)
+ /** Peripheral SYSCTL1 base pointer */
+ #define SYSCTL1_NS ((SYSCTL1_Type *)SYSCTL1_BASE_NS)
+ /** Array initializer of SYSCTL1 peripheral base addresses */
+ #define SYSCTL1_BASE_ADDRS { SYSCTL1_BASE }
+ /** Array initializer of SYSCTL1 peripheral base pointers */
+ #define SYSCTL1_BASE_PTRS { SYSCTL1 }
+ /** Array initializer of SYSCTL1 peripheral base addresses */
+ #define SYSCTL1_BASE_ADDRS_NS { SYSCTL1_BASE_NS }
+ /** Array initializer of SYSCTL1 peripheral base pointers */
+ #define SYSCTL1_BASE_PTRS_NS { SYSCTL1_NS }
+#else
+ /** Peripheral SYSCTL1 base address */
+ #define SYSCTL1_BASE (0x40022000u)
+ /** Peripheral SYSCTL1 base pointer */
+ #define SYSCTL1 ((SYSCTL1_Type *)SYSCTL1_BASE)
+ /** Array initializer of SYSCTL1 peripheral base addresses */
+ #define SYSCTL1_BASE_ADDRS { SYSCTL1_BASE }
+ /** Array initializer of SYSCTL1 peripheral base pointers */
+ #define SYSCTL1_BASE_PTRS { SYSCTL1 }
+#endif
+
+/*!
+ * @}
+ */ /* end of group SYSCTL1_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TRNG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
+ * @{
+ */
+
+/** TRNG - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */
+ __IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */
+ __IO uint32_t PKRRNG; /**< Poker Range Register, offset: 0x8 */
+ union { /* offset: 0xC */
+ __IO uint32_t PKRMAX; /**< Poker Maximum Limit Register, offset: 0xC */
+ __I uint32_t PKRSQ; /**< Poker Square Calculation Result Register, offset: 0xC */
+ };
+ __IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */
+ union { /* offset: 0x14 */
+ __IO uint32_t SBLIM; /**< Sparse Bit Limit Register, offset: 0x14 */
+ __I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */
+ };
+ __IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */
+ union { /* offset: 0x1C */
+ __I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */
+ __IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */
+ };
+ union { /* offset: 0x20 */
+ __I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */
+ __IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */
+ };
+ union { /* offset: 0x24 */
+ __I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */
+ __IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */
+ };
+ union { /* offset: 0x28 */
+ __I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */
+ __IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */
+ };
+ union { /* offset: 0x2C */
+ __I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */
+ __IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */
+ };
+ union { /* offset: 0x30 */
+ __I uint32_t SCR4C; /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */
+ __IO uint32_t SCR4L; /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */
+ };
+ union { /* offset: 0x34 */
+ __I uint32_t SCR5C; /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */
+ __IO uint32_t SCR5L; /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */
+ };
+ union { /* offset: 0x38 */
+ __I uint32_t SCR6PC; /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */
+ __IO uint32_t SCR6PL; /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */
+ };
+ __I uint32_t STATUS; /**< Status Register, offset: 0x3C */
+ __I uint32_t ENT[16]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */
+ __I uint32_t PKRCNT10; /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */
+ __I uint32_t PKRCNT32; /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */
+ __I uint32_t PKRCNT54; /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */
+ __I uint32_t PKRCNT76; /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */
+ __I uint32_t PKRCNT98; /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */
+ __I uint32_t PKRCNTBA; /**< Statistical Check Poker Count B and A Register, offset: 0x94 */
+ __I uint32_t PKRCNTDC; /**< Statistical Check Poker Count D and C Register, offset: 0x98 */
+ __I uint32_t PKRCNTFE; /**< Statistical Check Poker Count F and E Register, offset: 0x9C */
+ __IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */
+ __IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */
+ __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */
+ __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */
+ uint8_t RESERVED_0[64];
+ __I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */
+ __I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */
+} TRNG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TRNG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRNG_Register_Masks TRNG Register Masks
+ * @{
+ */
+
+/*! @name MCTL - Miscellaneous Control Register */
+/*! @{ */
+#define TRNG_MCTL_SAMP_MODE_MASK (0x3U)
+#define TRNG_MCTL_SAMP_MODE_SHIFT (0U)
+/*! SAMP_MODE
+ * 0b00..use Von Neumann data into both Entropy shifter and Statistical Checker
+ * 0b01..use raw data into both Entropy shifter and Statistical Checker
+ * 0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker
+ * 0b11..undefined/reserved.
+ */
+#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
+#define TRNG_MCTL_OSC_DIV_MASK (0xCU)
+#define TRNG_MCTL_OSC_DIV_SHIFT (2U)
+/*! OSC_DIV
+ * 0b00..use ring oscillator with no divide
+ * 0b01..use ring oscillator divided-by-2
+ * 0b10..use ring oscillator divided-by-4
+ * 0b11..use ring oscillator divided-by-8
+ */
+#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
+#define TRNG_MCTL_UNUSED4_MASK (0x10U)
+#define TRNG_MCTL_UNUSED4_SHIFT (4U)
+#define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)
+#define TRNG_MCTL_TRNG_ACC_MASK (0x20U)
+#define TRNG_MCTL_TRNG_ACC_SHIFT (5U)
+#define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)
+#define TRNG_MCTL_RST_DEF_MASK (0x40U)
+#define TRNG_MCTL_RST_DEF_SHIFT (6U)
+#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
+#define TRNG_MCTL_FOR_SCLK_MASK (0x80U)
+#define TRNG_MCTL_FOR_SCLK_SHIFT (7U)
+#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
+#define TRNG_MCTL_FCT_FAIL_MASK (0x100U)
+#define TRNG_MCTL_FCT_FAIL_SHIFT (8U)
+#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
+#define TRNG_MCTL_FCT_VAL_MASK (0x200U)
+#define TRNG_MCTL_FCT_VAL_SHIFT (9U)
+#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
+#define TRNG_MCTL_ENT_VAL_MASK (0x400U)
+#define TRNG_MCTL_ENT_VAL_SHIFT (10U)
+#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
+#define TRNG_MCTL_TST_OUT_MASK (0x800U)
+#define TRNG_MCTL_TST_OUT_SHIFT (11U)
+#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
+#define TRNG_MCTL_ERR_MASK (0x1000U)
+#define TRNG_MCTL_ERR_SHIFT (12U)
+#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
+#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
+#define TRNG_MCTL_TSTOP_OK_SHIFT (13U)
+#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
+#define TRNG_MCTL_PRGM_MASK (0x10000U)
+#define TRNG_MCTL_PRGM_SHIFT (16U)
+#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
+/*! @} */
+
+/*! @name SCMISC - Statistical Check Miscellaneous Register */
+/*! @{ */
+#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
+#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
+#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
+#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
+#define TRNG_SCMISC_RTY_CT_SHIFT (16U)
+#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
+/*! @} */
+
+/*! @name PKRRNG - Poker Range Register */
+/*! @{ */
+#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)
+#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U)
+#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
+/*! @} */
+
+/*! @name PKRMAX - Poker Maximum Limit Register */
+/*! @{ */
+#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)
+#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U)
+/*! PKR_MAX - Poker Maximum Limit.
+ */
+#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
+/*! @} */
+
+/*! @name PKRSQ - Poker Square Calculation Result Register */
+/*! @{ */
+#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)
+#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U)
+/*! PKR_SQ - Poker Square Calculation Result.
+ */
+#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
+/*! @} */
+
+/*! @name SDCTL - Seed Control Register */
+/*! @{ */
+#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
+#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
+#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
+#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
+#define TRNG_SDCTL_ENT_DLY_SHIFT (16U)
+#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
+/*! @} */
+
+/*! @name SBLIM - Sparse Bit Limit Register */
+/*! @{ */
+#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU)
+#define TRNG_SBLIM_SB_LIM_SHIFT (0U)
+#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
+/*! @} */
+
+/*! @name TOTSAM - Total Samples Register */
+/*! @{ */
+#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
+#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
+#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
+/*! @} */
+
+/*! @name FRQMIN - Frequency Count Minimum Limit Register */
+/*! @{ */
+#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
+#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
+#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
+/*! @} */
+
+/*! @name FRQCNT - Frequency Count Register */
+/*! @{ */
+#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
+#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
+#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
+/*! @} */
+
+/*! @name FRQMAX - Frequency Count Maximum Limit Register */
+/*! @{ */
+#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
+#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
+#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
+/*! @} */
+
+/*! @name SCMC - Statistical Check Monobit Count Register */
+/*! @{ */
+#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
+#define TRNG_SCMC_MONO_CT_SHIFT (0U)
+#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
+/*! @} */
+
+/*! @name SCML - Statistical Check Monobit Limit Register */
+/*! @{ */
+#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
+#define TRNG_SCML_MONO_MAX_SHIFT (0U)
+#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
+#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
+#define TRNG_SCML_MONO_RNG_SHIFT (16U)
+#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
+/*! @} */
+
+/*! @name SCR1C - Statistical Check Run Length 1 Count Register */
+/*! @{ */
+#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
+#define TRNG_SCR1C_R1_0_CT_SHIFT (0U)
+#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
+#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
+#define TRNG_SCR1C_R1_1_CT_SHIFT (16U)
+#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */
+/*! @{ */
+#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
+#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
+#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
+#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
+#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
+#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
+/*! @} */
+
+/*! @name SCR2C - Statistical Check Run Length 2 Count Register */
+/*! @{ */
+#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
+#define TRNG_SCR2C_R2_0_CT_SHIFT (0U)
+#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
+#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
+#define TRNG_SCR2C_R2_1_CT_SHIFT (16U)
+#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */
+/*! @{ */
+#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
+#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
+#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
+#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
+#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
+#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
+/*! @} */
+
+/*! @name SCR3C - Statistical Check Run Length 3 Count Register */
+/*! @{ */
+#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
+#define TRNG_SCR3C_R3_0_CT_SHIFT (0U)
+#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
+#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
+#define TRNG_SCR3C_R3_1_CT_SHIFT (16U)
+#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */
+/*! @{ */
+#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
+#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
+#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
+#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
+#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
+#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
+/*! @} */
+
+/*! @name SCR4C - Statistical Check Run Length 4 Count Register */
+/*! @{ */
+#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)
+#define TRNG_SCR4C_R4_0_CT_SHIFT (0U)
+#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
+#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)
+#define TRNG_SCR4C_R4_1_CT_SHIFT (16U)
+#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */
+/*! @{ */
+#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)
+#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U)
+#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
+#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)
+#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U)
+#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
+/*! @} */
+
+/*! @name SCR5C - Statistical Check Run Length 5 Count Register */
+/*! @{ */
+#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)
+#define TRNG_SCR5C_R5_0_CT_SHIFT (0U)
+#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
+#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)
+#define TRNG_SCR5C_R5_1_CT_SHIFT (16U)
+#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */
+/*! @{ */
+#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)
+#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U)
+#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
+#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)
+#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U)
+#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
+/*! @} */
+
+/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */
+/*! @{ */
+#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)
+#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)
+#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
+#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)
+#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)
+#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */
+/*! @{ */
+#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)
+#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)
+#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
+#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
+#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)
+#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
+/*! @} */
+
+/*! @name STATUS - Status Register */
+/*! @{ */
+#define TRNG_STATUS_TF1BR0_MASK (0x1U)
+#define TRNG_STATUS_TF1BR0_SHIFT (0U)
+#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
+#define TRNG_STATUS_TF1BR1_MASK (0x2U)
+#define TRNG_STATUS_TF1BR1_SHIFT (1U)
+#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
+#define TRNG_STATUS_TF2BR0_MASK (0x4U)
+#define TRNG_STATUS_TF2BR0_SHIFT (2U)
+#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
+#define TRNG_STATUS_TF2BR1_MASK (0x8U)
+#define TRNG_STATUS_TF2BR1_SHIFT (3U)
+#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
+#define TRNG_STATUS_TF3BR0_MASK (0x10U)
+#define TRNG_STATUS_TF3BR0_SHIFT (4U)
+#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
+#define TRNG_STATUS_TF3BR1_MASK (0x20U)
+#define TRNG_STATUS_TF3BR1_SHIFT (5U)
+#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
+#define TRNG_STATUS_TF4BR0_MASK (0x40U)
+#define TRNG_STATUS_TF4BR0_SHIFT (6U)
+#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
+#define TRNG_STATUS_TF4BR1_MASK (0x80U)
+#define TRNG_STATUS_TF4BR1_SHIFT (7U)
+#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
+#define TRNG_STATUS_TF5BR0_MASK (0x100U)
+#define TRNG_STATUS_TF5BR0_SHIFT (8U)
+#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
+#define TRNG_STATUS_TF5BR1_MASK (0x200U)
+#define TRNG_STATUS_TF5BR1_SHIFT (9U)
+#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
+#define TRNG_STATUS_TF6PBR0_MASK (0x400U)
+#define TRNG_STATUS_TF6PBR0_SHIFT (10U)
+#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
+#define TRNG_STATUS_TF6PBR1_MASK (0x800U)
+#define TRNG_STATUS_TF6PBR1_SHIFT (11U)
+#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
+#define TRNG_STATUS_TFSB_MASK (0x1000U)
+#define TRNG_STATUS_TFSB_SHIFT (12U)
+#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
+#define TRNG_STATUS_TFLR_MASK (0x2000U)
+#define TRNG_STATUS_TFLR_SHIFT (13U)
+#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
+#define TRNG_STATUS_TFP_MASK (0x4000U)
+#define TRNG_STATUS_TFP_SHIFT (14U)
+#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
+#define TRNG_STATUS_TFMB_MASK (0x8000U)
+#define TRNG_STATUS_TFMB_SHIFT (15U)
+#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
+#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
+#define TRNG_STATUS_RETRY_CT_SHIFT (16U)
+#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
+/*! @} */
+
+/*! @name ENT - Entropy Read Register */
+/*! @{ */
+#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
+#define TRNG_ENT_ENT_SHIFT (0U)
+#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
+/*! @} */
+
+/* The count of TRNG_ENT */
+#define TRNG_ENT_COUNT (16U)
+
+/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */
+/*! @{ */
+#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)
+#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)
+#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
+#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)
+#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)
+#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */
+/*! @{ */
+#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)
+#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)
+#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
+#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)
+#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)
+#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */
+/*! @{ */
+#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)
+#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)
+#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
+#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)
+#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)
+#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */
+/*! @{ */
+#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)
+#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)
+#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
+#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)
+#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)
+#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */
+/*! @{ */
+#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)
+#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)
+#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
+#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)
+#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)
+#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */
+/*! @{ */
+#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)
+#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)
+#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
+#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)
+#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)
+#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */
+/*! @{ */
+#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)
+#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)
+#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
+#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)
+#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)
+#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */
+/*! @{ */
+#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)
+#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)
+#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
+#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)
+#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)
+#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
+/*! @} */
+
+/*! @name SEC_CFG - Security Configuration Register */
+/*! @{ */
+#define TRNG_SEC_CFG_UNUSED0_MASK (0x1U)
+#define TRNG_SEC_CFG_UNUSED0_SHIFT (0U)
+#define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)
+#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
+#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
+/*! NO_PRGM
+ * 0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit.
+ * 0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming.
+ */
+#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
+#define TRNG_SEC_CFG_UNUSED2_MASK (0x4U)
+#define TRNG_SEC_CFG_UNUSED2_SHIFT (2U)
+#define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)
+/*! @} */
+
+/*! @name INT_CTRL - Interrupt Control Register */
+/*! @{ */
+#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
+#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
+/*! HW_ERR
+ * 0b0..Corresponding bit of INT_STATUS register cleared.
+ * 0b1..Corresponding bit of INT_STATUS register active.
+ */
+#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
+#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
+#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
+/*! ENT_VAL
+ * 0b0..Same behavior as bit 0 of this register.
+ * 0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
+#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
+#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
+/*! FRQ_CT_FAIL
+ * 0b0..Same behavior as bit 0 of this register.
+ * 0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
+#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
+#define TRNG_INT_CTRL_UNUSED_SHIFT (3U)
+#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
+/*! @} */
+
+/*! @name INT_MASK - Mask Register */
+/*! @{ */
+#define TRNG_INT_MASK_HW_ERR_MASK (0x1U)
+#define TRNG_INT_MASK_HW_ERR_SHIFT (0U)
+/*! HW_ERR
+ * 0b0..Corresponding interrupt of INT_STATUS is masked.
+ * 0b1..Corresponding bit of INT_STATUS is active.
+ */
+#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
+#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
+#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
+/*! ENT_VAL
+ * 0b0..Same behavior as bit 0 of this register.
+ * 0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
+#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
+#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
+/*! FRQ_CT_FAIL
+ * 0b0..Same behavior as bit 0 of this register.
+ * 0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
+/*! @} */
+
+/*! @name INT_STATUS - Interrupt Status Register */
+/*! @{ */
+#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
+#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
+/*! HW_ERR
+ * 0b0..no error
+ * 0b1..error detected.
+ */
+#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
+#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
+#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
+/*! ENT_VAL
+ * 0b0..Busy generation entropy. Any value read is invalid.
+ * 0b1..TRNG can be stopped and entropy is valid if read.
+ */
+#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
+#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
+#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
+/*! FRQ_CT_FAIL
+ * 0b0..No hardware nor self test frequency errors.
+ * 0b1..The frequency counter has detected a failure.
+ */
+#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
+/*! @} */
+
+/*! @name VID1 - Version ID Register (MS) */
+/*! @{ */
+#define TRNG_VID1_MIN_REV_MASK (0xFFU)
+#define TRNG_VID1_MIN_REV_SHIFT (0U)
+/*! MIN_REV
+ * 0b00000100..Minor revision number for TRNG.
+ */
+#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
+#define TRNG_VID1_MAJ_REV_MASK (0xFF00U)
+#define TRNG_VID1_MAJ_REV_SHIFT (8U)
+/*! MAJ_REV
+ * 0b00000001..Major revision number for TRNG.
+ */
+#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
+#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U)
+#define TRNG_VID1_IP_ID_SHIFT (16U)
+/*! IP_ID
+ * 0b0000000000110000..ID for TRNG.
+ */
+#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
+/*! @} */
+
+/*! @name VID2 - Version ID Register (LS) */
+/*! @{ */
+#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU)
+#define TRNG_VID2_CONFIG_OPT_SHIFT (0U)
+/*! CONFIG_OPT
+ * 0b00000000..TRNG_CONFIG_OPT for TRNG.
+ */
+#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
+#define TRNG_VID2_ECO_REV_MASK (0xFF00U)
+#define TRNG_VID2_ECO_REV_SHIFT (8U)
+/*! ECO_REV
+ * 0b00000000..TRNG_ECO_REV for TRNG.
+ */
+#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
+#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U)
+#define TRNG_VID2_INTG_OPT_SHIFT (16U)
+/*! INTG_OPT
+ * 0b00000000..INTG_OPT for TRNG.
+ */
+#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
+#define TRNG_VID2_ERA_MASK (0xFF000000U)
+#define TRNG_VID2_ERA_SHIFT (24U)
+/*! ERA
+ * 0b00000000..COMPILE_OPT for TRNG.
+ */
+#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group TRNG_Register_Masks */
+
+
+/* TRNG - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral TRNG base address */
+ #define TRNG_BASE (0x50138000u)
+ /** Peripheral TRNG base address */
+ #define TRNG_BASE_NS (0x40138000u)
+ /** Peripheral TRNG base pointer */
+ #define TRNG ((TRNG_Type *)TRNG_BASE)
+ /** Peripheral TRNG base pointer */
+ #define TRNG_NS ((TRNG_Type *)TRNG_BASE_NS)
+ /** Array initializer of TRNG peripheral base addresses */
+ #define TRNG_BASE_ADDRS { TRNG_BASE }
+ /** Array initializer of TRNG peripheral base pointers */
+ #define TRNG_BASE_PTRS { TRNG }
+ /** Array initializer of TRNG peripheral base addresses */
+ #define TRNG_BASE_ADDRS_NS { TRNG_BASE_NS }
+ /** Array initializer of TRNG peripheral base pointers */
+ #define TRNG_BASE_PTRS_NS { TRNG_NS }
+#else
+ /** Peripheral TRNG base address */
+ #define TRNG_BASE (0x40138000u)
+ /** Peripheral TRNG base pointer */
+ #define TRNG ((TRNG_Type *)TRNG_BASE)
+ /** Array initializer of TRNG peripheral base addresses */
+ #define TRNG_BASE_ADDRS { TRNG_BASE }
+ /** Array initializer of TRNG peripheral base pointers */
+ #define TRNG_BASE_PTRS { TRNG }
+#endif
+/** Interrupt vectors for the TRNG peripheral type */
+#define TRNG_IRQS { RNG_IRQn }
+/** Backward compatibility macros */
+#define TRNG0 TRNG
+
+
+/*!
+ * @}
+ */ /* end of group TRNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
+ * @{
+ */
+
+/** USART - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CFG; /**< USART Configuration, offset: 0x0 */
+ __IO uint32_t CTL; /**< USART Control, offset: 0x4 */
+ __IO uint32_t STAT; /**< USART Status, offset: 0x8 */
+ __IO uint32_t INTENSET; /**< Interrupt Enable Read and Set for USART (not FIFO) Status, offset: 0xC */
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear, offset: 0x10 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t BRG; /**< Baud Rate Generator, offset: 0x20 */
+ __I uint32_t INTSTAT; /**< Interrupt Status, offset: 0x24 */
+ __IO uint32_t OSR; /**< Oversample Selection Register for Asynchronous Communication, offset: 0x28 */
+ __IO uint32_t ADDR; /**< Address Register for Automatic Address Matching, offset: 0x2C */
+ uint8_t RESERVED_1[3536];
+ __IO uint32_t FIFOCFG; /**< FIFO Configuration, offset: 0xE00 */
+ __IO uint32_t FIFOSTAT; /**< FIFO Status, offset: 0xE04 */
+ __IO uint32_t FIFOTRIG; /**< FIFO Trigger Settings for Interrupt and DMA Request, offset: 0xE08 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t FIFOINTENSET; /**< FIFO Interrupt Enable, offset: 0xE10 */
+ __IO uint32_t FIFOINTENCLR; /**< FIFO Interrupt Enable Clear, offset: 0xE14 */
+ __I uint32_t FIFOINTSTAT; /**< FIFO Interrupt Status, offset: 0xE18 */
+ uint8_t RESERVED_3[4];
+ __O uint32_t FIFOWR; /**< FIFO Write Data, offset: 0xE20 */
+ uint8_t RESERVED_4[12];
+ __I uint32_t FIFORD; /**< FIFO Read Data, offset: 0xE30 */
+ uint8_t RESERVED_5[12];
+ __I uint32_t FIFORDNOPOP; /**< FIFO Data Read with No FIFO Pop, offset: 0xE40 */
+ uint8_t RESERVED_6[4];
+ __I uint32_t FIFOSIZE; /**< FIFO Size, offset: 0xE48 */
+ uint8_t RESERVED_7[432];
+ __I uint32_t ID; /**< Peripheral Identification, offset: 0xFFC */
+} USART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Register_Masks USART Register Masks
+ * @{
+ */
+
+/*! @name CFG - USART Configuration */
+/*! @{ */
+#define USART_CFG_ENABLE_MASK (0x1U)
+#define USART_CFG_ENABLE_SHIFT (0U)
+/*! ENABLE - USART Enable
+ * 0b0..Disabled
+ * 0b1..Enabled. The USART is enabled for operation.
+ */
+#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
+#define USART_CFG_DATALEN_MASK (0xCU)
+#define USART_CFG_DATALEN_SHIFT (2U)
+/*! DATALEN - Data Length. Selects the data size for the USART.
+ * 0b00..7 bit data length
+ * 0b01..8 bit data length
+ * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET[CTL].
+ * 0b11..Reserved
+ */
+#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
+#define USART_CFG_PARITYSEL_MASK (0x30U)
+#define USART_CFG_PARITYSEL_SHIFT (4U)
+/*! PARITYSEL - Parity Select. Selects what type of parity is used by the USART.
+ * 0b00..No parity
+ * 0b01..Reserved
+ * 0b10..Even parity
+ * 0b11..Odd parity
+ */
+#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
+#define USART_CFG_STOPLEN_MASK (0x40U)
+#define USART_CFG_STOPLEN_SHIFT (6U)
+/*! STOPLEN - Stop Length
+ * 0b0..1 stop bit
+ * 0b1..2 stop bits. This setting should be used only for asynchronous communication.
+ */
+#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
+#define USART_CFG_MODE32K_MASK (0x80U)
+#define USART_CFG_MODE32K_SHIFT (7U)
+/*! MODE32K - Mode 32 kHz
+ * 0b0..Disabled. USART uses standard clocking.
+ * 0b1..Enabled
+ */
+#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
+#define USART_CFG_LINMODE_MASK (0x100U)
+#define USART_CFG_LINMODE_SHIFT (8U)
+/*! LINMODE - LIN Break Mode Enable
+ * 0b0..Disabled. Break detect and generate is configured for normal operation.
+ * 0b1..Enabled. Break detect and generate is configured for LIN bus operation.
+ */
+#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
+#define USART_CFG_CTSEN_MASK (0x200U)
+#define USART_CFG_CTSEN_SHIFT (9U)
+/*! CTSEN - CTS Enable
+ * 0b0..No flow control. The transmitter does not receive any automatic flow control signal.
+ * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
+ */
+#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
+#define USART_CFG_SYNCEN_MASK (0x800U)
+#define USART_CFG_SYNCEN_SHIFT (11U)
+/*! SYNCEN - Synchronous Enable. Selects synchronous or asynchronous operation.
+ * 0b0..Asynchronous mode
+ * 0b1..Synchronous mode
+ */
+#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
+#define USART_CFG_CLKPOL_MASK (0x1000U)
+#define USART_CFG_CLKPOL_SHIFT (12U)
+/*! CLKPOL - Clock Polarity
+ * 0b0..Falling edge. RXD is sampled on the falling edge of SCLK.
+ * 0b1..Rising edge. RXD is sampled on the rising edge of SCLK.
+ */
+#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
+#define USART_CFG_SYNCMST_MASK (0x4000U)
+#define USART_CFG_SYNCMST_SHIFT (14U)
+/*! SYNCMST - Synchronous mode Master Select
+ * 0b0..Slave. When synchronous mode is enabled, the USART is a slave.
+ * 0b1..Master. When synchronous mode is enabled, the USART is a master.
+ */
+#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
+#define USART_CFG_LOOP_MASK (0x8000U)
+#define USART_CFG_LOOP_SHIFT (15U)
+/*! LOOP - Loopback Mode
+ * 0b0..Normal operation
+ * 0b1..Loopback mode
+ */
+#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
+#define USART_CFG_OETA_MASK (0x40000U)
+#define USART_CFG_OETA_SHIFT (18U)
+/*! OETA - Output Enable Turnaround Time Enable for RS-485 Operation.
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
+#define USART_CFG_AUTOADDR_MASK (0x80000U)
+#define USART_CFG_AUTOADDR_SHIFT (19U)
+/*! AUTOADDR - Automatic Address Matching Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
+#define USART_CFG_OESEL_MASK (0x100000U)
+#define USART_CFG_OESEL_SHIFT (20U)
+/*! OESEL - Output Enable Select
+ * 0b0..Standard. The RTS signal is used as the standard flow control function.
+ * 0b1..RS-485. The RTS signal is configured to provide an output enable signal to control an RS-485 transceiver.
+ */
+#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
+#define USART_CFG_OEPOL_MASK (0x200000U)
+#define USART_CFG_OEPOL_SHIFT (21U)
+/*! OEPOL - Output Enable Polarity
+ * 0b0..Low. If selected by OESEL, the output enable is active low.
+ * 0b1..High. If selected by OESEL, the output enable is active high.
+ */
+#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
+#define USART_CFG_RXPOL_MASK (0x400000U)
+#define USART_CFG_RXPOL_SHIFT (22U)
+/*! RXPOL - Receive Data Polarity
+ * 0b0..Standard
+ * 0b1..Inverted
+ */
+#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
+#define USART_CFG_TXPOL_MASK (0x800000U)
+#define USART_CFG_TXPOL_SHIFT (23U)
+/*! TXPOL - Transmit data polarity
+ * 0b0..Standard
+ * 0b1..Inverted
+ */
+#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
+/*! @} */
+
+/*! @name CTL - USART Control */
+/*! @{ */
+#define USART_CTL_TXBRKEN_MASK (0x2U)
+#define USART_CTL_TXBRKEN_SHIFT (1U)
+/*! TXBRKEN - Break Enable
+ * 0b0..Normal operation
+ * 0b1..Continuous break
+ */
+#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
+#define USART_CTL_ADDRDET_MASK (0x4U)
+#define USART_CTL_ADDRDET_SHIFT (2U)
+/*! ADDRDET - Enable Address Detect Mode
+ * 0b0..Disabled. The USART presents all incoming data.
+ * 0b1..Enabled
+ */
+#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
+#define USART_CTL_TXDIS_MASK (0x40U)
+#define USART_CTL_TXDIS_SHIFT (6U)
+/*! TXDIS - Transmit Disable
+ * 0b0..Not disabled. USART transmitter is not disabled.
+ * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This
+ * feature can be used to facilitate software flow control.
+ */
+#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
+#define USART_CTL_CC_MASK (0x100U)
+#define USART_CTL_CC_SHIFT (8U)
+/*! CC - Continuous Clock Generation
+ * 0b0..Clock on character
+ * 0b1..Continuous clock
+ */
+#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
+#define USART_CTL_CLRCCONRX_MASK (0x200U)
+#define USART_CTL_CLRCCONRX_SHIFT (9U)
+/*! CLRCCONRX - Clear Continuous Clock
+ * 0b0..No effect. No effect on the CC bit.
+ * 0b1..Auto-clear
+ */
+#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
+#define USART_CTL_AUTOBAUD_MASK (0x10000U)
+#define USART_CTL_AUTOBAUD_SHIFT (16U)
+/*! AUTOBAUD - Autobaud Enable
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
+/*! @} */
+
+/*! @name STAT - USART Status */
+/*! @{ */
+#define USART_STAT_RXIDLE_MASK (0x2U)
+#define USART_STAT_RXIDLE_SHIFT (1U)
+/*! RXIDLE - Receiver Idle
+ * 0b0..The receiver is currently receiving data.
+ * 0b1..The receiver is not currently receiving data.
+ */
+#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
+#define USART_STAT_TXIDLE_MASK (0x8U)
+#define USART_STAT_TXIDLE_SHIFT (3U)
+/*! TXIDLE - Transmitter Idle
+ * 0b0..The transmitter is currently sending data.
+ * 0b1..The transmitter is not currently sending data.
+ */
+#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
+#define USART_STAT_CTS_MASK (0x10U)
+#define USART_STAT_CTS_SHIFT (4U)
+/*! CTS - CTS value
+ */
+#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
+#define USART_STAT_DELTACTS_MASK (0x20U)
+#define USART_STAT_DELTACTS_SHIFT (5U)
+/*! DELTACTS - Delta CTS
+ */
+#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
+#define USART_STAT_TXDISSTAT_MASK (0x40U)
+#define USART_STAT_TXDISSTAT_SHIFT (6U)
+/*! TXDISSTAT - Transmitter Disabled Status Flag
+ * 0b0..Not Idle. Indicates that the USART transmitter is NOT fully idle after being disabled.
+ * 0b1..Idle. Indicates that the USART transmitter is fully idle after being disabled (CTL[TXDIS] = 1).
+ */
+#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
+#define USART_STAT_RXBRK_MASK (0x400U)
+#define USART_STAT_RXBRK_SHIFT (10U)
+/*! RXBRK - Received Break
+ */
+#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
+#define USART_STAT_DELTARXBRK_MASK (0x800U)
+#define USART_STAT_DELTARXBRK_SHIFT (11U)
+/*! DELTARXBRK - Delta Received Break
+ */
+#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
+#define USART_STAT_START_MASK (0x1000U)
+#define USART_STAT_START_SHIFT (12U)
+/*! START - Start
+ */
+#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
+#define USART_STAT_FRAMERRINT_MASK (0x2000U)
+#define USART_STAT_FRAMERRINT_SHIFT (13U)
+/*! FRAMERRINT - Framing Error Interrupt Flag
+ */
+#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
+#define USART_STAT_PARITYERRINT_MASK (0x4000U)
+#define USART_STAT_PARITYERRINT_SHIFT (14U)
+/*! PARITYERRINT - Parity Error Interrupt Flag
+ */
+#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
+#define USART_STAT_RXNOISEINT_MASK (0x8000U)
+#define USART_STAT_RXNOISEINT_SHIFT (15U)
+/*! RXNOISEINT - Received Noise Interrupt Flag
+ */
+#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
+#define USART_STAT_ABERR_MASK (0x10000U)
+#define USART_STAT_ABERR_SHIFT (16U)
+/*! ABERR - Auto Baud Error
+ */
+#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
+/*! @} */
+
+/*! @name INTENSET - Interrupt Enable Read and Set for USART (not FIFO) Status */
+/*! @{ */
+#define USART_INTENSET_TXIDLEEN_MASK (0x8U)
+#define USART_INTENSET_TXIDLEEN_SHIFT (3U)
+/*! TXIDLEEN - Transmit Idle Flag
+ * 0b1..Enables an interrupt when the transmitter becomes idle (STAT[TXIDLE] = 1).
+ */
+#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
+#define USART_INTENSET_DELTACTSEN_MASK (0x20U)
+#define USART_INTENSET_DELTACTSEN_SHIFT (5U)
+/*! DELTACTSEN - Delta CTS Input Flag
+ * 0b1..Enables an interrupt when there is a change in the state of the CTS input.
+ */
+#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
+#define USART_INTENSET_TXDISEN_MASK (0x40U)
+#define USART_INTENSET_TXDISEN_SHIFT (6U)
+/*! TXDISEN - Transmit Disabled Flag
+ * 0b1..Enables an interrupt when the transmitter is fully disabled as indicated by the STAT[TXDISINT] flag. See
+ * the description of the STAT[TXDISINT] flag.
+ */
+#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
+#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U)
+#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U)
+/*! DELTARXBRKEN - Delta Receive Break Enable
+ * 0b1..Enable
+ */
+#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
+#define USART_INTENSET_STARTEN_MASK (0x1000U)
+#define USART_INTENSET_STARTEN_SHIFT (12U)
+/*! STARTEN - Start Enable
+ * 0b1..Enables an interrupt when a received start bit has been detected.
+ */
+#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
+#define USART_INTENSET_FRAMERREN_MASK (0x2000U)
+#define USART_INTENSET_FRAMERREN_SHIFT (13U)
+/*! FRAMERREN - Frame Error Enable
+ * 0b1..Enables an interrupt when a framing error has been detected.
+ */
+#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
+#define USART_INTENSET_PARITYERREN_MASK (0x4000U)
+#define USART_INTENSET_PARITYERREN_SHIFT (14U)
+/*! PARITYERREN - Parity Error Enble
+ * 0b1..Enables an interrupt when a parity error has been detected.
+ */
+#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
+#define USART_INTENSET_RXNOISEEN_MASK (0x8000U)
+#define USART_INTENSET_RXNOISEEN_SHIFT (15U)
+/*! RXNOISEEN - Receive Noise Enable
+ * 0b1..Enables an interrupt when noise is detected. See the description of the CTL[RXNOISEINT] bit.
+ */
+#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
+#define USART_INTENSET_ABERREN_MASK (0x10000U)
+#define USART_INTENSET_ABERREN_SHIFT (16U)
+/*! ABERREN - Auto Baud Error Enable
+ * 0b1..Enables an interrupt when an auto baud error occurs.
+ */
+#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
+/*! @} */
+
+/*! @name INTENCLR - Interrupt Enable Clear */
+/*! @{ */
+#define USART_INTENCLR_TXIDLECLR_MASK (0x8U)
+#define USART_INTENCLR_TXIDLECLR_SHIFT (3U)
+/*! TXIDLECLR - Transmit Idle Clear
+ */
+#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
+#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U)
+#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U)
+/*! DELTACTSCLR - Delta CTS Clear
+ */
+#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
+#define USART_INTENCLR_TXDISCLR_MASK (0x40U)
+#define USART_INTENCLR_TXDISCLR_SHIFT (6U)
+/*! TXDISCLR - Transmit Disable Clear
+ */
+#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
+#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U)
+#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U)
+/*! DELTARXBRKCLR - Delta Receive Break Clear
+ */
+#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
+#define USART_INTENCLR_STARTCLR_MASK (0x1000U)
+#define USART_INTENCLR_STARTCLR_SHIFT (12U)
+/*! STARTCLR - Start Clear
+ */
+#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
+#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U)
+#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U)
+/*! FRAMERRCLR - Frame Error Clear
+ */
+#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
+#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U)
+#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U)
+/*! PARITYERRCLR - Parity Error Clear
+ */
+#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
+#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U)
+#define USART_INTENCLR_RXNOISECLR_SHIFT (15U)
+/*! RXNOISECLR - Receive Noise Clear
+ */
+#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
+#define USART_INTENCLR_ABERRCLR_MASK (0x10000U)
+#define USART_INTENCLR_ABERRCLR_SHIFT (16U)
+/*! ABERRCLR - Auto Baud Error Clear
+ */
+#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
+/*! @} */
+
+/*! @name BRG - Baud Rate Generator */
+/*! @{ */
+#define USART_BRG_BRGVAL_MASK (0xFFFFU)
+#define USART_BRG_BRGVAL_SHIFT (0U)
+/*! BRGVAL - Baud Rate Generator Value
+ * 0b0000000000000000..FCLK is used directly by the USART function.
+ * 0b0000000000000001..FCLK is divided by 2 before use by the USART function.
+ * 0b0000000000000010..FCLK is divided by 3 before use by the USART function.
+ * 0b1111111111111111..FCLK is divided by 65,536 before use by the USART function.
+ */
+#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt Status */
+/*! @{ */
+#define USART_INTSTAT_TXIDLE_MASK (0x8U)
+#define USART_INTSTAT_TXIDLE_SHIFT (3U)
+/*! TXIDLE - Transmitter Idle Flag
+ */
+#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
+#define USART_INTSTAT_DELTACTS_MASK (0x20U)
+#define USART_INTSTAT_DELTACTS_SHIFT (5U)
+/*! DELTACTS - Delta CTS Change Flag
+ */
+#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
+#define USART_INTSTAT_TXDISINT_MASK (0x40U)
+#define USART_INTSTAT_TXDISINT_SHIFT (6U)
+/*! TXDISINT - Transmitter Disabled Interrupt Flag
+ */
+#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
+#define USART_INTSTAT_DELTARXBRK_MASK (0x800U)
+#define USART_INTSTAT_DELTARXBRK_SHIFT (11U)
+/*! DELTARXBRK - Delta Receiver Break Change Flag
+ */
+#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
+#define USART_INTSTAT_START_MASK (0x1000U)
+#define USART_INTSTAT_START_SHIFT (12U)
+/*! START - Start Detected on Receiver Flag
+ */
+#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
+#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U)
+#define USART_INTSTAT_FRAMERRINT_SHIFT (13U)
+/*! FRAMERRINT - Framing Error Interrupt Flag
+ */
+#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
+#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U)
+#define USART_INTSTAT_PARITYERRINT_SHIFT (14U)
+/*! PARITYERRINT - Parity Error Interrupt Flag
+ */
+#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
+#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U)
+#define USART_INTSTAT_RXNOISEINT_SHIFT (15U)
+/*! RXNOISEINT - Received Noise Interrupt Flag
+ */
+#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
+#define USART_INTSTAT_ABERRINT_MASK (0x10000U)
+#define USART_INTSTAT_ABERRINT_SHIFT (16U)
+/*! ABERRINT - Auto Baud Error Interrupt Flag
+ */
+#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
+/*! @} */
+
+/*! @name OSR - Oversample Selection Register for Asynchronous Communication */
+/*! @{ */
+#define USART_OSR_OSRVAL_MASK (0xFU)
+#define USART_OSR_OSRVAL_SHIFT (0U)
+/*! OSRVAL - Oversample Selection Value
+ * 0b0000..Not supported
+ * 0b0001..Not supported
+ * 0b0010..Not supported
+ * 0b0011..Not supported
+ * 0b0100..5 function clocks are used to transmit and receive each data bit.
+ * 0b0101..6 function clocks are used to transmit and receive each data bit.
+ * 0b1111..16 function clocks are used to transmit and receive each data bit.
+ */
+#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
+/*! @} */
+
+/*! @name ADDR - Address Register for Automatic Address Matching */
+/*! @{ */
+#define USART_ADDR_ADDRESS_MASK (0xFFU)
+#define USART_ADDR_ADDRESS_SHIFT (0U)
+/*! ADDRESS - Address
+ */
+#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
+/*! @} */
+
+/*! @name FIFOCFG - FIFO Configuration */
+/*! @{ */
+#define USART_FIFOCFG_ENABLETX_MASK (0x1U)
+#define USART_FIFOCFG_ENABLETX_SHIFT (0U)
+/*! ENABLETX - Enable the Transmit FIFO.
+ * 0b0..The transmit FIFO is not enabled.
+ * 0b1..The transmit FIFO is enabled.
+ */
+#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
+#define USART_FIFOCFG_ENABLERX_MASK (0x2U)
+#define USART_FIFOCFG_ENABLERX_SHIFT (1U)
+/*! ENABLERX - Enable the Receive FIFO
+ * 0b0..The receive FIFO is not enabled.
+ * 0b1..The receive FIFO is enabled.
+ */
+#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
+#define USART_FIFOCFG_SIZE_MASK (0x30U)
+#define USART_FIFOCFG_SIZE_SHIFT (4U)
+/*! SIZE - FIFO Size Configuration
+ * 0b00..FIFO is configured as 16 entries of 8 bits.
+ * 0b01..Not used
+ * 0b10..Not used
+ * 0b11..Not used
+ */
+#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
+#define USART_FIFOCFG_DMATX_MASK (0x1000U)
+#define USART_FIFOCFG_DMATX_SHIFT (12U)
+/*! DMATX - DMA Configuration for Transmit
+ * 0b0..DMA is not used for the transmit function.
+ * 0b1..Triggers DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
+#define USART_FIFOCFG_DMARX_MASK (0x2000U)
+#define USART_FIFOCFG_DMARX_SHIFT (13U)
+/*! DMARX - DMA Configuration for Receive
+ * 0b0..DMA is not used for the receive function.
+ * 0b1..Triggers DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
+ */
+#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
+#define USART_FIFOCFG_WAKETX_MASK (0x4000U)
+#define USART_FIFOCFG_WAKETX_SHIFT (14U)
+/*! WAKETX - Wake-up for Transmit FIFO Level
+ * 0b0..Only enabled interrupts will wake up the device from low power modes.
+ * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by
+ * FIFOTRIG[TXLVL], even when the TXLVL interrupt is not enabled.
+ */
+#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
+#define USART_FIFOCFG_WAKERX_MASK (0x8000U)
+#define USART_FIFOCFG_WAKERX_SHIFT (15U)
+/*! WAKERX - Wake-up for Receive FIFO Level
+ * 0b0..Only enabled interrupts will wake up the device from low power modes.
+ * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by
+ * FIFOTRIG[RXLVL], even when the RXLVL interrupt is not enabled.
+ */
+#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
+#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U)
+#define USART_FIFOCFG_EMPTYTX_SHIFT (16U)
+/*! EMPTYTX - Empty Command for the Transmit FIFO
+ * 0b0..No effect
+ * 0b1..The TX FIFO is emptied.
+ */
+#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
+#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U)
+#define USART_FIFOCFG_EMPTYRX_SHIFT (17U)
+/*! EMPTYRX - Empty Command for the Receive FIFO
+ * 0b0..No effect
+ * 0b1..The RX FIFO is emptied.
+ */
+#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
+#define USART_FIFOCFG_POPDBG_MASK (0x40000U)
+#define USART_FIFOCFG_POPDBG_SHIFT (18U)
+/*! POPDBG - Pop FIFO for Debug Reads
+ * 0b0..Debug reads of the FIFO do not pop the FIFO.
+ * 0b1..A debug read will cause the FIFO to pop.
+ */
+#define USART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK)
+/*! @} */
+
+/*! @name FIFOSTAT - FIFO Status */
+/*! @{ */
+#define USART_FIFOSTAT_TXERR_MASK (0x1U)
+#define USART_FIFOSTAT_TXERR_SHIFT (0U)
+/*! TXERR - TX FIFO Error
+ * 0b0..A transmit FIFO error has not occurred.
+ * 0b1..A transmit FIFO error has occurred. This error could be an overflow caused by pushing data into a full
+ * FIFO, or by an underflow if the FIFO is empty when data is needed.
+ */
+#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
+#define USART_FIFOSTAT_RXERR_MASK (0x2U)
+#define USART_FIFOSTAT_RXERR_SHIFT (1U)
+/*! RXERR - RX FIFO Error
+ * 0b0..A receive FIFO overflow has not occurred
+ * 0b1..A receive FIFO overflow has occurred, caused by software or DMA not emptying the FIFO fast enough
+ */
+#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
+#define USART_FIFOSTAT_PERINT_MASK (0x8U)
+#define USART_FIFOSTAT_PERINT_SHIFT (3U)
+/*! PERINT - Peripheral Interrupt
+ * 0b0..No Peripheral Interrupt
+ * 0b1..Peripheral Interrupt
+ */
+#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
+#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U)
+#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U)
+/*! TXEMPTY - Transmit FIFO Empty
+ * 0b0..The transmit FIFO is not empty.
+ * 0b1..The transmit FIFO is empty, although the peripheral may still be processing the last piece of data.
+ */
+#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
+#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U)
+#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U)
+/*! TXNOTFULL - Transmit FIFO is Not Full
+ * 0b0..The transmit FIFO is full and another write would cause it to overflow.
+ * 0b1..The transmit FIFO is not full, so more data can be written.
+ */
+#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
+#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
+#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
+/*! RXNOTEMPTY - Receive FIFO is Not Empty
+ * 0b0..The receive FIFO is empty.
+ * 0b1..The receive FIFO is not empty, so data can be read.
+ */
+#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
+#define USART_FIFOSTAT_RXFULL_MASK (0x80U)
+#define USART_FIFOSTAT_RXFULL_SHIFT (7U)
+/*! RXFULL - Receive FIFO is Full
+ * 0b0..The receive FIFO is not full.
+ * 0b1..The receive FIFO is full.
+ */
+#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
+#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U)
+#define USART_FIFOSTAT_TXLVL_SHIFT (8U)
+/*! TXLVL - Transmit FIFO Current Level
+ */
+#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
+#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U)
+#define USART_FIFOSTAT_RXLVL_SHIFT (16U)
+/*! RXLVL - Receive FIFO Current Level
+ */
+#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOTRIG - FIFO Trigger Settings for Interrupt and DMA Request */
+/*! @{ */
+#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U)
+#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U)
+/*! TXLVLENA - Transmit FIFO Level Trigger Enable.
+ * 0b0..Transmit FIFO level does not generate a FIFO level trigger.
+ * 0b1..A trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field.
+ */
+#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
+#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U)
+#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U)
+/*! RXLVLENA - Receive FIFO Level Trigger Enable
+ * 0b0..Receive FIFO level does not generate a FIFO level trigger.
+ * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field.
+ */
+#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
+#define USART_FIFOTRIG_TXLVL_MASK (0xF00U)
+#define USART_FIFOTRIG_TXLVL_SHIFT (8U)
+/*! TXLVL - Transmit FIFO Level Trigger Point
+ * 0b0000..Trigger when the TX FIFO becomes empty
+ * 0b0001..Trigger when the TX FIFO level decreases to 1 entry
+ * 0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full)
+ */
+#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
+#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U)
+#define USART_FIFOTRIG_RXLVL_SHIFT (16U)
+/*! RXLVL - Receive FIFO Level Trigger Point
+ * 0b0000..Trigger when the RX FIFO has received 1 entry (is no longer empty)
+ * 0b0001..Trigger when the RX FIFO has received 2 entries
+ * 0b1111..Trigger when the RX FIFO has received 16 entries (has become full)
+ */
+#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENSET - FIFO Interrupt Enable */
+/*! @{ */
+#define USART_FIFOINTENSET_TXERR_MASK (0x1U)
+#define USART_FIFOINTENSET_TXERR_SHIFT (0U)
+/*! TXERR - Transmit Error Interrupt Enable
+ * 0b0..No interrupt will be generated for a transmit error.
+ * 0b1..An interrupt will be generated when a transmit error occurs.
+ */
+#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
+#define USART_FIFOINTENSET_RXERR_MASK (0x2U)
+#define USART_FIFOINTENSET_RXERR_SHIFT (1U)
+/*! RXERR - Receive Error Interrupt Enable
+ * 0b0..No interrupt will be generated for a receive error.
+ * 0b1..An interrupt will be generated when a receive error occurs.
+ */
+#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
+#define USART_FIFOINTENSET_TXLVL_MASK (0x4U)
+#define USART_FIFOINTENSET_TXLVL_SHIFT (2U)
+/*! TXLVL - Transmit FIFO Level Interrupt Enable
+ * 0b0..No interrupt will be generated based on the TX FIFO level.
+ * 0b1..If FIFOTRIG[TXLVLENA] = 1, then an interrupt will be generated when the TX FIFO level decreases to the level specified by FIFOTRIG[TXLVL]
+ */
+#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
+#define USART_FIFOINTENSET_RXLVL_MASK (0x8U)
+#define USART_FIFOINTENSET_RXLVL_SHIFT (3U)
+/*! RXLVL - Receive FIFO Level Interrupt Enable
+ * 0b0..No interrupt will be generated based on the RX FIFO level.
+ * 0b1..If FIFOTRIG[RXLVLENA] = 1, an interrupt will be generated when the when the RX FIFO level increases to
+ * the level specified by FIFOTRIG[RXLVL].
+ */
+#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear */
+/*! @{ */
+#define USART_FIFOINTENCLR_TXERR_MASK (0x1U)
+#define USART_FIFOINTENCLR_TXERR_SHIFT (0U)
+/*! TXERR - Transmit Error Interrupt Enable
+ * 0b0..No effect
+ * 0b1..Clear the interrupt
+ */
+#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
+#define USART_FIFOINTENCLR_RXERR_MASK (0x2U)
+#define USART_FIFOINTENCLR_RXERR_SHIFT (1U)
+/*! RXERR - Receive Error Interrupt Enable
+ * 0b0..No effect
+ * 0b1..Clear the interrupt
+ */
+#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
+#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U)
+#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U)
+/*! TXLVL - Transmit FIFO Level Interrupt Enable
+ * 0b0..No effect
+ * 0b1..Clear the interrupt
+ */
+#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
+#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U)
+#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U)
+/*! RXLVL - Receive FIFO Level Interrupt Enable
+ * 0b0..No effect
+ * 0b1..Clear the interrupt
+ */
+#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
+/*! @} */
+
+/*! @name FIFOINTSTAT - FIFO Interrupt Status */
+/*! @{ */
+#define USART_FIFOINTSTAT_TXERR_MASK (0x1U)
+#define USART_FIFOINTSTAT_TXERR_SHIFT (0U)
+/*! TXERR - TX FIFO Error Interrupt Status
+ * 0b0..Not pending
+ * 0b1..Pending
+ */
+#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
+#define USART_FIFOINTSTAT_RXERR_MASK (0x2U)
+#define USART_FIFOINTSTAT_RXERR_SHIFT (1U)
+/*! RXERR - RX FIFO Error Interrupt Status
+ * 0b0..Not pending
+ * 0b1..Pending
+ */
+#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
+#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U)
+#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U)
+/*! TXLVL - Transmit FIFO Level Interrupt Status
+ * 0b0..Not pending
+ * 0b1..Pending
+ */
+#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
+#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U)
+#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U)
+/*! RXLVL - Receive FIFO Level Interrupt Status
+ * 0b0..Not pending
+ * 0b1..Pending
+ */
+#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
+#define USART_FIFOINTSTAT_PERINT_MASK (0x10U)
+#define USART_FIFOINTSTAT_PERINT_SHIFT (4U)
+/*! PERINT - Peripheral Interrupt Status
+ * 0b0..Not pending
+ * 0b1..Pending
+ */
+#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
+/*! @} */
+
+/*! @name FIFOWR - FIFO Write Data */
+/*! @{ */
+#define USART_FIFOWR_TXDATA_MASK (0x1FFU)
+#define USART_FIFOWR_TXDATA_SHIFT (0U)
+/*! TXDATA - Transmit data to the FIFO
+ */
+#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
+/*! @} */
+
+/*! @name FIFORD - FIFO Read Data */
+/*! @{ */
+#define USART_FIFORD_RXDATA_MASK (0x1FFU)
+#define USART_FIFORD_RXDATA_SHIFT (0U)
+/*! RXDATA - Received Data from the FIFO
+ */
+#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
+#define USART_FIFORD_FRAMERR_MASK (0x2000U)
+#define USART_FIFORD_FRAMERR_SHIFT (13U)
+/*! FRAMERR - Framing Error Status Flag
+ */
+#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
+#define USART_FIFORD_PARITYERR_MASK (0x4000U)
+#define USART_FIFORD_PARITYERR_SHIFT (14U)
+/*! PARITYERR - Parity Error Status Flag
+ */
+#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
+#define USART_FIFORD_RXNOISE_MASK (0x8000U)
+#define USART_FIFORD_RXNOISE_SHIFT (15U)
+/*! RXNOISE - Received Noise Flag
+ */
+#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
+/*! @} */
+
+/*! @name FIFORDNOPOP - FIFO Data Read with No FIFO Pop */
+/*! @{ */
+#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU)
+#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U)
+/*! RXDATA - Received Data from the FIFO
+ */
+#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
+#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U)
+#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U)
+/*! FRAMERR - Framing Error Status Flag
+ */
+#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
+#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U)
+#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U)
+/*! PARITYERR - Parity Error Status Flag
+ */
+#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
+#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U)
+#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U)
+/*! RXNOISE - Received Noise Flag
+ */
+#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
+/*! @} */
+
+/*! @name FIFOSIZE - FIFO Size */
+/*! @{ */
+#define USART_FIFOSIZE_FIFOSIZE_MASK (0x1FU)
+#define USART_FIFOSIZE_FIFOSIZE_SHIFT (0U)
+/*! FIFOSIZE - FIFO Size
+ */
+#define USART_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK)
+/*! @} */
+
+/*! @name ID - Peripheral Identification */
+/*! @{ */
+#define USART_ID_APERTURE_MASK (0xFFU)
+#define USART_ID_APERTURE_SHIFT (0U)
+/*! APERTURE - Aperture
+ */
+#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)
+#define USART_ID_MINOR_REV_MASK (0xF00U)
+#define USART_ID_MINOR_REV_SHIFT (8U)
+/*! MINOR_REV - Minor revision of module implementation
+ */
+#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)
+#define USART_ID_MAJOR_REV_MASK (0xF000U)
+#define USART_ID_MAJOR_REV_SHIFT (12U)
+/*! MAJOR_REV - Major revision of module implementation
+ */
+#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)
+#define USART_ID_ID_MASK (0xFFFF0000U)
+#define USART_ID_ID_SHIFT (16U)
+/*! ID - Module identifier for the selected function
+ */
+#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USART_Register_Masks */
+
+
+/* USART - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral USART0 base address */
+ #define USART0_BASE (0x50106000u)
+ /** Peripheral USART0 base address */
+ #define USART0_BASE_NS (0x40106000u)
+ /** Peripheral USART0 base pointer */
+ #define USART0 ((USART_Type *)USART0_BASE)
+ /** Peripheral USART0 base pointer */
+ #define USART0_NS ((USART_Type *)USART0_BASE_NS)
+ /** Peripheral USART1 base address */
+ #define USART1_BASE (0x50107000u)
+ /** Peripheral USART1 base address */
+ #define USART1_BASE_NS (0x40107000u)
+ /** Peripheral USART1 base pointer */
+ #define USART1 ((USART_Type *)USART1_BASE)
+ /** Peripheral USART1 base pointer */
+ #define USART1_NS ((USART_Type *)USART1_BASE_NS)
+ /** Peripheral USART2 base address */
+ #define USART2_BASE (0x50108000u)
+ /** Peripheral USART2 base address */
+ #define USART2_BASE_NS (0x40108000u)
+ /** Peripheral USART2 base pointer */
+ #define USART2 ((USART_Type *)USART2_BASE)
+ /** Peripheral USART2 base pointer */
+ #define USART2_NS ((USART_Type *)USART2_BASE_NS)
+ /** Peripheral USART3 base address */
+ #define USART3_BASE (0x50109000u)
+ /** Peripheral USART3 base address */
+ #define USART3_BASE_NS (0x40109000u)
+ /** Peripheral USART3 base pointer */
+ #define USART3 ((USART_Type *)USART3_BASE)
+ /** Peripheral USART3 base pointer */
+ #define USART3_NS ((USART_Type *)USART3_BASE_NS)
+ /** Peripheral USART4 base address */
+ #define USART4_BASE (0x50122000u)
+ /** Peripheral USART4 base address */
+ #define USART4_BASE_NS (0x40122000u)
+ /** Peripheral USART4 base pointer */
+ #define USART4 ((USART_Type *)USART4_BASE)
+ /** Peripheral USART4 base pointer */
+ #define USART4_NS ((USART_Type *)USART4_BASE_NS)
+ /** Peripheral USART5 base address */
+ #define USART5_BASE (0x50123000u)
+ /** Peripheral USART5 base address */
+ #define USART5_BASE_NS (0x40123000u)
+ /** Peripheral USART5 base pointer */
+ #define USART5 ((USART_Type *)USART5_BASE)
+ /** Peripheral USART5 base pointer */
+ #define USART5_NS ((USART_Type *)USART5_BASE_NS)
+ /** Peripheral USART6 base address */
+ #define USART6_BASE (0x50124000u)
+ /** Peripheral USART6 base address */
+ #define USART6_BASE_NS (0x40124000u)
+ /** Peripheral USART6 base pointer */
+ #define USART6 ((USART_Type *)USART6_BASE)
+ /** Peripheral USART6 base pointer */
+ #define USART6_NS ((USART_Type *)USART6_BASE_NS)
+ /** Peripheral USART7 base address */
+ #define USART7_BASE (0x50125000u)
+ /** Peripheral USART7 base address */
+ #define USART7_BASE_NS (0x40125000u)
+ /** Peripheral USART7 base pointer */
+ #define USART7 ((USART_Type *)USART7_BASE)
+ /** Peripheral USART7 base pointer */
+ #define USART7_NS ((USART_Type *)USART7_BASE_NS)
+ /** Peripheral USART8 base address */
+ #define USART8_BASE (0x50209000u)
+ /** Peripheral USART8 base address */
+ #define USART8_BASE_NS (0x40209000u)
+ /** Peripheral USART8 base pointer */
+ #define USART8 ((USART_Type *)USART8_BASE)
+ /** Peripheral USART8 base pointer */
+ #define USART8_NS ((USART_Type *)USART8_BASE_NS)
+ /** Peripheral USART9 base address */
+ #define USART9_BASE (0x5020A000u)
+ /** Peripheral USART9 base address */
+ #define USART9_BASE_NS (0x4020A000u)
+ /** Peripheral USART9 base pointer */
+ #define USART9 ((USART_Type *)USART9_BASE)
+ /** Peripheral USART9 base pointer */
+ #define USART9_NS ((USART_Type *)USART9_BASE_NS)
+ /** Peripheral USART10 base address */
+ #define USART10_BASE (0x5020B000u)
+ /** Peripheral USART10 base address */
+ #define USART10_BASE_NS (0x4020B000u)
+ /** Peripheral USART10 base pointer */
+ #define USART10 ((USART_Type *)USART10_BASE)
+ /** Peripheral USART10 base pointer */
+ #define USART10_NS ((USART_Type *)USART10_BASE_NS)
+ /** Peripheral USART11 base address */
+ #define USART11_BASE (0x5020C000u)
+ /** Peripheral USART11 base address */
+ #define USART11_BASE_NS (0x4020C000u)
+ /** Peripheral USART11 base pointer */
+ #define USART11 ((USART_Type *)USART11_BASE)
+ /** Peripheral USART11 base pointer */
+ #define USART11_NS ((USART_Type *)USART11_BASE_NS)
+ /** Peripheral USART12 base address */
+ #define USART12_BASE (0x5020D000u)
+ /** Peripheral USART12 base address */
+ #define USART12_BASE_NS (0x4020D000u)
+ /** Peripheral USART12 base pointer */
+ #define USART12 ((USART_Type *)USART12_BASE)
+ /** Peripheral USART12 base pointer */
+ #define USART12_NS ((USART_Type *)USART12_BASE_NS)
+ /** Peripheral USART13 base address */
+ #define USART13_BASE (0x5020E000u)
+ /** Peripheral USART13 base address */
+ #define USART13_BASE_NS (0x4020E000u)
+ /** Peripheral USART13 base pointer */
+ #define USART13 ((USART_Type *)USART13_BASE)
+ /** Peripheral USART13 base pointer */
+ #define USART13_NS ((USART_Type *)USART13_BASE_NS)
+ /** Array initializer of USART peripheral base addresses */
+ #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE, USART10_BASE, USART11_BASE, USART12_BASE, USART13_BASE }
+ /** Array initializer of USART peripheral base pointers */
+ #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9, USART10, USART11, USART12, USART13 }
+ /** Array initializer of USART peripheral base addresses */
+ #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS, USART8_BASE_NS, USART9_BASE_NS, USART10_BASE_NS, USART11_BASE_NS, USART12_BASE_NS, USART13_BASE_NS }
+ /** Array initializer of USART peripheral base pointers */
+ #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS, USART8_NS, USART9_NS, USART10_NS, USART11_NS, USART12_NS, USART13_NS }
+#else
+ /** Peripheral USART0 base address */
+ #define USART0_BASE (0x40106000u)
+ /** Peripheral USART0 base pointer */
+ #define USART0 ((USART_Type *)USART0_BASE)
+ /** Peripheral USART1 base address */
+ #define USART1_BASE (0x40107000u)
+ /** Peripheral USART1 base pointer */
+ #define USART1 ((USART_Type *)USART1_BASE)
+ /** Peripheral USART2 base address */
+ #define USART2_BASE (0x40108000u)
+ /** Peripheral USART2 base pointer */
+ #define USART2 ((USART_Type *)USART2_BASE)
+ /** Peripheral USART3 base address */
+ #define USART3_BASE (0x40109000u)
+ /** Peripheral USART3 base pointer */
+ #define USART3 ((USART_Type *)USART3_BASE)
+ /** Peripheral USART4 base address */
+ #define USART4_BASE (0x40122000u)
+ /** Peripheral USART4 base pointer */
+ #define USART4 ((USART_Type *)USART4_BASE)
+ /** Peripheral USART5 base address */
+ #define USART5_BASE (0x40123000u)
+ /** Peripheral USART5 base pointer */
+ #define USART5 ((USART_Type *)USART5_BASE)
+ /** Peripheral USART6 base address */
+ #define USART6_BASE (0x40124000u)
+ /** Peripheral USART6 base pointer */
+ #define USART6 ((USART_Type *)USART6_BASE)
+ /** Peripheral USART7 base address */
+ #define USART7_BASE (0x40125000u)
+ /** Peripheral USART7 base pointer */
+ #define USART7 ((USART_Type *)USART7_BASE)
+ /** Peripheral USART8 base address */
+ #define USART8_BASE (0x40209000u)
+ /** Peripheral USART8 base pointer */
+ #define USART8 ((USART_Type *)USART8_BASE)
+ /** Peripheral USART9 base address */
+ #define USART9_BASE (0x4020A000u)
+ /** Peripheral USART9 base pointer */
+ #define USART9 ((USART_Type *)USART9_BASE)
+ /** Peripheral USART10 base address */
+ #define USART10_BASE (0x4020B000u)
+ /** Peripheral USART10 base pointer */
+ #define USART10 ((USART_Type *)USART10_BASE)
+ /** Peripheral USART11 base address */
+ #define USART11_BASE (0x4020C000u)
+ /** Peripheral USART11 base pointer */
+ #define USART11 ((USART_Type *)USART11_BASE)
+ /** Peripheral USART12 base address */
+ #define USART12_BASE (0x4020D000u)
+ /** Peripheral USART12 base pointer */
+ #define USART12 ((USART_Type *)USART12_BASE)
+ /** Peripheral USART13 base address */
+ #define USART13_BASE (0x4020E000u)
+ /** Peripheral USART13 base pointer */
+ #define USART13 ((USART_Type *)USART13_BASE)
+ /** Array initializer of USART peripheral base addresses */
+ #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE, USART10_BASE, USART11_BASE, USART12_BASE, USART13_BASE }
+ /** Array initializer of USART peripheral base pointers */
+ #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9, USART10, USART11, USART12, USART13 }
+#endif
+/** Interrupt vectors for the USART peripheral type */
+#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXCOMM10_IRQn, FLEXCOMM11_IRQn, FLEXCOMM12_IRQn, FLEXCOMM13_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBHSD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer
+ * @{
+ */
+
+/** USBHSD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status, offset: 0x0 */
+ __IO uint32_t INFO; /**< USB Info, offset: 0x4 */
+ __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List Start Address, offset: 0x8 */
+ __IO uint32_t DATABUFSTART; /**< USB Data Buffer List Start Address, offset: 0xC */
+ __IO uint32_t LPM; /**< USB Link Power Management, offset: 0x10 */
+ __IO uint32_t EPSKIP; /**< USB Endpoint Skip, offset: 0x14 */
+ __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */
+ __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration, offset: 0x1C */
+ __IO uint32_t INTSTAT; /**< USB Interrupt Status, offset: 0x20 */
+ __IO uint32_t INTEN; /**< USB Interrupt Enable, offset: 0x24 */
+ __IO uint32_t INTSETSTAT; /**< USB Set Interrupt Status, offset: 0x28 */
+ uint8_t RESERVED_0[8];
+ __I uint32_t EPTOGGLE; /**< USB Endpoint Toggle, offset: 0x34 */
+} USBHSD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBHSD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSD_Register_Masks USBHSD Register Masks
+ * @{
+ */
+
+/*! @name DEVCMDSTAT - USB Device Command/Status */
+/*! @{ */
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)
+/*! DEV_ADDR - USB Device Address
+ */
+#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK)
+#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U)
+#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U)
+/*! DEV_EN - USB device enable
+ */
+#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK)
+#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U)
+#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U)
+/*! SETUP - SETUP token received.
+ */
+#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)
+/*! FORCE_NEEDCLK - Force the NEEDCLK output to always be on.
+ * 0b0..USB_NEEDCLK has normal function.
+ * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend.
+ */
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U)
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U)
+/*! FORCE_VBUS - Force VBUS
+ */
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U)
+#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U)
+/*! LPM_SUP - LPM Support
+ * 0b0..LPM not supported.
+ * 0b1..LPM supported.
+ */
+#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)
+/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP
+ * 0b0..Only acknowledged packets generate an interrupt
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.
+ */
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)
+/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP
+ * 0b0..Only acknowledged packets generate an interrupt
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.
+ */
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)
+/*! INTONNAK_CO - Interrupt on NAK for interrupt and bulk OUT EP
+ * 0b0..Only acknowledged packets generate an interrupt
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.
+ */
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)
+/*! INTONNAK_CI - Interrupt on NAK for interrupt and bulk OUT EP
+ * 0b0..Only acknowledged packets generate an interrupt
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.
+ */
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK)
+#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U)
+#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U)
+/*! DCON - Device status - connect.
+ */
+#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK)
+#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U)
+#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U)
+/*! DSUS - Device status suspend.
+ * 0b0..When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect.
+ * 0b1..It is set to 1 when the device has not seen any activity on its upstream port for more than 3 ms. It is
+ * reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0
+ * to it, the device will generate a remote wake-up. This will only happen when the device is connected
+ * (Connect bit = 1).
+ */
+#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)
+#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U)
+/*! LPM_SUS - Device status - LPM Suspend.
+ * 0b0..Software can only write a 0 to this bit when the LPM_REWP bit is set to 1. Hardware resets this bit when
+ * it receives a host initiated resume. Hardware only updates the LPM_SUS bit when the LPM_SUPP bit is equal
+ * to 1.
+ * 0b1..When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a 0 to this
+ * bit, the device will generate a remote walk-up.
+ */
+#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)
+#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U)
+/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host.
+ */
+#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK)
+#define USBHSD_DEVCMDSTAT_SPEED_MASK (0xC00000U)
+#define USBHSD_DEVCMDSTAT_SPEED_SHIFT (22U)
+/*! SPEED - This field indicates the speed at which the device operates.
+ * 0b00..Reserved
+ * 0b01..Full-speed
+ * 0b10..High-speed
+ * 0b11..Reserved
+ */
+#define USBHSD_DEVCMDSTAT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SPEED_SHIFT)) & USBHSD_DEVCMDSTAT_SPEED_MASK)
+#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U)
+#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U)
+/*! DCON_C - Device status - connect change.
+ */
+#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK)
+#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)
+#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U)
+/*! DSUS_C - Device status - suspend change.
+ */
+#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK)
+#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U)
+#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U)
+/*! DRES_C - Device status - reset change.
+ */
+#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U)
+/*! VBUS_DEBOUNCED - VBUS detect.
+ */
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U)
+/*! PHY_TEST_MODE - PHY test mode
+ * 0b000..Test mode disabled
+ * 0b001..Test_J
+ * 0b010..Test_K
+ * 0b011..Test_SE0_NAK
+ * 0b100..Test_Packet
+ * 0b101..Test_Force_Enable
+ */
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)
+/*! @} */
+
+/*! @name INFO - USB Info */
+/*! @{ */
+#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU)
+#define USBHSD_INFO_FRAME_NR_SHIFT (0U)
+/*! FRAME_NR - Frame number.
+ */
+#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK)
+#define USBHSD_INFO_ERR_CODE_MASK (0x7800U)
+#define USBHSD_INFO_ERR_CODE_SHIFT (11U)
+/*! ERR_CODE - The error code which last occurred
+ */
+#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK)
+#define USBHSD_INFO_MINREV_MASK (0xFF0000U)
+#define USBHSD_INFO_MINREV_SHIFT (16U)
+/*! MINREV - Minor revision
+ */
+#define USBHSD_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MINREV_SHIFT)) & USBHSD_INFO_MINREV_MASK)
+#define USBHSD_INFO_MAJREV_MASK (0xFF000000U)
+#define USBHSD_INFO_MAJREV_SHIFT (24U)
+/*! MAJREV - Major revision
+ */
+#define USBHSD_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MAJREV_SHIFT)) & USBHSD_INFO_MAJREV_MASK)
+/*! @} */
+
+/*! @name EPLISTSTART - USB EP Command/Status List Start Address */
+/*! @{ */
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U)
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U)
+#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK)
+/*! @} */
+
+/*! @name DATABUFSTART - USB Data Buffer List Start Address */
+/*! @{ */
+#define USBHSD_DATABUFSTART_DA_BUF_FIXED_MASK (0x3FFFFU)
+#define USBHSD_DATABUFSTART_DA_BUF_FIXED_SHIFT (0U)
+#define USBHSD_DATABUFSTART_DA_BUF_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_FIXED_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_FIXED_MASK)
+#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFC0000U)
+#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (18U)
+#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK)
+/*! @} */
+
+/*! @name LPM - USB Link Power Management */
+/*! @{ */
+#define USBHSD_LPM_HIRD_HW_MASK (0xFU)
+#define USBHSD_LPM_HIRD_HW_SHIFT (0U)
+/*! HIRD_HW - Host Initiated Resume Duration - HW.
+ */
+#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK)
+#define USBHSD_LPM_HIRD_SW_MASK (0xF0U)
+#define USBHSD_LPM_HIRD_SW_SHIFT (4U)
+/*! HIRD_SW - Host Initiated Resume Duration - SW.
+ */
+#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK)
+#define USBHSD_LPM_DATA_PENDING_MASK (0x100U)
+#define USBHSD_LPM_DATA_PENDING_SHIFT (8U)
+/*! DATA_PENDING - Data pending
+ */
+#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK)
+/*! @} */
+
+/*! @name EPSKIP - USB Endpoint Skip */
+/*! @{ */
+#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU)
+#define USBHSD_EPSKIP_SKIP_SHIFT (0U)
+/*! SKIP - Endpoint skip.
+ */
+#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK)
+/*! @} */
+
+/*! @name EPINUSE - USB Endpoint Buffer in use */
+/*! @{ */
+#define USBHSD_EPINUSE_BUF_MASK (0xFFCU)
+#define USBHSD_EPINUSE_BUF_SHIFT (2U)
+/*! BUF - Buffer in use.
+ * 0b0000000000..HW is accessing buffer 0.
+ * 0b0000000001..HW is accessing buffer 1.
+ */
+#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK)
+/*! @} */
+
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration */
+/*! @{ */
+#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU)
+#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U)
+/*! BUF_SB - Buffer in use.
+ * 0b0000000000..Single buffer.
+ * 0b0000000001..Double buffer.
+ */
+#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK)
+/*! @} */
+
+/*! @name INTSTAT - USB Interrupt Status */
+/*! @{ */
+#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U)
+#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U)
+/*! EP0OUT - Control EP0 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK)
+#define USBHSD_INTSTAT_EP0IN_MASK (0x2U)
+#define USBHSD_INTSTAT_EP0IN_SHIFT (1U)
+/*! EP0IN - Control EP0 IN direction.
+ */
+#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK)
+#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U)
+#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U)
+/*! EP1OUT - Control EP1 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK)
+#define USBHSD_INTSTAT_EP1IN_MASK (0x8U)
+#define USBHSD_INTSTAT_EP1IN_SHIFT (3U)
+/*! EP1IN - Control EP1 IN direction.
+ */
+#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK)
+#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U)
+#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U)
+/*! EP2OUT - Control EP2 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK)
+#define USBHSD_INTSTAT_EP2IN_MASK (0x20U)
+#define USBHSD_INTSTAT_EP2IN_SHIFT (5U)
+/*! EP2IN - Control EP2 IN direction.
+ */
+#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK)
+#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U)
+#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U)
+/*! EP3OUT - Control EP3 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK)
+#define USBHSD_INTSTAT_EP3IN_MASK (0x80U)
+#define USBHSD_INTSTAT_EP3IN_SHIFT (7U)
+/*! EP3IN - Control EP3 IN direction.
+ */
+#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK)
+#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U)
+#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U)
+/*! EP4OUT - Control EP4 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK)
+#define USBHSD_INTSTAT_EP4IN_MASK (0x200U)
+#define USBHSD_INTSTAT_EP4IN_SHIFT (9U)
+/*! EP4IN - Control EP4 IN direction.
+ */
+#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK)
+#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U)
+#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U)
+/*! EP5OUT - Control EP5 OUT direction.
+ */
+#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK)
+#define USBHSD_INTSTAT_EP5IN_MASK (0x800U)
+#define USBHSD_INTSTAT_EP5IN_SHIFT (11U)
+/*! EP5IN - Control EP5 IN direction.
+ */
+#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK)
+#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U)
+#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U)
+/*! FRAME_INT - Frame interrupt.
+ */
+#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK)
+#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U)
+#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U)
+/*! DEV_INT - Device status interrupt.
+ */
+#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK)
+/*! @} */
+
+/*! @name INTEN - USB Interrupt Enable */
+/*! @{ */
+#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU)
+#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U)
+/*! EP_INT_EN - End Point Interrupt Enable.
+ */
+#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK)
+#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U)
+#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U)
+/*! FRAME_INT_EN - Frame interrupt.
+ */
+#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK)
+#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U)
+#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U)
+/*! DEV_INT_EN - Device status interrupt.
+ */
+#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK)
+/*! @} */
+
+/*! @name INTSETSTAT - USB Set Interrupt Status */
+/*! @{ */
+#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU)
+#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U)
+/*! EP_SET_INT - End Point Set Interrupt Enable.
+ */
+#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)
+/*! FRAME_SET_INT - Frame interrupt.
+ */
+#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK)
+#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)
+#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U)
+/*! DEV_SET_INT - Device status interrupt.
+ */
+#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK)
+/*! @} */
+
+/*! @name EPTOGGLE - USB Endpoint Toggle */
+/*! @{ */
+#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU)
+#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U)
+/*! TOGGLE - Endpoint data toggle.
+ */
+#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBHSD_Register_Masks */
+
+
+/* USBHSD - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral USBHSD base address */
+ #define USBHSD_BASE (0x50144000u)
+ /** Peripheral USBHSD base address */
+ #define USBHSD_BASE_NS (0x40144000u)
+ /** Peripheral USBHSD base pointer */
+ #define USBHSD ((USBHSD_Type *)USBHSD_BASE)
+ /** Peripheral USBHSD base pointer */
+ #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS)
+ /** Array initializer of USBHSD peripheral base addresses */
+ #define USBHSD_BASE_ADDRS { USBHSD_BASE }
+ /** Array initializer of USBHSD peripheral base pointers */
+ #define USBHSD_BASE_PTRS { USBHSD }
+ /** Array initializer of USBHSD peripheral base addresses */
+ #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS }
+ /** Array initializer of USBHSD peripheral base pointers */
+ #define USBHSD_BASE_PTRS_NS { USBHSD_NS }
+#else
+ /** Peripheral USBHSD base address */
+ #define USBHSD_BASE (0x40144000u)
+ /** Peripheral USBHSD base pointer */
+ #define USBHSD ((USBHSD_Type *)USBHSD_BASE)
+ /** Array initializer of USBHSD peripheral base addresses */
+ #define USBHSD_BASE_ADDRS { USBHSD_BASE }
+ /** Array initializer of USBHSD peripheral base pointers */
+ #define USBHSD_BASE_PTRS { USBHSD }
+#endif
+/** Interrupt vectors for the USBHSD peripheral type */
+#define USBHSD_IRQS { USB0_IRQn }
+/* Backward compatibility */
+#define USBHSD_DEVCMDSTAT_Speed_MASK (USBHSD_DEVCMDSTAT_SPEED_MASK)
+#define USBHSD_DEVCMDSTAT_Speed_SHIFT (USBHSD_DEVCMDSTAT_SPEED_SHIFT)
+#define USBHSD_DEVCMDSTAT_Speed(x) (USBHSD_DEVCMDSTAT_SPEED(x))
+
+
+/*!
+ * @}
+ */ /* end of group USBHSD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBHSDCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBHSDCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
+ __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
+ __I uint32_t STATUS; /**< Status register, offset: 0x8 */
+ __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override Register, offset: 0xC */
+ __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
+ __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
+ union { /* offset: 0x18 */
+ __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
+ __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
+ };
+} USBHSDCD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBHSDCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Control register */
+/*! @{ */
+#define USBHSDCD_CONTROL_IACK_MASK (0x1U)
+#define USBHSDCD_CONTROL_IACK_SHIFT (0U)
+/*! IACK - Interrupt Acknowledge
+ * 0b0..Do not clear the interrupt.
+ * 0b1..Clear the IF bit (interrupt flag).
+ */
+#define USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
+#define USBHSDCD_CONTROL_IF_MASK (0x100U)
+#define USBHSDCD_CONTROL_IF_SHIFT (8U)
+/*! IF - Interrupt Flag
+ * 0b0..No interrupt is pending.
+ * 0b1..An interrupt is pending.
+ */
+#define USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
+#define USBHSDCD_CONTROL_IE_MASK (0x10000U)
+#define USBHSDCD_CONTROL_IE_SHIFT (16U)
+/*! IE - Interrupt Enable
+ * 0b0..Disable interrupts to the system.
+ * 0b1..Enable interrupts to the system.
+ */
+#define USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
+#define USBHSDCD_CONTROL_BC12_MASK (0x20000U)
+#define USBHSDCD_CONTROL_BC12_SHIFT (17U)
+/*! BC12 - BC12
+ * 0b0..Compatible with BC1.1 (default)
+ * 0b1..Compatible with BC1.2
+ */
+#define USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
+#define USBHSDCD_CONTROL_START_MASK (0x1000000U)
+#define USBHSDCD_CONTROL_START_SHIFT (24U)
+/*! START - Start Change Detection Sequence
+ * 0b0..Do not start the sequence. Writes of this value have no effect.
+ * 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
+ */
+#define USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
+#define USBHSDCD_CONTROL_SR_MASK (0x2000000U)
+#define USBHSDCD_CONTROL_SR_SHIFT (25U)
+/*! SR - Software Reset
+ * 0b0..Do not perform a software reset.
+ * 0b1..Perform a software reset.
+ */
+#define USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
+/*! @} */
+
+/*! @name CLOCK - Clock register */
+/*! @{ */
+#define USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
+#define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
+/*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
+ * 0b0..kHz Speed (between 1 kHz and 1023 kHz)
+ * 0b1..MHz Speed (between 1 MHz and 1023 MHz)
+ */
+#define USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
+#define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
+/*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary
+ */
+#define USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
+/*! @} */
+
+/*! @name STATUS - Status register */
+/*! @{ */
+#define USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U)
+#define USBHSDCD_STATUS_SEQ_RES_SHIFT (16U)
+/*! SEQ_RES - Charger Detection Sequence Results
+ * 0b00..No results to report.
+ * 0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
+ * 0b10..Attached to a charging port. The exact meaning depends on bit 18 (value 0: Attached to either a CDP or a
+ * DCP. The charger type detection has not completed. value 1: Attached to a CDP. The charger type
+ * detection has completed.)
+ * 0b11..Attached to a DCP.
+ */
+#define USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
+#define USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
+#define USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U)
+/*! SEQ_STAT - Charger Detection Sequence Status
+ * 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
+ * 0b01..Data pin contact detection is complete.
+ * 0b10..Charging port detection is complete.
+ * 0b11..Charger type detection is complete.
+ */
+#define USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
+#define USBHSDCD_STATUS_ERR_MASK (0x100000U)
+#define USBHSDCD_STATUS_ERR_SHIFT (20U)
+/*! ERR - Error Flag
+ * 0b0..No sequence errors.
+ * 0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.
+ */
+#define USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
+#define USBHSDCD_STATUS_TO_MASK (0x200000U)
+#define USBHSDCD_STATUS_TO_SHIFT (21U)
+/*! TO - Timeout Flag
+ * 0b0..The detection sequence has not been running for over 1s.
+ * 0b1..It has been over 1 s since the data pin contact was detected and debounced.
+ */
+#define USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
+#define USBHSDCD_STATUS_ACTIVE_MASK (0x400000U)
+#define USBHSDCD_STATUS_ACTIVE_SHIFT (22U)
+/*! ACTIVE - Active Status Indicator
+ * 0b0..The sequence is not running.
+ * 0b1..The sequence is running.
+ */
+#define USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
+/*! @} */
+
+/*! @name SIGNAL_OVERRIDE - Signal Override Register */
+/*! @{ */
+#define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)
+#define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)
+/*! PS - Phase Selection
+ * 0b00..No overrides. Bit field must remain at this value during normal USB data communication to prevent
+ * unexpected conditions on USB_DP and USB_DM pins. (Default)
+ * 0b01..Reserved, not for customer use.
+ * 0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin.
+ * 0b11..Reserved, not for customer use.
+ */
+#define USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
+/*! @} */
+
+/*! @name TIMER0 - TIMER0 register */
+/*! @{ */
+#define USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU)
+#define USBHSDCD_TIMER0_TUNITCON_SHIFT (0U)
+/*! TUNITCON - Unit Connection Timer Elapse (in ms)
+ */
+#define USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
+#define USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
+#define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
+/*! TSEQ_INIT - Sequence Initiation Time
+ * 0b0000000000-0b1111111111..0ms - 1023ms
+ */
+#define USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
+/*! @} */
+
+/*! @name TIMER1 - TIMER1 register */
+/*! @{ */
+#define USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
+#define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
+/*! TVDPSRC_ON - Time Period Comparator Enabled
+ * 0b0000000001-0b1111111111..1ms - 1023ms
+ */
+#define USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
+#define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
+/*! TDCD_DBNC - Time Period to Debounce D+ Signal
+ * 0b0000000001-0b1111111111..1ms - 1023ms
+ */
+#define USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
+/*! @} */
+
+/*! @name TIMER2_BC11 - TIMER2_BC11 register */
+/*! @{ */
+#define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
+#define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
+/*! CHECK_DM - Time Before Check of D- Line
+ * 0b0001-0b1111..1ms - 15ms
+ */
+#define USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
+#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
+/*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup
+ * 0b0000000001-0b1111111111..1ms - 1023ms
+ */
+#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+/*! @} */
+
+/*! @name TIMER2_BC12 - TIMER2_BC12 register */
+/*! @{ */
+#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
+#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
+/*! TVDMSRC_ON - TVDMSRC_ON
+ * 0b0000000000-0b0000101000..0ms - 40ms
+ */
+#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
+#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
+/*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD
+ * 0b0000000001-0b1111111111..1ms - 1023ms
+ */
+#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBHSDCD_Register_Masks */
+
+
+/* USBHSDCD - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral USBHSDCD base address */
+ #define USBHSDCD_BASE (0x5013B800u)
+ /** Peripheral USBHSDCD base address */
+ #define USBHSDCD_BASE_NS (0x4013B800u)
+ /** Peripheral USBHSDCD base pointer */
+ #define USBHSDCD ((USBHSDCD_Type *)USBHSDCD_BASE)
+ /** Peripheral USBHSDCD base pointer */
+ #define USBHSDCD_NS ((USBHSDCD_Type *)USBHSDCD_BASE_NS)
+ /** Array initializer of USBHSDCD peripheral base addresses */
+ #define USBHSDCD_BASE_ADDRS { USBHSDCD_BASE }
+ /** Array initializer of USBHSDCD peripheral base pointers */
+ #define USBHSDCD_BASE_PTRS { USBHSDCD }
+ /** Array initializer of USBHSDCD peripheral base addresses */
+ #define USBHSDCD_BASE_ADDRS_NS { USBHSDCD_BASE_NS }
+ /** Array initializer of USBHSDCD peripheral base pointers */
+ #define USBHSDCD_BASE_PTRS_NS { USBHSDCD_NS }
+#else
+ /** Peripheral USBHSDCD base address */
+ #define USBHSDCD_BASE (0x4013B800u)
+ /** Peripheral USBHSDCD base pointer */
+ #define USBHSDCD ((USBHSDCD_Type *)USBHSDCD_BASE)
+ /** Array initializer of USBHSDCD peripheral base addresses */
+ #define USBHSDCD_BASE_ADDRS { USBHSDCD_BASE }
+ /** Array initializer of USBHSDCD peripheral base pointers */
+ #define USBHSDCD_BASE_PTRS { USBHSDCD }
+#endif
+/** Interrupt vectors for the USBHSDCD peripheral type */
+#define USBHSDCD_IRQS { USB_PHYDCD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHSDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBHSH Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer
+ * @{
+ */
+
+/** USBHSH - Register Layout Typedef */
+typedef struct {
+ __I uint32_t CAPLENGTH_CHIPID; /**< Version ID Register, offset: 0x0 */
+ __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */
+ __IO uint32_t HCCPARAMS; /**< INT PTD Base Address, offset: 0x8 */
+ __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */
+ __IO uint32_t ATL_PTD_BASE_ADDR; /**< ATL PTD Base Address, offset: 0x10 */
+ __IO uint32_t ISO_PTD_BASE_ADDR; /**< ISO PTD Base Address, offset: 0x14 */
+ __IO uint32_t INT_PTD_BASE_ADDR; /**< INT PTD Base Address, offset: 0x18 */
+ __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< DATA PAYLOAD Base Address, offset: 0x1C */
+ __IO uint32_t USBCMD; /**< USB Command, offset: 0x20 */
+ __IO uint32_t USBSTS; /**< USB Interrupt Status, offset: 0x24 */
+ __IO uint32_t USBINTR; /**< USB Interrupt Status, offset: 0x28 */
+ __IO uint32_t PORTSC1; /**< Port Status and Control, offset: 0x2C */
+ __IO uint32_t ATL_PTD_DONE_MAP; /**< ATL PTD Done Map, offset: 0x30 */
+ __IO uint32_t ATL_PTD_SKIP_MAP; /**< ATL PTD Skip Map, offset: 0x34 */
+ __IO uint32_t ISO_PTD_DONE_MAP; /**< ISO PTD Done Map, offset: 0x38 */
+ __IO uint32_t ISO_PTD_SKIP_MAP; /**< ISO PTD Skip Map, offset: 0x3C */
+ __IO uint32_t INT_PTD_DONE_MAP; /**< INT PTD Done Map, offset: 0x40 */
+ __IO uint32_t INT_PTD_SKIP_MAP; /**< INT PTD Skip Map, offset: 0x44 */
+ __IO uint32_t LAST_PTD_INUSE; /**< Last PTD in use, offset: 0x48 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t PORTMODE; /**< Port Mode, offset: 0x50 */
+} USBHSH_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBHSH Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSH_Register_Masks USBHSH Register Masks
+ * @{
+ */
+
+/*! @name CAPLENGTH_CHIPID - Version ID Register */
+/*! @{ */
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU)
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U)
+/*! CAPLENGTH - Capability Length.
+ */
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U)
+/*! CHIPID - Chip identification.
+ */
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK)
+/*! @} */
+
+/*! @name HCSPARAMS - Host Controller Structural Parameters */
+/*! @{ */
+#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU)
+#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U)
+/*! N_PORTS - Number of Physical downstream ports.
+ */
+#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK)
+#define USBHSH_HCSPARAMS_PPC_MASK (0x10U)
+#define USBHSH_HCSPARAMS_PPC_SHIFT (4U)
+/*! PPC - Port Power Control
+ */
+#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK)
+#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U)
+#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U)
+/*! P_INDICATOR - Port Indicator Control
+ */
+#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK)
+/*! @} */
+
+/*! @name HCCPARAMS - INT PTD Base Address */
+/*! @{ */
+#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U)
+#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U)
+/*! LPMC - Link Power Management Capability
+ */
+#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK)
+/*! @} */
+
+/*! @name FLADJ_FRINDEX - Frame Length Adjustment */
+/*! @{ */
+#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU)
+#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U)
+/*! FLADJ - Frame Length Timing Value.
+ */
+#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U)
+/*! FRINDEX - Frame Index
+ */
+#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK)
+/*! @} */
+
+/*! @name ATL_PTD_BASE_ADDR - ATL PTD Base Address */
+/*! @{ */
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U)
+/*! ATL_CUR - Current PTD
+ */
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U)
+/*! ATL_BASE - Start of ATL list.
+ */
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK)
+/*! @} */
+
+/*! @name ISO_PTD_BASE_ADDR - ISO PTD Base Address */
+/*! @{ */
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U)
+/*! ISO_FIRST - First PTD in the ISO list
+ */
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U)
+/*! ISO_BASE - Start of ISO PTD list
+ */
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK)
+/*! @} */
+
+/*! @name INT_PTD_BASE_ADDR - INT PTD Base Address */
+/*! @{ */
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U)
+/*! INT_FIRST - First PTD in the INT list
+ */
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U)
+/*! INT_BASE - Start of INT PTD list
+ */
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK)
+/*! @} */
+
+/*! @name DATA_PAYLOAD_BASE_ADDR - DATA PAYLOAD Base Address */
+/*! @{ */
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U)
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U)
+/*! DAT_BASE - Data Payload Section Base Address
+ */
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK)
+/*! @} */
+
+/*! @name USBCMD - USB Command */
+/*! @{ */
+#define USBHSH_USBCMD_RS_MASK (0x1U)
+#define USBHSH_USBCMD_RS_SHIFT (0U)
+/*! RS - Run/Stop
+ * 0b0..Stop
+ * 0b1..Run
+ */
+#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK)
+#define USBHSH_USBCMD_HCRESET_MASK (0x2U)
+#define USBHSH_USBCMD_HCRESET_SHIFT (1U)
+/*! HCRESET - Host Controller Reset
+ */
+#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK)
+#define USBHSH_USBCMD_FLS_MASK (0xCU)
+#define USBHSH_USBCMD_FLS_SHIFT (2U)
+/*! FLS - Frame List Size
+ * 0b00..1024 elements
+ * 0b01..512 elements
+ * 0b10..256 elements
+ * 0b11..
+ */
+#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK)
+#define USBHSH_USBCMD_LHCR_MASK (0x80U)
+#define USBHSH_USBCMD_LHCR_SHIFT (7U)
+/*! LHCR - Light Host Controller Reset
+ */
+#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK)
+#define USBHSH_USBCMD_ATL_EN_MASK (0x100U)
+#define USBHSH_USBCMD_ATL_EN_SHIFT (8U)
+/*! ATL_EN - ATL List enabled
+ */
+#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK)
+#define USBHSH_USBCMD_ISO_EN_MASK (0x200U)
+#define USBHSH_USBCMD_ISO_EN_SHIFT (9U)
+/*! ISO_EN - ISO List enabled
+ */
+#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK)
+#define USBHSH_USBCMD_INT_EN_MASK (0x400U)
+#define USBHSH_USBCMD_INT_EN_SHIFT (10U)
+/*! INT_EN - INT List enabled
+ */
+#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK)
+#define USBHSH_USBCMD_HIRD_MASK (0xF000000U)
+#define USBHSH_USBCMD_HIRD_SHIFT (24U)
+/*! HIRD - Host-Initiated Resume Duration
+ */
+#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK)
+#define USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U)
+#define USBHSH_USBCMD_LPM_RWU_SHIFT (28U)
+/*! LPM_RWU - Remote wake up.
+ */
+#define USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK)
+/*! @} */
+
+/*! @name USBSTS - USB Interrupt Status */
+/*! @{ */
+#define USBHSH_USBSTS_PCD_MASK (0x4U)
+#define USBHSH_USBSTS_PCD_SHIFT (2U)
+/*! PCD - Port Change Detect Interrupt Request
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK)
+#define USBHSH_USBSTS_FLR_MASK (0x8U)
+#define USBHSH_USBSTS_FLR_SHIFT (3U)
+/*! FLR - Frame List Rollover Interrupt Request
+ */
+#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK)
+#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U)
+#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U)
+/*! ATL_IRQ - ATL Interrupt Request Interrupt Request
+ * 0b0..No ATL PTD event occurred.
+ * 0b1..ATL PTD event occurred.
+ */
+#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK)
+#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U)
+#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U)
+/*! ISO_IRQ - ISO Interrupt Request
+ * 0b0..No ISO PTD event occurred.
+ * 0b1..ISO PTD event occurred.
+ */
+#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK)
+#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U)
+#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U)
+/*! INT_IRQ - INT Interrupt Request
+ * 0b0..No INT PTD event occurred.
+ * 0b1..INT PTD event occurred.
+ */
+#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK)
+#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U)
+#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U)
+/*! SOF_IRQ - SOF Interrupt Request
+ */
+#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK)
+/*! @} */
+
+/*! @name USBINTR - USB Interrupt Status */
+/*! @{ */
+#define USBHSH_USBINTR_PCDE_MASK (0x4U)
+#define USBHSH_USBINTR_PCDE_SHIFT (2U)
+/*! PCDE - Port Change Detect Interrupt Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK)
+#define USBHSH_USBINTR_FLRE_MASK (0x8U)
+#define USBHSH_USBINTR_FLRE_SHIFT (3U)
+/*! FLRE - Frame List Rollover Interrupt Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK)
+#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U)
+#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U)
+/*! ATL_IRQ_E - ATL Interrupt Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK)
+#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U)
+#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U)
+/*! ISO_IRQ_E - ISO Interrupt Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK)
+#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U)
+#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U)
+/*! INT_IRQ_E - INT Interrupt Enable
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK)
+#define USBHSH_USBINTR_SOF_E_MASK (0x80000U)
+#define USBHSH_USBINTR_SOF_E_SHIFT (19U)
+/*! SOF_E - SOF Interrupt Request
+ */
+#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK)
+/*! @} */
+
+/*! @name PORTSC1 - Port Status and Control */
+/*! @{ */
+#define USBHSH_PORTSC1_CCS_MASK (0x1U)
+#define USBHSH_PORTSC1_CCS_SHIFT (0U)
+/*! CCS - Current Connect Status
+ * 0b0..No Device is present
+ * 0b1..Device is present
+ */
+#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK)
+#define USBHSH_PORTSC1_CSC_MASK (0x2U)
+#define USBHSH_PORTSC1_CSC_SHIFT (1U)
+/*! CSC - Connect Status Change
+ * 0b0..CCS value has not changed
+ * 0b1..CCS value has changed
+ */
+#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK)
+#define USBHSH_PORTSC1_PED_MASK (0x4U)
+#define USBHSH_PORTSC1_PED_SHIFT (2U)
+/*! PED - Port Enabled/Disabled
+ * 0b0..Port Disabled
+ * 0b1..Port Enabled
+ */
+#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK)
+#define USBHSH_PORTSC1_PEDC_MASK (0x8U)
+#define USBHSH_PORTSC1_PEDC_SHIFT (3U)
+/*! PEDC - Port Enabled/Disabled Change
+ * 0b0..PED value has not changed
+ * 0b1..PED value has changed
+ */
+#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK)
+#define USBHSH_PORTSC1_OCA_MASK (0x10U)
+#define USBHSH_PORTSC1_OCA_SHIFT (4U)
+/*! OCA - Over-current active
+ * 0b0..Port does not have an over-current condition
+ * 0b1..Port has an over-current condition
+ */
+#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK)
+#define USBHSH_PORTSC1_OCC_MASK (0x20U)
+#define USBHSH_PORTSC1_OCC_SHIFT (5U)
+/*! OCC - Over-current active
+ * 0b0..OCA value has not changed
+ * 0b1..OCA value has changed
+ */
+#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK)
+#define USBHSH_PORTSC1_FPR_MASK (0x40U)
+#define USBHSH_PORTSC1_FPR_SHIFT (6U)
+/*! FPR - Force Port Resume
+ * 0b0..No Resume (K-state) detected or driven on the port.
+ * 0b1..Resume (K-state) detected or driven on the port.
+ */
+#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK)
+#define USBHSH_PORTSC1_SUSP_MASK (0x80U)
+#define USBHSH_PORTSC1_SUSP_SHIFT (7U)
+/*! SUSP - Suspend
+ * 0b0..Enabled port is not suspended
+ * 0b1..Enabled port is in the L1 or L2 suspend state
+ */
+#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK)
+#define USBHSH_PORTSC1_PR_MASK (0x100U)
+#define USBHSH_PORTSC1_PR_SHIFT (8U)
+/*! PR - Port Reset
+ * 0b0..Port is not in the reset state
+ * 0b1..Port is in the reset state
+ */
+#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK)
+#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U)
+#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U)
+/*! SUS_L1 - Suspend using L1
+ * 0b0..Suspend using L2
+ * 0b1..Suspend using L1
+ */
+#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK)
+#define USBHSH_PORTSC1_LS_MASK (0xC00U)
+#define USBHSH_PORTSC1_LS_SHIFT (10U)
+/*! LS - Line Status
+ */
+#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK)
+#define USBHSH_PORTSC1_PP_MASK (0x1000U)
+#define USBHSH_PORTSC1_PP_SHIFT (12U)
+/*! PP - Port Power
+ */
+#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK)
+#define USBHSH_PORTSC1_PIC_MASK (0xC000U)
+#define USBHSH_PORTSC1_PIC_SHIFT (14U)
+/*! PIC - Port Indicator Control
+ * 0b00..Port Indicators are off
+ * 0b01..Amber
+ * 0b10..Green
+ * 0b11..Undefined
+ */
+#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK)
+#define USBHSH_PORTSC1_PTC_MASK (0xF0000U)
+#define USBHSH_PORTSC1_PTC_SHIFT (16U)
+/*! PTC - Port Test Control
+ * 0b0000..Test mode not enabled
+ * 0b0001..Test J_STATE
+ * 0b0010..Test K_STATE
+ * 0b0011..TEST SE0_NAK
+ * 0b0100..Test_Packet
+ * 0b0101..Test Force_Enable
+ */
+#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK)
+#define USBHSH_PORTSC1_PSPD_MASK (0x300000U)
+#define USBHSH_PORTSC1_PSPD_SHIFT (20U)
+/*! PSPD - Port Speed
+ * 0b00..Reserved
+ * 0b01..Full-speed
+ * 0b10..High-speed
+ * 0b11..Reserved
+ */
+#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK)
+#define USBHSH_PORTSC1_WOO_MASK (0x400000U)
+#define USBHSH_PORTSC1_WOO_SHIFT (22U)
+/*! WOO - Wake on overcurrent enable
+ */
+#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK)
+#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U)
+#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U)
+/*! SUS_STAT - Suspend Status
+ * 0b00..State transition was successful (ACK)
+ * 0b01..Device was unable to enter the L1 state at this time (NYET)
+ * 0b10..Device does not support the L1 state (STALL)
+ * 0b11..Timeout/Error - Device failed to respond or an error occurred.
+ */
+#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK)
+#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U)
+#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U)
+/*! DEV_ADD - Device Address for LPM tokens
+ */
+#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK)
+/*! @} */
+
+/*! @name ATL_PTD_DONE_MAP - ATL PTD Done Map */
+/*! @{ */
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU)
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U)
+/*! ATL_DONE - ATL Done
+ */
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK)
+/*! @} */
+
+/*! @name ATL_PTD_SKIP_MAP - ATL PTD Skip Map */
+/*! @{ */
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU)
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U)
+/*! ATL_SKIP - ATL PTD Skip Map
+ */
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK)
+/*! @} */
+
+/*! @name ISO_PTD_DONE_MAP - ISO PTD Done Map */
+/*! @{ */
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU)
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U)
+/*! ISO_DONE - ISO Done
+ */
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK)
+/*! @} */
+
+/*! @name ISO_PTD_SKIP_MAP - ISO PTD Skip Map */
+/*! @{ */
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU)
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U)
+/*! ISO_SKIP - ISO Skip
+ */
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK)
+/*! @} */
+
+/*! @name INT_PTD_DONE_MAP - INT PTD Done Map */
+/*! @{ */
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU)
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U)
+/*! INT_DONE - INT Done
+ */
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK)
+/*! @} */
+
+/*! @name INT_PTD_SKIP_MAP - INT PTD Skip Map */
+/*! @{ */
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU)
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U)
+/*! INT_SKIP - INT Skip
+ */
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK)
+/*! @} */
+
+/*! @name LAST_PTD_INUSE - Last PTD in use */
+/*! @{ */
+#define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK (0x1FU)
+#define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT (0U)
+/*! ATL_LAST - Last PTD in ATL list
+ */
+#define USBHSH_LAST_PTD_INUSE_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK)
+#define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK (0x1F00U)
+#define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT (8U)
+/*! ISO_LAST - Last PTD in ISO list
+ */
+#define USBHSH_LAST_PTD_INUSE_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK)
+#define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK (0x1F0000U)
+#define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT (16U)
+/*! INT_LAST - Last PTD in INT list
+ */
+#define USBHSH_LAST_PTD_INUSE_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK)
+/*! @} */
+
+/*! @name PORTMODE - Port Mode */
+/*! @{ */
+#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)
+#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U)
+/*! DEV_ENABLE - If this bit is set to one, the port will behave as a USB device. If this bit is set
+ * to zero, the port will be controlled by the USB host block.
+ */
+#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBHSH_Register_Masks */
+
+
+/* USBHSH - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral USBHSH base address */
+ #define USBHSH_BASE (0x50145000u)
+ /** Peripheral USBHSH base address */
+ #define USBHSH_BASE_NS (0x40145000u)
+ /** Peripheral USBHSH base pointer */
+ #define USBHSH ((USBHSH_Type *)USBHSH_BASE)
+ /** Peripheral USBHSH base pointer */
+ #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS)
+ /** Array initializer of USBHSH peripheral base addresses */
+ #define USBHSH_BASE_ADDRS { USBHSH_BASE }
+ /** Array initializer of USBHSH peripheral base pointers */
+ #define USBHSH_BASE_PTRS { USBHSH }
+ /** Array initializer of USBHSH peripheral base addresses */
+ #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS }
+ /** Array initializer of USBHSH peripheral base pointers */
+ #define USBHSH_BASE_PTRS_NS { USBHSH_NS }
+#else
+ /** Peripheral USBHSH base address */
+ #define USBHSH_BASE (0x40145000u)
+ /** Peripheral USBHSH base pointer */
+ #define USBHSH ((USBHSH_Type *)USBHSH_BASE)
+ /** Array initializer of USBHSH peripheral base addresses */
+ #define USBHSH_BASE_ADDRS { USBHSH_BASE }
+ /** Array initializer of USBHSH peripheral base pointers */
+ #define USBHSH_BASE_PTRS { USBHSH }
+#endif
+/** Interrupt vectors for the USBHSH peripheral type */
+#define USBHSH_IRQS { USB0_IRQn }
+#define USBHSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHSH_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBPHY Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
+ * @{
+ */
+
+/** USBPHY - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PWD; /**< Power Down, offset: 0x0 */
+ __IO uint32_t PWD_SET; /**< Power Down Register Set, offset: 0x4 */
+ __IO uint32_t PWD_CLR; /**< Power Down Register Clear, offset: 0x8 */
+ __IO uint32_t PWD_TOG; /**< Power Down Register Toggle, offset: 0xC */
+ __IO uint32_t TX; /**< TX Control, offset: 0x10 */
+ __IO uint32_t TX_SET; /**< TX Control Set, offset: 0x14 */
+ __IO uint32_t TX_CLR; /**< TX Control Clear, offset: 0x18 */
+ __IO uint32_t TX_TOG; /**< TX Control Toggle, offset: 0x1C */
+ __IO uint32_t RX; /**< RX Control, offset: 0x20 */
+ __IO uint32_t RX_SET; /**< RX Control Set, offset: 0x24 */
+ __IO uint32_t RX_CLR; /**< RX Control Clear, offset: 0x28 */
+ __IO uint32_t RX_TOG; /**< RX Control Toggle, offset: 0x2C */
+ __IO uint32_t CTRL; /**< General Purpose Control, offset: 0x30 */
+ __IO uint32_t CTRL_SET; /**< General Purpose Control Set, offset: 0x34 */
+ __IO uint32_t CTRL_CLR; /**< General Purpose Control Clear, offset: 0x38 */
+ __IO uint32_t CTRL_TOG; /**< General Purpose Control Toggle, offset: 0x3C */
+ __I uint32_t STATUS; /**< Status, offset: 0x40 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t DEBUG0; /**< Debug 0, offset: 0x50 */
+ __IO uint32_t DEBUG0_SET; /**< Debug 0 Set, offset: 0x54 */
+ __IO uint32_t DEBUG0_CLR; /**< Debug Clear, offset: 0x58 */
+ __IO uint32_t DEBUG0_TOG; /**< Debug Toggle, offset: 0x5C */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t DEBUG1; /**< UTMI Debug 1, offset: 0x70 */
+ __IO uint32_t DEBUG1_SET; /**< UTMI Debug 1 Set, offset: 0x74 */
+ __IO uint32_t DEBUG1_CLR; /**< UTMI Debug 1 Clear, offset: 0x78 */
+ __IO uint32_t DEBUG1_TOG; /**< UTMI Debug 1 Toggle, offset: 0x7C */
+ __I uint32_t VERSION; /**< Version, offset: 0x80 */
+ uint8_t RESERVED_2[28];
+ __IO uint32_t PLL_SIC; /**< PLL Control/Status, offset: 0xA0 */
+ __IO uint32_t PLL_SIC_SET; /**< PLL Control/Status Set, offset: 0xA4 */
+ __IO uint32_t PLL_SIC_CLR; /**< PLL Control/Status Clear, offset: 0xA8 */
+ __IO uint32_t PLL_SIC_TOG; /**< PLL Control/Status Toggle, offset: 0xAC */
+ uint8_t RESERVED_3[16];
+ __IO uint32_t USB1_VBUS_DETECT; /**< VBUS detect, offset: 0xC0 */
+ __IO uint32_t USB1_VBUS_DETECT_SET; /**< VBUS detect Set, offset: 0xC4 */
+ __IO uint32_t USB1_VBUS_DETECT_CLR; /**< VBUS detect Clear, offset: 0xC8 */
+ __IO uint32_t USB1_VBUS_DETECT_TOG; /**< VBUS detect Toggle, offset: 0xCC */
+ __I uint32_t USB1_VBUS_DET_STAT; /**< VBUS Detect Status, offset: 0xD0 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t USB1_CHRG_DETECT; /**< Charger Detect Control, offset: 0xE0 */
+ __IO uint32_t USB1_CHRG_DETECT_SET; /**< Charger Detect Control Set, offset: 0xE4 */
+ __IO uint32_t USB1_CHRG_DETECT_CLR; /**< Charger Detect Control Clear, offset: 0xE8 */
+ __IO uint32_t USB1_CHRG_DETECT_TOG; /**< Charger Detect Control Toggle, offset: 0xEC */
+ __I uint32_t USB1_CHRG_DET_STAT; /**< Charge Detect Status, offset: 0xF0 */
+ uint8_t RESERVED_5[12];
+ __IO uint32_t ANACTRL; /**< Analog Control, offset: 0x100 */
+ __IO uint32_t ANACTRL_SET; /**< Analog Control Set, offset: 0x104 */
+ __IO uint32_t ANACTRL_CLR; /**< Analog Control Clear, offset: 0x108 */
+ __IO uint32_t ANACTRL_TOG; /**< Analog Control Toggle, offset: 0x10C */
+ __IO uint32_t USB1_LOOPBACK; /**< USB PHY Loopback Control/Status, offset: 0x110 */
+ __IO uint32_t USB1_LOOPBACK_SET; /**< USB PHY Loopback Control/Status Set, offset: 0x114 */
+ __IO uint32_t USB1_LOOPBACK_CLR; /**< USB PHY Loopback Control/Status Clear, offset: 0x118 */
+ __IO uint32_t USB1_LOOPBACK_TOG; /**< USB PHY Loopback Control/Status Toggle, offset: 0x11C */
+ __IO uint32_t USB1_LOOPBACK_HSFSCNT; /**< Loopback Packet Number Select, offset: 0x120 */
+ __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET; /**< USB PHY Loopback Packet Number Select Set, offset: 0x124 */
+ __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR; /**< USB PHY Loopback Packet Number Select Clear, offset: 0x128 */
+ __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG; /**< USB PHY Loopback Packet Number Select Toggle, offset: 0x12C */
+ __IO uint32_t TRIM_OVERRIDE_EN; /**< Trim Override Enable, offset: 0x130 */
+ __IO uint32_t TRIM_OVERRIDE_EN_SET; /**< Trim Set, offset: 0x134 */
+ __IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< Trim Clear, offset: 0x138 */
+ __IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< Trim Toggle, offset: 0x13C */
+} USBPHY_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBPHY Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
+ * @{
+ */
+
+/*! @name PWD - Power Down */
+/*! @{ */
+#define USBPHY_PWD_TXPWDFS_MASK (0x400U)
+#define USBPHY_PWD_TXPWDFS_SHIFT (10U)
+/*! TXPWDFS - Power down USB FS drivers.
+ * 0b0..Normal operation
+ * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
+ */
+#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
+#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
+#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
+/*! TXPWDIBIAS - Power down USB PHY current bias block.
+ * 0b0..Normal operation
+ * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB
+ * is in suspend mode. This effectively powers down the entire USB transmit path.
+ */
+#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
+#define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
+/*! TXPWDV2I - Power down USB PHY V-I converter and current mirror.
+ * 0b0..Normal operation
+ * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
+ */
+#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
+#define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
+#define USBPHY_PWD_RXPWDENV_SHIFT (17U)
+/*! RXPWDENV - Power down USB HS receiver envelope detector.
+ * 0b0..Normal operation
+ * 0b1..Power down the USB high-speed receiver envelope detector (squelch signal)
+ */
+#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
+#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
+#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
+/*! RXPWD1PT1 - Power down USB FS differential receiver.
+ * 0b0..Normal operation
+ * 0b1..Power down the USB full-speed differential receiver
+ */
+#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
+#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
+#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
+/*! RXPWDDIFF - Power down USB HS differential receiver.
+ * 0b0..Normal operation
+ * 0b1..Power down the USB high-speed differential receiver
+ */
+#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
+#define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
+#define USBPHY_PWD_RXPWDRX_SHIFT (20U)
+/*! RXPWDRX - Power down USB PHY receiver except the FS differential.
+ * 0b0..Normal operation
+ * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
+ */
+#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
+/*! @} */
+
+/*! @name PWD_SET - Power Down Register Set */
+/*! @{ */
+#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
+#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
+/*! TXPWDFS - Power down USB FS drivers.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding PWD bit
+ */
+#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
+#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
+#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
+/*! TXPWDIBIAS - Power down USB PHY current bias block.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding PWD bit
+ */
+#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
+#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
+/*! TXPWDV2I - Power down USB PHY V-I converter and current mirror.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding PWD bit
+ */
+#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
+#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
+#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
+/*! RXPWDENV - Power down USB HS receiver envelope detector.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding PWD bit
+ */
+#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
+#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
+#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
+/*! RXPWD1PT1 - Power down USB FS differential receiver.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding PWD bit
+ */
+#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
+#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
+#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
+/*! RXPWDDIFF - Power down USB HS differential receiver.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding PWD bit
+ */
+#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
+#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
+#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
+/*! RXPWDRX - Power down USB PHY receiver except the FS differential.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding PWD bit
+ */
+#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
+/*! @} */
+
+/*! @name PWD_CLR - Power Down Register Clear */
+/*! @{ */
+#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
+#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
+/*! TXPWDFS - Power down USB FS drivers.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding PWD bit
+ */
+#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
+#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
+#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
+/*! TXPWDIBIAS - Power down USB PHY current bias block.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding PWD bit
+ */
+#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
+#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
+/*! TXPWDV2I - Power down USB PHY V-I converter and current mirror.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding PWD bit
+ */
+#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
+#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
+#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
+/*! RXPWDENV - Power down USB HS receiver envelope detector.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding PWD bit
+ */
+#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
+#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
+#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
+/*! RXPWD1PT1 - Power down USB FS differential receiver.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding PWD bit
+ */
+#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
+#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
+#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
+/*! RXPWDDIFF - Power down USB HS differential receiver.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding PWD bit
+ */
+#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
+#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
+#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
+/*! RXPWDRX - Power down USB PHY receiver except the FS differential.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding PWD bit
+ */
+#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
+/*! @} */
+
+/*! @name PWD_TOG - Power Down Register Toggle */
+/*! @{ */
+#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
+#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
+/*! TXPWDFS - Power down USB FS drivers.
+ */
+#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
+#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
+#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
+/*! TXPWDIBIAS - Power down USB PHY current bias block.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding PWD bit
+ */
+#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
+#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
+/*! TXPWDV2I - Power down USB PHY V-I converter and current mirror.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding PWD bit
+ */
+#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
+#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
+#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
+/*! RXPWDENV - Power down USB HS receiver envelope detector.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding PWD bit
+ */
+#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
+#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
+#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
+/*! RXPWD1PT1 - Power down USB FS differential receiver.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding PWD bit
+ */
+#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
+#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
+#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
+/*! RXPWDDIFF - Power down USB HS differential receiver.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding PWD bit
+ */
+#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
+#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
+#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
+/*! RXPWDRX - Power down USB PHY receiver except the FS differential.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding PWD bit
+ */
+#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
+/*! @} */
+
+/*! @name TX - TX Control */
+/*! @{ */
+#define USBPHY_TX_D_CAL_MASK (0xFU)
+#define USBPHY_TX_D_CAL_SHIFT (0U)
+/*! D_CAL - Current Trim decode.
+ */
+#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TX_TXCAL45DM_MASK (0xF00U)
+#define USBPHY_TX_TXCAL45DM_SHIFT (8U)
+/*! TXCAL45DM - DM series termination resistance trim.
+ */
+#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK)
+#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U)
+#define USBPHY_TX_TXENCAL45DN_SHIFT (13U)
+/*! TXENCAL45DN - DN series Resistance calibration.
+ */
+#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK)
+#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
+#define USBPHY_TX_TXCAL45DP_SHIFT (16U)
+/*! TXCAL45DP - DP series termination resistance trim.
+ */
+#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
+#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U)
+#define USBPHY_TX_TXENCAL45DP_SHIFT (21U)
+/*! TXENCAL45DP - DP series resistance calibration
+ */
+#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK)
+/*! @} */
+
+/*! @name TX_SET - TX Control Set */
+/*! @{ */
+#define USBPHY_TX_SET_D_CAL_MASK (0xFU)
+#define USBPHY_TX_SET_D_CAL_SHIFT (0U)
+/*! D_CAL - Current Trim decode.
+ * 0b0000..No effect
+ * 0b0001..Sets the corresponding TX bit
+ */
+#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
+#define USBPHY_TX_SET_TXENCAL45DM_MASK (0xF00U)
+#define USBPHY_TX_SET_TXENCAL45DM_SHIFT (8U)
+/*! TXENCAL45DM - DM series termination resistance trim.
+ * 0b0000..No effect
+ * 0b0001..Sets the corresponding TX bit
+ */
+#define USBPHY_TX_SET_TXENCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DM_SHIFT)) & USBPHY_TX_SET_TXENCAL45DM_MASK)
+#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U)
+#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U)
+/*! TXENCAL45DN - Enable resistance calibration on DN.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding TX bit
+ */
+#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK)
+#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
+#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
+/*! TXCAL45DP - DP series termination resistance trim.
+ * 0b0000..No effect
+ * 0b0001..Sets the corresponding TX bit
+ */
+#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
+#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U)
+#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U)
+/*! TXENCAL45DP - Enable resistance calibration on DP
+ * 0b0..No effect
+ * 0b1..Sets the corresponding TX bit
+ */
+#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK)
+/*! @} */
+
+/*! @name TX_CLR - TX Control Clear */
+/*! @{ */
+#define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
+#define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
+/*! D_CAL - Current Trim decode.
+ * 0b0000..No effect
+ * 0b0001..Clears the corresponding TX bit
+ */
+#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
+#define USBPHY_TX_CLR_TXENCAL45DM_MASK (0xF00U)
+#define USBPHY_TX_CLR_TXENCAL45DM_SHIFT (8U)
+/*! TXENCAL45DM - DM series termination resistance trim.
+ * 0b0000..No effect
+ * 0b0001..Clears the corresponding TX bit
+ */
+#define USBPHY_TX_CLR_TXENCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DM_MASK)
+#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U)
+#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U)
+/*! TXENCAL45DN - Clears Enable resistance calibration on DN.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding TX bit
+ */
+#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK)
+#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
+#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
+/*! TXCAL45DP - DP series termination resistance trim.
+ * 0b0000..No effect
+ * 0b0001..Clears the corresponding TX bit
+ */
+#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
+#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U)
+#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U)
+/*! TXENCAL45DP - Enable resistance calibration on DP
+ * 0b0..No effect
+ * 0b1..Clears the corresponding TX bit
+ */
+#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK)
+/*! @} */
+
+/*! @name TX_TOG - TX Control Toggle */
+/*! @{ */
+#define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
+#define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
+/*! D_CAL - Current Trim decode.
+ * 0b0000..No effect
+ * 0b0001..Toggles the corresponding TX bit
+ */
+#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
+#define USBPHY_TX_TOG_TXENCAL45DM_MASK (0xF00U)
+#define USBPHY_TX_TOG_TXENCAL45DM_SHIFT (8U)
+/*! TXENCAL45DM - DM series termination resistance trim.
+ * 0b0000..No effect
+ * 0b0001..Toggles the corresponding TX bit
+ */
+#define USBPHY_TX_TOG_TXENCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DM_MASK)
+#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U)
+#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U)
+/*! TXENCAL45DN - Enable resistance calibration on DN.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding TX bit
+ */
+#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK)
+#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
+#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
+/*! TXCAL45DP - DP series termination resistance trim.
+ * 0b0000..No effect
+ * 0b0001..Toggles the corresponding TX bit
+ */
+#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
+#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U)
+#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U)
+/*! TXENCAL45DP - Enable resistance calibration on DP
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding TX bit
+ */
+#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK)
+/*! @} */
+
+/*! @name RX - RX Control */
+/*! @{ */
+#define USBPHY_RX_ENVADJ_MASK (0x7U)
+#define USBPHY_RX_ENVADJ_SHIFT (0U)
+/*! ENVADJ - Envelope detector trip point.
+ * 0b000..Trip-Level Voltage is 0.1000 V
+ * 0b001..Trip-Level Voltage is 0.1125 V
+ * 0b010..Trip-Level Voltage is 0.1250 V
+ * 0b011..Trip-Level Voltage is 0.0875 V
+ * 0b100-0b111..Reserved
+ */
+#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
+#define USBPHY_RX_DISCONADJ_MASK (0x70U)
+#define USBPHY_RX_DISCONADJ_SHIFT (4U)
+/*! DISCONADJ - Disconnect detector trip point.
+ * 0b000..Trip-Level Voltage is 0.56875 V
+ * 0b001..Trip-Level Voltage is 0.55000 V
+ * 0b010..Trip-Level Voltage is 0.58125 V
+ * 0b011..Trip-Level Voltage is 0.60000 V
+ * 0b100..reserved
+ * 0b101..reserved
+ * 0b110..reserved
+ * 0b111..reserved
+ */
+#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
+#define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
+#define USBPHY_RX_RXDBYPASS_SHIFT (22U)
+/*! RXDBYPASS - DM bypass
+ * 0b0..Normal operation
+ * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
+ */
+#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
+/*! @} */
+
+/*! @name RX_SET - RX Control Set */
+/*! @{ */
+#define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
+#define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
+/*! ENVADJ - Envelope detector trip point.
+ * 0b000..No effect
+ * 0b001..Sets the corresponding TX bit
+ */
+#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
+#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
+#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
+/*! DISCONADJ - Disconnect detector trip point.
+ * 0b000..No effect
+ * 0b001..Sets the corresponding TX bit
+ */
+#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
+#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
+#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
+/*! RXDBYPASS - DM bypass
+ * 0b0..No effect
+ * 0b1..Sets the corresponding TX bit
+ */
+#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
+/*! @} */
+
+/*! @name RX_CLR - RX Control Clear */
+/*! @{ */
+#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
+#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
+/*! ENVADJ - Envelope detector trip point.
+ * 0b000..No effect
+ * 0b001..Clears the corresponding TX bit
+ */
+#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
+#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
+#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
+/*! DISCONADJ - Disconnect detector trip point.
+ * 0b000..No effect
+ * 0b001..Clears the corresponding TX bit
+ */
+#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
+#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
+#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
+/*! RXDBYPASS - DM bypass
+ * 0b0..No effect
+ * 0b1..Clears the corresponding TX bit
+ */
+#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
+/*! @} */
+
+/*! @name RX_TOG - RX Control Toggle */
+/*! @{ */
+#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
+#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
+/*! ENVADJ - Envelope detector trip point.
+ * 0b000..No effect
+ * 0b001..Toggles the corresponding TX bit
+ */
+#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
+#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
+#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
+/*! DISCONADJ - Disconnect detector trip point.
+ * 0b000..No effect
+ * 0b001..Toggles the corresponding TX bit
+ */
+#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
+#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
+#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
+/*! RXDBYPASS - DM bypass
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding TX bit
+ */
+#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
+/*! @} */
+
+/*! @name CTRL - General Purpose Control */
+/*! @{ */
+#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
+#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
+/*! ENHOSTDISCONDETECT - Disconnect detect.
+ */
+#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
+/*! HOSTDISCONDETECT_IRQ - Device disconnect indication.
+ */
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
+#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U)
+#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U)
+/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection.
+ * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
+ * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
+ */
+#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
+#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
+/*! DEVPLUGIN_IRQ - Device connected indicator
+ */
+#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
+#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
+/*! ENUTMILEVEL2 - Enable level 2 operation
+ */
+#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
+#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
+/*! ENUTMILEVEL3 - Enable level 2 operation
+ */
+#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U)
+#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U)
+/*! AUTORESUME_EN - Enable autoresume
+ */
+#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
+/*! ENAUTOCLR_CLKGATE - Autoclear clock gate.
+ */
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
+/*! ENAUTOCLR_PHY_PWD - Autoclear PWD register bits.
+ */
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
+#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
+/*! FSDLL_RST_EN - Reset FSDLL lock
+ */
+#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
+/*! HOST_FORCE_LS_SE0 - FS EOP low-speed timing
+ */
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
+#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
+/*! UTMI_SUSPENDM - UTMI suspend
+ */
+#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
+#define USBPHY_CTRL_CLKGATE_SHIFT (30U)
+/*! CLKGATE - UTMI clock gate
+ */
+#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
+#define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
+#define USBPHY_CTRL_SFTRST_SHIFT (31U)
+/*! SFTRST - Software reset
+ */
+#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
+/*! @} */
+
+/*! @name CTRL_SET - General Purpose Control Set */
+/*! @{ */
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
+/*! ENHOSTDISCONDETECT - Disconnect detect.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
+#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
+/*! HOSTDISCONDETECT_IRQ - Device disconnect indication.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U)
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U)
+/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
+/*! DEVPLUGIN_IRQ - Device connected indicator
+ * 0b0..No effect
+ * 0b1..Sets the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
+#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
+/*! ENUTMILEVEL2 - Enable level 2 operation
+ * 0b0..No effect
+ * 0b1..Sets the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
+#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
+/*! ENUTMILEVEL3 - Enable level 2 operation
+ * 0b0..No effect
+ * 0b1..the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U)
+#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U)
+/*! AUTORESUME_EN - Enable autoresume
+ * 0b0..No effect
+ * 0b1..Sets the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
+/*! ENAUTOCLR_CLKGATE - Autoclear clock gate.
+ * 0b0..No effect
+ * 0b1..the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
+/*! ENAUTOCLR_PHY_PWD - Autoclear PWD register bits.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
+#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
+/*! FSDLL_RST_EN - Reset FSDLL lock
+ * 0b0..No effect
+ * 0b1..Sets the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
+/*! HOST_FORCE_LS_SE0 - FS EOP low-speed timing
+ */
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
+/*! UTMI_SUSPENDM - UTMI suspend
+ * 0b0..No effect
+ * 0b1..Sets the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
+#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
+/*! CLKGATE - UTMI clock gate
+ * 0b0..No effect
+ * 0b1..the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
+#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
+#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
+/*! SFTRST - Software reset
+ * 0b0..No effect
+ * 0b1..Sets the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
+/*! @} */
+
+/*! @name CTRL_CLR - General Purpose Control Clear */
+/*! @{ */
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
+/*! ENHOSTDISCONDETECT - Disconnect detect.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
+#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
+/*! HOSTDISCONDETECT_IRQ - Device disconnect indication.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U)
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U)
+/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
+/*! DEVPLUGIN_IRQ - Device connected indicator
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
+/*! ENUTMILEVEL2 - Enable level 2 operation
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
+/*! ENUTMILEVEL3 - Enable level 2 operation
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U)
+#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U)
+/*! AUTORESUME_EN - Enable autoresume
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
+/*! ENAUTOCLR_CLKGATE - Autoclear clock gate.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
+/*! ENAUTOCLR_PHY_PWD - Autoclear PWD register bits.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
+#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
+/*! FSDLL_RST_EN - Reset FSDLL lock
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
+/*! HOST_FORCE_LS_SE0 - FS EOP low-speed timing
+ */
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
+/*! UTMI_SUSPENDM - UTMI suspend
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
+#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
+/*! CLKGATE - UTMI clock gate
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
+#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
+#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
+/*! SFTRST - Software reset
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
+/*! @} */
+
+/*! @name CTRL_TOG - General Purpose Control Toggle */
+/*! @{ */
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
+/*! ENHOSTDISCONDETECT - Disconnect detect.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
+#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
+/*! HOSTDISCONDETECT_IRQ - Device disconnect indication.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U)
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U)
+/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
+/*! DEVPLUGIN_IRQ - Device connected indicator
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
+/*! ENUTMILEVEL2 - Enable level 2 operation
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
+/*! ENUTMILEVEL3 - Enable level 2 operation
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U)
+#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U)
+/*! AUTORESUME_EN - Enable autoresume
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
+/*! ENAUTOCLR_CLKGATE - Autoclear clock gate.
+ * 0b0..No effect
+ * 0b1..the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
+/*! ENAUTOCLR_PHY_PWD - Autoclear PWD register bits.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
+#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
+/*! FSDLL_RST_EN - Reset FSDLL lock
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
+/*! HOST_FORCE_LS_SE0 - FS EOP low-speed timing
+ */
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
+/*! UTMI_SUSPENDM - UTMI suspend
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
+#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
+/*! CLKGATE - UTMI clock gate
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
+#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
+#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
+/*! SFTRST - Software reset
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
+/*! @} */
+
+/*! @name STATUS - Status */
+/*! @{ */
+#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
+#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
+/*! HOSTDISCONDETECT_STATUS - Host disconnect status
+ * 0b1..USB cable disconnect has been detected at the local host
+ * 0b0..USB cable disconnect has not been detected at the local host
+ */
+#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
+#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
+#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
+/*! DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection.
+ * 0b0..No attachment to a USB host is detected
+ * 0b1..Cable attachment to a USB host is detected
+ */
+#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
+#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
+#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
+/*! RESUME_STATUS - Resume status
+ */
+#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
+/*! @} */
+
+/*! @name DEBUG0 - Debug 0 */
+/*! @{ */
+#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK (0x2U)
+#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT (1U)
+/*! DEBUG_INTERFACE_HOLD - Debug interface
+ */
+#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK)
+#define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU)
+#define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U)
+/*! HSTPULLDOWN - HS DP/DM pulldown resistance select.
+ */
+#define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U)
+#define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U)
+/*! ENHSTPULLDOWN - Enable Host pulldown
+ */
+#define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG0_TX2RXCOUNT_MASK (0xF00U)
+#define USBPHY_DEBUG0_TX2RXCOUNT_SHIFT (8U)
+/*! TX2RXCOUNT - TX2RXCOUNT
+ */
+#define USBPHY_DEBUG0_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG0_ENTX2RXCOUNT_MASK (0x1000U)
+#define USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT (12U)
+#define USBPHY_DEBUG0_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK (0x1F0000U)
+#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT (16U)
+/*! SQUELCHRESETCOUNT - Squelch reset count
+ */
+#define USBPHY_DEBUG0_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG0_ENSQUELCHRESET_MASK (0x1000000U)
+#define USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT (24U)
+/*! ENSQUELCHRESET - Enable squelch reset
+ */
+#define USBPHY_DEBUG0_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK (0x1E000000U)
+#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT (25U)
+/*! SQUELCHRESETLENGTH - Squelch reset length
+ */
+#define USBPHY_DEBUG0_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK)
+#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK (0x20000000U)
+#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT (29U)
+/*! HOST_RESUME_DEBUG - Host resume
+ */
+#define USBPHY_DEBUG0_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG0_CLKGATE_MASK (0x40000000U)
+#define USBPHY_DEBUG0_CLKGATE_SHIFT (30U)
+/*! CLKGATE - Test clock gate
+ */
+#define USBPHY_DEBUG0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLKGATE_MASK)
+/*! @} */
+
+/*! @name DEBUG0_SET - Debug 0 Set */
+/*! @{ */
+#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
+#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
+/*! DEBUG_INTERFACE_HOLD - Debug interface
+ * 0b0..No effect
+ * 0b1..Sets the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK)
+#define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU)
+#define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U)
+/*! HSTPULLDOWN - HS DP/DM pulldown resistance select.
+ * 0b00..No effect
+ * 0b01..Sets the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U)
+#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U)
+/*! ENHSTPULLDOWN - Enable Host pulldown
+ * 0b00..No effect
+ * 0b01..Sets the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK (0xF00U)
+#define USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT (8U)
+/*! TX2RXCOUNT - TX2RXCOUNT
+ * 0b0000..No effect
+ * 0b0001..Sets the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK (0x1000U)
+#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT (12U)
+/*! ENTX2RXCOUNT - ENTX2RXCOUNT
+ * 0b0..No effect
+ * 0b1..Sets the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
+#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT (16U)
+/*! SQUELCHRESETCOUNT - Squelch reset count
+ * 0b00000..No effect
+ * 0b00001..Sets the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK (0x1000000U)
+#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT (24U)
+/*! ENSQUELCHRESET - Enable squelch reset
+ * 0b0..No effect
+ * 0b1..Sets the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
+#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT (25U)
+/*! SQUELCHRESETLENGTH - Squelch reset length
+ * 0b0000..No effect
+ * 0b0001..Sets the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK)
+#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
+#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT (29U)
+/*! HOST_RESUME_DEBUG - Host resume
+ * 0b0..No effect
+ * 0b1..Sets the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG0_SET_CLKGATE_MASK (0x40000000U)
+#define USBPHY_DEBUG0_SET_CLKGATE_SHIFT (30U)
+/*! CLKGATE - Test clock gate
+ * 0b0..No effect
+ * 0b1..Sets the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG0_SET_CLKGATE_MASK)
+/*! @} */
+
+/*! @name DEBUG0_CLR - Debug Clear */
+/*! @{ */
+#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
+#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
+/*! DEBUG_INTERFACE_HOLD - Debug interface
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK)
+#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU)
+#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U)
+/*! HSTPULLDOWN - HS DP/DM pulldown resistance select.
+ * 0b00..No effect
+ * 0b01..Clears the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U)
+#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U)
+/*! ENHSTPULLDOWN - Enable Host pulldown
+ * 0b00..No effect
+ * 0b01..Clears the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK (0xF00U)
+#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT (8U)
+/*! TX2RXCOUNT - TX2RXCOUNT
+ * 0b0000..No effect
+ * 0b0001..Clears the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK (0x1000U)
+#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT (12U)
+/*! ENTX2RXCOUNT - ENTX2RXCOUNT
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
+#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
+/*! SQUELCHRESETCOUNT - Squelch reset count
+ * 0b00000..No effect
+ * 0b00001..Clears the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK (0x1000000U)
+#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT (24U)
+/*! ENSQUELCHRESET - Enable squelch reset
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
+#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
+/*! SQUELCHRESETLENGTH - Squelch reset length
+ * 0b0000..No effect
+ * 0b0001..Clears the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK)
+#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
+#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
+/*! HOST_RESUME_DEBUG - Host resume
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG0_CLR_CLKGATE_MASK (0x40000000U)
+#define USBPHY_DEBUG0_CLR_CLKGATE_SHIFT (30U)
+/*! CLKGATE - Test clock gate
+ * 0b0..No effect
+ * 0b1..Clears the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLR_CLKGATE_MASK)
+/*! @} */
+
+/*! @name DEBUG0_TOG - Debug Toggle */
+/*! @{ */
+#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
+#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
+/*! DEBUG_INTERFACE_HOLD - Debug interface
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK)
+#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU)
+#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U)
+/*! HSTPULLDOWN - HS DP/DM pulldown resistance select.
+ * 0b00..No effect
+ * 0b01..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U)
+#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U)
+/*! ENHSTPULLDOWN - Enable Host pulldown
+ * 0b00..No effect
+ * 0b01..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK (0xF00U)
+#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT (8U)
+/*! TX2RXCOUNT - TX2RXCOUNT
+ * 0b0000..No effect
+ * 0b0001..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK (0x1000U)
+#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT (12U)
+/*! ENTX2RXCOUNT - ENTX2RXCOUNT
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
+#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
+/*! SQUELCHRESETCOUNT - Squelch reset count
+ * 0b00000..No effect
+ * 0b00001..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK (0x1000000U)
+#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT (24U)
+/*! ENSQUELCHRESET - Enable squelch reset
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
+#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
+/*! SQUELCHRESETLENGTH - Squelch reset length
+ * 0b0000..No effect
+ * 0b0001..the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK)
+#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
+#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
+/*! HOST_RESUME_DEBUG - Host resume
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG0_TOG_CLKGATE_MASK (0x40000000U)
+#define USBPHY_DEBUG0_TOG_CLKGATE_SHIFT (30U)
+/*! CLKGATE - Test clock gate
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding CTRL bit
+ */
+#define USBPHY_DEBUG0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG0_TOG_CLKGATE_MASK)
+/*! @} */
+
+/*! @name DEBUG1 - UTMI Debug 1 */
+/*! @{ */
+#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
+#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
+/*! ENTAILADJVD - Enable delay increment
+ * 0b00..Delay is nominal
+ * 0b01..Delay is +20%
+ * 0b10..Delay is -20%
+ * 0b11..Delay is -40%
+ */
+#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
+#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
+#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT (18U)
+/*! USB2_REFBIAS_VBGADJ - Bandgap adjustment
+ */
+#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK)
+#define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK (0x600000U)
+#define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT (21U)
+/*! USB2_REFBIAS_TST - Bias current control
+ */
+#define USBPHY_DEBUG1_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK)
+/*! @} */
+
+/*! @name DEBUG1_SET - UTMI Debug 1 Set */
+/*! @{ */
+#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
+#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
+/*! ENTAILADJVD - Enable delay increment
+ * 0b00..No effect
+ * 0b01..Sets the corresponding DEBUG1 bit
+ */
+#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
+#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
+#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U)
+/*! USB2_REFBIAS_VBGADJ - Bandgap adjustment
+ * 0b000..No effect
+ * 0b001..Sets the corresponding DEBUG1 bit
+ */
+#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK)
+#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK (0x600000U)
+#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U)
+/*! USB2_REFBIAS_TST - Bias current control
+ * 0b00..No effect
+ * 0b01..Sets the corresponding DEBUG1 bit
+ */
+#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK)
+/*! @} */
+
+/*! @name DEBUG1_CLR - UTMI Debug 1 Clear */
+/*! @{ */
+#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
+#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
+/*! ENTAILADJVD - Enable delay increment
+ * 0b00..No effect
+ * 0b01..Clears the corresponding DEBUG1 bit
+ */
+#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
+#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
+#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U)
+/*! USB2_REFBIAS_VBGADJ - Bandgap adjustment
+ * 0b000..No effect
+ * 0b001..Clears the corresponding DEBUG1 bit
+ */
+#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK)
+#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK (0x600000U)
+#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U)
+/*! USB2_REFBIAS_TST - Bias current control
+ * 0b00..No effect
+ * 0b01..Clears the corresponding DEBUG1 bit
+ */
+#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK)
+/*! @} */
+
+/*! @name DEBUG1_TOG - UTMI Debug 1 Toggle */
+/*! @{ */
+#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
+#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
+/*! ENTAILADJVD - Enable delay increment
+ * 0b00..No effect
+ * 0b01..Clears the corresponding DEBUG1 bit
+ */
+#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
+#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
+#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U)
+/*! USB2_REFBIAS_VBGADJ - Bandgap adjustment
+ * 0b000..No effect
+ * 0b001..Toggles the corresponding DEBUG1 bit
+ */
+#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK)
+#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK (0x600000U)
+#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U)
+/*! USB2_REFBIAS_TST - Bias current control
+ * 0b00..No effect
+ * 0b01..Toggles the corresponding DEBUG1 bit
+ */
+#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK)
+/*! @} */
+
+/*! @name VERSION - Version */
+/*! @{ */
+#define USBPHY_VERSION_STEP_MASK (0xFFFFU)
+#define USBPHY_VERSION_STEP_SHIFT (0U)
+/*! STEP - STEP
+ */
+#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
+#define USBPHY_VERSION_MINOR_MASK (0xFF0000U)
+#define USBPHY_VERSION_MINOR_SHIFT (16U)
+/*! MINOR - MINOR
+ */
+#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
+#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
+#define USBPHY_VERSION_MAJOR_SHIFT (24U)
+/*! MAJOR - MAJOR
+ */
+#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
+/*! @} */
+
+/*! @name PLL_SIC - PLL Control/Status */
+/*! @{ */
+#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U)
+#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U)
+/*! PLL_EN_USB_CLKS - PLL clock enable
+ */
+#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
+#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U)
+#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U)
+/*! PLL_POWER - Power PLL
+ */
+#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U)
+#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U)
+/*! PLL_ENABLE - PLL enable
+ */
+#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U)
+#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U)
+/*! PLL_BYPASS - Bypass USB PLL
+ * 0b0..Use USB PLL
+ * 0b1..Bypass USB PLL
+ */
+#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U)
+#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U)
+/*! REFBIAS_PWD_SEL - Reference bias power control
+ * 0b0..Selects PLL_POWER to control the reference bias
+ * 0b1..Selects REFBIAS_PWD to control the reference bias
+ */
+#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK)
+#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U)
+#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U)
+/*! REFBIAS_PWD - Power down Reference bias
+ */
+#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK)
+#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U)
+#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U)
+/*! PLL_REG_ENABLE - Enable PLL regulator
+ */
+#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK)
+#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U)
+#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U)
+/*! PLL_DIV_SEL - PLL Divider value
+ * 0b000..Divide by 13
+ * 0b001..Divide by 15
+ * 0b010..Divide by 16
+ * 0b011..Divide by 20
+ * 0b100..Divide by 22
+ * 0b101..Divide by 25
+ * 0b110..Divide by 30
+ * 0b111..Divide by 240
+ */
+#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U)
+#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U)
+#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_SIC_SET - PLL Control/Status Set */
+/*! @{ */
+#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U)
+#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
+/*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U)
+#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U)
+/*! PLL_POWER - POWER
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U)
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U)
+/*! PLL_ENABLE - ENABLE
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U)
+#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U)
+/*! PLL_BYPASS - Bypass USB PLL
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U)
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U)
+/*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK)
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U)
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U)
+/*! REFBIAS_PWD - REFBIAS_PWD
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U)
+#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U)
+/*! PLL_REG_ENABLE - PLL_REG_ENABLE
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U)
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U)
+/*! PLL_DIV_SEL - PLL_DIV_SEL
+ * 0b000..No effect
+ * 0b001..Sets the corresponding bit
+ */
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U)
+#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U)
+/*! PLL_LOCK - PLL_LOCK
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_SIC_CLR - PLL Control/Status Clear */
+/*! @{ */
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U)
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
+/*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U)
+#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U)
+/*! PLL_POWER - POWER
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U)
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U)
+/*! PLL_ENABLE - ENABLE
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U)
+#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U)
+/*! PLL_BYPASS - Bypass USB PLL
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U)
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U)
+/*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK)
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U)
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U)
+/*! REFBIAS_PWD - REFBIAS_PWD
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U)
+#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U)
+/*! PLL_REG_ENABLE - PLL_REG_ENABLE
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U)
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U)
+/*! PLL_DIV_SEL - PLL_DIV_SEL
+ * 0b000..No effect
+ * 0b001..Clears the corresponding bit
+ */
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U)
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U)
+/*! PLL_LOCK - PLL_LOCK
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_SIC_TOG - PLL Control/Status Toggle */
+/*! @{ */
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U)
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
+/*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U)
+#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U)
+/*! PLL_POWER - POWER
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U)
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U)
+/*! PLL_ENABLE - PLL ENABLE
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U)
+#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U)
+/*! PLL_BYPASS - Bypass USB PLL
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U)
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U)
+/*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK)
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U)
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U)
+/*! REFBIAS_PWD - REFBIAS_PWD
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U)
+#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U)
+/*! PLL_REG_ENABLE - PLL_REG_ENABLE
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U)
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U)
+/*! PLL_DIV_SEL - PLL_DIV_SEL
+ * 0b000..No effect
+ * 0b001..Toggles the corresponding bit
+ */
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U)
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U)
+/*! PLL_LOCK - PLL_LOCK
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
+/*! @} */
+
+/*! @name USB1_VBUS_DETECT - VBUS detect */
+/*! @{ */
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
+/*! VBUSVALID_THRESH - VBUS comparator threshold
+ */
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
+/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
+ * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
+ * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
+ */
+#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
+#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
+/*! SESSEND_OVERRIDE - Override value for SESSEND
+ */
+#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
+#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
+/*! BVALID_OVERRIDE - Override value for B-Device Session Valid
+ */
+#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
+#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
+/*! AVALID_OVERRIDE - Override value for A-Device Session Valid
+ */
+#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
+/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
+ */
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
+/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
+ * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
+ */
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
+/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
+ * 0b01..Use the Session Valid comparator results for signal reported to the USB controller
+ * 0b10..Use the Session Valid comparator results for signal reported to the USB controller
+ * 0b11..Reserved, do not use
+ */
+#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
+/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
+ * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results
+ * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
+ */
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U)
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
+/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
+ * 0b0..Powers down the VBUS_VALID comparator
+ * 0b1..Enables the VBUS_VALID comparator (default)
+ */
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
+#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
+/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
+ * 0b0..VBUS discharge resistor is disabled (Default)
+ * 0b1..VBUS discharge resistor is enabled
+ */
+#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)
+#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)
+/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
+ * 0b0..Disable resistive charger detection resistors on DP and DP
+ * 0b1..Enable resistive charger detection resistors on DP and DP
+ */
+#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)
+/*! @} */
+
+/*! @name USB1_VBUS_DETECT_SET - VBUS detect Set */
+/*! @{ */
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
+/*! VBUSVALID_THRESH - VBUS comparator threshold
+ * 0b000..No effect
+ * 0b001..Sets the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
+/*! VBUS_OVERRIDE_EN - VBUS detect signal override. This bit is used when EXT_VBUS_OVERRIDE_EN = 1'b0.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
+#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
+/*! SESSEND_OVERRIDE - Override value for SESSEND
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
+#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
+/*! BVALID_OVERRIDE - Override value for B-Device Session Valid
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
+#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
+/*! AVALID_OVERRIDE - Override value for A-Device Session Valid
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
+/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
+/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
+/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
+/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U)
+#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
+/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
+#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
+/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)
+#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)
+/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)
+/*! @} */
+
+/*! @name USB1_VBUS_DETECT_CLR - VBUS detect Clear */
+/*! @{ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
+/*! VBUSVALID_THRESH - VBUS comparator threshold
+ * 0b000..No effect
+ * 0b001..clears the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
+/*! VBUS_OVERRIDE_EN - VBUS detect signal override. This bit is used when EXT_VBUS_OVERRIDE_EN = 1'b0.
+ * 0b0..No effect
+ * 0b1..clears the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
+/*! SESSEND_OVERRIDE - Override value for SESSEND
+ * 0b0..No effect
+ * 0b1..clears the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
+/*! BVALID_OVERRIDE - Override value for B-Device Session Valid
+ * 0b0..No effect
+ * 0b1..clears the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
+/*! AVALID_OVERRIDE - Override value for A-Device Session Valid
+ * 0b0..No effect
+ * 0b1..clears the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
+/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
+ * 0b0..No effect
+ * 0b1..clears the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
+/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ * 0b0..No effect
+ * 0b1..clears the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
+/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
+/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
+ * 0b0..No effect
+ * 0b1..clears the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
+/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
+ * 0b0..No effect
+ * 0b1..clears the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
+/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
+ * 0b0..No effect
+ * 0b1..clears the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)
+/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)
+/*! @} */
+
+/*! @name USB1_VBUS_DETECT_TOG - VBUS detect Toggle */
+/*! @{ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
+/*! VBUSVALID_THRESH - VBUS comparator threshold
+ * 0b000..No effect
+ * 0b001..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
+/*! VBUS_OVERRIDE_EN - VBUS detect signal override. This bit is used when EXT_VBUS_OVERRIDE_EN = 1'b0.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
+/*! SESSEND_OVERRIDE - Override value for SESSEND
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
+/*! BVALID_OVERRIDE - Override value for B-Device Session Valid
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
+/*! AVALID_OVERRIDE - Override value for A-Device Session Valid
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
+/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
+/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
+/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
+/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
+/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
+/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)
+/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)
+/*! @} */
+
+/*! @name USB1_VBUS_DET_STAT - VBUS Detect Status */
+/*! @{ */
+#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U)
+#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U)
+/*! SESSEND - Session End indicator
+ * 0b0..The VBUS voltage is above the Session Valid threshold
+ * 0b1..The VBUS voltage is below the Session Valid threshold
+ */
+#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U)
+#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U)
+/*! BVALID - B-Device Session Valid status
+ * 0b0..The VBUS voltage is below the Session Valid threshold
+ * 0b1..The VBUS voltage is above the Session Valid threshold
+ */
+#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U)
+#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U)
+/*! AVALID - A-Device Session Valid status
+ * 0b0..The VBUS voltage is below the Session Valid threshold
+ * 0b1..The VBUS voltage is above the Session Valid threshold
+ */
+#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
+/*! VBUS_VALID - VBUS voltage status
+ * 0b0..VBUS is below the comparator threshold
+ * 0b1..VBUS is above the comparator threshold
+ */
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
+/*! VBUS_VALID_3V - VBUS_VALID_3V detector status
+ * 0b0..VBUS voltage is below VBUS_VALID_3V threshold
+ * 0b1..VBUS voltage is above VBUS_VALID_3V threshold
+ */
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
+/*! @} */
+
+/*! @name USB1_CHRG_DETECT - Charger Detect Control */
+/*! @{ */
+#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U)
+#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U)
+/*! PULLUP_DP - PULLUP_DP
+ */
+#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK)
+#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK (0x800000U)
+#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT (23U)
+/*! BGR_IBIAS - USB charge detector bias current reference
+ * 0b0..Bias current is derived from the USB PHY internal current generator.
+ * 0b1..Bias current is derived from the reference generator of the bandgap.
+ */
+#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK)
+/*! @} */
+
+/*! @name USB1_CHRG_DETECT_SET - Charger Detect Control Set */
+/*! @{ */
+#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U)
+#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U)
+/*! PULLUP_DP - PULLUP_DP
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK)
+#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK (0x800000U)
+#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT (23U)
+/*! BGR_IBIAS - BGR_IBIAS
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK)
+/*! @} */
+
+/*! @name USB1_CHRG_DETECT_CLR - Charger Detect Control Clear */
+/*! @{ */
+#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U)
+#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U)
+/*! PULLUP_DP - PULLUP_DP
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK)
+#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK (0x800000U)
+#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT (23U)
+/*! BGR_IBIAS - BGR_IBIAS
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK)
+/*! @} */
+
+/*! @name USB1_CHRG_DETECT_TOG - Charger Detect Control Toggle */
+/*! @{ */
+#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U)
+#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U)
+/*! PULLUP_DP - PULLUP_DP
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK)
+#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK (0x800000U)
+#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT (23U)
+/*! BGR_IBIAS - BGR_IBIAS
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK)
+/*! @} */
+
+/*! @name USB1_CHRG_DET_STAT - Charge Detect Status */
+/*! @{ */
+#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
+#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
+/*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output
+ * 0b0..No USB cable attachment has been detected
+ * 0b1..A USB cable attachment between the device and host has been detected
+ */
+#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
+#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
+/*! CHRG_DETECTED - Battery Charging Primary Detection phase output
+ * 0b0..Standard Downstream Port (SDP) has been detected
+ * 0b1..Charging Port has been detected
+ */
+#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U)
+#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U)
+/*! DM_STATE - DM_STATE
+ * 0b0..DM pin voltage is < 0.8V
+ * 0b1..DM pin voltage is > 2.0V
+ */
+#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U)
+#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
+/*! DP_STATE - DP_STATE
+ * 0b0..DP pin voltage is < 0.8V
+ * 0b1..DP pin voltage is > 2.0V
+ */
+#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
+#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
+/*! SECDET_DCP - Battery Charging Secondary Detection phase output
+ * 0b0..Charging Downstream Port (CDP) has been detected
+ * 0b1..Downstream Charging Port (DCP) has been detected
+ */
+#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
+/*! @} */
+
+/*! @name ANACTRL - Analog Control */
+/*! @{ */
+#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U)
+#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U)
+/*! DEV_PULLDOWN - Device Pull-down
+ */
+#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
+/*! @} */
+
+/*! @name ANACTRL_SET - Analog Control Set */
+/*! @{ */
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U)
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U)
+/*! DEV_PULLDOWN - Device Pull-down
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
+/*! @} */
+
+/*! @name ANACTRL_CLR - Analog Control Clear */
+/*! @{ */
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U)
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U)
+/*! DEV_PULLDOWN - Device Pull-down
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
+/*! @} */
+
+/*! @name ANACTRL_TOG - Analog Control Toggle */
+/*! @{ */
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U)
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U)
+/*! DEV_PULLDOWN - Device Pull-down
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
+#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
+/*! UTMI_TESTSTART - USB loopback test.
+ */
+#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK (0x2U)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
+/*! UTMI_DIG_TST0 - Mode control for USB loopback test.
+ */
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK (0x4U)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
+/*! UTMI_DIG_TST1 - Mode control for USB loopback test.
+ */
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
+/*! TSTI_TX_HS_MODE - Select HS or FS mode for USB loopback testing.
+ */
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U)
+/*! TSTI_TX_LS_MODE - Select HS or FS mode for USB loopback testing.
+ */
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK (0x20U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT (5U)
+/*! TSTI_TX_EN - Enable TX for USB loopback test.
+ */
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK (0x40U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT (6U)
+/*! TSTI_TX_HIZ - Sets TX Hi-Z for USB loopback test.
+ */
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK (0x80U)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
+/*! UTMO_DIG_TST0 - Status bit for USB loopback test.
+ */
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK (0x100U)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
+/*! UTMO_DIG_TST1 - Status bit for USB loopback test.
+ */
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
+#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
+#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTPKT_MASK (0xFF0000U)
+#define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT (16U)
+/*! TSTPKT - Test packet
+ */
+#define USBPHY_USB1_LOOPBACK_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Set */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
+/*! UTMI_TESTSTART - USB loopback test.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U)
+/*! UTMI_DIG_TST0 - Mode control for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U)
+/*! UTMI_DIG_TST1 - Mode control for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U)
+/*! TSTI_TX_HS_MODE - Select HS or FS mode for USB loopback testing.
+ */
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U)
+/*! TSTI_TX_LS_MODE - Select HS or FS mode for USB loopback testing.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U)
+/*! TSTI_TX_EN - Enable TX for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U)
+/*! TSTI_TX_HIZ - Sets TX Hi-Z for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U)
+/*! UTMO_DIG_TST0 - Status bit for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U)
+/*! UTMO_DIG_TST1 - Status bit for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U)
+/*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK (0xFF0000U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT (16U)
+/*! TSTPKT - Test packet
+ * 0b00000000..No effect
+ * 0b00000001..Sets the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Clear */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
+/*! UTMI_TESTSTART - USB loopback test.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U)
+/*! UTMI_DIG_TST0 - Mode control for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U)
+/*! UTMI_DIG_TST1 - Mode control for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U)
+/*! TSTI_TX_HS_MODE - Select HS or FS mode for USB loopback testing.
+ */
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U)
+/*! TSTI_TX_LS_MODE - Select HS or FS mode for USB loopback testing.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U)
+/*! TSTI_TX_EN - Enable TX for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U)
+/*! TSTI_TX_HIZ - Sets TX Hi-Z for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U)
+/*! UTMO_DIG_TST0 - Status bit for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U)
+/*! UTMO_DIG_TST1 - Status bit for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U)
+/*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK (0xFF0000U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT (16U)
+/*! TSTPKT - Test packet
+ * 0b00000000..No effect
+ * 0b00000001..Clears the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Toggle */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
+/*! UTMI_TESTSTART - USB loopback test.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U)
+/*! UTMI_DIG_TST0 - Mode control for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U)
+/*! UTMI_DIG_TST1 - Mode control for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U)
+/*! TSTI_TX_HS_MODE - Select HS or FS mode for USB loopback testing.
+ */
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U)
+/*! TSTI_TX_LS_MODE - Select HS or FS mode for USB loopback testing.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U)
+/*! TSTI_TX_EN - Enable TX for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U)
+/*! TSTI_TX_HIZ - Sets TX Hi-Z for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U)
+/*! UTMO_DIG_TST0 - Status bit for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U)
+/*! UTMO_DIG_TST1 - Status bit for USB loopback test.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U)
+/*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK (0xFF0000U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT (16U)
+/*! TSTPKT - Test packet
+ * 0b00000000..No effect
+ * 0b00000001..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK_HSFSCNT - Loopback Packet Number Select */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U)
+/*! TSTI_HS_NUMBER - USB loopback test HS CNT.
+ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U)
+/*! TSTI_FS_NUMBER - USB loopback test FS CNT.
+ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Set */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U)
+/*! TSTI_HS_NUMBER - USB loopback test HS CNT.
+ * 0b0000000000000000..No effect
+ * 0b0000000000000001..Sets the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U)
+/*! TSTI_FS_NUMBER - USB loopback test FS CNT.
+ * 0b0000000000000000..No effect
+ * 0b0000000000000001..Sets the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Clear */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U)
+/*! TSTI_HS_NUMBER - USB loopback test HS CNT.
+ * 0b0000000000000000..No effect
+ * 0b0000000000000001..Clears the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U)
+/*! TSTI_FS_NUMBER - USB loopback test FS CNT.
+ * 0b0000000000000000..No effect
+ * 0b0000000000000001..Clears the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK)
+/*! @} */
+
+/*! @name USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Toggle */
+/*! @{ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U)
+/*! TSTI_HS_NUMBER - USB loopback test HS CNT.
+ * 0b0000000000000000..No effect
+ * 0b0000000000000001..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U)
+/*! TSTI_FS_NUMBER - USB loopback test FS CNT.
+ * 0b0000000000000000..No effect
+ * 0b0000000000000001..Toggles the corresponding bit
+ */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK)
+/*! @} */
+
+/*! @name TRIM_OVERRIDE_EN - Trim Override Enable */
+/*! @{ */
+#define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK (0x1U)
+#define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT (0U)
+/*! DIV_SEL_OVERRIDE - DIV_SEL_OVERRIDE
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
+#define USBPHY_TRIM_OVERRIDE_EN_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
+/*! ENV_TAIL_ADJ_VD_OVERRIDE - ENV_TAIL_ADJ_VD_OVERRIDE
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK (0x4U)
+#define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT (2U)
+/*! TX_D_CAL_OVERRIDE - TX_D_CAL_OVERRIDE
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK (0x8U)
+#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT (3U)
+/*! TX_CAL45DP_OVERRIDE - TX_CAL45DP_OVERRIDE
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK (0x10U)
+#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT (4U)
+/*! TX_CAL45DM_OVERRIDE - TX_CAL45DM_OVERRIDE
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
+#define USBPHY_TRIM_OVERRIDE_EN_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
+/*! REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_REFBIAS_VBGADJ_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_REFBIAS_TST_OVERRIDE_MASK (0x40U)
+#define USBPHY_TRIM_OVERRIDE_EN_REFBIAS_TST_OVERRIDE_SHIFT (6U)
+/*! REFBIAS_TST_OVERRIDE - Override enable for bias current control.
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_REFBIAS_TST_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
+#define USBPHY_TRIM_OVERRIDE_EN_USB2_REFBIAS_VBGADJ_SHIFT (10U)
+/*! USB2_REFBIAS_VBGADJ - Adjustment bits for bandgap
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USB2_REFBIAS_VBGADJ_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_USB2_REFBIAS_TST_MASK (0x6000U)
+#define USBPHY_TRIM_OVERRIDE_EN_USB2_REFBIAS_TST_SHIFT (13U)
+/*! USB2_REFBIAS_TST - Bias current control for usb2_phy and usb_PLL
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USB2_REFBIAS_TST_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
+#define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT (15U)
+/*! PLL_CTRL0_DIV_SEL - Default value of PLL_DIV_SEL.
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
+#define USBPHY_TRIM_OVERRIDE_EN_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
+/*! USB_REG_ENV_TAIL_ADJ_VD - Default value of ENV_TAIL_ADJ.
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USB_REG_ENV_TAIL_ADJ_VD_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK (0xF00000U)
+#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT (20U)
+/*! USBPHY_TX_D_CAL - Default value of TX_D_CAL.
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK (0xF000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT (24U)
+/*! USBPHY_TX_CAL45DP - Default value of TX_CAL45DP.
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT (28U)
+/*! USBPHY_TX_CAL45DN - Default value of TX_CAL45DM.
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK)
+/*! @} */
+
+/*! @name TRIM_OVERRIDE_EN_SET - Trim Set */
+/*! @{ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK (0x1U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT (0U)
+/*! DIV_SEL_OVERRIDE - DIV_SEL_OVERRIDE
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
+/*! ENV_TAIL_ADJ_VD_OVERRIDE - ENV_TAIL_ADJ_VD_OVERRIDE
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK (0x4U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT (2U)
+/*! TX_D_CAL_OVERRIDE - TX_D_CAL_OVERRIDE
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK (0x8U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT (3U)
+/*! TX_CAL45DP_OVERRIDE - TX_CAL45DP_OVERRIDE
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK (0x10U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT (4U)
+/*! TX_CAL45DM_OVERRIDE - TX_CAL45DM_OVERRIDE
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
+/*! REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_REFBIAS_VBGADJ_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_REFBIAS_TST_OVERRIDE_MASK (0x40U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_REFBIAS_TST_OVERRIDE_SHIFT (6U)
+/*! REFBIAS_TST_OVERRIDE - Override enable for bias current control.
+ * 0b0..No effect
+ * 0b1..Sets the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_REFBIAS_TST_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USB2_REFBIAS_VBGADJ_SHIFT (10U)
+/*! USB2_REFBIAS_VBGADJ - Adjustment bits for bandgap
+ * 0b000..No effect
+ * 0b001..Sets the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USB2_REFBIAS_VBGADJ_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USB2_REFBIAS_TST_MASK (0x6000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USB2_REFBIAS_TST_SHIFT (13U)
+/*! USB2_REFBIAS_TST - Bias current control for usb2_phy and usb_PLL
+ * 0b00..No effect
+ * 0b01..Sets the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USB2_REFBIAS_TST_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT (15U)
+/*! PLL_CTRL0_DIV_SEL - Default value of PLL_DIV_SEL.
+ * 0b000..No effect
+ * 0b001..Sets the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
+/*! USB_REG_ENV_TAIL_ADJ_VD - Default value of ENV_TAIL_ADJ.
+ * 0b00..No effect
+ * 0b01..Sets the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USB_REG_ENV_TAIL_ADJ_VD_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK (0xF00000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT (20U)
+/*! USBPHY_TX_D_CAL - Default value of TX_D_CAL.
+ * 0b0000..No effect
+ * 0b0001..Sets the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK (0xF000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT (24U)
+/*! USBPHY_TX_CAL45DP - Default value of TX_CAL45DP.
+ * 0b0000..No effect
+ * 0b0001..Sets the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT (28U)
+/*! USBPHY_TX_CAL45DN - Default value of TX_CAL45DM.
+ * 0b0000..No effect
+ * 0b0001..Sets the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK)
+/*! @} */
+
+/*! @name TRIM_OVERRIDE_EN_CLR - Trim Clear */
+/*! @{ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK (0x1U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT (0U)
+/*! DIV_SEL_OVERRIDE - DIV_SEL_OVERRIDE
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
+/*! ENV_TAIL_ADJ_VD_OVERRIDE - ENV_TAIL_ADJ_VD_OVERRIDE
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK (0x4U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT (2U)
+/*! TX_D_CAL_OVERRIDE - TX_D_CAL_OVERRIDE
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK (0x8U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT (3U)
+/*! TX_CAL45DP_OVERRIDE - TX_CAL45DP_OVERRIDE
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK (0x10U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT (4U)
+/*! TX_CAL45DM_OVERRIDE - TX_CAL45DM_OVERRIDE
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
+/*! REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_REFBIAS_VBGADJ_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_REFBIAS_TST_OVERRIDE_MASK (0x40U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_REFBIAS_TST_OVERRIDE_SHIFT (6U)
+/*! REFBIAS_TST_OVERRIDE - Override enable for bias current control.
+ * 0b0..No effect
+ * 0b1..Clears the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_REFBIAS_TST_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USB2_REFBIAS_VBGADJ_SHIFT (10U)
+/*! USB2_REFBIAS_VBGADJ - Adjustment bits for bandgap
+ * 0b000..No effect
+ * 0b001..Clears the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USB2_REFBIAS_VBGADJ_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USB2_REFBIAS_TST_MASK (0x6000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USB2_REFBIAS_TST_SHIFT (13U)
+/*! USB2_REFBIAS_TST - Bias current control for usb2_phy and usb_PLL
+ * 0b00..No effect
+ * 0b01..Clears the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USB2_REFBIAS_TST_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT (15U)
+/*! PLL_CTRL0_DIV_SEL - Default value of PLL_DIV_SEL.
+ * 0b000..No effect
+ * 0b001..Clears the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
+/*! USB_REG_ENV_TAIL_ADJ_VD - Default value of ENV_TAIL_ADJ.
+ * 0b00..No effect
+ * 0b01..Clears the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USB_REG_ENV_TAIL_ADJ_VD_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK (0xF00000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT (20U)
+/*! USBPHY_TX_D_CAL - Default value of TX_D_CAL.
+ * 0b0000..No effect
+ * 0b0001..Clears the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK (0xF000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT (24U)
+/*! USBPHY_TX_CAL45DP - Default value of TX_CAL45DP.
+ * 0b0000..No effect
+ * 0b0001..Clears the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT (28U)
+/*! USBPHY_TX_CAL45DN - Default value of TX_CAL45DM.
+ * 0b0000..No effect
+ * 0b0001..Clears the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK)
+/*! @} */
+
+/*! @name TRIM_OVERRIDE_EN_TOG - Trim Toggle */
+/*! @{ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK (0x1U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT (0U)
+/*! DIV_SEL_OVERRIDE - DIV_SEL_OVERRIDE
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
+/*! ENV_TAIL_ADJ_VD_OVERRIDE - ENV_TAIL_ADJ_VD_OVERRIDE
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK (0x4U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT (2U)
+/*! TX_D_CAL_OVERRIDE - TX_D_CAL_OVERRIDE
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK (0x8U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT (3U)
+/*! TX_CAL45DP_OVERRIDE - TX_CAL45DP_OVERRIDE
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK (0x10U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT (4U)
+/*! TX_CAL45DM_OVERRIDE - TX_CAL45DM_OVERRIDE
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
+/*! REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_REFBIAS_VBGADJ_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_REFBIAS_TST_OVERRIDE_MASK (0x40U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_REFBIAS_TST_OVERRIDE_SHIFT (6U)
+/*! REFBIAS_TST_OVERRIDE - Override enable for bias current control.
+ * 0b0..No effect
+ * 0b1..Toggles the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_REFBIAS_TST_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USB2_REFBIAS_VBGADJ_SHIFT (10U)
+/*! USB2_REFBIAS_VBGADJ - Adjustment bits for bandgap
+ * 0b000..No effect
+ * 0b001..Toggles the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USB2_REFBIAS_VBGADJ_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USB2_REFBIAS_TST_MASK (0x6000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USB2_REFBIAS_TST_SHIFT (13U)
+/*! USB2_REFBIAS_TST - Bias current control for usb2_phy and usb_PLL
+ * 0b00..No effect
+ * 0b01..Toggles the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USB2_REFBIAS_TST_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT (15U)
+/*! PLL_CTRL0_DIV_SEL - Default value of PLL_DIV_SEL.
+ * 0b000..No effect
+ * 0b001..Toggles the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
+/*! USB_REG_ENV_TAIL_ADJ_VD - Default value of ENV_TAIL_ADJ.
+ * 0b00..No effect
+ * 0b01..Toggles the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USB_REG_ENV_TAIL_ADJ_VD_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK (0xF00000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT (20U)
+/*! USBPHY_TX_D_CAL - Default value of TX_D_CAL.
+ * 0b0000..No effect
+ * 0b0001..Toggles the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK (0xF000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT (24U)
+/*! USBPHY_TX_CAL45DP - Default value of TX_CAL45DP.
+ * 0b0000..No effect
+ * 0b0001..Toggles the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT (28U)
+/*! USBPHY_TX_CAL45DN - Default value of TX_CAL45DM.
+ * 0b0000..No effect
+ * 0b0001..Toggles the corresponding bit
+ */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBPHY_Register_Masks */
+
+
+/* USBPHY - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral USBPHY base address */
+ #define USBPHY_BASE (0x5013B000u)
+ /** Peripheral USBPHY base address */
+ #define USBPHY_BASE_NS (0x4013B000u)
+ /** Peripheral USBPHY base pointer */
+ #define USBPHY ((USBPHY_Type *)USBPHY_BASE)
+ /** Peripheral USBPHY base pointer */
+ #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS)
+ /** Array initializer of USBPHY peripheral base addresses */
+ #define USBPHY_BASE_ADDRS { USBPHY_BASE }
+ /** Array initializer of USBPHY peripheral base pointers */
+ #define USBPHY_BASE_PTRS { USBPHY }
+ /** Array initializer of USBPHY peripheral base addresses */
+ #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS }
+ /** Array initializer of USBPHY peripheral base pointers */
+ #define USBPHY_BASE_PTRS_NS { USBPHY_NS }
+#else
+ /** Peripheral USBPHY base address */
+ #define USBPHY_BASE (0x4013B000u)
+ /** Peripheral USBPHY base pointer */
+ #define USBPHY ((USBPHY_Type *)USBPHY_BASE)
+ /** Array initializer of USBPHY peripheral base addresses */
+ #define USBPHY_BASE_ADDRS { USBPHY_BASE }
+ /** Array initializer of USBPHY peripheral base pointers */
+ #define USBPHY_BASE_PTRS { USBPHY }
+#endif
+
+/*!
+ * @}
+ */ /* end of group USBPHY_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USDHC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
+ * @{
+ */
+
+/** USDHC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */
+ __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */
+ __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */
+ __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */
+ __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */
+ __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */
+ __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */
+ __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */
+ __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */
+ __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */
+ __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */
+ __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */
+ __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */
+ __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */
+ __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */
+ __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */
+ __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */
+ __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */
+ __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */
+ uint8_t RESERVED_0[4];
+ __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */
+ __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status, offset: 0x54 */
+ __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */
+ __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */
+ __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t STROBE_DLL_CTRL; /**< Strobe DLL control, offset: 0x70 */
+ __I uint32_t STROBE_DLL_STATUS; /**< Strobe DLL status, offset: 0x74 */
+ uint8_t RESERVED_3[72];
+ __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */
+ __IO uint32_t MMC_BOOT; /**< MMC Boot, offset: 0xC4 */
+ __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */
+ __IO uint32_t TUNING_CTRL; /**< Tuning Control, offset: 0xCC */
+} USDHC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USDHC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USDHC_Register_Masks USDHC Register Masks
+ * @{
+ */
+
+/*! @name DS_ADDR - DMA System Address */
+/*! @{ */
+#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)
+#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)
+/*! DS_ADDR - System address
+ */
+#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
+/*! @} */
+
+/*! @name BLK_ATT - Block Attributes */
+/*! @{ */
+#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)
+#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)
+/*! BLKSIZE - Transfer block size
+ * 0b1000000000000..4096 bytes
+ * 0b0100000000000..2048 bytes
+ * 0b0001000000000..512 bytes
+ * 0b0000111111111..511 bytes
+ * 0b0000000000100..4 bytes
+ * 0b0000000000011..3 bytes
+ * 0b0000000000010..2 bytes
+ * 0b0000000000001..1 byte
+ * 0b0000000000000..No data transfer
+ */
+#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
+#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)
+#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U)
+/*! BLKCNT - Blocks count for current transfer
+ * 0b1111111111111111..65535 blocks
+ * 0b0000000000000010..2 blocks
+ * 0b0000000000000001..1 block
+ * 0b0000000000000000..Stop count
+ */
+#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
+/*! @} */
+
+/*! @name CMD_ARG - Command Argument */
+/*! @{ */
+#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)
+#define USDHC_CMD_ARG_CMDARG_SHIFT (0U)
+/*! CMDARG - Command argument
+ */
+#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
+/*! @} */
+
+/*! @name CMD_XFR_TYP - Command Transfer Type */
+/*! @{ */
+#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)
+#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)
+/*! RSPTYP - Response type select
+ * 0b00..No response
+ * 0b01..Response length 136
+ * 0b10..Response length 48
+ * 0b11..Response length 48, check busy after response
+ */
+#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
+#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)
+#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)
+/*! CCCEN - Command CRC check enable
+ * 0b1..Enables command CRC check
+ * 0b0..Disables command CRC check
+ */
+#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
+#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)
+#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)
+/*! CICEN - Command index check enable
+ * 0b1..Enables command index check
+ * 0b0..Disable command index check
+ */
+#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
+#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)
+#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)
+/*! DPSEL - Data present select
+ * 0b1..Data present
+ * 0b0..No data present
+ */
+#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
+#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)
+#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)
+/*! CMDTYP - Command type
+ * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
+ * 0b10..Resume CMD52 for writing function select in CCCR
+ * 0b01..Suspend CMD52 for writing bus suspend in CCCR
+ * 0b00..Normal other commands
+ */
+#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
+#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)
+#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)
+/*! CMDINX - Command index
+ */
+#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
+/*! @} */
+
+/*! @name CMD_RSP0 - Command Response0 */
+/*! @{ */
+#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)
+#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)
+/*! CMDRSP0 - Command response 0
+ */
+#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
+/*! @} */
+
+/*! @name CMD_RSP1 - Command Response1 */
+/*! @{ */
+#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)
+#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)
+/*! CMDRSP1 - Command response 1
+ */
+#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
+/*! @} */
+
+/*! @name CMD_RSP2 - Command Response2 */
+/*! @{ */
+#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)
+#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)
+/*! CMDRSP2 - Command response 2
+ */
+#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
+/*! @} */
+
+/*! @name CMD_RSP3 - Command Response3 */
+/*! @{ */
+#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)
+#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)
+/*! CMDRSP3 - Command response 3
+ */
+#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
+/*! @} */
+
+/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
+/*! @{ */
+#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)
+#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)
+/*! DATCONT - Data content
+ */
+#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
+/*! @} */
+
+/*! @name PRES_STATE - Present State */
+/*! @{ */
+#define USDHC_PRES_STATE_CIHB_MASK (0x1U)
+#define USDHC_PRES_STATE_CIHB_SHIFT (0U)
+/*! CIHB - Command inhibit (CMD)
+ * 0b1..Cannot issue command
+ * 0b0..Can issue command using only CMD line
+ */
+#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
+#define USDHC_PRES_STATE_CDIHB_MASK (0x2U)
+#define USDHC_PRES_STATE_CDIHB_SHIFT (1U)
+/*! CDIHB - Command inhibit (DATA)
+ * 0b1..Cannot issue command that uses the DATA line
+ * 0b0..Can issue command that uses the DATA line
+ */
+#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
+#define USDHC_PRES_STATE_DLA_MASK (0x4U)
+#define USDHC_PRES_STATE_DLA_SHIFT (2U)
+/*! DLA - Data line active
+ * 0b1..DATA line active
+ * 0b0..DATA line inactive
+ */
+#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
+#define USDHC_PRES_STATE_SDSTB_MASK (0x8U)
+#define USDHC_PRES_STATE_SDSTB_SHIFT (3U)
+/*! SDSTB - SD clock stable
+ * 0b1..Clock is stable.
+ * 0b0..Clock is changing frequency and not stable.
+ */
+#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
+#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U)
+#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U)
+/*! IPGOFF - Peripheral clock gated off internally
+ * 0b1..Peripheral clock is gated off.
+ * 0b0..Peripheral clock is active.
+ */
+#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
+#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U)
+#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U)
+/*! HCKOFF - HCLK gated off internally
+ * 0b1..HCLK is gated off.
+ * 0b0..HCLK is active.
+ */
+#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
+#define USDHC_PRES_STATE_PEROFF_MASK (0x40U)
+#define USDHC_PRES_STATE_PEROFF_SHIFT (6U)
+/*! PEROFF - IPG_PERCLK gated off internally
+ * 0b1..IPG_PERCLK is gated off.
+ * 0b0..IPG_PERCLK is active.
+ */
+#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
+#define USDHC_PRES_STATE_SDOFF_MASK (0x80U)
+#define USDHC_PRES_STATE_SDOFF_SHIFT (7U)
+/*! SDOFF - SD clock gated off internally
+ * 0b1..SD clock is gated off.
+ * 0b0..SD clock is active.
+ */
+#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
+#define USDHC_PRES_STATE_WTA_MASK (0x100U)
+#define USDHC_PRES_STATE_WTA_SHIFT (8U)
+/*! WTA - Write transfer active
+ * 0b1..Transferring data
+ * 0b0..No valid data
+ */
+#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
+#define USDHC_PRES_STATE_RTA_MASK (0x200U)
+#define USDHC_PRES_STATE_RTA_SHIFT (9U)
+/*! RTA - Read transfer active
+ * 0b1..Transferring data
+ * 0b0..No valid data
+ */
+#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
+#define USDHC_PRES_STATE_BWEN_MASK (0x400U)
+#define USDHC_PRES_STATE_BWEN_SHIFT (10U)
+/*! BWEN - Buffer write enable
+ * 0b1..Write enable
+ * 0b0..Write disable
+ */
+#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
+#define USDHC_PRES_STATE_BREN_MASK (0x800U)
+#define USDHC_PRES_STATE_BREN_SHIFT (11U)
+/*! BREN - Buffer read enable
+ * 0b1..Read enable
+ * 0b0..Read disable
+ */
+#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
+#define USDHC_PRES_STATE_RTR_MASK (0x1000U)
+#define USDHC_PRES_STATE_RTR_SHIFT (12U)
+/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)
+ * 0b1..Sampling clock needs re-tuning
+ * 0b0..Fixed or well tuned sampling clock
+ */
+#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
+#define USDHC_PRES_STATE_TSCD_MASK (0x8000U)
+#define USDHC_PRES_STATE_TSCD_SHIFT (15U)
+/*! TSCD - Tape select change done
+ * 0b1..Delay cell select change is finished.
+ * 0b0..Delay cell select change is not finished.
+ */
+#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
+#define USDHC_PRES_STATE_CINST_MASK (0x10000U)
+#define USDHC_PRES_STATE_CINST_SHIFT (16U)
+/*! CINST - Card inserted
+ * 0b1..Card inserted
+ * 0b0..Power on reset or no card
+ */
+#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
+#define USDHC_PRES_STATE_CDPL_MASK (0x40000U)
+#define USDHC_PRES_STATE_CDPL_SHIFT (18U)
+/*! CDPL - Card detect pin level
+ * 0b1..Card present (CD_B = 0)
+ * 0b0..No card present (CD_B = 1)
+ */
+#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
+#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U)
+#define USDHC_PRES_STATE_WPSPL_SHIFT (19U)
+/*! WPSPL - Write protect switch pin level
+ * 0b1..Write enabled (WP = 0)
+ * 0b0..Write protected (WP = 1)
+ */
+#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
+#define USDHC_PRES_STATE_CLSL_MASK (0x800000U)
+#define USDHC_PRES_STATE_CLSL_SHIFT (23U)
+/*! CLSL - CMD line signal level
+ */
+#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
+#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)
+#define USDHC_PRES_STATE_DLSL_SHIFT (24U)
+/*! DLSL - DATA[7:0] line signal level
+ * 0b00000111..Data 7 line signal level
+ * 0b00000110..Data 6 line signal level
+ * 0b00000101..Data 5 line signal level
+ * 0b00000100..Data 4 line signal level
+ * 0b00000011..Data 3 line signal level
+ * 0b00000010..Data 2 line signal level
+ * 0b00000001..Data 1 line signal level
+ * 0b00000000..Data 0 line signal level
+ */
+#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
+/*! @} */
+
+/*! @name PROT_CTRL - Protocol Control */
+/*! @{ */
+#define USDHC_PROT_CTRL_DTW_MASK (0x6U)
+#define USDHC_PROT_CTRL_DTW_SHIFT (1U)
+/*! DTW - Data transfer width
+ * 0b10..8-bit mode
+ * 0b01..4-bit mode
+ * 0b00..1-bit mode
+ * 0b11..Reserved
+ */
+#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
+#define USDHC_PROT_CTRL_D3CD_MASK (0x8U)
+#define USDHC_PROT_CTRL_D3CD_SHIFT (3U)
+/*! D3CD - DATA3 as card detection pin
+ * 0b1..DATA3 as card detection pin
+ * 0b0..DATA3 does not monitor card insertion
+ */
+#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
+#define USDHC_PROT_CTRL_EMODE_MASK (0x30U)
+#define USDHC_PROT_CTRL_EMODE_SHIFT (4U)
+/*! EMODE - Endian mode
+ * 0b00..Big endian mode
+ * 0b01..Half word big endian mode
+ * 0b10..Little endian mode
+ * 0b11..Reserved
+ */
+#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
+#define USDHC_PROT_CTRL_CDTL_MASK (0x40U)
+#define USDHC_PROT_CTRL_CDTL_SHIFT (6U)
+/*! CDTL - Card detect test level
+ * 0b1..Card detect test level is 1, card inserted
+ * 0b0..Card detect test level is 0, no card inserted
+ */
+#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
+#define USDHC_PROT_CTRL_CDSS_MASK (0x80U)
+#define USDHC_PROT_CTRL_CDSS_SHIFT (7U)
+/*! CDSS - Card detect signal selection
+ * 0b1..Card detection test level is selected (for test purpose).
+ * 0b0..Card detection level is selected (for normal purpose).
+ */
+#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
+#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U)
+#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U)
+/*! DMASEL - DMA select
+ * 0b00..No DMA or simple DMA is selected.
+ * 0b01..ADMA1 is selected.
+ * 0b10..ADMA2 is selected.
+ * 0b11..Reserved
+ */
+#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
+#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)
+#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)
+/*! SABGREQ - Stop at block gap request
+ * 0b1..Stop
+ * 0b0..Transfer
+ */
+#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
+#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U)
+#define USDHC_PROT_CTRL_CREQ_SHIFT (17U)
+/*! CREQ - Continue request
+ * 0b1..Restart
+ * 0b0..No effect
+ */
+#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
+#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)
+#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U)
+/*! RWCTL - Read wait control
+ * 0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set
+ * 0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set
+ */
+#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
+#define USDHC_PROT_CTRL_IABG_MASK (0x80000U)
+#define USDHC_PROT_CTRL_IABG_SHIFT (19U)
+/*! IABG - Interrupt at block gap
+ * 0b1..Enables interrupt at block gap
+ * 0b0..Disables interrupt at block gap
+ */
+#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
+#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)
+#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)
+/*! RD_DONE_NO_8CLK - Read performed number 8 clock
+ */
+#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
+#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)
+#define USDHC_PROT_CTRL_WECINT_SHIFT (24U)
+/*! WECINT - Wakeup event enable on card interrupt
+ * 0b1..Enables wakeup event enable on card interrupt
+ * 0b0..Disables wakeup event enable on card interrupt
+ */
+#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
+#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)
+#define USDHC_PROT_CTRL_WECINS_SHIFT (25U)
+/*! WECINS - Wakeup event enable on SD card insertion
+ * 0b1..Enable wakeup event enable on SD card insertion
+ * 0b0..Disable wakeup event enable on SD card insertion
+ */
+#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
+#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)
+#define USDHC_PROT_CTRL_WECRM_SHIFT (26U)
+/*! WECRM - Wakeup event enable on SD card removal
+ * 0b1..Enables wakeup event enable on SD card removal
+ * 0b0..Disables wakeup event enable on SD card removal
+ */
+#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
+#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)
+#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)
+/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
+ * 0bxx1..Burst length is enabled for INCR.
+ * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16.
+ * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP.
+ */
+#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
+#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)
+#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)
+/*! NON_EXACT_BLK_RD - Non-exact block read
+ * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
+ * 0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.
+ */
+#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
+/*! @} */
+
+/*! @name SYS_CTRL - System Control */
+/*! @{ */
+#define USDHC_SYS_CTRL_DVS_MASK (0xF0U)
+#define USDHC_SYS_CTRL_DVS_SHIFT (4U)
+/*! DVS - Divisor
+ * 0b0000..Divide-by-1
+ * 0b0001..Divide-by-2
+ * 0b1110..Divide-by-15
+ * 0b1111..Divide-by-16
+ */
+#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
+#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)
+#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)
+/*! SDCLKFS - SDCLK frequency select
+ */
+#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
+#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)
+#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U)
+/*! DTOCV - Data timeout counter value
+ * 0b1111..SDCLK x 2 29 + SDCLK x 2 28 + SDCLK x 2 27 + SDCLK x 2 26
+ * 0b1110..SDCLK x 2 28
+ * 0b1101..SDCLK x 2 27
+ * 0b1100..SDCLK x 2 26
+ * 0b1011..SDCLK x 2 25
+ * 0b1010..SDCLK x 2 24
+ * 0b1001..SDCLK x 2 23
+ * 0b1000..SDCLK x 2 22
+ * 0b0111..SDCLK x 2 21
+ * 0b0110..SDCLK x 2 20
+ * 0b0101..SDCLK x 2 19
+ * 0b0100..SDCLK x 2 18
+ * 0b0011..SDCLK x 2 17
+ * 0b0010..SDCLK x 2 16
+ * 0b0001..SDCLK x 2 15
+ * 0b0000..SDCLK x 2 14
+ */
+#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
+#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)
+#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)
+/*! IPP_RST_N - Hardware reset
+ */
+#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
+#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)
+#define USDHC_SYS_CTRL_RSTA_SHIFT (24U)
+/*! RSTA - Software reset for all
+ * 0b1..Reset
+ * 0b0..No reset
+ */
+#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
+#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)
+#define USDHC_SYS_CTRL_RSTC_SHIFT (25U)
+/*! RSTC - Software reset for CMD line
+ * 0b1..Reset
+ * 0b0..No reset
+ */
+#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
+#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)
+#define USDHC_SYS_CTRL_RSTD_SHIFT (26U)
+/*! RSTD - Software reset for data line
+ * 0b1..Reset
+ * 0b0..No reset
+ */
+#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
+#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U)
+#define USDHC_SYS_CTRL_INITA_SHIFT (27U)
+/*! INITA - Initialization active
+ */
+#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
+#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)
+#define USDHC_SYS_CTRL_RSTT_SHIFT (28U)
+/*! RSTT - Reset tuning
+ */
+#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
+/*! @} */
+
+/*! @name INT_STATUS - Interrupt Status */
+/*! @{ */
+#define USDHC_INT_STATUS_CC_MASK (0x1U)
+#define USDHC_INT_STATUS_CC_SHIFT (0U)
+/*! CC - Command complete
+ * 0b1..Command complete
+ * 0b0..Command not complete
+ */
+#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
+#define USDHC_INT_STATUS_TC_MASK (0x2U)
+#define USDHC_INT_STATUS_TC_SHIFT (1U)
+/*! TC - Transfer complete
+ * 0b1..Transfer complete
+ * 0b0..Transfer does not complete
+ */
+#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
+#define USDHC_INT_STATUS_BGE_MASK (0x4U)
+#define USDHC_INT_STATUS_BGE_SHIFT (2U)
+/*! BGE - Block gap event
+ * 0b1..Transaction stopped at block gap
+ * 0b0..No block gap event
+ */
+#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
+#define USDHC_INT_STATUS_DINT_MASK (0x8U)
+#define USDHC_INT_STATUS_DINT_SHIFT (3U)
+/*! DINT - DMA interrupt
+ * 0b1..DMA interrupt is generated.
+ * 0b0..No DMA interrupt
+ */
+#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
+#define USDHC_INT_STATUS_BWR_MASK (0x10U)
+#define USDHC_INT_STATUS_BWR_SHIFT (4U)
+/*! BWR - Buffer write ready
+ * 0b1..Ready to write buffer
+ * 0b0..Not ready to write buffer
+ */
+#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
+#define USDHC_INT_STATUS_BRR_MASK (0x20U)
+#define USDHC_INT_STATUS_BRR_SHIFT (5U)
+/*! BRR - Buffer read ready
+ * 0b1..Ready to read buffer
+ * 0b0..Not ready to read buffer
+ */
+#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
+#define USDHC_INT_STATUS_CINS_MASK (0x40U)
+#define USDHC_INT_STATUS_CINS_SHIFT (6U)
+/*! CINS - Card insertion
+ * 0b1..Card inserted
+ * 0b0..Card state unstable or removed
+ */
+#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
+#define USDHC_INT_STATUS_CRM_MASK (0x80U)
+#define USDHC_INT_STATUS_CRM_SHIFT (7U)
+/*! CRM - Card removal
+ * 0b1..Card removed
+ * 0b0..Card state unstable or inserted
+ */
+#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
+#define USDHC_INT_STATUS_CINT_MASK (0x100U)
+#define USDHC_INT_STATUS_CINT_SHIFT (8U)
+/*! CINT - Card interrupt
+ * 0b1..Generate card interrupt
+ * 0b0..No card interrupt
+ */
+#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
+#define USDHC_INT_STATUS_RTE_MASK (0x1000U)
+#define USDHC_INT_STATUS_RTE_SHIFT (12U)
+/*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
+ * 0b1..Re-tuning should be performed.
+ * 0b0..Re-tuning is not required.
+ */
+#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
+#define USDHC_INT_STATUS_TP_MASK (0x4000U)
+#define USDHC_INT_STATUS_TP_SHIFT (14U)
+/*! TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)
+ */
+#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
+#define USDHC_INT_STATUS_CTOE_MASK (0x10000U)
+#define USDHC_INT_STATUS_CTOE_SHIFT (16U)
+/*! CTOE - Command timeout error
+ * 0b1..Time out
+ * 0b0..No error
+ */
+#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
+#define USDHC_INT_STATUS_CCE_MASK (0x20000U)
+#define USDHC_INT_STATUS_CCE_SHIFT (17U)
+/*! CCE - Command CRC error
+ * 0b1..CRC error generated
+ * 0b0..No error
+ */
+#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
+#define USDHC_INT_STATUS_CEBE_MASK (0x40000U)
+#define USDHC_INT_STATUS_CEBE_SHIFT (18U)
+/*! CEBE - Command end bit error
+ * 0b1..End bit error generated
+ * 0b0..No error
+ */
+#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
+#define USDHC_INT_STATUS_CIE_MASK (0x80000U)
+#define USDHC_INT_STATUS_CIE_SHIFT (19U)
+/*! CIE - Command index error
+ * 0b1..Error
+ * 0b0..No error
+ */
+#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
+#define USDHC_INT_STATUS_DTOE_MASK (0x100000U)
+#define USDHC_INT_STATUS_DTOE_SHIFT (20U)
+/*! DTOE - Data timeout error
+ * 0b1..Time out
+ * 0b0..No error
+ */
+#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
+#define USDHC_INT_STATUS_DCE_MASK (0x200000U)
+#define USDHC_INT_STATUS_DCE_SHIFT (21U)
+/*! DCE - Data CRC error
+ * 0b1..Error
+ * 0b0..No error
+ */
+#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
+#define USDHC_INT_STATUS_DEBE_MASK (0x400000U)
+#define USDHC_INT_STATUS_DEBE_SHIFT (22U)
+/*! DEBE - Data end bit error
+ * 0b1..Error
+ * 0b0..No error
+ */
+#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
+#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U)
+#define USDHC_INT_STATUS_AC12E_SHIFT (24U)
+/*! AC12E - Auto CMD12 error
+ * 0b1..Error
+ * 0b0..No error
+ */
+#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
+#define USDHC_INT_STATUS_TNE_MASK (0x4000000U)
+#define USDHC_INT_STATUS_TNE_SHIFT (26U)
+/*! TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
+ */
+#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
+#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U)
+#define USDHC_INT_STATUS_DMAE_SHIFT (28U)
+/*! DMAE - DMA error
+ * 0b1..Error
+ * 0b0..No error
+ */
+#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
+/*! @} */
+
+/*! @name INT_STATUS_EN - Interrupt Status Enable */
+/*! @{ */
+#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)
+#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)
+/*! CCSEN - Command complete status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
+#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)
+#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)
+/*! TCSEN - Transfer complete status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
+#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)
+#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)
+/*! BGESEN - Block gap event status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
+#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)
+#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)
+/*! DINTSEN - DMA interrupt status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
+#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)
+#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)
+/*! BWRSEN - Buffer write ready status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
+#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)
+#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)
+/*! BRRSEN - Buffer read ready status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
+#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)
+#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)
+/*! CINSSEN - Card insertion status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
+#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)
+#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)
+/*! CRMSEN - Card removal status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
+#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)
+#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)
+/*! CINTSEN - Card interrupt status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
+#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)
+#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)
+/*! RTESEN - Re-tuning event status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
+#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)
+#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)
+/*! TPSEN - Tuning pass status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
+#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)
+#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)
+/*! CTOESEN - Command timeout error status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
+#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)
+#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)
+/*! CCESEN - Command CRC error status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
+#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)
+#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)
+/*! CEBESEN - Command end bit error status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
+#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)
+#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)
+/*! CIESEN - Command index error status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
+#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)
+#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)
+/*! DTOESEN - Data timeout error status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
+#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)
+#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)
+/*! DCESEN - Data CRC error status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
+#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)
+#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)
+/*! DEBESEN - Data end bit error status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
+#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)
+#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)
+/*! AC12ESEN - Auto CMD12 error status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
+#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)
+#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)
+/*! TNESEN - Tuning error status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
+#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)
+#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)
+/*! DMAESEN - DMA error status enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
+/*! @} */
+
+/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
+/*! @{ */
+#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)
+#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)
+/*! CCIEN - Command complete interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)
+#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)
+/*! TCIEN - Transfer complete interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)
+#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)
+/*! BGEIEN - Block gap event interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)
+#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)
+/*! DINTIEN - DMA interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)
+#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)
+/*! BWRIEN - Buffer write ready interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)
+#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)
+/*! BRRIEN - Buffer read ready interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)
+#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)
+/*! CINSIEN - Card insertion interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)
+#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)
+/*! CRMIEN - Card removal interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)
+#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)
+/*! CINTIEN - Card interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)
+#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)
+/*! RTEIEN - Re-tuning event interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)
+#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)
+/*! TPIEN - Tuning Pass interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)
+#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)
+/*! CTOEIEN - Command timeout error interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)
+#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)
+/*! CCEIEN - Command CRC error interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)
+#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)
+/*! CEBEIEN - Command end bit error interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)
+#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)
+/*! CIEIEN - Command index error interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)
+#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)
+/*! DTOEIEN - Data timeout error interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)
+#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)
+/*! DCEIEN - Data CRC error interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)
+#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)
+/*! DEBEIEN - Data end bit error interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)
+#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)
+/*! AC12EIEN - Auto CMD12 error interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)
+#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)
+/*! TNEIEN - Tuning error interrupt enable
+ * 0b1..Enabled
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)
+#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)
+/*! DMAEIEN - DMA error interrupt enable
+ * 0b1..Enable
+ * 0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
+/*! @} */
+
+/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
+/*! @{ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)
+/*! AC12NE - Auto CMD12 not executed
+ * 0b1..Not executed
+ * 0b0..Executed
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
+/*! AC12TOE - Auto CMD12 / 23 timeout error
+ * 0b1..Time out
+ * 0b0..No error
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
+/*! AC12EBE - Auto CMD12 / 23 end bit error
+ * 0b1..End bit error generated
+ * 0b0..No error
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)
+/*! AC12CE - Auto CMD12 / 23 CRC error
+ * 0b1..CRC error met in Auto CMD12/23 response
+ * 0b0..No CRC error
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)
+/*! AC12IE - Auto CMD12 / 23 index error
+ * 0b1..Error, the CMD index in response is not CMD12/23
+ * 0b0..No error
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
+#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
+/*! CNIBAC12E - Command not issued by Auto CMD12 error
+ * 0b1..Not issued
+ * 0b0..No error
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
+#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
+/*! EXECUTE_TUNING - Execute tuning
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
+#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
+/*! SMP_CLK_SEL - Sample clock select
+ * 0b1..Tuned clock is used to sample data
+ * 0b0..Fixed clock is used to sample data
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name HOST_CTRL_CAP - Host Controller Capabilities */
+/*! @{ */
+#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)
+#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)
+/*! SDR50_SUPPORT - SDR50 support
+ */
+#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
+#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)
+#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
+/*! SDR104_SUPPORT - SDR104 support
+ */
+#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
+#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)
+#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)
+/*! DDR50_SUPPORT - DDR50 support
+ */
+#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
+#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)
+#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)
+/*! TIME_COUNT_RETUNING - Time counter for retuning
+ */
+#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
+#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
+#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
+/*! USE_TUNING_SDR50 - Use Tuning for SDR50
+ * 0b1..SDR50 requires tuning.
+ * 0b0..SDR does not require tuning.
+ */
+#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
+#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)
+#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)
+/*! RETUNING_MODE - Retuning Mode
+ * 0b00..Mode 1
+ * 0b01..Mode 2
+ * 0b10..Mode 3
+ * 0b11..Reserved
+ */
+#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
+#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)
+#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)
+/*! MBL - Max block length
+ * 0b000..512 bytes
+ * 0b001..1024 bytes
+ * 0b010..2048 bytes
+ * 0b011..4096 bytes
+ */
+#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
+#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)
+#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)
+/*! ADMAS - ADMA support
+ * 0b1..Advanced DMA supported
+ * 0b0..Advanced DMA not supported
+ */
+#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
+#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)
+#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)
+/*! HSS - High speed support
+ * 0b1..High speed supported
+ * 0b0..High speed not supported
+ */
+#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
+#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)
+#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)
+/*! DMAS - DMA support
+ * 0b1..DMA supported
+ * 0b0..DMA not supported
+ */
+#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
+#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)
+#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)
+/*! SRS - Suspend / resume support
+ * 0b1..Supported
+ * 0b0..Not supported
+ */
+#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
+#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)
+#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)
+/*! VS33 - Voltage support 3.3 V
+ * 0b1..3.3 V supported
+ * 0b0..3.3 V not supported
+ */
+#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
+#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)
+#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)
+/*! VS30 - Voltage support 3.0 V
+ * 0b1..3.0 V supported
+ * 0b0..3.0 V not supported
+ */
+#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
+#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)
+#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)
+/*! VS18 - Voltage support 1.8 V
+ * 0b1..1.8 V supported
+ * 0b0..1.8 V not supported
+ */
+#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
+/*! @} */
+
+/*! @name WTMK_LVL - Watermark Level */
+/*! @{ */
+#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)
+#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U)
+/*! RD_WML - Read watermark level
+ */
+#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
+#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)
+#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)
+/*! RD_BRST_LEN - Read burst length due to system restriction, the actual burst length might not exceed 16
+ */
+#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
+#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)
+#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U)
+/*! WR_WML - Write watermark level
+ */
+#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
+#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)
+#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)
+/*! WR_BRST_LEN - Write burst length due to system restriction, the actual burst length might not exceed 16
+ */
+#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
+/*! @} */
+
+/*! @name MIX_CTRL - Mixer Control */
+/*! @{ */
+#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U)
+#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U)
+/*! DMAEN - DMA enable
+ * 0b1..Enable
+ * 0b0..Disable
+ */
+#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
+#define USDHC_MIX_CTRL_BCEN_MASK (0x2U)
+#define USDHC_MIX_CTRL_BCEN_SHIFT (1U)
+/*! BCEN - Block count enable
+ * 0b1..Enable
+ * 0b0..Disable
+ */
+#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
+#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U)
+#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U)
+/*! AC12EN - Auto CMD12 enable
+ * 0b1..Enable
+ * 0b0..Disable
+ */
+#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
+#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)
+#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)
+/*! DDR_EN - Dual data rate mode selection
+ */
+#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
+#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)
+#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)
+/*! DTDSEL - Data transfer direction select
+ * 0b1..Read (Card to host)
+ * 0b0..Write (Host to card)
+ */
+#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
+#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)
+#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)
+/*! MSBSEL - Multi / Single block select
+ * 0b1..Multiple blocks
+ * 0b0..Single block
+ */
+#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
+#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)
+#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)
+/*! NIBBLE_POS - Nibble position indication
+ */
+#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
+#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U)
+#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U)
+/*! AC23EN - Auto CMD23 enable
+ */
+#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
+#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)
+#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)
+/*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
+ * 0b1..Execute tuning
+ * 0b0..Not tuned or tuning completed
+ */
+#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
+#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)
+#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)
+/*! SMP_CLK_SEL - Clock selection
+ * 0b1..Tuned clock is used to sample data / cmd
+ * 0b0..Fixed clock is used to sample data / cmd
+ */
+#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
+#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)
+#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)
+/*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)
+ * 0b1..Enable auto tuning
+ * 0b0..Disable auto tuning
+ */
+#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
+#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)
+#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)
+/*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
+ * 0b1..Feedback clock comes from the ipp_card_clk_out
+ * 0b0..Feedback clock comes from the loopback CLK
+ */
+#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
+#define USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U)
+#define USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U)
+/*! HS400_MODE - Enable HS400 mode
+ */
+#define USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)
+/*! @} */
+
+/*! @name FORCE_EVENT - Force Event */
+/*! @{ */
+#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)
+#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)
+/*! FEVTAC12NE - Force event auto command 12 not executed
+ */
+#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
+#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)
+#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)
+/*! FEVTAC12TOE - Force event auto command 12 time out error
+ */
+#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
+#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)
+#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)
+/*! FEVTAC12CE - Force event auto command 12 CRC error
+ */
+#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
+#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)
+#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)
+/*! FEVTAC12EBE - Force event Auto Command 12 end bit error
+ */
+#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
+#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)
+#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)
+/*! FEVTAC12IE - Force event Auto Command 12 index error
+ */
+#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
+#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)
+#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)
+/*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error
+ */
+#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
+#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)
+#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)
+/*! FEVTCTOE - Force event command time out error
+ */
+#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
+#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)
+#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)
+/*! FEVTCCE - Force event command CRC error
+ */
+#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
+#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)
+#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)
+/*! FEVTCEBE - Force event command end bit error
+ */
+#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
+#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)
+#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)
+/*! FEVTCIE - Force event command index error
+ */
+#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
+#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)
+#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)
+/*! FEVTDTOE - Force event data time out error
+ */
+#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
+#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)
+#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)
+/*! FEVTDCE - Force event data CRC error
+ */
+#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
+#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)
+#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)
+/*! FEVTDEBE - Force event data end bit error
+ */
+#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
+#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)
+#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)
+/*! FEVTAC12E - Force event Auto Command 12 error
+ */
+#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
+#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)
+#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)
+/*! FEVTTNE - Force tuning error
+ */
+#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
+#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)
+#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)
+/*! FEVTDMAE - Force event DMA error
+ */
+#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
+#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)
+#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)
+/*! FEVTCINT - Force event card interrupt
+ */
+#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
+/*! @} */
+
+/*! @name ADMA_ERR_STATUS - ADMA Error Status */
+/*! @{ */
+#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)
+#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)
+/*! ADMAES - ADMA error state (when ADMA error is occurred)
+ */
+#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
+#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)
+#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)
+/*! ADMALME - ADMA length mismatch error
+ * 0b1..Error
+ * 0b0..No error
+ */
+#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
+#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)
+#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)
+/*! ADMADCE - ADMA descriptor error
+ * 0b1..Error
+ * 0b0..No error
+ */
+#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
+/*! @} */
+
+/*! @name ADMA_SYS_ADDR - ADMA System Address */
+/*! @{ */
+#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)
+#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)
+/*! ADS_ADDR - ADMA system address
+ */
+#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
+/*! @} */
+
+/*! @name DLL_CTRL - DLL (Delay Line) Control */
+/*! @{ */
+#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)
+#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)
+/*! DLL_CTRL_ENABLE - DLL and delay chain
+ */
+#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
+#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)
+#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)
+/*! DLL_CTRL_RESET - DLL reset
+ */
+#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
+/*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line
+ */
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
+/*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0
+ */
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
+#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
+#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
+/*! DLL_CTRL_GATE_UPDATE - DLL gate update
+ */
+#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
+/*! DLL_CTRL_SLV_OVERRIDE - DLL slave override
+ */
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
+/*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val
+ */
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
+/*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1
+ */
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
+/*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval
+ */
+#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
+#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
+#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
+/*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval
+ */
+#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
+/*! @} */
+
+/*! @name DLL_STATUS - DLL Status */
+/*! @{ */
+#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)
+#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)
+/*! DLL_STS_SLV_LOCK - Slave delay-line lock status
+ */
+#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
+#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)
+#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)
+/*! DLL_STS_REF_LOCK - Reference DLL lock status
+ */
+#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
+#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)
+#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)
+/*! DLL_STS_SLV_SEL - Slave delay line select status
+ */
+#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
+#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)
+#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)
+/*! DLL_STS_REF_SEL - Reference delay line select taps
+ */
+#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
+/*! @} */
+
+/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
+/*! @{ */
+#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
+#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
+/*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST
+ */
+#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
+#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
+#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
+/*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT
+ */
+#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
+#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
+#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
+/*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE
+ */
+#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
+#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)
+#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
+/*! NXT_ERR - NXT error
+ */
+#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
+#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
+#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
+/*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST
+ */
+#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
+#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
+#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
+/*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT
+ */
+#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
+#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
+#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
+/*! TAP_SEL_PRE - TAP_SEL_PRE
+ */
+#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
+#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)
+#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
+/*! PRE_ERR - PRE error
+ */
+#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
+/*! @} */
+
+/*! @name STROBE_DLL_CTRL - Strobe DLL control */
+/*! @{ */
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
+/*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable
+ */
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
+/*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset
+ */
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
+/*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated
+ */
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x38U)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
+/*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target
+ */
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK (0x40U)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT (6U)
+/*! STROBE_DLL_CTRL_GATE_UPDATE_0 - Strobe DLL control gate update
+ */
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK (0x80U)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT (7U)
+/*! STROBE_DLL_CTRL_GATE_UPDATE_1 - Strobe DLL control gate update
+ */
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
+/*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override
+ */
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
+/*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value
+ */
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
+/*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval
+ */
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
+/*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval
+ */
+#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
+/*! @} */
+
+/*! @name STROBE_DLL_STATUS - Strobe DLL status */
+/*! @{ */
+#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
+#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
+/*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock
+ */
+#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)
+#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
+#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
+/*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock
+ */
+#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)
+#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
+#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
+/*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select
+ */
+#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)
+#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
+#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
+/*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select
+ */
+#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
+/*! @} */
+
+/*! @name VEND_SPEC - Vendor Specific Register */
+/*! @{ */
+#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U)
+#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U)
+/*! VSELECT - Voltage selection
+ * 0b1..Change the voltage to low voltage range, around 1.8 V
+ * 0b0..Change the voltage to high voltage range, around 3.0 V
+ */
+#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
+#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)
+#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)
+/*! CONFLICT_CHK_EN - Conflict check enable
+ * 0b0..Conflict check disable
+ * 0b1..Conflict check enable
+ */
+#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
+#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)
+#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
+/*! AC12_WR_CHKBUSY_EN - Check busy enable
+ * 0b0..Do not check busy after auto CMD12 for write data packet
+ * 0b1..Check busy after auto CMD12 for write data packet
+ */
+#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
+#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)
+#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)
+/*! FRC_SDCLK_ON - Force CLK
+ * 0b0..CLK active or inactive is fully controlled by the hardware.
+ * 0b1..Force CLK active
+ */
+#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
+#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)
+#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)
+/*! CRC_CHK_DIS - CRC Check Disable
+ * 0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet
+ * 0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet
+ */
+#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
+#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)
+#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)
+/*! CMD_BYTE_EN - Byte access
+ * 0b0..Disable
+ * 0b1..Enable
+ */
+#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
+/*! @} */
+
+/*! @name MMC_BOOT - MMC Boot */
+/*! @{ */
+#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)
+#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)
+/*! DTOCV_ACK - Boot ACK time out
+ * 0b0000..SDCLK x 2^14
+ * 0b0001..SDCLK x 2^15
+ * 0b0010..SDCLK x 2^16
+ * 0b0011..SDCLK x 2^17
+ * 0b0100..SDCLK x 2^18
+ * 0b0101..SDCLK x 2^19
+ * 0b0110..SDCLK x 2^20
+ * 0b0111..SDCLK x 2^21
+ * 0b1110..SDCLK x 2^28
+ * 0b1111..SDCLK x 2^29
+ */
+#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
+#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)
+#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)
+/*! BOOT_ACK - BOOT ACK
+ * 0b0..No ack
+ * 0b1..Ack
+ */
+#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
+#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)
+#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)
+/*! BOOT_MODE - Boot mode
+ * 0b0..Normal boot
+ * 0b1..Alternative boot
+ */
+#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
+#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)
+#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)
+/*! BOOT_EN - Boot enable
+ * 0b0..Fast boot disable
+ * 0b1..Fast boot enable
+ */
+#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
+#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)
+#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)
+/*! AUTO_SABG_EN - Auto stop at block gap
+ */
+#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
+#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)
+#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)
+/*! DISABLE_TIME_OUT - Time out
+ * 0b0..Enable time out
+ * 0b1..Disable time out
+ */
+#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
+#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)
+#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)
+/*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode
+ */
+#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
+/*! @} */
+
+/*! @name VEND_SPEC2 - Vendor Specific 2 Register */
+/*! @{ */
+#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)
+#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)
+/*! CARD_INT_D3_TEST - Card interrupt detection test
+ * 0b0..Check the card interrupt only when DATA3 is high.
+ * 0b1..Check the card interrupt by ignoring the status of DATA3.
+ */
+#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
+#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)
+#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)
+/*! TUNING_8bit_EN - Tuning 8bit enable
+ */
+#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
+#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)
+#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)
+/*! TUNING_1bit_EN - Tuning 1bit enable
+ */
+#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
+#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)
+#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)
+/*! TUNING_CMD_EN - Tuning command enable
+ * 0b0..Auto tuning circuit does not check the CMD line.
+ * 0b1..Auto tuning circuit checks the CMD line.
+ */
+#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
+#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
+#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
+/*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable
+ */
+#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)
+#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
+#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
+/*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable
+ */
+#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)
+#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)
+#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)
+/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
+ * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.
+ * 0b0..Disable
+ */
+#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
+/*! @} */
+
+/*! @name TUNING_CTRL - Tuning Control */
+/*! @{ */
+#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)
+#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
+/*! TUNING_START_TAP - Tuning start
+ */
+#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
+#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)
+#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)
+/*! TUNING_COUNTER - Tuning counter
+ */
+#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
+#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)
+#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)
+/*! TUNING_STEP - TUNING_STEP
+ */
+#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
+#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)
+#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)
+/*! TUNING_WINDOW - Data window
+ */
+#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
+#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)
+#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)
+/*! STD_TUNING_EN - Standard tuning circuit and procedure enable
+ */
+#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USDHC_Register_Masks */
+
+
+/* USDHC - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral USDHC0 base address */
+ #define USDHC0_BASE (0x50136000u)
+ /** Peripheral USDHC0 base address */
+ #define USDHC0_BASE_NS (0x40136000u)
+ /** Peripheral USDHC0 base pointer */
+ #define USDHC0 ((USDHC_Type *)USDHC0_BASE)
+ /** Peripheral USDHC0 base pointer */
+ #define USDHC0_NS ((USDHC_Type *)USDHC0_BASE_NS)
+ /** Peripheral USDHC1 base address */
+ #define USDHC1_BASE (0x50137000u)
+ /** Peripheral USDHC1 base address */
+ #define USDHC1_BASE_NS (0x40137000u)
+ /** Peripheral USDHC1 base pointer */
+ #define USDHC1 ((USDHC_Type *)USDHC1_BASE)
+ /** Peripheral USDHC1 base pointer */
+ #define USDHC1_NS ((USDHC_Type *)USDHC1_BASE_NS)
+ /** Array initializer of USDHC peripheral base addresses */
+ #define USDHC_BASE_ADDRS { USDHC0_BASE, USDHC1_BASE }
+ /** Array initializer of USDHC peripheral base pointers */
+ #define USDHC_BASE_PTRS { USDHC0, USDHC1 }
+ /** Array initializer of USDHC peripheral base addresses */
+ #define USDHC_BASE_ADDRS_NS { USDHC0_BASE_NS, USDHC1_BASE_NS }
+ /** Array initializer of USDHC peripheral base pointers */
+ #define USDHC_BASE_PTRS_NS { USDHC0_NS, USDHC1_NS }
+#else
+ /** Peripheral USDHC0 base address */
+ #define USDHC0_BASE (0x40136000u)
+ /** Peripheral USDHC0 base pointer */
+ #define USDHC0 ((USDHC_Type *)USDHC0_BASE)
+ /** Peripheral USDHC1 base address */
+ #define USDHC1_BASE (0x40137000u)
+ /** Peripheral USDHC1 base pointer */
+ #define USDHC1 ((USDHC_Type *)USDHC1_BASE)
+ /** Array initializer of USDHC peripheral base addresses */
+ #define USDHC_BASE_ADDRS { USDHC0_BASE, USDHC1_BASE }
+ /** Array initializer of USDHC peripheral base pointers */
+ #define USDHC_BASE_PTRS { USDHC0, USDHC1 }
+#endif
+/** Interrupt vectors for the USDHC peripheral type */
+#define USDHC_IRQS { USDHC0_IRQn, USDHC1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UTICK Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
+ * @{
+ */
+
+/** UTICK - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< Control, offset: 0x0 */
+ __IO uint32_t STAT; /**< Status, offset: 0x4 */
+ __IO uint32_t CFG; /**< Capture Configuration, offset: 0x8 */
+ __O uint32_t CAPCLR; /**< Capture Clear, offset: 0xC */
+ __I uint32_t CAP[4]; /**< Capture, array offset: 0x10, array step: 0x4 */
+} UTICK_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UTICK Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Register_Masks UTICK Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control */
+/*! @{ */
+#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU)
+#define UTICK_CTRL_DELAYVAL_SHIFT (0U)
+/*! DELAYVAL - Tick interval
+ */
+#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
+#define UTICK_CTRL_REPEAT_MASK (0x80000000U)
+#define UTICK_CTRL_REPEAT_SHIFT (31U)
+/*! REPEAT - Repeat delay
+ * 0b0..One-time delay
+ * 0b1..Delay repeats continuously
+ */
+#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
+/*! @} */
+
+/*! @name STAT - Status */
+/*! @{ */
+#define UTICK_STAT_INTR_MASK (0x1U)
+#define UTICK_STAT_INTR_SHIFT (0U)
+/*! INTR - Interrupt flag
+ * 0b0..No interrupt is pending
+ * 0b1..An interrupt is pending
+ */
+#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
+#define UTICK_STAT_ACTIVE_MASK (0x2U)
+#define UTICK_STAT_ACTIVE_SHIFT (1U)
+/*! ACTIVE - Timer active flag
+ * 0b0..The Micro-Tick Timer is not active (stopped)
+ * 0b1..The Micro-Tick Timer is currently active
+ */
+#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
+/*! @} */
+
+/*! @name CFG - Capture Configuration */
+/*! @{ */
+#define UTICK_CFG_CAPEN0_MASK (0x1U)
+#define UTICK_CFG_CAPEN0_SHIFT (0U)
+/*! CAPEN0 - Enable Capture 0
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
+#define UTICK_CFG_CAPEN1_MASK (0x2U)
+#define UTICK_CFG_CAPEN1_SHIFT (1U)
+/*! CAPEN1 - Enable Capture 1
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
+#define UTICK_CFG_CAPEN2_MASK (0x4U)
+#define UTICK_CFG_CAPEN2_SHIFT (2U)
+/*! CAPEN2 - Enable Capture 2
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
+#define UTICK_CFG_CAPEN3_MASK (0x8U)
+#define UTICK_CFG_CAPEN3_SHIFT (3U)
+/*! CAPEN3 - Enable Capture 3
+ * 0b0..Disabled
+ * 0b1..Enabled
+ */
+#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
+#define UTICK_CFG_CAPPOL0_MASK (0x100U)
+#define UTICK_CFG_CAPPOL0_SHIFT (8U)
+/*! CAPPOL0 - Capture Polarity 0
+ * 0b0..Positive edge capture
+ * 0b1..Negative edge capture
+ */
+#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
+#define UTICK_CFG_CAPPOL1_MASK (0x200U)
+#define UTICK_CFG_CAPPOL1_SHIFT (9U)
+/*! CAPPOL1 - Capture Polarity 1
+ * 0b0..Positive edge capture
+ * 0b1..Negative edge capture
+ */
+#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
+#define UTICK_CFG_CAPPOL2_MASK (0x400U)
+#define UTICK_CFG_CAPPOL2_SHIFT (10U)
+/*! CAPPOL2 - Capture Polarity 2
+ * 0b0..Positive edge capture
+ * 0b1..Negative edge capture
+ */
+#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
+#define UTICK_CFG_CAPPOL3_MASK (0x800U)
+#define UTICK_CFG_CAPPOL3_SHIFT (11U)
+/*! CAPPOL3 - Capture Polarity 3
+ * 0b0..Positive edge capture
+ * 0b1..Negative edge capture
+ */
+#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
+/*! @} */
+
+/*! @name CAPCLR - Capture Clear */
+/*! @{ */
+#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U)
+#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U)
+/*! CAPCLR0 - Clear capture 0
+ * 0b0..Does nothing
+ * 0b1..Write 1 to clear the CAP0 register value
+ */
+#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
+#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U)
+#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U)
+/*! CAPCLR1 - Clear capture 1
+ * 0b0..Does nothing
+ * 0b1..Write 1 to clear the CAP1 register value
+ */
+#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
+#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U)
+#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U)
+/*! CAPCLR2 - Clear capture 2
+ * 0b0..Does nothing
+ * 0b1..Write 1 to clear the CAP2 register value
+ */
+#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
+#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U)
+#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U)
+/*! CAPCLR3 - Clear capture 3
+ * 0b0..Does nothing
+ * 0b1..Write 1 to clear the CAP3 register value
+ */
+#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
+/*! @} */
+
+/*! @name CAP - Capture */
+/*! @{ */
+#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU)
+#define UTICK_CAP_CAP_VALUE_SHIFT (0U)
+/*! CAP_VALUE - Captured value for the related capture event
+ */
+#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
+#define UTICK_CAP_VALID_MASK (0x80000000U)
+#define UTICK_CAP_VALID_SHIFT (31U)
+/*! VALID - Captured value is valid
+ * 0b0..A valid value has been not been captured
+ * 0b1..A valid value has been captured, based on a transition of the related UTICK_CAPn pin
+ */
+#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
+/*! @} */
+
+/* The count of UTICK_CAP */
+#define UTICK_CAP_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group UTICK_Register_Masks */
+
+
+/* UTICK - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral UTICK0 base address */
+ #define UTICK0_BASE (0x5000F000u)
+ /** Peripheral UTICK0 base address */
+ #define UTICK0_BASE_NS (0x4000F000u)
+ /** Peripheral UTICK0 base pointer */
+ #define UTICK0 ((UTICK_Type *)UTICK0_BASE)
+ /** Peripheral UTICK0 base pointer */
+ #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS)
+ /** Array initializer of UTICK peripheral base addresses */
+ #define UTICK_BASE_ADDRS { UTICK0_BASE }
+ /** Array initializer of UTICK peripheral base pointers */
+ #define UTICK_BASE_PTRS { UTICK0 }
+ /** Array initializer of UTICK peripheral base addresses */
+ #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS }
+ /** Array initializer of UTICK peripheral base pointers */
+ #define UTICK_BASE_PTRS_NS { UTICK0_NS }
+#else
+ /** Peripheral UTICK0 base address */
+ #define UTICK0_BASE (0x4000F000u)
+ /** Peripheral UTICK0 base pointer */
+ #define UTICK0 ((UTICK_Type *)UTICK0_BASE)
+ /** Array initializer of UTICK peripheral base addresses */
+ #define UTICK_BASE_ADDRS { UTICK0_BASE }
+ /** Array initializer of UTICK peripheral base pointers */
+ #define UTICK_BASE_PTRS { UTICK0 }
+#endif
+/** Interrupt vectors for the UTICK peripheral type */
+#define UTICK_IRQS { UTICK0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UTICK_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- WWDT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
+ * @{
+ */
+
+/** WWDT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MOD; /**< Mode, offset: 0x0 */
+ __IO uint32_t TC; /**< Timer Constant, offset: 0x4 */
+ __O uint32_t FEED; /**< Feed Sequence, offset: 0x8 */
+ __I uint32_t TV; /**< Timer Value, offset: 0xC */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t WARNINT; /**< Warning Interrupt Compare Value, offset: 0x14 */
+ __IO uint32_t WINDOW; /**< Window Compare Value, offset: 0x18 */
+} WWDT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- WWDT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Register_Masks WWDT Register Masks
+ * @{
+ */
+
+/*! @name MOD - Mode */
+/*! @{ */
+#define WWDT_MOD_WDEN_MASK (0x1U)
+#define WWDT_MOD_WDEN_SHIFT (0U)
+/*! WDEN - Watchdog Enable
+ * 0b0..Stop. The Watchdog timer is stopped.
+ * 0b1..Run. The Watchdog timer is running.
+ */
+#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
+#define WWDT_MOD_WDRESET_MASK (0x2U)
+#define WWDT_MOD_WDRESET_SHIFT (1U)
+/*! WDRESET - Watchdog Reset Enable
+ * 0b0..Interrupt. A Watchdog timeout will not cause a chip reset.
+ * 0b1..Reset. A Watchdog timeout will cause a chip reset.
+ */
+#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
+#define WWDT_MOD_WDTOF_MASK (0x4U)
+#define WWDT_MOD_WDTOF_SHIFT (2U)
+/*! WDTOF - Watchdog Timeout Flag
+ * 0b0..Clear.
+ * 0b1..Reset. Causes a chip reset if WDRESET = 1.
+ */
+#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
+#define WWDT_MOD_WDINT_MASK (0x8U)
+#define WWDT_MOD_WDINT_SHIFT (3U)
+/*! WDINT - Warning Interrupt Flag
+ * 0b0..No flag.
+ * 0b1..Flag. The Watchdog interrupt flag is set when the Watchdog counter is no longer greater than the value specified by WARNINT.
+ */
+#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
+#define WWDT_MOD_WDPROTECT_MASK (0x10U)
+#define WWDT_MOD_WDPROTECT_SHIFT (4U)
+/*! WDPROTECT - Watchdog Update Mode
+ * 0b0..Flexible
+ * 0b1..Threshold
+ */
+#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
+#define WWDT_MOD_LOCK_MASK (0x20U)
+#define WWDT_MOD_LOCK_SHIFT (5U)
+/*! LOCK - Lock
+ * 0b0..No Lock
+ * 0b1..Lock
+ */
+#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
+/*! @} */
+
+/*! @name TC - Timer Constant */
+/*! @{ */
+#define WWDT_TC_COUNT_MASK (0xFFFFFFU)
+#define WWDT_TC_COUNT_SHIFT (0U)
+/*! COUNT - Watchdog Timeout Value
+ */
+#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
+/*! @} */
+
+/*! @name FEED - Feed Sequence */
+/*! @{ */
+#define WWDT_FEED_FEED_MASK (0xFFU)
+#define WWDT_FEED_FEED_SHIFT (0U)
+/*! FEED - Feed Value
+ */
+#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
+/*! @} */
+
+/*! @name TV - Timer Value */
+/*! @{ */
+#define WWDT_TV_COUNT_MASK (0xFFFFFFU)
+#define WWDT_TV_COUNT_SHIFT (0U)
+/*! COUNT - Counter Timer Value
+ */
+#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
+/*! @} */
+
+/*! @name WARNINT - Warning Interrupt Compare Value */
+/*! @{ */
+#define WWDT_WARNINT_WARNINT_MASK (0x3FFU)
+#define WWDT_WARNINT_WARNINT_SHIFT (0U)
+/*! WARNINT - Watchdog Warning Interrupt Compare Value
+ */
+#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
+/*! @} */
+
+/*! @name WINDOW - Window Compare Value */
+/*! @{ */
+#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU)
+#define WWDT_WINDOW_WINDOW_SHIFT (0U)
+/*! WINDOW - Watchdog Window Value.
+ */
+#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group WWDT_Register_Masks */
+
+
+/* WWDT - Peripheral instance base addresses */
+#if (__ARM_FEATURE_CMSE & 0x2)
+ /** Peripheral WWDT0 base address */
+ #define WWDT0_BASE (0x5000E000u)
+ /** Peripheral WWDT0 base address */
+ #define WWDT0_BASE_NS (0x4000E000u)
+ /** Peripheral WWDT0 base pointer */
+ #define WWDT0 ((WWDT_Type *)WWDT0_BASE)
+ /** Peripheral WWDT0 base pointer */
+ #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS)
+ /** Peripheral WWDT1 base address */
+ #define WWDT1_BASE (0x5002E000u)
+ /** Peripheral WWDT1 base address */
+ #define WWDT1_BASE_NS (0x4002E000u)
+ /** Peripheral WWDT1 base pointer */
+ #define WWDT1 ((WWDT_Type *)WWDT1_BASE)
+ /** Peripheral WWDT1 base pointer */
+ #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS)
+ /** Array initializer of WWDT peripheral base addresses */
+ #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE }
+ /** Array initializer of WWDT peripheral base pointers */
+ #define WWDT_BASE_PTRS { WWDT0, WWDT1 }
+ /** Array initializer of WWDT peripheral base addresses */
+ #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS }
+ /** Array initializer of WWDT peripheral base pointers */
+ #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS }
+#else
+ /** Peripheral WWDT0 base address */
+ #define WWDT0_BASE (0x4000E000u)
+ /** Peripheral WWDT0 base pointer */
+ #define WWDT0 ((WWDT_Type *)WWDT0_BASE)
+ /** Peripheral WWDT1 base address */
+ #define WWDT1_BASE (0x4002E000u)
+ /** Peripheral WWDT1 base pointer */
+ #define WWDT1 ((WWDT_Type *)WWDT1_BASE)
+ /** Array initializer of WWDT peripheral base addresses */
+ #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE }
+ /** Array initializer of WWDT peripheral base pointers */
+ #define WWDT_BASE_PTRS { WWDT0, WWDT1 }
+#endif
+/** Interrupt vectors for the WWDT peripheral type */
+#define WWDT_IRQS { WDT0_IRQn, WDT1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group WWDT_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+ #else
+ #pragma pop
+ #endif
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header
+ #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDK Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+/** Used for get the base address of ROM API */
+#define FSL_ROM_API_BASE_ADDR 0x1302F000U
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif /* _MIMXRT595S_CM33_H_ */
+
diff --git a/minimal-examples/embedded/rt595/hello_world/project/device/MIMXRT595S_cm33_features.h b/minimal-examples/embedded/rt595/hello_world/project/device/MIMXRT595S_cm33_features.h
new file mode 100644
index 000000000..b355d7cd8
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/device/MIMXRT595S_cm33_features.h
@@ -0,0 +1,627 @@
+/*
+** ###################################################################
+** Version: rev. 4.0, 2020-05-18
+** Build: b210526
+**
+** Abstract:
+** Chip specific module features.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2021 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2019-04-19)
+** Initial version.
+** - rev. 2.0 (2019-07-22)
+** Base on rev 0.7 RM.
+** - rev. 3.0 (2020-03-16)
+** Base on Rev.A RM.
+** - rev. 4.0 (2020-05-18)
+** Base on Rev.B RM.
+**
+** ###################################################################
+*/
+
+#ifndef _MIMXRT595S_cm33_FEATURES_H_
+#define _MIMXRT595S_cm33_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ACMP availability on the SoC. */
+#define FSL_FEATURE_SOC_ACMP_COUNT (1)
+/* @brief AIPS availability on the SoC. */
+#define FSL_FEATURE_SOC_AIPS_COUNT (2)
+/* @brief CACHE64_CTRL availability on the SoC. */
+#define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (2)
+/* @brief CACHE64_POLSEL availability on the SoC. */
+#define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (2)
+/* @brief CASPER availability on the SoC. */
+#define FSL_FEATURE_SOC_CASPER_COUNT (1)
+/* @brief CLKCTL0 availability on the SoC. */
+#define FSL_FEATURE_SOC_CLKCTL0_COUNT (1)
+/* @brief CLKCTL1 availability on the SoC. */
+#define FSL_FEATURE_SOC_CLKCTL1_COUNT (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (2)
+/* @brief DMIC availability on the SoC. */
+#define FSL_FEATURE_SOC_DMIC_COUNT (1)
+/* @brief FLEXCOMM availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (17)
+/* @brief FLEXIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXIO_COUNT (1)
+/* @brief FLEXSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXSPI_COUNT (2)
+/* @brief FREQME availability on the SoC. */
+#define FSL_FEATURE_SOC_FREQME_COUNT (1)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)
+/* @brief SECGPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_SECGPIO_COUNT (1)
+/* @brief HASHCRYPT availability on the SoC. */
+#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (15)
+/* @brief I3C availability on the SoC. */
+#define FSL_FEATURE_SOC_I3C_COUNT (2)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (14)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOPCTL availability on the SoC. */
+#define FSL_FEATURE_SOC_IOPCTL_COUNT (1)
+/* @brief LCDIF availability on the SoC. */
+#define FSL_FEATURE_SOC_LCDIF_COUNT (1)
+/* @brief LPADC availability on the SoC. */
+#define FSL_FEATURE_SOC_LPADC_COUNT (1)
+/* @brief MIPI_DSI_HOST availability on the SoC. */
+#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT (1)
+/* @brief MU availability on the SoC. */
+#define FSL_FEATURE_SOC_MU_COUNT (1)
+/* @brief OCOTP availability on the SoC. */
+#define FSL_FEATURE_SOC_OCOTP_COUNT (1)
+/* @brief OSTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
+/* @brief OTFAD availability on the SoC. */
+#define FSL_FEATURE_SOC_OTFAD_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief PMC availability on the SoC. */
+#define FSL_FEATURE_SOC_PMC_COUNT (1)
+/* @brief POWERQUAD availability on the SoC. */
+#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
+/* @brief PUF availability on the SoC. */
+#define FSL_FEATURE_SOC_PUF_COUNT (1)
+/* @brief RSTCTL0 availability on the SoC. */
+#define FSL_FEATURE_SOC_RSTCTL0_COUNT (1)
+/* @brief RSTCTL1 availability on the SoC. */
+#define FSL_FEATURE_SOC_RSTCTL1_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT (1)
+/* @brief SEMA42 availability on the SoC. */
+#define FSL_FEATURE_SOC_SEMA42_COUNT (1)
+/* @brief SMARTDMA availability on the SoC. */
+#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (16)
+/* @brief SYSCTL0 availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCTL0_COUNT (1)
+/* @brief SYSCTL1 availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1)
+/* @brief TRNG availability on the SoC. */
+#define FSL_FEATURE_SOC_TRNG_COUNT (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (14)
+/* @brief USBHSD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
+/* @brief USBHSDCD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSDCD_COUNT (1)
+/* @brief USBHSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
+/* @brief USBPHY availability on the SoC. */
+#define FSL_FEATURE_SOC_USBPHY_COUNT (1)
+/* @brief USDHC availability on the SoC. */
+#define FSL_FEATURE_SOC_USDHC_COUNT (2)
+/* @brief UTICK availability on the SoC. */
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (2)
+
+/* ACMP module features */
+
+/* @brief Has CMP_C3. */
+#define FSL_FEATURE_ACMP_HAS_C3_REG (1)
+/* @brief Has C0 LINKEN Bit */
+#define FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT (1)
+/* @brief Has C0 OFFSET Bit */
+#define FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT (0)
+/* @brief Has C1 INPSEL Bit */
+#define FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT (0)
+/* @brief Has C1 INNSEL Bit */
+#define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (0)
+/* @brief Has C1 DACOE Bit */
+#define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (0)
+/* @brief Has C1 DMODE Bit */
+#define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1)
+/* @brief Has C2 RRE Bit */
+#define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0)
+
+/* LPADC module features */
+
+/* @brief FIFO availability on the SoC. */
+#define FSL_FEATURE_LPADC_FIFO_COUNT (2)
+/* @brief Does not support two simultanious single ended conversions (bitfield TCTRL[FIFO_SEL_B]). */
+#define FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B (1)
+/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
+/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (1)
+/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (1)
+/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (0)
+/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (0)
+/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
+#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
+/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (0)
+/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (0)
+/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (0)
+/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
+/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
+/* @brief Has calibration (bitfield CFG[CALOFS]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
+/* @brief Has offset trim (register OFSTRIM). */
+#define FSL_FEATURE_LPADC_HAS_OFSTRIM (0)
+
+/* CACHE64_CTRL module features */
+
+/* @brief Cache Line size in byte. */
+#define FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE (32)
+
+/* CACHE64_POLSEL module features */
+
+/* No feature definitions */
+
+/* CASPER module features */
+
+/* @brief Base address of the CASPER dedicated RAM. */
+#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x40202000u)
+
+/* CRC module features */
+
+/* @brief Has data register with name CRC */
+#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
+
+/* DMA module features */
+
+/* @brief Number of channels */
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) (37)
+/* @brief Number of all DMA channels */
+#define FSL_FEATURE_DMA_ALL_CHANNELS (74)
+/* @brief Max Number of DMA channels */
+#define FSL_FEATURE_DMA_MAX_CHANNELS (37)
+/* @brief Align size of DMA descriptor */
+#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (1024)
+/* @brief DMA head link descriptor table align size */
+#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
+
+/* DMIC module features */
+
+/* @brief Number of channels */
+#define FSL_FEATURE_DMIC_CHANNEL_NUM (8)
+/* @brief DMIC channel support stereo data */
+#define FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6 (1)
+/* @brief DMIC does not support bypass channel clock */
+#define FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS (1)
+/* @brief DMIC channel FIFO register support sign extended */
+#define FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND (1)
+/* @brief DMIC has no IOCFG register */
+#define FSL_FEATURE_DMIC_HAS_NO_IOCFG (1)
+/* @brief DMIC has decimator reset function */
+#define FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC (1)
+/* @brief DMIC has global channel synchronization function */
+#define FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC (1)
+
+/* FLEXCOMM module features */
+
+/* @brief FLEXCOMM0 USART INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
+/* @brief FLEXCOMM0 SPI INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
+/* @brief FLEXCOMM0 I2C INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
+/* @brief FLEXCOMM0 I2S INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0)
+/* @brief FLEXCOMM1 USART INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
+/* @brief FLEXCOMM1 SPI INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
+/* @brief FLEXCOMM1 I2C INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
+/* @brief FLEXCOMM1 I2S INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1)
+/* @brief FLEXCOMM2 USART INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
+/* @brief FLEXCOMM2 SPI INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
+/* @brief FLEXCOMM2 I2C INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
+/* @brief FLEXCOMM2 I2S INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2)
+/* @brief FLEXCOMM3 USART INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
+/* @brief FLEXCOMM3 SPI INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
+/* @brief FLEXCOMM3 I2C INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
+/* @brief FLEXCOMM3 I2S INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3)
+/* @brief FLEXCOMM4 USART INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)
+/* @brief FLEXCOMM4 SPI INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)
+/* @brief FLEXCOMM4 I2C INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)
+/* @brief FLEXCOMM4 I2S INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4)
+/* @brief FLEXCOMM5 USART INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)
+/* @brief FLEXCOMM5 SPI INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)
+/* @brief FLEXCOMM5 I2C INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)
+/* @brief FLEXCOMM5 I2S INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5)
+/* @brief FLEXCOMM6 USART INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)
+/* @brief FLEXCOMM6 SPI INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)
+/* @brief FLEXCOMM6 I2C INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)
+/* @brief FLEXCOMM6 I2S INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6)
+/* @brief FLEXCOMM7 USART INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)
+/* @brief FLEXCOMM7 SPI INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)
+/* @brief FLEXCOMM7 I2C INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)
+/* @brief FLEXCOMM7 I2S INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7)
+/* @brief I2S has DMIC interconnection */
+#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \
+ (((x) == FLEXCOMM0) ? (1) : \
+ (((x) == FLEXCOMM1) ? (0) : \
+ (((x) == FLEXCOMM2) ? (0) : \
+ (((x) == FLEXCOMM3) ? (0) : \
+ (((x) == FLEXCOMM4) ? (0) : \
+ (((x) == FLEXCOMM5) ? (0) : \
+ (((x) == FLEXCOMM6) ? (0) : \
+ (((x) == FLEXCOMM7) ? (0) : \
+ (((x) == FLEXCOMM14) ? (0) : \
+ (((x) == FLEXCOMM15) ? (0) : \
+ (((x) == FLEXCOMM16) ? (0) : \
+ (((x) == FLEXCOMM8) ? (0) : \
+ (((x) == FLEXCOMM9) ? (0) : \
+ (((x) == FLEXCOMM10) ? (0) : \
+ (((x) == FLEXCOMM11) ? (0) : \
+ (((x) == FLEXCOMM12) ? (0) : \
+ (((x) == FLEXCOMM13) ? (0) : (-1))))))))))))))))))
+/* @brief FLEXCOMM14 SPI(HS_SPI) INDEX 14 */
+#define FSL_FEATURE_FLEXCOMM14_SPI_INDEX (14)
+/* @brief FLEXCOMM15 I2C INDEX 15 */
+#define FSL_FEATURE_FLEXCOMM15_I2C_INDEX (15)
+/* @brief FLEXCOMM16 SPI(HS_SPI) INDEX 16 */
+#define FSL_FEATURE_FLEXCOMM16_SPI_INDEX (16)
+/* @brief FLEXCOMM8 USART INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_USART_INDEX (8)
+/* @brief FLEXCOMM9 USART INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_USART_INDEX (9)
+/* @brief FLEXCOMM10 USART INDEX 10 */
+#define FSL_FEATURE_FLEXCOMM10_USART_INDEX (10)
+/* @brief FLEXCOMM11 USART INDEX 11 */
+#define FSL_FEATURE_FLEXCOMM11_USART_INDEX (11)
+/* @brief FLEXCOMM12 USART INDEX 12 */
+#define FSL_FEATURE_FLEXCOMM12_USART_INDEX (12)
+/* @brief FLEXCOMM13 USART INDEX 13 */
+#define FSL_FEATURE_FLEXCOMM13_USART_INDEX (13)
+/* @brief FLEXCOMM8 SPI INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8)
+/* @brief FLEXCOMM9 SPI INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_SPI_INDEX (9)
+/* @brief FLEXCOMM10 SPI INDEX 10 */
+#define FSL_FEATURE_FLEXCOMM10_SPI_INDEX (10)
+/* @brief FLEXCOMM11 SPI INDEX 11 */
+#define FSL_FEATURE_FLEXCOMM11_SPI_INDEX (11)
+/* @brief FLEXCOMM12 SPI INDEX 12 */
+#define FSL_FEATURE_FLEXCOMM12_SPI_INDEX (12)
+/* @brief FLEXCOMM13 SPI INDEX 13 */
+#define FSL_FEATURE_FLEXCOMM13_SPI_INDEX (13)
+/* @brief FLEXCOMM8 I2C INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_I2C_INDEX (8)
+/* @brief FLEXCOMM9 I2C INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_I2C_INDEX (9)
+/* @brief FLEXCOMM10 I2C INDEX 10 */
+#define FSL_FEATURE_FLEXCOMM10_I2C_INDEX (10)
+/* @brief FLEXCOMM11 I2C INDEX 11 */
+#define FSL_FEATURE_FLEXCOMM11_I2C_INDEX (11)
+/* @brief FLEXCOMM12 I2C INDEX 12 */
+#define FSL_FEATURE_FLEXCOMM12_I2C_INDEX (12)
+/* @brief FLEXCOMM13 I2C INDEX 13 */
+#define FSL_FEATURE_FLEXCOMM13_I2C_INDEX (13)
+/* @brief FLEXCOMM8 I2S INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_I2S_INDEX (8)
+/* @brief FLEXCOMM9 I2S INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_I2S_INDEX (9)
+/* @brief FLEXCOMM10 I2S INDEX 10 */
+#define FSL_FEATURE_FLEXCOMM10_I2S_INDEX (10)
+/* @brief FLEXCOMM11 I2S INDEX 11 */
+#define FSL_FEATURE_FLEXCOMM11_I2S_INDEX (11)
+/* @brief FLEXCOMM12 I2S INDEX 12 */
+#define FSL_FEATURE_FLEXCOMM12_I2S_INDEX (12)
+/* @brief FLEXCOMM13 I2S INDEX 13 */
+#define FSL_FEATURE_FLEXCOMM13_I2S_INDEX (13)
+
+/* FLEXIO module features */
+
+/* @brief FLEXIO support reset from RSTCTL */
+#define FSL_FEATURE_FLEXIO_HAS_RESET (1)
+/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
+#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
+/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
+#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
+/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
+/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
+/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
+/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
+#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
+/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
+#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
+/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
+#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
+/* @brief Reset value of the FLEXIO_VERID register */
+#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003)
+/* @brief Reset value of the FLEXIO_PARAM register */
+#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x10100808)
+
+/* FLEXSPI module features */
+
+/* @brief FlexSPI AHB buffer count */
+#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8)
+/* @brief FlexSPI0 and FlexSPI1 have shared IRQ */
+#define FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 (1)
+/* @brief FlexSPI has no MCR0 ARDFEN bit */
+#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (1)
+/* @brief FlexSPI has no MCR0 ATDFEN bit */
+#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (1)
+/* @brief FlexSPI DMA needs multiple DES to transfer */
+#define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1)
+/* @brief FlexSPI uses min DQS delay */
+#define FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN (1)
+/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */
+#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1)
+
+/* GPIO module features */
+
+/* @brief GPIO has interrupts */
+#define FSL_FEATURE_GPIO_HAS_INTERRUPT (1)
+
+/* HASHCRYPT module features */
+
+/* @brief hashcrypt has reload feature */
+#define FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE (1)
+
+/* I2S module features */
+
+/* @brief I2S support dual channel transfer. */
+#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
+/* @brief I2S has DMIC interconnection. */
+#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1)
+
+/* INPUTMUX module features */
+
+/* @brief Number of channels */
+#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1)
+/* @brief Inputmux has channel mux control */
+#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (1)
+
+/* MIPI_DSI_HOST module features */
+
+/* @brief Does not have DPHY PLL */
+#define FSL_FEATURE_MIPI_DSI_HOST_NO_DPHY_PLL (1)
+/* @brief Support TX ULPS */
+#define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS (0)
+/* @brief Has control register to enable or disable TX ULPS */
+#define FSL_FEATURE_MIPI_DSI_HOST_HAS_ULPS_CTRL (0)
+/* @brief Has pixel-link to DPI remap */
+#define FSL_FEATURE_MIPI_DSI_HOST_HAS_PXL2DPI (0)
+
+/* MRT module features */
+
+/* @brief number of channels. */
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
+
+/* MU module features */
+
+/* @brief MU side for current core */
+#define FSL_FEATURE_MU_SIDE_A (1)
+/* @brief MU Has register CCR */
+#define FSL_FEATURE_MU_HAS_CCR (0)
+/* @brief MU Has register SR[RS], BSR[ARS] */
+#define FSL_FEATURE_MU_HAS_SR_RS (1)
+/* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */
+#define FSL_FEATURE_MU_HAS_RESET_INT (1)
+/* @brief MU Has register SR[MURIP] */
+#define FSL_FEATURE_MU_HAS_SR_MURIP (0)
+/* @brief brief MU Has register SR[HRIP] */
+#define FSL_FEATURE_MU_HAS_SR_HRIP (0)
+/* @brief brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */
+#define FSL_FEATURE_MU_NO_CLKE (1)
+/* @brief brief MU does not support NMI, CR[NMI]. */
+#define FSL_FEATURE_MU_NO_NMI (1)
+/* @brief brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */
+#define FSL_FEATURE_MU_NO_RSTH (1)
+/* @brief brief MU does not supports MU reset, CR[MUR]. */
+#define FSL_FEATURE_MU_NO_MUR (0)
+/* @brief brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */
+#define FSL_FEATURE_MU_NO_HR (1)
+/* @brief brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */
+#define FSL_FEATURE_MU_HAS_HRM (0)
+
+/* OTFAD module features */
+
+/* @brief OTFAD has Security Violation Mode (SVM) */
+#define FSL_FEATURE_OTFAD_HAS_SVM_MODE (0)
+/* @brief OTFAD has Key Blob Processing */
+#define FSL_FEATURE_OTFAD_HAS_KEYBLOB_PROCESSING (0)
+/* @brief OTFAD has interrupt request enable */
+#define FSL_FEATURE_OTFAD_HAS_HAS_IRQ_ENABLE (0)
+/* @brief OTFAD has Force Error */
+#define FSL_FEATURE_OTFAD_HAS_FORCE_ERR (0)
+
+/* PINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
+
+/* PMC module features */
+
+/* @brief Has no OS Timer control register in PMC. */
+#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1)
+
+/* PUF module features */
+
+/* @brief PUF need to setup SRAM manually */
+#define FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL (1)
+/* @brief PUF has SHIFT_STATUS register. */
+#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (0)
+/* @brief PUF has IDXBLK_SHIFT register. */
+#define FSL_FEATURE_PUF_HAS_IDXBLK_SHIFT (0)
+
+/* RTC module features */
+
+/* @brief RTC does not support reset from RSTCTL. */
+#define FSL_FEATURE_RTC_HAS_NO_RESET (1)
+
+/* SCT module features */
+
+/* @brief Number of events */
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
+/* @brief Number of states */
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)
+/* @brief Number of match capture */
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
+/* @brief Number of outputs */
+#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
+
+/* SECGPIO module features */
+
+/* @brief GPIO has interrupts */
+#define FSL_FEATURE_SECGPIO_HAS_INTERRUPT (1)
+
+/* SEMA42 module features */
+
+/* @brief Gate counts */
+#define FSL_FEATURE_SEMA42_GATE_COUNT (16)
+
+/* TRNG module features */
+
+/* @brief Need configure default frequency minimum value */
+#define FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM (1)
+/* @brief The user configured frequency minimum value */
+#define FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM_VALUE (0)
+
+/* USBHSD module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40140000)
+/* @brief USBHSD version */
+#define FSL_FEATURE_USBHSD_VERSION (300)
+/* @brief Number of the endpoint in USB HS */
+#define FSL_FEATURE_USBHSD_EP_NUM (6)
+/* @brief The controller doesn't exit HS mode automatically after vbus becomes invalid */
+#define FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE (1)
+
+/* USBHSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40140000)
+/* @brief USBHSH version */
+#define FSL_FEATURE_USBHSH_VERSION (300)
+/* @brief USBHSH has packet turnaround time-out register */
+#define FSL_FEATURE_USBHSH_HAS_TURNAROUND_TIMEOUT (0)
+
+/* USBPHY module features */
+
+/* @brief USBPHY contain DCD analog module */
+#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (1)
+/* @brief USBPHY has register TRIM_OVERRIDE_EN */
+#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1)
+/* @brief USBPHY is 28FDSOI */
+#define FSL_FEATURE_USBPHY_28FDSOI (0)
+
+/* USDHC module features */
+
+/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
+#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0)
+/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
+#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1)
+/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
+#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1)
+/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
+#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1)
+/* @brief USDHC has reset control */
+#define FSL_FEATURE_USDHC_HAS_RESET (1)
+/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */
+#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0)
+/* @brief If USDHC instance support 8 bit width */
+#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1)
+/* @brief If USDHC instance support HS400 mode */
+#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) \
+ (((x) == USDHC0) ? (1) : \
+ (((x) == USDHC1) ? (0) : (-1)))
+/* @brief If USDHC instance support 1v8 signal */
+#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1)
+/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */
+#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (0)
+
+/* UTICK module features */
+
+/* @brief UTICK does not support power down configure. */
+#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
+
+/* WWDT module features */
+
+/* @brief WWDT does not support oscillator lock. */
+#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (0)
+/* @brief WWDT does not support power down configure. */
+#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
+
+#endif /* _MIMXRT595S_cm33_FEATURES_H_ */
+
diff --git a/minimal-examples/embedded/rt595/hello_world/project/device/fsl_device_registers.h b/minimal-examples/embedded/rt595/hello_world/project/device/fsl_device_registers.h
new file mode 100644
index 000000000..63502996f
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/device/fsl_device_registers.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_MIMXRT595SFAWC_cm33) || defined(CPU_MIMXRT595SFFOC_cm33))
+
+#define MIMXRT595S_cm33_SERIES
+
+/* CMSIS-style register definitions */
+#include "MIMXRT595S_cm33.h"
+/* CPU specific feature definitions */
+#include "MIMXRT595S_cm33_features.h"
+
+#elif (defined(CPU_MIMXRT595SFAWC_dsp) || defined(CPU_MIMXRT595SFFOC_dsp))
+
+#define MIMXRT595S_dsp_SERIES
+
+/* CMSIS-style register definitions */
+#include "MIMXRT595S_dsp.h"
+/* CPU specific feature definitions */
+#include "MIMXRT595S_dsp_features.h"
+
+#else
+ #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/minimal-examples/embedded/rt595/hello_world/project/device/system_MIMXRT595S_cm33.c b/minimal-examples/embedded/rt595/hello_world/project/device/system_MIMXRT595S_cm33.c
new file mode 100644
index 000000000..e8985aa3c
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/device/system_MIMXRT595S_cm33.c
@@ -0,0 +1,232 @@
+/*
+** ###################################################################
+** Processors: MIMXRT595SFAWC_cm33
+** MIMXRT595SFFOC_cm33
+**
+** Compilers: GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** Keil ARM C/C++ Compiler
+** MCUXpresso Compiler
+**
+** Reference manual: RT500 Reference Manual. Rev.C, 8/2020
+** Version: rev. 5.0, 2020-08-27
+** Build: b201016
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2019-04-19)
+** Initial version.
+** - rev. 2.0 (2019-07-22)
+** Base on rev 0.7 RM.
+** - rev. 3.0 (2020-03-16)
+** Base on Rev.A RM.
+** - rev. 4.0 (2020-05-18)
+** Base on Rev.B RM.
+** - rev. 5.0 (2020-08-27)
+** Base on Rev.C RM.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MIMXRT595S_cm33
+ * @version 5.0
+ * @date 2020-08-27
+ * @brief Device specific configuration file for MIMXRT595S_cm33 (implementation
+ * file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+#define SYSTEM_IS_XIP_FLEXSPI() \
+ ((((uint32_t)SystemCoreClockUpdate >= 0x08000000U) && ((uint32_t)SystemCoreClockUpdate < 0x10000000U)) || \
+ (((uint32_t)SystemCoreClockUpdate >= 0x18000000U) && ((uint32_t)SystemCoreClockUpdate < 0x20000000U)))
+
+/* Get OSC clock from SYSOSCBYPASS */
+static uint32_t getOscClk(void)
+{
+ return (CLKCTL0->SYSOSCBYPASS == 0U) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1U) ? CLK_EXT_CLKIN : 0U);
+}
+
+/* Get FRO DIV clock from FRODIVSEL */
+static uint32_t getFroDivClk(void)
+{
+ uint32_t freq = 0U;
+
+ switch ((CLKCTL0->FRODIVSEL) & CLKCTL0_FRODIVSEL_SEL_MASK)
+ {
+ case CLKCTL0_FRODIVSEL_SEL(0):
+ freq = CLK_FRO_DIV2_CLK;
+ break;
+ case CLKCTL0_FRODIVSEL_SEL(1):
+ freq = CLK_FRO_DIV4_CLK;
+ break;
+ case CLKCTL0_FRODIVSEL_SEL(2):
+ freq = CLK_FRO_DIV8_CLK;
+ break;
+ case CLKCTL0_FRODIVSEL_SEL(3):
+ freq = CLK_FRO_DIV16_CLK;
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+__attribute__((weak)) void SystemInit(void)
+{
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */
+#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+ SCB->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
+
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ SCB_NS->CPACR |=
+ ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Non-secure mode (enable PowerQuad) */
+#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+ SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */
+
+ SYSCTL0->DSPSTALL = SYSCTL0_DSPSTALL_DSPSTALL_MASK;
+
+ PMC->CTRL |= PMC_CTRL_CLKDIVEN_MASK; /* enable the internal clock divider for power saving */
+
+ if (SYSTEM_IS_XIP_FLEXSPI() && (CACHE64_POLSEL0->POLSEL == 0U)) /* set CAHCHE64 if not configured */
+ {
+ /* set command to invalidate all ways and write GO bit to initiate command */
+ CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK;
+ CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK;
+ /* Wait until the command completes */
+ while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U)
+ {
+ }
+ /* Enable cache, enable write buffer */
+ CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK);
+
+ /* Set whole FlexSPI0 space to write through. */
+ CACHE64_POLSEL0->REG0_TOP = 0x07FFFC00U;
+ CACHE64_POLSEL0->REG1_TOP = 0x0U;
+ CACHE64_POLSEL0->POLSEL = 0x1U;
+
+ __ISB();
+ __DSB();
+ }
+
+ SystemInitHook();
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate(void)
+{
+ /* iMXRT5xx systemCoreClockUpdate */
+ uint32_t freq = 0U;
+ uint64_t freqTmp = 0U;
+
+ switch ((CLKCTL0->MAINCLKSELB) & CLKCTL0_MAINCLKSELB_SEL_MASK)
+ {
+ case CLKCTL0_MAINCLKSELB_SEL(0): /* MAINCLKSELA clock */
+ switch ((CLKCTL0->MAINCLKSELA) & CLKCTL0_MAINCLKSELA_SEL_MASK)
+ {
+ case CLKCTL0_MAINCLKSELA_SEL(0): /* Low Power Oscillator Clock (1m_lposc) */
+ freq = CLK_LPOSC_1MHZ;
+ break;
+ case CLKCTL0_MAINCLKSELA_SEL(1): /* FRO DIV clock */
+ freq = getFroDivClk();
+ break;
+ case CLKCTL0_MAINCLKSELA_SEL(2): /* OSC clock */
+ freq = getOscClk();
+ break;
+ case CLKCTL0_MAINCLKSELA_SEL(3): /* FRO clock */
+ freq = CLK_FRO_CLK;
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+ break;
+
+ case CLKCTL0_MAINCLKSELB_SEL(1): /* Main System PLL clock */
+ switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK)
+ {
+ case CLKCTL0_SYSPLL0CLKSEL_SEL(0): /* FRO_DIV8 clock */
+ freq = CLK_FRO_DIV8_CLK;
+ break;
+ case CLKCTL0_SYSPLL0CLKSEL_SEL(1): /* OSC clock */
+ freq = getOscClk();
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+
+ if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U)
+ {
+ /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
+ freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM));
+ freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT;
+ freq += (uint32_t)freqTmp;
+ freq =
+ (uint32_t)((uint64_t)freq * 18U /
+ ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT));
+ }
+
+ freq = freq / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U);
+ break;
+
+ case CLKCTL0_MAINCLKSELB_SEL(2): /* RTC 32KHz clock */
+ freq = CLK_RTC_32K_CLK;
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ SystemCoreClock = freq / ((CLKCTL0->SYSCPUAHBCLKDIV & CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK) + 1U);
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemInitHook()
+ ---------------------------------------------------------------------------- */
+
+__attribute__((weak)) void SystemInitHook(void)
+{
+ /* Void implementation of the weak function. */
+}
diff --git a/minimal-examples/embedded/rt595/hello_world/project/device/system_MIMXRT595S_cm33.h b/minimal-examples/embedded/rt595/hello_world/project/device/system_MIMXRT595S_cm33.h
new file mode 100644
index 000000000..7e6138767
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/device/system_MIMXRT595S_cm33.h
@@ -0,0 +1,124 @@
+/*
+** ###################################################################
+** Processors: MIMXRT595SFAWC_cm33
+** MIMXRT595SFFOC_cm33
+**
+** Compilers: GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** Keil ARM C/C++ Compiler
+** MCUXpresso Compiler
+**
+** Reference manual: RT500 Reference Manual. Rev.C, 8/2020
+** Version: rev. 5.0, 2020-08-27
+** Build: b201016
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2019-04-19)
+** Initial version.
+** - rev. 2.0 (2019-07-22)
+** Base on rev 0.7 RM.
+** - rev. 3.0 (2020-03-16)
+** Base on Rev.A RM.
+** - rev. 4.0 (2020-05-18)
+** Base on Rev.B RM.
+** - rev. 5.0 (2020-08-27)
+** Base on Rev.C RM.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MIMXRT595S_cm33
+ * @version 5.0
+ * @date 2020-08-27
+ * @brief Device specific configuration file for MIMXRT595S_cm33 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_MIMXRT595S_cm33_H_
+#define _SYSTEM_MIMXRT595S_cm33_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define DEFAULT_SYSTEM_CLOCK 1000000u /* Default System clock value */
+#ifndef CLK_XTAL_OSC_CLK
+#define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock */
+#endif
+#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz (32k_clk) */
+#define CLK_LPOSC_1MHZ 1000000u /* Low power oscillator 1 MHz (1m_lposc) */
+#define CLK_FRO_CLK ((CLKCTL0->FRO_SCTRIM & 0x3FU) == 0x2FU ? 96000000u : 192000000u) /* FRO clock frequency */
+#define CLK_FRO_DIV2_CLK (CLK_FRO_CLK / 2u) /* FRO_DIV2 clock frequency */
+#define CLK_FRO_DIV4_CLK (CLK_FRO_CLK / 4u) /* FRO_DIV4 clock frequency */
+#define CLK_FRO_DIV8_CLK (CLK_FRO_CLK / 8u) /* FRO_DIV8 clock frequency */
+#define CLK_FRO_DIV16_CLK (CLK_FRO_CLK / 16u) /* FRO_DIV16 clock frequency */
+#ifndef CLK_EXT_CLKIN
+#define CLK_EXT_CLKIN 0u /* Default external CLKIN pin clock */
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate(void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_MIMXRT595S_cm33_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_cache.c b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_cache.c
new file mode 100644
index 000000000..6fbd07f75
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_cache.c
@@ -0,0 +1,372 @@
+/*
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_cache.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.cache_cache64"
+#endif
+
+#if (FSL_FEATURE_SOC_CACHE64_CTRL_COUNT > 0)
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Array of CACHE64_CTRL peripheral base address. */
+static CACHE64_CTRL_Type *const s_cache64ctrlBases[] = CACHE64_CTRL_BASE_PTRS;
+/* Array of CACHE64_POLSEL peripheral base address. */
+static CACHE64_POLSEL_Type *const s_cache64polselBases[] = CACHE64_POLSEL_BASE_PTRS;
+
+/* Array of CACHE64 physical memory base address. */
+static uint32_t const s_cache64PhymemBases[] = CACHE64_CTRL_PHYMEM_BASES;
+/* Array of CACHE64 physical memory size. */
+static uint32_t const s_cache64PhymemSizes[] = CACHE64_CTRL_PHYMEM_SIZES;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of CACHE64_CTRL clock name. */
+static const clock_ip_name_t s_cache64Clocks[] = CACHE64_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief Returns an instance number given periphearl base address.
+ *
+ * param base The peripheral base address.
+ * return CACHE64_POLSEL instance number starting from 0.
+ */
+uint32_t CACHE64_GetInstance(CACHE64_POLSEL_Type *base)
+{
+ uint32_t i;
+
+ for (i = 0; i < ARRAY_SIZE(s_cache64polselBases); i++)
+ {
+ if (base == s_cache64polselBases[i])
+ {
+ break;
+ }
+ }
+
+ assert(i < ARRAY_SIZE(s_cache64polselBases));
+
+ return i;
+}
+/*!
+ * brief Returns an instance number given physical memory address.
+ *
+ * param address The physical memory address.
+ * return CACHE64_CTRL instance number starting from 0.
+ */
+uint32_t CACHE64_GetInstanceByAddr(uint32_t address)
+{
+ uint32_t i;
+
+ for (i = 0; i < ARRAY_SIZE(s_cache64ctrlBases); i++)
+ {
+ if ((address >= s_cache64PhymemBases[i]) && (address < s_cache64PhymemBases[i] + s_cache64PhymemSizes[i]))
+ {
+ break;
+ }
+ }
+
+ return i;
+}
+
+/*!
+ * @brief Initializes an CACHE64 instance with the user configuration structure.
+ *
+ * This function configures the CACHE64 module with user-defined settings. Call the CACHE64_GetDefaultConfig() function
+ * to configure the configuration structure and get the default configuration.
+ *
+ * @param base CACHE64_POLSEL peripheral base address.
+ * @param config Pointer to a user-defined configuration structure.
+ * @retval kStatus_Success CACHE64 initialize succeed
+ */
+status_t CACHE64_Init(CACHE64_POLSEL_Type *base, const cache64_config_t *config)
+{
+ volatile uint32_t *topReg = &base->REG0_TOP;
+ uint32_t i;
+ uint32_t polsel = 0;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ uint32_t instance = CACHE64_GetInstance(base);
+
+ /* Enable CACHE64 clock */
+ CLOCK_EnableClock(s_cache64Clocks[instance]);
+#endif
+
+ for (i = 0; i < CACHE64_REGION_NUM - 1U; i++)
+ {
+ assert((config->boundaryAddr[i] & (CACHE64_REGION_ALIGNMENT - 1U)) == 0U);
+ ((volatile uint32_t *)topReg)[i] = config->boundaryAddr[i] >= CACHE64_REGION_ALIGNMENT ?
+ config->boundaryAddr[i] - CACHE64_REGION_ALIGNMENT :
+ 0U;
+ }
+
+ for (i = 0; i < CACHE64_REGION_NUM; i++)
+ {
+ polsel |= (((uint32_t)config->policy[i]) << (2U * i));
+ }
+ base->POLSEL = polsel;
+
+ return kStatus_Success;
+}
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the CACHE64 configuration structure to a default value. The default
+ * values are first region covers whole cacheable area, and policy set to write back.
+ *
+ * @param config Pointer to a configuration structure.
+ */
+void CACHE64_GetDefaultConfig(cache64_config_t *config)
+{
+ (void)memset(config, 0, sizeof(cache64_config_t));
+
+ config->boundaryAddr[0] = s_cache64PhymemSizes[0];
+ config->policy[0] = kCACHE64_PolicyWriteBack;
+}
+
+/*!
+ * brief Enables the cache.
+ *
+ */
+void CACHE64_EnableCache(CACHE64_CTRL_Type *base)
+{
+ /* First, invalidate the entire cache. */
+ CACHE64_InvalidateCache(base);
+
+ /* Now enable the cache. */
+ base->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK;
+}
+
+/*!
+ * brief Disables the cache.
+ *
+ */
+void CACHE64_DisableCache(CACHE64_CTRL_Type *base)
+{
+ /* First, push any modified contents. */
+ CACHE64_CleanCache(base);
+
+ /* Now disable the cache. */
+ base->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK;
+}
+
+/*!
+ * brief Invalidates the cache.
+ *
+ */
+void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base)
+{
+ /* Invalidate all lines in both ways and initiate the cache command. */
+ base->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK;
+
+ /* Wait until the cache command completes. */
+ while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U)
+ {
+ }
+
+ /* As a precaution clear the bits to avoid inadvertently re-running this command. */
+ base->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK);
+}
+
+/*!
+ * brief Invalidates cache by range.
+ *
+ * param address The physical address of cache.
+ * param size_byte size of the memory to be invalidated.
+ * note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE".
+ * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte)
+{
+ uint32_t endAddr = address + size_byte;
+ uint32_t pccReg = 0;
+ /* Align address to cache line size. */
+ uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
+ uint32_t instance = CACHE64_GetInstanceByAddr(address);
+ uint32_t endLim;
+ CACHE64_CTRL_Type *base;
+
+ if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
+ {
+ return;
+ }
+ base = s_cache64ctrlBases[instance];
+ endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance];
+ endAddr = endAddr > endLim ? endLim : endAddr;
+
+ /* Set the invalidate by line command and use the physical address. */
+ pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(1) | CACHE64_CTRL_CLCR_LADSEL_MASK;
+ base->CLCR = pccReg;
+
+ while (startAddr < endAddr)
+ {
+ /* Set the address and initiate the command. */
+ base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
+
+ /* Wait until the cache command completes. */
+ while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
+ {
+ }
+ startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
+ }
+}
+
+/*!
+ * brief Cleans the cache.
+ *
+ */
+void CACHE64_CleanCache(CACHE64_CTRL_Type *base)
+{
+ /* Enable the to push all modified lines. */
+ base->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MASK;
+
+ /* Wait until the cache command completes. */
+ while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U)
+ {
+ }
+
+ /* As a precaution clear the bits to avoid inadvertently re-running this command. */
+ base->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK);
+}
+
+/*!
+ * brief Cleans cache by range.
+ *
+ * param address The physical address of cache.
+ * param size_byte size of the memory to be cleaned.
+ * note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
+ * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte)
+{
+ uint32_t endAddr = address + size_byte;
+ uint32_t pccReg = 0;
+ /* Align address to cache line size. */
+ uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
+ uint32_t instance = CACHE64_GetInstanceByAddr(address);
+ uint32_t endLim;
+ CACHE64_CTRL_Type *base;
+
+ if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
+ {
+ return;
+ }
+ base = s_cache64ctrlBases[instance];
+ endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance];
+ endAddr = endAddr > endLim ? endLim : endAddr;
+
+ /* Set the push by line command. */
+ pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(2) | CACHE64_CTRL_CLCR_LADSEL_MASK;
+ base->CLCR = pccReg;
+
+ while (startAddr < endAddr)
+ {
+ /* Set the address and initiate the command. */
+ base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
+
+ /* Wait until the cache command completes. */
+ while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
+ {
+ }
+ startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
+ }
+}
+
+/*!
+ * brief Cleans and invalidates the cache.
+ *
+ */
+void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base)
+{
+ /* Push and invalidate all. */
+ base->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK |
+ CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK;
+
+ /* Wait until the cache command completes. */
+ while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U)
+ {
+ }
+
+ /* As a precaution clear the bits to avoid inadvertently re-running this command. */
+ base->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK |
+ CACHE64_CTRL_CCR_INVW1_MASK);
+}
+
+/*!
+ * brief Cleans and invalidate cache by range.
+ *
+ * param address The physical address of cache.
+ * param size_byte size of the memory to be Cleaned and Invalidated.
+ * note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
+ * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte)
+{
+ uint32_t endAddr = address + size_byte;
+ uint32_t pccReg = 0;
+ /* Align address to cache line size. */
+ uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
+ uint32_t instance = CACHE64_GetInstanceByAddr(address);
+ uint32_t endLim;
+ CACHE64_CTRL_Type *base;
+
+ if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
+ {
+ return;
+ }
+ base = s_cache64ctrlBases[instance];
+ endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance];
+ endAddr = endAddr > endLim ? endLim : endAddr;
+
+ /* Set the push by line command. */
+ pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(3) | CACHE64_CTRL_CLCR_LADSEL_MASK;
+ base->CLCR = pccReg;
+
+ while (startAddr < endAddr)
+ {
+ /* Set the address and initiate the command. */
+ base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
+
+ /* Wait until the cache command completes. */
+ while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
+ {
+ }
+ startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
+ }
+}
+
+/*!
+ * brief Enable the cache write buffer.
+ *
+ */
+void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->CCR |= CACHE64_CTRL_CCR_ENWRBUF_MASK;
+ }
+ else
+ {
+ base->CCR &= ~CACHE64_CTRL_CCR_ENWRBUF_MASK;
+ }
+}
+
+#endif /* FSL_FEATURE_SOC_CACHE64_CTRL_COUNT > 0 */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_cache.h b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_cache.h
new file mode 100644
index 000000000..3e708ae45
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_cache.h
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CACHE_H_
+#define _FSL_CACHE_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup cache64
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief cache driver version 2.0.4. */
+#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
+/*@}*/
+
+/*! @brief cache line size. */
+#define CACHE64_LINESIZE_BYTE (FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE)
+/*! @brief cache region number. */
+#define CACHE64_REGION_NUM (3U)
+/*! @brief cache region alignment. */
+#define CACHE64_REGION_ALIGNMENT (0x400U)
+
+/*! @brief Level 2 cache controller way size. */
+typedef enum _cache64_policy
+{
+ kCACHE64_PolicyNonCacheable = 0, /*!< Non-cacheable */
+ kCACHE64_PolicyWriteThrough = 1, /*!< Write through */
+ kCACHE64_PolicyWriteBack = 2, /*!< Write back */
+} cache64_policy_t;
+
+/*! @brief CACHE64 configuration structure. */
+typedef struct _cache64_config
+{
+ /*!< The cache controller can divide whole memory into 3 regions.
+ * Boundary address is the FlexSPI internal address (start from 0) instead of system
+ * address (start from FlexSPI AMBA base) to split adjacent regions and must be 1KB
+ * aligned. The boundary address itself locates in upper region. */
+ uint32_t boundaryAddr[CACHE64_REGION_NUM - 1];
+ /*!< Cacheable policy for each region. */
+ cache64_policy_t policy[CACHE64_REGION_NUM];
+} cache64_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name cache control for cache64
+ *@{
+ */
+
+/*!
+ * @brief Returns an instance number given periphearl base address.
+ *
+ * @param base The peripheral base address.
+ * @return CACHE64_POLSEL instance number starting from 0.
+ */
+uint32_t CACHE64_GetInstance(CACHE64_POLSEL_Type *base);
+
+/*!
+ * brief Returns an instance number given physical memory address.
+ *
+ * param address The physical memory address.
+ * @return CACHE64_CTRL instance number starting from 0.
+ */
+uint32_t CACHE64_GetInstanceByAddr(uint32_t address);
+
+/*!
+ * @brief Initializes an CACHE64 instance with the user configuration structure.
+ *
+ * This function configures the CACHE64 module with user-defined settings. Call the CACHE64_GetDefaultConfig() function
+ * to configure the configuration structure and get the default configuration.
+ *
+ * @param base CACHE64_POLSEL peripheral base address.
+ * @param config Pointer to a user-defined configuration structure.
+ * @retval kStatus_Success CACHE64 initialize succeed
+ */
+status_t CACHE64_Init(CACHE64_POLSEL_Type *base, const cache64_config_t *config);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the CACHE64 configuration structure to a default value. The default
+ * values are first region covers whole cacheable area, and policy set to write back.
+ *
+ * @param config Pointer to a configuration structure.
+ */
+void CACHE64_GetDefaultConfig(cache64_config_t *config);
+
+/*!
+ * @brief Enables the cache.
+ *
+ * @param base CACHE64_CTRL peripheral base address.
+ *
+ */
+void CACHE64_EnableCache(CACHE64_CTRL_Type *base);
+
+/*!
+ * @brief Disables the cache.
+ *
+ * @param base CACHE64_CTRL peripheral base address.
+ *
+ */
+void CACHE64_DisableCache(CACHE64_CTRL_Type *base);
+
+/*!
+ * @brief Invalidates the cache.
+ *
+ * @param base CACHE64_CTRL peripheral base address.
+ *
+ */
+void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base);
+
+/*!
+ * @brief Invalidates cache by range.
+ *
+ * @param address The physical address of cache.
+ * @param size_byte size of the memory to be invalidated.
+ * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
+ * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte);
+
+/*!
+ * @brief Cleans the cache.
+ *
+ * @param base CACHE64_CTRL peripheral base address.
+ *
+ */
+void CACHE64_CleanCache(CACHE64_CTRL_Type *base);
+
+/*!
+ * @brief Cleans cache by range.
+ *
+ * @param address The physical address of cache.
+ * @param size_byte size of the memory to be cleaned.
+ * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
+ * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte);
+
+/*!
+ * @brief Cleans and invalidates the cache.
+ *
+ * @param base CACHE64_CTRL peripheral base address.
+ *
+ */
+void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base);
+
+/*!
+ * @brief Cleans and invalidate cache by range.
+ *
+ * @param address The physical address of cache.
+ * @param size_byte size of the memory to be Cleaned and Invalidated.
+ * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
+ * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte);
+
+/*!
+ * @brief Enables/disables the write buffer.
+ *
+ * @param base CACHE64_CTRL peripheral base address.
+ * @param enable The enable or disable flag.
+ * true - enable the write buffer.
+ * false - disable the write buffer.
+ */
+void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable);
+
+/*@}*/
+
+/*!
+ * @name Unified Cache Control for all caches
+ *@{
+ */
+
+/*!
+ * @brief Invalidates instruction cache by range.
+ *
+ * @param address The physical address.
+ * @param size_byte size of the memory to be invalidated.
+ * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
+ * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
+ * size if startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+ CACHE64_InvalidateCacheByRange(address, size_byte);
+}
+
+/*!
+ * @brief Invalidates data cache by range.
+ *
+ * @param address The physical address.
+ * @param size_byte size of the memory to be invalidated.
+ * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
+ * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
+ * size if startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+ CACHE64_InvalidateCacheByRange(address, size_byte);
+}
+
+/*!
+ * @brief Clean data cache by range.
+ *
+ * @param address The physical address.
+ * @param size_byte size of the memory to be cleaned.
+ * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
+ * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
+ * size if startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
+{
+ CACHE64_CleanCacheByRange(address, size_byte);
+}
+
+/*!
+ * @brief Cleans and Invalidates data cache by range.
+ *
+ * @param address The physical address.
+ * @param size_byte size of the memory to be Cleaned and Invalidated.
+ * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
+ * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
+ * size if startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+ CACHE64_CleanInvalidateCacheByRange(address, size_byte);
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_CACHE_H_*/
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_clock.c b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_clock.c
new file mode 100644
index 000000000..572be4707
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_clock.c
@@ -0,0 +1,1845 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_clock.h"
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.clock"
+#endif
+
+#define OTP_INIT_API ((void (*)(uint32_t src_clk_freq))0x13007FFF)
+#define OTP_DEINIT_API ((void (*)(void))0x1300804D)
+#define OTP_FUSE_READ_API ((void (*)(uint32_t addr, uint32_t * data))0x1300805D)
+/* OTP fuse index. */
+#define FRO_192MHZ_SC_TRIM 0x2C
+#define FRO_192MHZ_RD_TRIM 0x2B
+#define FRO_96MHZ_SC_TRIM 0x2E
+#define FRO_96MHZ_RD_TRIM 0x2D
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* External XTAL (OSC) clock frequency. */
+volatile uint32_t g_xtalFreq = 0U;
+/* External CLK_IN pin clock frequency. */
+volatile uint32_t g_clkinFreq = 0U;
+/* External MCLK IN clock frequency. */
+volatile uint32_t g_mclkFreq = 0U;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Clock Selection for IP */
+/**
+ * brief Configure the clock selection muxes.
+ * param connection : Clock to be configured.
+ * return Nothing
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection)
+{
+ bool final_descriptor = false;
+ uint32_t i;
+ uint32_t tuple;
+ volatile uint32_t *pClkSel;
+
+ for (i = 0U; (i < 2U) && (!final_descriptor); i++)
+ {
+ tuple = ((uint32_t)connection) >> (i * 14U); /*!< pick up next descriptor */
+ if ((((uint32_t)connection) & 0x80000000U) != 0UL)
+ {
+ pClkSel = CLKCTL_TUPLE_REG(CLKCTL1, tuple);
+ }
+ else
+ {
+ pClkSel = CLKCTL_TUPLE_REG(CLKCTL0, tuple);
+ }
+ if ((tuple & 0x7FFU) != 0U)
+ {
+ *pClkSel = CLKCTL_TUPLE_SEL(tuple);
+ }
+ else
+ {
+ final_descriptor = true;
+ }
+ }
+
+ if ((((uint32_t)connection) & 0x40000000U) != 0U)
+ {
+ CLKCTL0->FRODIVSEL = (((uint32_t)connection) >> 28U) & 0x3U;
+ }
+}
+
+/* Set IP Clock divider */
+/**
+ * brief Setup peripheral clock dividers.
+ * param div_name : Clock divider name
+ * param divider : Value to be divided. Divided clock frequency = Undivided clock frequency / divider.
+ * return Nothing
+ */
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divider)
+{
+ volatile uint32_t *pClkDiv;
+
+ if ((((uint32_t)div_name) & 0x80000000U) != 0U)
+ {
+ pClkDiv = CLKCTL_TUPLE_REG(CLKCTL1, div_name);
+ }
+ else
+ {
+ pClkDiv = CLKCTL_TUPLE_REG(CLKCTL0, div_name);
+ }
+ /* Reset the divider counter */
+ *pClkDiv |= 1UL << 29U;
+
+ if (divider == 0U) /*!< halt */
+ {
+ *pClkDiv |= 1UL << 30U;
+ }
+ else
+ {
+ *pClkDiv = divider - 1U;
+
+ while (((*pClkDiv) & 0x80000000U) != 0U)
+ {
+ }
+ }
+}
+
+/* Get SYSTEM PLL Clk */
+/*! brief Return Frequency of SYSPLL
+ * return Frequency of SYSPLL
+ */
+uint32_t CLOCK_GetSysPllFreq(void)
+{
+ uint32_t freq = 0U;
+ uint64_t freqTmp;
+
+ switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK)
+ {
+ case CLKCTL0_SYSPLL0CLKSEL_SEL(0):
+ freq = CLK_FRO_DIV8_CLK;
+ break;
+ case CLKCTL0_SYSPLL0CLKSEL_SEL(1):
+ freq = CLOCK_GetXtalInClkFreq();
+ break;
+ default:
+ assert(false);
+ break;
+ }
+
+ if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U)
+ {
+ /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
+ freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM));
+ freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT;
+ freq += (uint32_t)freqTmp;
+ }
+
+ return freq;
+}
+
+/* Get SYSTEM PLL PFDn Clk */
+/*! brief Get current output frequency of specific System PLL PFD.
+ * param pfd : pfd name to get frequency.
+ * return Frequency of SYSPLL PFD.
+ */
+uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd)
+{
+ uint32_t freq = CLOCK_GetSysPllFreq();
+
+ if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U)
+ {
+ switch (pfd)
+ {
+ case kCLOCK_Pfd0:
+ freq =
+ (uint32_t)((uint64_t)freq * 18U /
+ ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT));
+ break;
+
+ case kCLOCK_Pfd1:
+ freq =
+ (uint32_t)((uint64_t)freq * 18U /
+ ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD1_MASK) >> CLKCTL0_SYSPLL0PFD_PFD1_SHIFT));
+ break;
+
+ case kCLOCK_Pfd2:
+ freq =
+ (uint32_t)((uint64_t)freq * 18U /
+ ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD2_MASK) >> CLKCTL0_SYSPLL0PFD_PFD2_SHIFT));
+ break;
+
+ case kCLOCK_Pfd3:
+ freq =
+ (uint32_t)((uint64_t)freq * 18U /
+ ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD3_MASK) >> CLKCTL0_SYSPLL0PFD_PFD3_SHIFT));
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+ }
+
+ return freq;
+}
+
+static uint32_t CLOCK_GetMainPllClkFreq(void)
+{
+ return CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U);
+}
+static uint32_t CLOCK_GetDspPllClkFreq(void)
+{
+ return CLOCK_GetSysPfdFreq(kCLOCK_Pfd1) / ((CLKCTL0->DSPPLLCLKDIV & CLKCTL0_DSPPLLCLKDIV_DIV_MASK) + 1U);
+}
+static uint32_t CLOCK_GetAux0PllClkFreq(void)
+{
+ return CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / ((CLKCTL0->AUX0PLLCLKDIV & CLKCTL0_AUX0PLLCLKDIV_DIV_MASK) + 1U);
+}
+static uint32_t CLOCK_GetAux1PllClkFreq(void)
+{
+ return CLOCK_GetSysPfdFreq(kCLOCK_Pfd3) / ((CLKCTL0->AUX1PLLCLKDIV & CLKCTL0_AUX1PLLCLKDIV_DIV_MASK) + 1U);
+}
+
+/* Get AUDIO PLL Clk */
+/*! brief Return Frequency of AUDIO PLL
+ * return Frequency of AUDIO PLL
+ */
+uint32_t CLOCK_GetAudioPllFreq(void)
+{
+ uint32_t freq = 0U;
+ uint64_t freqTmp;
+
+ switch ((CLKCTL1->AUDIOPLL0CLKSEL) & CLKCTL1_AUDIOPLL0CLKSEL_SEL_MASK)
+ {
+ case CLKCTL1_AUDIOPLL0CLKSEL_SEL(0):
+ freq = CLK_FRO_DIV8_CLK;
+ break;
+ case CLKCTL1_AUDIOPLL0CLKSEL_SEL(1):
+ freq = CLOCK_GetXtalInClkFreq();
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+
+ if (((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK) == 0U)
+ {
+ /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
+ freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL1->AUDIOPLL0NUM))) / ((uint64_t)(CLKCTL1->AUDIOPLL0DENOM));
+ freq *= ((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) >> CLKCTL1_AUDIOPLL0CTL0_MULT_SHIFT;
+ freq += (uint32_t)freqTmp;
+ }
+
+ return freq;
+}
+
+/* Get AUDIO PLL PFDn Clk */
+/*! brief Get current output frequency of specific Audio PLL PFD.
+ * param pfd : pfd name to get frequency.
+ * return Frequency of AUDIO PLL PFD.
+ */
+uint32_t CLOCK_GetAudioPfdFreq(clock_pfd_t pfd)
+{
+ uint32_t freq = CLOCK_GetAudioPllFreq();
+
+ if (((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK) == 0U)
+ {
+ switch (pfd)
+ {
+ case kCLOCK_Pfd0:
+ freq = (uint32_t)(
+ (uint64_t)freq * 18U /
+ ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD0_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD0_SHIFT));
+ break;
+
+ case kCLOCK_Pfd1:
+ freq = (uint32_t)(
+ (uint64_t)freq * 18U /
+ ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD1_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD1_SHIFT));
+ break;
+
+ case kCLOCK_Pfd2:
+ freq = (uint32_t)(
+ (uint64_t)freq * 18U /
+ ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD2_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD2_SHIFT));
+ break;
+
+ case kCLOCK_Pfd3:
+ freq = (uint32_t)(
+ (uint64_t)freq * 18U /
+ ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD3_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD3_SHIFT));
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+ }
+
+ return freq;
+}
+
+static uint32_t CLOCK_GetAudioPllClkFreq(void)
+{
+ return CLOCK_GetAudioPfdFreq(kCLOCK_Pfd0) / ((CLKCTL1->AUDIOPLLCLKDIV & CLKCTL1_AUDIOPLLCLKDIV_DIV_MASK) + 1U);
+}
+
+static uint32_t CLOCK_GetFroDivFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch ((CLKCTL0->FRODIVSEL) & CLKCTL0_FRODIVSEL_SEL_MASK)
+ {
+ case CLKCTL0_FRODIVSEL_SEL(0):
+ freq = CLK_FRO_DIV2_CLK;
+ break;
+ case CLKCTL0_FRODIVSEL_SEL(1):
+ freq = CLK_FRO_DIV4_CLK;
+ break;
+ case CLKCTL0_FRODIVSEL_SEL(2):
+ freq = CLK_FRO_DIV8_CLK;
+ break;
+ case CLKCTL0_FRODIVSEL_SEL(3):
+ freq = CLK_FRO_DIV16_CLK;
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+/* Get MAIN Clk */
+/*! brief Return Frequency of main clk
+ * return Frequency of main clk
+ */
+uint32_t CLOCK_GetMainClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch ((CLKCTL0->MAINCLKSELB) & CLKCTL0_MAINCLKSELB_SEL_MASK)
+ {
+ case CLKCTL0_MAINCLKSELB_SEL(0):
+ switch ((CLKCTL0->MAINCLKSELA) & CLKCTL0_MAINCLKSELA_SEL_MASK)
+ {
+ case CLKCTL0_MAINCLKSELA_SEL(0):
+ freq = CLOCK_GetLpOscFreq();
+ break;
+ case CLKCTL0_MAINCLKSELA_SEL(1):
+ freq = CLOCK_GetFroDivFreq();
+ break;
+ case CLKCTL0_MAINCLKSELA_SEL(2):
+ freq = CLOCK_GetXtalInClkFreq();
+ break;
+ case CLKCTL0_MAINCLKSELA_SEL(3):
+ freq = CLK_FRO_CLK;
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+ break;
+
+ case CLKCTL0_MAINCLKSELB_SEL(1):
+ freq = CLOCK_GetMainPllClkFreq();
+ break;
+
+ case CLKCTL0_MAINCLKSELB_SEL(2):
+ freq = CLOCK_GetOsc32KFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+/* Get DSP MAIN Clk */
+/*! brief Return Frequency of DSP main clk
+ * return Frequency of DSP main clk
+ */
+uint32_t CLOCK_GetDspMainClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch ((CLKCTL1->DSPCPUCLKSELB) & CLKCTL1_DSPCPUCLKSELB_SEL_MASK)
+ {
+ case CLKCTL1_DSPCPUCLKSELB_SEL(0):
+ switch ((CLKCTL1->DSPCPUCLKSELA) & CLKCTL1_DSPCPUCLKSELA_SEL_MASK)
+ {
+ case CLKCTL1_DSPCPUCLKSELA_SEL(0):
+ freq = CLK_FRO_CLK;
+ break;
+ case CLKCTL1_DSPCPUCLKSELA_SEL(1):
+ freq = CLOCK_GetXtalInClkFreq();
+ break;
+ case CLKCTL1_DSPCPUCLKSELA_SEL(2):
+ freq = CLOCK_GetLpOscFreq();
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+ break;
+
+ case CLKCTL1_DSPCPUCLKSELB_SEL(1):
+ freq = CLOCK_GetMainPllClkFreq();
+ break;
+
+ case CLKCTL1_DSPCPUCLKSELB_SEL(2):
+ freq = CLOCK_GetDspPllClkFreq();
+ break;
+
+ case CLKCTL1_DSPCPUCLKSELB_SEL(3):
+ freq = CLOCK_GetOsc32KFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+/* Get ADC Clk */
+/*! brief Return Frequency of Adc Clock
+ * return Frequency of Adc Clock.
+ */
+uint32_t CLOCK_GetAdcClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch ((CLKCTL0->ADC0FCLKSEL1) & CLKCTL0_ADC0FCLKSEL1_SEL_MASK)
+ {
+ case CLKCTL0_ADC0FCLKSEL1_SEL(0):
+ switch ((CLKCTL0->ADC0FCLKSEL0) & CLKCTL0_ADC0FCLKSEL0_SEL_MASK)
+ {
+ case CLKCTL0_ADC0FCLKSEL0_SEL(0):
+ freq = CLOCK_GetXtalInClkFreq();
+ break;
+ case CLKCTL0_ADC0FCLKSEL0_SEL(1):
+ freq = CLOCK_GetLpOscFreq();
+ break;
+ case CLKCTL0_ADC0FCLKSEL0_SEL(2):
+ freq = CLK_FRO_DIV4_CLK;
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+ break;
+
+ case CLKCTL0_ADC0FCLKSEL1_SEL(1):
+ freq = CLOCK_GetMainPllClkFreq();
+ break;
+
+ case CLKCTL0_ADC0FCLKSEL1_SEL(2):
+ freq = CLOCK_GetAux0PllClkFreq();
+ break;
+
+ case CLKCTL0_ADC0FCLKSEL1_SEL(3):
+ freq = CLOCK_GetAux1PllClkFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((CLKCTL0->ADC0FCLKDIV & CLKCTL0_ADC0FCLKDIV_DIV_MASK) + 1U);
+}
+
+/* Get CLOCK OUT Clk */
+/*! brief Return Frequency of ClockOut
+ * return Frequency of ClockOut
+ */
+uint32_t CLOCK_GetClockOutClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch ((CLKCTL1->CLKOUTSEL1) & CLKCTL1_CLKOUTSEL1_SEL_MASK)
+ {
+ case CLKCTL1_CLKOUTSEL1_SEL(0):
+ switch ((CLKCTL1->CLKOUTSEL0) & CLKCTL1_CLKOUTSEL0_SEL_MASK)
+ {
+ case CLKCTL1_CLKOUTSEL0_SEL(0):
+ freq = CLOCK_GetXtalInClkFreq();
+ break;
+ case CLKCTL1_CLKOUTSEL0_SEL(1):
+ freq = CLOCK_GetLpOscFreq();
+ break;
+ case CLKCTL1_CLKOUTSEL0_SEL(2):
+ freq = CLK_FRO_DIV2_CLK;
+ break;
+ case CLKCTL1_CLKOUTSEL0_SEL(3):
+ freq = CLOCK_GetMainClkFreq();
+ break;
+ case CLKCTL1_CLKOUTSEL0_SEL(4):
+ freq = CLOCK_GetDspMainClkFreq();
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+ break;
+
+ case CLKCTL1_CLKOUTSEL1_SEL(1):
+ freq = CLOCK_GetMainPllClkFreq();
+ break;
+
+ case CLKCTL1_CLKOUTSEL1_SEL(2):
+ freq = CLOCK_GetAux0PllClkFreq();
+ break;
+
+ case CLKCTL1_CLKOUTSEL1_SEL(3):
+ freq = CLOCK_GetDspPllClkFreq();
+ break;
+
+ case CLKCTL1_CLKOUTSEL1_SEL(4):
+ freq = CLOCK_GetAux1PllClkFreq();
+ break;
+
+ case CLKCTL1_CLKOUTSEL1_SEL(5):
+ freq = CLOCK_GetAudioPllClkFreq();
+ break;
+
+ case CLKCTL1_CLKOUTSEL1_SEL(6):
+ freq = CLOCK_GetOsc32KFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((CLKCTL1->CLKOUTFCLKDIV & CLKCTL1_CLKOUTFCLKDIV_DIV_MASK) + 1U);
+}
+
+/* Get FRG Clk */
+/*! brief Return Input frequency for the Fractional baud rate generator
+ * return Input Frequency for FRG
+ */
+uint32_t CLOCK_GetFRGClock(uint32_t id)
+{
+ uint32_t freq = 0U;
+ uint32_t frgPllDiv = 1U;
+ uint32_t clkSel = 0U;
+ uint32_t frgDiv = 0U;
+ uint32_t frgMul = 0U;
+
+ assert(id <= 17U);
+
+ if (id == 17U)
+ {
+ clkSel = CLKCTL1->FRG17CLKSEL & CLKCTL1_FRG17CLKSEL_SEL_MASK;
+ frgMul = (CLKCTL1->FRG17CTL & CLKCTL1_FRG17CTL_MULT_MASK) >> CLKCTL1_FRG17CTL_MULT_SHIFT;
+ frgDiv = (CLKCTL1->FRG17CTL & CLKCTL1_FRG17CTL_DIV_MASK) >> CLKCTL1_FRG17CTL_DIV_SHIFT;
+ }
+ else
+ {
+ clkSel = CLKCTL1->FLEXCOMM[id].FRGCLKSEL & CLKCTL1_FRGCLKSEL_SEL_MASK;
+ frgMul = (CLKCTL1->FLEXCOMM[id].FRGCTL & CLKCTL1_FRGCTL_MULT_MASK) >> CLKCTL1_FRGCTL_MULT_SHIFT;
+ frgDiv = (CLKCTL1->FLEXCOMM[id].FRGCTL & CLKCTL1_FRGCTL_DIV_MASK) >> CLKCTL1_FRGCTL_DIV_SHIFT;
+ }
+
+ switch (clkSel)
+ {
+ case CLKCTL1_FRGCLKSEL_SEL(0):
+ freq = CLOCK_GetMainClkFreq();
+ break;
+
+ case CLKCTL1_FRGCLKSEL_SEL(1):
+ frgPllDiv = (CLKCTL1->FRGPLLCLKDIV & CLKCTL1_FRGPLLCLKDIV_DIV_MASK) + 1U;
+ freq = CLOCK_GetMainPllClkFreq() / frgPllDiv;
+ break;
+
+ case CLKCTL1_FRGCLKSEL_SEL(2):
+ freq = CLK_FRO_DIV4_CLK;
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return (uint32_t)(((uint64_t)freq * ((uint64_t)frgDiv + 1ULL)) / (frgMul + frgDiv + 1UL));
+}
+
+/* Get FLEXCOMM Clk */
+/*! brief Return Frequency of Flexcomm functional Clock
+ * param id : flexcomm index to get frequency.
+ * return Frequency of Flexcomm functional Clock
+ */
+uint32_t CLOCK_GetFlexcommClkFreq(uint32_t id)
+{
+ uint32_t freq = 0U;
+ uint32_t clkSel = 0U;
+
+ assert(id <= 16U);
+
+ clkSel = CLKCTL1->FLEXCOMM[id].FCFCLKSEL;
+
+ switch (clkSel & CLKCTL1_FCFCLKSEL_SEL_MASK)
+ {
+ case CLKCTL1_FCFCLKSEL_SEL(0):
+ freq = CLK_FRO_DIV4_CLK;
+ break;
+
+ case CLKCTL1_FCFCLKSEL_SEL(1):
+ freq = CLOCK_GetAudioPllClkFreq();
+ break;
+
+ case CLKCTL1_FCFCLKSEL_SEL(2):
+ freq = g_mclkFreq;
+ break;
+
+ case CLKCTL1_FCFCLKSEL_SEL(3):
+ freq = CLOCK_GetFRGClock(id);
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+/*! @brief Return Frequency of Flexio functional Clock
+ * @return Frequency of Flexcomm functional Clock
+ */
+uint32_t CLOCK_GetFlexioClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (CLKCTL1->FLEXIOCLKSEL & CLKCTL1_FLEXIOCLKSEL_SEL_MASK)
+ {
+ case CLKCTL1_FLEXIOCLKSEL_SEL(0):
+ freq = CLK_FRO_DIV2_CLK;
+ break;
+
+ case CLKCTL1_FLEXIOCLKSEL_SEL(1):
+ freq = CLOCK_GetAudioPllClkFreq();
+ break;
+
+ case CLKCTL1_FLEXIOCLKSEL_SEL(2):
+ freq = CLOCK_GetMclkInClkFreq();
+ break;
+
+ case CLKCTL1_FLEXIOCLKSEL_SEL(3):
+ freq = CLOCK_GetFRGClock(17);
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((CLKCTL1->FLEXIOCLKDIV & CLKCTL1_FLEXIOCLKDIV_DIV_MASK) + 1U);
+}
+
+/* Get CTIMER Clk */
+/*! brief Return Frequency of Ctimer Clock
+ * param id : ctimer index to get frequency.
+ * return Frequency of Ctimer Clock
+ */
+uint32_t CLOCK_GetCtimerClkFreq(uint32_t id)
+{
+ uint32_t freq = 0U;
+
+ switch ((CLKCTL1->CT32BITFCLKSEL[id]) & CLKCTL1_CT32BITFCLKSEL_SEL_MASK)
+ {
+ case CLKCTL1_CT32BITFCLKSEL_SEL(0):
+ freq = CLOCK_GetMainClkFreq();
+ break;
+
+ case CLKCTL1_CT32BITFCLKSEL_SEL(1):
+ freq = CLK_FRO_CLK;
+ break;
+
+ case CLKCTL1_CT32BITFCLKSEL_SEL(2):
+ freq = CLOCK_GetAudioPllClkFreq();
+ break;
+
+ case CLKCTL1_CT32BITFCLKSEL_SEL(3):
+ freq = CLOCK_GetMclkInClkFreq();
+ break;
+
+ case CLKCTL1_CT32BITFCLKSEL_SEL(4):
+ freq = CLOCK_GetWakeClk32KFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+/*! @brief Return Frequency of FLEXSPI Clock
+ * @param id : flexspi index to get frequency.
+ * @return Frequency of Flexspi.
+ */
+uint32_t CLOCK_GetFlexspiClkFreq(uint32_t id)
+{
+ uint32_t freq = 0U;
+ uint32_t clkSel;
+ uint32_t clkDiv;
+
+ assert(id <= 1U);
+
+ if (id == 0U)
+ {
+ clkSel = CLKCTL0->FLEXSPI0FCLKSEL & CLKCTL0_FLEXSPI0FCLKSEL_SEL_MASK;
+ clkDiv = CLKCTL0->FLEXSPI0FCLKDIV & CLKCTL0_FLEXSPI0FCLKDIV_DIV_MASK;
+ }
+ else
+ {
+ clkSel = CLKCTL0->FLEXSPI1FCLKSEL & CLKCTL0_FLEXSPI1FCLKSEL_SEL_MASK;
+ clkDiv = CLKCTL0->FLEXSPI1FCLKDIV & CLKCTL0_FLEXSPI1FCLKDIV_DIV_MASK;
+ }
+
+ switch (clkSel)
+ {
+ case CLKCTL0_FLEXSPI0FCLKSEL_SEL(0):
+ freq = CLOCK_GetMainClkFreq();
+ break;
+
+ case CLKCTL0_FLEXSPI0FCLKSEL_SEL(1):
+ freq = CLOCK_GetMainPllClkFreq();
+ break;
+
+ case CLKCTL0_FLEXSPI0FCLKSEL_SEL(2):
+ freq = CLOCK_GetAux0PllClkFreq();
+ break;
+
+ case CLKCTL0_FLEXSPI0FCLKSEL_SEL(3):
+ freq = CLK_FRO_CLK;
+ break;
+
+ case CLKCTL0_FLEXSPI0FCLKSEL_SEL(4):
+ freq = CLOCK_GetAux1PllClkFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / (clkDiv + 1U);
+}
+
+/* Get SCT Clk */
+/*! brief Return Frequency of sct
+ * return Frequency of sct clk
+ */
+uint32_t CLOCK_GetSctClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch ((CLKCTL0->SCTFCLKSEL) & CLKCTL0_SCTFCLKSEL_SEL_MASK)
+ {
+ case CLKCTL0_SCTFCLKSEL_SEL(0):
+ freq = CLOCK_GetMainClkFreq();
+ break;
+
+ case CLKCTL0_SCTFCLKSEL_SEL(1):
+ freq = CLOCK_GetMainPllClkFreq();
+ break;
+
+ case CLKCTL0_SCTFCLKSEL_SEL(2):
+ freq = CLOCK_GetAux0PllClkFreq();
+ break;
+
+ case CLKCTL0_SCTFCLKSEL_SEL(3):
+ freq = CLK_FRO_CLK;
+ break;
+
+ case CLKCTL0_SCTFCLKSEL_SEL(4):
+ freq = CLOCK_GetAux1PllClkFreq();
+ break;
+
+ case CLKCTL0_SCTFCLKSEL_SEL(5):
+ freq = CLOCK_GetAudioPllClkFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((CLKCTL0->SCTIN7CLKDIV & CLKCTL0_SCTIN7CLKDIV_DIV_MASK) + 1U);
+}
+
+/*! brief Return Frequency of mclk
+ * return Frequency of mclk clk
+ */
+uint32_t CLOCK_GetMclkClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ if ((CLKCTL1->AUDIOMCLKSEL & CLKCTL1_AUDIOMCLKSEL_SEL_MASK) == CLKCTL1_AUDIOMCLKSEL_SEL(0))
+ {
+ freq = CLK_FRO_DIV8_CLK;
+ }
+ else if ((CLKCTL1->AUDIOMCLKSEL & CLKCTL1_AUDIOMCLKSEL_SEL_MASK) == CLKCTL1_AUDIOMCLKSEL_SEL(1))
+ {
+ freq = CLOCK_GetAudioPllClkFreq();
+ }
+ else
+ {
+ freq = 0U;
+ }
+
+ return freq / ((CLKCTL1->AUDIOMCLKDIV & CLKCTL1_AUDIOMCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! @brief Return Frequency of WDT clk
+ * @param id : WDT index to get frequency.
+ * @return Frequency of WDT clk
+ */
+uint32_t CLOCK_GetWdtClkFreq(uint32_t id)
+{
+ uint32_t freq = 0U;
+
+ assert(id <= 1U);
+
+ if (id == 0U)
+ {
+ if ((CLKCTL0->WDT0FCLKSEL & CLKCTL0_WDT0FCLKSEL_SEL_MASK) == CLKCTL0_WDT0FCLKSEL_SEL(0))
+ {
+ freq = CLOCK_GetLpOscFreq();
+ }
+ else
+ {
+ freq = 0U;
+ }
+ }
+ else
+ {
+ if ((CLKCTL1->WDT1FCLKSEL & CLKCTL1_WDT1FCLKSEL_SEL_MASK) == CLKCTL1_WDT1FCLKSEL_SEL(0))
+ {
+ freq = CLOCK_GetLpOscFreq();
+ }
+ else
+ {
+ freq = 0U;
+ }
+ }
+
+ return freq;
+}
+
+/*! brief Return Frequency of systick clk
+ * return Frequency of systick clk
+ */
+uint32_t CLOCK_GetSystickClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (CLKCTL0->SYSTICKFCLKSEL & CLKCTL0_SYSTICKFCLKSEL_SEL_MASK)
+ {
+ case CLKCTL0_SYSTICKFCLKSEL_SEL(0):
+ freq = CLOCK_GetMainClkFreq() / ((CLKCTL0->SYSTICKFCLKDIV & CLKCTL0_SYSTICKFCLKDIV_DIV_MASK) + 1U);
+ break;
+
+ case CLKCTL0_SYSTICKFCLKSEL_SEL(1):
+ freq = CLOCK_GetLpOscFreq();
+ break;
+
+ case CLKCTL0_SYSTICKFCLKSEL_SEL(2):
+ freq = CLOCK_GetOsc32KFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+/*! brief Return Frequency of SDIO clk
+ * param id : SDIO index to get frequency.
+ * return Frequency of SDIO clk
+ */
+uint32_t CLOCK_GetSdioClkFreq(uint32_t id)
+{
+ uint32_t freq = 0U;
+ volatile uint32_t *pClkSel;
+ volatile uint32_t *pClkDiv;
+
+ assert(id <= 1U);
+
+ if (id == 0U)
+ {
+ pClkSel = &CLKCTL0->SDIO0FCLKSEL;
+ pClkDiv = &CLKCTL0->SDIO0FCLKDIV;
+ }
+ else
+ {
+ pClkSel = &CLKCTL0->SDIO1FCLKSEL;
+ pClkDiv = &CLKCTL0->SDIO1FCLKDIV;
+ }
+
+ switch ((*pClkSel) & CLKCTL0_SDIO0FCLKSEL_SEL_MASK)
+ {
+ case CLKCTL0_SDIO0FCLKSEL_SEL(0):
+ freq = CLOCK_GetMainClkFreq();
+ break;
+
+ case CLKCTL0_SDIO0FCLKSEL_SEL(1):
+ freq = CLOCK_GetMainPllClkFreq();
+ break;
+
+ case CLKCTL0_SDIO0FCLKSEL_SEL(2):
+ freq = CLOCK_GetAux0PllClkFreq();
+ break;
+
+ case CLKCTL0_SDIO0FCLKSEL_SEL(3):
+ freq = CLK_FRO_DIV2_CLK;
+ break;
+
+ case CLKCTL0_SDIO0FCLKSEL_SEL(4):
+ freq = CLOCK_GetAux1PllClkFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / (((*pClkDiv) & CLKCTL0_SDIO0FCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! @brief Return Frequency of I3C clk
+ * @return Frequency of I3C clk
+ */
+uint32_t CLOCK_GetI3cClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (CLKCTL1->I3C01FCLKSEL & CLKCTL1_I3C01FCLKSEL_SEL_MASK)
+ {
+ case CLKCTL1_I3C01FCLKSEL_SEL(0):
+ freq = CLOCK_GetMainClkFreq();
+ break;
+
+ case CLKCTL1_I3C01FCLKSEL_SEL(1):
+ freq = CLK_FRO_DIV8_CLK;
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((CLKCTL1->I3C01FCLKDIV & CLKCTL1_I3C01FCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! brief Return Frequency of USB clk
+ * return Frequency of USB clk
+ */
+uint32_t CLOCK_GetUsbClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (CLKCTL0->USBHSFCLKSEL & CLKCTL0_USBHSFCLKSEL_SEL_MASK)
+ {
+ case CLKCTL0_USBHSFCLKSEL_SEL(0):
+ freq = CLOCK_GetXtalInClkFreq();
+ break;
+ case CLKCTL0_USBHSFCLKSEL_SEL(1):
+ freq = CLOCK_GetMainClkFreq();
+ break;
+ case CLKCTL0_USBHSFCLKSEL_SEL(2):
+ freq = CLK_FRO_DIV8_CLK;
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((CLKCTL0->USBHSFCLKDIV & CLKCTL0_USBHSFCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! brief Return Frequency of DMIC clk
+ * return Frequency of DMIC clk
+ */
+uint32_t CLOCK_GetDmicClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch ((CLKCTL1->DMIC0FCLKSEL) & CLKCTL1_DMIC0FCLKSEL_SEL_MASK)
+ {
+ case CLKCTL1_DMIC0FCLKSEL_SEL(0):
+ freq = CLK_FRO_DIV4_CLK;
+ break;
+
+ case CLKCTL1_DMIC0FCLKSEL_SEL(1):
+ freq = CLOCK_GetAudioPllClkFreq();
+ break;
+
+ case CLKCTL1_DMIC0FCLKSEL_SEL(2):
+ freq = CLOCK_GetMclkInClkFreq();
+ break;
+
+ case CLKCTL1_DMIC0FCLKSEL_SEL(3):
+ freq = CLOCK_GetLpOscFreq();
+ break;
+
+ case CLKCTL1_DMIC0FCLKSEL_SEL(4):
+ freq = CLOCK_GetWakeClk32KFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((CLKCTL1->DMIC0FCLKDIV & CLKCTL1_DMIC0FCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! brief Return Frequency of ACMP clk
+ * return Frequency of ACMP clk
+ */
+uint32_t CLOCK_GetAcmpClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch ((CLKCTL1->ACMP0FCLKSEL) & CLKCTL1_ACMP0FCLKSEL_SEL_MASK)
+ {
+ case CLKCTL1_ACMP0FCLKSEL_SEL(0):
+ freq = CLOCK_GetMainClkFreq();
+ break;
+
+ case CLKCTL1_ACMP0FCLKSEL_SEL(1):
+ freq = CLK_FRO_DIV4_CLK;
+ break;
+
+ case CLKCTL1_ACMP0FCLKSEL_SEL(2):
+ freq = CLOCK_GetAux0PllClkFreq();
+ break;
+
+ case CLKCTL1_ACMP0FCLKSEL_SEL(3):
+ freq = CLOCK_GetAux1PllClkFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((CLKCTL1->ACMP0FCLKDIV & CLKCTL1_ACMP0FCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! @brief Return Frequency of GPU functional Clock
+ * @return Frequency of GPU functional Clock
+ */
+uint32_t CLOCK_GetGpuClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (CLKCTL0->GPUCLKSEL & CLKCTL0_GPUCLKSEL_SEL_MASK)
+ {
+ case CLKCTL0_GPUCLKSEL_SEL(0):
+ freq = CLOCK_GetMainClkFreq();
+ break;
+
+ case CLKCTL0_GPUCLKSEL_SEL(1):
+ freq = CLK_FRO_CLK;
+ break;
+
+ case CLKCTL0_GPUCLKSEL_SEL(2):
+ freq = CLOCK_GetMainPllClkFreq();
+ break;
+
+ case CLKCTL0_GPUCLKSEL_SEL(3):
+ freq = CLOCK_GetAux0PllClkFreq();
+ break;
+
+ case CLKCTL0_GPUCLKSEL_SEL(4):
+ freq = CLOCK_GetAux1PllClkFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((CLKCTL0->GPUCLKDIV & CLKCTL0_GPUCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! @brief Return Frequency of DCNano Pixel functional Clock
+ * @return Frequency of DCNano pixel functional Clock
+ */
+uint32_t CLOCK_GetDcPixelClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (CLKCTL0->DCPIXELCLKSEL & CLKCTL0_DCPIXELCLKSEL_SEL_MASK)
+ {
+ case CLKCTL0_DCPIXELCLKSEL_SEL(0):
+ freq = CLOCK_GetMipiDphyClkFreq();
+ break;
+ case CLKCTL0_DCPIXELCLKSEL_SEL(1):
+ freq = CLOCK_GetMainClkFreq();
+ break;
+
+ case CLKCTL0_DCPIXELCLKSEL_SEL(2):
+ freq = CLK_FRO_CLK;
+ break;
+
+ case CLKCTL0_DCPIXELCLKSEL_SEL(3):
+ freq = CLOCK_GetMainPllClkFreq();
+ break;
+
+ case CLKCTL0_DCPIXELCLKSEL_SEL(4):
+ freq = CLOCK_GetAux0PllClkFreq();
+ break;
+
+ case CLKCTL0_DCPIXELCLKSEL_SEL(5):
+ freq = CLOCK_GetAux1PllClkFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((CLKCTL0->DCPIXELCLKDIV & CLKCTL0_DCPIXELCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! @brief Return Frequency of MIPI DPHY functional Clock
+ * @return Frequency of MIPI DPHY functional Clock
+ */
+uint32_t CLOCK_GetMipiDphyClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (CLKCTL0->DPHYCLKSEL & CLKCTL0_DPHYCLKSEL_SEL_MASK)
+ {
+ case CLKCTL0_DPHYCLKSEL_SEL(0):
+ freq = CLK_FRO_CLK;
+ break;
+ case CLKCTL0_DPHYCLKSEL_SEL(1):
+ freq = CLOCK_GetMainPllClkFreq();
+ break;
+
+ case CLKCTL0_DPHYCLKSEL_SEL(2):
+ freq = CLOCK_GetAux0PllClkFreq();
+ break;
+
+ case CLKCTL0_DPHYCLKSEL_SEL(3):
+ freq = CLOCK_GetAux1PllClkFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((CLKCTL0->DPHYCLKDIV & CLKCTL0_DPHYCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! @brief Return Frequency of MIPI DPHY Esc RX functional Clock
+ * @return Frequency of MIPI DPHY Esc RX functional Clock
+ */
+uint32_t CLOCK_GetMipiDphyEscRxClkFreq(void)
+{
+ uint32_t freq = 0U;
+
+ switch (CLKCTL0->DPHYESCCLKSEL & CLKCTL0_DPHYESCCLKSEL_SEL_MASK)
+ {
+ case CLKCTL0_DPHYESCCLKSEL_SEL(0):
+ freq = CLK_FRO_CLK;
+ break;
+ case CLKCTL0_DPHYESCCLKSEL_SEL(1):
+ freq = CLK_FRO_DIV16_CLK;
+ break;
+ case CLKCTL0_DPHYESCCLKSEL_SEL(2):
+ freq = CLOCK_GetAux0PllClkFreq();
+ break;
+ case CLKCTL0_DPHYESCCLKSEL_SEL(3):
+ freq = CLOCK_GetAux1PllClkFreq();
+ break;
+
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq / ((CLKCTL0->DPHYESCRXCLKDIV & CLKCTL0_DPHYESCRXCLKDIV_DIV_MASK) + 1U);
+}
+
+/*! @brief Return Frequency of MIPI DPHY Esc Tx functional Clock
+ * @return Frequency of MIPI DPHY Esc Tx functional Clock
+ */
+uint32_t CLOCK_GetMipiDphyEscTxClkFreq(void)
+{
+ return CLOCK_GetMipiDphyEscRxClkFreq() / ((CLKCTL0->DPHYESCTXCLKDIV & CLKCTL0_DPHYESCTXCLKDIV_DIV_MASK) + 1U);
+}
+
+/* Get IP Clk */
+/*! brief Return Frequency of selected clock
+ * return Frequency of selected clock
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName)
+{
+ uint32_t freq = 0U;
+
+ switch (clockName)
+ {
+ case kCLOCK_CoreSysClk:
+ case kCLOCK_BusClk:
+ freq = CLOCK_GetMainClkFreq() / ((CLKCTL0->SYSCPUAHBCLKDIV & CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK) + 1U);
+ break;
+ case kCLOCK_MclkClk:
+ freq = CLOCK_GetMclkClkFreq();
+ break;
+ case kCLOCK_ClockOutClk:
+ freq = CLOCK_GetClockOutClkFreq();
+ break;
+ case kCLOCK_AdcClk:
+ freq = CLOCK_GetAdcClkFreq();
+ break;
+ case kCLOCK_Flexspi0Clk:
+ freq = CLOCK_GetFlexspiClkFreq(0U);
+ break;
+ case kCLOCK_Flexspi1Clk:
+ freq = CLOCK_GetFlexspiClkFreq(1U);
+ break;
+ case kCLOCK_SctClk:
+ freq = CLOCK_GetSctClkFreq();
+ break;
+ case kCLOCK_Wdt0Clk:
+ freq = CLOCK_GetWdtClkFreq(0U);
+ break;
+ case kCLOCK_Wdt1Clk:
+ freq = CLOCK_GetWdtClkFreq(1U);
+ break;
+ case kCLOCK_SystickClk:
+ freq = CLOCK_GetSystickClkFreq();
+ break;
+ case kCLOCK_Sdio0Clk:
+ freq = CLOCK_GetSdioClkFreq(0U);
+ break;
+ case kCLOCK_Sdio1Clk:
+ freq = CLOCK_GetSdioClkFreq(1U);
+ break;
+ case kCLOCK_I3cClk:
+ freq = CLOCK_GetI3cClkFreq();
+ break;
+ case kCLOCK_UsbClk:
+ freq = CLOCK_GetUsbClkFreq();
+ break;
+ case kCLOCK_DmicClk:
+ freq = CLOCK_GetDmicClkFreq();
+ break;
+ case kCLOCK_DspCpuClk:
+ freq = CLOCK_GetDspMainClkFreq() / ((CLKCTL1->DSPCPUCLKDIV & CLKCTL1_DSPCPUCLKDIV_DIV_MASK) + 1U);
+ break;
+ case kCLOCK_AcmpClk:
+ freq = CLOCK_GetAcmpClkFreq();
+ break;
+ case kCLOCK_Flexcomm0Clk:
+ freq = CLOCK_GetFlexcommClkFreq(0U);
+ break;
+ case kCLOCK_Flexcomm1Clk:
+ freq = CLOCK_GetFlexcommClkFreq(1U);
+ break;
+ case kCLOCK_Flexcomm2Clk:
+ freq = CLOCK_GetFlexcommClkFreq(2U);
+ break;
+ case kCLOCK_Flexcomm3Clk:
+ freq = CLOCK_GetFlexcommClkFreq(3U);
+ break;
+ case kCLOCK_Flexcomm4Clk:
+ freq = CLOCK_GetFlexcommClkFreq(4U);
+ break;
+ case kCLOCK_Flexcomm5Clk:
+ freq = CLOCK_GetFlexcommClkFreq(5U);
+ break;
+ case kCLOCK_Flexcomm6Clk:
+ freq = CLOCK_GetFlexcommClkFreq(6U);
+ break;
+ case kCLOCK_Flexcomm7Clk:
+ freq = CLOCK_GetFlexcommClkFreq(7U);
+ break;
+ case kCLOCK_Flexcomm8Clk:
+ freq = CLOCK_GetFlexcommClkFreq(8U);
+ break;
+ case kCLOCK_Flexcomm9Clk:
+ freq = CLOCK_GetFlexcommClkFreq(9U);
+ break;
+ case kCLOCK_Flexcomm10Clk:
+ freq = CLOCK_GetFlexcommClkFreq(10U);
+ break;
+ case kCLOCK_Flexcomm11Clk:
+ freq = CLOCK_GetFlexcommClkFreq(11U);
+ break;
+ case kCLOCK_Flexcomm12Clk:
+ freq = CLOCK_GetFlexcommClkFreq(12U);
+ break;
+ case kCLOCK_Flexcomm13Clk:
+ freq = CLOCK_GetFlexcommClkFreq(13U);
+ break;
+ case kCLOCK_Flexcomm14Clk:
+ freq = CLOCK_GetFlexcommClkFreq(14U);
+ break;
+ case kCLOCK_Flexcomm15Clk:
+ freq = CLOCK_GetFlexcommClkFreq(15U);
+ break;
+ case kCLOCK_Flexcomm16Clk:
+ freq = CLOCK_GetFlexcommClkFreq(16U);
+ break;
+ case kCLOCK_FlexioClk:
+ freq = CLOCK_GetFlexioClkFreq();
+ break;
+ case kCLOCK_GpuClk:
+ freq = CLOCK_GetGpuClkFreq();
+ break;
+ case kCLOCK_DcPixelClk:
+ freq = CLOCK_GetDcPixelClkFreq();
+ break;
+ case kCLOCK_MipiDphyClk:
+ freq = CLOCK_GetMipiDphyClkFreq();
+ break;
+ case kCLOCK_MipiDphyEscRxClk:
+ freq = CLOCK_GetMipiDphyEscRxClkFreq();
+ break;
+ case kCLOCK_MipiDphyEscTxClk:
+ freq = CLOCK_GetMipiDphyEscTxClkFreq();
+ break;
+ default:
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+/* Set FRG Clk */
+/*! brief Set output of the Fractional baud rate generator
+ * param config : Configuration to set to FRGn clock.
+ */
+void CLOCK_SetFRGClock(const clock_frg_clk_config_t *config)
+{
+ uint32_t i = config->num;
+
+ assert(i <= 17U);
+ assert(config->divider == 255U); /* Always set to 0xFF to use with the fractional baudrate generator.*/
+
+ if (i == 17U)
+ {
+ CLKCTL1->FRG17CLKSEL = (uint32_t)config->sfg_clock_src;
+ CLKCTL1->FRG17CTL = (CLKCTL1_FRG17CTL_MULT(config->mult) | CLKCTL1_FRG17CTL_DIV(config->divider));
+ }
+ else
+ {
+ CLKCTL1->FLEXCOMM[i].FRGCLKSEL = (uint32_t)config->sfg_clock_src;
+ CLKCTL1->FLEXCOMM[i].FRGCTL = (CLKCTL1_FRGCTL_MULT(config->mult) | CLKCTL1_FRGCTL_DIV(config->divider));
+ }
+}
+
+/* Initialize the SYSTEM PLL Clk */
+/*! brief Initialize the System PLL.
+ * param config : Configuration to set to PLL.
+ */
+void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
+{
+ /* Power down SYSPLL before change fractional settings */
+ SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK;
+
+ CLKCTL0->SYSPLL0CLKSEL = (uint32_t)config->sys_pll_src;
+ CLKCTL0->SYSPLL0NUM = config->numerator;
+ CLKCTL0->SYSPLL0DENOM = config->denominator;
+ switch (config->sys_pll_mult)
+ {
+ case kCLOCK_SysPllMult16:
+ CLKCTL0->SYSPLL0CTL0 =
+ (CLKCTL0->SYSPLL0CTL0 & ~CLKCTL0_SYSPLL0CTL0_MULT_MASK) | CLKCTL0_SYSPLL0CTL0_MULT(16);
+ break;
+ case kCLOCK_SysPllMult17:
+ CLKCTL0->SYSPLL0CTL0 =
+ (CLKCTL0->SYSPLL0CTL0 & ~CLKCTL0_SYSPLL0CTL0_MULT_MASK) | CLKCTL0_SYSPLL0CTL0_MULT(17);
+ break;
+ case kCLOCK_SysPllMult18:
+ CLKCTL0->SYSPLL0CTL0 =
+ (CLKCTL0->SYSPLL0CTL0 & ~CLKCTL0_SYSPLL0CTL0_MULT_MASK) | CLKCTL0_SYSPLL0CTL0_MULT(18);
+ break;
+ case kCLOCK_SysPllMult19:
+ CLKCTL0->SYSPLL0CTL0 =
+ (CLKCTL0->SYSPLL0CTL0 & ~CLKCTL0_SYSPLL0CTL0_MULT_MASK) | CLKCTL0_SYSPLL0CTL0_MULT(19);
+ break;
+ case kCLOCK_SysPllMult20:
+ CLKCTL0->SYSPLL0CTL0 =
+ (CLKCTL0->SYSPLL0CTL0 & ~CLKCTL0_SYSPLL0CTL0_MULT_MASK) | CLKCTL0_SYSPLL0CTL0_MULT(20);
+ break;
+ case kCLOCK_SysPllMult21:
+ CLKCTL0->SYSPLL0CTL0 =
+ (CLKCTL0->SYSPLL0CTL0 & ~CLKCTL0_SYSPLL0CTL0_MULT_MASK) | CLKCTL0_SYSPLL0CTL0_MULT(21);
+ break;
+ case kCLOCK_SysPllMult22:
+ CLKCTL0->SYSPLL0CTL0 =
+ (CLKCTL0->SYSPLL0CTL0 & ~CLKCTL0_SYSPLL0CTL0_MULT_MASK) | CLKCTL0_SYSPLL0CTL0_MULT(22);
+ break;
+ default:
+ assert(false);
+ break;
+ }
+ /* Clear System PLL reset*/
+ CLKCTL0->SYSPLL0CTL0 &= ~CLKCTL0_SYSPLL0CTL0_RESET_MASK;
+ /* Power up SYSPLL*/
+ SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK;
+ SDK_DelayAtLeastUs((CLKCTL0->SYSPLL0LOCKTIMEDIV2 & CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 2U,
+ SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ /* Set System PLL HOLDRINGOFF_ENA */
+ CLKCTL0->SYSPLL0CTL0 |= CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_MASK;
+ SDK_DelayAtLeastUs((CLKCTL0->SYSPLL0LOCKTIMEDIV2 & CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 6U,
+ SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ /* Clear System PLL HOLDRINGOFF_ENA*/
+ CLKCTL0->SYSPLL0CTL0 &= ~CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_MASK;
+ SDK_DelayAtLeastUs((CLKCTL0->SYSPLL0LOCKTIMEDIV2 & CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 3U,
+ SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+}
+
+/* Initialize the System PLL PFD */
+/*! brief Initialize the System PLL PFD.
+ * param pfd : Which PFD clock to enable.
+ * param divider : The PFD divider value.
+ * note It is recommended that PFD settings are kept between 12-35.
+ */
+void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t divider)
+{
+ uint32_t pfdIndex = (uint32_t)pfd;
+ uint32_t syspfd;
+
+ syspfd = CLKCTL0->SYSPLL0PFD &
+ ~(((uint32_t)CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_MASK | (uint32_t)CLKCTL0_SYSPLL0PFD_PFD0_MASK)
+ << (8UL * pfdIndex));
+
+ /* Disable the clock output first. */
+ CLKCTL0->SYSPLL0PFD = syspfd | ((uint32_t)CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_MASK << (8UL * pfdIndex));
+
+ /* Set the new value and enable output. */
+ CLKCTL0->SYSPLL0PFD = syspfd | ((uint32_t)CLKCTL0_SYSPLL0PFD_PFD0(divider) << (8UL * pfdIndex));
+ /* Wait for output becomes stable. */
+ while ((CLKCTL0->SYSPLL0PFD & ((uint32_t)CLKCTL0_SYSPLL0PFD_PFD0_CLKRDY_MASK << (8UL * pfdIndex))) == 0UL)
+ {
+ }
+ /* Clear ready status flag. */
+ CLKCTL0->SYSPLL0PFD |= ((uint32_t)CLKCTL0_SYSPLL0PFD_PFD0_CLKRDY_MASK << (8UL * pfdIndex));
+}
+
+/* Initialize the Audio PLL Clk */
+/*! brief Initialize the audio PLL.
+ * param config : Configuration to set to PLL.
+ */
+void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
+{
+ /* Power down Audio PLL before change fractional settings */
+ SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK;
+
+ CLKCTL1->AUDIOPLL0CLKSEL = (uint32_t)config->audio_pll_src;
+ CLKCTL1->AUDIOPLL0NUM = config->numerator;
+ CLKCTL1->AUDIOPLL0DENOM = config->denominator;
+
+ switch (config->audio_pll_mult)
+ {
+ case kCLOCK_AudioPllMult16:
+ CLKCTL1->AUDIOPLL0CTL0 =
+ (CLKCTL1->AUDIOPLL0CTL0 & ~CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) | CLKCTL1_AUDIOPLL0CTL0_MULT(16);
+ break;
+ case kCLOCK_AudioPllMult17:
+ CLKCTL1->AUDIOPLL0CTL0 =
+ (CLKCTL1->AUDIOPLL0CTL0 & ~CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) | CLKCTL1_AUDIOPLL0CTL0_MULT(17);
+ break;
+ case kCLOCK_AudioPllMult18:
+ CLKCTL1->AUDIOPLL0CTL0 =
+ (CLKCTL1->AUDIOPLL0CTL0 & ~CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) | CLKCTL1_AUDIOPLL0CTL0_MULT(18);
+ break;
+ case kCLOCK_AudioPllMult19:
+ CLKCTL1->AUDIOPLL0CTL0 =
+ (CLKCTL1->AUDIOPLL0CTL0 & ~CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) | CLKCTL1_AUDIOPLL0CTL0_MULT(19);
+ break;
+ case kCLOCK_AudioPllMult20:
+ CLKCTL1->AUDIOPLL0CTL0 =
+ (CLKCTL1->AUDIOPLL0CTL0 & ~CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) | CLKCTL1_AUDIOPLL0CTL0_MULT(20);
+ break;
+ case kCLOCK_AudioPllMult21:
+ CLKCTL1->AUDIOPLL0CTL0 =
+ (CLKCTL1->AUDIOPLL0CTL0 & ~CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) | CLKCTL1_AUDIOPLL0CTL0_MULT(21);
+ break;
+ case kCLOCK_AudioPllMult22:
+ CLKCTL1->AUDIOPLL0CTL0 =
+ (CLKCTL1->AUDIOPLL0CTL0 & ~CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) | CLKCTL1_AUDIOPLL0CTL0_MULT(22);
+ break;
+ default:
+ assert(false);
+ break;
+ }
+ /* Clear Audio PLL reset*/
+ CLKCTL1->AUDIOPLL0CTL0 &= ~CLKCTL1_AUDIOPLL0CTL0_RESET_MASK;
+ /* Power up Audio PLL*/
+ SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK;
+ SDK_DelayAtLeastUs((CLKCTL1->AUDIOPLL0LOCKTIMEDIV2 & CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 2U,
+ SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ /* Set Audio PLL HOLDRINGOFF_ENA */
+ CLKCTL1->AUDIOPLL0CTL0 |= CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK;
+ SDK_DelayAtLeastUs((CLKCTL1->AUDIOPLL0LOCKTIMEDIV2 & CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 6U,
+ SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ /* Clear Audio PLL HOLDRINGOFF_ENA*/
+ CLKCTL1->AUDIOPLL0CTL0 &= ~CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK;
+ SDK_DelayAtLeastUs((CLKCTL1->AUDIOPLL0LOCKTIMEDIV2 & CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 3U,
+ SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+}
+
+/* Initialize the Audio PLL PFD */
+/*! brief Initialize the audio PLL PFD.
+ * param pfd : Which PFD clock to enable.
+ * param divider : The PFD divider value.
+ * note It is recommended that PFD settings are kept between 12-35.
+ */
+void CLOCK_InitAudioPfd(clock_pfd_t pfd, uint8_t divider)
+{
+ uint32_t pfdIndex = (uint32_t)pfd;
+ uint32_t syspfd;
+
+ syspfd = CLKCTL1->AUDIOPLL0PFD &
+ ~(((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK | (uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_MASK)
+ << (8UL * pfdIndex));
+
+ /* Disable the clock output first. */
+ CLKCTL1->AUDIOPLL0PFD = syspfd | ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8UL * pfdIndex));
+
+ /* Set the new value and enable output. */
+ CLKCTL1->AUDIOPLL0PFD = syspfd | ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0(divider) << (8UL * pfdIndex));
+ /* Wait for output becomes stable. */
+ while ((CLKCTL1->AUDIOPLL0PFD & ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKRDY_MASK << (8UL * pfdIndex))) == 0UL)
+ {
+ }
+ /* Clear ready status flag. */
+ CLKCTL1->AUDIOPLL0PFD |= ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKRDY_MASK << (8UL * pfdIndex));
+}
+
+/*! @brief Enable/Disable sys osc clock from external crystal clock.
+ * @param enable : true to enable system osc clock, false to bypass system osc.
+ * @param enableLowPower : true to enable low power mode, false to enable high gain mode.
+ * @param delay_us : Delay time after OSC power up.
+ */
+void CLOCK_EnableSysOscClk(bool enable, bool enableLowPower, uint32_t delay_us)
+{
+ uint32_t ctrl = enableLowPower ? CLKCTL0_SYSOSCCTL0_LP_ENABLE_MASK : 0U;
+
+ if (enable)
+ {
+ CLKCTL0->SYSOSCCTL0 = ctrl;
+ CLKCTL0->SYSOSCBYPASS = 0U;
+ SDK_DelayAtLeastUs(delay_us, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ }
+ else
+ {
+ CLKCTL0->SYSOSCCTL0 = ctrl | CLKCTL0_SYSOSCCTL0_BYPASS_ENABLE_MASK;
+ }
+}
+
+/*! @brief Enable/Disable FRO clock output.
+ * @param divOutEnable : Or'ed value of clock_fro_output_en_t to enable certain clock freq output.
+ */
+void CLOCK_EnableFroClk(uint32_t divOutEnable)
+{
+ if (divOutEnable != 0U)
+ {
+ /* Some FRO frequency need to be outputed. Wait FRO stable first in case FRO just get powered on. */
+ while ((CLKCTL0->FROCLKSTATUS & CLKCTL0_FROCLKSTATUS_CLK_OK_MASK) == 0U)
+ {
+ }
+ }
+ else
+ {
+ /* Do nothing */
+ }
+ CLKCTL0->FRODIVOEN = divOutEnable & (uint32_t)kCLOCK_FroAllOutEn;
+}
+
+#ifndef __XCC__
+/*! @brief Enable/Disable FRO192M or FRO96M clock output.
+ * @param froFreq : target fro frequency.
+ * @param divOutEnable : Or'ed value of clock_fro_output_en_t to enable certain clock freq output.
+ */
+void CLOCK_EnableFroClkRange(clock_fro_freq_t froFreq, uint32_t divOutEnable)
+{
+ uint32_t scTrim, rdTrim;
+
+ OTP_INIT_API(CLOCK_GetFreq(kCLOCK_BusClk));
+ if (froFreq == kCLOCK_Fro192M)
+ {
+ /* Read 192M FRO clock Trim settings from fuse. */
+ OTP_FUSE_READ_API(FRO_192MHZ_SC_TRIM, &scTrim);
+ OTP_FUSE_READ_API(FRO_192MHZ_RD_TRIM, &rdTrim);
+ }
+ else
+ {
+ /* Read 96M FRO clock Trim settings from fuse. */
+ OTP_FUSE_READ_API(FRO_96MHZ_SC_TRIM, &scTrim);
+ OTP_FUSE_READ_API(FRO_96MHZ_RD_TRIM, &rdTrim);
+ }
+ OTP_DEINIT_API();
+
+ CLKCTL0->FRO_SCTRIM = CLKCTL0_FRO_SCTRIM_TRIM(scTrim);
+ CLKCTL0->FRO_RDTRIM = CLKCTL0_FRO_RDTRIM_TRIM(rdTrim);
+ CLOCK_EnableFroClk(divOutEnable);
+}
+#endif /* __XCC__ */
+
+/*! @brief Enable LPOSC 1MHz clock.
+ */
+void CLOCK_EnableLpOscClk(void)
+{
+ /* No LPOSC enable/disable control in CLKCTL. Just wait LPOSC stable in case LPOSC just get powered on. */
+ while ((CLKCTL0->LPOSCCTL0 & CLKCTL0_LPOSCCTL0_CLKRDY_MASK) == 0U)
+ {
+ }
+}
+
+void CLOCK_EnableFroTuning(bool enable)
+{
+ uint32_t xtalFreq = CLOCK_GetXtalInClkFreq();
+ uint32_t froDiv4Freq = CLK_FRO_DIV4_CLK;
+ uint64_t targetFreq = (uint64_t)froDiv4Freq;
+ uint32_t expected, up, low;
+ uint32_t captured, trim;
+
+ assert(xtalFreq);
+ assert(targetFreq > xtalFreq);
+
+ if (enable)
+ {
+ expected = (uint32_t)((targetFreq * (2047U * 2U + 1U) / xtalFreq + 6U) / 2U);
+ up = (uint32_t)(targetFreq * 2047U * 100085U / xtalFreq / 100000U + 2U);
+ low = (uint32_t)((targetFreq * 2048U * 99915U + (uint64_t)xtalFreq * 100000U) / xtalFreq / 100000U + 3U);
+
+ /* Start tuning */
+ CLKCTL0->FRO_CONTROL = CLKCTL0_FRO_CONTROL_EXP_COUNT(expected) |
+ CLKCTL0_FRO_CONTROL_THRESH_RANGE_UP(up - expected) |
+ CLKCTL0_FRO_CONTROL_THRESH_RANGE_LOW(expected - low) | CLKCTL0_FRO_CONTROL_ENA_TUNE_MASK;
+
+ while (true)
+ {
+ while ((CLKCTL0->FRO_CAPVAL & CLKCTL0_FRO_CAPVAL_DATA_VALID_MASK) == 0U)
+ {
+ }
+
+ captured = CLKCTL0->FRO_CAPVAL & CLKCTL0_FRO_CAPVAL_CAPVAL_MASK;
+ trim = CLKCTL0->FRO_RDTRIM;
+ /* Clear FRO_CAPVAL VALID flag */
+ CLKCTL0->FRO_RDTRIM = trim;
+ /* Reach the frequency range, then return. */
+ if ((captured <= up) && (captured >= low))
+ {
+ break;
+ }
+ }
+ }
+ else
+ {
+ CLKCTL0->FRO_CONTROL &= ~CLKCTL0_FRO_CONTROL_ENA_TUNE_MASK;
+ }
+}
+
+/*! @brief Enable USB HS device clock.
+ *
+ * This function enables USB HS device clock.
+ */
+void CLOCK_EnableUsbHs0DeviceClock(clock_attach_id_t src, uint8_t divider)
+{
+ CLOCK_AttachClk(src);
+ /* frequency division for usb ip clock */
+ CLOCK_SetClkDiv(kCLOCK_DivUsbHsFclk, divider);
+ /* Enable usbhs device clock */
+ CLOCK_EnableClock(kCLOCK_UsbhsDevice);
+}
+
+/*! @brief Disable USB HS device clock.
+ *
+ * This function disables USB HS device clock.
+ */
+void CLOCK_DisableUsbHs0DeviceClock(void)
+{
+ /* Disable usbhs device clock */
+ CLOCK_DisableClock(kCLOCK_UsbhsDevice);
+}
+
+/*! @brief Enable USB HS host clock.
+ *
+ * This function enables USB HS host clock.
+ */
+void CLOCK_EnableUsbHs0HostClock(clock_attach_id_t src, uint8_t divider)
+{
+ CLOCK_AttachClk(src);
+ /* frequency division for usb ip clock */
+ CLOCK_SetClkDiv(kCLOCK_DivUsbHsFclk, divider);
+ /* Enable usbhs host clock */
+ CLOCK_EnableClock(kCLOCK_UsbhsHost);
+}
+
+/*! @brief Disable USB HS host clock.
+ *
+ * This function disables USB HS host clock.
+ */
+void CLOCK_DisableUsbHs0HostClock(void)
+{
+ /* Disable usbhs host clock */
+ CLOCK_DisableClock(kCLOCK_UsbhsHost);
+}
+
+/*! brief Enable USB hs0PhyPll clock.
+ *
+ * param src USB HS clock source.
+ * param freq The frequency specified by src.
+ * retval true The clock is set successfully.
+ * retval false The clock source is invalid to get proper USB HS clock.
+ */
+bool CLOCK_EnableUsbHs0PhyPllClock(clock_attach_id_t src, uint32_t freq)
+{
+ uint32_t phyPllDiv = 0U;
+ uint16_t multiplier = 0U;
+ bool retVal = true;
+
+ if (((uint32_t)(CLKCTL0->USBHSFCLKSEL & CLKCTL0_USBHSFCLKSEL_SEL_MASK)) != CLKCTL0_USBHSFCLKSEL_SEL(src))
+ {
+ retVal = false;
+ }
+
+ if ((480000000U % freq) != 0U)
+ {
+ retVal = false;
+ }
+
+ multiplier = (uint16_t)(480000000U / freq);
+
+ switch (multiplier)
+ {
+ case 13U:
+ {
+ phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U);
+ break;
+ }
+ case 15U:
+ {
+ phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U);
+ break;
+ }
+ case 16U:
+ {
+ phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U);
+ break;
+ }
+ case 20U:
+ {
+ phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(3U);
+ break;
+ }
+ case 22U:
+ {
+ phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U);
+ break;
+ }
+ case 25U:
+ {
+ phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U);
+ break;
+ }
+ case 30U:
+ {
+ phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U);
+ break;
+ }
+ case 240U:
+ {
+ phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(7U);
+ break;
+ }
+ default:
+ {
+ retVal = false;
+ break;
+ }
+ }
+
+ if (retVal)
+ {
+ /* enable usb phy clock */
+ CLOCK_EnableClock(kCLOCK_UsbhsPhy);
+ USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK;
+ USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK;
+
+ /* This field controls the USB PLL regulator, set to enable the regulator. SW
+ must set this bit 15 us before setting PLL_POWER to avoid glitches on PLL
+ output clock. */
+ USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK;
+ uint32_t i = 5000U;
+ while ((i--) != 0U)
+ {
+ __NOP();
+ }
+
+ USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_POWER(1);
+ while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_POWER_MASK) == 0U)
+ {
+ USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_POWER(1);
+ }
+
+ while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK) == 0U)
+ {
+ }
+
+ USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv;
+ USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK;
+ while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_BYPASS_MASK) != 0U)
+ {
+ USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK;
+ }
+
+ USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_ENABLE(1);
+ USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(1);
+ while ((USBPHY->PLL_SIC & (USBPHY_PLL_SIC_PLL_ENABLE(1) | USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(1))) !=
+ (USBPHY_PLL_SIC_PLL_ENABLE(1) | USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(1)))
+ {
+ USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_ENABLE(1) | USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(1);
+ }
+
+ USBPHY->PWD = 0x0;
+ }
+
+ return retVal;
+}
+
+/*! @brief Disable USB hs0PhyPll clock.
+ *
+ * This function disables USB hs0PhyPll clock.
+ */
+void CLOCK_DisableUsbHs0PhyPllClock(void)
+{
+ USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
+ USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* Power down PLL */
+}
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_clock.h b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_clock.h
new file mode 100644
index 000000000..e9f98883d
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_clock.h
@@ -0,0 +1,1540 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CLOCK_H_
+#define _FSL_CLOCK_H_
+
+#include "fsl_device_registers.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+#include "fsl_reset.h"
+#include "fsl_common.h"
+
+/*! @addtogroup clock */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CLOCK driver version 2.6.1 */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 6, 1))
+/*@}*/
+
+/* Definition for delay API in clock driver, users can redefine it to the real application. */
+#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
+#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (198000000UL)
+#endif
+
+/*! @brief External XTAL (SYSOSC) clock frequency.
+ *
+ * The XTAL (YSOSC) clock frequency in Hz, when the clock is setup, use the
+ * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
+ * if XTAL is 16MHz,
+ * @code
+ * CLOCK_SetXtalFreq(160000000);
+ * @endcode
+ */
+extern volatile uint32_t g_xtalFreq;
+
+/*! @brief External CLK_IN pin clock frequency (clkin) clock frequency.
+ *
+ * The CLK_IN pin (clkin) clock frequency in Hz, when the clock is setup, use the
+ * function CLOCK_SetClkinFreq to set the value in to clock driver. For example,
+ * if CLK_IN is 16MHz,
+ * @code
+ * CLOCK_SetClkinFreq(160000000);
+ * @endcode
+ */
+extern volatile uint32_t g_clkinFreq;
+
+/*! @brief External MCLK IN clock frequency.
+ *
+ * The MCLK IN clock frequency in Hz, when the clock is setup, use the
+ * function CLOCK_SetMclkFreq to set the value in to clock driver. For example,
+ * if MCLK IN is 16MHz,
+ * @code
+ * CLOCK_SetMclkFreq(160000000);
+ * @endcode
+ */
+extern volatile uint32_t g_mclkFreq;
+
+/*! @brief Clock ip name array for MIPI DSI. */
+#define MIPI_DSI_HOST_CLOCKS \
+ { \
+ kCLOCK_MipiDsiCtrl \
+ }
+
+/*! @brief Clock ip name array for LCDIF. */
+#define LCDIF_CLOCKS \
+ { \
+ kCLOCK_DisplayCtrl \
+ }
+
+/*! @brief Clock ip name array for SCT. */
+#define SCT_CLOCKS \
+ { \
+ kCLOCK_Sct \
+ }
+
+/*! @brief Clock ip name array for USBD. */
+#define USBD_CLOCKS \
+ { \
+ kCLOCK_UsbhsDevice \
+ }
+
+/*! @brief Clock ip name array for FlexSPI */
+#define FLEXSPI_CLOCKS \
+ { \
+ kCLOCK_Flexspi0, kCLOCK_Flexspi1 \
+ }
+
+/*! @brief Clock ip name array for Cache64 */
+#define CACHE64_CLOCKS \
+ { \
+ kCLOCK_Flexspi0, kCLOCK_Flexspi1 \
+ }
+
+/*! @brief Clock ip name array for RNG */
+#define TRNG_CLOCKS \
+ { \
+ kCLOCK_Rng \
+ }
+
+/*! @brief Clock ip name array for PUF */
+#define PUF_CLOCKS \
+ { \
+ kCLOCK_Puf \
+ }
+
+/*! @brief Clock ip name array for HashCrypt */
+#define HASHCRYPT_CLOCKS \
+ { \
+ kCLOCK_Hashcrypt \
+ }
+
+/*! @brief Clock ip name array for Casper */
+#define CASPER_CLOCKS \
+ { \
+ kCLOCK_Casper \
+ }
+
+/*! @brief Clock ip name array for Powerquad */
+#define POWERQUAD_CLOCKS \
+ { \
+ kCLOCK_PowerQuad \
+ }
+
+/*! @brief Clock ip name array for ADC. */
+#define LPADC_CLOCKS \
+ { \
+ kCLOCK_Adc0 \
+ }
+
+/*! @brief Clock ip name array for ACMP. */
+#define CMP_CLOCKS \
+ { \
+ kCLOCK_Acmp0 \
+ }
+
+/*! @brief Clock ip name array for uSDHC */
+#define USDHC_CLOCKS \
+ { \
+ kCLOCK_Sdio0, kCLOCK_Sdio1 \
+ }
+
+/*! @brief Clock ip name array for WWDT. */
+#define WWDT_CLOCKS \
+ { \
+ kCLOCK_Wwdt0, kCLOCK_Wwdt1 \
+ }
+
+/*! @brief Clock ip name array for UTICK. */
+#define UTICK_CLOCKS \
+ { \
+ kCLOCK_Utick0 \
+ }
+
+/*! @brief Clock ip name array for FlexIO. */
+#define FLEXIO_CLOCKS \
+ { \
+ kCLOCK_Flexio \
+ }
+
+/*! @brief Clock ip name array for OSTimer */
+#define OSTIMER_CLOCKS \
+ { \
+ kCLOCK_OsEventTimer \
+ }
+
+/*! @brief Clock ip name array for FLEXCOMM. */
+#define FLEXCOMM_CLOCKS \
+ { \
+ kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3, kCLOCK_Flexcomm4, kCLOCK_Flexcomm5, \
+ kCLOCK_Flexcomm6, kCLOCK_Flexcomm7, kCLOCK_Flexcomm8, kCLOCK_Flexcomm9, kCLOCK_Flexcomm10, \
+ kCLOCK_Flexcomm11, kCLOCK_Flexcomm12, kCLOCK_Flexcomm13, kCLOCK_Flexcomm14, kCLOCK_Flexcomm15, \
+ kCLOCK_Flexcomm16 \
+ }
+
+/*! @brief Clock ip name array for LPUART. */
+#define USART_CLOCKS \
+ { \
+ kCLOCK_Usart0, kCLOCK_Usart1, kCLOCK_Usart2, kCLOCK_Usart3, kCLOCK_Usart4, kCLOCK_Usart5, kCLOCK_Usart6, \
+ kCLOCK_Usart7, kCLOCK_Usart8, kCLOCK_Usart9, kCLOCK_Usart10, kCLOCK_Usart11, kCLOCK_Usart12, \
+ kCLOCK_Usart13 \
+ }
+
+/*! @brief Clock ip name array for I2C. */
+#define I2C_CLOCKS \
+ { \
+ kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, kCLOCK_I2c5, kCLOCK_I2c6, kCLOCK_I2c7, \
+ kCLOCK_I2c8, kCLOCK_I2c9, kCLOCK_I2c10, kCLOCK_I2c11, kCLOCK_I2c12, kCLOCK_I2c13, kCLOCK_I2c15 \
+ }
+
+/*! @brief Clock ip name array for SPI. */
+#define SPI_CLOCKS \
+ { \
+ kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2, kCLOCK_Spi3, kCLOCK_Spi4, kCLOCK_Spi5, kCLOCK_Spi6, kCLOCK_Spi7, \
+ kCLOCK_Spi8, kCLOCK_Spi9, kCLOCK_Spi10, kCLOCK_Spi11, kCLOCK_Spi12, kCLOCK_Spi13, kCLOCK_Spi14, \
+ kCLOCK_Spi16 \
+ }
+/*! @brief Clock ip name array for FLEXI2S. */
+#define I2S_CLOCKS \
+ { \
+ kCLOCK_I2s0, kCLOCK_I2s1, kCLOCK_I2s2, kCLOCK_I2s3, kCLOCK_I2s4, kCLOCK_I2s5, kCLOCK_I2s6, kCLOCK_I2s7, \
+ kCLOCK_I2s8, kCLOCK_I2s9, kCLOCK_I2s10, kCLOCK_I2s11, kCLOCK_I2s12, kCLOCK_I2s13 \
+ }
+
+/*! @brief Clock ip name array for DMIC. */
+#define DMIC_CLOCKS \
+ { \
+ kCLOCK_Dmic0 \
+ }
+
+/*! @brief Clock ip name array for SEMA */
+#define SEMA42_CLOCKS \
+ { \
+ kCLOCK_Sema \
+ }
+
+/*! @brief Clock ip name array for MUA */
+#define MU_CLOCKS \
+ { \
+ kCLOCK_Mu \
+ }
+
+/*! @brief Clock ip name array for DMA. */
+#define DMA_CLOCKS \
+ { \
+ kCLOCK_Dmac0, kCLOCK_Dmac1 \
+ }
+
+/*! @brief Clock ip name array for CRC. */
+#define CRC_CLOCKS \
+ { \
+ kCLOCK_Crc \
+ }
+
+/*! @brief Clock ip name array for GPIO. */
+#define GPIO_CLOCKS \
+ { \
+ kCLOCK_HsGpio0, kCLOCK_HsGpio1, kCLOCK_HsGpio2, kCLOCK_HsGpio3, kCLOCK_HsGpio4, kCLOCK_HsGpio5, \
+ kCLOCK_HsGpio6, kCLOCK_HsGpio7 \
+ }
+
+/*! @brief Clock ip name array for PINT. */
+#define PINT_CLOCKS \
+ { \
+ kCLOCK_GpioIntCtl \
+ }
+
+/*! @brief Clock ip name array for I3C. */
+#define I3C_CLOCKS \
+ { \
+ kCLOCK_I3c0, kCLOCK_I3c1 \
+ }
+
+/*! @brief Clock ip name array for MRT. */
+#define MRT_CLOCKS \
+ { \
+ kCLOCK_Mrt0 \
+ }
+
+/*! @brief Clock ip name array for RTC. */
+#define RTC_CLOCKS \
+ { \
+ kCLOCK_Rtc \
+ }
+
+/*! @brief Clock ip name array for CT32B. */
+#define CTIMER_CLOCKS \
+ { \
+ kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
+ }
+
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+/*------------------------------------------------------------------------------
+ clock_ip_name_t definition:
+------------------------------------------------------------------------------*/
+
+#define CLK_GATE_REG_OFFSET_SHIFT 8U
+#define CLK_GATE_REG_OFFSET_MASK 0xFF00U
+#define CLK_GATE_BIT_SHIFT_SHIFT 0U
+#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
+
+#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
+ ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
+ (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
+
+#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
+#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
+
+#define CLK_CTL0_PSCCTL0 0
+#define CLK_CTL0_PSCCTL1 1
+#define CLK_CTL0_PSCCTL2 2
+#define CLK_CTL1_PSCCTL0 3
+#define CLK_CTL1_PSCCTL1 4
+#define CLK_CTL1_PSCCTL2 5
+
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+typedef enum _clock_ip_name
+{
+ kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
+ kCLOCK_Dsp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1), /*!< Clock gate name: Dsp*/
+ kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /*!< Clock gate name: RomCtrlr*/
+ kCLOCK_AxiSwitch = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 3), /*!< Clock gate name: AxiSwitch*/
+ kCLOCK_AxiCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 4), /*!< Clock gate name: AxiCtrl*/
+ kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8), /*!< Clock gate name: PowerQuad*/
+ kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9), /*!< Clock gate name: Casper*/
+ kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10), /*!< Clock gate name: HashCrypt*/
+ kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11), /*!< Clock gate name: Puf*/
+ kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /*!< Clock gate name: Rng*/
+ kCLOCK_Flexspi0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 16), /*!< Clock gate name: Flexspi0*/
+ kCLOCK_OtpCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 17), /*!< Clock gate name: OtpCtrl*/
+ kCLOCK_Flexspi1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 18), /*!< Clock gate name: Flexspi1*/
+ kCLOCK_UsbhsPhy = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 20), /*!< Clock gate name: UsbhsPhy*/
+ kCLOCK_UsbhsDevice = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 21), /*!< Clock gate name: UsbhsDevice*/
+ kCLOCK_UsbhsHost = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 22), /*!< Clock gate name: UsbhsHost*/
+ kCLOCK_UsbhsSram = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 23), /*!< Clock gate name: UsbhsSram*/
+ kCLOCK_Sct = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 24), /*!< Clock gate name: Sct*/
+ kCLOCK_Gpu = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 26), /*!< Clock gate name: Gpu*/
+ kCLOCK_DisplayCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 27), /*!< Clock gate name: DisplayCtrl*/
+ kCLOCK_MipiDsiCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 28), /*!< Clock gate name: MipiDsiCtrl*/
+ kCLOCK_Smartdma = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 30), /*!< Clock gate name: Smartdma*/
+
+ kCLOCK_Sdio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 2), /*!< Clock gate name: Sdio0*/
+ kCLOCK_Sdio1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 3), /*!< Clock gate name: Sdio1*/
+ kCLOCK_Acmp0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 15), /*!< Clock gate name: Acmp0*/
+ kCLOCK_Adc0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 16), /*!< Clock gate name: Adc0*/
+ kCLOCK_ShsGpio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 24), /*!< Clock gate name: ShsGpio0*/
+
+ kCLOCK_Utick0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: Utick0*/
+ kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: Wwdt0*/
+ kCLOCK_Pmc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 29), /*!< Clock gate name: Pmc*/
+
+ kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Flexcomm0*/
+ kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Flexcomm1*/
+ kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Flexcomm2*/
+ kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Flexcomm3*/
+ kCLOCK_Flexcomm4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Flexcomm4*/
+ kCLOCK_Flexcomm5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Flexcomm5*/
+ kCLOCK_Flexcomm6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Flexcomm6*/
+ kCLOCK_Flexcomm7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Flexcomm7*/
+ kCLOCK_Flexcomm8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: Flexcomm8*/
+ kCLOCK_Flexcomm9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 17), /*!< Clock gate name: Flexcomm9*/
+ kCLOCK_Flexcomm10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 18), /*!< Clock gate name: Flexcomm10*/
+ kCLOCK_Flexcomm11 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 19), /*!< Clock gate name: Flexcomm11*/
+ kCLOCK_Flexcomm12 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 20), /*!< Clock gate name: Flexcomm12*/
+ kCLOCK_Flexcomm13 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 21), /*!< Clock gate name: Flexcomm13*/
+ kCLOCK_Flexcomm14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22), /*!< Clock gate name: Flexcomm14*/
+ kCLOCK_Flexcomm15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23), /*!< Clock gate name: Flexcomm15*/
+ kCLOCK_Flexcomm16 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 25), /*!< Clock gate name: Flexcomm16*/
+ kCLOCK_Usart0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Usart0*/
+ kCLOCK_Usart1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Usart1*/
+ kCLOCK_Usart2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Usart2*/
+ kCLOCK_Usart3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Usart3*/
+ kCLOCK_Usart4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Usart4*/
+ kCLOCK_Usart5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Usart5*/
+ kCLOCK_Usart6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Usart6*/
+ kCLOCK_Usart7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Usart7*/
+ kCLOCK_Usart8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: Usart8*/
+ kCLOCK_Usart9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 17), /*!< Clock gate name: Usart9*/
+ kCLOCK_Usart10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 18), /*!< Clock gate name: Usart10*/
+ kCLOCK_Usart11 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 19), /*!< Clock gate name: Usart11*/
+ kCLOCK_Usart12 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 20), /*!< Clock gate name: Usart12*/
+ kCLOCK_Usart13 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 21), /*!< Clock gate name: Usart13*/
+ kCLOCK_I2s0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: I2s0*/
+ kCLOCK_I2s1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: I2s1*/
+ kCLOCK_I2s2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: I2s2*/
+ kCLOCK_I2s3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: I2s3*/
+ kCLOCK_I2s4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: I2s4*/
+ kCLOCK_I2s5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: I2s5*/
+ kCLOCK_I2s6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: I2s6*/
+ kCLOCK_I2s7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: I2s7*/
+ kCLOCK_I2s8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: I2s8*/
+ kCLOCK_I2s9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 17), /*!< Clock gate name: I2s9*/
+ kCLOCK_I2s10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 18), /*!< Clock gate name: I2s10*/
+ kCLOCK_I2s11 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 19), /*!< Clock gate name: I2s11*/
+ kCLOCK_I2s12 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 20), /*!< Clock gate name: I2s12*/
+ kCLOCK_I2s13 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 21), /*!< Clock gate name: I2s13*/
+ kCLOCK_I2c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: I2c0*/
+ kCLOCK_I2c1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: I2c1*/
+ kCLOCK_I2c2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: I2c2*/
+ kCLOCK_I2c3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: I2c3*/
+ kCLOCK_I2c4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: I2c4*/
+ kCLOCK_I2c5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: I2c5*/
+ kCLOCK_I2c6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: I2c6*/
+ kCLOCK_I2c7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: I2c7*/
+ kCLOCK_I2c8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: I2c8*/
+ kCLOCK_I2c9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 17), /*!< Clock gate name: I2c9*/
+ kCLOCK_I2c10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 18), /*!< Clock gate name: I2c10*/
+ kCLOCK_I2c11 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 19), /*!< Clock gate name: I2c11*/
+ kCLOCK_I2c12 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 20), /*!< Clock gate name: I2c12*/
+ kCLOCK_I2c13 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 21), /*!< Clock gate name: I2c13*/
+ kCLOCK_I2c15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23), /*!< Clock gate name: I2c15*/
+ kCLOCK_Spi0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Spi0*/
+ kCLOCK_Spi1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Spi1*/
+ kCLOCK_Spi2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Spi2*/
+ kCLOCK_Spi3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Spi3*/
+ kCLOCK_Spi4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Spi4*/
+ kCLOCK_Spi5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Spi5*/
+ kCLOCK_Spi6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Spi6*/
+ kCLOCK_Spi7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Spi7*/
+ kCLOCK_Spi8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: Spi8*/
+ kCLOCK_Spi9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 17), /*!< Clock gate name: Spi9*/
+ kCLOCK_Spi10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 18), /*!< Clock gate name: Spi10*/
+ kCLOCK_Spi11 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 19), /*!< Clock gate name: Spi11*/
+ kCLOCK_Spi12 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 20), /*!< Clock gate name: Spi12*/
+ kCLOCK_Spi13 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 21), /*!< Clock gate name: Spi13*/
+ kCLOCK_Spi14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22), /*!< Clock gate name: Spi14*/
+ kCLOCK_Spi16 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 25), /*!< Clock gate name: Spi16*/
+ kCLOCK_Dmic0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 24), /*!< Clock gate name: Dmic0*/
+ kCLOCK_OsEventTimer = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 27), /*!< Clock gate name: OsEventTimer*/
+ kCLOCK_Flexio = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 29), /*!< Clock gate name: Flexio*/
+
+ kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0), /*!< Clock gate name: HsGpio0*/
+ kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1), /*!< Clock gate name: HsGpio1*/
+ kCLOCK_HsGpio2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 2), /*!< Clock gate name: HsGpio2*/
+ kCLOCK_HsGpio3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 3), /*!< Clock gate name: HsGpio3*/
+ kCLOCK_HsGpio4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4), /*!< Clock gate name: HsGpio4*/
+ kCLOCK_HsGpio5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5), /*!< Clock gate name: HsGpio5*/
+ kCLOCK_HsGpio6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: HsGpio6*/
+ kCLOCK_HsGpio7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: HsGpio7*/
+ kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16), /*!< Clock gate name: Crc*/
+ kCLOCK_Dmac0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 23), /*!< Clock gate name: Dmac0*/
+ kCLOCK_Dmac1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 24), /*!< Clock gate name: Dmac1*/
+ kCLOCK_Mu = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 28), /*!< Clock gate name: Mu*/
+ kCLOCK_Sema = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 29), /*!< Clock gate name: Sema*/
+ kCLOCK_Freqme = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 31), /*!< Clock gate name: Freqme*/
+
+ kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0), /*!< Clock gate name: Ct32b0*/
+ kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1), /*!< Clock gate name: Ct32b1*/
+ kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2), /*!< Clock gate name: Ct32b2*/
+ kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3), /*!< Clock gate name: Ct32b3*/
+ kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4), /*!< Clock gate name: Ct32b4*/
+ kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7), /*!< Clock gate name: Rtc*/
+ kCLOCK_Mrt0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8), /*!< Clock gate name: Mrt0*/
+ kCLOCK_Wwdt1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 10), /*!< Clock gate name: Wwdt1*/
+ kCLOCK_I3c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 16), /*!< Clock gate name: I3c0*/
+ kCLOCK_I3c1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 17), /*!< Clock gate name: I3c1*/
+ kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 30), /*!< Clock gate name: Pint*/
+ kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 31) /*!< Clock gate name: InputMux. */
+} clock_ip_name_t;
+
+/*! @brief Clock name used to get clock frequency. */
+typedef enum _clock_name
+{
+ kCLOCK_CoreSysClk, /*!< Core clock (aka HCLK) */
+ kCLOCK_BusClk, /*!< Bus clock (AHB/APB clock, aka HCLK) */
+ kCLOCK_MclkClk, /*!< MCLK, to MCLK pin */
+ kCLOCK_ClockOutClk, /*!< CLOCKOUT */
+ kCLOCK_AdcClk, /*!< ADC */
+ kCLOCK_Flexspi0Clk, /*!< FlexSpi0 */
+ kCLOCK_Flexspi1Clk, /*!< FlexSpi1 */
+ kCLOCK_SctClk, /*!< SCT */
+ kCLOCK_Wdt0Clk, /*!< Watchdog0 */
+ kCLOCK_Wdt1Clk, /*!< Watchdog1 */
+ kCLOCK_SystickClk, /*!< Systick */
+ kCLOCK_Sdio0Clk, /*!< SDIO0 */
+ kCLOCK_Sdio1Clk, /*!< SDIO1 */
+ kCLOCK_I3cClk, /*!< I3C0 and I3C1 */
+ kCLOCK_UsbClk, /*!< USB0 */
+ kCLOCK_DmicClk, /*!< Digital Mic clock */
+ kCLOCK_DspCpuClk, /*!< DSP clock */
+ kCLOCK_AcmpClk, /*!< Acmp clock */
+ kCLOCK_Flexcomm0Clk, /*!< Flexcomm0Clock */
+ kCLOCK_Flexcomm1Clk, /*!< Flexcomm1Clock */
+ kCLOCK_Flexcomm2Clk, /*!< Flexcomm2Clock */
+ kCLOCK_Flexcomm3Clk, /*!< Flexcomm3Clock */
+ kCLOCK_Flexcomm4Clk, /*!< Flexcomm4Clock */
+ kCLOCK_Flexcomm5Clk, /*!< Flexcomm5Clock */
+ kCLOCK_Flexcomm6Clk, /*!< Flexcomm6Clock */
+ kCLOCK_Flexcomm7Clk, /*!< Flexcomm7Clock */
+ kCLOCK_Flexcomm8Clk, /*!< Flexcomm8Clock */
+ kCLOCK_Flexcomm9Clk, /*!< Flexcomm9Clock */
+ kCLOCK_Flexcomm10Clk, /*!< Flexcomm10Clock */
+ kCLOCK_Flexcomm11Clk, /*!< Flexcomm11Clock */
+ kCLOCK_Flexcomm12Clk, /*!< Flexcomm12Clock */
+ kCLOCK_Flexcomm13Clk, /*!< Flexcomm13Clock */
+ kCLOCK_Flexcomm14Clk, /*!< Flexcomm14Clock */
+ kCLOCK_Flexcomm15Clk, /*!< Flexcomm15Clock */
+ kCLOCK_Flexcomm16Clk, /*!< Flexcomm16Clock */
+ kCLOCK_FlexioClk, /*!< FlexIO */
+ kCLOCK_GpuClk, /*!< GPU Core */
+ kCLOCK_DcPixelClk, /*!< DCNano Pixel Clock */
+ kCLOCK_MipiDphyClk, /*!< MIPI D-PHY Bit Clock */
+ kCLOCK_MipiDphyEscRxClk, /*!< MIPI D-PHY RX Clock */
+ kCLOCK_MipiDphyEscTxClk, /*!< MIPI D-PHY TX Clock */
+} clock_name_t;
+
+/**
+ * @brief PLL PFD clock name
+ */
+typedef enum _clock_pfd
+{
+ kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
+ kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
+ kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
+ kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
+} clock_pfd_t;
+
+/*! @brief Clock Mux Switches
+ * The encoding is as follows each connection identified is 32bits wide
+ * starting from LSB upwards
+ *
+ * [ 31 30 29:28 27:25 24:14 13:11 10:0 ]
+ * [CLKCTL index]:[FRODIVSEL onoff]:[FRODIVSEL]:[MUXB choice]:[MUXB offset]:[MUXA choice]:[MUXA offset]
+ * FRODIVSEL onoff '1' means need to set FRODIVSEL. MUX offset 0 means end of descriptor.
+ */
+/* CLKCTL0 SEL */
+#define SYSPLL0CLKSEL_OFFSET 0x200
+#define MAINCLKSELA_OFFSET 0x430
+#define MAINCLKSELB_OFFSET 0x434
+#define FLEXSPI0FCLKSEL_OFFSET 0x620
+#define FLEXSPI1FCLKSEL_OFFSET 0x630
+#define SCTFCLKSEL_OFFSET 0x640
+#define USBHSFCLKSEL_OFFSET 0x660
+#define SDIO0FCLKSEL_OFFSET 0x680
+#define SDIO1FCLKSEL_OFFSET 0x690
+#define ADC0FCLKSEL0_OFFSET 0x6D0
+#define ADC0FCLKSEL1_OFFSET 0x6D4
+#define UTICKFCLKSEL_OFFSET 0x700
+#define WDT0FCLKSEL_OFFSET 0x720
+#define A32KHZWAKECLKSEL_OFFSET 0x730
+#define SYSTICKFCLKSEL_OFFSET 0x760
+#define DPHYCLKSEL_OFFSET 0x770
+#define DPHYESCCLKSEL_OFFSET 0x778
+#define GPUCLKSEL_OFFSET 0x790
+#define DCPIXELCLKSEL_OFFSET 0x7A0
+/* CLKCTL1 SEL */
+#define AUDIOPLL0CLKSEL_OFFSET 0x200
+#define DSPCPUCLKSELA_OFFSET 0x430
+#define DSPCPUCLKSELB_OFFSET 0x434
+#define OSEVENTTFCLKSEL_OFFSET 0x480
+#define FC0FCLKSEL_OFFSET 0x508
+#define FC1FCLKSEL_OFFSET 0x528
+#define FC2FCLKSEL_OFFSET 0x548
+#define FC3FCLKSEL_OFFSET 0x568
+#define FC4FCLKSEL_OFFSET 0x588
+#define FC5FCLKSEL_OFFSET 0x5A8
+#define FC6FCLKSEL_OFFSET 0x5C8
+#define FC7FCLKSEL_OFFSET 0x5E8
+#define FC8FCLKSEL_OFFSET 0x608
+#define FC9FCLKSEL_OFFSET 0x628
+#define FC10FCLKSEL_OFFSET 0x648
+#define FC11FCLKSEL_OFFSET 0x668
+#define FC12FCLKSEL_OFFSET 0x688
+#define FC13FCLKSEL_OFFSET 0x6A8
+#define FC14FCLKSEL_OFFSET 0x6C8
+#define FC15FCLKSEL_OFFSET 0x6E8
+#define FC16FCLKSEL_OFFSET 0x708
+#define FLEXIOCLKSEL_OFFSET 0x728
+#define DMIC0FCLKSEL_OFFSET 0x780
+#define CT32BIT0FCLKSEL_OFFSET 0x7A0
+#define CT32BIT1FCLKSEL_OFFSET 0x7A4
+#define CT32BIT2FCLKSEL_OFFSET 0x7A8
+#define CT32BIT3FCLKSEL_OFFSET 0x7AC
+#define CT32BIT4FCLKSEL_OFFSET 0x7B0
+#define AUDIOMCLKSEL_OFFSET 0x7C0
+#define CLKOUTSEL0_OFFSET 0x7E0
+#define CLKOUTSEL1_OFFSET 0x7E4
+#define I3C01FCLKSEL_OFFSET 0x800
+#define I3C01FCLKSTCSEL_OFFSET 0x804
+#define I3C01FCLKSTSTCLKSEL_OFFSET 0x814
+#define WDT1FCLKSEL_OFFSET 0x820
+#define ACMP0FCLKSEL_OFFSET 0x830
+/* CLKCTL0 DIV */
+#define LOWFREQCLKDIV_OFFSET 0x130
+#define MAINPLLCLKDIV_OFFSET 0x240
+#define DSPPLLCLKDIV_OFFSET 0x244
+#define AUX0PLLCLKDIV_OFFSET 0x248
+#define AUX1PLLCLKDIV_OFFSET 0x24C
+#define SYSCPUAHBCLKDIV_OFFSET 0x400
+#define PFC0CLKDIV_OFFSET 0x500
+#define PFC1CLKDIV_OFFSET 0x504
+#define FLEXSPI0FCLKDIV_OFFSET 0x624
+#define FLEXSPI1FCLKDIV_OFFSET 0x634
+#define SCTFCLKDIV_OFFSET 0x644
+#define USBHSFCLKDIV_OFFSET 0x664
+#define SDIO0FCLKDIV_OFFSET 0x684
+#define SDIO1FCLKDIV_OFFSET 0x694
+#define ADC0FCLKDIV_OFFSET 0x6D8
+#define A32KHZWAKECLKDIV_OFFSET 0x734
+#define SYSTICKFCLKDIV_OFFSET 0x764
+#define DPHYCLKDIV_OFFSET 0x774
+#define DPHYESCRXCLKDIV_OFFSET 0x77C
+#define DPHYESCTXCLKDIV_OFFSET 0x780
+#define GPUCLKDIV_OFFSET 0x794
+#define DCPIXELCLKDIV_OFFSET 0x7A4
+/* CLKCTL1 DIV */
+#define AUDIOPLLCLKDIV_OFFSET 0x240
+#define DSPCPUCLKDIV_OFFSET 0x400
+#define FLEXIOCLKDIV_OFFSET 0x740
+#define FRGPLLCLKDIV_OFFSET 0x760
+#define DMIC0FCLKDIV_OFFSET 0x784
+#define AUDIOMCLKDIV_OFFSET 0x7C4
+#define CLKOUTFCLKDIV_OFFSET 0x7E8
+#define I3C01FCLKSTCDIV_OFFSET 0x808
+#define I3C01FCLKSDIV_OFFSET 0x80C
+#define I3C01FCLKDIV_OFFSET 0x810
+#define ACMP0FCLKDIV_OFFSET 0x834
+
+#define CLKCTL0_TUPLE_MUXA(reg, choice) ((((reg) >> 2U) & 0x7FFU) | (((choice)&0x7U) << 11U))
+#define CLKCTL0_TUPLE_MUXB(reg, choice) (((((reg) >> 2U) & 0x7FFU) << 14U) | (((choice)&0x7U) << 25U))
+#define CLKCTL1_TUPLE_MUXA(reg, choice) (0x80000000U | ((((reg) >> 2U) & 0x7FFU) | (((choice)&0x7U) << 11U)))
+#define CLKCTL1_TUPLE_MUXB(reg, choice) (0x80000000U | (((((reg) >> 2U) & 0x7FFU) << 14U) | (((choice)&0x7U) << 25U)))
+#define CLKCTL_TUPLE_FRODIVSEL(choice) (0x40000000U | (((choice)&0x7U) << 28U))
+#define CLKCTL_TUPLE_REG(base, tuple) ((volatile uint32_t *)(((uint32_t)(base)) + (((uint32_t)(tuple)&0x7FFU) << 2U)))
+#define CLKCTL_TUPLE_SEL(tuple) (((uint32_t)(tuple) >> 11U) & 0x7U)
+
+/*!
+ * @brief The enumerator of clock attach Id.
+ */
+typedef enum _clock_attach_id
+{
+ kFRO_DIV8_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 0), /*!< Attach FRO_DIV8 to SYS_PLL. */
+ kOSC_CLK_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 1), /*!< Attach OSC_CLK to SYS_PLL. */
+ kNONE_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 7), /*!< Attach NONE to SYS_PLL. */
+
+ kFRO_DIV8_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 0), /*!< Attach FRO_DIV8 to AUDIO_PLL. */
+ kOSC_CLK_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 1), /*!< Attach OSC_CLK to AUDIO_PLL. */
+ kNONE_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 7), /*!< Attach NONE to AUDIO_PLL. */
+
+ kLPOSC_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 0) |
+ CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach LPOSC to MAIN_CLK. */
+ kFRO_DIV2_to_MAIN_CLK = CLKCTL_TUPLE_FRODIVSEL(0) | CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 1) |
+ CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach Fro_DIV2 to MAIN_CLK. */
+ kFRO_DIV4_to_MAIN_CLK = CLKCTL_TUPLE_FRODIVSEL(1) | CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 1) |
+ CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach Fro_DIV4 to MAIN_CLK. */
+ kFRO_DIV8_to_MAIN_CLK = CLKCTL_TUPLE_FRODIVSEL(2) | CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 1) |
+ CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach Fro_DIV8 to MAIN_CLK. */
+ kFRO_DIV16_to_MAIN_CLK = CLKCTL_TUPLE_FRODIVSEL(3) | CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 1) |
+ CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach Fro_DIV16 to MAIN_CLK. */
+ kOSC_CLK_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 2) |
+ CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach OSC_CLK to MAIN_CLK. */
+ kFRO_DIV1_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 3) |
+ CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach FRO_DIV1 to MAIN_CLK. */
+ kMAIN_PLL_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 1), /*!< Attach MAIN_PLL to MAIN_CLK. */
+ kOSC32K_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 2), /*!< Attach OSC32K to MAIN_CLK. */
+
+ kFRO_DIV1_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 0) |
+ CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0), /*!< Attach Fro_DIV1 to DSP_MAIN_CLK. */
+ kOSC_CLK_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 1) |
+ CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0), /*!< Attach OSC_CLK to DSP_MAIN_CLK. */
+ kLPOSC_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 2) |
+ CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0), /*!< Attach LPOSC to DSP_MAIN_CLK. */
+ kMAIN_PLL_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 1), /*!< Attach MAIN_PLL to DSP_MAIN_CLK. */
+ kDSP_PLL_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 2), /*!< Attach DSP_PLL to DSP_MAIN_CLK. */
+ kOSC32K_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 3), /*!< Attach OSC32K to DSP_MAIN_CLK. */
+
+ kLPOSC_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(UTICKFCLKSEL_OFFSET, 0), /*!< Attach LPOSC to UTICK_CLK. */
+ kNONE_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(UTICKFCLKSEL_OFFSET, 7), /*!< Attach NONE to UTICK_CLK. */
+
+ kLPOSC_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(WDT0FCLKSEL_OFFSET, 0), /*!< Attach LPOSC to WDT0_CLK. */
+ kNONE_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(WDT0FCLKSEL_OFFSET, 7), /*!< Attach NONE to WDT0_CLK. */
+
+ kLPOSC_to_WDT1_CLK = CLKCTL1_TUPLE_MUXA(WDT1FCLKSEL_OFFSET, 0), /*!< Attach LPOSC to WDT1_CLK. */
+ kNONE_to_WDT1_CLK = CLKCTL1_TUPLE_MUXA(WDT1FCLKSEL_OFFSET, 7), /*!< Attach NONE to WDT1_CLK. */
+
+ kOSC32K_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(A32KHZWAKECLKSEL_OFFSET, 0), /*!< Attach OSC32K to 32KHZWAKE_CLK. */
+ kLPOSC_DIV32_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(A32KHZWAKECLKSEL_OFFSET, 1), /*!< Attach LPOSC_DIV32
+ to 32KHZWAKE_CLK. */
+ kNONE_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(A32KHZWAKECLKSEL_OFFSET, 7), /*!< Attach NONE to 32KHZWAKE_CLK. */
+
+ kMAIN_CLK_DIV_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK_DIV
+ to SYSTICK_CLK. */
+ kLPOSC_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 1), /*!< Attach LPOSC to SYSTICK_CLK. */
+ kOSC32K_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 2), /*!< Attach OSC32K to SYSTICK_CLK. */
+ kNONE_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 7), /*!< Attach NONE to SYSTICK_CLK. */
+
+ kMAIN_CLK_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to SDIO0_CLK. */
+ kMAIN_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to SDIO0_CLK. */
+ kAUX0_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to SDIO0_CLK. */
+ kFRO_DIV2_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 3), /*!< Attach FRO_DIV2 to SDIO0_CLK. */
+ kAUX1_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to SDIO0_CLK. */
+ kNONE_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 7), /*!< Attach NONE to SDIO0_CLK. */
+
+ kMAIN_CLK_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to SDIO1_CLK. */
+ kMAIN_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to SDIO1_CLK. */
+ kAUX0_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to SDIO1_CLK. */
+ kFRO_DIV2_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 3), /*!< Attach FRO_DIV2 to SDIO1_CLK. */
+ kAUX1_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to SDIO1_CLK. */
+ kNONE_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 7), /*!< Attach NONE to SDIO1_CLK. */
+
+ kMAIN_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to CTIMER0. */
+ kFRO_DIV1_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV1 to CTIMER0. */
+ kAUDIO_PLL_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to CTIMER0. */
+ kMASTER_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to CTIMER0. */
+ k32K_WAKE_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 4), /*!< Attach 32K_WAKE_CLK to CTIMER0. */
+ kNONE_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 7), /*!< Attach NONE to CTIMER0. */
+
+ kMAIN_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to CTIMER1. */
+ kFRO_DIV1_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV1 to CTIMER1. */
+ kAUDIO_PLL_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to CTIMER1. */
+ kMASTER_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to CTIMER1. */
+ k32K_WAKE_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 4), /*!< Attach 32K_WAKE_CLK to CTIMER1. */
+ kNONE_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 7), /*!< Attach NONE to CTIMER1. */
+
+ kMAIN_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to CTIMER2. */
+ kFRO_DIV1_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV1 to CTIMER2. */
+ kAUDIO_PLL_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to CTIMER2. */
+ kMASTER_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to CTIMER2. */
+ k32K_WAKE_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 4), /*!< Attach 32K_WAKE_CLK to CTIMER2. */
+ kNONE_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 7), /*!< Attach NONE to CTIMER2. */
+
+ kMAIN_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to CTIMER3. */
+ kFRO_DIV1_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV1 to CTIMER3. */
+ kAUDIO_PLL_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to CTIMER3. */
+ kMASTER_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to CTIMER3. */
+ k32K_WAKE_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 4), /*!< Attach 32K_WAKE_CLK to CTIMER3. */
+ kNONE_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 7), /*!< Attach NONE to CTIMER3. */
+
+ kMAIN_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to CTIMER4. */
+ kFRO_DIV1_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV1 to CTIMER4. */
+ kAUDIO_PLL_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to CTIMER4. */
+ kMASTER_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to CTIMER4. */
+ k32K_WAKE_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 4), /*!< Attach 32K_WAKE_CLK to CTIMER4. */
+ kNONE_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 7), /*!< Attach NONE to CTIMER4. */
+
+ kMAIN_CLK_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to FLEXSPI0_CLK. */
+ kMAIN_PLL_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to FLEXSPI0_CLK. */
+ kAUX0_PLL_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to FLEXSPI0_CLK. */
+ kFRO_DIV1_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 3), /*!< Attach FRO_DIV1 to FLEXSPI0_CLK. */
+ kAUX1_PLL_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to FLEXSPI0_CLK. */
+ kFRO_DIV4_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 5), /*!< Attach FRO_DIV4 to FLEXSPI0_CLK. */
+ kFRO_DIV8_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 6), /*!< Attach FRO_DIV8 to FLEXSPI0_CLK. */
+ kNONE_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXSPI0_CLK. */
+
+ kMAIN_CLK_to_FLEXSPI1_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI1FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to FLEXSPI1_CLK. */
+ kMAIN_PLL_to_FLEXSPI1_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI1FCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to FLEXSPI1_CLK. */
+ kAUX0_PLL_to_FLEXSPI1_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI1FCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to FLEXSPI1_CLK. */
+ kFRO_DIV1_to_FLEXSPI1_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI1FCLKSEL_OFFSET, 3), /*!< Attach FRO_DIV1 to FLEXSPI1_CLK. */
+ kAUX1_PLL_to_FLEXSPI1_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI1FCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to FLEXSPI1_CLK. */
+ kNONE_to_FLEXSPI1_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI1FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXSPI1_CLK. */
+
+ kOSC_CLK_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 0), /*!< Attach OSC_CLK to USB_CLK. */
+ kMAIN_CLK_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 1), /*!< Attach MAIN_CLK to USB_CLK. */
+ kAUX0_PLL_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 3), /*!< Attach AUX0_PLL to USB_CLK. */
+ kNONE_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 7), /*!< Attach NONE to USB_CLK. */
+
+ kMAIN_CLK_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to SCT_CLK. */
+ kMAIN_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to SCT_CLK. */
+ kAUX0_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to SCT_CLK. */
+ kFRO_DIV1_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 3), /*!< Attach FRO_DIV1 to SCT_CLK. */
+ kAUX1_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to SCT_CLK. */
+ kAUDIO_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 5), /*!< Attach AUDIO_PLL to SCT_CLK. */
+ kNONE_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 7), /*!< Attach NONE to SCT_CLK. */
+
+ kLPOSC_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTTFCLKSEL_OFFSET, 0), /*!< Attach LPOSC to OSTIMER_CLK. */
+ kOSC32K_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTTFCLKSEL_OFFSET, 1), /*!< Attach OSC32K to OSTIMER_CLK. */
+ kHCLK_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTTFCLKSEL_OFFSET, 2), /*!< Attach HCLK to OSTIMER_CLK. */
+ kNONE_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTTFCLKSEL_OFFSET, 7), /*!< Attach NONE to OSTIMER_CLK. */
+
+ kFRO_DIV8_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV8 to MCLK_CLK. */
+ kAUDIO_PLL_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to MCLK_CLK. */
+ kNONE_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 7), /*!< Attach NONE to MCLK_CLK. */
+
+ kFRO_DIV4_to_DMIC = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to DMIC. */
+ kAUDIO_PLL_to_DMIC = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to DMIC. */
+ kMASTER_CLK_to_DMIC = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to DMIC. */
+ kLPOSC_to_DMIC = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 3), /*!< Attach LPOSC to DMIC. */
+ k32K_WAKE_CLK_to_DMIC = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 4), /*!< Attach 32K_WAKE_CLK to DMIC. */
+ kNONE_to_DMIC = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 7), /*!< Attach NONE to DMIC. */
+
+ kFRO_DIV4_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM0. */
+ kAUDIO_PLL_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM0. */
+ kMASTER_CLK_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM0. */
+ kFRG_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM0. */
+ kNONE_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM0. */
+
+ kFRO_DIV4_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM1. */
+ kAUDIO_PLL_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM1. */
+ kMASTER_CLK_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM1. */
+ kFRG_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM1. */
+ kNONE_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM1. */
+
+ kFRO_DIV4_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM2. */
+ kAUDIO_PLL_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM2. */
+ kMASTER_CLK_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM2. */
+ kFRG_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM2. */
+ kNONE_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM2. */
+
+ kFRO_DIV4_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM3. */
+ kAUDIO_PLL_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM3. */
+ kMASTER_CLK_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM3. */
+ kFRG_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM3. */
+ kNONE_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM3. */
+
+ kFRO_DIV4_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM4. */
+ kAUDIO_PLL_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM4. */
+ kMASTER_CLK_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM4. */
+ kFRG_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM4. */
+ kNONE_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM4. */
+
+ kFRO_DIV4_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM5. */
+ kAUDIO_PLL_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM5. */
+ kMASTER_CLK_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM5. */
+ kFRG_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM5. */
+ kNONE_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM5. */
+
+ kFRO_DIV4_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM6. */
+ kAUDIO_PLL_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM6. */
+ kMASTER_CLK_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM6. */
+ kFRG_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM6. */
+ kNONE_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM6. */
+
+ kFRO_DIV4_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM7. */
+ kAUDIO_PLL_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM7. */
+ kMASTER_CLK_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM7. */
+ kFRG_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM7. */
+ kNONE_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM7. */
+
+ kFRO_DIV4_to_FLEXCOMM8 = CLKCTL1_TUPLE_MUXA(FC8FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM8. */
+ kAUDIO_PLL_to_FLEXCOMM8 = CLKCTL1_TUPLE_MUXA(FC8FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM8. */
+ kMASTER_CLK_to_FLEXCOMM8 = CLKCTL1_TUPLE_MUXA(FC8FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM8. */
+ kFRG_to_FLEXCOMM8 = CLKCTL1_TUPLE_MUXA(FC8FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM8. */
+ kNONE_to_FLEXCOMM8 = CLKCTL1_TUPLE_MUXA(FC8FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM8. */
+
+ kFRO_DIV4_to_FLEXCOMM9 = CLKCTL1_TUPLE_MUXA(FC9FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM9. */
+ kAUDIO_PLL_to_FLEXCOMM9 = CLKCTL1_TUPLE_MUXA(FC9FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM9. */
+ kMASTER_CLK_to_FLEXCOMM9 = CLKCTL1_TUPLE_MUXA(FC9FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM9. */
+ kFRG_to_FLEXCOMM9 = CLKCTL1_TUPLE_MUXA(FC9FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM9. */
+ kNONE_to_FLEXCOMM9 = CLKCTL1_TUPLE_MUXA(FC9FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM9. */
+
+ kFRO_DIV4_to_FLEXCOMM10 = CLKCTL1_TUPLE_MUXA(FC10FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM10. */
+ kAUDIO_PLL_to_FLEXCOMM10 = CLKCTL1_TUPLE_MUXA(FC10FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM10. */
+ kMASTER_CLK_to_FLEXCOMM10 = CLKCTL1_TUPLE_MUXA(FC10FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM10. */
+ kFRG_to_FLEXCOMM10 = CLKCTL1_TUPLE_MUXA(FC10FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM10. */
+ kNONE_to_FLEXCOMM10 = CLKCTL1_TUPLE_MUXA(FC10FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM10. */
+
+ kFRO_DIV4_to_FLEXCOMM11 = CLKCTL1_TUPLE_MUXA(FC11FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM11. */
+ kAUDIO_PLL_to_FLEXCOMM11 = CLKCTL1_TUPLE_MUXA(FC11FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM11. */
+ kMASTER_CLK_to_FLEXCOMM11 = CLKCTL1_TUPLE_MUXA(FC11FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM11. */
+ kFRG_to_FLEXCOMM11 = CLKCTL1_TUPLE_MUXA(FC11FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM11. */
+ kNONE_to_FLEXCOMM11 = CLKCTL1_TUPLE_MUXA(FC11FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM11. */
+
+ kFRO_DIV4_to_FLEXCOMM12 = CLKCTL1_TUPLE_MUXA(FC12FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM12. */
+ kAUDIO_PLL_to_FLEXCOMM12 = CLKCTL1_TUPLE_MUXA(FC12FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM12. */
+ kMASTER_CLK_to_FLEXCOMM12 = CLKCTL1_TUPLE_MUXA(FC12FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM12. */
+ kFRG_to_FLEXCOMM12 = CLKCTL1_TUPLE_MUXA(FC12FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM12. */
+ kNONE_to_FLEXCOMM12 = CLKCTL1_TUPLE_MUXA(FC12FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM12. */
+
+ kFRO_DIV4_to_FLEXCOMM13 = CLKCTL1_TUPLE_MUXA(FC13FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM13. */
+ kAUDIO_PLL_to_FLEXCOMM13 = CLKCTL1_TUPLE_MUXA(FC13FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM13. */
+ kMASTER_CLK_to_FLEXCOMM13 = CLKCTL1_TUPLE_MUXA(FC13FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM13. */
+ kFRG_to_FLEXCOMM13 = CLKCTL1_TUPLE_MUXA(FC13FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM13. */
+ kNONE_to_FLEXCOMM13 = CLKCTL1_TUPLE_MUXA(FC13FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM13. */
+
+ kFRO_DIV4_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM14. */
+ kAUDIO_PLL_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM14. */
+ kMASTER_CLK_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM14. */
+ kFRG_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM14. */
+ kNONE_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM14. */
+
+ kFRO_DIV4_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM15. */
+ kAUDIO_PLL_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM15. */
+ kMASTER_CLK_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM15. */
+ kFRG_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM15. */
+ kNONE_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM15. */
+
+ kFRO_DIV4_to_FLEXCOMM16 = CLKCTL1_TUPLE_MUXA(FC16FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM16. */
+ kAUDIO_PLL_to_FLEXCOMM16 = CLKCTL1_TUPLE_MUXA(FC16FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM16. */
+ kMASTER_CLK_to_FLEXCOMM16 = CLKCTL1_TUPLE_MUXA(FC16FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM16. */
+ kFRG_to_FLEXCOMM16 = CLKCTL1_TUPLE_MUXA(FC16FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM16. */
+ kNONE_to_FLEXCOMM16 = CLKCTL1_TUPLE_MUXA(FC16FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM16. */
+
+ kFRO_DIV2_to_FLEXIO = CLKCTL1_TUPLE_MUXA(FLEXIOCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV2 to FLEXIO. */
+ kAUDIO_PLL_to_FLEXIO = CLKCTL1_TUPLE_MUXA(FLEXIOCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXIO. */
+ kMASTER_CLK_to_FLEXIO = CLKCTL1_TUPLE_MUXA(FLEXIOCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXIO. */
+ kFRG_to_FLEXIO = CLKCTL1_TUPLE_MUXA(FLEXIOCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXIO. */
+ kNONE_to_FLEXIO = CLKCTL1_TUPLE_MUXA(FLEXIOCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXIO. */
+
+ kMAIN_CLK_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C01FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to I3C_CLK. */
+ kFRO_DIV8_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C01FCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV8 to I3C_CLK. */
+ kNONE_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C01FCLKSEL_OFFSET, 7), /*!< Attach NONE to I3C_CLK. */
+
+ kI3C_CLK_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C01FCLKSTCSEL_OFFSET, 0), /*!< Attach I3C_CLK to I3C_TC_CLK. */
+ kLPOSC_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C01FCLKSTCSEL_OFFSET, 1), /*!< Attach LPOSC to I3C_TC_CLK. */
+ kNONE_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C01FCLKSTCSEL_OFFSET, 7), /*!< Attach NONE to I3C_TC_CLK. */
+
+ kMAIN_CLK_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to ACMP_CLK. */
+ kFRO_DIV4_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV4 to ACMP_CLK. */
+ kAUX0_PLL_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to ACMP_CLK. */
+ kAUX1_PLL_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 3), /*!< Attach AUX1_PLL to ACMP_CLK. */
+ kNONE_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 7), /*!< Attach NONE to ACMP_CLK. */
+
+ kOSC_CLK_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 0) |
+ CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0), /*!< Attach OSC_CLK to ADC_CLK. */
+ kLPOSC_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 1) |
+ CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0), /*!< Attach LPOSC to ADC_CLK. */
+ kFRO_DIV4_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 2) |
+ CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0), /*!< Attach FRO_DIV4 to ADC_CLK. */
+ kMAIN_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 1), /*!< Attach MAIN_PLL to ADC_CLK. */
+ kAUX0_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 2), /*!< Attach AUX0_PLL to ADC_CLK. */
+ kAUX1_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 3), /*!< Attach AUX1_PLL to ADC_CLK. */
+
+ kOSC_CLK_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 0) |
+ CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach OSC_CLK to CLKOUT. */
+ kLPOSC_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 1) |
+ CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach LPOSC to CLKOUT. */
+ kFRO_DIV2_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 2) |
+ CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach FRO_DIV2 to CLKOUT. */
+ kMAIN_CLK_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 3) |
+ CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach MAIN_CLK to CLKOUT. */
+ kDSP_MAIN_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 4) |
+ CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach DSP_MAIN to CLKOUT. */
+ kMAIN_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 1), /*!< Attach MAIN_PLL to CLKOUT. */
+ kAUX0_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 2), /*!< Attach AUX0_PLL to CLKOUT. */
+ kDSP_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 3), /*!< Attach DSP_PLL to CLKOUT. */
+ kAUX1_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 4), /*!< Attach AUX1_PLL to CLKOUT. */
+ kAUDIO_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 5), /*!< Attach AUDIO_PLL to CLKOUT. */
+ kOSC32K_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 6), /*!< Attach OSC32K to CLKOUT. */
+ kNONE_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 7), /*!< Attach NONE to CLKOUT. */
+
+ kMAIN_CLK_to_GPU_CLK = CLKCTL0_TUPLE_MUXA(GPUCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to GPU_CLK. */
+ kFRO_DIV1_to_GPU_CLK = CLKCTL0_TUPLE_MUXA(GPUCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV1 to GPU_CLK. */
+ kMAIN_PLL_to_GPU_CLK = CLKCTL0_TUPLE_MUXA(GPUCLKSEL_OFFSET, 2), /*!< Attach MAIN_PLL to GPU_CLK. */
+ kAUX0_PLL_to_GPU_CLK = CLKCTL0_TUPLE_MUXA(GPUCLKSEL_OFFSET, 3), /*!< Attach AUX0_PLL to GPU_CLK. */
+ kAUX1_PLL_to_GPU_CLK = CLKCTL0_TUPLE_MUXA(GPUCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to GPU_CLK. */
+ kNONE_to_GPU_CLK = CLKCTL0_TUPLE_MUXA(GPUCLKSEL_OFFSET, 7), /*!< Attach NONE to GPU_CLK. */
+
+ kFRO_DIV1_to_MIPI_DPHY_CLK = CLKCTL0_TUPLE_MUXA(DPHYCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV1 to MIPI_DPHY_CLK. */
+ kMAIN_PLL_to_MIPI_DPHY_CLK = CLKCTL0_TUPLE_MUXA(DPHYCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to MIPI_DPHY_CLK. */
+ kAUX0_PLL_to_MIPI_DPHY_CLK = CLKCTL0_TUPLE_MUXA(DPHYCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to MIPI_DPHY_CLK. */
+ kAUX1_PLL_to_MIPI_DPHY_CLK = CLKCTL0_TUPLE_MUXA(DPHYCLKSEL_OFFSET, 3), /*!< Attach AUX1_PLL to MIPI_DPHY_CLK. */
+ kNONE_to_MIPI_DPHY_CLK = CLKCTL0_TUPLE_MUXA(DPHYCLKSEL_OFFSET, 7), /*!< Attach NONE to MIPI_DPHY_CLK. */
+
+ kFRO_DIV1_to_MIPI_DPHYESC_CLK = CLKCTL0_TUPLE_MUXA(DPHYESCCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV1
+ to MIPI_DPHYESC_CLK. */
+ kFRO_DIV16_to_MIPI_DPHYESC_CLK = CLKCTL0_TUPLE_MUXA(DPHYESCCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV16
+ to MIPI_DPHYESC_CLK. */
+ kAUX0_PLL_to_MIPI_DPHYESC_CLK = CLKCTL0_TUPLE_MUXA(DPHYESCCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL
+ to MIPI_DPHYESC_CLK. */
+ kAUX1_PLL_to_MIPI_DPHYESC_CLK = CLKCTL0_TUPLE_MUXA(DPHYESCCLKSEL_OFFSET, 3), /*!< Attach AUX1_PLL
+ to MIPI_DPHYESC_CLK. */
+
+ kMIPI_DPHY_CLK_to_DCPIXEL_CLK = CLKCTL0_TUPLE_MUXA(DCPIXELCLKSEL_OFFSET, 0), /*!< Attach MIPI_DPHY_CLK
+ to DCPIXEL_CLK. */
+ kMAIN_CLK_to_DCPIXEL_CLK = CLKCTL0_TUPLE_MUXA(DCPIXELCLKSEL_OFFSET, 1), /*!< Attach MAIN_CLK to DCPIXEL_CLK. */
+ kFRO_DIV1_to_DCPIXEL_CLK = CLKCTL0_TUPLE_MUXA(DCPIXELCLKSEL_OFFSET, 2), /*!< Attach FRO_DIV1 to DCPIXEL_CLK. */
+ kMAIN_PLL_to_DCPIXEL_CLK = CLKCTL0_TUPLE_MUXA(DCPIXELCLKSEL_OFFSET, 3), /*!< Attach MAIN_PLL to DCPIXEL_CLK. */
+ kAUX0_PLL_to_DCPIXEL_CLK = CLKCTL0_TUPLE_MUXA(DCPIXELCLKSEL_OFFSET, 4), /*!< Attach AUX0_PLL to DCPIXEL_CLK. */
+ kAUX1_PLL_to_DCPIXEL_CLK = CLKCTL0_TUPLE_MUXA(DCPIXELCLKSEL_OFFSET, 5), /*!< Attach AUX1_PLL to DCPIXEL_CLK. */
+ kNONE_to_DCPIXEL_CLK = CLKCTL0_TUPLE_MUXA(DCPIXELCLKSEL_OFFSET, 7), /*!< Attach NONE to DCPIXEL_CLK. */
+} clock_attach_id_t;
+
+/*! @brief Clock dividers */
+typedef enum _clock_div_name
+{
+ kCLOCK_DivAudioPllClk = CLKCTL1_TUPLE_MUXA(AUDIOPLLCLKDIV_OFFSET, 0), /*!< Audio Pll Clk Divider. */
+ kCLOCK_DivMainPllClk = CLKCTL0_TUPLE_MUXA(MAINPLLCLKDIV_OFFSET, 0), /*!< Main Pll Clk Divider. */
+ kCLOCK_DivDspPllClk = CLKCTL0_TUPLE_MUXA(DSPPLLCLKDIV_OFFSET, 0), /*!< Dsp Pll Clk Divider. */
+ kCLOCK_DivAux0PllClk = CLKCTL0_TUPLE_MUXA(AUX0PLLCLKDIV_OFFSET, 0), /*!< Aux0 Pll Clk Divider. */
+ kCLOCK_DivAux1PllClk = CLKCTL0_TUPLE_MUXA(AUX1PLLCLKDIV_OFFSET, 0), /*!< Aux1 Pll Clk Divider. */
+ kCLOCK_DivPfc0Clk = CLKCTL0_TUPLE_MUXA(PFC0CLKDIV_OFFSET, 0), /*!< Pfc0 Clk Divider. */
+ kCLOCK_DivPfc1Clk = CLKCTL0_TUPLE_MUXA(PFC1CLKDIV_OFFSET, 0), /*!< Pfc1 Clk Divider. */
+ kCLOCK_DivSysCpuAhbClk = CLKCTL0_TUPLE_MUXA(SYSCPUAHBCLKDIV_OFFSET, 0), /*!< Sys Cpu Ahb Clk Divider. */
+ kCLOCK_Div32KhzWakeClk = CLKCTL0_TUPLE_MUXA(A32KHZWAKECLKDIV_OFFSET, 0), /*!< Khz Wake Clk Divider. */
+ kCLOCK_DivSystickClk = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKDIV_OFFSET, 0), /*!< Systick Clk Divider. */
+ kCLOCK_DivSdio0Clk = CLKCTL0_TUPLE_MUXA(SDIO0FCLKDIV_OFFSET, 0), /*!< Sdio0 Clk Divider. */
+ kCLOCK_DivSdio1Clk = CLKCTL0_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0), /*!< Sdio1 Clk Divider. */
+ kCLOCK_DivFlexspi0Clk = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKDIV_OFFSET, 0), /*!< Flexspi0 Clk Divider. */
+ kCLOCK_DivFlexspi1Clk = CLKCTL0_TUPLE_MUXA(FLEXSPI1FCLKDIV_OFFSET, 0), /*!< Flexspi1 Clk Divider. */
+ kCLOCK_DivUsbHsFclk = CLKCTL0_TUPLE_MUXA(USBHSFCLKDIV_OFFSET, 0), /*!< Usb Hs Fclk Divider. */
+ kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0), /*!< Sct Clk Divider. */
+ kCLOCK_DivMclkClk = CLKCTL1_TUPLE_MUXA(AUDIOMCLKDIV_OFFSET, 0), /*!< Mclk Clk Divider. */
+ kCLOCK_DivDmicClk = CLKCTL1_TUPLE_MUXA(DMIC0FCLKDIV_OFFSET, 0), /*!< Dmic Clk Divider. */
+ kCLOCK_DivPLLFRGClk = CLKCTL1_TUPLE_MUXA(FRGPLLCLKDIV_OFFSET, 0), /*!< P L L F R G Clk Divider. */
+ kCLOCK_DivFlexioClk = CLKCTL1_TUPLE_MUXA(FLEXIOCLKDIV_OFFSET, 0), /*!< Flexio Clk Divider. */
+ kCLOCK_DivI3cClk = CLKCTL1_TUPLE_MUXA(I3C01FCLKDIV_OFFSET, 0), /*!< I3c Clk Divider. */
+ kCLOCK_DivI3cTcClk = CLKCTL1_TUPLE_MUXA(I3C01FCLKSTCDIV_OFFSET, 0), /*!< I3c Tc Clk Divider. */
+ kCLOCK_DivI3cSlowClk = CLKCTL1_TUPLE_MUXA(I3C01FCLKSDIV_OFFSET, 0), /*!< I3c Slow Clk Divider. */
+ kCLOCK_DivDspCpuClk = CLKCTL1_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0), /*!< Dsp Cpu Clk Divider. */
+ kCLOCK_DivAcmpClk = CLKCTL1_TUPLE_MUXA(ACMP0FCLKDIV_OFFSET, 0), /*!< Acmp Clk Divider. */
+ kCLOCK_DivAdcClk = CLKCTL0_TUPLE_MUXA(ADC0FCLKDIV_OFFSET, 0), /*!< Adc Clk Divider. */
+ kCLOCK_DivLowFreqClk = CLKCTL0_TUPLE_MUXA(LOWFREQCLKDIV_OFFSET, 0), /*!< Low Freq Clk Divider. */
+ kCLOCK_DivClockOut = CLKCTL1_TUPLE_MUXA(CLKOUTFCLKDIV_OFFSET, 0), /*!< Clock Out Divider. */
+ kCLOCK_DivGpuClk = CLKCTL0_TUPLE_MUXA(GPUCLKDIV_OFFSET, 0), /*!< Gpu Clk Divider. */
+ kCLOCK_DivDcPixelClk = CLKCTL0_TUPLE_MUXA(DCPIXELCLKDIV_OFFSET, 0), /*!< Dc Pixel Clk Divider. */
+ kCLOCK_DivDphyClk = CLKCTL0_TUPLE_MUXA(DPHYCLKDIV_OFFSET, 0), /*!< Dphy Clk Divider. */
+ kCLOCK_DivDphyEscRxClk = CLKCTL0_TUPLE_MUXA(DPHYESCRXCLKDIV_OFFSET, 0), /*!< Dphy Esc Rx Clk Divider. */
+ kCLOCK_DivDphyEscTxClk = CLKCTL0_TUPLE_MUXA(DPHYESCTXCLKDIV_OFFSET, 0), /*!< Dphy Esc Tx Clk Divider. */
+} clock_div_name_t;
+
+/*! @brief SysPLL Reference Input Clock Source */
+typedef enum _sys_pll_src
+{
+ kCLOCK_SysPllFroDiv8Clk = 0, /*!< FRO_DIV8 clock */
+ kCLOCK_SysPllXtalIn = 1, /*!< OSC clock */
+ kCLOCK_SysPllNone = 7 /*!< Gated to reduce power */
+} sys_pll_src_t;
+
+/*! @brief SysPLL Multiplication Factor */
+typedef enum _sys_pll_mult
+{
+ kCLOCK_SysPllMult16 = 0, /*!< Divide by 16 */
+ kCLOCK_SysPllMult17, /*!< Divide by 17 */
+ kCLOCK_SysPllMult18, /*!< Divide by 18 */
+ kCLOCK_SysPllMult19, /*!< Divide by 19 */
+ kCLOCK_SysPllMult20, /*!< Divide by 20 */
+ kCLOCK_SysPllMult21, /*!< Divide by 21 */
+ kCLOCK_SysPllMult22, /*!< Divide by 22 */
+} sys_pll_mult_t;
+
+/*! @brief PLL configuration for SYSPLL */
+typedef struct _clock_sys_pll_config
+{
+ sys_pll_src_t sys_pll_src; /*!< Reference Input Clock Source */
+ uint32_t numerator; /*!< 30 bit numerator of fractional loop divider. */
+ uint32_t denominator; /*!< 30 bit numerator of fractional loop divider. */
+ sys_pll_mult_t sys_pll_mult; /*!< Multiplication Factor */
+} clock_sys_pll_config_t;
+
+/*! @brief AudioPll Reference Input Clock Source */
+typedef enum _audio_pll_src
+{
+ kCLOCK_AudioPllFroDiv8Clk = 0, /*!< FRO_DIV8 clock */
+ kCLOCK_AudioPllXtalIn = 1, /*!< OSC clock */
+ kCLOCK_AudioPllNone = 7 /*!< Gated to reduce power */
+} audio_pll_src_t;
+
+/*! @brief AudioPll Multiplication Factor */
+typedef enum _audio_pll_mult
+{
+ kCLOCK_AudioPllMult16 = 0, /*!< Divide by 16 */
+ kCLOCK_AudioPllMult17, /*!< Divide by 17 */
+ kCLOCK_AudioPllMult18, /*!< Divide by 18 */
+ kCLOCK_AudioPllMult19, /*!< Divide by 19 */
+ kCLOCK_AudioPllMult20, /*!< Divide by 20 */
+ kCLOCK_AudioPllMult21, /*!< Divide by 21 */
+ kCLOCK_AudioPllMult22, /*!< Divide by 22 */
+} audio_pll_mult_t;
+
+/*! @brief PLL configuration for SYSPLL */
+typedef struct _clock_audio_pll_config
+{
+ audio_pll_src_t audio_pll_src; /*!< Reference Input Clock Source */
+ uint32_t numerator; /*!< 30 bit numerator of fractional loop divider. */
+ uint32_t denominator; /*!< 30 bit numerator of fractional loop divider. */
+ audio_pll_mult_t audio_pll_mult; /*!< Multiplication Factor */
+} clock_audio_pll_config_t;
+
+/*! @brief PLL configuration for FRG */
+typedef struct _clock_frg_clk_config
+{
+ uint8_t num; /*!< FRG clock, [0 - 16]: Flexcomm, [17]: Flexio */
+ enum
+ {
+ kCLOCK_FrgMainClk = 0, /*!< Main System clock */
+ kCLOCK_FrgPllDiv, /*!< Main pll clock divider*/
+ kCLOCK_FrgFroDiv4, /*!< FRO_DIV4 */
+ } sfg_clock_src;
+ uint8_t divider; /*!< Denominator of the fractional divider. */
+ uint8_t mult; /*!< Numerator of the fractional divider. */
+} clock_frg_clk_config_t;
+
+/*! @brief FRO output enable */
+typedef enum _clock_fro_output_en
+{
+ kCLOCK_FroDiv1OutEn = CLKCTL0_FRODIVOEN_FRO_DIV1_O_EN_MASK, /*!< Enable Fro Div1 output. */
+ kCLOCK_FroDiv2OutEn = CLKCTL0_FRODIVOEN_FRO_DIV2_O_EN_MASK, /*!< Enable Fro Div2 output. */
+ kCLOCK_FroDiv4OutEn = CLKCTL0_FRODIVOEN_FRO_DIV4_O_EN_MASK, /*!< Enable Fro Div4 output. */
+ kCLOCK_FroDiv8OutEn = CLKCTL0_FRODIVOEN_FRO_DIV8_O_EN_MASK, /*!< Enable Fro Div8 output. */
+ kCLOCK_FroDiv16OutEn = CLKCTL0_FRODIVOEN_FRO_DIV16_O_EN_MASK, /*!< Enable Fro Div16 output. */
+ kCLOCK_FroAllOutEn = CLKCTL0_FRODIVOEN_FRO_DIV1_O_EN_MASK | CLKCTL0_FRODIVOEN_FRO_DIV2_O_EN_MASK |
+ CLKCTL0_FRODIVOEN_FRO_DIV4_O_EN_MASK | CLKCTL0_FRODIVOEN_FRO_DIV8_O_EN_MASK |
+ CLKCTL0_FRODIVOEN_FRO_DIV16_O_EN_MASK
+} clock_fro_output_en_t;
+
+/*! @brief FRO frequence configuration */
+typedef enum _clock_fro_freq
+{
+ kCLOCK_Fro192M, /*!< 192MHz FRO clock. */
+ kCLOCK_Fro96M, /*!< 96MHz FRO clock. */
+} clock_fro_freq_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+static inline void CLOCK_EnableClock(clock_ip_name_t clk)
+{
+ uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
+
+ switch (index)
+ {
+ case CLK_CTL0_PSCCTL0:
+ CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ break;
+ case CLK_CTL0_PSCCTL1:
+ CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ break;
+ case CLK_CTL0_PSCCTL2:
+ CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ break;
+ case CLK_CTL1_PSCCTL0:
+ CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ break;
+ case CLK_CTL1_PSCCTL1:
+ CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ break;
+ case CLK_CTL1_PSCCTL2:
+ CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ break;
+ default:
+ assert(false);
+ break;
+ }
+}
+
+static inline void CLOCK_DisableClock(clock_ip_name_t clk)
+{
+ uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
+ switch (index)
+ {
+ case CLK_CTL0_PSCCTL0:
+ CLKCTL0->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ break;
+ case CLK_CTL0_PSCCTL1:
+ CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ break;
+ case CLK_CTL0_PSCCTL2:
+ CLKCTL0->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ break;
+ case CLK_CTL1_PSCCTL0:
+ CLKCTL1->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ break;
+ case CLK_CTL1_PSCCTL1:
+ CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ break;
+ case CLK_CTL1_PSCCTL2:
+ CLKCTL1->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+ break;
+ default:
+ assert(false);
+ break;
+ }
+}
+
+/**
+ * @brief Configure the clock selection muxes.
+ * @param connection : Clock to be configured.
+ * @return Nothing
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection);
+
+/**
+ * @brief Setup peripheral clock dividers.
+ * @param div_name : Clock divider name
+ * @param divider : Value to be divided. Divided clock frequency = Undivided clock frequency / divider.
+ * @return Nothing
+ */
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divider);
+
+/*! @brief Return Frequency of selected clock
+ * @return Frequency of selected clock
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName);
+
+/*! @brief Return Input frequency for the Fractional baud rate generator
+ * @return Input Frequency for FRG
+ */
+uint32_t CLOCK_GetFRGClock(uint32_t id);
+
+/*! @brief Set output of the Fractional baud rate generator
+ * @param config : Configuration to set to FRGn clock.
+ */
+void CLOCK_SetFRGClock(const clock_frg_clk_config_t *config);
+
+/*! @brief Return Frequency of SYSPLL
+ * @return Frequency of SYSPLL
+ */
+uint32_t CLOCK_GetSysPllFreq(void);
+
+/*! @brief Get current output frequency of specific System PLL PFD.
+ * @param pfd : pfd name to get frequency.
+ * @return Frequency of SYSPLL PFD.
+ */
+uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
+
+/*! @brief Return Frequency of AUDIO PLL
+ * @return Frequency of AUDIO PLL
+ */
+uint32_t CLOCK_GetAudioPllFreq(void);
+
+/*! @brief Get current output frequency of specific Audio PLL PFD.
+ * @param pfd : pfd name to get frequency.
+ * @return Frequency of AUDIO PLL PFD.
+ */
+uint32_t CLOCK_GetAudioPfdFreq(clock_pfd_t pfd);
+
+/*! @brief Return Frequency of main clk
+ * @return Frequency of main clk
+ */
+uint32_t CLOCK_GetMainClkFreq(void);
+
+/*! @brief Return Frequency of DSP main clk
+ * @return Frequency of DSP main clk
+ */
+uint32_t CLOCK_GetDspMainClkFreq(void);
+
+/*! @brief Return Frequency of ACMP clk
+ * @return Frequency of ACMP clk
+ */
+uint32_t CLOCK_GetAcmpClkFreq(void);
+
+/*! @brief Return Frequency of DMIC clk
+ * @return Frequency of DMIC clk
+ */
+uint32_t CLOCK_GetDmicClkFreq(void);
+
+/*! @brief Return Frequency of USB clk
+ * @return Frequency of USB clk
+ */
+uint32_t CLOCK_GetUsbClkFreq(void);
+
+/*! @brief Return Frequency of SDIO clk
+ * @param id : SDIO index to get frequency.
+ * @return Frequency of SDIO clk
+ */
+uint32_t CLOCK_GetSdioClkFreq(uint32_t id);
+
+/*! @brief Return Frequency of I3C clk
+ * @return Frequency of I3C clk
+ */
+uint32_t CLOCK_GetI3cClkFreq(void);
+
+/*! @brief Return Frequency of systick clk
+ * @return Frequency of systick clk
+ */
+uint32_t CLOCK_GetSystickClkFreq(void);
+
+/*! @brief Return Frequency of WDT clk
+ * @param id : WDT index to get frequency.
+ * @return Frequency of WDT clk
+ */
+uint32_t CLOCK_GetWdtClkFreq(uint32_t id);
+
+/*! @brief Return output Frequency of mclk
+ * @return Frequency of mclk output clk
+ */
+uint32_t CLOCK_GetMclkClkFreq(void);
+
+/*! @brief Return Frequency of sct
+ * @return Frequency of sct clk
+ */
+uint32_t CLOCK_GetSctClkFreq(void);
+
+/*! @brief Enable/Disable sys osc clock from external crystal clock.
+ * @param enable : true to enable system osc clock, false to bypass system osc.
+ * @param enableLowPower : true to enable low power mode, false to enable high gain mode.
+ * @param delay_us : Delay time after OSC power up.
+ */
+void CLOCK_EnableSysOscClk(bool enable, bool enableLowPower, uint32_t delay_us);
+
+/*! @brief Enable/Disable FRO clock output.
+ * @param divOutEnable : Or'ed value of clock_fro_output_en_t to enable certain clock freq output.
+ */
+void CLOCK_EnableFroClk(uint32_t divOutEnable);
+
+#ifndef __XCC__
+/*! @brief Enable/Disable FRO192M or FRO96M clock output.
+ * @param froFreq : target fro frequency.
+ * @param divOutEnable : Or'ed value of clock_fro_output_en_t to enable certain clock freq output.
+ */
+void CLOCK_EnableFroClkRange(clock_fro_freq_t froFreq, uint32_t divOutEnable);
+#endif /* __XCC__ */
+
+/*! @brief Enable LPOSC 1MHz clock.
+ */
+void CLOCK_EnableLpOscClk(void);
+
+/*! @brief Return Frequency of sys osc Clock
+ * @return Frequency of sys osc Clock. Or CLK_IN pin frequency.
+ */
+static inline uint32_t CLOCK_GetXtalInClkFreq(void)
+{
+ return (CLKCTL0->SYSOSCBYPASS == 0U) ? g_xtalFreq : ((CLKCTL0->SYSOSCBYPASS == 1U) ? g_clkinFreq : 0U);
+}
+
+/*! @brief Return Frequency of MCLK Input Clock
+ * @return Frequency of MCLK input Clock.
+ */
+static inline uint32_t CLOCK_GetMclkInClkFreq(void)
+{
+ return g_mclkFreq;
+}
+
+/*! @brief Return Frequency of Lower power osc
+ * @return Frequency of LPOSC
+ */
+static inline uint32_t CLOCK_GetLpOscFreq(void)
+{
+ return CLK_LPOSC_1MHZ;
+}
+
+/*! @brief Return Frequency of 32kHz osc
+ * @return Frequency of 32kHz osc
+ */
+static inline uint32_t CLOCK_GetOsc32KFreq(void)
+{
+ return ((CLKCTL0->OSC32KHZCTL0 & CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK) != 0UL) ? CLK_RTC_32K_CLK : 0U;
+}
+
+/*! @brief Enables and disables 32kHz osc
+ * @param enable : true to enable 32k osc clock, false to disable clock
+ */
+static inline void CLOCK_EnableOsc32K(bool enable)
+{
+ if (enable)
+ {
+ CLKCTL0->OSC32KHZCTL0 |= CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK;
+ }
+ else
+ {
+ CLKCTL0->OSC32KHZCTL0 &= ~CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK;
+ }
+}
+
+/*! @brief Return Frequency of 32khz wake clk
+ * @return Frequency of 32kHz wake clk
+ */
+static inline uint32_t CLOCK_GetWakeClk32KFreq(void)
+{
+ return ((CLKCTL0->A32KHZWAKECLKSEL & CLKCTL0_A32KHZWAKECLKSEL_SEL_MASK) != 0U) ?
+ CLOCK_GetLpOscFreq() / ((CLKCTL0->A32KHZWAKECLKDIV & CLKCTL0_A32KHZWAKECLKDIV_DIV_MASK) + 1U) :
+ CLOCK_GetOsc32KFreq();
+}
+
+/*!
+ * @brief Set the XTALIN (system OSC) frequency based on board setting.
+ *
+ * @param freq : The XTAL input clock frequency in Hz.
+ */
+static inline void CLOCK_SetXtalFreq(uint32_t freq)
+{
+ g_xtalFreq = freq;
+}
+
+/*!
+ * @brief Set the CLKIN (CLKIN pin) frequency based on board setting.
+ *
+ * @param freq : The CLK_IN pin input clock frequency in Hz.
+ */
+static inline void CLOCK_SetClkinFreq(uint32_t freq)
+{
+ g_clkinFreq = freq;
+}
+
+/*!
+ * @brief Set the MCLK IN frequency based on board setting.
+ *
+ * @param freq : The MCLK input clock frequency in Hz.
+ */
+static inline void CLOCK_SetMclkFreq(uint32_t freq)
+{
+ g_mclkFreq = freq;
+}
+
+/*! @brief Return Frequency of Flexcomm functional Clock
+ * @param id : flexcomm index to get frequency.
+ * @return Frequency of Flexcomm functional Clock
+ */
+uint32_t CLOCK_GetFlexcommClkFreq(uint32_t id);
+
+/*! @brief Return Frequency of Flexio functional Clock
+ * @return Frequency of Flexcomm functional Clock
+ */
+uint32_t CLOCK_GetFlexioClkFreq(void);
+
+/*! @brief Return Frequency of Ctimer Clock
+ * @param id : ctimer index to get frequency.
+ * @return Frequency of Ctimer Clock
+ */
+uint32_t CLOCK_GetCtimerClkFreq(uint32_t id);
+/*! @brief Return Frequency of ClockOut
+ * @return Frequency of ClockOut
+ */
+uint32_t CLOCK_GetClockOutClkFreq(void);
+/*! @brief Return Frequency of Adc Clock
+ * @return Frequency of Adc Clock.
+ */
+uint32_t CLOCK_GetAdcClkFreq(void);
+/*! @brief Return Frequency of FLEXSPI Clock
+ * @param id : flexspi index to get frequency.
+ * @return Frequency of Flexspi.
+ */
+uint32_t CLOCK_GetFlexspiClkFreq(uint32_t id);
+
+/*! @brief Return Frequency of GPU functional Clock
+ * @return Frequency of GPU functional Clock
+ */
+uint32_t CLOCK_GetGpuClkFreq(void);
+
+/*! @brief Return Frequency of DCNano Pixel functional Clock
+ * @return Frequency of DCNano pixel functional Clock
+ */
+uint32_t CLOCK_GetDcPixelClkFreq(void);
+
+/*! @brief Return Frequency of MIPI DPHY functional Clock
+ * @return Frequency of MIPI DPHY functional Clock
+ */
+uint32_t CLOCK_GetMipiDphyClkFreq(void);
+
+/*! @brief Return Frequency of MIPI DPHY Esc RX functional Clock
+ * @return Frequency of MIPI DPHY Esc RX functional Clock
+ */
+uint32_t CLOCK_GetMipiDphyEscRxClkFreq(void);
+
+/*! @brief Return Frequency of MIPI DPHY Esc Tx functional Clock
+ * @return Frequency of MIPI DPHY Esc Tx functional Clock
+ */
+uint32_t CLOCK_GetMipiDphyEscTxClkFreq(void);
+
+/*! @brief Initialize the System PLL.
+ * @param config : Configuration to set to PLL.
+ */
+void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
+
+/*! brief Deinit the System PLL.
+ * param none.
+ */
+static inline void CLOCK_DeinitSysPll(void)
+{
+ /* Set System PLL Reset & HOLDRINGOFF_ENA */
+ CLKCTL0->SYSPLL0CTL0 |= CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_MASK | CLKCTL0_SYSPLL0CTL0_RESET_MASK;
+ /* Power down System PLL*/
+ SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK;
+}
+
+/*! @brief Initialize the System PLL PFD.
+ * @param pfd : Which PFD clock to enable.
+ * @param divider : The PFD divider value.
+ * @note It is recommended that PFD settings are kept between 12-35.
+ */
+void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t divider);
+
+/*! brief Disable the audio PLL PFD.
+ * param pfd : Which PFD clock to disable.
+ */
+static inline void CLOCK_DeinitSysPfd(clock_pfd_t pfd)
+{
+ CLKCTL0->SYSPLL0PFD |= ((uint32_t)CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_MASK << (8U * (uint32_t)pfd));
+}
+
+/*! @brief Initialize the audio PLL.
+ * @param config : Configuration to set to PLL.
+ */
+void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
+
+/*! brief Deinit the Audio PLL.
+ * param none.
+ */
+static inline void CLOCK_DeinitAudioPll(void)
+{
+ /* Set Audio PLL Reset & HOLDRINGOFF_ENA */
+ CLKCTL1->AUDIOPLL0CTL0 |= CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK | CLKCTL1_AUDIOPLL0CTL0_RESET_MASK;
+ /* Power down Audio PLL */
+ SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK;
+}
+
+/*! @brief Initialize the audio PLL PFD.
+ * @param pfd : Which PFD clock to enable.
+ * @param divider : The PFD divider value.
+ * @note It is recommended that PFD settings are kept between 12-35.
+ */
+void CLOCK_InitAudioPfd(clock_pfd_t pfd, uint8_t divider);
+
+/*! brief Disable the audio PLL PFD.
+ * param pfd : Which PFD clock to disable.
+ */
+static inline void CLOCK_DeinitAudioPfd(uint32_t pfd)
+{
+ CLKCTL1->AUDIOPLL0PFD |= ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8U * pfd));
+}
+
+/*! @brief Enable/Disable FRO tuning.
+ * On enable, the function will wait until FRO is close to the target frequency.
+ */
+void CLOCK_EnableFroTuning(bool enable);
+
+/*! @brief Enable USB HS device clock.
+ *
+ * This function enables USB HS device clock.
+ */
+void CLOCK_EnableUsbHs0DeviceClock(clock_attach_id_t src, uint8_t divider);
+
+/*! @brief Disable USB HS device clock.
+ *
+ * This function disables USB HS device clock.
+ */
+void CLOCK_DisableUsbHs0DeviceClock(void);
+
+/*! @brief Enable USB HS host clock.
+ *
+ * This function enables USB HS host clock.
+ */
+void CLOCK_EnableUsbHs0HostClock(clock_attach_id_t src, uint8_t divider);
+
+/*! @brief Disable USB HS host clock.
+ *
+ * This function disables USB HS host clock.
+ */
+void CLOCK_DisableUsbHs0HostClock(void);
+
+/*! brief Enable USB hs0PhyPll clock.
+ *
+ * param src USB HS clock source.
+ * param freq The frequency specified by src.
+ * retval true The clock is set successfully.
+ * retval false The clock source is invalid to get proper USB HS clock.
+ */
+bool CLOCK_EnableUsbHs0PhyPllClock(clock_attach_id_t src, uint32_t freq);
+
+/*! @brief Disable USB hs0PhyPll clock.
+ *
+ * This function disables USB hs0PhyPll clock.
+ */
+void CLOCK_DisableUsbHs0PhyPllClock(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_CLOCK_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common.c b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common.c
new file mode 100644
index 000000000..8b17fc366
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+
+#define SDK_MEM_MAGIC_NUMBER 12345U
+
+typedef struct _mem_align_control_block
+{
+ uint16_t identifier; /*!< Identifier for the memory control block. */
+ uint16_t offset; /*!< offset from aligned address to real address */
+} mem_align_cb_t;
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common"
+#endif
+
+void *SDK_Malloc(size_t size, size_t alignbytes)
+{
+ mem_align_cb_t *p_cb = NULL;
+ uint32_t alignedsize;
+
+ /* Check overflow. */
+ alignedsize = SDK_SIZEALIGN(size, alignbytes);
+ if (alignedsize < size)
+ {
+ return NULL;
+ }
+
+ if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t))
+ {
+ return NULL;
+ }
+
+ alignedsize += alignbytes + sizeof(mem_align_cb_t);
+
+ union
+ {
+ void *pointer_value;
+ uint32_t unsigned_value;
+ } p_align_addr, p_addr;
+
+ p_addr.pointer_value = malloc(alignedsize);
+
+ if (p_addr.pointer_value == NULL)
+ {
+ return NULL;
+ }
+
+ p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
+
+ p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
+ p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
+ p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
+
+ return p_align_addr.pointer_value;
+}
+
+void SDK_Free(void *ptr)
+{
+ union
+ {
+ void *pointer_value;
+ uint32_t unsigned_value;
+ } p_free;
+ p_free.pointer_value = ptr;
+ mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
+
+ if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
+ {
+ return;
+ }
+
+ p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
+
+ free(p_free.pointer_value);
+}
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common.h b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common.h
new file mode 100644
index 000000000..663b23a73
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common.h
@@ -0,0 +1,293 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_COMMON_H_
+#define _FSL_COMMON_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+
+#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__)
+#include <stddef.h>
+#endif
+
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Configurations
+ ******************************************************************************/
+
+/*! @brief Macro to use the default weak IRQ handler in drivers. */
+#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+
+/*! @brief Construct the version number for drivers. */
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief common driver version. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
+/*@}*/
+
+/* Debug console type definition. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+ kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
+ kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
+ kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
+ kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
+ kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
+ kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
+ kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
+ kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
+ kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
+ kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
+ kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
+ kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
+ kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
+ kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
+ kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
+ kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
+ kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
+ kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
+ kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
+ kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
+ kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
+ kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
+ kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
+ kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
+ kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
+ kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
+ kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
+ kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
+ kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
+ kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
+ kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
+ kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
+ kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
+ kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
+ kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
+ kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
+ kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
+ kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
+ kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
+ kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
+ kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
+ kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
+ kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
+ kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
+ kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
+ kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
+ kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
+ kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
+ kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
+ kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
+ kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
+ kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
+ kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
+ kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
+ kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
+ kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
+ kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
+ kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
+ kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
+ kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */
+ kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
+ kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
+ kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
+ kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
+ kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */
+ kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */
+ kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */
+ kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */
+ kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
+ kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
+ kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
+ kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
+ kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
+ kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/
+ kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */
+ kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */
+ kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */
+
+ kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
+ kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
+ kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */
+ kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */
+ kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */
+ kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */
+ kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */
+ kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */
+ kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */
+ kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */
+ kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */
+ kStatusGroup_LED = 137, /*!< Group number for LED status codes. */
+ kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */
+ kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */
+ kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */
+ kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */
+ kStatusGroup_LIST = 142, /*!< Group number for List status codes. */
+ kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */
+ kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */
+ kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */
+ kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */
+ kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/
+ kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */
+ kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */
+ kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */
+ kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */
+ kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */
+ kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */
+ kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */
+ kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */
+ kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */
+ kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */
+};
+
+/*! \public
+ * @brief Generic status return codes.
+ */
+enum
+{
+ kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */
+ kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */
+ kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */
+ kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */
+ kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */
+ kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */
+ kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */
+ kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+/*!
+ * @name Min/max macros
+ * @{
+ */
+#if !defined(MIN)
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+/* @} */
+
+/*! @brief Computes the number of elements in an array. */
+#if !defined(ARRAY_SIZE)
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
+
+/*! @name UINT16_MAX/UINT32_MAX value */
+/* @{ */
+#if !defined(UINT16_MAX)
+#define UINT16_MAX ((uint16_t)-1)
+#endif
+
+#if !defined(UINT32_MAX)
+#define UINT32_MAX ((uint32_t)-1)
+#endif
+/* @} */
+
+/*! @name Suppress fallthrough warning macro */
+/* For switch case code block, if case section ends without "break;" statement, there wil be
+ fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
+ To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
+ case section which misses "break;"statement.
+ */
+/* @{ */
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__ ((fallthrough))
+#else
+#define SUPPRESS_FALL_THROUGH_WARNING()
+#endif
+/* @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Allocate memory with given alignment and aligned size.
+ *
+ * This is provided to support the dynamically allocated memory
+ * used in cache-able region.
+ * @param size The length required to malloc.
+ * @param alignbytes The alignment size.
+ * @retval The allocated memory.
+ */
+void *SDK_Malloc(size_t size, size_t alignbytes);
+
+/*!
+ * @brief Free memory.
+ *
+ * @param ptr The memory to be release.
+ */
+void SDK_Free(void *ptr);
+
+/*!
+* @brief Delay at least for some time.
+* Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
+* if precise delay count was needed, please implement a new delay function with hardware timer.
+*
+* @param delayTime_us Delay time in unit of microsecond.
+* @param coreClock_Hz Core clock frequency with Hz.
+*/
+void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#if (defined(__DSC__) && defined(__CW__))
+#include "fsl_common_dsc.h"
+#elif defined(__XCC__)
+#include "fsl_common_dsp.h"
+#else
+#include "fsl_common_arm.h"
+#endif
+
+#endif /* _FSL_COMMON_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common_arm.c b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common_arm.c
new file mode 100644
index 000000000..e77a265ce
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common_arm.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common_arm"
+#endif
+
+#ifndef __GIC_PRIO_BITS
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+#ifdef __VECTOR_TABLE
+#undef __VECTOR_TABLE
+#endif
+
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Image$$VECTOR_ROM$$Base[];
+ extern uint32_t Image$$VECTOR_RAM$$Base[];
+ extern uint32_t Image$$RW_m_data$$Base[];
+
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+ extern uint32_t __VECTOR_TABLE[];
+ extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+ extern uint32_t __VECTOR_TABLE[];
+ extern uint32_t __VECTOR_RAM[];
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+ uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
+ uint32_t n;
+ uint32_t ret;
+ uint32_t irqMaskValue;
+
+ irqMaskValue = DisableGlobalIRQ();
+ if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+ {
+ /* Copy the vector table from ROM to RAM */
+ for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+ {
+ __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+ }
+ /* Point the VTOR to the position of vector table */
+ SCB->VTOR = (uint32_t)__VECTOR_RAM;
+ }
+
+ ret = __VECTOR_RAM[(int32_t)irq + 16];
+ /* make sure the __VECTOR_RAM is noncachable */
+ __VECTOR_RAM[(int32_t)irq + 16] = irqHandler;
+
+ EnableGlobalIRQ(irqMaskValue);
+
+ return ret;
+}
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+#endif /* __GIC_PRIO_BITS. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+/*
+ * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
+ * powerlib should be used instead of these functions.
+ */
+#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
+
+/*
+ * When the SYSCON STARTER registers are discontinuous, these functions are
+ * implemented in fsl_power.c.
+ */
+#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+ uint32_t intNumber = (uint32_t)interrupt;
+
+ uint32_t index = 0;
+
+ while (intNumber >= 32u)
+ {
+ index++;
+ intNumber -= 32u;
+ }
+
+ SYSCON->STARTERSET[index] = 1UL << intNumber;
+ (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+ uint32_t intNumber = (uint32_t)interrupt;
+
+ (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+ uint32_t index = 0;
+
+ while (intNumber >= 32u)
+ {
+ index++;
+ intNumber -= 32u;
+ }
+
+ SYSCON->STARTERCLR[index] = 1UL << intNumber;
+}
+#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
+#endif /* FSL_FEATURE_POWERLIB_EXTEND */
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(SDK_DELAY_USE_DWT) && defined(DWT)
+/* Use WDT. */
+static void enableCpuCycleCounter(void)
+{
+ /* Make sure the DWT trace fucntion is enabled. */
+ if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
+ {
+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+ }
+
+ /* CYCCNT not supported on this device. */
+ assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk));
+
+ /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */
+ if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL))
+ {
+ DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+ }
+}
+
+static uint32_t getCpuCycleCount(void)
+{
+ return DWT->CYCCNT;
+}
+#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+/* Use software loop. */
+#if defined(__CC_ARM) /* This macro is arm v5 specific */
+/* clang-format off */
+__ASM static void DelayLoop(uint32_t count)
+{
+loop
+ SUBS R0, R0, #1
+ CMP R0, #0
+ BNE loop
+ BX LR
+}
+/* clang-format on */
+#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
+/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
+ * use SUB and CMP here for compatibility */
+static void DelayLoop(uint32_t count)
+{
+ __ASM volatile(" MOV R0, %0" : : "r"(count));
+ __ASM volatile(
+ "loop: \n"
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+ " SUB R0, R0, #1 \n"
+#else
+ " SUBS R0, R0, #1 \n"
+#endif
+ " CMP R0, #0 \n"
+
+ " BNE loop \n"
+ :
+ :
+ : "r0");
+}
+#endif /* defined(__CC_ARM) */
+#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+
+/*!
+ * @brief Delay at least for some time.
+ * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have
+ * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and
+ * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports
+ * up to 4294967 in current code. If long time delay is needed, please implement a new delay function.
+ *
+ * @param delayTime_us Delay time in unit of microsecond.
+ * @param coreClock_Hz Core clock frequency with Hz.
+ */
+void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
+{
+ uint64_t count;
+
+ if (delayTime_us > 0U)
+ {
+ count = USEC_TO_COUNT(delayTime_us, coreClock_Hz);
+
+ assert(count <= UINT32_MAX);
+
+#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */
+
+ enableCpuCycleCounter();
+ /* Calculate the count ticks. */
+ count += getCpuCycleCount();
+
+ if (count > UINT32_MAX)
+ {
+ count -= UINT32_MAX;
+ /* Wait for cyccnt overflow. */
+ while (count < getCpuCycleCount())
+ {
+ }
+ }
+
+ /* Wait for cyccnt reach count value. */
+ while (count > getCpuCycleCount())
+ {
+ }
+#else
+ /* Divide value may be different in various environment to ensure delay is precise.
+ * Every loop count includes three instructions, due to Cortex-M7 sometimes executes
+ * two instructions in one period, through test here set divide 1.5. Other M cores use
+ * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
+ * not matter because other instructions outside while loop is enough to fill the time.
+ */
+#if (__CORTEX_M == 7)
+ count = count / 3U * 2U;
+#else
+ count = count / 4U;
+#endif
+ DelayLoop((uint32_t)count);
+#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+ }
+}
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common_arm.h b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common_arm.h
new file mode 100644
index 000000000..8b28aa888
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_common_arm.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_COMMON_ARM_H_
+#define _FSL_COMMON_ARM_H_
+
+/*
+ * For CMSIS pack RTE.
+ * CMSIS pack RTE generates "RTC_Components.h" which contains the statements
+ * of the related <RTE_Components_h> element for all selected software components.
+ */
+#ifdef _RTE_
+#include "RTE_Components.h"
+#endif
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*! @name Atomic modification
+ *
+ * These macros are used for atomic access, such as read-modify-write
+ * to the peripheral registers.
+ *
+ * - SDK_ATOMIC_LOCAL_ADD
+ * - SDK_ATOMIC_LOCAL_SET
+ * - SDK_ATOMIC_LOCAL_CLEAR
+ * - SDK_ATOMIC_LOCAL_TOGGLE
+ * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET
+ *
+ * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr
+ * means the address of the peripheral register or variable you want to modify
+ * atomically, the parameter @c clearBits is the bits to clear, the parameter
+ * @c setBits it the bits to set.
+ * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this:
+ *
+ * @code
+ volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR;
+
+ SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02);
+ @endcode
+ *
+ * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result,
+ * register bit1:bit0 = 0b10.
+ *
+ * @note For the platforms don't support exclusive load and store, these macros
+ * disable the global interrupt to pretect the modification.
+ *
+ * @note These macros only guarantee the local processor atomic operations. For
+ * the multi-processor devices, use hardware semaphore such as SEMA42 to
+ * guarantee exclusive access if necessary.
+ *
+ * @{
+ */
+
+/* clang-format off */
+#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1)))
+/* clang-format on */
+
+/* If the LDREX and STREX are supported, use them. */
+#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \
+ do \
+ { \
+ (val) = __LDREXB(addr); \
+ (ops); \
+ } while (0UL != __STREXB((val), (addr)))
+
+#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \
+ do \
+ { \
+ (val) = __LDREXH(addr); \
+ (ops); \
+ } while (0UL != __STREXH((val), (addr)))
+
+#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \
+ do \
+ { \
+ (val) = __LDREXW(addr); \
+ (ops); \
+ } while (0UL != __STREXW((val), (addr)))
+
+static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val)
+{
+ uint8_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val);
+}
+
+static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val)
+{
+ uint16_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val);
+}
+
+static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val)
+{
+ uint32_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val);
+}
+
+static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val)
+{
+ uint8_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val);
+}
+
+static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val)
+{
+ uint16_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val);
+}
+
+static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val)
+{
+ uint32_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val);
+}
+
+static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits)
+{
+ uint8_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits);
+}
+
+static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits)
+{
+ uint16_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits);
+}
+
+static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits)
+{
+ uint32_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits);
+}
+
+static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits)
+{
+ uint8_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits);
+}
+
+static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits)
+{
+ uint16_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits);
+}
+
+static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits)
+{
+ uint32_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits);
+}
+
+static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits)
+{
+ uint8_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits);
+}
+
+static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits)
+{
+ uint16_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits);
+}
+
+static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits)
+{
+ uint32_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits);
+}
+
+static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits)
+{
+ uint8_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
+}
+
+static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits)
+{
+ uint16_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
+}
+
+static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits)
+{
+ uint32_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
+}
+
+#define SDK_ATOMIC_LOCAL_ADD(addr, val) \
+ ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd1Byte((volatile uint8_t*)(volatile void*)(addr), (val)) : \
+ ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t*)(volatile void*)(addr), (val)) : \
+ _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void*)(addr), (val))))
+
+#define SDK_ATOMIC_LOCAL_SET(addr, bits) \
+ ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \
+ ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \
+ _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void*)(addr), (bits))))
+
+#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \
+ ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalClear1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \
+ ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalClear2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \
+ _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void*)(addr), (bits))))
+
+#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \
+ ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalToggle1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \
+ ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalToggle2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \
+ _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void*)(addr), (bits))))
+
+#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
+ ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t*)(volatile void*)(addr), (clearBits), (setBits)) : \
+ ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t*)(volatile void*)(addr), (clearBits), (setBits)) : \
+ _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void*)(addr), (clearBits), (setBits))))
+#else
+
+#define SDK_ATOMIC_LOCAL_ADD(addr, val) \
+ do { \
+ uint32_t s_atomicOldInt; \
+ s_atomicOldInt = DisableGlobalIRQ(); \
+ *(addr) += (val); \
+ EnableGlobalIRQ(s_atomicOldInt); \
+ } while (0)
+
+#define SDK_ATOMIC_LOCAL_SET(addr, bits) \
+ do { \
+ uint32_t s_atomicOldInt; \
+ s_atomicOldInt = DisableGlobalIRQ(); \
+ *(addr) |= (bits); \
+ EnableGlobalIRQ(s_atomicOldInt); \
+ } while (0)
+
+#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \
+ do { \
+ uint32_t s_atomicOldInt; \
+ s_atomicOldInt = DisableGlobalIRQ(); \
+ *(addr) &= ~(bits); \
+ EnableGlobalIRQ(s_atomicOldInt); \
+ } while (0)
+
+#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \
+ do { \
+ uint32_t s_atomicOldInt; \
+ s_atomicOldInt = DisableGlobalIRQ(); \
+ *(addr) ^= (bits); \
+ EnableGlobalIRQ(s_atomicOldInt); \
+ } while (0)
+
+#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
+ do { \
+ uint32_t s_atomicOldInt; \
+ s_atomicOldInt = DisableGlobalIRQ(); \
+ *(addr) = (*(addr) & ~(clearBits)) | (setBits); \
+ EnableGlobalIRQ(s_atomicOldInt); \
+ } while (0)
+
+#endif
+/* @} */
+
+/*! @name Timer utilities */
+/* @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000000U / (clockFreqInHz))
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000U / (clockFreqInHz))
+/* @} */
+
+/*! @name ISR exit barrier
+ * @{
+ *
+ * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ * exception return operation might vector to incorrect interrupt.
+ * For Cortex-M7, if core speed much faster than peripheral register write speed,
+ * the peripheral interrupt flags may be still set after exiting ISR, this results to
+ * the same error similar with errata 83869.
+ */
+#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U))
+#define SDK_ISR_EXIT_BARRIER __DSB()
+#else
+#define SDK_ISR_EXIT_BARRIER
+#endif
+
+/* @} */
+
+/*! @name Alignment variable definition macros */
+/* @{ */
+#if (defined(__ICCARM__))
+/*
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ * http:/ /supp.iar.com/Support/?note=24725
+ */
+_Pragma("diag_suppress=Pm120")
+#define SDK_PRAGMA(x) _Pragma(#x)
+_Pragma("diag_error=Pm120")
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
+#elif defined(__GNUC__)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#else
+#error Toolchain not supported
+#endif
+
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#endif
+
+/*! Macro to change a value to a given size aligned value */
+#define SDK_SIZEALIGN(var, alignbytes) \
+ ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
+/* @} */
+
+/*! @name Non-cacheable region definition macros */
+/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
+ * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
+ * will be initialized to zero in system startup.
+ */
+/* @{ */
+
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
+
+#if (defined(__ICCARM__))
+#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
+
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+ __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
+#if(defined(__CC_ARM))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+ __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
+#else
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+ __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
+#endif
+
+#elif(defined(__GNUC__))
+/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ */
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+ __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+ __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
+#else
+#error Toolchain not supported.
+#endif
+
+#else
+
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes)
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes)
+
+#endif
+
+/* @} */
+
+/*!
+ * @name Time sensitive region
+ * @{
+ */
+#if (defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE)
+
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
+#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#elif(defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+
+#else /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
+
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+
+#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
+/* @} */
+
+/*! @name Ram Function */
+#if (defined(__ICCARM__))
+#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#elif(defined(__GNUC__))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+/* @} */
+
+#if defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+void DefaultISR(void);
+#endif
+
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+ (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt enabled successfully
+ * @retval kStatus_Fail Failed to enable the interrupt
+ */
+static inline status_t EnableIRQ(IRQn_Type interrupt)
+{
+ status_t status = kStatus_Success;
+
+ if (NotAvail_IRQn == interrupt)
+ {
+ status = kStatus_Fail;
+ }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+ else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+ {
+ status = kStatus_Fail;
+ }
+#endif
+
+ else
+ {
+#if defined(__GIC_PRIO_BITS)
+ GIC_EnableIRQ(interrupt);
+#else
+ NVIC_EnableIRQ(interrupt);
+#endif
+ }
+
+ return status;
+}
+
+/*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt disabled successfully
+ * @retval kStatus_Fail Failed to disable the interrupt
+ */
+static inline status_t DisableIRQ(IRQn_Type interrupt)
+{
+ status_t status = kStatus_Success;
+
+ if (NotAvail_IRQn == interrupt)
+ {
+ status = kStatus_Fail;
+ }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+ else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+ {
+ status = kStatus_Fail;
+ }
+#endif
+
+ else
+ {
+#if defined(__GIC_PRIO_BITS)
+ GIC_DisableIRQ(interrupt);
+#else
+ NVIC_DisableIRQ(interrupt);
+#endif
+ }
+
+ return status;
+}
+
+/*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+static inline uint32_t DisableGlobalIRQ(void)
+{
+#if defined(CPSR_I_Msk)
+ uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
+
+ __disable_irq();
+
+ return cpsr;
+#else
+ uint32_t regPrimask = __get_PRIMASK();
+
+ __disable_irq();
+
+ return regPrimask;
+#endif
+}
+
+/*!
+ * @brief Enable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+static inline void EnableGlobalIRQ(uint32_t primask)
+{
+#if defined(CPSR_I_Msk)
+ __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#else
+ __set_PRIMASK(primask);
+#endif
+}
+
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+/*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ * @return The old IRQ handler address
+ */
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+/*
+ * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
+ * powerlib should be used instead of these functions.
+ */
+#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
+/*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
+ *
+ * @param interrupt The IRQ number.
+ */
+void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+/*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
+ *
+ * @param interrupt The IRQ number.
+ */
+void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_POWERLIB_EXTEND */
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @} */
+
+#endif /* _FSL_COMMON_ARM_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexcomm.c b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexcomm.c
new file mode 100644
index 000000000..7a21a1ce0
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexcomm.c
@@ -0,0 +1,412 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm"
+#endif
+
+/*!
+ * @brief Used for conversion between `void*` and `uint32_t`.
+ */
+typedef union pvoid_to_u32
+{
+ void *pvoid;
+ uint32_t u32;
+} pvoid_to_u32_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*! @brief Set the FLEXCOMM mode . */
+static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock);
+
+/*! @brief check whether flexcomm supports peripheral type */
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Array to map FLEXCOMM instance number to base address. */
+static const uint32_t s_flexcommBaseAddrs[] = FLEXCOMM_BASE_ADDRS;
+
+/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
+static flexcomm_irq_handler_t s_flexcommIrqHandler[ARRAY_SIZE(s_flexcommBaseAddrs)];
+
+/*! @brief Pointers to handles for each instance to provide context to interrupt routines */
+static void *s_flexcommHandle[ARRAY_SIZE(s_flexcommBaseAddrs)];
+
+/*! @brief Array to map FLEXCOMM instance number to IRQ number. */
+IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief IDs of clock for each FLEXCOMM module */
+static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)
+/*! @brief Pointers to FLEXCOMM resets for each instance. */
+static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS;
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* check whether flexcomm supports peripheral type */
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph)
+{
+ if (periph == FLEXCOMM_PERIPH_NONE)
+ {
+ return true;
+ }
+ else if (periph <= FLEXCOMM_PERIPH_I2S_TX)
+ {
+ return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false;
+ }
+ else if (periph == FLEXCOMM_PERIPH_I2S_RX)
+ {
+ return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false;
+ }
+ else
+ {
+ return false;
+ }
+}
+
+/* Get the index corresponding to the FLEXCOMM */
+/*! brief Returns instance number for FLEXCOMM module with given base address. */
+uint32_t FLEXCOMM_GetInstance(void *base)
+{
+ uint32_t i;
+ pvoid_to_u32_t BaseAddr;
+ BaseAddr.pvoid = base;
+
+ for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++)
+ {
+ if (BaseAddr.u32 == s_flexcommBaseAddrs[i])
+ {
+ break;
+ }
+ }
+
+ assert(i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT);
+ return i;
+}
+
+/* Changes FLEXCOMM mode */
+static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock)
+{
+ /* Check whether peripheral type is present */
+ if (!FLEXCOMM_PeripheralIsPresent(base, periph))
+ {
+ return kStatus_OutOfRange;
+ }
+
+ /* Flexcomm is locked to different peripheral type than expected */
+ if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) &&
+ ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph))
+ {
+ return kStatus_Fail;
+ }
+
+ /* Check if we are asked to lock */
+ if (lock != 0)
+ {
+ base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK;
+ }
+ else
+ {
+ base->PSELID = (uint32_t)periph;
+ }
+
+ return kStatus_Success;
+}
+
+/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)
+{
+ uint32_t idx = FLEXCOMM_GetInstance(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Enable the peripheral clock */
+ CLOCK_EnableClock(s_flexcommClocks[idx]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)
+ /* Reset the FLEXCOMM module */
+ RESET_PeripheralReset(s_flexcommResets[idx]);
+#endif
+
+ /* Set the FLEXCOMM to given peripheral */
+ return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0);
+}
+
+/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
+ * mode */
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(base);
+
+ /* Clear handler first to avoid execution of the handler with wrong handle */
+ s_flexcommIrqHandler[instance] = NULL;
+ s_flexcommHandle[instance] = flexcommHandle;
+ s_flexcommIrqHandler[instance] = handler;
+ SDK_ISR_EXIT_BARRIER;
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+#if defined(FLEXCOMM0)
+void FLEXCOMM0_DriverIRQHandler(void);
+void FLEXCOMM0_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM0);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM1)
+void FLEXCOMM1_DriverIRQHandler(void);
+void FLEXCOMM1_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM1);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM2)
+void FLEXCOMM2_DriverIRQHandler(void);
+void FLEXCOMM2_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM2);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM3)
+void FLEXCOMM3_DriverIRQHandler(void);
+void FLEXCOMM3_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM3);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM4)
+void FLEXCOMM4_DriverIRQHandler(void);
+void FLEXCOMM4_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM4);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+
+#endif
+
+#if defined(FLEXCOMM5)
+void FLEXCOMM5_DriverIRQHandler(void);
+void FLEXCOMM5_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM5);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM6)
+void FLEXCOMM6_DriverIRQHandler(void);
+void FLEXCOMM6_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM6);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM7)
+void FLEXCOMM7_DriverIRQHandler(void);
+void FLEXCOMM7_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM7);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM8)
+void FLEXCOMM8_DriverIRQHandler(void);
+void FLEXCOMM8_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM8);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM9)
+void FLEXCOMM9_DriverIRQHandler(void);
+void FLEXCOMM9_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM9);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM10)
+void FLEXCOMM10_DriverIRQHandler(void);
+void FLEXCOMM10_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM10);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM11)
+void FLEXCOMM11_DriverIRQHandler(void);
+void FLEXCOMM11_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM11);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM12)
+void FLEXCOMM12_DriverIRQHandler(void);
+void FLEXCOMM12_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM12);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM13)
+void FLEXCOMM13_DriverIRQHandler(void);
+void FLEXCOMM13_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM13);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM14)
+void FLEXCOMM14_DriverIRQHandler(void);
+void FLEXCOMM14_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM14);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM15)
+void FLEXCOMM15_DriverIRQHandler(void);
+void FLEXCOMM15_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM15);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXCOMM16)
+void FLEXCOMM16_DriverIRQHandler(void);
+void FLEXCOMM16_DriverIRQHandler(void)
+{
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM16);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexcomm.h b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexcomm.h
new file mode 100644
index 000000000..f96086fde
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexcomm.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_FLEXCOMM_H_
+#define _FSL_FLEXCOMM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flexcomm_driver
+ * @{
+ */
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexCOMM driver version 2.0.2. */
+#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*! @brief FLEXCOMM peripheral modes. */
+typedef enum
+{
+ FLEXCOMM_PERIPH_NONE, /*!< No peripheral */
+ FLEXCOMM_PERIPH_USART, /*!< USART peripheral */
+ FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */
+ FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */
+ FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */
+ FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */
+} FLEXCOMM_PERIPH_T;
+
+/*! @brief Typedef for interrupt handler. */
+typedef void (*flexcomm_irq_handler_t)(void *base, void *handle);
+
+/*! @brief Array with IRQ number for each FLEXCOMM module. */
+extern IRQn_Type const kFlexcommIrqs[];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @brief Returns instance number for FLEXCOMM module with given base address. */
+uint32_t FLEXCOMM_GetInstance(void *base);
+
+/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);
+
+/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
+ * mode */
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_FLEXCOMM_H_*/
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexspi.c b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexspi.c
new file mode 100644
index 000000000..ef72d3709
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexspi.c
@@ -0,0 +1,1157 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexspi.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexspi"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define FREQ_1MHz (1000000UL)
+#define FLEXSPI_DLLCR_DEFAULT (0x100UL)
+#define FLEXSPI_LUT_KEY_VAL (0x5AF05AF0UL)
+
+enum
+{
+ kFLEXSPI_DelayCellUnitMin = 75, /* 75ps. */
+ kFLEXSPI_DelayCellUnitMax = 225, /* 225ps. */
+};
+
+enum
+{
+ kFLEXSPI_FlashASampleClockSlaveDelayLocked =
+ FLEXSPI_STS2_ASLVLOCK_MASK, /* Flash A sample clock slave delay line locked. */
+ kFLEXSPI_FlashASampleClockRefDelayLocked =
+ FLEXSPI_STS2_AREFLOCK_MASK, /* Flash A sample clock reference delay line locked. */
+ kFLEXSPI_FlashBSampleClockSlaveDelayLocked =
+ FLEXSPI_STS2_BSLVLOCK_MASK, /* Flash B sample clock slave delay line locked. */
+ kFLEXSPI_FlashBSampleClockRefDelayLocked =
+ FLEXSPI_STS2_BREFLOCK_MASK, /* Flash B sample clock reference delay line locked. */
+};
+
+/*! @brief Common sets of flags used by the driver, _flexspi_flag_constants. */
+enum
+{
+ /*! IRQ sources enabled by the non-blocking transactional API. */
+ kIrqFlags = kFLEXSPI_IpTxFifoWatermarkEmptyFlag | kFLEXSPI_IpRxFifoWatermarkAvailableFlag |
+ kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag |
+ kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExecutionDoneFlag,
+
+ /*! Errors to check for. */
+ kErrorFlags = kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag |
+ kFLEXSPI_IpCommandGrantTimeoutFlag,
+};
+
+/* FLEXSPI transfer state, _flexspi_transfer_state. */
+enum
+{
+ kFLEXSPI_Idle = 0x0U, /*!< Transfer is done. */
+ kFLEXSPI_BusyWrite = 0x1U, /*!< FLEXSPI is busy write transfer. */
+ kFLEXSPI_BusyRead = 0x2U, /*!< FLEXSPI is busy write transfer. */
+};
+
+/*! @brief Typedef for interrupt handler. */
+typedef void (*flexspi_isr_t)(FLEXSPI_Type *base, flexspi_handle_t *handle);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static void FLEXSPI_Memset(void *src, uint8_t value, size_t length);
+
+/*!
+ * @brief Calculate flash A/B sample clock DLL.
+ *
+ * @param base FLEXSPI base pointer.
+ * @param config Flash configuration parameters.
+ */
+static uint32_t FLEXSPI_CalculateDll(FLEXSPI_Type *base, flexspi_device_config_t *config);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to flexspi bases for each instance. */
+static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS;
+
+/*! @brief Pointers to flexspi IRQ number for each instance. */
+static const IRQn_Type s_flexspiIrqs[] = FLEXSPI_IRQS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Clock name array */
+static const clock_ip_name_t s_flexspiClock[] = FLEXSPI_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+/*! @brief Pointers to flexspi handles for each instance. */
+static flexspi_handle_t *s_flexspiHandle[ARRAY_SIZE(s_flexspiBases)];
+#endif
+
+#if defined(FSL_FEATURE_FLEXSPI_HAS_RESET) && FSL_FEATURE_FLEXSPI_HAS_RESET
+/*! @brief Pointers to FLEXSPI resets for each instance. */
+static const reset_ip_name_t s_flexspiResets[] = FLEXSPI_RSTS;
+#endif
+
+#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+/*! @brief Pointer to flexspi IRQ handler. */
+static flexspi_isr_t s_flexspiIsr;
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* To avoid compiler opitimizing this API into memset() in library. */
+#if defined(__ICCARM__)
+#pragma optimize = none
+#endif /* defined(__ICCARM__) */
+static void FLEXSPI_Memset(void *src, uint8_t value, size_t length)
+{
+ assert(src != NULL);
+ uint8_t *p = src;
+
+ for (uint32_t i = 0U; i < length; i++)
+ {
+ *p = value;
+ p++;
+ }
+}
+
+uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
+{
+ uint32_t instance;
+
+ /* Find the instance index from base address mappings. */
+ for (instance = 0; instance < ARRAY_SIZE(s_flexspiBases); instance++)
+ {
+ if (s_flexspiBases[instance] == base)
+ {
+ break;
+ }
+ }
+
+ assert(instance < ARRAY_SIZE(s_flexspiBases));
+
+ return instance;
+}
+
+static uint32_t FLEXSPI_CalculateDll(FLEXSPI_Type *base, flexspi_device_config_t *config)
+{
+ bool isUnifiedConfig = true;
+ uint32_t flexspiDllValue;
+ uint32_t dllValue;
+ uint32_t temp;
+#if defined(FSL_FEATURE_FLEXSPI_DQS_DELAY_PS) && FSL_FEATURE_FLEXSPI_DQS_DELAY_PS
+ uint32_t internalDqsDelayPs = FSL_FEATURE_FLEXSPI_DQS_DELAY_PS;
+#endif
+ uint32_t rxSampleClock = (base->MCR0 & FLEXSPI_MCR0_RXCLKSRC_MASK) >> FLEXSPI_MCR0_RXCLKSRC_SHIFT;
+ switch (rxSampleClock)
+ {
+ case (uint32_t)kFLEXSPI_ReadSampleClkLoopbackInternally:
+ case (uint32_t)kFLEXSPI_ReadSampleClkLoopbackFromDqsPad:
+ case (uint32_t)kFLEXSPI_ReadSampleClkLoopbackFromSckPad:
+ isUnifiedConfig = true;
+ break;
+ case (uint32_t)kFLEXSPI_ReadSampleClkExternalInputFromDqsPad:
+ if (config->isSck2Enabled)
+ {
+ isUnifiedConfig = true;
+ }
+ else
+ {
+ isUnifiedConfig = false;
+ }
+ break;
+ default:
+ assert(false);
+ break;
+ }
+
+ if (isUnifiedConfig)
+ {
+ flexspiDllValue = FLEXSPI_DLLCR_DEFAULT; /* 1 fixed delay cells in DLL delay chain) */
+ }
+ else
+ {
+ if (config->flexspiRootClk >= 100U * FREQ_1MHz)
+ {
+#if defined(FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN) && FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN
+ /* DLLEN = 1, SLVDLYTARGET = 0x0, */
+ flexspiDllValue = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x00);
+#else
+ /* DLLEN = 1, SLVDLYTARGET = 0xF, */
+ flexspiDllValue = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x0F);
+#endif
+ }
+ else
+ {
+ temp = (uint32_t)config->dataValidTime * 1000U; /* Convert data valid time in ns to ps. */
+ dllValue = temp / (uint32_t)kFLEXSPI_DelayCellUnitMin;
+ if (dllValue * (uint32_t)kFLEXSPI_DelayCellUnitMin < temp)
+ {
+ dllValue++;
+ }
+ flexspiDllValue = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(dllValue);
+ }
+ }
+ return flexspiDllValue;
+}
+
+status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
+{
+ status_t result = kStatus_Success;
+
+ /* Check for error. */
+ status &= (uint32_t)kErrorFlags;
+ if (0U != status)
+ {
+ /* Select the correct error code.. */
+ if (0U != (status & (uint32_t)kFLEXSPI_SequenceExecutionTimeoutFlag))
+ {
+ result = kStatus_FLEXSPI_SequenceExecutionTimeout;
+ }
+ else if (0U != (status & (uint32_t)kFLEXSPI_IpCommandSequenceErrorFlag))
+ {
+ result = kStatus_FLEXSPI_IpCommandSequenceError;
+ }
+ else if (0U != (status & (uint32_t)kFLEXSPI_IpCommandGrantTimeoutFlag))
+ {
+ result = kStatus_FLEXSPI_IpCommandGrantTimeout;
+ }
+ else
+ {
+ assert(false);
+ }
+
+ /* Clear the flags. */
+ FLEXSPI_ClearInterruptStatusFlags(base, status);
+
+ /* Reset fifos. These flags clear automatically. */
+ base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
+ base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;
+ }
+
+ return result;
+}
+
+/*!
+ * brief Initializes the FLEXSPI module and internal state.
+ *
+ * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the
+ * input configure parameters. Users should call this function before any FLEXSPI operations.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param config FLEXSPI configure structure.
+ */
+void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
+{
+ uint32_t configValue = 0;
+ uint8_t i = 0;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Enable the flexspi clock */
+ (void)CLOCK_EnableClock(s_flexspiClock[FLEXSPI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(FSL_FEATURE_FLEXSPI_HAS_RESET) && FSL_FEATURE_FLEXSPI_HAS_RESET
+ /* Reset the FLEXSPI module */
+ RESET_PeripheralReset(s_flexspiResets[FLEXSPI_GetInstance(base)]);
+#endif
+
+ /* Reset peripheral before configuring it. */
+ base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+ FLEXSPI_SoftwareReset(base);
+
+ /* Configure MCR0 configuration items. */
+ configValue = FLEXSPI_MCR0_RXCLKSRC(config->rxSampleClock) | FLEXSPI_MCR0_DOZEEN(config->enableDoze) |
+ FLEXSPI_MCR0_IPGRANTWAIT(config->ipGrantTimeoutCycle) |
+ FLEXSPI_MCR0_AHBGRANTWAIT(config->ahbConfig.ahbGrantTimeoutCycle) |
+ FLEXSPI_MCR0_SCKFREERUNEN(config->enableSckFreeRunning) |
+ FLEXSPI_MCR0_HSEN(config->enableHalfSpeedAccess) |
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
+ FLEXSPI_MCR0_COMBINATIONEN(config->enableCombination) |
+#endif
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN)
+ FLEXSPI_MCR0_ATDFEN(config->ahbConfig.enableAHBWriteIpTxFifo) |
+#endif
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN)
+ FLEXSPI_MCR0_ARDFEN(config->ahbConfig.enableAHBWriteIpRxFifo) |
+#endif
+ FLEXSPI_MCR0_MDIS_MASK;
+ base->MCR0 = configValue;
+
+ /* Configure MCR1 configurations. */
+ configValue =
+ FLEXSPI_MCR1_SEQWAIT(config->seqTimeoutCycle) | FLEXSPI_MCR1_AHBBUSWAIT(config->ahbConfig.ahbBusTimeoutCycle);
+ base->MCR1 = configValue;
+
+ /* Configure MCR2 configurations. */
+ configValue = base->MCR2;
+ configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK | FLEXSPI_MCR2_SCKBDIFFOPT_MASK | FLEXSPI_MCR2_SAMEDEVICEEN_MASK |
+ FLEXSPI_MCR2_CLRAHBBUFOPT_MASK);
+ configValue |= FLEXSPI_MCR2_RESUMEWAIT(config->ahbConfig.resumeWaitCycle) |
+ FLEXSPI_MCR2_SCKBDIFFOPT(config->enableSckBDiffOpt) |
+ FLEXSPI_MCR2_SAMEDEVICEEN(config->enableSameConfigForAll) |
+ FLEXSPI_MCR2_CLRAHBBUFOPT(config->ahbConfig.enableClearAHBBufferOpt);
+
+ base->MCR2 = configValue;
+
+ /* Configure AHB control items. */
+ configValue = base->AHBCR;
+ configValue &= ~(FLEXSPI_AHBCR_READADDROPT_MASK | FLEXSPI_AHBCR_PREFETCHEN_MASK | FLEXSPI_AHBCR_BUFFERABLEEN_MASK |
+ FLEXSPI_AHBCR_CACHABLEEN_MASK);
+ configValue |= FLEXSPI_AHBCR_READADDROPT(config->ahbConfig.enableReadAddressOpt) |
+ FLEXSPI_AHBCR_PREFETCHEN(config->ahbConfig.enableAHBPrefetch) |
+ FLEXSPI_AHBCR_BUFFERABLEEN(config->ahbConfig.enableAHBBufferable) |
+ FLEXSPI_AHBCR_CACHABLEEN(config->ahbConfig.enableAHBCachable);
+ base->AHBCR = configValue;
+
+ /* Configure AHB rx buffers. */
+ for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++)
+ {
+ configValue = base->AHBRXBUFCR0[i];
+
+ configValue &= ~(FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK |
+ FLEXSPI_AHBRXBUFCR0_MSTRID_MASK | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK);
+ configValue |= FLEXSPI_AHBRXBUFCR0_PREFETCHEN(config->ahbConfig.buffer[i].enablePrefetch) |
+ FLEXSPI_AHBRXBUFCR0_PRIORITY(config->ahbConfig.buffer[i].priority) |
+ FLEXSPI_AHBRXBUFCR0_MSTRID(config->ahbConfig.buffer[i].masterIndex) |
+ FLEXSPI_AHBRXBUFCR0_BUFSZ((uint32_t)config->ahbConfig.buffer[i].bufferSize / 8U);
+ base->AHBRXBUFCR0[i] = configValue;
+ }
+
+ /* Configure IP Fifo watermarks. */
+ base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXWMRK_MASK;
+ base->IPRXFCR |= FLEXSPI_IPRXFCR_RXWMRK((uint32_t)config->rxWatermark / 8U - 1U);
+ base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXWMRK_MASK;
+ base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK((uint32_t)config->txWatermark / 8U - 1U);
+
+ /* Reset flash size on all ports */
+ for (i = 0; i < (uint32_t)kFLEXSPI_PortCount; i++)
+ {
+ base->FLSHCR0[i] = 0;
+ }
+}
+
+/*!
+ * brief Gets default settings for FLEXSPI.
+ *
+ * param config FLEXSPI configuration structure.
+ */
+void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
+{
+ /* Initializes the configure structure to zero. */
+ FLEXSPI_Memset(config, 0, sizeof(*config));
+
+ config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally;
+ config->enableSckFreeRunning = false;
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
+ config->enableCombination = false;
+#endif
+ config->enableDoze = true;
+ config->enableHalfSpeedAccess = false;
+ config->enableSckBDiffOpt = false;
+ config->enableSameConfigForAll = false;
+ config->seqTimeoutCycle = 0xFFFFU;
+ config->ipGrantTimeoutCycle = 0xFFU;
+ config->txWatermark = 8;
+ config->rxWatermark = 8;
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN)
+ config->ahbConfig.enableAHBWriteIpTxFifo = false;
+#endif
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN)
+ config->ahbConfig.enableAHBWriteIpRxFifo = false;
+#endif
+ config->ahbConfig.ahbGrantTimeoutCycle = 0xFFU;
+ config->ahbConfig.ahbBusTimeoutCycle = 0xFFFFU;
+ config->ahbConfig.resumeWaitCycle = 0x20U;
+ FLEXSPI_Memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer));
+ /* Use invalid master ID 0xF and buffer size 0 for the first several buffers. */
+ for (uint8_t i = 0; i < ((uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 2U); i++)
+ {
+ config->ahbConfig.buffer[i].enablePrefetch = true; /* Default enable AHB prefetch. */
+ config->ahbConfig.buffer[i].masterIndex = 0xFU; /* Invalid master index which is not used, so will never hit. */
+ config->ahbConfig.buffer[i].bufferSize =
+ 0; /* Default buffer size 0 for buffer0 to buffer(FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 3U)*/
+ }
+
+ for (uint8_t i = ((uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 2U);
+ i < (uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++)
+ {
+ config->ahbConfig.buffer[i].enablePrefetch = true; /* Default enable AHB prefetch. */
+ config->ahbConfig.buffer[i].bufferSize = 256U; /* Default buffer size 256 bytes. */
+ }
+ config->ahbConfig.enableClearAHBBufferOpt = false;
+ config->ahbConfig.enableReadAddressOpt = false;
+ config->ahbConfig.enableAHBPrefetch = false;
+ config->ahbConfig.enableAHBBufferable = false;
+ config->ahbConfig.enableAHBCachable = false;
+}
+
+/*!
+ * brief Deinitializes the FLEXSPI module.
+ *
+ * Clears the FLEXSPI state and FLEXSPI module registers.
+ * param base FLEXSPI peripheral base address.
+ */
+void FLEXSPI_Deinit(FLEXSPI_Type *base)
+{
+ /* Reset peripheral. */
+ FLEXSPI_SoftwareReset(base);
+}
+
+/*!
+ * brief Update FLEXSPI DLL value depending on currently flexspi root clock.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param config Flash configuration parameters.
+ * param port FLEXSPI Operation port.
+ */
+void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
+{
+ uint32_t configValue = 0;
+ uint32_t statusValue = 0;
+ uint8_t index = (uint8_t)port >> 1U; /* PortA with index 0, PortB with index 1. */
+
+ /* Wait for bus to be idle before changing flash configuration. */
+ while (!FLEXSPI_GetBusIdleStatus(base))
+ {
+ }
+
+ /* Configure DLL. */
+ configValue = FLEXSPI_CalculateDll(base, config);
+ base->DLLCR[index] = configValue;
+
+ /* Exit stop mode. */
+ base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+
+ /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
+ statusValue =
+ (index == 0U) ?
+ ((uint32_t)kFLEXSPI_FlashASampleClockSlaveDelayLocked |
+ (uint32_t)kFLEXSPI_FlashASampleClockRefDelayLocked) :
+ ((uint32_t)kFLEXSPI_FlashBSampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashBSampleClockRefDelayLocked);
+
+ if (0U != (configValue & FLEXSPI_DLLCR_DLLEN_MASK))
+ {
+ /* Wait slave delay line locked and slave reference delay line locked. */
+ while ((base->STS2 & statusValue) != statusValue)
+ {
+ }
+
+ /* Wait at least 100 NOPs*/
+ for (uint8_t delay = 100U; delay > 0U; delay--)
+ {
+ __NOP();
+ }
+ }
+}
+
+/*!
+ * brief Configures the connected device parameter.
+ *
+ * This function configures the connected device relevant parameters, such as the size, command, and so on.
+ * The flash configuration value cannot have a default value. The user needs to configure it according to the
+ * connected device.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param config Flash configuration parameters.
+ * param port FLEXSPI Operation port.
+ */
+void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
+{
+ uint32_t configValue = 0;
+ uint8_t index = (uint8_t)port >> 1U; /* PortA with index 0, PortB with index 1. */
+
+ /* Wait for bus to be idle before changing flash configuration. */
+ while (!FLEXSPI_GetBusIdleStatus(base))
+ {
+ }
+
+ /* Configure flash size. */
+ base->FLSHCR0[port] = config->flashSize;
+
+ /* Configure flash parameters. */
+ base->FLSHCR1[port] = FLEXSPI_FLSHCR1_CSINTERVAL(config->CSInterval) |
+ FLEXSPI_FLSHCR1_CSINTERVALUNIT(config->CSIntervalUnit) |
+ FLEXSPI_FLSHCR1_TCSH(config->CSHoldTime) | FLEXSPI_FLSHCR1_TCSS(config->CSSetupTime) |
+ FLEXSPI_FLSHCR1_CAS(config->columnspace) | FLEXSPI_FLSHCR1_WA(config->enableWordAddress);
+
+ /* Configure AHB operation items. */
+ configValue = base->FLSHCR2[port];
+
+ configValue &= ~(FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK | FLEXSPI_FLSHCR2_AWRWAIT_MASK | FLEXSPI_FLSHCR2_AWRSEQNUM_MASK |
+ FLEXSPI_FLSHCR2_AWRSEQID_MASK | FLEXSPI_FLSHCR2_ARDSEQNUM_MASK | FLEXSPI_FLSHCR2_ARDSEQID_MASK);
+
+ configValue |=
+ FLEXSPI_FLSHCR2_AWRWAITUNIT(config->AHBWriteWaitUnit) | FLEXSPI_FLSHCR2_AWRWAIT(config->AHBWriteWaitInterval);
+
+ if (config->AWRSeqNumber > 0U)
+ {
+ configValue |= FLEXSPI_FLSHCR2_AWRSEQID((uint32_t)config->AWRSeqIndex) |
+ FLEXSPI_FLSHCR2_AWRSEQNUM((uint32_t)config->AWRSeqNumber - 1U);
+ }
+
+ if (config->ARDSeqNumber > 0U)
+ {
+ configValue |= FLEXSPI_FLSHCR2_ARDSEQID((uint32_t)config->ARDSeqIndex) |
+ FLEXSPI_FLSHCR2_ARDSEQNUM((uint32_t)config->ARDSeqNumber - 1U);
+ }
+
+ base->FLSHCR2[port] = configValue;
+
+ /* Configure DLL. */
+ FLEXSPI_UpdateDllValue(base, config, port);
+
+ /* Step into stop mode. */
+ base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
+
+ /* Configure write mask. */
+ if (config->enableWriteMask)
+ {
+ base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMOPT1_MASK;
+ }
+ else
+ {
+ base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMOPT1_MASK;
+ }
+
+ if (index == 0U) /*PortA*/
+ {
+ base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENA_MASK;
+ base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENA(config->enableWriteMask);
+ }
+ else
+ {
+ base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENB_MASK;
+ base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENB(config->enableWriteMask);
+ }
+
+ /* Exit stop mode. */
+ base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+
+ /* Wait for bus to be idle before use it access to external flash. */
+ while (!FLEXSPI_GetBusIdleStatus(base))
+ {
+ }
+}
+
+/*! brief Updates the LUT table.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param index From which index start to update. It could be any index of the LUT table, which
+ * also allows user to update command content inside a command. Each command consists of up to
+ * 8 instructions and occupy 4*32-bit memory.
+ * param cmd Command sequence array.
+ * param count Number of sequences.
+ */
+void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)
+{
+ assert(index < 64U);
+
+ uint32_t i = 0;
+ volatile uint32_t *lutBase;
+
+ /* Wait for bus to be idle before changing flash configuration. */
+ while (!FLEXSPI_GetBusIdleStatus(base))
+ {
+ }
+
+ /* Unlock LUT for update. */
+ base->LUTKEY = FLEXSPI_LUT_KEY_VAL;
+ base->LUTCR = 0x02;
+
+ lutBase = &base->LUT[index];
+ for (i = 0; i < count; i++)
+ {
+ *lutBase++ = *cmd++;
+ }
+
+ /* Lock LUT. */
+ base->LUTKEY = FLEXSPI_LUT_KEY_VAL;
+ base->LUTCR = 0x01;
+}
+
+/*! brief Update read sample clock source
+ *
+ * param base FLEXSPI peripheral base address.
+ * param clockSource clockSource of type #flexspi_read_sample_clock_t
+ */
+void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource)
+{
+ uint32_t mcr0Val;
+
+ /* Wait for bus to be idle before changing flash configuration. */
+ while (!FLEXSPI_GetBusIdleStatus(base))
+ {
+ }
+
+ mcr0Val = base->MCR0;
+ mcr0Val &= ~FLEXSPI_MCR0_RXCLKSRC_MASK;
+ mcr0Val |= FLEXSPI_MCR0_RXCLKSRC(clockSource);
+ base->MCR0 = mcr0Val;
+
+ /* Reset peripheral. */
+ FLEXSPI_SoftwareReset(base);
+}
+
+/*!
+ * brief Sends a buffer of data bytes using blocking method.
+ * note This function blocks via polling until all bytes have been sent.
+ * param base FLEXSPI peripheral base address
+ * param buffer The data bytes to send
+ * param size The number of data bytes to send
+ * retval kStatus_Success write success without error
+ * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
+ * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
+ * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
+ */
+status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
+{
+ uint32_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1U;
+ uint32_t status;
+ status_t result = kStatus_Success;
+ uint32_t i = 0;
+
+ /* Send data buffer */
+ while (0U != size)
+ {
+ /* Wait until there is room in the fifo. This also checks for errors. */
+ while (0U == ((status = base->INTR) & (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag))
+ {
+ }
+
+ result = FLEXSPI_CheckAndClearError(base, status);
+
+ if (kStatus_Success != result)
+ {
+ return result;
+ }
+
+ /* Write watermark level data into tx fifo . */
+ if (size >= 8U * txWatermark)
+ {
+ for (i = 0U; i < 2U * txWatermark; i++)
+ {
+ base->TFDR[i] = *buffer++;
+ }
+
+ size = size - 8U * txWatermark;
+ }
+ else
+ {
+ for (i = 0U; i < ((size + 3U) / 4U); i++)
+ {
+ base->TFDR[i] = *buffer++;
+ }
+ size = 0U;
+ }
+
+ /* Push a watermark level data into IP TX FIFO. */
+ base->INTR |= (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag;
+ }
+
+ return result;
+}
+
+/*!
+ * brief Receives a buffer of data bytes using a blocking method.
+ * note This function blocks via polling until all bytes have been sent.
+ * param base FLEXSPI peripheral base address
+ * param buffer The data bytes to send
+ * param size The number of data bytes to receive
+ * retval kStatus_Success read success without error
+ * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
+ * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
+ * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
+ */
+status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
+{
+ uint32_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1U;
+ uint32_t status;
+ status_t result = kStatus_Success;
+ uint32_t i = 0;
+ bool isReturn = false;
+
+ /* Send data buffer */
+ while (0U != size)
+ {
+ if (size >= 8U * rxWatermark)
+ {
+ /* Wait until there is room in the fifo. This also checks for errors. */
+ while (0U == ((status = base->INTR) & (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag))
+ {
+ result = FLEXSPI_CheckAndClearError(base, status);
+
+ if (kStatus_Success != result)
+ {
+ isReturn = true;
+ break;
+ }
+ }
+ }
+ else
+ {
+ /* Wait fill level. This also checks for errors. */
+ while (size > ((((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U))
+ {
+ result = FLEXSPI_CheckAndClearError(base, base->INTR);
+
+ if (kStatus_Success != result)
+ {
+ isReturn = true;
+ break;
+ }
+ }
+ }
+
+ if (isReturn)
+ {
+ break;
+ }
+
+ result = FLEXSPI_CheckAndClearError(base, base->INTR);
+
+ if (kStatus_Success != result)
+ {
+ break;
+ }
+
+ /* Read watermark level data from rx fifo . */
+ if (size >= 8U * rxWatermark)
+ {
+ for (i = 0U; i < 2U * rxWatermark; i++)
+ {
+ *buffer++ = base->RFDR[i];
+ }
+
+ size = size - 8U * rxWatermark;
+ }
+ else
+ {
+ for (i = 0U; i < ((size + 3U) / 4U); i++)
+ {
+ *buffer++ = base->RFDR[i];
+ }
+ size = 0;
+ }
+
+ /* Pop out a watermark level datas from IP RX FIFO. */
+ base->INTR |= (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
+ }
+
+ return result;
+}
+
+/*!
+ * brief Execute command to transfer a buffer data bytes using a blocking method.
+ * param base FLEXSPI peripheral base address
+ * param xfer pointer to the transfer structure.
+ * retval kStatus_Success command transfer success without error
+ * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
+ * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
+ * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
+ */
+status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
+{
+ uint32_t configValue = 0;
+ status_t result = kStatus_Success;
+
+ /* Clear sequence pointer before sending data to external devices. */
+ base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK;
+
+ /* Clear former pending status before start this transfer. */
+ base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
+ FLEXSPI_INTR_IPCMDGE_MASK;
+
+ /* Configure base address. */
+ base->IPCR0 = xfer->deviceAddress;
+
+ /* Reset fifos. */
+ base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
+ base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;
+
+ /* Configure data size. */
+ if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config))
+ {
+ configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize);
+ }
+
+ /* Configure sequence ID. */
+ configValue |=
+ FLEXSPI_IPCR1_ISEQID((uint32_t)xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM((uint32_t)xfer->SeqNumber - 1U);
+ base->IPCR1 = configValue;
+
+ /* Start Transfer. */
+ base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK;
+
+ if ((xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config))
+ {
+ result = FLEXSPI_WriteBlocking(base, xfer->data, xfer->dataSize);
+ }
+ else if (xfer->cmdType == kFLEXSPI_Read)
+ {
+ result = FLEXSPI_ReadBlocking(base, xfer->data, xfer->dataSize);
+ }
+ else
+ {
+ /* Empty else. */
+ }
+
+ /* Wait for bus to be idle before changing flash configuration. */
+ while (!FLEXSPI_GetBusIdleStatus(base))
+ {
+ }
+
+ if (xfer->cmdType == kFLEXSPI_Command)
+ {
+ result = FLEXSPI_CheckAndClearError(base, base->INTR);
+ }
+
+ return result;
+}
+
+/*!
+ * brief Initializes the FLEXSPI handle which is used in transactional functions.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param handle pointer to flexspi_handle_t structure to store the transfer state.
+ * param callback pointer to user callback function.
+ * param userData user parameter passed to the callback function.
+ */
+void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
+ flexspi_handle_t *handle,
+ flexspi_transfer_callback_t callback,
+ void *userData)
+{
+ assert(NULL != handle);
+
+ uint32_t instance = FLEXSPI_GetInstance(base);
+
+ /* Zero handle. */
+ (void)memset(handle, 0, sizeof(*handle));
+
+ /* Set callback and userData. */
+ handle->completionCallback = callback;
+ handle->userData = userData;
+
+#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+ /* Save the context in global variables to support the double weak mechanism. */
+ s_flexspiHandle[instance] = handle;
+ s_flexspiIsr = FLEXSPI_TransferHandleIRQ;
+#endif
+
+ /* Enable NVIC interrupt. */
+ (void)EnableIRQ(s_flexspiIrqs[instance]);
+}
+
+/*!
+ * brief Performs a interrupt non-blocking transfer on the FLEXSPI bus.
+ *
+ * note Calling the API returns immediately after transfer initiates. The user needs
+ * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether
+ * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer
+ * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or
+ * FLEXSPI could not read data properly.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param handle pointer to flexspi_handle_t structure which stores the transfer state.
+ * param xfer pointer to flexspi_transfer_t structure.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_FLEXSPI_Busy Previous transmission still not finished.
+ */
+status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer)
+{
+ uint32_t configValue = 0;
+ status_t result = kStatus_Success;
+
+ assert(NULL != handle);
+ assert(NULL != xfer);
+
+ /* Check if the I2C bus is idle - if not return busy status. */
+ if (handle->state != (uint32_t)kFLEXSPI_Idle)
+ {
+ result = kStatus_FLEXSPI_Busy;
+ }
+ else
+ {
+ handle->data = xfer->data;
+ handle->dataSize = xfer->dataSize;
+ handle->transferTotalSize = xfer->dataSize;
+ handle->state = (xfer->cmdType == kFLEXSPI_Read) ? (uint32_t)kFLEXSPI_BusyRead : (uint32_t)kFLEXSPI_BusyWrite;
+
+ /* Clear sequence pointer before sending data to external devices. */
+ base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK;
+
+ /* Clear former pending status before start this transfer. */
+ base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
+ FLEXSPI_INTR_IPCMDGE_MASK;
+
+ /* Configure base address. */
+ base->IPCR0 = xfer->deviceAddress;
+
+ /* Reset fifos. */
+ base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
+ base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;
+
+ /* Configure data size. */
+ if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write))
+ {
+ configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize);
+ }
+
+ /* Configure sequence ID. */
+ configValue |=
+ FLEXSPI_IPCR1_ISEQID((uint32_t)xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM((uint32_t)xfer->SeqNumber - 1U);
+ base->IPCR1 = configValue;
+
+ /* Start Transfer. */
+ base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK;
+
+ if (handle->state == (uint32_t)kFLEXSPI_BusyRead)
+ {
+ FLEXSPI_EnableInterrupts(base, (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag |
+ (uint32_t)kFLEXSPI_SequenceExecutionTimeoutFlag |
+ (uint32_t)kFLEXSPI_IpCommandSequenceErrorFlag |
+ (uint32_t)kFLEXSPI_IpCommandGrantTimeoutFlag |
+ (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag);
+ }
+ else
+ {
+ FLEXSPI_EnableInterrupts(
+ base, (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag | (uint32_t)kFLEXSPI_SequenceExecutionTimeoutFlag |
+ (uint32_t)kFLEXSPI_IpCommandSequenceErrorFlag | (uint32_t)kFLEXSPI_IpCommandGrantTimeoutFlag |
+ (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag);
+ }
+ }
+
+ return result;
+}
+
+/*!
+ * brief Gets the master transfer status during a interrupt non-blocking transfer.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param handle pointer to flexspi_handle_t structure which stores the transfer state.
+ * param count Number of bytes transferred so far by the non-blocking transaction.
+ * retval kStatus_InvalidArgument count is Invalid.
+ * retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)
+{
+ assert(NULL != handle);
+
+ status_t result = kStatus_Success;
+
+ if (handle->state == (uint32_t)kFLEXSPI_Idle)
+ {
+ result = kStatus_NoTransferInProgress;
+ }
+ else
+ {
+ *count = handle->transferTotalSize - handle->dataSize;
+ }
+
+ return result;
+}
+
+/*!
+ * brief Aborts an interrupt non-blocking transfer early.
+ *
+ * note This API can be called at any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param handle pointer to flexspi_handle_t structure which stores the transfer state
+ */
+void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
+{
+ assert(NULL != handle);
+
+ FLEXSPI_DisableInterrupts(base, (uint32_t)kIrqFlags);
+ handle->state = (uint32_t)kFLEXSPI_Idle;
+}
+
+/*!
+ * brief Master interrupt handler.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param handle pointer to flexspi_handle_t structure.
+ */
+void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
+{
+ uint32_t status;
+ status_t result;
+ uint32_t intEnableStatus;
+ uint32_t txWatermark;
+ uint32_t rxWatermark;
+ uint8_t i = 0;
+
+ status = base->INTR;
+ intEnableStatus = base->INTEN;
+
+ /* Check if interrupt is enabled and status is alerted. */
+ if ((status & intEnableStatus) != 0U)
+ {
+ result = FLEXSPI_CheckAndClearError(base, status);
+
+ if ((result != kStatus_Success) && (handle->completionCallback != NULL))
+ {
+ FLEXSPI_TransferAbort(base, handle);
+ if (NULL != handle->completionCallback)
+ {
+ handle->completionCallback(base, handle, result, handle->userData);
+ }
+ }
+ else
+ {
+ if ((0U != (status & (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag)) &&
+ (handle->state == (uint32_t)kFLEXSPI_BusyRead))
+ {
+ rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1U;
+
+ /* Read watermark level data from rx fifo . */
+ if (handle->dataSize >= 8U * rxWatermark)
+ {
+ /* Read watermark level data from rx fifo . */
+ for (i = 0U; i < 2U * rxWatermark; i++)
+ {
+ *handle->data++ = base->RFDR[i];
+ }
+
+ handle->dataSize = handle->dataSize - 8U * rxWatermark;
+ }
+ else
+ {
+ for (i = 0; i < (handle->dataSize + 3U) / 4U; i++)
+ {
+ *handle->data++ = base->RFDR[i];
+ }
+ handle->dataSize = 0;
+ }
+ /* Pop out a watermark level data from IP RX FIFO. */
+ base->INTR |= (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
+ }
+
+ if (0U != (status & (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag))
+ {
+ base->INTR |= (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag;
+
+ FLEXSPI_TransferAbort(base, handle);
+
+ if (NULL != handle->completionCallback)
+ {
+ handle->completionCallback(base, handle, kStatus_Success, handle->userData);
+ }
+ }
+
+ /* TX FIFO empty interrupt, push watermark level data into tx FIFO. */
+ if ((0U != (status & (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag)) &&
+ (handle->state == (uint32_t)kFLEXSPI_BusyWrite))
+ {
+ if (0U != handle->dataSize)
+ {
+ txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1U;
+ /* Write watermark level data into tx fifo . */
+ if (handle->dataSize >= 8U * txWatermark)
+ {
+ for (i = 0; i < 2U * txWatermark; i++)
+ {
+ base->TFDR[i] = *handle->data++;
+ }
+
+ handle->dataSize = handle->dataSize - 8U * txWatermark;
+ }
+ else
+ {
+ for (i = 0; i < (handle->dataSize + 3U) / 4U; i++)
+ {
+ base->TFDR[i] = *handle->data++;
+ }
+ handle->dataSize = 0;
+ }
+
+ /* Push a watermark level data into IP TX FIFO. */
+ base->INTR |= (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag;
+ }
+ }
+ else
+ {
+ /* Empty else */
+ }
+ }
+ }
+ else
+ {
+ /* Empty else */
+ }
+}
+
+#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+#if defined(FLEXSPI)
+void FLEXSPI_DriverIRQHandler(void);
+void FLEXSPI_DriverIRQHandler(void)
+{
+ s_flexspiIsr(FLEXSPI, s_flexspiHandle[0]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FLEXSPI0)
+void FLEXSPI0_DriverIRQHandler(void);
+void FLEXSPI0_DriverIRQHandler(void)
+{
+ s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#if defined(FLEXSPI1)
+void FLEXSPI1_DriverIRQHandler(void);
+void FLEXSPI1_DriverIRQHandler(void)
+{
+ s_flexspiIsr(FLEXSPI1, s_flexspiHandle[1]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(LSIO__FLEXSPI0)
+void LSIO_OCTASPI0_INT_DriverIRQHandler(void);
+void LSIO_OCTASPI0_INT_DriverIRQHandler(void)
+{
+ s_flexspiIsr(LSIO__FLEXSPI0, s_flexspiHandle[0]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#if defined(LSIO__FLEXSPI1)
+void LSIO_OCTASPI1_INT_DriverIRQHandler(void);
+void LSIO_OCTASPI1_INT_DriverIRQHandler(void)
+{
+ s_flexspiIsr(LSIO__FLEXSPI1, s_flexspiHandle[1]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1
+
+void FLEXSPI0_FLEXSPI1_DriverIRQHandler(void);
+void FLEXSPI0_FLEXSPI1_DriverIRQHandler(void)
+{
+ /* If handle is registered, treat the transfer function is enabled. */
+ if (NULL != s_flexspiHandle[0])
+ {
+ s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]);
+ }
+ if (NULL != s_flexspiHandle[1])
+ {
+ s_flexspiIsr(FLEXSPI1, s_flexspiHandle[1]);
+ }
+}
+#endif
+
+#endif
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexspi.h b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexspi.h
new file mode 100644
index 000000000..e009fec11
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_flexspi.h
@@ -0,0 +1,864 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_FLEXSPI_H_
+#define __FSL_FLEXSPI_H_
+
+#include <stddef.h>
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flexspi
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FLEXSPI driver version 2.3.5. */
+#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 5))
+/*@}*/
+
+#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)
+
+/*! @brief Formula to form FLEXSPI instructions in LUT table. */
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
+ (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+ FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+/*! @brief Status structure of FLEXSPI.*/
+enum
+{
+ kStatus_FLEXSPI_Busy = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< FLEXSPI is busy */
+ kStatus_FLEXSPI_SequenceExecutionTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), /*!< Sequence execution timeout
+ error occurred during FLEXSPI transfer. */
+ kStatus_FLEXSPI_IpCommandSequenceError = MAKE_STATUS(kStatusGroup_FLEXSPI, 2), /*!< IP command Sequence execution
+ timeout error occurred during FLEXSPI transfer. */
+ kStatus_FLEXSPI_IpCommandGrantTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 3), /*!< IP command grant timeout error
+ occurred during FLEXSPI transfer. */
+};
+
+/*! @brief CMD definition of FLEXSPI, use to form LUT instruction, _flexspi_command. */
+enum
+{
+ kFLEXSPI_Command_STOP = 0x00U, /*!< Stop execution, deassert CS. */
+ kFLEXSPI_Command_SDR = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */
+ kFLEXSPI_Command_RADDR_SDR = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */
+ kFLEXSPI_Command_CADDR_SDR = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */
+ kFLEXSPI_Command_MODE1_SDR = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */
+ kFLEXSPI_Command_MODE2_SDR = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */
+ kFLEXSPI_Command_MODE4_SDR = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */
+ kFLEXSPI_Command_MODE8_SDR = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */
+ kFLEXSPI_Command_WRITE_SDR = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */
+ kFLEXSPI_Command_READ_SDR = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */
+ kFLEXSPI_Command_LEARN_SDR = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */
+ kFLEXSPI_Command_DATSZ_SDR = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */
+ kFLEXSPI_Command_DUMMY_SDR = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/
+ kFLEXSPI_Command_DUMMY_RWDS_SDR = 0x0DU, /*!< Leave data lines undriven by FlexSPI controller,
+ dummy cycles decided by RWDS. */
+ kFLEXSPI_Command_DDR = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */
+ kFLEXSPI_Command_RADDR_DDR = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */
+ kFLEXSPI_Command_CADDR_DDR = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */
+ kFLEXSPI_Command_MODE1_DDR = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */
+ kFLEXSPI_Command_MODE2_DDR = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */
+ kFLEXSPI_Command_MODE4_DDR = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */
+ kFLEXSPI_Command_MODE8_DDR = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */
+ kFLEXSPI_Command_WRITE_DDR = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */
+ kFLEXSPI_Command_READ_DDR = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */
+ kFLEXSPI_Command_LEARN_DDR = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */
+ kFLEXSPI_Command_DATSZ_DDR = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */
+ kFLEXSPI_Command_DUMMY_DDR = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/
+ kFLEXSPI_Command_DUMMY_RWDS_DDR = 0x2DU, /*!< Leave data lines undriven by FlexSPI controller,
+ dummy cycles decided by RWDS. */
+ kFLEXSPI_Command_JUMP_ON_CS = 0x1FU, /*!< Stop execution, deassert CS and save operand[7:0] as the
+ instruction start pointer for next sequence */
+};
+
+/*! @brief pad definition of FLEXSPI, use to form LUT instruction. */
+typedef enum _flexspi_pad
+{
+ kFLEXSPI_1PAD = 0x00U, /*!< Transmit command/address and transmit/receive data only through DATA0/DATA1. */
+ kFLEXSPI_2PAD = 0x01U, /*!< Transmit command/address and transmit/receive data only through DATA[1:0]. */
+ kFLEXSPI_4PAD = 0x02U, /*!< Transmit command/address and transmit/receive data only through DATA[3:0]. */
+ kFLEXSPI_8PAD = 0x03U, /*!< Transmit command/address and transmit/receive data only through DATA[7:0]. */
+} flexspi_pad_t;
+
+/*! @brief FLEXSPI interrupt status flags.*/
+typedef enum _flexspi_flags
+{
+ kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK, /*!< Sequence execution timeout. */
+#if defined(FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN) && FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN
+ kFLEXSPI_AhbBusErrorFlag = FLEXSPI_INTEN_AHBBUSERROREN_MASK, /*!< AHB Bus error flag. */
+#else
+ kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, /*!< AHB Bus timeout. */
+#endif
+ kFLEXSPI_SckStoppedBecauseTxEmptyFlag =
+ FLEXSPI_INTEN_SCKSTOPBYWREN_MASK, /*!< SCK is stopped during command
+ sequence because Async TX FIFO empty. */
+ kFLEXSPI_SckStoppedBecauseRxFullFlag =
+ FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK, /*!< SCK is stopped during command
+ sequence because Async RX FIFO full. */
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
+ kFLEXSPI_DataLearningFailedFlag = FLEXSPI_INTEN_DATALEARNFAILEN_MASK, /*!< Data learning failed. */
+#endif
+ kFLEXSPI_IpTxFifoWatermarkEmptyFlag = FLEXSPI_INTEN_IPTXWEEN_MASK, /*!< IP TX FIFO WaterMark empty. */
+ kFLEXSPI_IpRxFifoWatermarkAvailableFlag = FLEXSPI_INTEN_IPRXWAEN_MASK, /*!< IP RX FIFO WaterMark available. */
+ kFLEXSPI_AhbCommandSequenceErrorFlag =
+ FLEXSPI_INTEN_AHBCMDERREN_MASK, /*!< AHB triggered Command Sequences Error. */
+ kFLEXSPI_IpCommandSequenceErrorFlag = FLEXSPI_INTEN_IPCMDERREN_MASK, /*!< IP triggered Command Sequences Error. */
+ kFLEXSPI_AhbCommandGrantTimeoutFlag =
+ FLEXSPI_INTEN_AHBCMDGEEN_MASK, /*!< AHB triggered Command Sequences Grant Timeout. */
+ kFLEXSPI_IpCommandGrantTimeoutFlag =
+ FLEXSPI_INTEN_IPCMDGEEN_MASK, /*!< IP triggered Command Sequences Grant Timeout. */
+ kFLEXSPI_IpCommandExecutionDoneFlag =
+ FLEXSPI_INTEN_IPCMDDONEEN_MASK, /*!< IP triggered Command Sequences Execution finished. */
+ kFLEXSPI_AllInterruptFlags = 0xFFFU, /*!< All flags. */
+} flexspi_flags_t;
+
+/*! @brief FLEXSPI sample clock source selection for Flash Reading.*/
+typedef enum _flexspi_read_sample_clock
+{
+ kFLEXSPI_ReadSampleClkLoopbackInternally = 0x0U, /*!< Dummy Read strobe generated by FlexSPI Controller
+ and loopback internally. */
+ kFLEXSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, /*!< Dummy Read strobe generated by FlexSPI Controller
+ and loopback from DQS pad. */
+ kFLEXSPI_ReadSampleClkLoopbackFromSckPad = 0x2U, /*!< SCK output clock and loopback from SCK pad. */
+ kFLEXSPI_ReadSampleClkExternalInputFromDqsPad = 0x3U, /*!< Flash provided Read strobe and input from DQS pad. */
+} flexspi_read_sample_clock_t;
+
+/*! @brief FLEXSPI interval unit for flash device select.*/
+typedef enum _flexspi_cs_interval_cycle_unit
+{
+ kFLEXSPI_CsIntervalUnit1SckCycle = 0x0U, /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */
+ kFLEXSPI_CsIntervalUnit256SckCycle = 0x1U, /*!< Chip selection interval: CSINTERVAL * 256 serial clock cycle. */
+} flexspi_cs_interval_cycle_unit_t;
+
+/*! @brief FLEXSPI AHB wait interval unit for writing.*/
+typedef enum _flexspi_ahb_write_wait_unit
+{
+ kFLEXSPI_AhbWriteWaitUnit2AhbCycle = 0x0U, /*!< AWRWAIT unit is 2 ahb clock cycle. */
+ kFLEXSPI_AhbWriteWaitUnit8AhbCycle = 0x1U, /*!< AWRWAIT unit is 8 ahb clock cycle. */
+ kFLEXSPI_AhbWriteWaitUnit32AhbCycle = 0x2U, /*!< AWRWAIT unit is 32 ahb clock cycle. */
+ kFLEXSPI_AhbWriteWaitUnit128AhbCycle = 0x3U, /*!< AWRWAIT unit is 128 ahb clock cycle. */
+ kFLEXSPI_AhbWriteWaitUnit512AhbCycle = 0x4U, /*!< AWRWAIT unit is 512 ahb clock cycle. */
+ kFLEXSPI_AhbWriteWaitUnit2048AhbCycle = 0x5U, /*!< AWRWAIT unit is 2048 ahb clock cycle. */
+ kFLEXSPI_AhbWriteWaitUnit8192AhbCycle = 0x6U, /*!< AWRWAIT unit is 8192 ahb clock cycle. */
+ kFLEXSPI_AhbWriteWaitUnit32768AhbCycle = 0x7U, /*!< AWRWAIT unit is 32768 ahb clock cycle. */
+} flexspi_ahb_write_wait_unit_t;
+
+/*! @brief Error Code when IP command Error detected.*/
+typedef enum _flexspi_ip_error_code
+{
+ kFLEXSPI_IpCmdErrorNoError = 0x0U, /*!< No error. */
+ kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd = 0x2U, /*!< IP command with JMP_ON_CS instruction used. */
+ kFLEXSPI_IpCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */
+ kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR
+ used in DDR sequence. */
+ kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR
+ used in SDR sequence. */
+ kFLEXSPI_IpCmdErrorInvalidAddress = 0x6U, /*!< Flash access start address exceed the whole
+ flash address range (A1/A2/B1/B2). */
+ kFLEXSPI_IpCmdErrorSequenceExecutionTimeout = 0xEU, /*!< Sequence execution timeout. */
+ kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss = 0xFU, /*!< Flash boundary crossed. */
+} flexspi_ip_error_code_t;
+
+/*! @brief Error Code when AHB command Error detected.*/
+typedef enum _flexspi_ahb_error_code
+{
+ kFLEXSPI_AhbCmdErrorNoError = 0x0U, /*!< No error. */
+ kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd = 0x2U, /*!< AHB Write command with JMP_ON_CS instruction
+ used in the sequence. */
+ kFLEXSPI_AhbCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */
+ kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR used
+ in DDR sequence. */
+ kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR
+ used in SDR sequence. */
+ kFLEXSPI_AhbCmdSequenceExecutionTimeout = 0x6U, /*!< Sequence execution timeout. */
+} flexspi_ahb_error_code_t;
+
+/*! @brief FLEXSPI operation port select.*/
+typedef enum _flexspi_port
+{
+ kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */
+ kFLEXSPI_PortA2, /*!< Access flash on A2 port. */
+ kFLEXSPI_PortB1, /*!< Access flash on B1 port. */
+ kFLEXSPI_PortB2, /*!< Access flash on B2 port. */
+ kFLEXSPI_PortCount
+} flexspi_port_t;
+
+/*! @brief Trigger source of current command sequence granted by arbitrator.*/
+typedef enum _flexspi_arb_command_source
+{
+ kFLEXSPI_AhbReadCommand = 0x0U,
+ kFLEXSPI_AhbWriteCommand = 0x1U,
+ kFLEXSPI_IpCommand = 0x2U,
+ kFLEXSPI_SuspendedCommand = 0x3U,
+} flexspi_arb_command_source_t;
+
+/*! @brief Command type. */
+typedef enum _flexspi_command_type
+{
+ kFLEXSPI_Command, /*!< FlexSPI operation: Only command, both TX and Rx buffer are ignored. */
+ kFLEXSPI_Config, /*!< FlexSPI operation: Configure device mode, the TX fifo size is fixed in LUT. */
+ kFLEXSPI_Read, /* /!< FlexSPI operation: Read, only Rx Buffer is effective. */
+ kFLEXSPI_Write, /* /!< FlexSPI operation: Read, only Tx Buffer is effective. */
+} flexspi_command_type_t;
+
+typedef struct _flexspi_ahbBuffer_config
+{
+ uint8_t priority; /*!< This priority for AHB Master Read which this AHB RX Buffer is assigned. */
+ uint8_t masterIndex; /*!< AHB Master ID the AHB RX Buffer is assigned. */
+ uint16_t bufferSize; /*!< AHB buffer size in byte. */
+ bool enablePrefetch; /*!< AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows
+ prefetch disable/enable separately for each master. */
+} flexspi_ahbBuffer_config_t;
+
+/*! @brief FLEXSPI configuration structure. */
+typedef struct _flexspi_config
+{
+ flexspi_read_sample_clock_t rxSampleClock; /*!< Sample Clock source selection for Flash Reading. */
+ bool enableSckFreeRunning; /*!< Enable/disable SCK output free-running. */
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
+ bool enableCombination; /*!< Enable/disable combining PORT A and B Data Pins
+ (SIOA[3:0] and SIOB[3:0]) to support Flash Octal mode. */
+#endif
+ bool enableDoze; /*!< Enable/disable doze mode support. */
+ bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half
+ speed commands. */
+ bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock
+ output, when enable, Port B flash access is not available. */
+ bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices
+ when enabled, same configuration in FLASHA1CRx is applied to all. */
+ uint16_t seqTimeoutCycle; /*!< Timeout wait cycle for command sequence execution,
+ timeout after ahbGrantTimeoutCyle*1024 serial root clock cycles. */
+ uint8_t ipGrantTimeoutCycle; /*!< Timeout wait cycle for IP command grant, timeout after
+ ipGrantTimeoutCycle*1024 AHB clock cycles. */
+ uint8_t txWatermark; /*!< FLEXSPI IP transmit watermark value. */
+ uint8_t rxWatermark; /*!< FLEXSPI receive watermark value. */
+ struct
+ {
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN)
+ bool enableAHBWriteIpTxFifo; /*!< Enable AHB bus write access to IP TX FIFO. */
+#endif
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN)
+ bool enableAHBWriteIpRxFifo; /*!< Enable AHB bus write access to IP RX FIFO. */
+#endif
+ uint8_t ahbGrantTimeoutCycle; /*!< Timeout wait cycle for AHB command grant,
+ timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles. */
+ uint16_t ahbBusTimeoutCycle; /*!< Timeout wait cycle for AHB read/write access,
+ timeout after ahbBusTimeoutCycle*1024 AHB clock cycles. */
+ uint8_t resumeWaitCycle; /*!< Wait cycle for idle state before suspended command sequence
+ resume, timeout after ahbBusTimeoutCycle AHB clock cycles. */
+ flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */
+ bool enableClearAHBBufferOpt; /*!< Enable/disable automatically clean AHB RX Buffer and TX Buffer
+ when FLEXSPI returns STOP mode ACK. */
+ bool enableReadAddressOpt; /*!< Enable/disable remove AHB read burst start address alignment limitation.
+ when enable, there is no AHB read burst start address alignment limitation. */
+ bool enableAHBPrefetch; /*!< Enable/disable AHB read prefetch feature, when enabled, FLEXSPI
+ will fetch more data than current AHB burst. */
+ bool enableAHBBufferable; /*!< Enable/disable AHB bufferable write access support, when enabled,
+ FLEXSPI return before waiting for command execution finished. */
+ bool enableAHBCachable; /*!< Enable AHB bus cachable read access support. */
+ } ahbConfig;
+} flexspi_config_t;
+
+/*! @brief External device configuration items. */
+typedef struct _flexspi_device_config
+{
+ uint32_t flexspiRootClk; /*!< FLEXSPI serial root clock. */
+ bool isSck2Enabled; /*!< FLEXSPI use SCK2. */
+ uint32_t flashSize; /*!< Flash size in KByte. */
+ flexspi_cs_interval_cycle_unit_t CSIntervalUnit; /*!< CS interval unit, 1 or 256 cycle. */
+ uint16_t CSInterval; /*!< CS line assert interval, multiply CS interval unit to
+ get the CS line assert interval cycles. */
+ uint8_t CSHoldTime; /*!< CS line hold time. */
+ uint8_t CSSetupTime; /*!< CS line setup time. */
+ uint8_t dataValidTime; /*!< Data valid time for external device. */
+ uint8_t columnspace; /*!< Column space size. */
+ bool enableWordAddress; /*!< If enable word address.*/
+ uint8_t AWRSeqIndex; /*!< Sequence ID for AHB write command. */
+ uint8_t AWRSeqNumber; /*!< Sequence number for AHB write command. */
+ uint8_t ARDSeqIndex; /*!< Sequence ID for AHB read command. */
+ uint8_t ARDSeqNumber; /*!< Sequence number for AHB read command. */
+ flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit; /*!< AHB write wait unit. */
+ uint16_t AHBWriteWaitInterval; /*!< AHB write wait interval, multiply AHB write interval
+ unit to get the AHB write wait cycles. */
+ bool enableWriteMask; /*!< Enable/Disable FLEXSPI drive DQS pin as write mask
+ when writing to external device. */
+} flexspi_device_config_t;
+
+/*! @brief Transfer structure for FLEXSPI. */
+typedef struct _flexspi_transfer
+{
+ uint32_t deviceAddress; /*!< Operation device address. */
+ flexspi_port_t port; /*!< Operation port. */
+ flexspi_command_type_t cmdType; /*!< Execution command type. */
+ uint8_t seqIndex; /*!< Sequence ID for command. */
+ uint8_t SeqNumber; /*!< Sequence number for command. */
+ uint32_t *data; /*!< Data buffer. */
+ size_t dataSize; /*!< Data size in bytes. */
+} flexspi_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _flexspi_handle flexspi_handle_t;
+
+/*! @brief FLEXSPI transfer callback function. */
+typedef void (*flexspi_transfer_callback_t)(FLEXSPI_Type *base,
+ flexspi_handle_t *handle,
+ status_t status,
+ void *userData);
+
+/*! @brief Transfer handle structure for FLEXSPI. */
+struct _flexspi_handle
+{
+ uint32_t state; /*!< Internal state for FLEXSPI transfer */
+ uint32_t *data; /*!< Data buffer. */
+ size_t dataSize; /*!< Remaining Data size in bytes. */
+ size_t transferTotalSize; /*!< Total Data size in bytes. */
+ flexspi_transfer_callback_t completionCallback; /*!< Callback for users while transfer finish or error occurred */
+ void *userData; /*!< FLEXSPI callback function parameter.*/
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus. */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Get the instance number for FLEXSPI.
+ *
+ * @param base FLEXSPI base pointer.
+ */
+uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base);
+
+/*!
+ * @brief Check and clear IP command execution errors.
+ *
+ * @param base FLEXSPI base pointer.
+ * @param status interrupt status.
+ */
+status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status);
+
+/*!
+ * @brief Initializes the FLEXSPI module and internal state.
+ *
+ * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the
+ * input configure parameters. Users should call this function before any FLEXSPI operations.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param config FLEXSPI configure structure.
+ */
+void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config);
+
+/*!
+ * @brief Gets default settings for FLEXSPI.
+ *
+ * @param config FLEXSPI configuration structure.
+ */
+void FLEXSPI_GetDefaultConfig(flexspi_config_t *config);
+
+/*!
+ * @brief Deinitializes the FLEXSPI module.
+ *
+ * Clears the FLEXSPI state and FLEXSPI module registers.
+ * @param base FLEXSPI peripheral base address.
+ */
+void FLEXSPI_Deinit(FLEXSPI_Type *base);
+
+/*!
+ * @brief Update FLEXSPI DLL value depending on currently flexspi root clock.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param config Flash configuration parameters.
+ * @param port FLEXSPI Operation port.
+ */
+void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port);
+
+/*!
+ * @brief Configures the connected device parameter.
+ *
+ * This function configures the connected device relevant parameters, such as the size, command, and so on.
+ * The flash configuration value cannot have a default value. The user needs to configure it according to the
+ * connected device.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param config Flash configuration parameters.
+ * @param port FLEXSPI Operation port.
+ */
+void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port);
+
+/*!
+ * @brief Software reset for the FLEXSPI logic.
+ *
+ * This function sets the software reset flags for both AHB and buffer domain and
+ * resets both AHB buffer and also IP FIFOs.
+ *
+ * @param base FLEXSPI peripheral base address.
+ */
+static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
+{
+ base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
+ while (0U != (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK))
+ {
+ }
+}
+
+/*!
+ * @brief Enables or disables the FLEXSPI module.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param enable True means enable FLEXSPI, false means disable.
+ */
+static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+ }
+ else
+ {
+ base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
+ }
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+/*!
+ * @brief Enables the FLEXSPI interrupts.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param mask FLEXSPI interrupt source.
+ */
+static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
+{
+ base->INTEN |= mask;
+}
+
+/*!
+ * @brief Disable the FLEXSPI interrupts.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param mask FLEXSPI interrupt source.
+ */
+static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
+{
+ base->INTEN &= ~mask;
+}
+
+/* @} */
+
+/*! @name DMA control */
+/*@{*/
+
+/*!
+ * @brief Enables or disables FLEXSPI IP Tx FIFO DMA requests.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param enable Enable flag for transmit DMA request. Pass true for enable, false for disable.
+ */
+static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->IPTXFCR |= FLEXSPI_IPTXFCR_TXDMAEN_MASK;
+ }
+ else
+ {
+ base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXDMAEN_MASK;
+ }
+}
+
+/*!
+ * @brief Enables or disables FLEXSPI IP Rx FIFO DMA requests.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param enable Enable flag for receive DMA request. Pass true for enable, false for disable.
+ */
+static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->IPRXFCR |= FLEXSPI_IPRXFCR_RXDMAEN_MASK;
+ }
+ else
+ {
+ base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXDMAEN_MASK;
+ }
+}
+
+/*!
+ * @brief Gets FLEXSPI IP tx fifo address for DMA transfer.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @retval The tx fifo address.
+ */
+static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
+{
+ return (uint32_t)&base->TFDR[0];
+}
+
+/*!
+ * @brief Gets FLEXSPI IP rx fifo address for DMA transfer.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @retval The rx fifo address.
+ */
+static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
+{
+ return (uint32_t)&base->RFDR[0];
+}
+
+/*@}*/
+
+/*! @name FIFO control */
+/*@{*/
+
+/*! @brief Clears the FLEXSPI IP FIFO logic.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param txFifo Pass true to reset TX FIFO.
+ * @param rxFifo Pass true to reset RX FIFO.
+ */
+static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)
+{
+ if (txFifo)
+ {
+ base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
+ }
+ if (rxFifo)
+ {
+ base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;
+ }
+}
+
+/*!
+ * @brief Gets the valid data entries in the FLEXSPI FIFOs.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned.
+ * Pass NULL if this value is not required.
+ * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned.
+ * Pass NULL if this value is not required.
+ */
+static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)
+{
+ if (NULL != txCount)
+ {
+ *txCount = (((base->IPTXFSTS) & FLEXSPI_IPTXFSTS_FILL_MASK) >> FLEXSPI_IPTXFSTS_FILL_SHIFT) * 8U;
+ }
+ if (NULL != rxCount)
+ {
+ *rxCount = (((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U;
+ }
+}
+
+/*@}*/
+
+/*!
+ * @name Status
+ * @{
+ */
+/*!
+ * @brief Get the FLEXSPI interrupt status flags.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @retval interrupt status flag, use status flag to AND #flexspi_flags_t could get the related status.
+ */
+static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
+{
+ return base->INTR;
+}
+
+/*!
+ * @brief Get the FLEXSPI interrupt status flags.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param mask FLEXSPI interrupt source.
+ */
+static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
+{
+ base->INTR |= mask;
+}
+
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
+/*! @brief Gets the sampling clock phase selection after Data Learning.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param portAPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTA.
+ * @param portBPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTB.
+ */
+static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *portAPhase, uint8_t *portBPhase)
+{
+ if (portAPhase != NULL)
+ {
+ *portAPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT);
+ }
+
+ if (portBPhase != NULL)
+ {
+ *portBPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT);
+ }
+}
+#endif
+
+/*! @brief Gets the trigger source of current command sequence granted by arbitrator.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @retval trigger source of current command sequence.
+ */
+static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)
+{
+ return (flexspi_arb_command_source_t)(
+ (uint32_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT));
+}
+
+/*! @brief Gets the error code when IP command error detected.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected.
+ * @retval error code when IP command error detected.
+ */
+static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
+{
+ *index = (uint8_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT);
+ return (flexspi_ip_error_code_t)(
+ (uint32_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT));
+}
+
+/*! @brief Gets the error code when AHB command error detected.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected.
+ * @retval error code when AHB command error detected.
+ */
+static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
+{
+ *index = (uint8_t)(base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT;
+ return (flexspi_ahb_error_code_t)(
+ (uint32_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >> FLEXSPI_STS1_AHBCMDERRCODE_SHIFT));
+}
+
+/*! @brief Returns whether the bus is idle.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @retval true Bus is idle.
+ * @retval false Bus is busy.
+ */
+static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
+{
+ return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK));
+}
+/*@}*/
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*! @brief Update read sample clock source
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param clockSource clockSource of type #flexspi_read_sample_clock_t
+ */
+void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource);
+
+/*! @brief Enables/disables the FLEXSPI IP command parallel mode.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param enable True means enable parallel mode, false means disable parallel mode.
+ */
+static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->IPCR1 |= FLEXSPI_IPCR1_IPAREN_MASK;
+ }
+ else
+ {
+ base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK;
+ }
+}
+
+/*! @brief Enables/disables the FLEXSPI AHB command parallel mode.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param enable True means enable parallel mode, false means disable parallel mode.
+ */
+static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->AHBCR |= FLEXSPI_AHBCR_APAREN_MASK;
+ }
+ else
+ {
+ base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK;
+ }
+}
+
+/*! @brief Updates the LUT table.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param index From which index start to update. It could be any index of the LUT table, which
+ * also allows user to update command content inside a command. Each command consists of up to
+ * 8 instructions and occupy 4*32-bit memory.
+ * @param cmd Command sequence array.
+ * @param count Number of sequences.
+ */
+void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count);
+
+/*!
+ * @brief Writes data into FIFO.
+ *
+ * @param base FLEXSPI peripheral base address
+ * @param data The data bytes to send
+ * @param fifoIndex Destination fifo index.
+ */
+static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)
+{
+ base->TFDR[fifoIndex] = data;
+}
+
+/*!
+ * @brief Receives data from data FIFO.
+ *
+ * @param base FLEXSPI peripheral base address
+ * @param fifoIndex Source fifo index.
+ * @return The data in the FIFO.
+ */
+static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
+{
+ return base->RFDR[fifoIndex];
+}
+
+/*!
+ * @brief Sends a buffer of data bytes using blocking method.
+ * @note This function blocks via polling until all bytes have been sent.
+ * @param base FLEXSPI peripheral base address
+ * @param buffer The data bytes to send
+ * @param size The number of data bytes to send
+ * @retval kStatus_Success write success without error
+ * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
+ * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
+ * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
+ */
+status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size);
+
+/*!
+ * @brief Receives a buffer of data bytes using a blocking method.
+ * @note This function blocks via polling until all bytes have been sent.
+ * @param base FLEXSPI peripheral base address
+ * @param buffer The data bytes to send
+ * @param size The number of data bytes to receive
+ * @retval kStatus_Success read success without error
+ * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
+ * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
+ * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
+ */
+status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size);
+
+/*!
+ * @brief Execute command to transfer a buffer data bytes using a blocking method.
+ * @param base FLEXSPI peripheral base address
+ * @param xfer pointer to the transfer structure.
+ * @retval kStatus_Success command transfer success without error
+ * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
+ * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
+ * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
+ */
+status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer);
+/*! @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FLEXSPI handle which is used in transactional functions.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param handle pointer to flexspi_handle_t structure to store the transfer state.
+ * @param callback pointer to user callback function.
+ * @param userData user parameter passed to the callback function.
+ */
+void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
+ flexspi_handle_t *handle,
+ flexspi_transfer_callback_t callback,
+ void *userData);
+
+/*!
+ * @brief Performs a interrupt non-blocking transfer on the FLEXSPI bus.
+ *
+ * @note Calling the API returns immediately after transfer initiates. The user needs
+ * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether
+ * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer
+ * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or
+ * FLEXSPI could not read data properly.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param handle pointer to flexspi_handle_t structure which stores the transfer state.
+ * @param xfer pointer to flexspi_transfer_t structure.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_FLEXSPI_Busy Previous transmission still not finished.
+ */
+status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer);
+
+/*!
+ * @brief Gets the master transfer status during a interrupt non-blocking transfer.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param handle pointer to flexspi_handle_t structure which stores the transfer state.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Aborts an interrupt non-blocking transfer early.
+ *
+ * @note This API can be called at any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param handle pointer to flexspi_handle_t structure which stores the transfer state
+ */
+void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle);
+
+/*!
+ * @brief Master interrupt handler.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param handle pointer to flexspi_handle_t structure.
+ */
+void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle);
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus. */
+/*@}*/
+
+#endif /* __FSL_FLEXSPI_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_gpio.c b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_gpio.c
new file mode 100644
index 000000000..be100d5e9
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_gpio.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_gpio.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map FGPIO instance number to clock name. */
+static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
+/*! @brief Pointers to GPIO resets for each instance. */
+static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N;
+#endif
+/*******************************************************************************
+ * Prototypes
+ ************ ******************************************************************/
+/*!
+ * @brief Enable GPIO port clock.
+ *
+ * @param base GPIO peripheral base pointer.
+ * @param port GPIO port number.
+ */
+static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ assert(port < ARRAY_SIZE(s_gpioClockName));
+
+ /* Upgate the GPIO clock */
+ CLOCK_EnableClock(s_gpioClockName[port]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Initializes the GPIO peripheral.
+ *
+ * This function ungates the GPIO clock.
+ *
+ * param base GPIO peripheral base pointer.
+ * param port GPIO port number.
+ */
+void GPIO_PortInit(GPIO_Type *base, uint32_t port)
+{
+ GPIO_EnablePortClock(base, port);
+
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
+ /* Reset the GPIO module */
+ RESET_PeripheralReset(s_gpioResets[port]);
+#endif
+}
+
+/*!
+ * brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ * kGPIO_DigitalInput,
+ * 0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ * kGPIO_DigitalOutput,
+ * 0,
+ * }
+ * endcode
+ *
+ * param base GPIO peripheral base pointer(Typically GPIO)
+ * param port GPIO port number
+ * param pin GPIO pin number
+ * param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
+{
+ GPIO_EnablePortClock(base, port);
+
+ if (config->pinDirection == kGPIO_DigitalInput)
+ {
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
+ base->DIRCLR[port] = 1UL << pin;
+#else
+ base->DIR[port] &= ~(1UL << pin);
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
+ }
+ else
+ {
+ /* Set default output value */
+ if (config->outputLogic == 0U)
+ {
+ base->CLR[port] = (1UL << pin);
+ }
+ else
+ {
+ base->SET[port] = (1UL << pin);
+ }
+/* Set pin direction */
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
+ base->DIRSET[port] = 1UL << pin;
+#else
+ base->DIR[port] |= 1UL << pin;
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
+ }
+}
+
+#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
+/*!
+ * @brief Set the configuration of pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param pin GPIO pin number.
+ * @param config GPIO pin interrupt configuration..
+ */
+void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config)
+{
+ base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin);
+
+ base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin);
+}
+
+/*!
+ * @brief Enables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
+{
+ if ((uint32_t)kGPIO_InterruptA == index)
+ {
+ base->INTENA[port] = base->INTENA[port] | mask;
+ }
+ else if ((uint32_t)kGPIO_InterruptB == index)
+ {
+ base->INTENB[port] = base->INTENB[port] | mask;
+ }
+ else
+ {
+ /*Should not enter here*/
+ }
+}
+
+/*!
+ * @brief Disables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
+{
+ if ((uint32_t)kGPIO_InterruptA == index)
+ {
+ base->INTENA[port] = base->INTENA[port] & ~mask;
+ }
+ else if ((uint32_t)kGPIO_InterruptB == index)
+ {
+ base->INTENB[port] = base->INTENB[port] & ~mask;
+ }
+ else
+ {
+ /*Should not enter here*/
+ }
+}
+
+/*!
+ * @brief Clears multiple pins interrupt flag. Status flags are cleared by
+ * writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
+{
+ if ((uint32_t)kGPIO_InterruptA == index)
+ {
+ base->INTSTATA[port] = mask;
+ }
+ else if ((uint32_t)kGPIO_InterruptB == index)
+ {
+ base->INTSTATB[port] = mask;
+ }
+ else
+ {
+ /*Should not enter here*/
+ }
+}
+
+/*!
+ * @ Read port interrupt status.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param index GPIO interrupt number.
+ * @retval masked GPIO status value
+ */
+uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index)
+{
+ uint32_t status = 0U;
+
+ if ((uint32_t)kGPIO_InterruptA == index)
+ {
+ status = base->INTSTATA[port];
+ }
+ else if ((uint32_t)kGPIO_InterruptB == index)
+ {
+ status = base->INTSTATB[port];
+ }
+ else
+ {
+ /*Should not enter here*/
+ }
+ return status;
+}
+
+/*!
+ * @brief Enables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
+{
+ if ((uint32_t)kGPIO_InterruptA == index)
+ {
+ base->INTENA[port] = base->INTENA[port] | (1UL << pin);
+ }
+ else if ((uint32_t)kGPIO_InterruptB == index)
+ {
+ base->INTENB[port] = base->INTENB[port] | (1UL << pin);
+ }
+ else
+ {
+ /*Should not enter here*/
+ }
+}
+
+/*!
+ * @brief Disables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
+{
+ if ((uint32_t)kGPIO_InterruptA == index)
+ {
+ base->INTENA[port] = base->INTENA[port] & ~(1UL << pin);
+ }
+ else if ((uint32_t)kGPIO_InterruptB == index)
+ {
+ base->INTENB[port] = base->INTENB[port] & ~(1UL << pin);
+ }
+ else
+ {
+ /*Should not enter here*/
+ }
+}
+
+/*!
+ * @brief Clears the specific pin interrupt flag. Status flags are cleared by
+ * writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
+{
+ if ((uint32_t)kGPIO_InterruptA == index)
+ {
+ base->INTSTATA[port] = 1UL << pin;
+ }
+ else if ((uint32_t)kGPIO_InterruptB == index)
+ {
+ base->INTSTATB[port] = 1UL << pin;
+ }
+ else
+ {
+ /*Should not enter here*/
+ }
+}
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_gpio.h b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_gpio.h
new file mode 100644
index 000000000..50a33f892
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_gpio.h
@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _LPC_GPIO_H_
+#define _LPC_GPIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_gpio
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPC GPIO driver version. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7))
+/*@}*/
+
+/*! @brief LPC GPIO direction definition */
+typedef enum _gpio_pin_direction
+{
+ kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/
+ kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+/*!
+ * @brief The GPIO pin configuration structure.
+ *
+ * Every pin can only be configured as either output pin or input pin at a time.
+ * If configured as a input pin, then leave the outputConfig unused.
+ */
+typedef struct _gpio_pin_config
+{
+ gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
+ /* Output configurations, please ignore if configured as a input one */
+ uint8_t outputLogic; /*!< Set default output logic, no use in input */
+} gpio_pin_config_t;
+
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT)
+#define GPIO_PIN_INT_LEVEL 0x00U
+#define GPIO_PIN_INT_EDGE 0x01U
+
+#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U
+#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U
+
+/*! @brief GPIO Pin Interrupt enable mode */
+typedef enum _gpio_pin_enable_mode
+{
+ kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */
+ kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */
+} gpio_pin_enable_mode_t;
+
+/*! @brief GPIO Pin Interrupt enable polarity */
+typedef enum _gpio_pin_enable_polarity
+{
+ kGPIO_PinIntEnableHighOrRise =
+ PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */
+ kGPIO_PinIntEnableLowOrFall =
+ PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */
+} gpio_pin_enable_polarity_t;
+
+/*! @brief LPC GPIO interrupt index definition */
+typedef enum _gpio_interrupt_index
+{
+ kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/
+ kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/
+} gpio_interrupt_index_t;
+
+/*! @brief Configures the interrupt generation condition. */
+typedef struct _gpio_interrupt_config
+{
+ uint8_t mode; /* The trigger mode of GPIO interrupts */
+ uint8_t polarity; /* The polarity of GPIO interrupts */
+} gpio_interrupt_config_t;
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name GPIO Configuration */
+/*@{*/
+
+/*!
+ * @brief Initializes the GPIO peripheral.
+ *
+ * This function ungates the GPIO clock.
+ *
+ * @param base GPIO peripheral base pointer.
+ * @param port GPIO port number.
+ */
+void GPIO_PortInit(GPIO_Type *base, uint32_t port);
+
+/*!
+ * @brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * @code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ * kGPIO_DigitalInput,
+ * 0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ * kGPIO_DigitalOutput,
+ * 0,
+ * }
+ * @endcode
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param pin GPIO pin number
+ * @param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);
+
+/*@}*/
+
+/*! @name GPIO Output Operations */
+/*@{*/
+
+/*!
+ * @brief Sets the output level of the one GPIO pin to the logic 1 or 0.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param pin GPIO pin number
+ * @param output GPIO pin output logic level.
+ * - 0: corresponding pin output low-logic level.
+ * - 1: corresponding pin output high-logic level.
+ */
+static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
+{
+ base->B[port][pin] = output;
+}
+
+/*@}*/
+/*! @name GPIO Input Operations */
+/*@{*/
+
+/*!
+ * @brief Reads the current input value of the GPIO PIN.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param pin GPIO pin number
+ * @retval GPIO port input value
+ * - 0: corresponding pin input low-logic level.
+ * - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin)
+{
+ return (uint32_t)base->B[port][pin];
+}
+
+/*@}*/
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ base->SET[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ base->CLR[port] = mask;
+}
+
+/*!
+ * @brief Reverses current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ base->NOT[port] = mask;
+}
+
+/*@}*/
+
+/*!
+ * @brief Reads the current input value of the whole GPIO port.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ */
+static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port)
+{
+ return (uint32_t)base->PIN[port];
+}
+
+/*@}*/
+/*! @name GPIO Mask Operations */
+/*@{*/
+
+/*!
+ * @brief Sets port mask, 0 - enable pin, 1 - disable pin.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ base->MASK[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param output GPIO port output value.
+ */
+static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output)
+{
+ base->MPIN[port] = output;
+}
+
+/*!
+ * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be
+ * affected.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @retval masked GPIO port value
+ */
+static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port)
+{
+ return (uint32_t)base->MPIN[port];
+}
+
+#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
+/*!
+ * @brief Set the configuration of pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param pin GPIO pin number.
+ * @param config GPIO pin interrupt configuration..
+ */
+void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config);
+
+/*!
+ * @brief Enables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
+
+/*!
+ * @brief Disables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
+
+/*!
+ * @brief Clears pin interrupt flag. Status flags are cleared by
+ * writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
+
+/*!
+ * @ Read port interrupt status.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param index GPIO interrupt number.
+ * @retval masked GPIO status value
+ */
+uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index);
+
+/*!
+ * @brief Enables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
+
+/*!
+ * @brief Disables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
+
+/*!
+ * @brief Clears the specific pin interrupt flag. Status flags are cleared by
+ * writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
+
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _LPC_GPIO_H_*/
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_iap.c b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_iap.c
new file mode 100644
index 000000000..b76443115
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_iap.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "fsl_iap.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iap"
+#endif
+
+/*!
+ * @addtogroup rom_api
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief FLEXSPI Flash driver API Interface */
+typedef struct
+{
+ uint32_t version;
+ status_t (*init)(uint32_t instance, flexspi_nor_config_t *config);
+ status_t (*page_program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dstAddr, const uint32_t *src);
+ status_t (*erase_all)(uint32_t instance, flexspi_nor_config_t *config);
+ status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length);
+ status_t (*erase_sector)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
+ status_t (*erase_block)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
+ status_t (*get_config)(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option);
+ status_t (*read)(uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes);
+ status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer);
+ status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq);
+ status_t (*set_clock_source)(uint32_t clockSrc);
+ void (*config_clock)(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode);
+} flexspi_nor_flash_driver_t;
+
+/*! @brief OTP driver API Interface */
+typedef struct
+{
+ status_t (*init)(uint32_t src_clk_freq);
+ status_t (*deinit)(void);
+ status_t (*fuse_read)(uint32_t addr, uint32_t *data);
+ status_t (*fuse_program)(uint32_t addr, uint32_t data, bool lock);
+ status_t (*crc_calc)(uint32_t *src, uint32_t numberOfWords, uint32_t *crcChecksum);
+ status_t (*reload)(void);
+ status_t (*crc_check)(uint32_t start_addr, uint32_t end_addr, uint32_t crc_addr);
+} ocotp_driver_t;
+
+/*!
+ * @brief Root of the bootloader API tree.
+ *
+ * An instance of this struct resides in read-only memory in the bootloader. It
+ * provides a user application access to APIs exported by the bootloader.
+ *
+ * @note The order of existing fields must not be changed.
+ */
+typedef struct BootloaderTree
+{
+ void (*runBootloader)(iap_boot_option_t *arg); /*!< Function to start the bootloader executing. */
+ uint32_t version; /*!< Bootloader version number. */
+ const char *copyright; /*!< Copyright string. */
+ const uint32_t reserved0;
+ const uint32_t reserved1;
+ const uint32_t reserved2;
+ const uint32_t reserved3;
+ const flexspi_nor_flash_driver_t *flexspiNorDriver; /*!< FlexSPI NOR FLASH Driver API. */
+ const ocotp_driver_t *otpDriver; /*!< OTP driver API. */
+ const uint32_t reserved4;
+} bootloader_tree_t;
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define ROM_API_TREE ((uint32_t *)FSL_ROM_API_BASE_ADDR)
+#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)ROM_API_TREE)
+
+/*! Get pointer to flexspi/otp driver API table in ROM. */
+#define FLEXSPI_API_TREE BOOTLOADER_API_TREE_POINTER->flexspiNorDriver
+#define OTP_API_TREE BOOTLOADER_API_TREE_POINTER->otpDriver
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * runBootloader API
+ ******************************************************************************/
+void IAP_RunBootLoader(iap_boot_option_t *option)
+{
+ BOOTLOADER_API_TREE_POINTER->runBootloader(option);
+}
+
+/*******************************************************************************
+ * FlexSPI NOR driver
+ ******************************************************************************/
+AT_QUICKACCESS_SECTION_CODE(status_t IAP_FlexspiNorInit(uint32_t instance, flexspi_nor_config_t *config))
+{
+ return FLEXSPI_API_TREE->init(instance, config);
+}
+
+status_t IAP_FlexspiNorPageProgram(uint32_t instance,
+ flexspi_nor_config_t *config,
+ uint32_t dstAddr,
+ const uint32_t *src)
+{
+ return FLEXSPI_API_TREE->page_program(instance, config, dstAddr, src);
+}
+
+status_t IAP_FlexspiNorEraseAll(uint32_t instance, flexspi_nor_config_t *config)
+{
+ return FLEXSPI_API_TREE->erase_all(instance, config);
+}
+
+status_t IAP_FlexspiNorErase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length)
+{
+ return FLEXSPI_API_TREE->erase(instance, config, start, length);
+}
+
+status_t IAP_FlexspiNorEraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address)
+{
+ return FLEXSPI_API_TREE->erase_sector(instance, config, address);
+}
+
+status_t IAP_FlexspiNorEraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t address)
+{
+ return FLEXSPI_API_TREE->erase_block(instance, config, address);
+}
+
+status_t IAP_FlexspiNorGetConfig(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option)
+{
+ return FLEXSPI_API_TREE->get_config(instance, config, option);
+}
+
+status_t IAP_FlexspiNorRead(
+ uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes)
+{
+ return FLEXSPI_API_TREE->read(instance, config, dst, start, bytes);
+}
+
+status_t IAP_FlexspiXfer(uint32_t instance, flexspi_xfer_t *xfer)
+{
+ return FLEXSPI_API_TREE->xfer(instance, xfer);
+}
+
+status_t IAP_FlexspiUpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq)
+{
+ return FLEXSPI_API_TREE->update_lut(instance, seqIndex, lutBase, numberOfSeq);
+}
+
+status_t IAP_FlexspiSetClockSource(uint32_t clockSrc)
+{
+ return FLEXSPI_API_TREE->set_clock_source(clockSrc);
+}
+
+void IAP_FlexspiConfigClock(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode)
+{
+ FLEXSPI_API_TREE->config_clock(instance, freqOption, sampleClkMode);
+}
+
+AT_QUICKACCESS_SECTION_CODE(status_t IAP_FlexspiNorAutoConfig(uint32_t instance,
+ flexspi_nor_config_t *config,
+ serial_nor_config_option_t *option))
+{
+ /* Wait until the FLEXSPI is idle */
+ register uint32_t delaycnt = 10000u;
+ status_t status;
+
+ while ((delaycnt--) != 0U)
+ {
+ }
+
+ status = FLEXSPI_API_TREE->get_config(instance, config, option);
+ if (status == kStatus_Success)
+ {
+ status = FLEXSPI_API_TREE->init(instance, config);
+ }
+
+ return status;
+}
+
+/*******************************************************************************
+ * OTP driver
+ ******************************************************************************/
+status_t IAP_OtpInit(uint32_t src_clk_freq)
+{
+ return OTP_API_TREE->init(src_clk_freq);
+}
+
+status_t IAP_OtpDeinit(void)
+{
+ return OTP_API_TREE->deinit();
+}
+
+status_t IAP_OtpFuseRead(uint32_t addr, uint32_t *data)
+{
+ return OTP_API_TREE->fuse_read(addr, data);
+}
+
+status_t IAP_OtpFuseProgram(uint32_t addr, uint32_t data, bool lock)
+{
+ return OTP_API_TREE->fuse_program(addr, data, lock);
+}
+
+status_t IAP_OtpCrcCalc(uint32_t *src, uint32_t numberOfWords, uint32_t *crcChecksum)
+{
+ return OTP_API_TREE->crc_calc(src, numberOfWords, crcChecksum);
+}
+
+status_t IAP_OtpShadowRegisterReload(void)
+{
+ return OTP_API_TREE->reload();
+}
+
+status_t IAP_OtpCrcCheck(uint32_t start_addr, uint32_t end_addr, uint32_t crc_addr)
+{
+ return OTP_API_TREE->crc_check(start_addr, end_addr, crc_addr);
+}
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_iap.h b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_iap.h
new file mode 100644
index 000000000..48334ffa7
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_iap.h
@@ -0,0 +1,727 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_IAP_H_
+#define __FSL_IAP_H_
+
+#include "fsl_common.h"
+/*!
+ * @addtogroup IAP_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @name Driver version */
+/*@{*/
+/*! @brief IAP driver version 2.1.2. */
+#define FSL_IAP_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
+/*@}*/
+
+/*!
+ * @addtogroup iap_flexspi_driver
+ * @{
+ */
+
+/*! @brief FlexSPI LUT command */
+
+#define NOR_CMD_INDEX_READ 0 /*!< 0 */
+#define NOR_CMD_INDEX_READSTATUS 1 /*!< 1 */
+#define NOR_CMD_INDEX_WRITEENABLE 2 /*!< 2 */
+#define NOR_CMD_INDEX_ERASESECTOR 3 /*!< 3 */
+#define NOR_CMD_INDEX_PAGEPROGRAM 4 /*!< 4 */
+#define NOR_CMD_INDEX_CHIPERASE 5 /*!< 5 */
+#define NOR_CMD_INDEX_DUMMY 6 /*!< 6 */
+#define NOR_CMD_INDEX_ERASEBLOCK 7 /*!< 7 */
+
+#define NOR_CMD_LUT_SEQ_IDX_READ 0 /*!< 0 READ LUT sequence id in lookupTable stored in config block */
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1 /*!< 1 Read Status LUT sequence id in lookupTable stored in config block */
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+ 2 /*!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block */
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3 /*!< 3 Write Enable sequence id in lookupTable stored in config block */
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+ 4 /*!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block */
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 /*!< 5 Erase Sector sequence id in lookupTable stored in config block */
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 /*!< 8 Erase Block sequence id in lookupTable stored in config block */
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9 /*!< 9 Program sequence id in lookupTable stored in config block */
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 /*!< 11 Chip Erase sequence in lookupTable id stored in config block */
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 /*!< 13 Read SFDP sequence in lookupTable id stored in config block */
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+ 14 /*!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block */
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+ 15 /*!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk */
+
+/*!
+ * @name FlexSPI status.
+ * @{
+ */
+/*! @brief FlexSPI Driver status group. */
+enum
+{
+ kStatusGroup_FlexSPI = 60,
+ kStatusGroup_FlexSPINOR = 201,
+};
+
+/*! @brief FlexSPI Driver status. */
+enum _flexspi_status
+{
+ kStatus_FLEXSPI_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< API is executed successfully*/
+ kStatus_FLEXSPI_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< API is executed fails*/
+ kStatus_FLEXSPI_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Invalid argument*/
+ kStatus_FLEXSPI_SequenceExecutionTimeout =
+ MAKE_STATUS(kStatusGroup_FlexSPI, 0), /*!< The FlexSPI Sequence Execution timeout*/
+ kStatus_FLEXSPI_InvalidSequence = MAKE_STATUS(kStatusGroup_FlexSPI, 1), /*!< The FlexSPI LUT sequence invalid*/
+ kStatus_FLEXSPI_DeviceTimeout = MAKE_STATUS(kStatusGroup_FlexSPI, 2), /*!< The FlexSPI device timeout*/
+ kStatus_FLEXSPINOR_ProgramFail =
+ MAKE_STATUS(kStatusGroup_FlexSPINOR, 0), /*!< Status for Page programming failure */
+ kStatus_FLEXSPINOR_EraseSectorFail =
+ MAKE_STATUS(kStatusGroup_FlexSPINOR, 1), /*!< Status for Sector Erase failure */
+ kStatus_FLEXSPINOR_EraseAllFail = MAKE_STATUS(kStatusGroup_FlexSPINOR, 2), /*!< Status for Chip Erase failure */
+ kStatus_FLEXSPINOR_WaitTimeout = MAKE_STATUS(kStatusGroup_FlexSPINOR, 3), /*!< Status for timeout */
+ kStatus_FLEXSPINOR_NotSupported = MAKE_STATUS(kStatusGroup_FlexSPINOR, 4), /* Status for PageSize overflow */
+ kStatus_FLEXSPINOR_WriteAlignmentError =
+ MAKE_STATUS(kStatusGroup_FlexSPINOR, 5), /*!< Status for Alignement error */
+ kStatus_FLEXSPINOR_CommandFailure =
+ MAKE_STATUS(kStatusGroup_FlexSPINOR, 6), /*!< Status for Erase/Program Verify Error */
+ kStatus_FLEXSPINOR_SFDP_NotFound = MAKE_STATUS(kStatusGroup_FlexSPINOR, 7), /*!< Status for SFDP read failure */
+ kStatus_FLEXSPINOR_Unsupported_SFDP_Version =
+ MAKE_STATUS(kStatusGroup_FlexSPINOR, 8), /*!< Status for Unrecognized SFDP version */
+ kStatus_FLEXSPINOR_Flash_NotFound =
+ MAKE_STATUS(kStatusGroup_FlexSPINOR, 9), /*!< Status for Flash detection failure */
+ kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed =
+ MAKE_STATUS(kStatusGroup_FlexSPINOR, 10), /*!< Status for DDR Read dummy probe failure */
+};
+/*! @} */
+
+/*! @brief Flash Configuration Option0 device_type. */
+enum
+{
+ kSerialNorCfgOption_Tag = 0x0c,
+ kSerialNorCfgOption_DeviceType_ReadSFDP_SDR = 0,
+ kSerialNorCfgOption_DeviceType_ReadSFDP_DDR = 1,
+ kSerialNorCfgOption_DeviceType_HyperFLASH1V8 = 2,
+ kSerialNorCfgOption_DeviceType_HyperFLASH3V0 = 3,
+ kSerialNorCfgOption_DeviceType_MacronixOctalDDR = 4,
+ kSerialNorCfgOption_DeviceType_MacronixOctalSDR = 5, /* For RT600 devcies only. */
+ kSerialNorCfgOption_DeviceType_MicronOctalDDR = 6,
+ kSerialNorCfgOption_DeviceType_MicronOctalSDR = 7, /* For RT600 devcies only. */
+ kSerialNorCfgOption_DeviceType_AdestoOctalDDR = 8,
+ kSerialNorCfgOption_DeviceType_AdestoOctalSDR = 9, /* For RT600 devcies only. */
+};
+
+/*! @brief Flash Configuration Option0 quad_mode_setting. */
+enum
+{
+ kSerialNorQuadMode_NotConfig = 0,
+ kSerialNorQuadMode_StatusReg1_Bit6 = 1,
+ kSerialNorQuadMode_StatusReg2_Bit1 = 2,
+ kSerialNorQuadMode_StatusReg2_Bit7 = 3,
+ kSerialNorQuadMode_StatusReg2_Bit1_0x31 = 4,
+};
+
+/*! @brief Flash Configuration Option0 misc_mode. */
+enum
+{
+ kSerialNorEnhanceMode_Disabled = 0,
+ kSerialNorEnhanceMode_0_4_4_Mode = 1,
+ kSerialNorEnhanceMode_0_8_8_Mode = 2,
+ kSerialNorEnhanceMode_DataOrderSwapped = 3,
+ kSerialNorEnhanceMode_2ndPinMux = 4,
+};
+
+/*! @brief FLEXSPI_RESET_PIN boot configurations in OTP */
+enum
+{
+ kFlashResetLogic_Disabled = 0,
+ kFlashResetLogic_ResetPin = 1,
+ kFlashResetLogic_JedecHwReset = 2,
+};
+
+/*! @brief Flash Configuration Option1 flash_connection. */
+enum
+{
+ kSerialNorConnection_SinglePortA,
+ kSerialNorConnection_Parallel,
+ kSerialNorConnection_SinglePortB,
+ kSerialNorConnection_BothPorts
+};
+
+/*! @brief Serial NOR Configuration Option */
+typedef struct _serial_nor_config_option
+{
+ union
+ {
+ struct
+ {
+ uint32_t max_freq : 4; /*!< Maximum supported Frequency */
+ uint32_t misc_mode : 4; /*!< miscellaneous mode */
+ uint32_t quad_mode_setting : 4; /*!< Quad mode setting */
+ uint32_t cmd_pads : 4; /*!< Command pads */
+ uint32_t query_pads : 4; /*!< SFDP read pads */
+ uint32_t device_type : 4; /*!< Device type */
+ uint32_t option_size : 4; /*!< Option size, in terms of uint32_t, size = (option_size + 1) * 4 */
+ uint32_t tag : 4; /*!< Tag, must be 0x0E */
+ } B;
+ uint32_t U;
+ } option0;
+
+ union
+ {
+ struct
+ {
+ uint32_t dummy_cycles : 8; /*!< Dummy cycles before read */
+ uint32_t status_override : 8; /*!< Override status register value during device mode configuration */
+ uint32_t pinmux_group : 4; /*!< The pinmux group selection */
+ uint32_t dqs_pinmux_group : 4; /*!< The DQS Pinmux Group Selection */
+ uint32_t drive_strength : 4; /*!< The Drive Strength of FlexSPI Pads */
+ uint32_t flash_connection : 4; /*!< Flash connection option: 0 - Single Flash connected to port A, 1 - */
+ /*! Parallel mode, 2 - Single Flash connected to Port B */
+ } B;
+ uint32_t U;
+ } option1;
+
+} serial_nor_config_option_t;
+
+/*! @brief Flash Run Context */
+typedef union
+{
+ struct
+ {
+ uint8_t por_mode;
+ uint8_t current_mode;
+ uint8_t exit_no_cmd_sequence;
+ uint8_t restore_sequence;
+ } B;
+ uint32_t U;
+} flash_run_context_t;
+
+/*!@brief Flash Device Mode Configuration Sequence */
+enum
+{
+ kRestoreSequence_None = 0,
+ kRestoreSequence_HW_Reset = 1,
+ kRestoreSequence_4QPI_FF = 2,
+ kRestoreSequence_5QPI_FF = 3,
+ kRestoreSequence_8QPI_FF = 4,
+ kRestoreSequence_Send_F0 = 5,
+ kRestoreSequence_Send_66_99 = 6,
+ kRestoreSequence_Send_6699_9966 = 7,
+ kRestoreSequence_Send_06_FF = 8, /* Adesto EcoXIP */
+};
+
+/*!@brief Flash Config Mode Definition */
+enum
+{
+ kFlashInstMode_ExtendedSpi = 0x00,
+ kFlashInstMode_0_4_4_SDR = 0x01,
+ kFlashInstMode_0_4_4_DDR = 0x02,
+ kFlashInstMode_QPI_SDR = 0x41,
+ kFlashInstMode_QPI_DDR = 0x42,
+ kFlashInstMode_OPI_SDR = 0x81, /* For RT600 devices only. */
+ kFlashInstMode_OPI_DDR = 0x82,
+};
+
+/*!@brief Flash Device Type Definition */
+enum
+{
+ kFlexSpiDeviceType_SerialNOR = 1, /*!< Flash devices are Serial NOR */
+ kFlexSpiDeviceType_SerialNAND = 2, /*!< Flash devices are Serial NAND */
+ kFlexSpiDeviceType_SerialRAM = 3, /*!< Flash devices are Serial RAM/HyperFLASH */
+ kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, /*!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */
+ kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, /*!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs */
+};
+
+/*!@brief Flash Pad Definitions */
+enum
+{
+ kSerialFlash_1Pad = 1,
+ kSerialFlash_2Pads = 2,
+ kSerialFlash_4Pads = 4,
+ kSerialFlash_8Pads = 8,
+};
+
+/*!@brief FlexSPI LUT Sequence structure */
+typedef struct _lut_sequence
+{
+ uint8_t seqNum; /*!< Sequence Number, valid number: 1-16 */
+ uint8_t seqId; /*!< Sequence Index, valid number: 0-15 */
+ uint16_t reserved;
+} flexspi_lut_seq_t;
+
+/*!@brief Flash Configuration Command Type */
+enum
+{
+ kDeviceConfigCmdType_Generic, /*!< Generic command, for example: configure dummy cycles, drive strength, etc */
+ kDeviceConfigCmdType_QuadEnable, /*!< Quad Enable command */
+ kDeviceConfigCmdType_Spi2Xpi, /*!< Switch from SPI to DPI/QPI/OPI mode */
+ kDeviceConfigCmdType_Xpi2Spi, /*!< Switch from DPI/QPI/OPI to SPI mode */
+ kDeviceConfigCmdType_Spi2NoCmd, /*!< Switch to 0-4-4/0-8-8 mode */
+ kDeviceConfigCmdType_Reset, /*!< Reset device command */
+};
+
+/*!@brief FlexSPI Dll Time Block */
+typedef struct
+{
+ uint8_t time_100ps; /* Data valid time, in terms of 100ps */
+ uint8_t delay_cells; /* Data valid time, in terms of delay cells */
+} flexspi_dll_time_t;
+
+/*!@brief FlexSPI Memory Configuration Block */
+typedef struct _FlexSPIConfig
+{
+ uint32_t tag; /*!< [0x000-0x003] Tag, fixed value 0x42464346UL */
+ uint32_t version; /*!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */
+ uint32_t reserved0; /*!< [0x008-0x00b] Reserved for future use */
+ uint8_t readSampleClkSrc; /*!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */
+ uint8_t csHoldTime; /*!< [0x00d-0x00d] CS hold time, default value: 3 */
+ uint8_t csSetupTime; /*!< [0x00e-0x00e] CS setup time, default value: 3 */
+ uint8_t columnAddressWidth; /*!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For */
+ /*! Serial NAND, need to refer to datasheet */
+ uint8_t deviceModeCfgEnable; /*!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */
+ uint8_t
+ deviceModeType; /*!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, */
+ /*! Generic configuration, etc. */
+ uint16_t waitTimeCfgCommands; /*!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for */
+ /*! DPI/QPI/OPI switch or reset command */
+ flexspi_lut_seq_t
+ deviceModeSeq; /*!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt */
+ /*! sequence number, [31:16] Reserved */
+ uint32_t deviceModeArg; /*!< [0x018-0x01b] Argument/Parameter for device configuration */
+ uint8_t configCmdEnable; /*!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */
+ uint8_t configModeType[3]; /*!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */
+ flexspi_lut_seq_t
+ configCmdSeqs[3]; /*!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq */
+ uint32_t reserved1; /*!< [0x02c-0x02f] Reserved for future use */
+ uint32_t configCmdArgs[3]; /*!< [0x030-0x03b] Arguments/Parameters for device Configuration commands */
+ uint32_t reserved2; /*!< [0x03c-0x03f] Reserved for future use */
+ uint32_t
+ controllerMiscOption; /*!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more */
+ /*! details */
+ uint8_t deviceType; /*!< [0x044-0x044] Device Type: See Flash Type Definition for more details */
+ uint8_t sflashPadType; /*!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */
+ uint8_t serialClkFreq; /*!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot */
+ /*! Chapter for more details */
+ uint8_t
+ lutCustomSeqEnable; /*!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot */
+ /*! be done using 1 LUT sequence, currently, only applicable to HyperFLASH */
+ uint32_t reserved3[2]; /*!< [0x048-0x04f] Reserved for future use */
+ uint32_t sflashA1Size; /*!< [0x050-0x053] Size of Flash connected to A1 */
+ uint32_t sflashA2Size; /*!< [0x054-0x057] Size of Flash connected to A2 */
+ uint32_t sflashB1Size; /*!< [0x058-0x05b] Size of Flash connected to B1 */
+ uint32_t sflashB2Size; /*!< [0x05c-0x05f] Size of Flash connected to B2 */
+ uint32_t csPadSettingOverride; /*!< [0x060-0x063] CS pad setting override value */
+ uint32_t sclkPadSettingOverride; /*!< [0x064-0x067] SCK pad setting override value */
+ uint32_t dataPadSettingOverride; /*!< [0x068-0x06b] data pad setting override value */
+ uint32_t dqsPadSettingOverride; /*!< [0x06c-0x06f] DQS pad setting override value */
+ uint32_t timeoutInMs; /*!< [0x070-0x073] Timeout threshold for read status command */
+ uint32_t commandInterval; /*!< [0x074-0x077] CS deselect interval between two commands */
+ flexspi_dll_time_t dataValidTime[2]; /*!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */
+ uint16_t busyOffset; /*!< [0x07c-0x07d] Busy offset, valid value: 0-31 */
+ uint16_t
+ busyBitPolarity; /*!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - */
+ /*! busy flag is 0 when flash device is busy */
+ uint32_t lookupTable[64]; /*!< [0x080-0x17f] Lookup table holds Flash command sequences */
+ flexspi_lut_seq_t lutCustomSeq[12]; /*!< [0x180-0x1af] Customizable LUT Sequences */
+ uint32_t reserved4[4]; /*!< [0x1b0-0x1bf] Reserved for future use */
+} flexspi_mem_config_block_t;
+
+/*!@brief FlexSPI Operation Type */
+typedef enum _FlexSPIOperationType
+{
+ kFlexSpiOperation_Command = 0, /*!< FlexSPI operation: Only command, both TX and */
+ /*! RX buffer are ignored. */
+ kFlexSpiOperation_Config = 1, /*!< FlexSPI operation: Configure device mode, the */
+ /*! TX FIFO size is fixed in LUT. */
+ kFlexSpiOperation_Write = 2, /*!< FlexSPI operation: Write, only TX buffer is */
+ /*! effective */
+ kFlexSpiOperation_Read = 3, /*!< FlexSPI operation: Read, only Rx Buffer is */
+ /*! effective. */
+ kFlexSpiOperation_End = kFlexSpiOperation_Read,
+} flexspi_operation_t;
+
+/*!@brief FlexSPI Transfer Context */
+typedef struct _FlexSpiXfer
+{
+ flexspi_operation_t operation; /*!< FlexSPI operation */
+ uint32_t baseAddress; /*!< FlexSPI operation base address */
+ uint32_t seqId; /*!< Sequence Id */
+ uint32_t seqNum; /*!< Sequence Number */
+ bool isParallelModeEnable; /*!< Is a parallel transfer */
+ uint32_t *txBuffer; /*!< Tx buffer */
+ uint32_t txSize; /*!< Tx size in bytes */
+ uint32_t *rxBuffer; /*!< Rx buffer */
+ uint32_t rxSize; /*!< Rx size in bytes */
+} flexspi_xfer_t;
+
+/*!@brief Serial NOR configuration block */
+typedef struct _flexspi_nor_config
+{
+ flexspi_mem_config_block_t memConfig; /*!< Common memory configuration info via FlexSPI */
+ uint32_t pageSize; /*!< Page size of Serial NOR */
+ uint32_t sectorSize; /*!< Sector size of Serial NOR */
+ uint8_t ipcmdSerialClkFreq; /*!< Clock frequency for IP command */
+ uint8_t isUniformBlockSize; /*!< Sector/Block size is the same */
+ uint8_t isDataOrderSwapped; /*!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */
+ uint8_t reserved0[1]; /*!< Reserved for future use */
+ uint8_t serialNorType; /*!< Serial NOR Flash type: 0/1/2/3 */
+ uint8_t needExitNoCmdMode; /*!< Need to exit NoCmd mode before other IP command */
+ uint8_t halfClkForNonReadCmd; /*!< Half the Serial Clock for non-read command: true/false */
+ uint8_t needRestoreNoCmdMode; /*!< Need to Restore NoCmd mode after IP commmand execution */
+ uint32_t blockSize; /*!< Block size */
+ uint32_t flashStateCtx; /*!< Flash State Context */
+ uint32_t reserve2[10]; /*!< Reserved for future use */
+} flexspi_nor_config_t;
+/*! @} */
+
+/*!
+ * @addtogroup iap_otp_driver
+ * @{
+ */
+
+/*! @brief OTP Status Group */
+enum
+{
+ kStatusGroup_OtpGroup = 0x210,
+};
+
+/*! @brief OTP Error Status definitions */
+enum
+{
+ kStatus_OTP_InvalidAddress = MAKE_STATUS(kStatusGroup_OtpGroup, 1), /*!< Invalid OTP address */
+ kStatus_OTP_ProgramFail = MAKE_STATUS(kStatusGroup_OtpGroup, 2), /*!< Program Fail */
+ kStatus_OTP_CrcFail = MAKE_STATUS(kStatusGroup_OtpGroup, 3), /*!< CrcCheck Fail */
+ kStatus_OTP_Error = MAKE_STATUS(kStatusGroup_OtpGroup, 4), /*!< Errors happened during OTP operation */
+ kStatus_OTP_EccCheckFail = MAKE_STATUS(kStatusGroup_OtpGroup, 5), /*!< Ecc Check failed during OTP operation */
+ kStatus_OTP_Locked = MAKE_STATUS(kStatusGroup_OtpGroup, 6), /*!< OTP Fuse field has been locked */
+ kStatus_OTP_Timeout = MAKE_STATUS(kStatusGroup_OtpGroup, 7), /*!< OTP operation time out */
+ kStatus_OTP_CrcCheckPass = MAKE_STATUS(kStatusGroup_OtpGroup, 8), /*!< OTP CRC Check Pass */
+};
+/*! @} */
+
+/*!
+ * @addtogroup iap_boot_driver
+ * @{
+ */
+
+/*! @brief IAP boot option. */
+typedef struct _iap_boot_option
+{
+ union
+ {
+ struct
+ {
+ uint32_t reserved : 8; /*! reserved field. */
+ uint32_t bootImageIndex : 4; /*! FlexSPI boot image index for FlexSPI NOR flash. */
+ uint32_t instance : 4; /*! Only used when boot interface is FlexSPI/SD/MMC. */
+ uint32_t bootInterface : 4; /*! RT500: 0: USART 2: SPI 3: USB HID 4:FlexSPI 6:SD 7:MMC.
+ RT600: 0: USART 1: I2C 2: SPI 3: USB HID 4:FlexSPI 7:SD 8:MMC*/
+ uint32_t mode : 4; /* boot mode, 0: Master boot mode; 1: ISP boot */
+ uint32_t tag : 8; /*! tag, should always be "0xEB". */
+ } B;
+ uint32_t U;
+ } option;
+} iap_boot_option_t;
+
+/*! IAP boot option tag */
+#define IAP_BOOT_OPTION_TAG (0xEBU)
+/*! IAP boot option mode */
+#define IAP_BOOT_OPTION_MODE_MASTER (0U)
+#define IAP_BOOT_OPTION_MODE_ISP (1U)
+
+/*! @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @addtogroup iap_boot_driver
+ * @{
+ */
+
+/*!
+ * @brief Invoke into ROM with specified boot parameters.
+ *
+ * @param option Boot parameters. Refer to #iap_boot_option_t.
+ */
+void IAP_RunBootLoader(iap_boot_option_t *option);
+/*! @} */
+
+/*!
+ * @addtogroup iap_flexspi_driver
+ * @{
+ */
+
+/*!
+ * @brief Initialize Serial NOR devices via FlexSPI.
+ *
+ * This function configures the FlexSPI controller with the arguments pointed by param config.
+ *
+ * @param instance FlexSPI controller instance, only support 0.
+ * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
+ * @return The status flags. This is a member of the
+ * enumeration ::_flexspi_status
+ */
+#if defined(DOXYGEN_OUTPUT) && DOXYGEN_OUTPUT
+status_t IAP_FlexspiNorInit(uint32_t instance, flexspi_nor_config_t *config);
+#else
+AT_QUICKACCESS_SECTION_CODE(status_t IAP_FlexspiNorInit(uint32_t instance, flexspi_nor_config_t *config));
+#endif
+
+/*!
+ * @brief Program data to Serial NOR via FlexSPI.
+ *
+ * This function Program data to specified destination address.
+ *
+ * @param instance FlexSPI controller instance, only support 0.
+ * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
+ * @param dstAddr The destination address to be programmed.
+ * @param src Points to the buffer which hold the data to be programmed.
+ * @return The status flags. This is a member of the
+ * enumeration ::_flexspi_status
+ */
+status_t IAP_FlexspiNorPageProgram(uint32_t instance,
+ flexspi_nor_config_t *config,
+ uint32_t dstAddr,
+ const uint32_t *src);
+
+/*!
+ * @brief Erase all the Serial NOR devices connected on FlexSPI.
+ *
+ * @param instance FlexSPI controller instance, only support 0.
+ * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
+ * @return The status flags. This is a member of the
+ * enumeration ::_flexspi_status
+ */
+status_t IAP_FlexspiNorEraseAll(uint32_t instance, flexspi_nor_config_t *config);
+
+/*!
+ * @brief Erase Flash Region specified by address and length.
+ *
+ * @param instance FlexSPI controller instance, only support 0.
+ * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
+ * @param start The start address to be erased.
+ * @param length The length to be erased.
+ * @return The status flags. This is a member of the
+ * enumeration ::_flexspi_status
+ */
+status_t IAP_FlexspiNorErase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length);
+
+/*!
+ * @brief Erase one sector specified by address.
+ *
+ * @param instance FlexSPI controller instance, only support 0.
+ * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
+ * @param address The address of the sector to be erased.
+ * @return The status flags. This is a member of the
+ * enumeration ::_flexspi_status
+ */
+status_t IAP_FlexspiNorEraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
+
+/*!
+ * @brief Erase one block specified by address.
+ *
+ * @param instance FlexSPI controller instance, only support 0.
+ * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
+ * @param address The address of the block to be erased.
+ * @return The status flags. This is a member of the
+ * enumeration ::_flexspi_status
+ */
+status_t IAP_FlexspiNorEraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
+
+/*!
+ * @brief Get FlexSPI NOR Configuration Block based on specified option.
+ *
+ * @param instance FlexSPI controller instance, only support 0.
+ * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
+ * @param option The Flash Configuration Option block. Refer to #serial_nor_config_option_t.
+ * @return The status flags. This is a member of the
+ * enumeration ::_flexspi_status
+ */
+status_t IAP_FlexspiNorGetConfig(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option);
+
+/*!
+ * @brief Read data from Flexspi NOR Flash.
+ *
+ * @param instance FlexSPI controller instance, only support 0.
+ * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
+ * @param dst Buffer address used to store the read data.
+ * @param start The Read address.
+ * @param bytes The Read size
+ * @return The status flags. This is a member of the
+ * enumeration ::_flexspi_status
+ */
+status_t IAP_FlexspiNorRead(
+ uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes);
+
+/*!
+ * @brief Get FlexSPI Xfer data.
+ *
+ * @param instance FlexSPI controller instance, only support 0.
+ * @param xfer The FlexSPI Transfer Context block. Refer to #flexspi_xfer_t.
+ * @return The status flags. This is a member of the
+ * enumeration ::_flexspi_status
+ */
+status_t IAP_FlexspiXfer(uint32_t instance, flexspi_xfer_t *xfer);
+
+/*!
+ * @brief Update FlexSPI Lookup table.
+ *
+ * @param instance FlexSPI controller instance, only support 0.
+ * @param seqIndex The index of FlexSPI LUT to be updated.
+ * @param lutBase Points to the buffer which hold the LUT data to be programmed.
+ * @param numberOfSeq The number of LUT seq that need to be updated.
+ * @return The status flags. This is a member of the
+ * enumeration ::_flexspi_status
+ */
+status_t IAP_FlexspiUpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq);
+
+/*!
+ * @brief Set the clock source for FlexSPI.
+ *
+ * @param clockSrc Clock source for flexspi interface.
+ * @return The status flags. This is a member of the
+ * enumeration ::_flexspi_status
+ */
+status_t IAP_FlexspiSetClockSource(uint32_t clockSrc);
+
+/*!
+ * @brief Configure the flexspi interface clock frequency and data sample mode.
+ *
+ * @param instance FlexSPI controller instance, only support 0.
+ * @param freqOption FlexSPI interface clock frequency selection.
+ * @param sampleClkMode FlexSPI controller data sample mode.
+ * @return The status flags. This is a member of the
+ * enumeration ::_flexspi_status
+ */
+void IAP_FlexspiConfigClock(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode);
+
+/*!
+ * @brief Configure flexspi nor automatically.
+ *
+ * @param instance FlexSPI controller instance, only support 0.
+ * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
+ * @param option The Flash Configuration Option block. Refer to #serial_nor_config_option_t.
+ * @return The status flags. This is a member of the
+ * enumeration ::_flexspi_status
+ */
+#if defined(DOXYGEN_OUTPUT) && DOXYGEN_OUTPUT
+status_t IAP_FlexspiNorAutoConfig(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option);
+#else
+AT_QUICKACCESS_SECTION_CODE(status_t IAP_FlexspiNorAutoConfig(uint32_t instance,
+ flexspi_nor_config_t *config,
+ serial_nor_config_option_t *option));
+#endif
+/*! @} */
+
+/*!
+ * @addtogroup iap_otp_driver
+ * @{
+ */
+
+/*!
+ * @brief Initialize OTP controller
+ *
+ * This function enables OTP Controller clock.
+ *
+ * @param src_clk_freq The Frequency of the source clock of OTP controller
+ * @return kStatus_Success
+ */
+status_t IAP_OtpInit(uint32_t src_clk_freq);
+
+/*!
+ * @brief De-Initialize OTP controller
+ *
+ * This functin disables OTP Controller Clock.
+ * @return kStatus_Success
+ */
+status_t IAP_OtpDeinit(void);
+
+/*!
+ * @brief Read Fuse value from OTP Fuse Block
+ *
+ * This function read fuse data from OTP Fuse block to specified data buffer.
+ *
+ * @param addr Fuse address
+ * @param data Buffer to hold the data read from OTP Fuse block
+ * @return kStatus_Success - Data read from OTP Fuse block successfully
+ * kStatus_InvalidArgument - data pointer is invalid
+ * kStatus_OTP_EccCheckFail - Ecc Check Failed
+ * kStatus_OTP_Error - Other Errors
+ */
+status_t IAP_OtpFuseRead(uint32_t addr, uint32_t *data);
+
+/*!
+ * @brief Program value to OTP Fuse block
+ *
+ * This function program data to specified OTP Fuse address.
+ *
+ * @param addr Fuse address
+ * @param data data to be programmed into OTP Fuse block
+ * @param lock lock the fuse field or not
+ * @return kStatus_Success - Data has been programmed into OTP Fuse block successfully
+ * kStatus_OTP_ProgramFail - Fuse programming failed
+ * kStatus_OTP_Locked - The address to be programmed into is locked
+ * kStatus_OTP_Error - Other Errors
+ */
+status_t IAP_OtpFuseProgram(uint32_t addr, uint32_t data, bool lock);
+
+/*!
+ * @brief Reload all shadow registers from OTP fuse block
+ *
+ * This function reloads all the shadow registers from OTP Fuse block
+ *
+ * @return kStatus_Success - Shadow registers' reloadding succeeded.
+ * kStatus_OTP_EccCheckFail - Ecc Check Failed
+ * kStatus_OTP_Error - Other Errors
+ */
+status_t IAP_OtpShadowRegisterReload(void);
+
+/*!
+ * @brief Do CRC Check via OTP controller
+ *
+ * This function checks whether data in specified fuse address ranges match the crc value in the specified CRC address
+ * and return the actual crc value as needed.
+ *
+ * @param start_addr Start address of selected Fuse address range
+ * @param end_addr End address of selected Fuse address range
+ * @param crc_addr Address that hold CRC data
+ *
+ * @return kStatus_Success CRC check succeeded, CRC value matched.
+ * kStatus_InvalidArgument - Invalid Argument
+ * kStatus_OTP_EccCheckFail Ecc Check Failed
+ * kStatus_OTP_CrcFail CRC Check Failed
+ */
+status_t IAP_OtpCrcCheck(uint32_t start_addr, uint32_t end_addr, uint32_t crc_addr);
+
+/*!
+ * @brief Calculate the CRC checksum for specified data for OTP
+ *
+ * This function calculates the CRC checksum for specified data for OTP
+ *
+ * @param src the source address of data
+ * @param numberOfWords number of Fuse words
+ * @param crcChecksum Buffer to store the CRC checksum
+ *
+ * @return kStatus_Success CRC checksum is computed successfully.
+ * kStatus_InvalidArgument - Invalid Argument
+ */
+status_t IAP_OtpCrcCalc(uint32_t *src, uint32_t numberOfWords, uint32_t *crcChecksum);
+/*! @} */
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_IAP_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_iopctl.h b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_iopctl.h
new file mode 100644
index 000000000..144f020ff
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_iopctl.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2013-2016, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOPCTL_H_
+#define _FSL_IOPCTL_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iopctl_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpc_iopctl"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOPCTL driver version 2.0.0. */
+#define LPC_IOPCTL_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/**
+ * @brief Array of IOPCTL pin definitions passed to IOPCTL_SetPinMuxing() must be in this format
+ */
+typedef struct _iopctl_group
+{
+ uint32_t port : 8; /* Pin port */
+ uint32_t pin : 32; /* Pin number */
+ uint32_t modefunc : 12; /* Function and mode */
+} iopctl_group_t;
+
+/**
+ * @brief IOPCTL function and mode selection definitions
+ * @note See the User Manual for specific modes and functions supported by the various pins.
+ */
+#define IOPCTL_FUNC0 0x0 /*!< Selects pin function 0 */
+#define IOPCTL_FUNC1 0x1 /*!< Selects pin function 1 */
+#define IOPCTL_FUNC2 0x2 /*!< Selects pin function 2 */
+#define IOPCTL_FUNC3 0x3 /*!< Selects pin function 3 */
+#define IOPCTL_FUNC4 0x4 /*!< Selects pin function 4 */
+#define IOPCTL_FUNC5 0x5 /*!< Selects pin function 5 */
+#define IOPCTL_FUNC6 0x6 /*!< Selects pin function 6 */
+#define IOPCTL_FUNC7 0x7 /*!< Selects pin function 7 */
+#define IOPCTL_FUNC8 0x8 /*!< Selects pin function 8 */
+#define IOPCTL_FUNC9 0x9 /*!< Selects pin function 9 */
+#define IOPCTL_FUNC10 0xA /*!< Selects pin function 10 */
+#define IOPCTL_FUNC11 0xB /*!< Selects pin function 11 */
+#define IOPCTL_FUNC12 0xC /*!< Selects pin function 12 */
+#define IOPCTL_FUNC13 0xD /*!< Selects pin function 13 */
+#define IOPCTL_FUNC14 0xE /*!< Selects pin function 14 */
+#define IOPCTL_FUNC15 0xF /*!< Selects pin function 15 */
+#define IOPCTL_PUPD_EN (0x1 << 4) /*!< Enables Pullup / Pulldown */
+#define IOPCTL_PULLDOWN_EN (0x0 << 5) /*!< Selects pull-down function */
+#define IOPCTL_PULLUP_EN (0x1 << 5) /*!< Selects pull-up function */
+#define IOPCTL_INBUF_EN (0x1 << 6) /*!< Enables buffer function on input */
+#define IOPCTL_SLEW_RATE (0x0 << 7) /*!< Slew Rate Control */
+#define IOPCTL_FULLDRIVE_EN (0x1 << 8) /*!< Selects full drive */
+#define IOPCTL_ANAMUX_EN (0x1 << 9) /*!< Enables analog mux function by setting 0 to bit 7 */
+#define IOPCTL_PSEDRAIN_EN (0x1 << 10) /*!< Enables pseudo output drain function */
+#define IOPCTL_INV_EN (0x1 << 11) /*!< Enables invert function on input */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * @brief Sets I/O Pad Control pin mux
+ * @param base : The base of IOPCTL peripheral on the chip
+ * @param port : Port to mux
+ * @param pin : Pin to mux
+ * @param modefunc : OR'ed values of type IOPCTL_*
+ * @return Nothing
+ */
+__STATIC_INLINE void IOPCTL_PinMuxSet(IOPCTL_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc)
+{
+ base->PIO[port][pin] = modefunc;
+}
+
+/**
+ * @brief Set all I/O Control pin muxing
+ * @param base : The base of IOPCTL peripheral on the chip
+ * @param pinArray : Pointer to array of pin mux selections
+ * @param arrayLength : Number of entries in pinArray
+ * @return Nothing
+ */
+__STATIC_INLINE void IOPCTL_SetPinMuxing(IOPCTL_Type *base, const iopctl_group_t *pinArray, uint32_t arrayLength)
+{
+ uint32_t i;
+
+ for (i = 0; i < arrayLength; i++)
+ {
+ IOPCTL_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc);
+ }
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_IOPCTL_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_power.c b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_power.c
new file mode 100644
index 000000000..0885f2c69
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_power.c
@@ -0,0 +1,1226 @@
+/*
+ * Copyright 2018-2021, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_common.h"
+#include "fsl_power.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+AT_QUICKACCESS_SECTION_DATA(static uint32_t oscSettlingTime);
+AT_QUICKACCESS_SECTION_DATA(static uint32_t pmicVddcoreRecoveryTime);
+AT_QUICKACCESS_SECTION_DATA(static uint32_t lvdChangeFlag);
+AT_QUICKACCESS_SECTION_DATA(static power_deep_sleep_clk_t deepSleepClk);
+
+#define MEGA (1000000U)
+
+const uint32_t powerFreqLevel[POWER_FREQ_LEVELS_NUM] = {275U * MEGA, 230U * MEGA, 192U * MEGA, 100U * MEGA, 60U * MEGA};
+
+static const uint32_t powerLdoVoltLevel[POWER_FREQ_LEVELS_NUM] = {
+ 0x2FU, /* 1.1V */
+ 0x26U, /* 1.0V */
+ 0x1DU, /* 0.9V */
+ 0x13U, /* 0.8V */
+ 0x0AU, /* 0.7V */
+};
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.power"
+#endif
+
+#define PCFG0_XBB_MASK \
+ (SYSCTL0_PDSLEEPCFG0_RBB_PD_MASK | SYSCTL0_PDSLEEPCFG0_FBB_PD_MASK | SYSCTL0_PDSLEEPCFG0_RBBSRAM_PD_MASK)
+
+/* DeepSleep PDSLEEP0 */
+#define PCFG0_DEEP_SLEEP \
+ (SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF_MASK | SYSCTL0_PDSLEEPCFG0_VDDCOREREG_LP_MASK | \
+ SYSCTL0_PDSLEEPCFG0_PMCREF_LP_MASK | SYSCTL0_PDSLEEPCFG0_HVD1V8_PD_MASK | SYSCTL0_PDSLEEPCFG0_LVDCORE_LP_MASK | \
+ SYSCTL0_PDSLEEPCFG0_PORCORE_LP_MASK | SYSCTL0_PDSLEEPCFG0_HVDCORE_PD_MASK | SYSCTL0_PDSLEEPCFG0_RBB_PD_MASK | \
+ SYSCTL0_PDSLEEPCFG0_FBB_PD_MASK | SYSCTL0_PDSLEEPCFG0_SYSXTAL_PD_MASK | SYSCTL0_PDSLEEPCFG0_LPOSC_PD_MASK | \
+ SYSCTL0_PDSLEEPCFG0_RBBSRAM_PD_MASK | SYSCTL0_PDSLEEPCFG0_FFRO_PD_MASK | SYSCTL0_PDSLEEPCFG0_SYSPLLLDO_PD_MASK | \
+ SYSCTL0_PDSLEEPCFG0_SYSPLLANA_PD_MASK | SYSCTL0_PDSLEEPCFG0_AUDPLLLDO_PD_MASK | \
+ SYSCTL0_PDSLEEPCFG0_AUDPLLANA_PD_MASK | SYSCTL0_PDSLEEPCFG0_ADC_PD_MASK | SYSCTL0_PDSLEEPCFG0_ADC_LP_MASK | \
+ SYSCTL0_PDSLEEPCFG0_ADC_TEMPSNS_PD_MASK | SYSCTL0_PDSLEEPCFG0_PMC_TEMPSNS_PD_MASK | \
+ SYSCTL0_PDSLEEPCFG0_ACMP_PD_MASK | SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_VDET_LP_MASK | \
+ SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_REF_PD_MASK | SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_VDET_LP_MASK | \
+ SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_REF_PD_MASK | SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_VDET_LP_MASK | \
+ SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_REF_PD_MASK)
+
+/* DeepSleep PDSLEEP1 */
+#define PCFG1_DEEP_SLEEP \
+ (SYSCTL0_PDSLEEPCFG1_PQ_SRAM_PPD_MASK | SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_APD_MASK | \
+ SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_PPD_MASK | SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_APD_MASK | \
+ SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_PPD_MASK | SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_APD_MASK | \
+ SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_PPD_MASK | SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_APD_MASK | \
+ SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_PPD_MASK | SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_APD_MASK | \
+ SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_PPD_MASK | SYSCTL0_PDSLEEPCFG1_CASPER_SRAM_PPD_MASK | \
+ SYSCTL0_PDSLEEPCFG1_GPU_SRAM_APD_MASK | SYSCTL0_PDSLEEPCFG1_GPU_SRAM_PPD_MASK | \
+ SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_APD_MASK | SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_PPD_MASK | \
+ SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_APD_MASK | SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_PPD_MASK | \
+ SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_APD_MASK | SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_PPD_MASK | \
+ SYSCTL0_PDSLEEPCFG1_DSP_PD_MASK | SYSCTL0_PDSLEEPCFG1_MIPIDSI_PD_MASK | SYSCTL0_PDSLEEPCFG1_OTP_PD_MASK | \
+ SYSCTL0_PDSLEEPCFG1_ROM_PD_MASK | SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_VDET_LP_MASK | \
+ SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_REF_PD_MASK | SYSCTL0_PDSLEEPCFG1_SRAM_SLEEP_MASK)
+
+/* DeepSleep PDSLEEP2 */
+#define PCFG2_DEEP_SLEEP 0xFFFFFFFFU
+
+/* DeepSleep PDSLEEP3 */
+#define PCFG3_DEEP_SLEEP 0xFFFFFFFFU
+
+/* System PLL PFD mask */
+#define SYSPLL0PFD_PFD_MASK \
+ (CLKCTL0_SYSPLL0PFD_PFD0_MASK | CLKCTL0_SYSPLL0PFD_PFD1_MASK | CLKCTL0_SYSPLL0PFD_PFD2_MASK | \
+ CLKCTL0_SYSPLL0PFD_PFD3_MASK)
+#define SYSPLL0PFD_PFD_CLKRDY_MASK \
+ (CLKCTL0_SYSPLL0PFD_PFD0_CLKRDY_MASK | CLKCTL0_SYSPLL0PFD_PFD1_CLKRDY_MASK | CLKCTL0_SYSPLL0PFD_PFD2_CLKRDY_MASK | \
+ CLKCTL0_SYSPLL0PFD_PFD3_CLKRDY_MASK)
+#define SYSPLL0PFD_PFD_CLKGATE_MASK \
+ (CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_MASK | CLKCTL0_SYSPLL0PFD_PFD1_CLKGATE_MASK | \
+ CLKCTL0_SYSPLL0PFD_PFD2_CLKGATE_MASK | CLKCTL0_SYSPLL0PFD_PFD3_CLKGATE_MASK)
+
+/*Audio PLL PFD mask*/
+#define AUDIOPLL0PFD_PFD_MASK \
+ (CLKCTL1_AUDIOPLL0PFD_PFD0_MASK | CLKCTL1_AUDIOPLL0PFD_PFD1_MASK | CLKCTL1_AUDIOPLL0PFD_PFD2_MASK | \
+ CLKCTL1_AUDIOPLL0PFD_PFD3_MASK)
+#define AUDIOPLL0PFD_PFD_CLKRDY_MASK \
+ (CLKCTL1_AUDIOPLL0PFD_PFD0_CLKRDY_MASK | CLKCTL1_AUDIOPLL0PFD_PFD1_CLKRDY_MASK | \
+ CLKCTL1_AUDIOPLL0PFD_PFD2_CLKRDY_MASK | CLKCTL1_AUDIOPLL0PFD_PFD3_CLKRDY_MASK)
+#define AUDIOPLL0PFD_PFD_CLKGATE_MASK \
+ (CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK | CLKCTL1_AUDIOPLL0PFD_PFD1_CLKGATE_MASK | \
+ CLKCTL1_AUDIOPLL0PFD_PFD2_CLKGATE_MASK | CLKCTL1_AUDIOPLL0PFD_PFD3_CLKGATE_MASK)
+
+#define PDWAKECFG_RBBKEEPST_MASK (0x1U)
+#define PDWAKECFG_FBBKEEPST_MASK (0x2U)
+#define PDWAKECFG_RBBSRAMKEEPST_MASK (0x4U)
+
+#define IS_SYSPLL_ON(pdruncfg) \
+ (((pdruncfg) & (SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK)) == 0U)
+#define IS_AUDPLL_ON(pdruncfg) \
+ (((pdruncfg) & (SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK)) == 0U)
+
+/* CPU running 1MHz, each instruction 1us, each loop 4 instructions. Each loop 4us.
+ * CPU running 24MHz, each instruction 1/24 us, each loop 4 instructions. 6 loops per us.
+ * CPU running 48MHz, each instruction 1/48 us, each loop 4 instructions. 12 loops per us. */
+#define US2LOOP(clk, x) ((clk) == kDeepSleepClk_LpOsc ? (x) / 4U : (x)*6U * (CLK_FRO_CLK / 96000000U))
+
+#define IS_XIP_FLEXSPI0() \
+ ((((uint32_t)POWER_ApplyPD >= 0x08000000U) && ((uint32_t)POWER_ApplyPD < 0x10000000U)) || \
+ (((uint32_t)POWER_ApplyPD >= 0x18000000U) && ((uint32_t)POWER_ApplyPD < 0x20000000U)))
+#define IS_XIP_FLEXSPI1() \
+ ((((uint32_t)POWER_ApplyPD >= 0x28000000U) && ((uint32_t)POWER_ApplyPD < 0x30000000U)) || \
+ (((uint32_t)POWER_ApplyPD >= 0x38000000U) && ((uint32_t)POWER_ApplyPD < 0x40000000U)))
+#define FLEXSPI_DLL_LOCK_RETRY (10U)
+
+#define PMC_DECREASE_LVD_LEVEL_IF_HIGHER_THAN(level) \
+ do \
+ { \
+ if (((PMC->LVDCORECTRL & PMC_LVDCORECTRL_LVDCORELVL_MASK) >> PMC_LVDCORECTRL_LVDCORELVL_SHIFT) > \
+ ((uint32_t)(level))) \
+ { \
+ PMC->LVDCORECTRL = PMC_LVDCORECTRL_LVDCORELVL(kLvdFallingTripVol_720); \
+ } \
+ } while (false)
+
+#define PMC_REG(off) (*((volatile uint32_t *)(void *)PMC + (off) / 4U))
+
+#define PMU_MIN_CLOCK_MHZ (14U)
+/* Turn on all partitions in parallel.
+ * Be cautious to change the PMC_MEM_SEQ_NUM. To save code size, countPartitionSwitches() counted with 0x3F.
+ */
+#define PMC_MEM_SEQ_NUM (0x3FU)
+#define SYSCTL0_PDRUNCFG1_MEM_BITS_MASK (0x103FEFFEU)
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Configure bias voltage level and enable/disable pull-down.
+ *
+ * This function change the RBB&FBB voltage level and RBB pull-down.
+ */
+AT_QUICKACCESS_SECTION_CODE(static void POWER_SetBiasConfig(void))
+{
+ if (PMC_REG(0x20U) != 0x84040808U)
+ {
+ PMC_REG(0x20U) = 0x84040808U;
+ }
+ if (PMC->SLEEPCTRL != PMC_SLEEPCTRL_CORELVL(1))
+ {
+ /* Deep sleep core voltage 0.6V */
+ PMC->SLEEPCTRL = PMC_SLEEPCTRL_CORELVL(1);
+ }
+}
+
+static uint32_t POWER_CalcVoltLevel(uint32_t cm33_clk_freq, uint32_t dsp_clk_freq)
+{
+ uint32_t i;
+ uint32_t volt;
+ uint32_t freq = MAX(cm33_clk_freq, dsp_clk_freq);
+
+ for (i = 0U; i < POWER_FREQ_LEVELS_NUM; i++)
+ {
+ if (freq > powerFreqLevel[i])
+ {
+ break;
+ }
+ }
+
+ if (i == 0U) /* Frequency exceed max supported */
+ {
+ volt = POWER_INVALID_VOLT_LEVEL;
+ }
+ else
+ {
+ volt = powerLdoVoltLevel[i - 1U];
+ }
+
+ return volt;
+}
+
+void POWER_DisableLVD(void)
+{
+ if ((PMC->CTRL & (PMC_CTRL_LVDCORERE_MASK | PMC_CTRL_LVDCOREIE_MASK)) != 0U)
+ {
+ lvdChangeFlag = PMC->CTRL & (PMC_CTRL_LVDCORERE_MASK | PMC_CTRL_LVDCOREIE_MASK);
+ PMC->CTRL &= ~(PMC_CTRL_LVDCORERE_MASK | PMC_CTRL_LVDCOREIE_MASK);
+ }
+}
+
+void POWER_RestoreLVD(void)
+{
+ PMC->CTRL |= lvdChangeFlag & (PMC_CTRL_LVDCORERE_MASK | PMC_CTRL_LVDCOREIE_MASK);
+ lvdChangeFlag = 0;
+}
+
+/**
+ * @brief API to update XTAL oscillator settling time .
+ * @param osc_delay : OSC stabilization time in unit of microsecond
+ */
+void POWER_UpdateOscSettlingTime(uint32_t osc_delay)
+{
+ oscSettlingTime = osc_delay;
+}
+
+/**
+ * @brief API to update on-board PMIC vddcore recovery time.
+ * @param pmic_delay : PMIC stabilization time in unit of microsecond
+ */
+void POWER_UpdatePmicRecoveryTime(uint32_t pmic_delay)
+{
+ pmicVddcoreRecoveryTime = pmic_delay;
+}
+
+/*!
+ * @brief API to enable PDRUNCFG bit in the Sysctl0. Note that enabling the bit powers down the peripheral
+ *
+ * @param en peripheral for which to enable the PDRUNCFG bit
+ * @return none
+ */
+void POWER_EnablePD(pd_bit_t en)
+{
+ /* PDRUNCFGSET */
+ SYSCTL0_PDRCFGSET_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU));
+
+ if (en == kPDRUNCFG_PD_OTP)
+ {
+ PMC->CTRL |= PMC_CTRL_OTPSWREN_MASK; /* Enable RBB for OTP switch */
+ }
+}
+
+/*!
+ * @brief API to disable PDRUNCFG bit in the Sysctl0. Note that disabling the bit powers up the peripheral
+ *
+ * @param en peripheral for which to disable the PDRUNCFG bit
+ * @return none
+ */
+void POWER_DisablePD(pd_bit_t en)
+{
+ if (en == kPDRUNCFG_PD_OTP)
+ {
+ PMC->CTRL &= ~PMC_CTRL_OTPSWREN_MASK; /* Disable RBB for OTP switch */
+ }
+
+ /* PDRUNCFGCLR */
+ SYSCTL0_PDRCFGCLR_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU));
+}
+
+/**
+ * @brief API to apply updated PMC PDRUNCFG bits in the Sysctl0.
+ */
+void POWER_ApplyPD(void)
+{
+ PMC->CTRL &= ~PMC_CTRL_CLKDIVEN_MASK; /* Disable internal clock divider to decrease the PMC register access delay.*/
+ /* Cannot set APPLYCFG when ACTIVEFSM is 1 */
+ while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U)
+ {
+ }
+ PMC->CTRL |= PMC_CTRL_APPLYCFG_MASK;
+ /* Wait all PMC finite state machines finished. */
+ while ((PMC->STATUS & PMC_STATUS_ACTIVEFSM_MASK) != 0U)
+ {
+ }
+ PMC->CTRL |= PMC_CTRL_CLKDIVEN_MASK; /* Enable internal clock divider for power saving.*/
+}
+
+/**
+ * @brief Clears the PMC event flags state.
+ * @param statusMask : A bitmask of event flags that are to be cleared.
+ */
+void POWER_ClearEventFlags(uint32_t statusMask)
+{
+ PMC->FLAGS = statusMask;
+}
+
+/**
+ * @brief Get the PMC event flags state.
+ * @return PMC FLAGS register value
+ */
+uint32_t POWER_GetEventFlags(void)
+{
+ return PMC->FLAGS;
+}
+
+/**
+ * @brief Enable the PMC interrupt requests.
+ * @param interruptMask : A bitmask of of interrupts to enable.
+ */
+void POWER_EnableInterrupts(uint32_t interruptMask)
+{
+ PMC->CTRL |= interruptMask;
+}
+
+/**
+ * @brief Disable the PMC interrupt requests.
+ * @param interruptMask : A bitmask of of interrupts to disable.
+ */
+void POWER_DisableInterrupts(uint32_t interruptMask)
+{
+ PMC->CTRL &= ~interruptMask;
+}
+
+/**
+ * @brief Set the PMC analog buffer for references or ATX2.
+ * @param enable : Set true to enable analog buffer for references or ATX2, false to disable.
+ */
+void POWER_SetAnalogBuffer(bool enable)
+{
+ if (enable)
+ {
+ PMC->CTRL |= PMC_CTRL_BUFEN_MASK;
+ }
+ else
+ {
+ PMC->CTRL &= ~PMC_CTRL_BUFEN_MASK;
+ }
+}
+
+/*!
+ * @brief Configure pad voltage level. Wide voltage range cost more power due to enabled voltage detector.
+ *
+ * NOTE: BE CAUTIOUS TO CALL THIS API. IF THE PAD SUPPLY IS BEYOND THE SET RANGE, SILICON MIGHT BE DAMAGED.
+ *
+ * @param config pad voltage range configuration.
+ */
+void POWER_SetPadVolRange(const power_pad_vrange_t *config)
+{
+ PMC->PADVRANGE = (*((const uint32_t *)(const void *)config)) & 0x3FFU;
+}
+
+/**
+ * @brief PMC Enter Rbb mode function call
+ * @return nothing
+ */
+
+AT_QUICKACCESS_SECTION_CODE(void POWER_EnterRbb(void))
+{
+ uint32_t pmsk;
+ bool irqEnabled;
+ uint32_t pmc_ctrl;
+ pmsk = __get_PRIMASK();
+ __disable_irq();
+ POWER_SetBiasConfig();
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ irqEnabled = NVIC_GetEnableIRQ(PMU_PMIC_IRQn) != 0U;
+ /* MAINCLK_SHUTOFF=1, RBB_PD=0, RBBSRAM_PD=0 */
+ SYSCTL0->PDSLEEPCFG0 = (SYSCTL0->PDRUNCFG0 | SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF_MASK) &
+ ~(SYSCTL0_PDSLEEPCFG0_RBB_PD_MASK | SYSCTL0_PDSLEEPCFG0_RBBSRAM_PD_MASK);
+ SYSCTL0->PDSLEEPCFG1 = SYSCTL0->PDRUNCFG1;
+ SYSCTL0->PDSLEEPCFG2 = SYSCTL0->PDRUNCFG2;
+ SYSCTL0->PDSLEEPCFG3 = SYSCTL0->PDRUNCFG3;
+ SYSCTL0->PDWAKECFG = PDWAKECFG_RBBKEEPST_MASK | PDWAKECFG_RBBSRAMKEEPST_MASK;
+ /* Add PMC count delay before auto wakeup (clocked by the PMC 16MHz oscillator) */
+ PMC->AUTOWKUP = 0x800U;
+ /* Disable LVD core reset and enable PMC auto wakeup interrupt */
+ pmc_ctrl = PMC->CTRL;
+ PMC->CTRL = (pmc_ctrl | PMC_CTRL_AUTOWKEN_MASK) & ~(PMC_CTRL_LVDCORERE_MASK | PMC_CTRL_LVDCOREIE_MASK);
+ SYSCTL0->STARTEN1_SET = 1UL << ((uint32_t)PMU_PMIC_IRQn - 32U);
+ if (!irqEnabled)
+ {
+ NVIC_EnableIRQ(PMU_PMIC_IRQn);
+ }
+ __WFI();
+ /* Restore PMC setting, clear interrupt flag */
+ PMC->CTRL = pmc_ctrl;
+ PMC->FLAGS = PMC_FLAGS_AUTOWKF_MASK;
+ SYSCTL0->STARTEN1_CLR = 1UL << ((uint32_t)PMU_PMIC_IRQn - 32U);
+ SYSCTL0->PDWAKECFG = 0U;
+ NVIC_ClearPendingIRQ(PMU_PMIC_IRQn);
+ if (!irqEnabled)
+ {
+ /* Recover NVIC state. */
+ NVIC_DisableIRQ(PMU_PMIC_IRQn);
+ }
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+ __set_PRIMASK(pmsk);
+}
+/**
+ * @brief PMC Enter Fbb mode function call
+ * @return nothing
+ */
+
+AT_QUICKACCESS_SECTION_CODE(void POWER_EnterFbb(void))
+{
+ uint32_t pmsk;
+ bool irqEnabled;
+ uint32_t pmc_ctrl;
+ pmsk = __get_PRIMASK();
+ __disable_irq();
+ POWER_SetBiasConfig();
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ irqEnabled = NVIC_GetEnableIRQ(PMU_PMIC_IRQn) != 0U;
+
+ /* MAINCLK_SHUTOFF=1, FBB_PD=0 */
+ SYSCTL0->PDSLEEPCFG0 =
+ (SYSCTL0->PDRUNCFG0 | SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF_MASK) & ~SYSCTL0_PDSLEEPCFG0_FBB_PD_MASK;
+ SYSCTL0->PDSLEEPCFG1 = SYSCTL0->PDRUNCFG1;
+ SYSCTL0->PDSLEEPCFG2 = SYSCTL0->PDRUNCFG2;
+ SYSCTL0->PDSLEEPCFG3 = SYSCTL0->PDRUNCFG3;
+ SYSCTL0->PDWAKECFG = PDWAKECFG_FBBKEEPST_MASK;
+ /* Add PMC count delay before auto wakeup (clocked by the PMC 16MHz oscillator) */
+ PMC->AUTOWKUP = 0x800;
+ /* Disable LVD core reset and enable PMC auto wakeup interrupt */
+ pmc_ctrl = PMC->CTRL;
+ PMC->CTRL = (pmc_ctrl | PMC_CTRL_AUTOWKEN_MASK) & ~(PMC_CTRL_LVDCORERE_MASK | PMC_CTRL_LVDCOREIE_MASK);
+ SYSCTL0->STARTEN1_SET = 1UL << ((uint32_t)PMU_PMIC_IRQn - 32U);
+ if (!irqEnabled)
+ {
+ NVIC_EnableIRQ(PMU_PMIC_IRQn);
+ }
+ __WFI();
+ /* Restore PMC setting, clear interrupt flag */
+ PMC->CTRL = pmc_ctrl;
+ PMC->FLAGS = PMC_FLAGS_AUTOWKF_MASK;
+ SYSCTL0->STARTEN1_CLR = 1UL << ((uint32_t)PMU_PMIC_IRQn - 32U);
+ SYSCTL0->PDWAKECFG = 0;
+ NVIC_ClearPendingIRQ(PMU_PMIC_IRQn);
+ if (!irqEnabled)
+ {
+ /* Recover NVIC state. */
+ NVIC_DisableIRQ(PMU_PMIC_IRQn);
+ }
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+ __set_PRIMASK(pmsk);
+}
+/**
+ * @brief PMC exit Rbb & Fbb mode function call
+ * @return nothing
+ */
+
+AT_QUICKACCESS_SECTION_CODE(void POWER_EnterNbb(void))
+{
+ uint32_t pmsk;
+ bool irqEnabled;
+ uint32_t pmc_ctrl;
+ pmsk = __get_PRIMASK();
+ __disable_irq();
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ irqEnabled = NVIC_GetEnableIRQ(PMU_PMIC_IRQn) != 0U;
+ /* MAINCLK_SHUTOFF=1, RBB_PD=1 RBBSRAM_PD=1 FBB_PD=1 */
+ SYSCTL0->PDSLEEPCFG0 = SYSCTL0->PDRUNCFG0 | SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF_MASK |
+ SYSCTL0_PDSLEEPCFG0_RBB_PD_MASK | SYSCTL0_PDSLEEPCFG0_RBBSRAM_PD_MASK |
+ SYSCTL0_PDSLEEPCFG0_FBB_PD_MASK;
+ SYSCTL0->PDSLEEPCFG1 = SYSCTL0->PDRUNCFG1;
+ SYSCTL0->PDSLEEPCFG2 = SYSCTL0->PDRUNCFG2;
+ SYSCTL0->PDSLEEPCFG3 = SYSCTL0->PDRUNCFG3;
+ SYSCTL0->PDWAKECFG = PDWAKECFG_RBBKEEPST_MASK | PDWAKECFG_RBBSRAMKEEPST_MASK | PDWAKECFG_FBBKEEPST_MASK;
+ /* Add PMC count delay before auto wakeup (clocked by the PMC 16MHz oscillator) */
+ PMC->AUTOWKUP = 0x800;
+ /* Disable LVD core reset and enable PMC auto wakeup interrupt */
+ pmc_ctrl = PMC->CTRL;
+ PMC->CTRL = (pmc_ctrl | PMC_CTRL_AUTOWKEN_MASK) & ~(PMC_CTRL_LVDCORERE_MASK | PMC_CTRL_LVDCOREIE_MASK);
+ SYSCTL0->STARTEN1_SET = 1UL << ((uint32_t)PMU_PMIC_IRQn - 32U);
+ if (!irqEnabled)
+ {
+ NVIC_EnableIRQ(PMU_PMIC_IRQn);
+ }
+ __WFI();
+ /* Restore PMC setting, clear interrupt flag */
+ PMC->CTRL = pmc_ctrl;
+ PMC->FLAGS = PMC_FLAGS_AUTOWKF_MASK;
+ SYSCTL0->STARTEN1_CLR = 1UL << ((uint32_t)PMU_PMIC_IRQn - 32U);
+ SYSCTL0->PDWAKECFG = 0U;
+ NVIC_ClearPendingIRQ(PMU_PMIC_IRQn);
+ if (!irqEnabled)
+ {
+ /* Recover NVIC state. */
+ NVIC_DisableIRQ(PMU_PMIC_IRQn);
+ }
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+ __set_PRIMASK(pmsk);
+}
+
+/**
+ * @brief PMC set Ldo volatage function call
+ * @return true for success.
+ */
+bool POWER_SetLdoVoltageForFreq(uint32_t cm33_clk_freq, uint32_t dsp_clk_freq)
+{
+ uint32_t pmsk;
+ uint32_t volt;
+ bool ret;
+
+ pmsk = __get_PRIMASK();
+ __disable_irq();
+
+ /* Enter FBB mode first */
+ if (POWER_GetBodyBiasMode(kCfg_Run) != kPmu_Fbb)
+ {
+ POWER_EnterFbb();
+ }
+
+ volt = POWER_CalcVoltLevel(cm33_clk_freq, dsp_clk_freq);
+ ret = volt != POWER_INVALID_VOLT_LEVEL;
+
+ if (ret)
+ {
+ if (volt < 0x13U) /* < 0.8V */
+ {
+ POWER_DisableLVD();
+ }
+ else
+ {
+ if (volt < 0x1DU) /* < 0.9V */
+ {
+ PMC_DECREASE_LVD_LEVEL_IF_HIGHER_THAN(kLvdFallingTripVol_795);
+ }
+ else if (volt < 0x26U) /* < 1.0V */
+ {
+ PMC_DECREASE_LVD_LEVEL_IF_HIGHER_THAN(kLvdFallingTripVol_885);
+ }
+ else
+ {
+ /* Do nothing */
+ }
+ }
+
+ /* Configure vddcore voltage value */
+ PMC->RUNCTRL = volt;
+ POWER_ApplyPD();
+
+ if (volt >= 0x13U) /* >= 0.8V */
+ {
+ POWER_RestoreLVD();
+ }
+
+ ret = true;
+ }
+
+ __set_PRIMASK(pmsk);
+
+ return ret;
+}
+
+void POWER_SetLvdFallingTripVoltage(power_lvd_falling_trip_vol_val_t volt)
+{
+ PMC->LVDCORECTRL = PMC_LVDCORECTRL_LVDCORELVL((uint32_t)volt);
+ POWER_ApplyPD();
+}
+
+power_lvd_falling_trip_vol_val_t POWER_GetLvdFallingTripVoltage(void)
+{
+ uint32_t ret = ((PMC->LVDCORECTRL & PMC_LVDCORECTRL_LVDCORELVL_MASK) >> PMC_LVDCORECTRL_LVDCORELVL_SHIFT);
+ return (power_lvd_falling_trip_vol_val_t)ret;
+}
+
+AT_QUICKACCESS_SECTION_CODE(static void delay(uint32_t count))
+{
+ uint32_t i = 0U;
+ for (i = 0U; i < count; ++i)
+ {
+ __NOP();
+ }
+}
+
+AT_QUICKACCESS_SECTION_CODE(static void deinitXip(void))
+{
+ if (IS_XIP_FLEXSPI0())
+ { /* FlexSPI0 */
+ /* Wait until FLEXSPI is not busy */
+ while (!(((FLEXSPI0->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) != 0U) &&
+ ((FLEXSPI0->STS0 & FLEXSPI_STS0_SEQIDLE_MASK) != 0U)))
+ {
+ }
+ /* Disable module. */
+ FLEXSPI0->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
+ /* Disable clock. */
+ CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_MASK;
+ }
+ else if (IS_XIP_FLEXSPI1())
+ { /* FlexSPI1 */
+ /* Wait until FLEXSPI is not busy */
+ while (!(((FLEXSPI1->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) != 0U) &&
+ ((FLEXSPI1->STS0 & FLEXSPI_STS0_SEQIDLE_MASK) != 0U)))
+ {
+ }
+ /* Disable module. */
+ FLEXSPI1->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
+ /* Disable clock. */
+ CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_MASK;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+}
+
+AT_QUICKACCESS_SECTION_CODE(static void initFlexSPI(FLEXSPI_Type *base))
+{
+ uint32_t status;
+ uint32_t lastStatus;
+ uint32_t retry;
+
+ /* Enable FLEXSPI module */
+ base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+
+ base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
+ while ((base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) != 0U)
+ {
+ }
+
+ /* Need to wait DLL locked if DLL enabled */
+ if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK))
+ {
+ lastStatus = base->STS2;
+ retry = FLEXSPI_DLL_LOCK_RETRY;
+ /* Wait slave delay line locked and slave reference delay line locked. */
+ do
+ {
+ status = base->STS2;
+ if ((status & (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) ==
+ (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK))
+ {
+ /* Locked */
+ retry = 100;
+ break;
+ }
+ else if (status == lastStatus)
+ {
+ /* Same delay cell number in calibration */
+ retry--;
+ }
+ else
+ {
+ retry = FLEXSPI_DLL_LOCK_RETRY;
+ lastStatus = status;
+ }
+ } while (retry > 0U);
+ /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
+ for (; retry > 0U; retry--)
+ {
+ __NOP();
+ }
+ }
+}
+
+AT_QUICKACCESS_SECTION_CODE(static void initXip(void))
+{
+ if (IS_XIP_FLEXSPI0())
+ { /* FlexSPI0 */
+ /* Enable FLEXSPI clock again */
+ CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK;
+ /* Re-enable FLEXSPI module */
+ initFlexSPI(FLEXSPI0);
+ }
+ else if (IS_XIP_FLEXSPI1())
+ { /* FlexSPI1 */
+ /* Enable FLEXSPI clock again */
+ CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK;
+ /* Re-enable FLEXSPI module */
+ initFlexSPI(FLEXSPI1);
+ }
+ else
+ {
+ /* Do nothing */
+ }
+}
+
+AT_QUICKACCESS_SECTION_CODE(static void countPartitionSwitches(uint32_t numPerSwitch,
+ uint32_t *pFastSwitches,
+ uint32_t *pSlowSwitches))
+{
+ const uint32_t slowBitmap =
+ 0x103CCF3CU; /* Bit value 1 stands for containing slow memory, 0 stands for fast memory only. */
+ const uint32_t fastBitmap = (slowBitmap ^ SYSCTL0_PDRUNCFG1_MEM_BITS_MASK) |
+ 0x100014U; /* FlexSPI and LCDIF have both fast and slow memory controller */
+
+ (void)numPerSwitch;
+ /* All partitions are turned on in parallel */
+ *pFastSwitches = 0U;
+
+ if (0U == ((SYSCTL0->PDRUNCFG1 ^ SYSCTL0_PDRUNCFG1_MEM_BITS_MASK) &
+ (SYSCTL0->PDSLEEPCFG1 & SYSCTL0_PDRUNCFG1_MEM_BITS_MASK) & slowBitmap))
+ {
+ *pSlowSwitches = 0U;
+ if (0U != (((SYSCTL0->PDRUNCFG1 ^ SYSCTL0_PDRUNCFG1_MEM_BITS_MASK) &
+ (SYSCTL0->PDSLEEPCFG1 & SYSCTL0_PDRUNCFG1_MEM_BITS_MASK) & fastBitmap) |
+ ((~SYSCTL0->PDRUNCFG2) & SYSCTL0->PDSLEEPCFG2) | ((~SYSCTL0->PDRUNCFG3) & SYSCTL0->PDSLEEPCFG3)))
+ {
+ *pFastSwitches = 1U;
+ }
+ }
+ else
+ {
+ *pSlowSwitches = 1U;
+ }
+}
+
+AT_QUICKACCESS_SECTION_CODE(static uint32_t POWER_CalculateSafetyCount(uint32_t clkMhz))
+{
+ uint32_t ns = 0U;
+ bool flag, step6Flag, step7Flag;
+ uint32_t temp, groups, fastSwitches, slowSwitches;
+
+ ns += 200U; /* PMU clock startup */
+ ns += 2000U / PMU_MIN_CLOCK_MHZ; /* Wakeup sync */
+ ns += 1000U / PMU_MIN_CLOCK_MHZ; /* Senquencer start */
+ /* Bandgap to HP mode */
+ flag = ((SYSCTL0->PDSLEEPCFG0 & 0x10017D0U) == 0x10017D0U);
+ ns += (flag ? 6000UL : 1000UL) / PMU_MIN_CLOCK_MHZ + (flag ? 9000U : 0U);
+
+ step7Flag = (PMC->RUNCTRL != PMC->SLEEPCTRL) && (pmicVddcoreRecoveryTime == 0U);
+ step6Flag = step7Flag || (SYSCTL0->PDRUNCFG2 != SYSCTL0->PDSLEEPCFG2) ||
+ (SYSCTL0->PDRUNCFG3 != SYSCTL0->PDSLEEPCFG3) ||
+ ((SYSCTL0->PDRUNCFG1 & 0x9FFFFFFFU) != (SYSCTL0->PDSLEEPCFG1 & 0x9FFFFFFFU));
+
+ /* Monitors to HP */
+ ns += 1000U / PMU_MIN_CLOCK_MHZ;
+ /* Core Regulator HP */
+ flag = ((SYSCTL0->PDSLEEPCFG0 & 0x10U) == 0x10U) && step6Flag && step7Flag;
+ ns += (flag ? 47000UL : 1000UL) / PMU_MIN_CLOCK_MHZ + (flag ? 1000U : 0U);
+
+ if (pmicVddcoreRecoveryTime == 0U)
+ {
+ /* Application uses internal LDO */
+ flag = (SYSCTL0->PDSLEEPCFG0 & 0x10U) == 0x10U;
+ ns += flag ? 1000U : 0U; /* Monitors to HP */
+
+ /* Core Regulator Voltage adj */
+ if (step6Flag && step7Flag)
+ {
+ temp = (PMC->RUNCTRL & PMC_RUNCTRL_CORELVL_MASK) - (PMC->SLEEPCTRL & PMC_SLEEPCTRL_CORELVL_MASK);
+ ns += (temp * 32000U + 1000U) / PMU_MIN_CLOCK_MHZ + temp * 600U;
+ }
+
+ /* Core Regulator mode */
+ ns += ((SYSCTL0->PDRUNCFG0 & 0x10U) == 0x10U ? 43000UL : 1000UL) / PMU_MIN_CLOCK_MHZ;
+ }
+ else
+ {
+ /* Application uses on-board PMIC */
+ ns += 2000U / PMU_MIN_CLOCK_MHZ;
+ if (pmicVddcoreRecoveryTime != PMIC_VDDCORE_RECOVERY_TIME_IGNORE)
+ {
+ /* Application uses on-board PMIC */
+ ns += (((SYSCTL0->PDSLEEPCFG0 & 0x200U) == 0x200U) ? 39000U : 1300U) +
+ pmicVddcoreRecoveryTime * 1000U; /* PMIC vddcore recovery */
+ }
+ }
+
+ /* Body Bias disable */
+ flag = ((SYSCTL0->PDSLEEPCFG0 & 0x800U) == 0U) && step6Flag;
+ ns += (flag ? 6000U : (((SYSCTL0->PDSLEEPCFG0 & 0x1000U) == 0U) ? 88000U : 1000U)) / PMU_MIN_CLOCK_MHZ +
+ (flag ? 26000U : 0U);
+ /* SRAM RBB disable */
+ flag = ((SYSCTL0->PDSLEEPCFG0 & 0x8000U) == 0U) && step6Flag;
+ ns += ((flag ? 6000UL : 1000UL) / PMU_MIN_CLOCK_MHZ) + (flag ? 26000U : 0U);
+
+ /* SRAM power switches */
+ groups = (47U + PMC_MEM_SEQ_NUM - 1U) / PMC_MEM_SEQ_NUM;
+ countPartitionSwitches(PMC_MEM_SEQ_NUM, &fastSwitches, &slowSwitches);
+ ns += (1000U + 50000U * slowSwitches + 18000U * fastSwitches +
+ (((SYSCTL0->PDSLEEPCFG1 & (1UL << 31U)) != 0U) ? 8000U : 1000U) * (groups - fastSwitches - slowSwitches)) /
+ PMU_MIN_CLOCK_MHZ +
+ 8000U;
+
+ ns += 1000U / PMU_MIN_CLOCK_MHZ; /* Monitor change */
+
+ /* Body Bias change */
+ if (((SYSCTL0->PDRUNCFG0 & 0x800U) == 0U) ||
+ (((SYSCTL0->PDSLEEPCFG0 & 0x800U) == 0U) && ((SYSCTL0->PDWAKECFG & PDWAKECFG_RBBKEEPST_MASK) != 0U)) ||
+ ((SYSCTL0->PDRUNCFG0 & 0x8000U) == 0U) ||
+ (((SYSCTL0->PDSLEEPCFG0 & 0x8000U) == 0U) && ((SYSCTL0->PDWAKECFG & PDWAKECFG_RBBSRAMKEEPST_MASK) != 0U)))
+ {
+ temp = 5000U;
+ ns += 251000U;
+ }
+ else if (((SYSCTL0->PDRUNCFG0 & 0x1000U) == 0U) ||
+ (((SYSCTL0->PDSLEEPCFG0 & 0x1000U) == 0U) && ((SYSCTL0->PDWAKECFG & PDWAKECFG_FBBKEEPST_MASK) != 0U)))
+ {
+ temp = 312000U;
+ }
+ else
+ {
+ temp = 1000U;
+ }
+ ns += temp / PMU_MIN_CLOCK_MHZ;
+
+ /* Bandgap mode */
+ if (((SYSCTL0->PDRUNCFG0 & 0x10017D0U) == 0x10017D0U) &&
+ (((SYSCTL0->PDSLEEPCFG0 & 0x1000U) == 0x1000U) || ((SYSCTL0->PDWAKECFG & PDWAKECFG_FBBKEEPST_MASK) == 0U)))
+ {
+ ns += 7000U / PMU_MIN_CLOCK_MHZ + 50U;
+ }
+ else
+ {
+ ns += 1000U / PMU_MIN_CLOCK_MHZ;
+ }
+
+ return (ns * clkMhz + 999U) / 1000U;
+}
+
+/**
+ * @brief PMC Sleep function call
+ * @return nothing
+ */
+
+void POWER_EnterSleep(void)
+{
+ uint32_t pmsk;
+ pmsk = __get_PRIMASK();
+ __disable_irq();
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+ __WFI();
+ __set_PRIMASK(pmsk);
+}
+
+/**
+ * @brief PMC Deep Sleep function call
+ * @return nothing
+ */
+AT_QUICKACCESS_SECTION_CODE(void POWER_EnterDeepSleep(const uint32_t exclude_from_pd[4]))
+{
+ uint32_t cpu_div;
+ uint32_t frodiv_sel;
+ uint32_t mainclk_sel[2];
+ uint32_t dspclk_sel[2];
+ uint32_t pmsk = __get_PRIMASK();
+ uint32_t pll_need_pd;
+ uint32_t pll_need_rst[2];
+ uint32_t pfd_need_gate[2];
+ bool dsp_state = false;
+ bool dsclk_changed = false;
+ uint32_t fro_oen = 0;
+ uint32_t pmc_ctrl;
+ uint32_t otp_cfg = 0;
+
+ __disable_irq();
+ POWER_SetBiasConfig();
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ frodiv_sel = CLKCTL0->FRODIVSEL;
+ mainclk_sel[0] = CLKCTL0->MAINCLKSELA;
+ mainclk_sel[1] = CLKCTL0->MAINCLKSELB;
+ dspclk_sel[0] = CLKCTL1->DSPCPUCLKSELA;
+ dspclk_sel[1] = CLKCTL1->DSPCPUCLKSELB;
+ cpu_div = CLKCTL0->SYSCPUAHBCLKDIV;
+
+ /* Power on mask bit correspond modules during Deep Sleep mode*/
+ SYSCTL0->PDSLEEPCFG0 = (PCFG0_DEEP_SLEEP & ~exclude_from_pd[0]) |
+ (SYSCTL0->PDRUNCFG0 & ~exclude_from_pd[0] &
+ ~(SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_MASK | SYSCTL0_PDSLEEPCFG0_PMIC_MODE1_MASK));
+ SYSCTL0->PDSLEEPCFG1 = (PCFG1_DEEP_SLEEP & ~exclude_from_pd[1]) | (SYSCTL0->PDRUNCFG1 & ~exclude_from_pd[1]);
+ SYSCTL0->PDSLEEPCFG2 = (PCFG2_DEEP_SLEEP & ~exclude_from_pd[2]) | (SYSCTL0->PDRUNCFG2 & ~exclude_from_pd[2]);
+ SYSCTL0->PDSLEEPCFG3 = (PCFG3_DEEP_SLEEP & ~exclude_from_pd[3]) | (SYSCTL0->PDRUNCFG3 & ~exclude_from_pd[3]);
+
+ /* Configuration PMC to respond changes on pdruncfg[2:1] (PMIC mode select pin values) like below:
+ * 0b00 run mode, all supplies on.
+ * 0b01 deep sleep mode, all supplies on.
+ * 0b10 deep powerdown mode, vddcore off.
+ * 0b11 full deep powerdown mode vdd1v8 and vddcore off. */
+ PMC->PMICCFG = 0x73U;
+ /* Set PMIC mode pin as 0b01 to let PMC turn on vdd1v8 and vddcore*/
+ SYSCTL0->PDSLEEPCFG0 |= SYSCTL0_PDSLEEPCFG0_PMIC_MODE0(1) | SYSCTL0_PDSLEEPCFG0_PMIC_MODE1(0);
+
+ /* Stall DSP if shut off main clock*/
+ if (((SYSCTL0->PDSLEEPCFG0 & SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF_MASK) != 0U) && (SYSCTL0->DSPSTALL == 0U))
+ {
+ SYSCTL0->DSPSTALL = SYSCTL0_DSPSTALL_DSPSTALL_MASK;
+ dsp_state = true;
+ }
+ /* Clear all event flags before enter deep sleep */
+ PMC->FLAGS = PMC->FLAGS;
+
+ PMC->MEMSEQCTRL = PMC_MEMSEQCTRL_MEMSEQNUM(PMC_MEM_SEQ_NUM);
+
+ /* Disable LVD core reset. */
+ pmc_ctrl = PMC->CTRL;
+ PMC->CTRL = pmc_ctrl & ~(PMC_CTRL_LVDCORERE_MASK | PMC_CTRL_LVDCOREIE_MASK);
+
+ /* Judge if need to power down OTP in deep sleep */
+ if ((SYSCTL0->PDSLEEPCFG1 & SYSCTL0_PDSLEEPCFG1_OTP_PD_MASK) != 0U)
+ {
+ otp_cfg = (SYSCTL0->PDRUNCFG1 & SYSCTL0_PDRUNCFG1_OTP_PD_MASK) ^ SYSCTL0_PDRUNCFG1_OTP_PD_MASK;
+ /* If OTP powered on, power down it first */
+ SYSCTL0->PDRUNCFG1_SET = otp_cfg;
+ /* Enable RBB for OTP switch */
+ PMC->CTRL |= PMC_CTRL_OTPSWREN_MASK;
+ }
+
+ if (deepSleepClk == kDeepSleepClk_LpOsc)
+ {
+ /* Make sure LPOSC clock been powered up */
+ if ((SYSCTL0->PDRUNCFG0 & SYSCTL0_PDRUNCFG0_LPOSC_PD_MASK) != 0U)
+ {
+ SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_CLR_LPOSC_PD_MASK;
+ dsclk_changed = true; /* Enabled */
+ while ((CLKCTL0->LPOSCCTL0 & CLKCTL0_LPOSCCTL0_CLKRDY_MASK) == 0U)
+ {
+ }
+ }
+ }
+ else
+ {
+ fro_oen = CLKCTL0->FRODIVOEN;
+ /* Make sure FRO clock been powered up */
+ if ((SYSCTL0->PDRUNCFG0 & SYSCTL0_PDRUNCFG0_FFRO_PD_MASK) != 0U)
+ {
+ SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_CLR_FFRO_PD_MASK;
+ dsclk_changed = true;
+ while ((CLKCTL0->FROCLKSTATUS & CLKCTL0_FROCLKSTATUS_CLK_OK_MASK) == 0U)
+ {
+ }
+ }
+ CLKCTL0->FRODIVOEN = fro_oen | CLKCTL0_FRODIVOEN_FRO_DIV4_O_EN_MASK;
+ }
+
+ /* Calculate PMC delay needed for safe wakeup.
+ User should not touch this register and should rely on the SDK to calculate the delay */
+ if ((deepSleepClk == kDeepSleepClk_LpOsc) && ((SYSCTL0->PDSLEEPCFG0 & SYSCTL0_PDSLEEPCFG0_LPOSC_PD_MASK) == 0U))
+ {
+ /* Main clock source LPOSC remains on in deep sleep */
+ SYSCTL0->MAINCLKSAFETY = POWER_CalculateSafetyCount(1U);
+ }
+ else if ((deepSleepClk == kDeepSleepClk_Fro) && ((SYSCTL0->PDSLEEPCFG0 & SYSCTL0_PDSLEEPCFG0_FFRO_PD_MASK) == 0U))
+ {
+ /* Main clock source FRO remains on in deep sleep */
+ SYSCTL0->MAINCLKSAFETY = POWER_CalculateSafetyCount(CLK_FRO_CLK / 4U / 1000000U);
+ }
+ else
+ {
+ SYSCTL0->MAINCLKSAFETY = 0U;
+ }
+
+ /* Deinit FlexSPI interface in case XIP */
+ deinitXip();
+
+ /* Switch main clock before entering Deep Sleep mode*/
+ CLKCTL0->FRODIVSEL = CLKCTL0_FRODIVSEL_SEL(1);
+ CLKCTL0->MAINCLKSELA = CLKCTL0_MAINCLKSELA_SEL(deepSleepClk);
+ CLKCTL0->MAINCLKSELB = CLKCTL0_MAINCLKSELB_SEL(0);
+ CLKCTL1->DSPCPUCLKSELA = CLKCTL1_DSPCPUCLKSELA_SEL(0);
+ CLKCTL1->DSPCPUCLKSELB = CLKCTL1_DSPCPUCLKSELB_SEL(0);
+ CLKCTL0->SYSCPUAHBCLKDIV = 0U;
+ while ((CLKCTL0->SYSCPUAHBCLKDIV & CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG_MASK) != 0U)
+ {
+ }
+
+ /* PLL power down should not rely on PD_SLEEP_CFG auto loading.*/
+ pll_need_pd = (SYSCTL0->PDRUNCFG0 ^ SYSCTL0->PDSLEEPCFG0) &
+ (SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK |
+ SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK);
+ pll_need_rst[0] =
+ IS_SYSPLL_ON(pll_need_pd) ? 0U : (CLKCTL0_SYSPLL0CTL0_RESET_MASK | CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_MASK);
+ pll_need_rst[1] = IS_AUDPLL_ON(pll_need_pd) ?
+ 0U :
+ (CLKCTL1_AUDIOPLL0CTL0_RESET_MASK | CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK);
+ pfd_need_gate[0] = IS_SYSPLL_ON(pll_need_pd) ? 0U : ((~CLKCTL0->SYSPLL0PFD) & SYSPLL0PFD_PFD_CLKGATE_MASK);
+ pfd_need_gate[1] = IS_AUDPLL_ON(pll_need_pd) ? 0U : ((~CLKCTL1->AUDIOPLL0PFD) & AUDIOPLL0PFD_PFD_CLKGATE_MASK);
+ /* Disable the PFD clock output first. */
+ CLKCTL0->SYSPLL0PFD |= pfd_need_gate[0];
+ CLKCTL1->AUDIOPLL0PFD |= pfd_need_gate[1];
+ /* Set the PLL RESET and HOLDRINGOFF_ENA bits. */
+ CLKCTL0->SYSPLL0CTL0 |= pll_need_rst[0];
+ CLKCTL1->AUDIOPLL0CTL0 |= pll_need_rst[1];
+ /* Power down the PLLs */
+ SYSCTL0->PDRUNCFG0_SET = pll_need_pd;
+
+ /* Enter deep sleep mode */
+ __WFI();
+
+ /* Wait OSC clock stable */
+ if (((SYSCTL0->PDRUNCFG0 ^ SYSCTL0->PDSLEEPCFG0) & SYSCTL0_PDRUNCFG0_SYSXTAL_PD_MASK) != 0U)
+ {
+ delay(US2LOOP(deepSleepClk, oscSettlingTime));
+ }
+
+ /* Restore PLL state*/
+ if (pll_need_pd != 0U)
+ {
+ /* Power up the PLLs */
+ SYSCTL0->PDRUNCFG0_CLR = pll_need_pd;
+ /* Delay (CLKCTL0-> SYSPLL0LOCKTIMEDIV2 / 2) us */
+ delay(
+ US2LOOP(deepSleepClk, (CLKCTL0->SYSPLL0LOCKTIMEDIV2 & CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 2U));
+
+ /* Clear System & Audio PLL reset with hold ring off enable*/
+ CLKCTL0->SYSPLL0CTL0 &= ~(pll_need_rst[0] & CLKCTL0_SYSPLL0CTL0_RESET_MASK);
+ CLKCTL1->AUDIOPLL0CTL0 &= ~(pll_need_rst[1] & CLKCTL1_AUDIOPLL0CTL0_RESET_MASK);
+ /* Delay (CLKCTL0-> SYSPLL0LOCKTIMEDIV2 / 6) us */
+ delay(
+ US2LOOP(deepSleepClk, (CLKCTL0->SYSPLL0LOCKTIMEDIV2 & CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 6U));
+
+ /* Clear System PLL HOLDRINGOFF_ENA*/
+ CLKCTL0->SYSPLL0CTL0 &= ~(pll_need_rst[0] & CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_MASK);
+ /* Clear Audio PLL HOLDRINGOFF_ENA*/
+ CLKCTL1->AUDIOPLL0CTL0 &= ~(pll_need_rst[1] & CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK);
+ /* Make sure PLL's output is stable, delay (CLKCTL0-> SYSPLL0LOCKTIMEDIV2 / 3) us */
+ delay(
+ US2LOOP(deepSleepClk, (CLKCTL0->SYSPLL0LOCKTIMEDIV2 & CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 3U));
+
+ if (pfd_need_gate[0] != 0U)
+ {
+ /* Clear ready status flag and restore PFD output status. */
+ CLKCTL0->SYSPLL0PFD &= ~pfd_need_gate[0];
+ /* Wait for output becomes stable. */
+ while ((CLKCTL0->SYSPLL0PFD & SYSPLL0PFD_PFD_CLKRDY_MASK) != (pfd_need_gate[0] >> 1U))
+ {
+ }
+ }
+
+ if (pfd_need_gate[1] != 0U)
+ {
+ /* Clear ready status flag and restore PFD output status. */
+ CLKCTL1->AUDIOPLL0PFD &= ~pfd_need_gate[1];
+ /* Wait for output becomes stable. */
+ while ((CLKCTL1->AUDIOPLL0PFD & AUDIOPLL0PFD_PFD_CLKRDY_MASK) != (pfd_need_gate[1] >> 1U))
+ {
+ }
+ }
+ }
+
+ /* Restore CPU DIV clock configure*/
+ CLKCTL0->SYSCPUAHBCLKDIV = cpu_div;
+ while ((CLKCTL0->SYSCPUAHBCLKDIV & CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG_MASK) != 0U)
+ {
+ }
+ /* Restore CPU/DSP clock configure*/
+ CLKCTL0->FRODIVSEL = frodiv_sel;
+ CLKCTL0->MAINCLKSELA = mainclk_sel[0] & CLKCTL0_MAINCLKSELA_SEL_MASK;
+ CLKCTL0->MAINCLKSELB = mainclk_sel[1] & CLKCTL0_MAINCLKSELB_SEL_MASK;
+ CLKCTL1->DSPCPUCLKSELA = dspclk_sel[0] & CLKCTL1_DSPCPUCLKSELA_SEL_MASK;
+ CLKCTL1->DSPCPUCLKSELB = dspclk_sel[1] & CLKCTL1_DSPCPUCLKSELB_SEL_MASK;
+
+ /* Restore main clock state*/
+ if (deepSleepClk == kDeepSleepClk_LpOsc)
+ {
+ if (dsclk_changed)
+ {
+ /* LPOSC */
+ SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SET_LPOSC_PD_MASK;
+ }
+ }
+ else
+ {
+ /* FRO */
+ CLKCTL0->FRODIVOEN = fro_oen;
+ if (dsclk_changed)
+ {
+ SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SET_FFRO_PD_MASK;
+ }
+ }
+
+ /* Init FlexSPI in case XIP */
+ initXip();
+
+ /* Restore PMC LVD core reset and OTP switch setting */
+ PMC->CTRL = pmc_ctrl;
+ /* Recover OTP power */
+ SYSCTL0->PDRUNCFG1_CLR = otp_cfg;
+
+ /* Restore DSP stall status */
+ if (dsp_state)
+ {
+ SYSCTL0->DSPSTALL &= ~SYSCTL0_DSPSTALL_DSPSTALL_MASK;
+ }
+
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+ __set_PRIMASK(pmsk);
+}
+
+/**
+ * @brief PMC Deep Sleep Power Down function call
+ * @return nothing
+ */
+
+void POWER_EnterDeepPowerDown(const uint32_t exclude_from_pd[4])
+{
+ uint32_t state;
+
+ state = DisableGlobalIRQ();
+ POWER_EnableDeepSleep();
+
+ /* Set mask bit before enter Deep Power Down mode.*/
+ SYSCTL0->PDSLEEPCFG0 |= (~exclude_from_pd[0] & PCFG0_DEEP_SLEEP);
+ SYSCTL0->PDSLEEPCFG1 |= (~exclude_from_pd[1] & PCFG1_DEEP_SLEEP);
+ SYSCTL0->PDSLEEPCFG2 |= (~exclude_from_pd[2] & PCFG2_DEEP_SLEEP);
+ SYSCTL0->PDSLEEPCFG3 |= (~exclude_from_pd[3] & PCFG3_DEEP_SLEEP);
+
+ /* Set DEEPPD bit in PDSLEEPCFG0*/
+ SYSCTL0->PDSLEEPCFG0 |= SYSCTL0_PDSLEEPCFG0_DEEP_PD_MASK;
+ /* Configuration PMC to respond changes on pdruncfg[2:1] (PMIC mode select pin values) like below:
+ * 0b00 run mode, all supplies on.
+ * 0b01 deep sleep mode, all supplies on.
+ * 0b10 deep powerdown mode, vddcore off.
+ * 0b11 full deep powerdown mode vdd1v8 and vddcore off. */
+ PMC->PMICCFG = 0x73U;
+ /* Set PMIC mode pin as 0b10 to let PMC trun off VDDCORE */
+ POWER_SetPmicMode(0x2U, kCfg_Sleep);
+ /* Clear all event flags before enter deep powerdown */
+ PMC->FLAGS = PMC->FLAGS;
+ /* Enter deep powerdown mode */
+ __WFI();
+
+ /* Note that this code is never reached because we re-boot */
+ EnableGlobalIRQ(state);
+}
+
+/**
+ * @brief PMC Full Deep Sleep Power Down function call
+ * @return nothing
+ */
+
+void POWER_EnterFullDeepPowerDown(const uint32_t exclude_from_pd[4])
+{
+ uint32_t state;
+
+ state = DisableGlobalIRQ();
+ POWER_EnableDeepSleep();
+
+ /* Set mask bit before enter Full Deep Power Down mode.*/
+ SYSCTL0->PDSLEEPCFG0 |= (~exclude_from_pd[0] & PCFG0_DEEP_SLEEP);
+ SYSCTL0->PDSLEEPCFG1 |= (~exclude_from_pd[1] & PCFG1_DEEP_SLEEP);
+ SYSCTL0->PDSLEEPCFG2 |= (~exclude_from_pd[2] & PCFG2_DEEP_SLEEP);
+ SYSCTL0->PDSLEEPCFG3 |= (~exclude_from_pd[3] & PCFG3_DEEP_SLEEP);
+
+ /* Set DEEPPD bit in PDSLEEPCFG0*/
+ SYSCTL0->PDSLEEPCFG0 |= SYSCTL0_PDSLEEPCFG0_DEEP_PD_MASK;
+ /* Configuration PMC to respond changes on pdruncfg[2:1] (PMIC mode select pin values) like below:
+ * 0b00 run mode, all supplies on.
+ * 0b01 deep sleep mode, all supplies on.
+ * 0b10 deep powerdown mode, vddcore off.
+ * 0b11 full deep powerdown mode vdd1v8 and vddcore off. */
+ PMC->PMICCFG = 0x73U;
+ /* Set PMIC mode pin as 0b11 to let PMC trun off VDDCORE and VDD1V8*/
+ POWER_SetPmicMode(0x3U, kCfg_Sleep);
+ /* Clear all event flags before enter full deep powerdown */
+ PMC->FLAGS = PMC->FLAGS;
+ /* Enter full deep powerdown mode */
+ __WFI();
+
+ /* Note that this code is never reached because we re-boot */
+ EnableGlobalIRQ(state);
+}
+
+/* Enter Power mode */
+void POWER_EnterPowerMode(power_mode_cfg_t mode, const uint32_t exclude_from_pd[4])
+{
+ switch (mode)
+ {
+ case kPmu_Sleep:
+ POWER_EnterSleep();
+ break;
+
+ case kPmu_Deep_Sleep:
+ POWER_EnterDeepSleep(exclude_from_pd);
+ break;
+
+ case kPmu_Deep_PowerDown:
+ POWER_EnterDeepPowerDown(exclude_from_pd);
+ break;
+
+ case kPmu_Full_Deep_PowerDown:
+ POWER_EnterFullDeepPowerDown(exclude_from_pd);
+ break;
+
+ default:
+ assert(false);
+ break;
+ }
+}
+
+void POWER_SetPmicMode(uint32_t mode, pmic_mode_reg_t reg)
+{
+ __disable_irq();
+
+ SYSCTL0_TUPLE_REG(reg) =
+ (SYSCTL0_TUPLE_REG(reg) & ~(SYSCTL0_PDRUNCFG0_PMIC_MODE1_MASK | SYSCTL0_PDRUNCFG0_PMIC_MODE0_MASK)) |
+ (mode << SYSCTL0_PDRUNCFG0_PMIC_MODE0_SHIFT);
+
+ __enable_irq();
+}
+
+void POWER_SetDeepSleepClock(power_deep_sleep_clk_t clk)
+{
+ deepSleepClk = clk;
+}
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+ uint32_t intNumber = (uint32_t)interrupt;
+
+ if (intNumber >= 32U)
+ {
+ /* enable interrupt wake up in the STARTEN1 register */
+ SYSCTL0->STARTEN1_SET = 1UL << (intNumber - 32U);
+ }
+ else
+ {
+ /* enable interrupt wake up in the STARTEN0 register */
+ SYSCTL0->STARTEN0_SET = 1UL << intNumber;
+ }
+ /* also enable interrupt at NVIC */
+ (void)EnableIRQ(interrupt);
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+ uint32_t intNumber = (uint32_t)interrupt;
+
+ /* also disable interrupt at NVIC */
+ (void)DisableIRQ(interrupt);
+
+ if (intNumber >= 32U)
+ {
+ /* disable interrupt wake up in the STARTEN1 register */
+ SYSCTL0->STARTEN1_CLR = 1UL << (intNumber - 32U);
+ }
+ else
+ {
+ /* disable interrupt wake up in the STARTEN0 register */
+ SYSCTL0->STARTEN0_CLR = 1UL << intNumber;
+ }
+}
+
+/* Get power lib version */
+uint32_t POWER_GetLibVersion(void)
+{
+ return FSL_POWER_DRIVER_VERSION;
+}
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_power.h b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_power.h
new file mode 100644
index 000000000..9a821779a
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_power.h
@@ -0,0 +1,584 @@
+/*
+ * Copyright 2018-2021, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_POWER_H_
+#define _FSL_POWER_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup power
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief power driver version 2.3.2. */
+#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2UL, 3UL, 2UL))
+/*@}*/
+
+#define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot))
+#define SYSCTL0_PDRCFGSET_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_SET)) + ((x) << 2U))))
+#define SYSCTL0_PDRCFGCLR_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_CLR)) + ((x) << 2U))))
+#define PDRCFG0 0x0U
+#define PDRCFG1 0x1U
+#define PDRCFG2 0x2U
+#define PDRCFG3 0x3U
+
+/* PMC FLAGS register bitfield MASK. */
+#define PMC_FLAGS_PORCOREF_MASK (0x10000U)
+#define PMC_FLAGS_POR1V8F_MASK (0x20000U)
+#define PMC_FLAGS_PORAO18F_MASK (0x40000U)
+#define PMC_FLAGS_LVDCOREF_MASK (0x100000U)
+#define PMC_FLAGS_HVDCOREF_MASK (0x400000U)
+#define PMC_FLAGS_HVD1V8F_MASK (0x1000000U)
+#define PMC_FLAGS_RTCF_MASK (0x8000000U)
+#define PMC_FLAGS_AUTOWKF_MASK (0x10000000U)
+#define PMC_FLAGS_INTNPADF_MASK (0x20000000U)
+#define PMC_FLAGS_RESETNPADF_MASK (0x40000000U)
+#define PMC_FLAGS_DEEPPDF_MASK (0x80000000U)
+
+#define PMC_CTRL_LVDCOREIE_MASK (0x100000U)
+#define PMC_CTRL_HVDCOREIE_MASK (0x400000U)
+#define PMC_CTRL_HVD1V8IE_MASK (0x1000000U)
+#define PMC_CTRL_AUTOWKEN_MASK (0x10000000U)
+#define PMC_CTRL_INTRPADEN_MASK (0x20000000U)
+
+/*! PMIC is used but vddcore supply is always above LVD threshold. */
+#define PMIC_VDDCORE_RECOVERY_TIME_IGNORE (0xFFFFFFFFU)
+
+/**
+ * @brief PMC event flags.
+ *
+ * @note These enums are meant to be OR'd together to form a bit mask.
+ */
+enum _pmc_interrupt
+{
+ kPMC_INT_LVDCORE = PMC_CTRL_LVDCOREIE_MASK, /*!< Vddcore Low-Voltage Detector Interrupt Enable. */
+ kPMC_INT_HVDCORE = PMC_CTRL_HVDCOREIE_MASK, /*!< Vddcore High-Voltage Detector Interrupt Enable. */
+ kPMC_INT_HVD1V8 = PMC_CTRL_HVD1V8IE_MASK, /*!< Vdd1v8 High-Voltage Detector Interrupt Enable. */
+ kPMC_INT_AUTOWK = PMC_CTRL_AUTOWKEN_MASK, /*!< PMC automatic wakeup enable and interrupt enable. */
+ kPMC_INT_INTRPAD =
+ PMC_CTRL_INTRPADEN_MASK /*!< Interrupt pad deep powerdown and deep sleep wake up & interrupt enable. */
+};
+
+/**
+ * @brief PMC event flags.
+ *
+ * @note These enums are meant to be OR'd together to form a bit mask.
+ */
+enum _pmc_event_flags
+{
+ kPMC_FLAGS_PORCORE = PMC_FLAGS_PORCOREF_MASK, /*!< POR triggered by the vddcore POR monitor (0 = no, 1 = yes). */
+ kPMC_FLAGS_POR1V8 =
+ PMC_FLAGS_POR1V8F_MASK, /*!< vdd1v8 power on event detected since last cleared(0 = no, 1 = yes). */
+ kPMC_FLAGS_PORAO18 =
+ PMC_FLAGS_PORAO18F_MASK, /*!< vdd_ao18 power on event detected since last cleared (0 = no, 1 = yes). */
+ kPMC_FLAGS_LVDCORE =
+ PMC_FLAGS_LVDCOREF_MASK, /*!< LVD tripped since last time this bit was cleared (0 = no, 1 = yes). */
+ kPMC_FLAGS_HVDCORE =
+ PMC_FLAGS_HVDCOREF_MASK, /*!< HVD tripped since last time this bit was cleared (0 = no, 1 = yes). */
+ kPMC_FLAGS_HVD1V8 =
+ PMC_FLAGS_HVD1V8F_MASK, /*!< vdd1v8 HVD tripped since last time this bit was cleared (0 = no, 1 = yes). */
+ kPMC_FLAGS_RTC =
+ PMC_FLAGS_RTCF_MASK, /*!< RTC wakeup detected since last time flag was cleared (0 = no, 1 = yes). */
+ kPMC_FLAGS_AUTOWK =
+ PMC_FLAGS_AUTOWKF_MASK, /*!< PMC Auto wakeup caused a deep sleep wakeup and interrupt (0 = no, 1 = yes). */
+ kPMC_FLAGS_INTNPADF = PMC_FLAGS_INTNPADF_MASK, /*!< Pad interrupt caused a wakeup or interrupt event since the last
+ time this flag was cleared (0 = no, 1 = yes). */
+ kPMC_FLAGS_RESETNPAD = PMC_FLAGS_RESETNPADF_MASK, /*!< Reset pad wakeup caused a wakeup or reset event since the
+ last time this bit was cleared. (0 = no, 1 = yes). */
+ kPMC_FLAGS_DEEPPD = PMC_FLAGS_DEEPPDF_MASK /*!< Deep powerdown was entered since the last time this flag was cleared
+ (0 = no, 1 = yes). */
+};
+
+typedef enum pd_bits
+{
+ kPDRUNCFG_PMC_MODE0 = MAKE_PD_BITS(PDRCFG0, 1U),
+ kPDRUNCFG_PMC_MODE1 = MAKE_PD_BITS(PDRCFG0, 2U),
+ kPDRUNCFG_LP_VDD_COREREG = MAKE_PD_BITS(PDRCFG0, 4U),
+ kPDRUNCFG_LP_PMCREF = MAKE_PD_BITS(PDRCFG0, 6U),
+ kPDRUNCFG_PD_HVD1V8 = MAKE_PD_BITS(PDRCFG0, 7U),
+ kPDRUNCFG_LP_LVDCORE = MAKE_PD_BITS(PDRCFG0, 9U),
+ kPDRUNCFG_PD_HVDCORE = MAKE_PD_BITS(PDRCFG0, 10U),
+ kPDRUNCFG_PD_RBB = MAKE_PD_BITS(PDRCFG0, 11U),
+ kPDRUNCFG_PD_FBB = MAKE_PD_BITS(PDRCFG0, 12U),
+ kPDRUNCFG_PD_SYSXTAL = MAKE_PD_BITS(PDRCFG0, 13U),
+ kPDRUNCFG_PD_LPOSC = MAKE_PD_BITS(PDRCFG0, 14U),
+ kPDRUNCFG_PD_RBBSRAM = MAKE_PD_BITS(PDRCFG0, 15U),
+ kPDRUNCFG_PD_FFRO = MAKE_PD_BITS(PDRCFG0, 16U),
+ kPDRUNCFG_PD_SYSPLL_LDO = MAKE_PD_BITS(PDRCFG0, 17U),
+ kPDRUNCFG_PD_SYSPLL_ANA = MAKE_PD_BITS(PDRCFG0, 18U),
+ kPDRUNCFG_PD_AUDPLL_LDO = MAKE_PD_BITS(PDRCFG0, 19U),
+ kPDRUNCFG_PD_AUDPLL_ANA = MAKE_PD_BITS(PDRCFG0, 20U),
+ kPDRUNCFG_PD_ADC = MAKE_PD_BITS(PDRCFG0, 21U),
+ kPDRUNCFG_LP_ADC = MAKE_PD_BITS(PDRCFG0, 22U),
+ kPDRUNCFG_PD_ADC_TEMPSNS = MAKE_PD_BITS(PDRCFG0, 23U),
+ kPDRUNCFG_PD_PMC_TEMPSNS = MAKE_PD_BITS(PDRCFG0, 24U),
+ kPDRUNCFG_PD_ACMP = MAKE_PD_BITS(PDRCFG0, 25U),
+ kPDRUNCFG_LP_HSPAD_FSPI0_VDET = MAKE_PD_BITS(PDRCFG0, 26U),
+ kPDRUNCFG_PD_HSPAD_FSPI0_REF = MAKE_PD_BITS(PDRCFG0, 27U),
+ kPDRUNCFG_LP_HSPAD_SDIO0_VDET = MAKE_PD_BITS(PDRCFG0, 28U),
+ kPDRUNCFG_PD_HSPAD_SDIO0_REF = MAKE_PD_BITS(PDRCFG0, 29U),
+ kPDRUNCFG_LP_HSPAD_FSPI1_VDET = MAKE_PD_BITS(PDRCFG0, 30U),
+ kPDRUNCFG_PD_HSPAD_FSPI1_REF = MAKE_PD_BITS(PDRCFG0, 31U),
+
+ kPDRUNCFG_PPD_PQ_SRAM = MAKE_PD_BITS(PDRCFG1, 1U),
+ kPDRUNCFG_APD_FLEXSPI0_SRAM = MAKE_PD_BITS(PDRCFG1, 2U),
+ kPDRUNCFG_PPD_FLEXSPI0_SRAM = MAKE_PD_BITS(PDRCFG1, 3U),
+ kPDRUNCFG_APD_FLEXSPI1_SRAM = MAKE_PD_BITS(PDRCFG1, 4U),
+ kPDRUNCFG_PPD_FLEXSPI1_SRAM = MAKE_PD_BITS(PDRCFG1, 5U),
+ kPDRUNCFG_APD_USBHS_SRAM = MAKE_PD_BITS(PDRCFG1, 6U),
+ kPDRUNCFG_PPD_USBHS_SRAM = MAKE_PD_BITS(PDRCFG1, 7U),
+ kPDRUNCFG_APD_USDHC0_SRAM = MAKE_PD_BITS(PDRCFG1, 8U),
+ kPDRUNCFG_PPD_USDHC0_SRAM = MAKE_PD_BITS(PDRCFG1, 9U),
+ kPDRUNCFG_APD_USDHC1_SRAM = MAKE_PD_BITS(PDRCFG1, 10U),
+ kPDRUNCFG_PPD_USDHC1_SRAM = MAKE_PD_BITS(PDRCFG1, 11U),
+ kPDRUNCFG_PPD_CASPER_SRAM = MAKE_PD_BITS(PDRCFG1, 13U),
+ kPDRUNCFG_APD_GPU_SRAM = MAKE_PD_BITS(PDRCFG1, 14U),
+ kPDRUNCFG_PPD_GPU_SRAM = MAKE_PD_BITS(PDRCFG1, 15U),
+ kPDRUNCFG_APD_SMARTDMA_SRAM = MAKE_PD_BITS(PDRCFG1, 16U),
+ kPDRUNCFG_PPD_SMARTDMA_SRAM = MAKE_PD_BITS(PDRCFG1, 17U),
+ kPDRUNCFG_APD_MIPIDSI_SRAM = MAKE_PD_BITS(PDRCFG1, 18U),
+ kPDRUNCFG_PPD_MIPIDSI_SRAM = MAKE_PD_BITS(PDRCFG1, 19U),
+ kPDRUNCFG_APD_DCNANO_SRAM = MAKE_PD_BITS(PDRCFG1, 20U),
+ kPDRUNCFG_PPD_DCNANO_SRAM = MAKE_PD_BITS(PDRCFG1, 21U),
+ kPDRUNCFG_PD_DSP = MAKE_PD_BITS(PDRCFG1, 25U),
+ kPDRUNCFG_PD_MIPIDSI = MAKE_PD_BITS(PDRCFG1, 26U),
+ kPDRUNCFG_PD_OTP = MAKE_PD_BITS(PDRCFG1, 27U),
+ kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG1, 28U),
+ kPDRUNCFG_LP_HSPAD_SDIO1_VDET = MAKE_PD_BITS(PDRCFG1, 29U),
+ kPDRUNCFG_PD_HSPAD_SDIO1_REF = MAKE_PD_BITS(PDRCFG1, 30U),
+ kPDRUNCFG_SRAM_SLEEP = MAKE_PD_BITS(PDRCFG1, 31U),
+
+ kPDRUNCFG_APD_SRAM_IF0 = MAKE_PD_BITS(PDRCFG2, 0U),
+ kPDRUNCFG_APD_SRAM_IF1 = MAKE_PD_BITS(PDRCFG2, 1U),
+ kPDRUNCFG_APD_SRAM_IF2 = MAKE_PD_BITS(PDRCFG2, 2U),
+ kPDRUNCFG_APD_SRAM_IF3 = MAKE_PD_BITS(PDRCFG2, 3U),
+ kPDRUNCFG_APD_SRAM_IF4 = MAKE_PD_BITS(PDRCFG2, 4U),
+ kPDRUNCFG_APD_SRAM_IF5 = MAKE_PD_BITS(PDRCFG2, 5U),
+ kPDRUNCFG_APD_SRAM_IF6 = MAKE_PD_BITS(PDRCFG2, 6U),
+ kPDRUNCFG_APD_SRAM_IF7 = MAKE_PD_BITS(PDRCFG2, 7U),
+ kPDRUNCFG_APD_SRAM_IF8 = MAKE_PD_BITS(PDRCFG2, 8U),
+ kPDRUNCFG_APD_SRAM_IF9 = MAKE_PD_BITS(PDRCFG2, 9U),
+ kPDRUNCFG_APD_SRAM_IF10 = MAKE_PD_BITS(PDRCFG2, 10U),
+ kPDRUNCFG_APD_SRAM_IF11 = MAKE_PD_BITS(PDRCFG2, 11U),
+ kPDRUNCFG_APD_SRAM_IF12 = MAKE_PD_BITS(PDRCFG2, 12U),
+ kPDRUNCFG_APD_SRAM_IF13 = MAKE_PD_BITS(PDRCFG2, 13U),
+ kPDRUNCFG_APD_SRAM_IF14 = MAKE_PD_BITS(PDRCFG2, 14U),
+ kPDRUNCFG_APD_SRAM_IF15 = MAKE_PD_BITS(PDRCFG2, 15U),
+ kPDRUNCFG_APD_SRAM_IF16 = MAKE_PD_BITS(PDRCFG2, 16U),
+ kPDRUNCFG_APD_SRAM_IF17 = MAKE_PD_BITS(PDRCFG2, 17U),
+ kPDRUNCFG_APD_SRAM_IF18 = MAKE_PD_BITS(PDRCFG2, 18U),
+ kPDRUNCFG_APD_SRAM_IF19 = MAKE_PD_BITS(PDRCFG2, 19U),
+ kPDRUNCFG_APD_SRAM_IF20 = MAKE_PD_BITS(PDRCFG2, 20U),
+ kPDRUNCFG_APD_SRAM_IF21 = MAKE_PD_BITS(PDRCFG2, 21U),
+ kPDRUNCFG_APD_SRAM_IF22 = MAKE_PD_BITS(PDRCFG2, 22U),
+ kPDRUNCFG_APD_SRAM_IF23 = MAKE_PD_BITS(PDRCFG2, 23U),
+ kPDRUNCFG_APD_SRAM_IF24 = MAKE_PD_BITS(PDRCFG2, 24U),
+ kPDRUNCFG_APD_SRAM_IF25 = MAKE_PD_BITS(PDRCFG2, 25U),
+ kPDRUNCFG_APD_SRAM_IF26 = MAKE_PD_BITS(PDRCFG2, 26U),
+ kPDRUNCFG_APD_SRAM_IF27 = MAKE_PD_BITS(PDRCFG2, 27U),
+ kPDRUNCFG_APD_SRAM_IF28 = MAKE_PD_BITS(PDRCFG2, 28U),
+ kPDRUNCFG_APD_SRAM_IF29 = MAKE_PD_BITS(PDRCFG2, 29U),
+ kPDRUNCFG_APD_SRAM_IF30 = MAKE_PD_BITS(PDRCFG2, 30U),
+ kPDRUNCFG_APD_SRAM_IF31 = MAKE_PD_BITS(PDRCFG2, 31U),
+
+ kPDRUNCFG_PPD_SRAM_IF0 = MAKE_PD_BITS(PDRCFG3, 0U),
+ kPDRUNCFG_PPD_SRAM_IF1 = MAKE_PD_BITS(PDRCFG3, 1U),
+ kPDRUNCFG_PPD_SRAM_IF2 = MAKE_PD_BITS(PDRCFG3, 2U),
+ kPDRUNCFG_PPD_SRAM_IF3 = MAKE_PD_BITS(PDRCFG3, 3U),
+ kPDRUNCFG_PPD_SRAM_IF4 = MAKE_PD_BITS(PDRCFG3, 4U),
+ kPDRUNCFG_PPD_SRAM_IF5 = MAKE_PD_BITS(PDRCFG3, 5U),
+ kPDRUNCFG_PPD_SRAM_IF6 = MAKE_PD_BITS(PDRCFG3, 6U),
+ kPDRUNCFG_PPD_SRAM_IF7 = MAKE_PD_BITS(PDRCFG3, 7U),
+ kPDRUNCFG_PPD_SRAM_IF8 = MAKE_PD_BITS(PDRCFG3, 8U),
+ kPDRUNCFG_PPD_SRAM_IF9 = MAKE_PD_BITS(PDRCFG3, 9U),
+ kPDRUNCFG_PPD_SRAM_IF10 = MAKE_PD_BITS(PDRCFG3, 10U),
+ kPDRUNCFG_PPD_SRAM_IF11 = MAKE_PD_BITS(PDRCFG3, 11U),
+ kPDRUNCFG_PPD_SRAM_IF12 = MAKE_PD_BITS(PDRCFG3, 12U),
+ kPDRUNCFG_PPD_SRAM_IF13 = MAKE_PD_BITS(PDRCFG3, 13U),
+ kPDRUNCFG_PPD_SRAM_IF14 = MAKE_PD_BITS(PDRCFG3, 14U),
+ kPDRUNCFG_PPD_SRAM_IF15 = MAKE_PD_BITS(PDRCFG3, 15U),
+ kPDRUNCFG_PPD_SRAM_IF16 = MAKE_PD_BITS(PDRCFG3, 16U),
+ kPDRUNCFG_PPD_SRAM_IF17 = MAKE_PD_BITS(PDRCFG3, 17U),
+ kPDRUNCFG_PPD_SRAM_IF18 = MAKE_PD_BITS(PDRCFG3, 18U),
+ kPDRUNCFG_PPD_SRAM_IF19 = MAKE_PD_BITS(PDRCFG3, 19U),
+ kPDRUNCFG_PPD_SRAM_IF20 = MAKE_PD_BITS(PDRCFG3, 20U),
+ kPDRUNCFG_PPD_SRAM_IF21 = MAKE_PD_BITS(PDRCFG3, 21U),
+ kPDRUNCFG_PPD_SRAM_IF22 = MAKE_PD_BITS(PDRCFG3, 22U),
+ kPDRUNCFG_PPD_SRAM_IF23 = MAKE_PD_BITS(PDRCFG3, 23U),
+ kPDRUNCFG_PPD_SRAM_IF24 = MAKE_PD_BITS(PDRCFG3, 24U),
+ kPDRUNCFG_PPD_SRAM_IF25 = MAKE_PD_BITS(PDRCFG3, 25U),
+ kPDRUNCFG_PPD_SRAM_IF26 = MAKE_PD_BITS(PDRCFG3, 26U),
+ kPDRUNCFG_PPD_SRAM_IF27 = MAKE_PD_BITS(PDRCFG3, 27U),
+ kPDRUNCFG_PPD_SRAM_IF28 = MAKE_PD_BITS(PDRCFG3, 28U),
+ kPDRUNCFG_PPD_SRAM_IF29 = MAKE_PD_BITS(PDRCFG3, 29U),
+ kPDRUNCFG_PPD_SRAM_IF30 = MAKE_PD_BITS(PDRCFG3, 30U),
+ kPDRUNCFG_PPD_SRAM_IF31 = MAKE_PD_BITS(PDRCFG3, 31U),
+ /*
+ This enum member has no practical meaning,it is used to avoid MISRA issue,
+ user should not trying to use it.
+ */
+ kPDRUNCFG_ForceUnsigned = (int)0x80000000U,
+} pd_bit_t;
+
+/*! @brief Power mode configuration API parameter */
+typedef enum _power_mode_config
+{
+ kPmu_Sleep = 0U,
+ kPmu_Deep_Sleep = 1U,
+ kPmu_Deep_PowerDown = 2U,
+ kPmu_Full_Deep_PowerDown = 3U,
+} power_mode_cfg_t;
+
+/*! @brief Body Bias mode definition */
+typedef enum _body_bias_mode
+{
+ kPmu_Fbb = 0x01U, /* Forward Body Bias Mode. */
+ kPmu_Rbb = 0x02U, /* Reverse Body Bias Mode. */
+ kPmu_Nbb = 0x03U, /* Normal Body Bias Mode. */
+} body_bias_mode_t;
+
+/*! @brief PMIC mode pin configuration API parameter */
+#define SYSCTL0_TUPLE_REG(reg) (*((volatile uint32_t *)(((uint32_t)(SYSCTL0)) + (((uint32_t)(reg)) & 0xFFFU))))
+typedef enum _pmic_mode_reg
+{
+ kCfg_Run = 0x610,
+ kCfg_Sleep = 0x600,
+} pmic_mode_reg_t;
+
+/*! @brief Clock source of main clock before entering deep sleep. */
+typedef enum _power_deep_sleep_clk
+{
+ kDeepSleepClk_LpOsc = 0U,
+ kDeepSleepClk_Fro = 1U,
+} power_deep_sleep_clk_t;
+
+/*!
+ * @brief pad voltage range value. Note, refer to Reference Manual PMC GPIO VDDIO Range Selection Control (PADVRANGE)
+ * register's description for the supported voltage by different VDDDIO.
+ */
+typedef enum _power_pad_vrange_val
+{
+ kPadVol_171_360 = 0U, /*!< Deprecated! Voltage from 1.71V to 3.60V. */
+ kPadVol_Continuous = 0U, /*!< Continuous mode, VDDE detector on. */
+ kPadVol_171_198 = 1U, /*!< Voltage from 1.71V to 1.98V. VDDE detector off. */
+ kPadVol_300_360 = 2U, /*!< Voltage from 3.00V to 3.60V. VDDE detector off. */
+} power_pad_vrange_val_t;
+
+/*!
+ * @brief pad voltage range configuration.
+ */
+typedef struct _power_pad_vrange
+{
+ uint32_t Vdde0Range : 2; /*!< VDDE0 voltage range for VDDIO_0. @ref power_pad_vrange_val_t */
+ uint32_t Vdde1Range : 2; /*!< VDDE1 voltage range for VDDIO_1. @ref power_pad_vrange_val_t */
+ uint32_t Vdde2Range : 2; /*!< VDDE2 voltage range for VDDIO_2. @ref power_pad_vrange_val_t */
+ uint32_t Vdde3Range : 2; /*!< VDDE3 voltage range for VDDIO_3. @ref power_pad_vrange_val_t */
+ uint32_t Vdde4Range : 2; /*!< VDDE4 voltage range for VDDIO_4. @ref power_pad_vrange_val_t */
+ uint32_t : 22; /*!< Reserved. */
+} power_pad_vrange_t;
+
+/*!
+ * @brief LVD falling trip voltage value.
+ */
+typedef enum _power_lvd_falling_trip_vol_val
+{
+ kLvdFallingTripVol_720 = 0U, /*!< Voltage 720mV. */
+ kLvdFallingTripVol_735 = 1U, /*!< Voltage 735mV. */
+ kLvdFallingTripVol_750 = 2U, /*!< Voltage 750mV. */
+ kLvdFallingTripVol_765 = 3U, /*!< Voltage 765mV. */
+ kLvdFallingTripVol_780 = 4U, /*!< Voltage 780mV. */
+ kLvdFallingTripVol_795 = 5U, /*!< Voltage 795mV. */
+ kLvdFallingTripVol_810 = 6U, /*!< Voltage 810mV. */
+ kLvdFallingTripVol_825 = 7U, /*!< Voltage 825mV. */
+ kLvdFallingTripVol_840 = 8U, /*!< Voltage 840mV. */
+ kLvdFallingTripVol_855 = 9U, /*!< Voltage 855mV. */
+ kLvdFallingTripVol_870 = 10U, /*!< Voltage 870mV. */
+ kLvdFallingTripVol_885 = 11U, /*!< Voltage 885mV. */
+ kLvdFallingTripVol_900 = 12U, /*!< Voltage 900mV. */
+ kLvdFallingTripVol_915 = 13U, /*!< Voltage 915mV. */
+ kLvdFallingTripVol_930 = 14U, /*!< Voltage 930mV. */
+ kLvdFallingTripVol_945 = 15U, /*!< Voltage 945mV. */
+} power_lvd_falling_trip_vol_val_t;
+
+/*! Invalid voltage level. */
+#define POWER_INVALID_VOLT_LEVEL (0xFFFFFFFFU)
+
+/*! Core frequency levels number. */
+#define POWER_FREQ_LEVELS_NUM (5U)
+/*! Frequency levels defined in power library. */
+extern const uint32_t powerFreqLevel[POWER_FREQ_LEVELS_NUM];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @brief API to enable PDRUNCFG bit in the Sysctl0. Note that enabling the bit powers down the peripheral
+ *
+ * @param en peripheral for which to enable the PDRUNCFG bit
+ */
+void POWER_EnablePD(pd_bit_t en);
+
+/*!
+ * @brief API to disable PDRUNCFG bit in the Sysctl0. Note that disabling the bit powers up the peripheral
+ *
+ * @param en peripheral for which to disable the PDRUNCFG bit
+ */
+void POWER_DisablePD(pd_bit_t en);
+
+/*!
+ * @brief API to enable deep sleep bit in the ARM Core.
+ */
+static inline void POWER_EnableDeepSleep(void)
+{
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+}
+
+/*!
+ * @brief API to disable deep sleep bit in the ARM Core.
+ */
+static inline void POWER_DisableDeepSleep(void)
+{
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+}
+
+/**
+ * @brief API to update XTAL oscillator settling time .
+ * @param osc_delay : OSC stabilization time in unit of microsecond
+ */
+void POWER_UpdateOscSettlingTime(uint32_t osc_delay);
+
+/**
+ * @brief API to update on-board PMIC vddcore recovery time.
+ *
+ * NOTE: If LDO is used instead of PMIC, don't call it. Otherwise it must be called to allow power library to well
+ * handle the deep sleep process.
+ *
+ * @param pmic_delay : PMIC stabilization time in unit of microsecond, or PMIC_VDDCORE_RECOVERY_TIME_IGNORE if not
+ * care.
+ */
+void POWER_UpdatePmicRecoveryTime(uint32_t pmic_delay);
+
+/*!
+ * @brief API to apply updated PMC PDRUNCFG bits in the Sysctl0.
+ */
+void POWER_ApplyPD(void);
+
+/**
+ * @brief Clears the PMC event flags state.
+ * @param statusMask : A bitmask of event flags that are to be cleared.
+ */
+void POWER_ClearEventFlags(uint32_t statusMask);
+
+/**
+ * @brief Get the PMC event flags state.
+ * @return PMC FLAGS register value
+ */
+uint32_t POWER_GetEventFlags(void);
+
+/**
+ * @brief Enable the PMC interrupt requests.
+ * @param interruptMask : A bitmask of of interrupts to enable.
+ */
+void POWER_EnableInterrupts(uint32_t interruptMask);
+
+/**
+ * @brief Disable the PMC interrupt requests.
+ * @param interruptMask : A bitmask of of interrupts to disable.
+ */
+void POWER_DisableInterrupts(uint32_t interruptMask);
+
+/**
+ * @brief Set the PMC analog buffer for references or ATX2.
+ * @param enable : Set to true to enable analog buffer for references or ATX2, false to disable.
+ */
+void POWER_SetAnalogBuffer(bool enable);
+
+/**
+ * @brief Get PMIC_MODE pins configure value.
+ * @param reg : PDSLEEPCFG0 or PDRUNCFG0 register offset
+ * @return PMIC_MODE pins value in PDSLEEPCFG0
+ */
+static inline uint32_t POWER_GetPmicMode(pmic_mode_reg_t reg)
+{
+ uint32_t mode = (uint32_t)reg;
+
+ return ((SYSCTL0_TUPLE_REG(mode) & (SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_MASK | SYSCTL0_PDSLEEPCFG0_PMIC_MODE1_MASK)) >>
+ SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_SHIFT);
+}
+
+/**
+ * @brief Get RBB/FBB bit value.
+ * @param reg : PDSLEEPCFG0 or PDRUNCFG0 register offset
+ * @return Current body bias mode
+ */
+static inline body_bias_mode_t POWER_GetBodyBiasMode(pmic_mode_reg_t reg)
+{
+ uint32_t mode = (uint32_t)reg;
+ uint32_t bbMode = (SYSCTL0_TUPLE_REG(mode) & (SYSCTL0_PDRUNCFG0_RBB_PD_MASK | SYSCTL0_PDRUNCFG0_FBB_PD_MASK)) >>
+ SYSCTL0_PDRUNCFG0_RBB_PD_SHIFT;
+
+ return (body_bias_mode_t)bbMode;
+}
+
+/*!
+ * @brief Configure pad voltage level. Wide voltage range cost more power due to enabled voltage detector.
+ *
+ * NOTE: BE CAUTIOUS TO CALL THIS API. IF THE PAD SUPPLY IS BEYOND THE SET RANGE, SILICON MIGHT BE DAMAGED.
+ *
+ * @param config pad voltage range configuration.
+ */
+void POWER_SetPadVolRange(const power_pad_vrange_t *config);
+
+/**
+ * @brief PMC Enter Rbb mode function call
+ */
+void POWER_EnterRbb(void);
+
+/**
+ * @brief PMC Enter Fbb mode function call
+ */
+void POWER_EnterFbb(void);
+
+/**
+ * @brief PMC exit Rbb & Fbb mode function call
+ */
+void POWER_EnterNbb(void);
+
+/**
+ * @brief PMC Set Ldo volatage for particular frequency.
+ * NOTE: If LVD falling trip voltage is higher than the required core voltage for particular frequency,
+ * LVD voltage will be decreased to safe level to avoid unexpected LVD reset or interrupt event.
+ * @param cm33_clk_freq : CM33 core frequency value
+ * @param dsp_clk_freq : dsp core frequency value
+ * @return true for success and false for CPU frequency out of specified voltOpRange.
+ */
+bool POWER_SetLdoVoltageForFreq(uint32_t cm33_clk_freq, uint32_t dsp_clk_freq);
+
+/*!
+ * @brief Set vddcore low voltage detection falling trip voltage.
+ * @param volt target LVD voltage to set.
+ */
+void POWER_SetLvdFallingTripVoltage(power_lvd_falling_trip_vol_val_t volt);
+
+/**
+ * @brief Get current vddcore low voltage detection falling trip voltage.
+ * @return Current LVD voltage.
+ */
+power_lvd_falling_trip_vol_val_t POWER_GetLvdFallingTripVoltage(void);
+
+/**
+ * @brief Disable low voltage detection, no reset or interrupt is triggered when vddcore voltage drops below
+ * threshold.
+ * NOTE: This API is for internal use only. Application should not touch it.
+ */
+void POWER_DisableLVD(void);
+
+/**
+ * @brief Restore low voltage detection setting.
+ * NOTE: This API is for internal use only. Application should not touch it.
+ */
+void POWER_RestoreLVD(void);
+
+/**
+ * @brief Set PMIC_MODE pins configure value.
+ * @param mode : PMIC MODE pin value
+ * @param reg : PDSLEEPCFG0 or PDRUNCFG0 register offset
+ * @return PMIC_MODE pins value in PDSLEEPCFG0
+ */
+void POWER_SetPmicMode(uint32_t mode, pmic_mode_reg_t reg);
+
+/**
+ * @brief Set deep sleep clock source of main clock.
+ * @param clk : clock source of main clock.
+ */
+void POWER_SetDeepSleepClock(power_deep_sleep_clk_t clk);
+
+/**
+ * @brief Configures and enters in SLEEP low power mode
+ */
+void POWER_EnterSleep(void);
+
+/**
+ * @brief PMC Deep Sleep function call
+ * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during Deep Sleep mode
+ * selected.
+ */
+void POWER_EnterDeepSleep(const uint32_t exclude_from_pd[4]);
+
+/**
+ * @brief PMC Deep Power Down function call
+ * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during Deep Power Down
+ * mode selected.
+ */
+void POWER_EnterDeepPowerDown(const uint32_t exclude_from_pd[4]);
+
+/**
+ * @brief PMC Full Deep Power Down function call
+ * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during Full Deep Power
+ * Down mode selected.
+ */
+void POWER_EnterFullDeepPowerDown(const uint32_t exclude_from_pd[4]);
+
+/*!
+ * @brief Power Library API to enter different power mode.
+ *
+ * @param mode Power mode to enter.
+ * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during power mode selected.
+ */
+void POWER_EnterPowerMode(power_mode_cfg_t mode, const uint32_t exclude_from_pd[4]);
+
+/*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
+ * @param interrupt The IRQ number.
+ */
+void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+/*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
+ * @param interrupt The IRQ number.
+ */
+void DisableDeepSleepIRQ(IRQn_Type interrupt);
+
+/*!
+ * @brief Power Library API to return the library version.
+ *
+ * @return version number of the power library
+ */
+uint32_t POWER_GetLibVersion(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _FSL_POWER_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_reset.c b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_reset.c
new file mode 100644
index 000000000..2a61c1f7c
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_reset.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_reset.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.reset"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ * and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
+{
+ const uint32_t regIndex = ((uint32_t)peripheral & 0x0000FF00u) >> 8;
+ const uint32_t bitPos = ((uint32_t)peripheral & 0x000000FFu);
+ const uint32_t bitMask = 1UL << bitPos;
+
+ assert(bitPos < 32u);
+
+ switch (regIndex)
+ {
+ case RST_CTL0_PSCCTL0:
+ RSTCTL0->PRSTCTL0_SET = bitMask;
+ while (0u == (RSTCTL0->PRSTCTL0 & bitMask))
+ {
+ }
+ break;
+ case RST_CTL0_PSCCTL1:
+ RSTCTL0->PRSTCTL1_SET = bitMask;
+ while (0u == (RSTCTL0->PRSTCTL1 & bitMask))
+ {
+ }
+ break;
+ case RST_CTL0_PSCCTL2:
+ RSTCTL0->PRSTCTL2_SET = bitMask;
+ while (0u == (RSTCTL0->PRSTCTL2 & bitMask))
+ {
+ }
+ break;
+ case RST_CTL1_PSCCTL0:
+ RSTCTL1->PRSTCTL0_SET = bitMask;
+ while (0u == (RSTCTL1->PRSTCTL0 & bitMask))
+ {
+ }
+ break;
+ case RST_CTL1_PSCCTL1:
+ RSTCTL1->PRSTCTL1_SET = bitMask;
+ while (0u == (RSTCTL1->PRSTCTL1 & bitMask))
+ {
+ }
+ break;
+ case RST_CTL1_PSCCTL2:
+ RSTCTL1->PRSTCTL2_SET = bitMask;
+ while (0u == (RSTCTL1->PRSTCTL2 & bitMask))
+ {
+ }
+ break;
+ default:
+ /* Added comments to prevent the violation of MISRA C-2012 rule. */
+ break;
+ }
+}
+
+/*!
+ * brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ * and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
+{
+ const uint32_t regIndex = ((uint32_t)peripheral & 0x0000FF00u) >> 8;
+ const uint32_t bitPos = ((uint32_t)peripheral & 0x000000FFu);
+ const uint32_t bitMask = 1UL << bitPos;
+
+ assert(bitPos < 32u);
+
+ switch (regIndex)
+ {
+ case RST_CTL0_PSCCTL0:
+ RSTCTL0->PRSTCTL0_CLR = bitMask;
+ while (bitMask == (RSTCTL0->PRSTCTL0 & bitMask))
+ {
+ }
+ break;
+ case RST_CTL0_PSCCTL1:
+ RSTCTL0->PRSTCTL1_CLR = bitMask;
+ while (bitMask == (RSTCTL0->PRSTCTL1 & bitMask))
+ {
+ }
+ break;
+ case RST_CTL0_PSCCTL2:
+ RSTCTL0->PRSTCTL2_CLR = bitMask;
+ while (bitMask == (RSTCTL0->PRSTCTL2 & bitMask))
+ {
+ }
+ break;
+ case RST_CTL1_PSCCTL0:
+ RSTCTL1->PRSTCTL0_CLR = bitMask;
+ while (bitMask == (RSTCTL1->PRSTCTL0 & bitMask))
+ {
+ }
+ break;
+ case RST_CTL1_PSCCTL1:
+ RSTCTL1->PRSTCTL1_CLR = bitMask;
+ while (bitMask == (RSTCTL1->PRSTCTL1 & bitMask))
+ {
+ }
+ break;
+ case RST_CTL1_PSCCTL2:
+ RSTCTL1->PRSTCTL2_CLR = bitMask;
+ while (bitMask == (RSTCTL1->PRSTCTL2 & bitMask))
+ {
+ }
+ break;
+ default:
+ /* Added comments to prevent the violation of MISRA C-2012 rule. */
+ break;
+ }
+}
+
+/*!
+ * brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ * and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral)
+{
+ RESET_SetPeripheralReset(peripheral);
+ RESET_ClearPeripheralReset(peripheral);
+}
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_reset.h b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_reset.h
new file mode 100644
index 000000000..67cc2c398
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_reset.h
@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_RESET_H_
+#define _FSL_RESET_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup reset
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief reset driver version 2.0.1. */
+#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*!
+ * @brief Reset control registers index
+ */
+#define RST_CTL0_PSCCTL0 0
+#define RST_CTL0_PSCCTL1 1
+#define RST_CTL0_PSCCTL2 2
+#define RST_CTL1_PSCCTL0 3
+#define RST_CTL1_PSCCTL1 4
+#define RST_CTL1_PSCCTL2 5
+/*!
+ * @brief Enumeration for peripheral reset control bits
+ *
+ * Defines the enumeration for peripheral reset control bits in RSTCLTx registers
+ */
+typedef enum _RSTCTL_RSTn
+{
+ kDSP_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 1U, /**< DSP reset control */
+ kAXI_SWITCH_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 3U, /**< AXI Switch reset control */
+ kPOWERQUAD_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 8U, /**< POWERQUAD reset control */
+ kCASPER_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 9U, /**< CASPER reset control */
+ kHASHCRYPT_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 10U, /**< HASHCRYPT reset control */
+ kPUF_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 11U, /**< Physical unclonable function reset control */
+ kRNG_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 12U, /**< Random number generator (RNG) reset control */
+ kFLEXSPI0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 16U, /**< FLEXSPI0/OTFAD reset control */
+ kFLEXSPI1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 18U, /**< FLEXSPI1 reset control */
+ kUSBHS_PHY_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 20U, /**< High speed USB PHY reset control */
+ kUSBHS_DEVICE_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 21U, /**< High speed USB Device reset control */
+ kUSBHS_HOST_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 22U, /**< High speed USB Host reset control */
+ kUSBHS_SRAM_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 23U, /**< High speed USB SRAM reset control */
+ kSCT_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 24U, /**< Standard ctimers reset control */
+ kGPU_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 26U, /**< GPU reset control */
+ kDISP_CTRL_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 27U, /**< Display controller reset control */
+ kMIPI_DSI_CTRL_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 28U, /**< MIPI DSI controller reset control */
+ kMIPI_DSI_PHY_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 29U, /**< MIPI DSI PHY reset control */
+ kSMART_DMA_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 30U, /**< Smart DMA reset control */
+
+ kSDIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 2U, /**< SDIO0 reset control */
+ kSDIO1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 3U, /**< SDIO1 reset control */
+ kACMP0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 15U, /**< Grouped interrupt (PINT) reset control. */
+ kADC0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 16U, /**< ADC0 reset control */
+ kSHSGPIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 24U, /**< Security HSGPIO 0 reset control */
+
+ kUTICK0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 0U, /**< Micro-tick timer reset control */
+ kWWDT0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 1U, /**< Windowed Watchdog timer 0 reset control */
+
+ kFC0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 8U, /**< Flexcomm Interface 0 reset control */
+ kFC1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 9U, /**< Flexcomm Interface 1 reset control */
+ kFC2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 10U, /**< Flexcomm Interface 2 reset control */
+ kFC3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 11U, /**< Flexcomm Interface 3 reset control */
+ kFC4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 12U, /**< Flexcomm Interface 4 reset control */
+ kFC5_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 13U, /**< Flexcomm Interface 5 reset control */
+ kFC6_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 14U, /**< Flexcomm Interface 6 reset control */
+ kFC7_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 15U, /**< Flexcomm Interface 7 reset control */
+ kFC8_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 16U, /**< Flexcomm Interface 8 reset control */
+ kFC9_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 17U, /**< Flexcomm Interface 9 reset control */
+ kFC10_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 18U, /**< Flexcomm Interface 10 reset control */
+ kFC11_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 19U, /**< Flexcomm Interface 11 reset control */
+ kFC12_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 20U, /**< Flexcomm Interface 12 reset control */
+ kFC13_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 21U, /**< Flexcomm Interface 13 reset control */
+ kFC14_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 22U, /**< Flexcomm Interface 14 reset control */
+ kFC15_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 23U, /**< Flexcomm Interface 15 reset control */
+ kDMIC_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 24U, /**< Digital microphone interface reset control */
+ kFC16_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 25U, /**< Flexcomm Interface 16 reset control */
+ kOSEVENT_TIMER_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 27U, /**< Osevent Timer reset control */
+ kFLEXIO_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 29U, /**< FlexIO reset control */
+
+ kHSGPIO0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 0U, /**< HSGPIO 0 reset control */
+ kHSGPIO1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 1U, /**< HSGPIO 1 reset control */
+ kHSGPIO2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 2U, /**< HSGPIO 2 reset control */
+ kHSGPIO3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 3U, /**< HSGPIO 3 reset control */
+ kHSGPIO4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 4U, /**< HSGPIO 4 reset control */
+ kHSGPIO5_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 5U, /**< HSGPIO 5 reset control */
+ kHSGPIO6_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 6U, /**< HSGPIO 6 reset control */
+ kHSGPIO7_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 7U, /**< HSGPIO 7 reset control */
+ kCRC_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 16U, /**< CRC reset control */
+ kDMAC0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 23U, /**< DMA Controller 0 reset control */
+ kDMAC1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 24U, /**< DMA Controller 1 reset control */
+ kMU_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 28U, /**< Message Unit reset control */
+ kSEMA_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 29U, /**< Semaphore reset control */
+ kFREQME_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 31U, /**< Frequency Measure reset control */
+
+ kCT32B0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 0U, /**< CT32B0 reset control */
+ kCT32B1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 1U, /**< CT32B1 reset control */
+ kCT32B2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 2U, /**< CT32B3 reset control */
+ kCT32B3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 3U, /**< CT32B4 reset control */
+ kCT32B4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 4U, /**< CT32B4 reset control */
+ kMRT0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 8U, /**< Multi-rate timer (MRT) reset control */
+ kWWDT1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 10U, /**< Windowed Watchdog timer 1 reset control */
+ kI3C0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 16U, /**< I3C0 reset control */
+ kI3C1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 17U, /**< I3C1 reset control */
+ kPINT_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 30U, /**< GPIO Pin interrupt reset control */
+ kINPUTMUX_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 31U, /**< Peripheral input muxes reset control */
+} RSTCTL_RSTn_t;
+
+/** Array initializers with peripheral reset bits **/
+#define ADC_RSTS \
+ { \
+ kADC0_RST_SHIFT_RSTn \
+ } /* Reset bits for ADC peripheral */
+#define CASPER_RSTS \
+ { \
+ kCASPER_RST_SHIFT_RSTn \
+ } /* Reset bits for Casper peripheral */
+#define CRC_RSTS \
+ { \
+ kCRC_RST_SHIFT_RSTn \
+ } /* Reset bits for CRC peripheral */
+#define CTIMER_RSTS \
+ { \
+ kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \
+ kCT32B4_RST_SHIFT_RSTn \
+ } /* Reset bits for TIMER peripheral */
+#define DCNANO_RSTS \
+ { \
+ kDISP_CTRL_RST_SHIFT_RSTn \
+ } /* Reset bits for CRC peripheral */
+#define MIPI_DSI_RSTS \
+ { \
+ kMIPI_DSI_CTRL_RST_SHIFT_RSTn \
+ } /* Reset bits for CRC peripheral */
+#define DMA_RSTS_N \
+ { \
+ kDMAC0_RST_SHIFT_RSTn, kDMAC1_RST_SHIFT_RSTn \
+ } /* Reset bits for DMA peripheral */
+#define DMIC_RSTS \
+ { \
+ kDMIC_RST_SHIFT_RSTn \
+ } /* Reset bits for ADC peripheral */
+#define FLEXCOMM_RSTS \
+ { \
+ kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
+ kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn, \
+ kFC10_RST_SHIFT_RSTn, kFC11_RST_SHIFT_RSTn, kFC12_RST_SHIFT_RSTn, kFC13_RST_SHIFT_RSTn, \
+ kFC14_RST_SHIFT_RSTn, kFC15_RST_SHIFT_RSTn, kFC16_RST_SHIFT_RSTn \
+ } /* Reset bits for FLEXCOMM peripheral */
+#define FLEXIO_RSTS \
+ { \
+ kFLEXIO_RST_SHIFT_RSTn \
+ } /* Resets bits for FLEXIO peripheral */
+#define FLEXSPI_RSTS \
+ { \
+ kFLEXSPI0_RST_SHIFT_RSTn, kFLEXSPI1_RST_SHIFT_RSTn \
+ } /* Resets bits for FLEXSPI peripheral */
+#define GPIO_RSTS_N \
+ { \
+ kHSGPIO0_RST_SHIFT_RSTn, kHSGPIO1_RST_SHIFT_RSTn, kHSGPIO2_RST_SHIFT_RSTn, kHSGPIO3_RST_SHIFT_RSTn, \
+ kHSGPIO4_RST_SHIFT_RSTn, kHSGPIO5_RST_SHIFT_RSTn, kHSGPIO6_RST_SHIFT_RSTn, kHSGPIO7_RST_SHIFT_RSTn \
+ } /* Reset bits for GPIO peripheral */
+#define HASHCRYPT_RSTS \
+ { \
+ kHASHCRYPT_RST_SHIFT_RSTn \
+ } /* Reset bits for Hashcrypt peripheral */
+#define I3C_RSTS \
+ { \
+ kI3C0_RST_SHIFT_RSTn, kI3C1_RST_SHIFT_RSTn \
+ } /* Reset bits for I3C peripheral */
+#define INPUTMUX_RSTS \
+ { \
+ kINPUTMUX_RST_SHIFT_RSTn \
+ } /* Reset bits for INPUTMUX peripheral */
+#define MRT_RSTS \
+ { \
+ kMRT0_RST_SHIFT_RSTn \
+ } /* Reset bits for MRT peripheral */
+#define MU_RSTS \
+ { \
+ kMU_RST_SHIFT_RSTn \
+ } /* Reset bits for MU peripheral */
+#define OSTIMER_RSTS \
+ { \
+ kOSEVENT_TIMER_RST_SHIFT_RSTn \
+ } /* Reset bits for OSTIMER peripheral */
+#define PINT_RSTS \
+ { \
+ kPINT_RST_SHIFT_RSTn \
+ } /* Reset bits for PINT peripheral */
+#define POWERQUAD_RSTS \
+ { \
+ kPOWERQUAD_RST_SHIFT_RSTn \
+ } /* Reset bits for Powerquad peripheral */
+#define PUF_RSTS \
+ { \
+ kPUF_RST_SHIFT_RSTn \
+ } /* Reset bits for PUF peripheral */
+#define SCT_RSTS \
+ { \
+ kSCT_RST_SHIFT_RSTn \
+ } /* Reset bits for SCT peripheral */
+#define SEMA42_RSTS \
+ { \
+ kSEMA_RST_SHIFT_RSTn \
+ } /* Reset bits for SEMA42 peripheral */
+#define TRNG_RSTS \
+ { \
+ kRNG_RST_SHIFT_RSTn \
+ } /* Reset bits for TRNG peripheral */
+#define USDHC_RSTS \
+ { \
+ kSDIO0_RST_SHIFT_RSTn, kSDIO1_RST_SHIFT_RSTn \
+ } /* Reset bits for USDHC peripheral */
+#define UTICK_RSTS \
+ { \
+ kUTICK0_RST_SHIFT_RSTn \
+ } /* Reset bits for UTICK peripheral */
+#define WWDT_RSTS \
+ { \
+ kWWDT0_RST_SHIFT_RSTn, kWWDT1_RST_SHIFT_RSTn \
+ } /* Reset bits for WWDT peripheral */
+
+/*!
+ * @brief IP reset handle
+ */
+typedef RSTCTL_RSTn_t reset_ip_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ * and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ * and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ * and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_RESET_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_usart.c b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_usart.c
new file mode 100644
index 000000000..1bbf23587
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_usart.c
@@ -0,0 +1,1160 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_usart.h"
+#include "fsl_device_registers.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart"
+#endif
+
+/*!
+ * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t`
+ */
+typedef union usart_to_flexcomm
+{
+ flexcomm_usart_irq_handler_t usart_master_handler;
+ flexcomm_irq_handler_t flexcomm_handler;
+} usart_to_flexcomm_t;
+
+enum
+{
+ kUSART_TxIdle, /* TX idle. */
+ kUSART_TxBusy, /* TX busy. */
+ kUSART_RxIdle, /* RX idle. */
+ kUSART_RxBusy /* RX busy. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief IRQ name array */
+static const IRQn_Type s_usartIRQ[] = USART_IRQS;
+
+/*! @brief Array to map USART instance number to base address. */
+static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Get the index corresponding to the USART */
+/*! brief Returns instance number for USART peripheral base address. */
+uint32_t USART_GetInstance(USART_Type *base)
+{
+ uint32_t i;
+
+ for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++)
+ {
+ if ((uint32_t)base == s_usartBaseAddrs[i])
+ {
+ break;
+ }
+ }
+
+ assert(i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT);
+ return i;
+}
+
+/*!
+ * brief Get the length of received data in RX ring buffer.
+ *
+ * param handle USART handle pointer.
+ * return Length of received data in RX ring buffer.
+ */
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle)
+{
+ size_t size;
+
+ /* Check arguments */
+ assert(NULL != handle);
+ uint16_t rxRingBufferHead = handle->rxRingBufferHead;
+ uint16_t rxRingBufferTail = handle->rxRingBufferTail;
+
+ if (rxRingBufferTail > rxRingBufferHead)
+ {
+ size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail;
+ }
+ else
+ {
+ size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail;
+ }
+ return size;
+}
+
+static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle)
+{
+ bool full;
+
+ /* Check arguments */
+ assert(NULL != handle);
+
+ if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
+ {
+ full = true;
+ }
+ else
+ {
+ full = false;
+ }
+ return full;
+}
+
+/*!
+ * brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific USART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * param ringBufferSize size of the ring buffer.
+ */
+void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
+{
+ /* Check arguments */
+ assert(NULL != base);
+ assert(NULL != handle);
+ assert(NULL != ringBuffer);
+
+ /* Setup the ringbuffer address */
+ handle->rxRingBuffer = ringBuffer;
+ handle->rxRingBufferSize = ringBufferSize;
+ handle->rxRingBufferHead = 0U;
+ handle->rxRingBufferTail = 0U;
+ /* ring buffer is ready we can start receiving data */
+ base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+}
+
+/*!
+ * brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle)
+{
+ /* Check arguments */
+ assert(NULL != base);
+ assert(NULL != handle);
+
+ if (handle->rxState == (uint8_t)kUSART_RxIdle)
+ {
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK;
+ }
+ handle->rxRingBuffer = NULL;
+ handle->rxRingBufferSize = 0U;
+ handle->rxRingBufferHead = 0U;
+ handle->rxRingBufferTail = 0U;
+}
+
+/*!
+ * brief Initializes a USART instance with user configuration structure and peripheral clock.
+ *
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.
+ * Example below shows how to use this API to configure USART.
+ * code
+ * usart_config_t usartConfig;
+ * usartConfig.baudRate_Bps = 115200U;
+ * usartConfig.parityMode = kUSART_ParityDisabled;
+ * usartConfig.stopBitCount = kUSART_OneStopBit;
+ * USART_Init(USART1, &usartConfig, 20000000U);
+ * endcode
+ *
+ * param base USART peripheral base address.
+ * param config Pointer to user-defined configuration structure.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_InvalidArgument USART base address is not valid
+ * retval kStatus_Success Status USART initialize succeed
+ */
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz)
+{
+ int result;
+
+ /* check arguments */
+ assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz)));
+ if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ /* initialize flexcomm to USART mode */
+ result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART);
+ if (kStatus_Success != result)
+ {
+ return result;
+ }
+
+ if (config->enableTx)
+ {
+ /* empty and enable txFIFO */
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK;
+ /* setup trigger level */
+ base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK);
+ base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark);
+ /* enable trigger interrupt */
+ base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK;
+ }
+
+ /* empty and enable rxFIFO */
+ if (config->enableRx)
+ {
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK;
+ /* setup trigger level */
+ base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK);
+ base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark);
+ /* enable trigger interrupt */
+ base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK;
+ }
+ /* setup configuration and enable USART */
+ base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) |
+ USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) |
+ USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) |
+ USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) |
+ USART_CFG_CTSEN(config->enableHardwareFlowControl) | USART_CFG_ENABLE_MASK;
+
+ /* Setup baudrate */
+ if (config->enableMode32k)
+ {
+ if ((9600U % config->baudRate_Bps) == 0U)
+ {
+ base->BRG = 9600U / config->baudRate_Bps;
+ }
+ else
+ {
+ return kStatus_USART_BaudrateNotSupport;
+ }
+ }
+ else
+ {
+ result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);
+ if (kStatus_Success != result)
+ {
+ return result;
+ }
+ }
+ /* Setting continuous Clock configuration. used for synchronous mode. */
+ USART_EnableContinuousSCLK(base, config->enableContinuousSCLK);
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Deinitializes a USART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.
+ *
+ * param base USART peripheral base address.
+ */
+void USART_Deinit(USART_Type *base)
+{
+ /* Check arguments */
+ assert(NULL != base);
+ while (0U == (base->STAT & USART_STAT_TXIDLE_MASK))
+ {
+ }
+ /* Disable interrupts, disable dma requests, disable peripheral */
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK |
+ USART_FIFOINTENCLR_RXLVL_MASK;
+ base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK);
+ base->CFG &= ~(USART_CFG_ENABLE_MASK);
+}
+
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the USART configuration structure to a default value. The default
+ * values are:
+ * usartConfig->baudRate_Bps = 115200U;
+ * usartConfig->parityMode = kUSART_ParityDisabled;
+ * usartConfig->stopBitCount = kUSART_OneStopBit;
+ * usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
+ * usartConfig->loopback = false;
+ * usartConfig->enableTx = false;
+ * usartConfig->enableRx = false;
+ *
+ * param config Pointer to configuration structure.
+ */
+void USART_GetDefaultConfig(usart_config_t *config)
+{
+ /* Check arguments */
+ assert(NULL != config);
+
+ /* Initializes the configure structure to zero. */
+ (void)memset(config, 0, sizeof(*config));
+
+ /* Set always all members ! */
+ config->baudRate_Bps = 115200U;
+ config->parityMode = kUSART_ParityDisabled;
+ config->stopBitCount = kUSART_OneStopBit;
+ config->bitCountPerChar = kUSART_8BitsPerChar;
+ config->loopback = false;
+ config->enableRx = false;
+ config->enableTx = false;
+ config->enableMode32k = false;
+ config->txWatermark = kUSART_TxFifo0;
+ config->rxWatermark = kUSART_RxFifo1;
+ config->syncMode = kUSART_SyncModeDisabled;
+ config->enableContinuousSCLK = false;
+ config->clockPolarity = kUSART_RxSampleOnFallingEdge;
+ config->enableHardwareFlowControl = false;
+}
+
+/*!
+ * brief Sets the USART instance baud rate.
+ *
+ * This function configures the USART module baud rate. This function is used to update
+ * the USART module baud rate after the USART module is initialized by the USART_Init.
+ * code
+ * USART_SetBaudRate(USART1, 115200U, 20000000U);
+ * endcode
+ *
+ * param base USART peripheral base address.
+ * param baudrate_Bps USART baudrate to be set.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success Set baudrate succeed.
+ * retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
+{
+ uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1;
+ uint32_t osrval, brgval, diff, baudrate;
+
+ /* check arguments */
+ assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)));
+ if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ /* If synchronous master mode is enabled, only configure the BRG value. */
+ if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U)
+ {
+ if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U)
+ {
+ brgval = srcClock_Hz / baudrate_Bps;
+ base->BRG = brgval - 1U;
+ }
+ }
+ else
+ {
+ /*
+ * Smaller values of OSR can make the sampling position within a data bit less accurate and may
+ * potentially cause more noise errors or incorrect data.
+ */
+ for (osrval = best_osrval; osrval >= 8U; osrval--)
+ {
+ brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U;
+ if (brgval > 0xFFFFU)
+ {
+ continue;
+ }
+ baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U));
+ diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate);
+ if (diff < best_diff)
+ {
+ best_diff = diff;
+ best_osrval = osrval;
+ best_brgval = brgval;
+ }
+ }
+
+ /* Check to see if actual baud rate is within 3% of desired baud rate
+ * based on the best calculated OSR and BRG value */
+ baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U));
+ diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate);
+ if (diff > ((baudrate_Bps / 100U) * 3U))
+ {
+ return kStatus_USART_BaudrateNotSupport;
+ }
+
+ /* value over range */
+ if (best_brgval > 0xFFFFU)
+ {
+ return kStatus_USART_BaudrateNotSupport;
+ }
+
+ base->OSR = best_osrval;
+ base->BRG = best_brgval;
+ }
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source.
+ *
+ * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator
+ * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting
+ * SYSCON_RTCOSCCTRL_EN bit to 1.
+ * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that
+ * 9600 can evenly divide, eg: 4800, 3200.
+ *
+ * param base USART peripheral base address.
+ * param baudRate_Bps USART baudrate to be set..
+ * param enableMode32k true is 32k mode, false is normal mode.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success Set baudrate succeed.
+ * retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz)
+{
+ status_t result = kStatus_Success;
+ base->CFG &= ~(USART_CFG_ENABLE_MASK);
+ if (enableMode32k)
+ {
+ base->CFG |= USART_CFG_MODE32K_MASK;
+ if ((9600U % baudRate_Bps) == 0U)
+ {
+ base->BRG = 9600U / baudRate_Bps - 1U;
+ }
+ else
+ {
+ return kStatus_USART_BaudrateNotSupport;
+ }
+ }
+ else
+ {
+ base->CFG &= ~(USART_CFG_MODE32K_MASK);
+ result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz);
+ if (kStatus_Success != result)
+ {
+ return result;
+ }
+ }
+ base->CFG |= USART_CFG_ENABLE_MASK;
+ return result;
+}
+
+/*!
+ * brief Enable 9-bit data mode for USART.
+ *
+ * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user.
+ *
+ * param base USART peripheral base address.
+ * param enable true to enable, false to disable.
+ */
+void USART_Enable9bitMode(USART_Type *base, bool enable)
+{
+ assert(base != NULL);
+
+ uint32_t temp = 0U;
+
+ if (enable)
+ {
+ /* Set USART 9-bit mode, disable parity. */
+ temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK);
+ temp |= (uint32_t)USART_CFG_DATALEN(0x2U);
+ base->CFG = temp;
+ }
+ else
+ {
+ /* Set USART to 8-bit mode. */
+ base->CFG &= ~((uint32_t)USART_CFG_DATALEN_MASK);
+ base->CFG |= (uint32_t)USART_CFG_DATALEN(0x1U);
+ }
+}
+
+/*!
+ * brief Transmit an address frame in 9-bit data mode.
+ *
+ * param base USART peripheral base address.
+ * param address USART slave address.
+ */
+void USART_SendAddress(USART_Type *base, uint8_t address)
+{
+ assert(base != NULL);
+ base->FIFOWR = ((uint32_t)address | 0x100UL);
+}
+
+/*!
+ * brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * param base USART peripheral base address.
+ * param data Start address of the data to write.
+ * param length Size of the data to write.
+ * retval kStatus_USART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_InvalidArgument Invalid argument.
+ * retval kStatus_Success Successfully wrote all data.
+ */
+status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length)
+{
+ /* Check arguments */
+ assert(!((NULL == base) || (NULL == data)));
+#if UART_RETRY_TIMES
+ uint32_t waitTimes;
+#endif
+ if ((NULL == base) || (NULL == data))
+ {
+ return kStatus_InvalidArgument;
+ }
+ /* Check whether txFIFO is enabled */
+ if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK))
+ {
+ return kStatus_InvalidArgument;
+ }
+ for (; length > 0U; length--)
+ {
+ /* Loop until txFIFO get some space for new data */
+#if UART_RETRY_TIMES
+ waitTimes = UART_RETRY_TIMES;
+ while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U))
+#else
+ while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
+#endif
+ {
+ }
+#if UART_RETRY_TIMES
+ if (0U == waitTimes)
+ {
+ return kStatus_USART_Timeout;
+ }
+#endif
+ base->FIFOWR = *data;
+ data++;
+ }
+ /* Wait to finish transfer */
+#if UART_RETRY_TIMES
+ waitTimes = UART_RETRY_TIMES;
+ while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U))
+#else
+ while (0U == (base->STAT & USART_STAT_TXIDLE_MASK))
+#endif
+ {
+ }
+#if UART_RETRY_TIMES
+ if (0U == waitTimes)
+ {
+ return kStatus_USART_Timeout;
+ }
+#endif
+ return kStatus_Success;
+}
+
+/*!
+ * brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data and read data from the TX register.
+ *
+ * param base USART peripheral base address.
+ * param data Start address of the buffer to store the received data.
+ * param length Size of the buffer.
+ * retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
+ * retval kStatus_USART_ParityError Noise error happened while receiving data.
+ * retval kStatus_USART_NoiseError Framing error happened while receiving data.
+ * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * retval kStatus_USART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_Success Successfully received all data.
+ */
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length)
+{
+ uint32_t statusFlag;
+ status_t status = kStatus_Success;
+#if UART_RETRY_TIMES
+ uint32_t waitTimes;
+#endif
+
+ /* check arguments */
+ assert(!((NULL == base) || (NULL == data)));
+ if ((NULL == base) || (NULL == data))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ /* Check whether rxFIFO is enabled */
+ if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U)
+ {
+ return kStatus_Fail;
+ }
+ for (; length > 0U; length--)
+ {
+ /* loop until rxFIFO have some data to read */
+#if UART_RETRY_TIMES
+ waitTimes = UART_RETRY_TIMES;
+ while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U))
+#else
+ while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U)
+#endif
+ {
+ }
+#if UART_RETRY_TIMES
+ if (waitTimes == 0U)
+ {
+ status = kStatus_USART_Timeout;
+ break;
+ }
+#endif
+ /* check rxFIFO statusFlag */
+ if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U)
+ {
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+ base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+ status = kStatus_USART_RxError;
+ break;
+ }
+ /* check receive statusFlag */
+ statusFlag = base->STAT;
+ /* Clear all status flags */
+ base->STAT |= statusFlag;
+ if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U)
+ {
+ status = kStatus_USART_ParityError;
+ }
+ if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U)
+ {
+ status = kStatus_USART_FramingError;
+ }
+ if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U)
+ {
+ status = kStatus_USART_NoiseError;
+ }
+
+ if (kStatus_Success == status)
+ {
+ *data = (uint8_t)base->FIFORD;
+ data++;
+ }
+ else
+ {
+ break;
+ }
+ }
+ return status;
+}
+
+/*!
+ * brief Initializes the USART handle.
+ *
+ * This function initializes the USART handle which can be used for other USART
+ * transactional APIs. Usually, for a specified USART instance,
+ * call this API once to get the initialized handle.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ */
+status_t USART_TransferCreateHandle(USART_Type *base,
+ usart_handle_t *handle,
+ usart_transfer_callback_t callback,
+ void *userData)
+{
+ /* Check 'base' */
+ assert(!((NULL == base) || (NULL == handle)));
+
+ uint32_t instance = 0;
+ usart_to_flexcomm_t handler;
+ handler.usart_master_handler = USART_TransferHandleIRQ;
+
+ if ((NULL == base) || (NULL == handle))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ instance = USART_GetInstance(base);
+
+ (void)memset(handle, 0, sizeof(*handle));
+ /* Set the TX/RX state. */
+ handle->rxState = (uint8_t)kUSART_RxIdle;
+ handle->txState = (uint8_t)kUSART_TxIdle;
+ /* Set the callback and user data. */
+ handle->callback = callback;
+ handle->userData = userData;
+ handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base);
+ handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base);
+
+ FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle);
+
+ /* Enable interrupt in NVIC. */
+ (void)EnableIRQ(s_usartIRQ[instance]);
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback
+ * function and passes the ref kStatus_USART_TxIdle as status parameter.
+ *
+ * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param xfer USART transfer structure. See #usart_transfer_t.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer)
+{
+ /* Check arguments */
+ assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+ if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+ {
+ return kStatus_InvalidArgument;
+ }
+ /* Check xfer members */
+ assert(!((0U == xfer->dataSize) || (NULL == xfer->txData)));
+ if ((0U == xfer->dataSize) || (NULL == xfer->txData))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ /* Return error if current TX busy. */
+ if ((uint8_t)kUSART_TxBusy == handle->txState)
+ {
+ return kStatus_USART_TxBusy;
+ }
+ else
+ {
+ /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up the
+ * handle value. */
+ uint32_t interruptMask = USART_GetEnabledInterrupts(base);
+ USART_DisableInterrupts(base, interruptMask);
+ handle->txData = xfer->txData;
+ handle->txDataSize = xfer->dataSize;
+ handle->txDataSizeAll = xfer->dataSize;
+ handle->txState = (uint8_t)kUSART_TxBusy;
+ /* Enable transmiter interrupt and the previously disabled interrupt. */
+ USART_EnableInterrupts(base, interruptMask | (uint32_t)kUSART_TxLevelInterruptEnable);
+ }
+ return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are still not sent out.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle)
+{
+ assert(NULL != handle);
+
+ /* Disable interrupts */
+ USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable);
+ /* Empty txFIFO */
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK;
+
+ handle->txDataSize = 0U;
+ handle->txState = (uint8_t)kUSART_TxIdle;
+}
+
+/*!
+ * brief Get the number of bytes that have been sent out to bus.
+ *
+ * This function gets the number of bytes that have been sent out to bus by interrupt method.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param count Send bytes count.
+ * retval kStatus_NoTransferInProgress No send in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+ assert(NULL != handle);
+ assert(NULL != count);
+
+ if ((uint8_t)kUSART_TxIdle == handle->txState)
+ {
+ return kStatus_NoTransferInProgress;
+ }
+
+ *count = handle->txDataSizeAll - handle->txDataSize -
+ ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT);
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the USART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the USART driver notifies the upper layer
+ * through a callback function and passes the status parameter ref kStatus_USART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param xfer USART transfer structure, see #usart_transfer_t.
+ * param receivedBytes Bytes received from the ring buffer directly.
+ * retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * retval kStatus_USART_RxBusy Previous receive request is not finished.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+ usart_handle_t *handle,
+ usart_transfer_t *xfer,
+ size_t *receivedBytes)
+{
+ uint32_t i;
+ /* How many bytes to copy from ring buffer to user memory. */
+ size_t bytesToCopy = 0U;
+ /* How many bytes to receive. */
+ size_t bytesToReceive;
+ /* How many bytes currently have received. */
+ size_t bytesCurrentReceived;
+ uint32_t interruptMask = 0U;
+
+ /* Check arguments */
+ assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+ if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+ {
+ return kStatus_InvalidArgument;
+ }
+ /* Check xfer members */
+ assert(!((0U == xfer->dataSize) || (NULL == xfer->rxData)));
+ if ((0U == xfer->dataSize) || (NULL == xfer->rxData))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ /* Enable address detect when address match is enabled. */
+ if ((base->CFG & (uint32_t)USART_CFG_AUTOADDR_MASK) != 0U)
+ {
+ base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK;
+ }
+
+ /* How to get data:
+ 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+ to uart handle, enable interrupt to store received data to xfer->data. When
+ all data received, trigger callback.
+ 2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+ If there are enough data in ring buffer, copy them to xfer->data and return.
+ If there are not enough data in ring buffer, copy all of them to xfer->data,
+ save the xfer->data remained empty space to uart handle, receive data
+ to this empty space and trigger callback when finished. */
+ if ((uint8_t)kUSART_RxBusy == handle->rxState)
+ {
+ return kStatus_USART_RxBusy;
+ }
+ else
+ {
+ bytesToReceive = xfer->dataSize;
+ bytesCurrentReceived = 0U;
+ /* If RX ring buffer is used. */
+ if (handle->rxRingBuffer != NULL)
+ {
+ /* Disable IRQ, protect ring buffer. */
+ interruptMask = USART_GetEnabledInterrupts(base);
+ USART_DisableInterrupts(base, interruptMask);
+
+ /* How many bytes in RX ring buffer currently. */
+ bytesToCopy = USART_TransferGetRxRingBufferLength(handle);
+ if (bytesToCopy != 0U)
+ {
+ bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+ bytesToReceive -= bytesToCopy;
+ /* Copy data from ring buffer to user memory. */
+ for (i = 0U; i < bytesToCopy; i++)
+ {
+ xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+ /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+ if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+ {
+ handle->rxRingBufferTail = 0U;
+ }
+ else
+ {
+ handle->rxRingBufferTail++;
+ }
+ }
+ }
+ /* If ring buffer does not have enough data, still need to read more data. */
+ if (bytesToReceive != 0U)
+ {
+ /* No data in ring buffer, save the request to UART handle. */
+ handle->rxData = xfer->rxData + bytesCurrentReceived;
+ handle->rxDataSize = bytesToReceive;
+ handle->rxDataSizeAll = xfer->dataSize;
+ handle->rxState = (uint8_t)kUSART_RxBusy;
+ }
+ /* Re-enable IRQ. */
+ USART_EnableInterrupts(base, interruptMask);
+ /* Call user callback since all data are received. */
+ if (0U == bytesToReceive)
+ {
+ if (handle->callback != NULL)
+ {
+ handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+ }
+ }
+ }
+ /* Ring buffer not used. */
+ else
+ {
+ /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up
+ * the handle value. */
+ interruptMask = USART_GetEnabledInterrupts(base);
+ USART_DisableInterrupts(base, interruptMask);
+ handle->rxData = xfer->rxData + bytesCurrentReceived;
+ handle->rxDataSize = bytesToReceive;
+ handle->rxDataSizeAll = bytesToReceive;
+ handle->rxState = (uint8_t)kUSART_RxBusy;
+
+ /* Enable RX interrupt. */
+ base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK;
+ /* Re-enable IRQ. */
+ USART_EnableInterrupts(base, interruptMask);
+ }
+ /* Return the how many bytes have read. */
+ if (receivedBytes != NULL)
+ {
+ *receivedBytes = bytesCurrentReceived;
+ }
+ }
+ return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle)
+{
+ assert(NULL != handle);
+
+ /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+ if (NULL == handle->rxRingBuffer)
+ {
+ /* Disable interrupts */
+ USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable);
+ /* Empty rxFIFO */
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+ }
+
+ handle->rxDataSize = 0U;
+ handle->rxState = (uint8_t)kUSART_RxIdle;
+}
+
+/*!
+ * brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param count Receive bytes count.
+ * retval kStatus_NoTransferInProgress No receive in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+ assert(NULL != handle);
+ assert(NULL != count);
+
+ if ((uint8_t)kUSART_RxIdle == handle->rxState)
+ {
+ return kStatus_NoTransferInProgress;
+ }
+
+ *count = handle->rxDataSizeAll - handle->rxDataSize;
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief USART IRQ handle function.
+ *
+ * This function handles the USART transmit and receive IRQ request.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle)
+{
+ /* Check arguments */
+ assert((NULL != base) && (NULL != handle));
+
+ bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL));
+ bool sendEnabled = (handle->txDataSize != 0U);
+ uint8_t rxdata;
+ size_t tmpsize;
+
+ /* If RX overrun. */
+ if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U)
+ {
+ /* Clear rx error state. */
+ base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+ /* clear rxFIFO */
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+ /* Trigger callback. */
+ if (handle->callback != NULL)
+ {
+ handle->callback(base, handle, kStatus_USART_RxError, handle->userData);
+ }
+ }
+ while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) ||
+ (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)))
+ {
+ /* Receive data */
+ if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U))
+ {
+ /* Clear address detect when RXFIFO has data. */
+ base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK;
+ /* Receive to app bufffer if app buffer is present */
+ if (handle->rxDataSize != 0U)
+ {
+ rxdata = (uint8_t)base->FIFORD;
+ *handle->rxData = rxdata;
+ handle->rxDataSize--;
+ handle->rxData++;
+ receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL));
+ if (0U == handle->rxDataSize)
+ {
+ if (NULL == handle->rxRingBuffer)
+ {
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+ }
+ handle->rxState = (uint8_t)kUSART_RxIdle;
+ if (handle->callback != NULL)
+ {
+ handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+ }
+ }
+ }
+ /* Otherwise receive to ring buffer if ring buffer is present */
+ else
+ {
+ if (handle->rxRingBuffer != NULL)
+ {
+ /* If RX ring buffer is full, trigger callback to notify over run. */
+ if (USART_TransferIsRxRingBufferFull(handle))
+ {
+ if (handle->callback != NULL)
+ {
+ handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData);
+ }
+ }
+ /* If ring buffer is still full after callback function, the oldest data is overridden. */
+ if (USART_TransferIsRxRingBufferFull(handle))
+ {
+ /* Increase handle->rxRingBufferTail to make room for new data. */
+ if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+ {
+ handle->rxRingBufferTail = 0U;
+ }
+ else
+ {
+ handle->rxRingBufferTail++;
+ }
+ }
+ /* Read data. */
+ rxdata = (uint8_t)base->FIFORD;
+ handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata;
+ /* Increase handle->rxRingBufferHead. */
+ if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+ {
+ handle->rxRingBufferHead = 0U;
+ }
+ else
+ {
+ handle->rxRingBufferHead++;
+ }
+ }
+ }
+ }
+ /* Send data */
+ if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))
+ {
+ base->FIFOWR = *handle->txData;
+ handle->txDataSize--;
+ handle->txData++;
+ sendEnabled = handle->txDataSize != 0U;
+ if (!sendEnabled)
+ {
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;
+
+ base->INTENSET = USART_INTENSET_TXIDLEEN_MASK;
+ }
+ }
+ }
+
+ /* Tx idle and the interrupt is enabled. */
+ if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK)))
+ {
+ /* Set txState to idle only when all data has been sent out to bus. */
+ handle->txState = (uint8_t)kUSART_TxIdle;
+ /* Disable tx idle interrupt */
+ base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK;
+
+ /* Trigger callback. */
+ if (handle->callback != NULL)
+ {
+ handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData);
+ }
+ }
+
+ /* ring buffer is not used */
+ if (NULL == handle->rxRingBuffer)
+ {
+ tmpsize = handle->rxDataSize;
+
+ /* restore if rx transfer ends and rxLevel is different from default value */
+ if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark))
+ {
+ base->FIFOTRIG =
+ (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark);
+ }
+ /* decrease level if rx transfer is bellow */
+ if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U)))
+ {
+ base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U));
+ }
+ }
+}
diff --git a/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_usart.h b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_usart.h
new file mode 100644
index 000000000..68467e7e2
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/drivers/fsl_usart.h
@@ -0,0 +1,866 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_USART_H_
+#define _FSL_USART_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup usart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief USART driver version. */
+#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
+/*@}*/
+
+#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT)
+#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT)
+
+/*! @brief Retry times for waiting flag. */
+#ifndef UART_RETRY_TIMES
+#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */
+#endif
+
+/*! @brief Error codes for the USART driver. */
+enum
+{
+ kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */
+ kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */
+ kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */
+ kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */
+ kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */
+ kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */
+ kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */
+ kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */
+ kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */
+ kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */
+ kStatus_USART_BaudrateNotSupport =
+ MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */
+ kStatus_USART_Timeout = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART time out. */
+};
+
+/*! @brief USART synchronous mode. */
+typedef enum _usart_sync_mode
+{
+ kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */
+ kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */
+ kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */
+} usart_sync_mode_t;
+
+/*! @brief USART parity mode. */
+typedef enum _usart_parity_mode
+{
+ kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */
+ kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
+ kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */
+} usart_parity_mode_t;
+
+/*! @brief USART stop bit count. */
+typedef enum _usart_stop_bit_count
+{
+ kUSART_OneStopBit = 0U, /*!< One stop bit */
+ kUSART_TwoStopBit = 1U, /*!< Two stop bits */
+} usart_stop_bit_count_t;
+
+/*! @brief USART data size. */
+typedef enum _usart_data_len
+{
+ kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */
+ kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */
+} usart_data_len_t;
+
+/*! @brief USART clock polarity configuration, used in sync mode.*/
+typedef enum _usart_clock_polarity
+{
+ kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */
+ kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */
+} usart_clock_polarity_t;
+
+/*! @brief txFIFO watermark values */
+typedef enum _usart_txfifo_watermark
+{
+ kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */
+ kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */
+ kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */
+ kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */
+ kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */
+ kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */
+ kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */
+ kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */
+} usart_txfifo_watermark_t;
+
+/*! @brief rxFIFO watermark values */
+typedef enum _usart_rxfifo_watermark
+{
+ kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */
+ kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */
+ kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */
+ kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */
+ kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */
+ kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */
+ kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */
+ kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */
+} usart_rxfifo_watermark_t;
+
+/*!
+ * @brief USART interrupt configuration structure, default settings all disabled.
+ */
+enum _usart_interrupt_enable
+{
+ kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK),
+ kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK),
+ kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK),
+ kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK),
+};
+
+/*!
+ * @brief USART status flags.
+ *
+ * This provides constants for the USART status flags for use in the USART functions.
+ */
+enum _usart_flags
+{
+ kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */
+ kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */
+ kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */
+ kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */
+ kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */
+ kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */
+};
+
+/*! @brief USART configuration structure. */
+typedef struct _usart_config
+{
+ uint32_t baudRate_Bps; /*!< USART baud rate */
+ usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
+ usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
+ usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */
+ bool loopback; /*!< Enable peripheral loopback */
+ bool enableRx; /*!< Enable RX */
+ bool enableTx; /*!< Enable TX */
+ bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */
+ bool enableMode32k; /*!< USART uses 32 kHz clock from the RTC oscillator as the clock source. */
+ bool enableHardwareFlowControl; /*!< Enable hardware control RTS/CTS */
+ usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+ usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+ usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */
+ usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */
+} usart_config_t;
+
+/*! @brief USART transfer structure. */
+typedef struct _usart_transfer
+{
+ /*
+ * Use separate TX and RX data pointer, because TX data is const data.
+ * The member data is kept for backward compatibility.
+ */
+ union
+ {
+ uint8_t *data; /*!< The buffer of data to be transfer.*/
+ uint8_t *rxData; /*!< The buffer to receive data. */
+ const uint8_t *txData; /*!< The buffer of data to be sent. */
+ };
+ size_t dataSize; /*!< The byte count to be transfer. */
+} usart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _usart_handle usart_handle_t;
+
+/*! @brief USART transfer callback function. */
+typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData);
+
+/*! @brief USART handle structure. */
+struct _usart_handle
+{
+ const uint8_t *volatile txData; /*!< Address of remaining data to send. */
+ volatile size_t txDataSize; /*!< Size of the remaining data to send. */
+ size_t txDataSizeAll; /*!< Size of the data to send out. */
+ uint8_t *volatile rxData; /*!< Address of remaining data to receive. */
+ volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
+ size_t rxDataSizeAll; /*!< Size of the data to receive. */
+
+ uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */
+ size_t rxRingBufferSize; /*!< Size of the ring buffer. */
+ volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+ volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+ usart_transfer_callback_t callback; /*!< Callback function. */
+ void *userData; /*!< USART callback function parameter.*/
+
+ volatile uint8_t txState; /*!< TX transfer state. */
+ volatile uint8_t rxState; /*!< RX transfer state */
+
+ uint8_t txWatermark; /*!< txFIFO watermark */
+ uint8_t rxWatermark; /*!< rxFIFO watermark */
+};
+
+/*! @brief Typedef for usart interrupt handler. */
+typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*! @brief Returns instance number for USART peripheral base address. */
+uint32_t USART_GetInstance(USART_Type *base);
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a USART instance with user configuration structure and peripheral clock.
+ *
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.
+ * Example below shows how to use this API to configure USART.
+ * @code
+ * usart_config_t usartConfig;
+ * usartConfig.baudRate_Bps = 115200U;
+ * usartConfig.parityMode = kUSART_ParityDisabled;
+ * usartConfig.stopBitCount = kUSART_OneStopBit;
+ * USART_Init(USART1, &usartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param config Pointer to user-defined configuration structure.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_InvalidArgument USART base address is not valid
+ * @retval kStatus_Success Status USART initialize succeed
+ */
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes a USART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.
+ *
+ * @param base USART peripheral base address.
+ */
+void USART_Deinit(USART_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the USART configuration structure to a default value. The default
+ * values are:
+ * usartConfig->baudRate_Bps = 115200U;
+ * usartConfig->parityMode = kUSART_ParityDisabled;
+ * usartConfig->stopBitCount = kUSART_OneStopBit;
+ * usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
+ * usartConfig->loopback = false;
+ * usartConfig->enableTx = false;
+ * usartConfig->enableRx = false;
+ *
+ * @param config Pointer to configuration structure.
+ */
+void USART_GetDefaultConfig(usart_config_t *config);
+
+/*!
+ * @brief Sets the USART instance baud rate.
+ *
+ * This function configures the USART module baud rate. This function is used to update
+ * the USART module baud rate after the USART module is initialized by the USART_Init.
+ * @code
+ * USART_SetBaudRate(USART1, 115200U, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param baudrate_Bps USART baudrate to be set.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success Set baudrate succeed.
+ * @retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source
+ *
+ * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator
+ * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting
+ * SYSCON_RTCOSCCTRL_EN bit to 1.
+ * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that
+ * 9600 can evenly divide, eg: 4800, 3200.
+ *
+ * @param base USART peripheral base address.
+ * @param baudRate_Bps USART baudrate to be set..
+ * @param enableMode32k true is 32k mode, false is normal mode.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success Set baudrate succeed.
+ * @retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Enable 9-bit data mode for USART.
+ *
+ * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user.
+ *
+ * @param base USART peripheral base address.
+ * @param enable true to enable, false to disable.
+ */
+void USART_Enable9bitMode(USART_Type *base, bool enable);
+
+/*!
+ * @brief Set the USART slave address.
+ *
+ * This function configures the address for USART module that works as slave in 9-bit data mode. When the address
+ * detection is enabled, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is
+ * considered as data frame. Once the address frame matches slave's own addresses, this slave is addressed. This
+ * address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded.
+ * To un-address a slave, just send an address frame with unmatched address.
+ *
+ * @note Any USART instance joined in the multi-slave system can work as slave. The position of the address mark is the
+ * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats.
+ *
+ * @param base USART peripheral base address.
+ * @param address USART slave address.
+ */
+static inline void USART_SetMatchAddress(USART_Type *base, uint8_t address)
+{
+ /* Configure match address. */
+ base->ADDR = (uint32_t)address;
+}
+
+/*!
+ * @brief Enable the USART match address feature.
+ *
+ * @param base USART peripheral base address.
+ * @param match true to enable match address, false to disable.
+ */
+static inline void USART_EnableMatchAddress(USART_Type *base, bool match)
+{
+ /* Configure match address enable bit. */
+ if (match)
+ {
+ base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK;
+ base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK;
+ }
+ else
+ {
+ base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK;
+ base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK;
+ }
+}
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Get USART status flags.
+ *
+ * This function get all USART status flags, the flags are returned as the logical
+ * OR value of the enumerators @ref _usart_flags. To check a specific status,
+ * compare the return value with enumerators in @ref _usart_flags.
+ * For example, to check whether the TX is empty:
+ * @code
+ * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1))
+ * {
+ * ...
+ * }
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @return USART status flags which are ORed by the enumerators in the _usart_flags.
+ */
+static inline uint32_t USART_GetStatusFlags(USART_Type *base)
+{
+ return base->FIFOSTAT;
+}
+
+/*!
+ * @brief Clear USART status flags.
+ *
+ * This function clear supported USART status flags
+ * Flags that can be cleared or set are:
+ * kUSART_TxError
+ * kUSART_RxError
+ * For example:
+ * @code
+ * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError)
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask status flags to be cleared.
+ */
+static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask)
+{
+ /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */
+ base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK);
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables USART interrupts according to the provided mask.
+ *
+ * This function enables the USART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * For example, to enable TX empty interrupt and RX full interrupt:
+ * @code
+ * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask)
+{
+ base->FIFOINTENSET = mask & 0xFUL;
+}
+
+/*!
+ * @brief Disables USART interrupts according to a provided mask.
+ *
+ * This function disables the USART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:
+ * @code
+ * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)
+{
+ base->FIFOINTENCLR = mask & 0xFUL;
+}
+
+/*!
+ * @brief Returns enabled USART interrupts.
+ *
+ * This function returns the enabled USART interrupts.
+ *
+ * @param base USART peripheral base address.
+ */
+static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base)
+{
+ return base->FIFOINTENSET;
+}
+
+/*!
+ * @brief Enable DMA for Tx
+ */
+static inline void USART_EnableTxDMA(USART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK;
+ }
+ else
+ {
+ base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK);
+ }
+}
+
+/*!
+ * @brief Enable DMA for Rx
+ */
+static inline void USART_EnableRxDMA(USART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK;
+ }
+ else
+ {
+ base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK);
+ }
+}
+
+/*!
+ * @brief Enable CTS.
+ * This function will determine whether CTS is used for flow control.
+ *
+ * @param base USART peripheral base address.
+ * @param enable Enable CTS or not, true for enable and false for disable.
+ */
+static inline void USART_EnableCTS(USART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->CFG |= USART_CFG_CTSEN_MASK;
+ }
+ else
+ {
+ base->CFG &= ~USART_CFG_CTSEN_MASK;
+ }
+}
+
+/*!
+ * @brief Continuous Clock generation.
+ * By default, SCLK is only output while data is being transmitted in synchronous mode.
+ * Enable this funciton, SCLK will run continuously in synchronous mode, allowing
+ * characters to be received on Un_RxD independently from transmission on Un_TXD).
+ *
+ * @param base USART peripheral base address.
+ * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable.
+ */
+static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->CTL |= USART_CTL_CC_MASK;
+ }
+ else
+ {
+ base->CTL &= ~USART_CTL_CC_MASK;
+ }
+}
+
+/*!
+ * @brief Enable Continuous Clock generation bit auto clear.
+ * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete
+ * character has been received. This bit is cleared at the same time.
+ *
+ * @param base USART peripheral base address.
+ * @param enable Enable auto clear or not, true for enable and false for disable.
+ */
+static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->CTL |= USART_CTL_CLRCCONRX_MASK;
+ }
+ else
+ {
+ base->CTL &= ~USART_CTL_CLRCCONRX_MASK;
+ }
+}
+
+/*!
+ * @brief Sets the rx FIFO watermark.
+ *
+ * @param base USART peripheral base address.
+ * @param water Rx FIFO watermark.
+ */
+static inline void USART_SetRxFifoWatermark(USART_Type *base, uint8_t water)
+{
+ assert(water <= (USART_FIFOTRIG_RXLVL_MASK >> USART_FIFOTRIG_RXLVL_SHIFT));
+ base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_RXLVL_MASK) | USART_FIFOTRIG_RXLVL(water);
+}
+
+/*!
+ * @brief Sets the tx FIFO watermark.
+ *
+ * @param base USART peripheral base address.
+ * @param water Tx FIFO watermark.
+ */
+static inline void USART_SetTxFifoWatermark(USART_Type *base, uint8_t water)
+{
+ assert(water <= (USART_FIFOTRIG_TXLVL_MASK >> USART_FIFOTRIG_TXLVL_SHIFT));
+ base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_TXLVL_MASK) | USART_FIFOTRIG_TXLVL(water);
+}
+/* @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Writes to the FIFOWR register.
+ *
+ * This function writes data to the txFIFO directly. The upper layer must ensure
+ * that txFIFO has space for data to write before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @param data The byte to write.
+ */
+static inline void USART_WriteByte(USART_Type *base, uint8_t data)
+{
+ base->FIFOWR = data;
+}
+
+/*!
+ * @brief Reads the FIFORD register directly.
+ *
+ * This function reads data from the rxFIFO directly. The upper layer must
+ * ensure that the rxFIFO is not empty before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @return The byte read from USART data register.
+ */
+static inline uint8_t USART_ReadByte(USART_Type *base)
+{
+ return (uint8_t)base->FIFORD;
+}
+
+/*!
+ * @brief Gets the rx FIFO data count.
+ *
+ * @param base USART peripheral base address.
+ * @return rx FIFO data count.
+ */
+static inline uint8_t USART_GetRxFifoCount(USART_Type *base)
+{
+ return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_RXLVL_MASK) >> USART_FIFOSTAT_RXLVL_SHIFT);
+}
+
+/*!
+ * @brief Gets the tx FIFO data count.
+ *
+ * @param base USART peripheral base address.
+ * @return tx FIFO data count.
+ */
+static inline uint8_t USART_GetTxFifoCount(USART_Type *base)
+{
+ return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT);
+}
+
+/*!
+ * @brief Transmit an address frame in 9-bit data mode.
+ *
+ * @param base USART peripheral base address.
+ * @param address USART slave address.
+ */
+void USART_SendAddress(USART_Type *base, uint8_t address);
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_USART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ * @retval kStatus_Success Successfully wrote all data.
+ */
+status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+ * @brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data and read data from the TX register.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
+ * @retval kStatus_USART_ParityError Noise error happened while receiving data.
+ * @retval kStatus_USART_NoiseError Framing error happened while receiving data.
+ * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * @retval kStatus_USART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length);
+
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the USART handle.
+ *
+ * This function initializes the USART handle which can be used for other USART
+ * transactional APIs. Usually, for a specified USART instance,
+ * call this API once to get the initialized handle.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ */
+status_t USART_TransferCreateHandle(USART_Type *base,
+ usart_handle_t *handle,
+ usart_transfer_callback_t callback,
+ void *userData);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback
+ * function and passes the @ref kStatus_USART_TxIdle as status parameter.
+ *
+ * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure. See #usart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific USART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * @note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize size of the ring buffer.
+ */
+void USART_TransferStartRingBuffer(USART_Type *base,
+ usart_handle_t *handle,
+ uint8_t *ringBuffer,
+ size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the length of received data in RX ring buffer.
+ *
+ * @param handle USART handle pointer.
+ * @return Length of received data in RX ring buffer.
+ */
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are still not sent out.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been sent out to bus.
+ *
+ * This function gets the number of bytes that have been sent out to bus by interrupt method.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the USART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the USART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure, see #usart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * @retval kStatus_USART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+ usart_handle_t *handle,
+ usart_transfer_t *xfer,
+ size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief USART IRQ handle function.
+ *
+ * This function handles the USART transmit and receive IRQ request.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_USART_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm LinkServer Debug.launch b/minimal-examples/embedded/rt595/hello_world/project/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm LinkServer Debug.launch
new file mode 100644
index 000000000..e96bb3356
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm LinkServer Debug.launch
@@ -0,0 +1,95 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.crt.dsfdebug.crtmcu.launchType">
+ <stringAttribute key=".gdbinit" value=""/>
+ <booleanAttribute key="attach" value="false"/>
+ <stringAttribute key="bootrom.stall" value="0x50002034"/>
+ <stringAttribute key="com.crt.ctrlcenter.OFSemuDetails" value="LinkServer"/>
+ <booleanAttribute key="com.crt.ctrlcenter.crtInit" value="true"/>
+ <stringAttribute key="com.crt.ctrlcenter.currentWireType" value="SWD"/>
+ <booleanAttribute key="com.crt.ctrlcenter.mainBreakIsHardware" value="true"/>
+ <stringAttribute key="com.crt.ctrlcenter.serialNumber" value="LinkServerNXP SemiconductorsLPC-LINK2 CMSIS-DAP V5.361FRAQBQAR"/>
+ <mapAttribute key="com.crt.ctrlcenter.symbolsGroupSettings"/>
+ <intAttribute key="com.crt.ctrlcenter.version" value="6"/>
+ <stringAttribute key="com.nxp.mcuxpresso.flash.base.address" value="0x8000000"/>
+ <booleanAttribute key="com.nxp.mcuxpresso.flash.clear.console" value="true"/>
+ <booleanAttribute key="com.nxp.mcuxpresso.flash.confirm" value="false"/>
+ <stringAttribute key="com.nxp.mcuxpresso.flash.erase.algorithm" value="Mass erase"/>
+ <stringAttribute key="com.nxp.mcuxpresso.flash.executable" value="axf"/>
+ <stringAttribute key="com.nxp.mcuxpresso.flash.program.action" value="Program"/>
+ <booleanAttribute key="com.nxp.mcuxpresso.flash.reset.target" value="true"/>
+ <stringAttribute key="com.nxp.mcuxpresso.ide.probe.manufacturer" value="NXP Semiconductors"/>
+ <stringAttribute key="com.nxp.mcuxpresso.ide.probe.name" value="LPC-LINK2 CMSIS-DAP V5.361"/>
+ <stringAttribute key="com.nxp.mcuxpresso.ide.probe.type" value="LinkServer"/>
+ <stringAttribute key="debug.level" value="2"/>
+ <stringAttribute key="emu.speed" value=""/>
+ <stringAttribute key="flash.driver.reset" value=""/>
+ <booleanAttribute key="internal.attach.slave" value="false"/>
+ <booleanAttribute key="internal.cache" value="false"/>
+ <stringAttribute key="internal.connect.script" value="RT500_connect.scp"/>
+ <stringAttribute key="internal.core.index" value=""/>
+ <booleanAttribute key="internal.has_swo" value="true"/>
+ <booleanAttribute key="internal.multi.swd" value="true"/>
+ <stringAttribute key="internal.prelaunch.command" value=""/>
+ <stringAttribute key="internal.reset.script" value=""/>
+ <stringAttribute key="internal.resethandling" value=""/>
+ <stringAttribute key="internal.semihost" value="On"/>
+ <stringAttribute key="internal.wirespeed" value=""/>
+ <stringAttribute key="internal.wiretype" value="SWD"/>
+ <stringAttribute key="launch.config.handler" value="com.crt.ctrlcenter.launch.CRTLaunchConfigHandler"/>
+ <booleanAttribute key="mem.access" value="false"/>
+ <stringAttribute key="misc.options" value=""/>
+ <stringAttribute key="ondisconnect" value="cont"/>
+ <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="0"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set non-stop on set pagination off set mi-async set remotetimeout 60000 ##target_extended_remote## set mem inaccessible-by-default ${mem.access} mon ondisconnect ${ondisconnect} set arm force-mode thumb ${load}"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value="${run}"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+ <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+ <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+ <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+ <booleanAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_ON_FORK" value="false"/>
+ <booleanAttribute key="org.eclipse.cdt.dsf.gdb.EXTERNAL_CONSOLE" value="false"/>
+ <stringAttribute key="org.eclipse.cdt.dsf.gdb.GDB_INIT" value=""/>
+ <booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="true"/>
+ <booleanAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE" value="false"/>
+ <stringAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE_MODE" value="UseSoftTrace"/>
+ <stringAttribute key="org.eclipse.cdt.dsf.gdb.TRACEPOINT_MODE" value="TP_NORMAL_ONLY"/>
+ <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+ <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+ <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="gdb"/>
+ <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+ <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm.axf"/>
+ <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm"/>
+ <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+ <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.crt.advproject.config.exe.debug.1881597443"/>
+ <booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="false"/>
+ <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+ <listEntry value="/evkmimxrt595_dev_composite_cdc_vcom_cdc_vcom_bm"/>
+ </listAttribute>
+ <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+ <listEntry value="4"/>
+ </listAttribute>
+ <mapAttribute key="org.eclipse.debug.core.preferred_launchers">
+ <mapEntry key="[debug]" value="com.nxp.mcuxpresso.core.debug.support.linkserver.launch.LinkServerGdbLaunch"/>
+ </mapAttribute>
+ <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><memoryBlockExpressionList context="reserved-for-future-use"/>"/>
+ <stringAttribute key="process_factory_id" value="com.nxp.mcuxpresso.core.debug.override.MCXProcessFactory"/>
+ <booleanAttribute key="redlink.disable.preconnect.script" value="false"/>
+ <booleanAttribute key="redlink.enable.flashhashing" value="true"/>
+ <booleanAttribute key="redlink.enable.rangestepping" value="true"/>
+ <stringAttribute key="run" value="cont"/>
+ <booleanAttribute key="vector.catch" value="false"/>
+</launchConfiguration>
diff --git a/minimal-examples/embedded/rt595/hello_world/project/flash_config/flash_config.c b/minimal-examples/embedded/rt595/hello_world/project/flash_config/flash_config.c
new file mode 100644
index 000000000..e066f6acc
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/flash_config/flash_config.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ * SPDXLicense-Identifier: BSD-3-Clause
+ */
+#include "flash_config.h"
+#include "board.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flash_config"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(BOOT_HEADER_ENABLE) && (BOOT_HEADER_ENABLE == 1)
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".flash_conf"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".flash_conf"
+#endif
+
+const flexspi_nor_config_t flash_config = {
+ .memConfig =
+ {
+ .tag = FLEXSPI_CFG_BLK_TAG,
+ .version = FLEXSPI_CFG_BLK_VERSION,
+ .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
+ .csHoldTime = 3,
+ .csSetupTime = 3,
+ .deviceModeCfgEnable = 1,
+ .deviceModeType = kDeviceConfigCmdType_Spi2Xpi,
+ .waitTimeCfgCommands = 1,
+ .deviceModeSeq =
+ {
+ .seqNum = 1,
+ .seqId = 6, /* See Lookup table for more details */
+ .reserved = 0,
+ },
+ .deviceModeArg = 2, /* Enable OPI DDR mode */
+ .controllerMiscOption =
+ (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DdrModeEnable),
+ .deviceType = kFlexSpiDeviceType_SerialNOR,
+ .sflashPadType = kSerialFlash_8Pads,
+ .serialClkFreq = kFlexSpiSerialClk_80MHz,
+ .sflashA1Size = 64ul * 1024u * 1024u,
+ .dataValidTime =
+ {
+ [0] = {.time_100ps = 16},
+ },
+ .busyOffset = 0u,
+ .busyBitPolarity = 0u,
+ .lookupTable =
+ {
+ /* Read */
+ [0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xEE, CMD_DDR, FLEXSPI_8PAD, 0x11),
+ [1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x04),
+ [2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0x00),
+
+ /* Read Status */
+ [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
+
+ /* Write Enable */
+ [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP_EXE, FLEXSPI_1PAD, 0x00),
+
+ /* Enable OPI DDR mode */
+ [4 * 6 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x72, CMD_SDR, FLEXSPI_1PAD, 0x00),
+ [4 * 6 + 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, CMD_SDR, FLEXSPI_1PAD, 0x00),
+ [4 * 6 + 2] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, WRITE_SDR, FLEXSPI_1PAD, 0x01),
+ },
+ },
+ .pageSize = 256u,
+ .sectorSize = 4u * 1024u,
+ .blockSize = 64u * 1024u,
+ .flashStateCtx = 0x07008200u,
+};
+#endif /* BOOT_HEADER_ENABLE */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/flash_config/flash_config.h b/minimal-examples/embedded/rt595/hello_world/project/flash_config/flash_config.h
new file mode 100644
index 000000000..14c6a913a
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/flash_config/flash_config.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#ifndef __FLASH_CONFIG_H__
+#define __FLASH_CONFIG_H__
+#include <stdint.h>
+#include "fsl_iap.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FLASH_CONFIG driver version 2.0.0. */
+#define FSL_FLASH_CONFIG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*******************************************************************************
+ * Definition
+ ******************************************************************************/
+
+/* FLEXSPI memory config block related defintions */
+#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) /* ascii "FCFB" Big Endian */
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) /* V1.4.0 */
+
+/* !@brief FLEXSPI clock configuration - When clock source is PLL */
+enum
+{
+ kFlexSpiSerialClk_30MHz = 1,
+ kFlexSpiSerialClk_50MHz = 2,
+ kFlexSpiSerialClk_60MHz = 3,
+ kFlexSpiSerialClk_80MHz = 4,
+ kFlexSpiSerialClk_100MHz = 5,
+ kFlexSpiSerialClk_120MHz = 6,
+ kFlexSpiSerialClk_133MHz = 7,
+ kFlexSpiSerialClk_166MHz = 8,
+ kFlexSpiSerialClk_200MHz = 9,
+};
+
+/* !@brief LUT instructions supported by FLEXSPI */
+#define CMD_SDR 0x01
+#define CMD_DDR 0x21
+#define RADDR_SDR 0x02
+#define RADDR_DDR 0x22
+#define CADDR_SDR 0x03
+#define CADDR_DDR 0x23
+#define MODE1_SDR 0x04
+#define MODE1_DDR 0x24
+#define MODE2_SDR 0x05
+#define MODE2_DDR 0x25
+#define MODE4_SDR 0x06
+#define MODE4_DDR 0x26
+#define MODE8_SDR 0x07
+#define MODE8_DDR 0x27
+#define WRITE_SDR 0x08
+#define WRITE_DDR 0x28
+#define READ_SDR 0x09
+#define READ_DDR 0x29
+#define LEARN_SDR 0x0A
+#define LEARN_DDR 0x2A
+#define DATSZ_SDR 0x0B
+#define DATSZ_DDR 0x2B
+#define DUMMY_SDR 0x0C
+#define DUMMY_DDR 0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS 0x1F
+#define STOP_EXE 0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
+ (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+ FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+/* !@brief FlexSPI Read Sample Clock Source definition */
+typedef enum _FlashReadSampleClkSource
+{
+ kFlexSPIReadSampleClk_LoopbackInternally = 0,
+ kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
+ kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
+ kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+/* !@brief Misc feature bit definitions */
+enum
+{
+ kFlexSpiMiscOffset_DiffClkEnable = 0, /* !< Bit for Differential clock enable */
+ kFlexSpiMiscOffset_ParallelEnable = 2, /* !< Bit for Parallel mode enable */
+ kFlexSpiMiscOffset_WordAddressableEnable = 3, /* !< Bit for Word Addressable enable */
+ kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, /* !< Bit for Safe Configuration Frequency enable */
+ kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, /* !< Bit for Pad setting override enable */
+ kFlexSpiMiscOffset_DdrModeEnable = 6, /* !< Bit for DDR clock confiuration indication. */
+ kFlexSpiMiscOffset_UseValidTimeForAllFreq = 7, /* !< Bit for DLLCR settings under all modes */
+};
+
+#endif
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/composite.c b/minimal-examples/embedded/rt595/hello_world/project/source/composite.c
new file mode 100644
index 000000000..a59dec250
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/source/composite.c
@@ -0,0 +1,379 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "usb_device_config.h"
+#include "usb.h"
+#include "usb_device.h"
+
+#include "usb_device_class.h"
+#include "usb_device_cdc_acm.h"
+#include "usb_device_ch9.h"
+#include "usb_device_descriptor.h"
+
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "composite.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#if (defined(FSL_FEATURE_SOC_SYSMPU_COUNT) && (FSL_FEATURE_SOC_SYSMPU_COUNT > 0U))
+#include "fsl_sysmpu.h"
+#endif /* FSL_FEATURE_SOC_SYSMPU_COUNT */
+
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+#include "usb_phy.h"
+#endif
+
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+void BOARD_InitHardware(void);
+void USB_DeviceClockInit(void);
+void USB_DeviceIsrEnable(void);
+#if USB_DEVICE_CONFIG_USE_TASK
+void USB_DeviceTaskFn(void *deviceHandle);
+#endif
+/*!
+ * @brief USB device callback function.
+ *
+ * This function handles the usb device specific requests.
+ *
+ * @param handle The USB device handle.
+ * @param event The USB device event type.
+ * @param param The parameter of the device specific request.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceCallback(usb_device_handle handle, uint32_t event, void *param);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Composite device structure. */
+usb_device_composite_struct_t g_composite;
+extern usb_device_class_struct_t g_UsbDeviceCdcVcomConfig[2];
+
+/* USB device class information */
+usb_device_class_config_struct_t g_CompositeClassConfig[2] = {{
+ USB_DeviceCdcVcomCallback,
+ (class_handle_t)NULL,
+ &g_UsbDeviceCdcVcomConfig[0],
+ },
+ {
+ USB_DeviceCdcVcomCallback,
+ (class_handle_t)NULL,
+ &g_UsbDeviceCdcVcomConfig[1],
+ }};
+
+/* USB device class configuration information */
+usb_device_class_config_list_struct_t g_UsbDeviceCompositeConfigList = {
+ g_CompositeClassConfig,
+ USB_DeviceCallback,
+ 2,
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void USB0_IRQHandler(void)
+{
+ USB_DeviceLpcIp3511IsrFunction(g_composite.deviceHandle);
+}
+
+void USB_DeviceClockInit(void)
+{
+ uint8_t usbClockDiv = 1;
+ uint32_t usbClockFreq;
+ usb_phy_config_struct_t phyConfig = {
+ BOARD_USB_PHY_D_CAL,
+ BOARD_USB_PHY_TXCAL45DP,
+ BOARD_USB_PHY_TXCAL45DM,
+ };
+
+ /* Make sure USDHC ram buffer and usb1 phy has power up */
+ POWER_DisablePD(kPDRUNCFG_APD_USBHS_SRAM);
+ POWER_DisablePD(kPDRUNCFG_PPD_USBHS_SRAM);
+ POWER_DisablePD(kPDRUNCFG_LP_HSPAD_FSPI0_VDET);
+ POWER_ApplyPD();
+
+ RESET_PeripheralReset(kUSBHS_PHY_RST_SHIFT_RSTn);
+ RESET_PeripheralReset(kUSBHS_DEVICE_RST_SHIFT_RSTn);
+ RESET_PeripheralReset(kUSBHS_HOST_RST_SHIFT_RSTn);
+ RESET_PeripheralReset(kUSBHS_SRAM_RST_SHIFT_RSTn);
+
+ /* enable usb ip clock */
+ CLOCK_EnableUsbHs0DeviceClock(kOSC_CLK_to_USB_CLK, usbClockDiv);
+ /* save usb ip clock freq*/
+ usbClockFreq = g_xtalFreq / usbClockDiv;
+ CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 4);
+ /* enable usb ram clock */
+ CLOCK_EnableClock(kCLOCK_UsbhsSram);
+ /* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */
+ CLOCK_EnableUsbHs0PhyPllClock(kOSC_CLK_to_USB_CLK, usbClockFreq);
+
+ /* USB PHY initialization */
+ USB_EhciPhyInit(CONTROLLER_ID, BOARD_XTAL_SYS_CLK_HZ, &phyConfig);
+
+#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM)
+ for (int i = 0; i < FSL_FEATURE_USBHSD_USB_RAM; i++)
+ {
+ ((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)[i] = 0x00U;
+ }
+#endif
+
+ /* the following code should run after phy initialization and should wait some microseconds to make sure utmi clock
+ * valid */
+ /* enable usb1 host clock */
+ CLOCK_EnableClock(kCLOCK_UsbhsHost);
+ /* Wait until host_needclk de-asserts */
+ while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK)
+ {
+ __ASM("nop");
+ }
+ /*According to reference mannual, device mode setting has to be set by access usb host register */
+ USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
+ /* disable usb1 host clock */
+ CLOCK_DisableClock(kCLOCK_UsbhsHost);
+}
+
+void USB_DeviceIsrEnable(void)
+{
+ uint8_t irqNumber;
+
+ uint8_t usbDeviceIP3511Irq[] = USBHSD_IRQS;
+ irqNumber = usbDeviceIP3511Irq[CONTROLLER_ID - kUSB_ControllerLpcIp3511Hs0];
+
+ /* Install isr, set priority, and enable IRQ. */
+ NVIC_SetPriority((IRQn_Type)irqNumber, USB_DEVICE_INTERRUPT_PRIORITY);
+ EnableIRQ((IRQn_Type)irqNumber);
+}
+
+#if USB_DEVICE_CONFIG_USE_TASK
+void USB_DeviceTaskFn(void *deviceHandle)
+{
+ USB_DeviceLpcIp3511TaskFunction(deviceHandle);
+}
+#endif
+/*!
+ * @brief USB device callback function.
+ *
+ * This function handles the usb device specific requests.
+ *
+ * @param handle The USB device handle.
+ * @param event The USB device event type.
+ * @param param The parameter of the device specific request.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceCallback(usb_device_handle handle, uint32_t event, void *param)
+{
+ usb_status_t error = kStatus_USB_InvalidRequest;
+ uint16_t *temp16 = (uint16_t *)param;
+ uint8_t *temp8 = (uint8_t *)param;
+
+ switch (event)
+ {
+ case kUSB_DeviceEventBusReset:
+ {
+ g_composite.attach = 0;
+ g_composite.currentConfiguration = 0U;
+ error = kStatus_USB_Success;
+ for (uint8_t i = 0; i < USB_DEVICE_CONFIG_CDC_ACM; i++)
+ {
+ g_composite.cdcVcom[i].recvSize = 0;
+ g_composite.cdcVcom[i].sendSize = 0;
+ g_composite.cdcVcom[i].attach = 0;
+ }
+#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)) || \
+ (defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+ /* Get USB speed to configure the device, including max packet size and interval of the endpoints. */
+ if (kStatus_USB_Success == USB_DeviceClassGetSpeed(CONTROLLER_ID, &g_composite.speed))
+ {
+ USB_DeviceSetSpeed(handle, g_composite.speed);
+ }
+#endif
+ }
+ break;
+ case kUSB_DeviceEventSetConfiguration:
+ if (0U == (*temp8))
+ {
+ g_composite.attach = 0U;
+ g_composite.currentConfiguration = 0U;
+ error = kStatus_USB_Success;
+ for (uint8_t i = 0; i < USB_DEVICE_CONFIG_CDC_ACM; i++)
+ {
+ g_composite.cdcVcom[i].recvSize = 0;
+ g_composite.cdcVcom[i].sendSize = 0;
+ g_composite.cdcVcom[i].attach = 0;
+ }
+ }
+ else if (USB_COMPOSITE_CONFIGURE_INDEX == (*temp8))
+ {
+ g_composite.attach = 1;
+ USB_DeviceCdcVcomSetConfigure(g_composite.cdcVcom[0].cdcAcmHandle, *temp8);
+ g_composite.currentConfiguration = *temp8;
+ error = kStatus_USB_Success;
+ }
+ else
+ {
+ /* no action, return kStatus_USB_InvalidRequest */
+ }
+ break;
+ case kUSB_DeviceEventSetInterface:
+ if (g_composite.attach)
+ {
+ uint8_t interface = (uint8_t)((*temp16 & 0xFF00U) >> 0x08U);
+ uint8_t alternateSetting = (uint8_t)(*temp16 & 0x00FFU);
+
+ if (interface == USB_CDC_VCOM_CIC_INTERFACE_INDEX)
+ {
+ if (alternateSetting < USB_CDC_VCOM_CIC_INTERFACE_ALTERNATE_COUNT)
+ {
+ g_composite.currentInterfaceAlternateSetting[interface] = alternateSetting;
+ error = kStatus_USB_Success;
+ }
+ }
+ else if (interface == USB_CDC_VCOM_DIC_INTERFACE_INDEX)
+ {
+ if (alternateSetting < USB_CDC_VCOM_DIC_INTERFACE_ALTERNATE_COUNT)
+ {
+ g_composite.currentInterfaceAlternateSetting[interface] = alternateSetting;
+ error = kStatus_USB_Success;
+ }
+ }
+ else if (interface == USB_CDC_VCOM_CIC_INTERFACE_INDEX_2)
+ {
+ if (alternateSetting < USB_CDC_VCOM_CIC_INTERFACE_2_ALTERNATE_COUNT)
+ {
+ g_composite.currentInterfaceAlternateSetting[interface] = alternateSetting;
+ error = kStatus_USB_Success;
+ }
+ }
+ else if (interface == USB_CDC_VCOM_DIC_INTERFACE_INDEX_2)
+ {
+ if (alternateSetting < USB_CDC_VCOM_DIC_INTERFACE_2_ALTERNATE_COUNT)
+ {
+ g_composite.currentInterfaceAlternateSetting[interface] = alternateSetting;
+ error = kStatus_USB_Success;
+ }
+ }
+ else
+ {
+ /* no action, return kStatus_USB_InvalidRequest */
+ }
+ }
+ break;
+ case kUSB_DeviceEventGetConfiguration:
+ if (param)
+ {
+ *temp8 = g_composite.currentConfiguration;
+ error = kStatus_USB_Success;
+ }
+ break;
+ case kUSB_DeviceEventGetInterface:
+ if (param)
+ {
+ uint8_t interface = (uint8_t)((*temp16 & 0xFF00U) >> 0x08U);
+ if (interface < USB_INTERFACE_COUNT)
+ {
+ *temp16 = (*temp16 & 0xFF00U) | g_composite.currentInterfaceAlternateSetting[interface];
+ error = kStatus_USB_Success;
+ }
+ }
+ break;
+ case kUSB_DeviceEventGetDeviceDescriptor:
+ if (param)
+ {
+ error = USB_DeviceGetDeviceDescriptor(handle, (usb_device_get_device_descriptor_struct_t *)param);
+ }
+ break;
+ case kUSB_DeviceEventGetConfigurationDescriptor:
+ if (param)
+ {
+ error = USB_DeviceGetConfigurationDescriptor(handle,
+ (usb_device_get_configuration_descriptor_struct_t *)param);
+ }
+ break;
+#if (defined(USB_DEVICE_CONFIG_CV_TEST) && (USB_DEVICE_CONFIG_CV_TEST > 0U))
+ case kUSB_DeviceEventGetDeviceQualifierDescriptor:
+ if (param)
+ {
+ /* Get device descriptor request */
+ error = USB_DeviceGetDeviceQualifierDescriptor(
+ handle, (usb_device_get_device_qualifier_descriptor_struct_t *)param);
+ }
+ break;
+#endif
+ case kUSB_DeviceEventGetStringDescriptor:
+ if (param)
+ {
+ error = USB_DeviceGetStringDescriptor(handle, (usb_device_get_string_descriptor_struct_t *)param);
+ }
+ break;
+ default:
+ break;
+ }
+
+ return error;
+}
+
+/*!
+ * @brief Application initialization function.
+ *
+ * This function initializes the application.
+ *
+ * @return None.
+ */
+void USB_DeviceApplicationInit(void)
+{
+ USB_DeviceClockInit();
+#if (defined(FSL_FEATURE_SOC_SYSMPU_COUNT) && (FSL_FEATURE_SOC_SYSMPU_COUNT > 0U))
+ SYSMPU_Enable(SYSMPU, 0);
+#endif /* FSL_FEATURE_SOC_SYSMPU_COUNT */
+
+ g_composite.speed = USB_SPEED_FULL;
+ g_composite.attach = 0;
+ for (uint8_t i = 0; i < USB_DEVICE_CONFIG_CDC_ACM; i++)
+ {
+ g_composite.cdcVcom[i].cdcAcmHandle = (class_handle_t)NULL;
+ }
+ g_composite.deviceHandle = NULL;
+
+ if (kStatus_USB_Success !=
+ USB_DeviceClassInit(CONTROLLER_ID, &g_UsbDeviceCompositeConfigList, &g_composite.deviceHandle))
+ {
+ usb_echo("USB device composite demo init failed\r\n");
+ return;
+ }
+ else
+ {
+ usb_echo("USB device composite demo\r\n");
+ /*Init classhandle in cdc instance*/
+ for (uint8_t i = 0; i < USB_DEVICE_CONFIG_CDC_ACM; i++)
+ {
+ g_composite.cdcVcom[i].cdcAcmHandle = g_UsbDeviceCompositeConfigList.config[i].classHandle;
+ }
+ USB_DeviceCdcVcomInit(&g_composite);
+ }
+
+ USB_DeviceIsrEnable();
+
+ /*Add one delay here to make the DP pull down long enough to allow host to detect the previous disconnection.*/
+ SDK_DelayAtLeastUs(5000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ USB_DeviceRun(g_composite.deviceHandle);
+}
+
+
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/composite.h b/minimal-examples/embedded/rt595/hello_world/project/source/composite.h
new file mode 100644
index 000000000..6f45b82b3
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/source/composite.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _USB_DEVICE_COMPOSITE_H_
+#define _USB_DEVICE_COMPOSITE_H_ 1
+
+#include "virtual_com.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0)
+#define CONTROLLER_ID kUSB_ControllerEhci0
+#endif
+#if defined(USB_DEVICE_CONFIG_KHCI) && (USB_DEVICE_CONFIG_KHCI > 0)
+#define CONTROLLER_ID kUSB_ControllerKhci0
+#endif
+#if defined(USB_DEVICE_CONFIG_LPCIP3511FS) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)
+#define CONTROLLER_ID kUSB_ControllerLpcIp3511Fs0
+#endif
+#if defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)
+#define CONTROLLER_ID kUSB_ControllerLpcIp3511Hs0
+#endif
+
+#define USB_DEVICE_INTERRUPT_PRIORITY (3U)
+typedef struct _usb_device_composite_struct
+{
+ usb_device_handle deviceHandle; /* USB device handle. */
+ usb_cdc_vcom_struct_t cdcVcom[USB_DEVICE_CONFIG_CDC_ACM]; /* CDC virtual com device structure. */
+ uint8_t speed; /* Speed of USB device. USB_SPEED_FULL/USB_SPEED_LOW/USB_SPEED_HIGH. */
+ uint8_t attach; /* A flag to indicate whether a usb device is attached. 1: attached, 0: not attached */
+ uint8_t currentConfiguration; /* Current configuration value. */
+ uint8_t
+ currentInterfaceAlternateSetting[USB_INTERFACE_COUNT]; /* Current alternate setting value for each interface. */
+} usb_device_composite_struct_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+/*!
+ * @brief CDC class specific callback function.
+ *
+ * This function handles the CDC class specific requests.
+ *
+ * @param handle The CDC ACM class handle.
+ * @param event The CDC ACM class event type.
+ * @param param The parameter of the class specific request.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceCdcVcomCallback(class_handle_t handle, uint32_t event, void *param);
+
+/*!
+ * @brief Virtual COM device set configuration function.
+ *
+ * This function sets configuration for CDC class.
+ *
+ * @param handle The CDC ACM class handle.
+ * @param configure The CDC ACM class configure index.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceCdcVcomSetConfigure(class_handle_t handle, uint8_t configure);
+/*!
+ * @brief Virtual COM device initialization function.
+ *
+ * This function initializes the device with the composite device class information.
+ *
+ * @param deviceComposite The pointer to the composite device structure.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceCdcVcomInit(usb_device_composite_struct_t *deviceComposite);
+/*!
+ * @brief Application task function.
+ *
+ * This function runs the task for application.
+ *
+ * @return None.
+ */
+extern void USB_DeviceCdcVcomTask(void);
+
+#endif /* _USB_DEVICE_COMPOSITE_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/semihost_hardfault.c b/minimal-examples/embedded/rt595/hello_world/project/source/semihost_hardfault.c
new file mode 100644
index 000000000..945cc5bc4
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/source/semihost_hardfault.c
@@ -0,0 +1,98 @@
+// ****************************************************************************
+// semihost_hardfault.c
+// - Provides hard fault handler to allow semihosting code not
+// to hang application when debugger not connected.
+//
+// ****************************************************************************
+// Copyright 2017-2021 NXP
+// All rights reserved.
+//
+// NXP Confidential. This software is owned or controlled by NXP and may only be
+// used strictly in accordance with the applicable license terms.
+//
+// By expressly accepting such terms or by downloading, installing, activating
+// and/or otherwise using the software, you are agreeing that you have read, and
+// that you agree to comply with and are bound by, such license terms.
+//
+// If you do not agree to be bound by the applicable license terms, then you may not
+// retain, install, activate or otherwise use the software.
+// ****************************************************************************
+//
+// ===== DESCRIPTION =====
+//
+// One of the issues with applications that make use of semihosting operations
+// (such as printf calls) is that the code will not execute correctly when the
+// debugger is not connected. Generally this will show up with the application
+// appearing to just hang. This may include the application running from reset
+// or powering up the board (with the application already in FLASH), and also
+// as the application failing to continue to execute after a debug session is
+// terminated.
+//
+// The problem here is that the "bottom layer" of the semihosted variants of
+// the C library, semihosting is implemented by a "BKPT 0xAB" instruction.
+// When the debug tools are not connected, this instruction triggers a hard
+// fault - and the default hard fault handler within an application will
+// typically just contains an infinite loop - causing the application to
+// appear to have hang when no debugger is connected.
+//
+// The below code provides an example hard fault handler which instead looks
+// to see what the instruction that caused the hard fault was - and if it
+// was a "BKPT 0xAB", then it instead returns back to the user application.
+//
+// In most cases this will allow applications containing semihosting
+// operations to execute (to some degree) when the debugger is not connected.
+//
+// == NOTE ==
+//
+// Correct execution of the application containing semihosted operations
+// which are vectored onto this hard fault handler cannot be guaranteed. This
+// is because the handler may not return data or return codes that the higher
+// level C library code or application code expects. This hard fault handler
+// is meant as a development aid, and it is not recommended to leave
+// semihosted code in a production build of your application!
+//
+// ****************************************************************************
+
+// Allow handler to be removed by setting a define (via command line)
+#if !defined (__SEMIHOST_HARDFAULT_DISABLE)
+
+__attribute__((naked))
+void HardFault_Handler(void){
+ __asm( ".syntax unified\n"
+ // Check which stack is in use
+ "MOVS R0, #4 \n"
+ "MOV R1, LR \n"
+ "TST R0, R1 \n"
+ "BEQ _MSP \n"
+ "MRS R0, PSP \n"
+ "B _process \n"
+ "_MSP: \n"
+ "MRS R0, MSP \n"
+ // Load the instruction that triggered hard fault
+ "_process: \n"
+ "LDR R1,[R0,#24] \n"
+ "LDRH R2,[r1] \n"
+ // Semihosting instruction is "BKPT 0xAB" (0xBEAB)
+ "LDR R3,=0xBEAB \n"
+ "CMP R2,R3 \n"
+ "BEQ _semihost_return \n"
+ // Wasn't semihosting instruction so enter infinite loop
+ "B . \n"
+ // Was semihosting instruction, so adjust location to
+ // return to by 1 instruction (2 bytes), then exit function
+ "_semihost_return: \n"
+ "ADDS R1,#2 \n"
+ "STR R1,[R0,#24] \n"
+ // Set a return value from semihosting operation.
+ // 32 is slightly arbitrary, but appears to allow most
+ // C Library IO functions sitting on top of semihosting to
+ // continue to operate to some degree
+ "MOVS R1,#32 \n"
+ "STR R1,[ R0,#0 ] \n" // R0 is at location 0 on stack
+ // Return from hard fault handler to application
+ "BX LR \n"
+ ".syntax divided\n") ;
+}
+
+#endif
+
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/sspc/binance-ss.c b/minimal-examples/embedded/rt595/hello_world/project/source/sspc/binance-ss.c
new file mode 100644
index 000000000..747e513b2
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/source/sspc/binance-ss.c
@@ -0,0 +1,223 @@
+/*
+ * rt595-sspc-binance
+ *
+ * Written in 2010-2021 by Andy Green <andy@warmcat.com>
+ * Kutoga <kutoga@user.github.invalid>
+ *
+ * This file is made available under the Creative Commons CC0 1.0
+ * Universal Public Domain Dedication.
+ *
+ *
+ * This is a version of minimal-secure-streams-binance that uses a custom
+ * SS Serialization transport.
+ */
+
+#include "private.h"
+#include <string.h>
+#include <signal.h>
+#include <ctype.h>
+
+extern uint64_t
+get_us_timeofday(void);
+
+typedef struct range {
+ uint64_t sum;
+ uint64_t lowest;
+ uint64_t highest;
+
+ unsigned int samples;
+} range_t;
+
+LWS_SS_USER_TYPEDEF
+ uint64_t data_in;
+ uint64_t data_in_last_sec;
+
+ lws_sorted_usec_list_t sul_hz; /* 1hz summary dump */
+ char msgbuf[8192];
+ size_t msg_len;
+
+ range_t e_lat_range;
+ range_t price_range;
+} binance_t;
+
+
+/*
+ * Rest of the file is Binance application SS processing (UNCHANGED from
+ * minimal-secure-streams-binance)
+ */
+
+static void
+range_reset(range_t *r)
+{
+ r->sum = r->highest = 0;
+ r->lowest = 999999999999ull;
+ r->samples = 0;
+}
+
+static uint64_t
+pennies(const char *s)
+{
+ uint64_t price = (uint64_t)atoll(s) * 100;
+
+ s = strchr(s, '.');
+
+ if (s && isdigit(s[1]) && isdigit(s[2]))
+ price = price + (uint64_t)((10 * (s[1] - '0')) + (s[2] - '0'));
+
+ return price;
+}
+
+static void
+sul_hz_cb(lws_sorted_usec_list_t *sul)
+{
+ binance_t *bin = lws_container_of(sul, binance_t, sul_hz);
+
+ /*
+ * We are called once a second to dump statistics on the connection
+ */
+
+ lws_sul_schedule(lws_ss_get_context(bin->ss), 0, &bin->sul_hz,
+ sul_hz_cb, LWS_US_PER_SEC);
+
+ if (bin->price_range.samples)
+ lwsl_user("%s: price: min: %llu¢, max: %llu¢, avg: %llu¢, "
+ "(%d prices/s)\n", __func__,
+ (unsigned long long)bin->price_range.lowest,
+ (unsigned long long)bin->price_range.highest,
+ (unsigned long long)(bin->price_range.sum /
+ bin->price_range.samples),
+ bin->price_range.samples);
+ if (bin->e_lat_range.samples)
+ lwsl_user("%s: elatency: min: %lums, max: %lums, "
+ "avg: %lums, (%d msg/s, %lu KiBytes/s SS RX)\n",
+ __func__,
+ (unsigned long)(bin->e_lat_range.lowest / 1000),
+ (unsigned long)(bin->e_lat_range.highest / 1000),
+ (unsigned long)((bin->e_lat_range.sum /
+ bin->e_lat_range.samples) / 1000),
+ bin->e_lat_range.samples,
+ (unsigned long)((bin->data_in -
+ bin->data_in_last_sec) / 1024));
+
+ range_reset(&bin->e_lat_range);
+ range_reset(&bin->price_range);
+
+ bin->data_in_last_sec = bin->data_in;
+}
+
+static lws_ss_state_return_t
+binance_rx(void *userobj, const uint8_t *in, size_t len, int flags)
+{
+ binance_t *bin = (binance_t *)userobj;
+ uint64_t latency_us, now_us, l1;
+ const uint8_t *msg;
+ char numbuf[20];
+ uint64_t price;
+ const char *p;
+ size_t alen;
+
+ bin->data_in += len;
+
+ msg = bin->msgbuf;
+ if (flags & LWSSS_FLAG_SOM) {
+ bin->msg_len = 0;
+ if (flags & LWSSS_FLAG_EOM) {
+ msg = in;
+ bin->msg_len = len;
+ goto handle;
+ }
+ }
+
+ if (bin->msg_len + len < sizeof(bin->msgbuf)) {
+ memcpy(bin->msgbuf + bin->msg_len, in, len);
+ bin->msg_len += len;
+ }
+
+ /* assemble a full message */
+ if (!(flags & LWSSS_FLAG_EOM))
+ return LWSSSSRET_OK;
+
+
+handle:
+ //lwsl_notice("%s: chunk len %d\n", __func__, (int)len);
+
+ now_us = (uint64_t)get_us_timeofday();
+
+ p = lws_json_simple_find(msg, bin->msg_len, "\"depthUpdate\"",
+ &alen);
+ if (!p)
+ return LWSSSSRET_OK;
+
+ p = lws_json_simple_find(msg, bin->msg_len, "\"E\":", &alen);
+ if (!p) {
+ lwsl_err("%s: no E JSON\n", __func__);
+ return LWSSSSRET_OK;
+ }
+
+ lws_strnncpy(numbuf, p, alen, sizeof(numbuf));
+ l1 = ((uint64_t)atoll(numbuf) * LWS_US_PER_MS);
+ latency_us = now_us - l1;
+
+// lwsl_notice("%s: now_us adjusted %llu, %llu, %llu, %s\n", __func__, tm->us_unixtime_peer, now_us, l1, numbuf);
+
+
+ if (latency_us < bin->e_lat_range.lowest)
+ bin->e_lat_range.lowest = latency_us;
+ if (latency_us > bin->e_lat_range.highest)
+ bin->e_lat_range.highest = latency_us;
+
+ bin->e_lat_range.sum += latency_us;
+ bin->e_lat_range.samples++;
+
+ p = lws_json_simple_find(msg, bin->msg_len, "\"a\":[[\"", &alen);
+ if (!p)
+ return LWSSSSRET_OK;
+
+ lws_strnncpy(numbuf, p, alen, sizeof(numbuf));
+ price = pennies(numbuf);
+
+ if (price < bin->price_range.lowest)
+ bin->price_range.lowest = price;
+ if (price > bin->price_range.highest)
+ bin->price_range.highest = price;
+
+ bin->price_range.sum += price;
+ bin->price_range.samples++;
+
+ return LWSSSSRET_OK;
+}
+
+static lws_ss_state_return_t
+binance_state(void *userobj, void *h_src, lws_ss_constate_t state,
+ lws_ss_tx_ordinal_t ack)
+{
+ binance_t *bin = (binance_t *)userobj;
+
+ lwsl_ss_info(bin->ss, "%s (%d), ord 0x%x",
+ lws_ss_state_name((int)state), state, (unsigned int)ack);
+
+ switch (state) {
+
+ case LWSSSCS_CONNECTED:
+ lws_sul_schedule(lws_ss_get_context(bin->ss), 0, &bin->sul_hz,
+ sul_hz_cb, LWS_US_PER_SEC);
+ range_reset(&bin->e_lat_range);
+ range_reset(&bin->price_range);
+
+ return LWSSSSRET_OK;
+
+ case LWSSSCS_DISCONNECTED:
+ lws_sul_cancel(&bin->sul_hz);
+ break;
+
+ default:
+ break;
+ }
+
+ return LWSSSSRET_OK;
+}
+
+LWS_SS_INFO("binance", binance_t)
+ .rx = binance_rx,
+ .state = binance_state,
+};
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/sspc/get-ss.c b/minimal-examples/embedded/rt595/hello_world/project/source/sspc/get-ss.c
new file mode 100644
index 000000000..3940d1281
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/source/sspc/get-ss.c
@@ -0,0 +1,71 @@
+/*
+ * rt595-sspc-binance
+ *
+ * Written in 2010 - 2021 by Andy Green <andy@warmcat.com>
+ *
+ * This file is made available under the Creative Commons CC0 1.0
+ * Universal Public Domain Dedication.
+ *
+ * The SS user struct for the "GET" stream... it reads from
+ * https://libwebsockets.org/index.html every 5s
+ */
+
+#include "private.h"
+
+LWS_SS_USER_TYPEDEF
+ lws_sorted_usec_list_t sul5;
+} get_t;
+
+static void
+sul_start_get(lws_sorted_usec_list_t *sul)
+{
+ get_t *g = lws_container_of(sul, get_t, sul5);
+
+ lws_ss_request_tx(lws_ss_from_user(g));
+ lws_sul_schedule(lws_ss_cx_from_user(g), 0, sul, sul_start_get,
+ 5 * LWS_US_PER_SEC);
+}
+
+static lws_ss_state_return_t
+get_rx(void *userobj, const uint8_t *in, size_t len, int flags)
+{
+ get_t *g = (get_t *)userobj;
+
+ lwsl_ss_notice(lws_ss_from_user(g), "RX %u, flags 0x%x",
+ (unsigned int)len, (unsigned int)flags);
+
+ if (len) {
+ lwsl_hexdump_notice(in, 16);
+ if (len >= 16)
+ lwsl_hexdump_notice(in + len - 16, 16);
+ }
+
+ return LWSSSSRET_OK;
+}
+
+static lws_ss_state_return_t
+get_state(void *userobj, void *h_src, lws_ss_constate_t state,
+ lws_ss_tx_ordinal_t ack)
+{
+ get_t *g = (get_t *)userobj;
+
+ lwsl_ss_notice(lws_ss_from_user(g), "%s (%d), ord 0x%x",
+ lws_ss_state_name((int)state), state, (unsigned int)ack);
+
+ switch (state) {
+ case LWSSSCS_CREATING:
+ lws_sul_schedule(lws_ss_cx_from_user(g), 0, &g->sul5,
+ sul_start_get, 5 * LWS_US_PER_SEC);
+ break;
+ case LWSSSCS_DESTROYING:
+ lws_sul_cancel(&g->sul5);
+ break;
+ }
+
+ return LWSSSSRET_OK;
+}
+
+LWS_SS_INFO("mintest-lws", get_t)
+ .rx = get_rx,
+ .state = get_state,
+};
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/sspc/helpers.c b/minimal-examples/embedded/rt595/hello_world/project/source/sspc/helpers.c
new file mode 100644
index 000000000..937469301
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/source/sspc/helpers.c
@@ -0,0 +1,151 @@
+/*
+ * rt595-sspc-binance
+ *
+ * Written in 2010-2021 by Andy Green <andy@warmcat.com>
+ *
+ * This file is made available under the Creative Commons CC0 1.0
+ * Universal Public Domain Dedication.
+ *
+ * Since LWS_ONLY_SSPC chops down libwebsockets.a to have just the pieces needed
+ * for SSPC, we need to bring in our own copies of any other lws apis we use in
+ * the user Binance SS code
+ */
+
+#include "private.h"
+#include <string.h>
+#include <stdio.h>
+
+const char *
+lws_nstrstr(const char *buf, size_t len, const char *name, size_t nl)
+{
+ const char *end = buf + len - nl + 1;
+ size_t n;
+
+ if (nl > len)
+ /* it cannot be found if the needle is longer than the haystack */
+ return NULL;
+
+ while (buf < end) {
+ if (*buf != name[0]) {
+ buf++;
+ continue;
+ }
+
+ if (nl == 1)
+ /* single char match, we are done */
+ return buf;
+
+ if (buf[nl - 1] == name[nl - 1]) {
+ /*
+ * This is looking interesting then... the first
+ * and last chars match, let's check the insides
+ */
+ n = 1;
+ while (n < nl && buf[n] == name[n])
+ n++;
+
+ if (n == nl)
+ /* it's a hit */
+ return buf;
+ }
+
+ buf++;
+ }
+
+ return NULL;
+}
+
+
+const char *
+lws_json_simple_find(const char *buf, size_t len, const char *name, size_t *alen)
+{
+ size_t nl = strlen(name);
+ const char *np = lws_nstrstr(buf, len, name, nl),
+ *end = buf + len, *as;
+ int qu = 0;
+
+ if (!np)
+ return NULL;
+
+ np += nl;
+
+ while (np < end && (*np == ' ' || *np == '\t'))
+ np++;
+
+ if (np >= end)
+ return NULL;
+
+ /*
+ * The arg could be lots of things after "name": with JSON, commonly a
+ * string like "mystring", true, false, null, [...] or {...} ... we want
+ * to handle common, simple cases cheaply with this; the user can choose
+ * a full JSON parser like lejp if it's complicated. So if no opening
+ * quote, return until a terminator like , ] }. If there's an opening
+ * quote, return until closing quote, handling escaped quotes.
+ */
+
+ if (*np == '\"') {
+ qu = 1;
+ np++;
+ }
+
+ as = np;
+ while (np < end &&
+ (!qu || *np != '\"') && /* end quote is EOT if quoted */
+ (qu || (*np != '}' && *np != ']' && *np != ',')) /* delimiters */
+ ) {
+ if (qu && *np == '\\') /* skip next char if quoted escape */
+ np++;
+ np++;
+ }
+
+ *alen = (unsigned int)lws_ptr_diff(np, as);
+
+ return as;
+}
+
+void
+lwsl_hexdump_level(int hexdump_level, const void *vbuf, size_t len)
+{
+ unsigned char *buf = (unsigned char *)vbuf;
+ unsigned int n;
+
+ for (n = 0; n < len;) {
+ unsigned int start = n, m;
+ char line[80], *p = line;
+
+ p += snprintf(p, 10, "%04X: ", start);
+
+ for (m = 0; m < 16 && n < len; m++)
+ p += snprintf(p, 5, "%02X ", buf[n++]);
+ while (m++ < 16)
+ p += snprintf(p, 5, " ");
+
+ p += snprintf(p, 6, " ");
+
+ for (m = 0; m < 16 && (start + m) < len; m++) {
+ if (buf[start + m] >= ' ' && buf[start + m] < 127)
+ *p++ = (char)buf[start + m];
+ else
+ *p++ = '.';
+ }
+ while (m++ < 16)
+ *p++ = ' ';
+
+ *p++ = '\n';
+ *p = '\0';
+ _lws_log(hexdump_level, "%s", line);
+ (void)line;
+ }
+
+ _lws_log(hexdump_level, "\n");
+}
+
+uint64_t
+get_us_timeofday(void)
+{
+ if (!tm)
+ return lws_now_usecs();
+
+ return lws_now_usecs() - tm->us_unixtime_peer_loc + tm->us_unixtime_peer;
+}
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/sspc/main.c b/minimal-examples/embedded/rt595/hello_world/project/source/sspc/main.c
new file mode 100644
index 000000000..b9b6bcbbf
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/source/sspc/main.c
@@ -0,0 +1,130 @@
+/*
+ * rt595-sspc-binance
+ *
+ * Written in 2010-2021 by Andy Green <andy@warmcat.com>
+ *
+ * This file is made available under the Creative Commons CC0 1.0
+ * Universal Public Domain Dedication.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "usb_device_config.h"
+#include "usb.h"
+#include "usb_device.h"
+
+#include "usb_device_class.h"
+#include "usb_device_cdc_acm.h"
+#include "usb_device_ch9.h"
+#include "usb_device_descriptor.h"
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "composite.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+#include "private.h"
+
+void USB_DeviceApplicationInit(void);
+
+extern const lws_ss_info_t ssi_binance_t, /* binance-ss.c */
+ ssi_get_t; /* get-ss.c */
+extern const lws_transport_client_ops_t lws_sss_ops_client_serial;
+
+static struct lws_context_standalone cx = {
+ .txp_cpath.ops_onw = &lws_transport_mux_client_ops,
+};
+
+lws_transport_mux_t *tm;
+
+/*
+ * Describes how the lws_transport path goes through the transport_mux
+ */
+
+lws_transport_info_t info_serial = {
+ .ping_interval_us = LWS_US_PER_SEC * 10,
+ .pong_grace_us = LWS_US_PER_SEC * 2,
+ .flags = 0,
+}, info_mux = {
+ .ping_interval_us = LWS_US_PER_SEC * 10,
+ .pong_grace_us = LWS_US_PER_SEC * 2,
+ .txp_cpath = {
+ .ops_onw = &lws_sss_ops_client_serial,
+ /**< onward transport for mux is serial */
+ .ops_in = &lws_transport_mux_client_ops,
+ },
+ .onward_txp_info = &info_serial,
+ .flags = 0,
+};
+
+extern usb_cdc_acm_info_t s_usbCdcAcmInfo[USB_DEVICE_CONFIG_CDC_ACM];
+
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION)) || defined(__GNUC__)
+int main(void)
+#else
+void main(void)
+#endif
+{
+ unsigned int f = 0, din = 0;
+
+ BOARD_InitPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+
+ *((volatile uint32_t*)0xE0001000) = 0x40000001;
+
+ USB_DeviceApplicationInit();
+
+ /* create the ss transport mux object itself... only one of these */
+
+ tm = lws_transport_mux_create(&cx, &info_mux, NULL);
+ if (!tm) {
+ lwsl_err("%s: unable to create client mux\n", __func__);
+ return 1;
+ }
+ tm->info.txp_cpath.priv_in = tm;
+ cx.txp_cpath.mux = tm;
+
+
+ while (1) {
+
+ /*
+ * When the host link ttyACM is hooked up, create the SS. They could be
+ * created before the link, but delaying it like this means we will be
+ * able to hook up the log ttyACM and see the related logs for this.
+ */
+
+ if (!din && (s_usbCdcAcmInfo[1].uartState & USB_DEVICE_CDC_UART_STATE_RX_CARRIER)) {
+ din = 1;
+
+ if (lws_ss_create(&cx, 0, &ssi_binance_t, NULL, NULL, NULL, NULL)) {
+ lwsl_err("failed to create binance secure stream\n");
+ f = 1;
+ }
+
+ if (lws_ss_create(&cx, 0, &ssi_get_t, NULL, NULL, NULL, NULL)) {
+ lwsl_err("failed to create get secure stream\n");
+ f = 2;
+ }
+ }
+
+ USB_DeviceCdcVcomTask();
+ lws_now_usecs();
+ serial_handle_events(tm);
+
+ /* check the scheduler */
+
+ while (scheduler.head) {
+ lws_sorted_usec_list_t *sul = lws_container_of(
+ scheduler.head, lws_sorted_usec_list_t, list);
+
+ if (sul->us > lws_now_usecs())
+ break;
+ lws_dll2_remove(&sul->list);
+
+ sul->cb(sul);
+ }
+ }
+}
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/sspc/private.h b/minimal-examples/embedded/rt595/hello_world/project/source/sspc/private.h
new file mode 100644
index 000000000..879500dc6
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/source/sspc/private.h
@@ -0,0 +1,51 @@
+/*
+ * rt595-sspc-binance
+ *
+ * Written in 2010-2021 by Andy Green <andy@warmcat.com>
+ *
+ * This file is made available under the Creative Commons CC0 1.0
+ * Universal Public Domain Dedication.
+ */
+
+/* boilerplate for LWS_ONLY_SSPC Secure Streams
+ * LWS_SS_USE_SSPC should be defined by cmake
+ */
+
+#define lws_context lws_context_standalone
+#undef LWS_SS_USE_SSPC
+#define LWS_SS_USE_SSPC
+#undef STANDALONE
+#define STANDALONE
+#include <libwebsockets.h>
+
+typedef struct vcring {
+ uint8_t log_ring[4096];
+ unsigned int lrh, lrt;
+} vcring_t;
+
+extern vcring_t vcr_log, vcr_txp_out, vcr_txp_in;
+
+long long
+atoll(const char *s);
+
+size_t
+space_available(vcring_t *v);
+int
+append_vcring(vcring_t *v, const uint8_t *b, size_t l);
+size_t
+next_chonk(vcring_t *v, const uint8_t ** pp);
+void
+consume_chonk(vcring_t *v, size_t n);
+
+extern lws_dll2_owner_t scheduler;
+extern lws_transport_mux_t *tm;
+
+/* our transport related apis */
+
+extern const lws_transport_client_ops_t lws_sss_ops_client_serial;
+void serial_handle_events(lws_transport_mux_t *tm);
+
+/* our SS bindings */
+
+extern const lws_ss_info_t ssi_binance_t, /* binance-ss.c */
+ ssi_get_t; /* get-ss.c */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/sspc/system.c b/minimal-examples/embedded/rt595/hello_world/project/source/sspc/system.c
new file mode 100644
index 000000000..ddfc3f590
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/source/sspc/system.c
@@ -0,0 +1,277 @@
+/*
+ * rt595-sspc-binance
+ *
+ * Written in 2010-2021 by Andy Green <andy@warmcat.com>
+ *
+ * This file is made available under the Creative Commons CC0 1.0
+ * Universal Public Domain Dedication.
+ *
+ * These are the bindings for our system to the libwebsockets.a imports.
+ */
+
+#include "private.h"
+#include <string.h>
+#include <stdio.h>
+
+static uint32_t ticks_high, last_tick_low;
+
+/*
+ * wire up libwebsockets.a logs to native application logs, we just wire it up
+ * to the device console in our case.
+ *
+ * We add the lws loglevel colour scheme ourselves.
+ */
+
+int log_level = LLL_USER | LLL_ERR | LLL_WARN | LLL_NOTICE | LLL_INFO;
+
+static const char * const colours[] = {
+ "[31;1m", /* LLL_ERR */
+ "[36;1m", /* LLL_WARN */
+ "[35;1m", /* LLL_NOTICE */
+ "[32;1m", /* LLL_INFO */
+ "[34;1m", /* LLL_DEBUG */
+ "[33;1m", /* LLL_PARSER */
+ "[33m", /* LLL_HEADER */
+ "[33m", /* LLL_EXT */
+ "[33m", /* LLL_CLIENT */
+ "[33;1m", /* LLL_LATENCY */
+ "[0;1m", /* LLL_USER */
+ "[31m", /* LLL_THREAD */
+};
+
+
+size_t
+space_available(vcring_t *v)
+{
+ if (v->lrt < v->lrh)
+ return (sizeof(v->log_ring) - v->lrh) + v->lrt;
+
+ if (v->lrt == v->lrh)
+ return sizeof(v->log_ring) - 1;
+
+ return (v->lrt - v->lrh) - 1;
+}
+
+int
+append_vcring(vcring_t *v, const uint8_t *b, size_t l)
+{
+ size_t r = sizeof(v->log_ring) - v->lrh;
+
+ if (v->lrt < v->lrh) {
+ /* ---t=====h--- */
+
+ if (r > l)
+ r = l;
+ memcpy(v->log_ring + v->lrh, b, r);
+ v->lrh += r;
+
+ if (v->lrh >= sizeof(v->log_ring))
+ v->lrh = 0;
+
+ b += r;
+ l -= r;
+
+ if (!l)
+ return 0;
+ }
+
+ /* ===h------t=== or ht--------- */
+
+ r = v->lrt - v->lrh;
+ if (!r) {
+ r = sizeof(v->log_ring) - 1;
+ v->lrt = v->lrh = 0;
+ }
+ if (r > l)
+ r = l;
+ memcpy(v->log_ring + v->lrh, b, r);
+ v->lrh += r;
+ if (v->lrh >= sizeof(v->log_ring))
+ v->lrh = 0;
+
+ __sync_synchronize();
+
+ return 0;
+}
+
+size_t
+next_chonk(vcring_t *v, const uint8_t ** pp)
+{
+ size_t c = v->lrh < v->lrt ? sizeof(v->log_ring) - v->lrt : v->lrh - v->lrt;
+
+ *pp = v->log_ring + v->lrt;
+
+ return c;
+}
+
+void
+consume_chonk(vcring_t *v, size_t n)
+{
+ v->lrt += n;
+ if (v->lrt >= sizeof(v->log_ring))
+ v->lrt = 0;
+}
+
+int
+add_log_buf(const uint8_t *b, size_t l)
+{
+ return append_vcring(&vcr_log, b, l);
+}
+
+void
+__lws_logv(lws_log_cx_t *cx, lws_log_prepend_cx_t prep, void *obj,
+ int filter, const char * const _fun, const char *format, va_list ap)
+{
+ int n, m = LWS_ARRAY_SIZE(colours) - 1;
+ char logbuf[200], *p = logbuf, *e = logbuf + sizeof(logbuf) - 7;
+
+ if (!(filter & log_level))
+ return;
+
+ n = 1 << (LWS_ARRAY_SIZE(colours) - 1);
+ while (n) {
+ if (filter & n)
+ break;
+ m--;
+ n >>= 1;
+ }
+
+ n = snprintf(p, lws_ptr_diff(e, p), "%lu: %c%s%s: ", (unsigned long)lws_now_usecs(), 27,
+ colours[m], _fun);
+ p += n;
+ if (prep && obj)
+ prep(cx, obj, &p, e);
+
+ n = vsnprintf(p, lws_ptr_diff(e, p), format, ap);
+ p += n;
+
+ if (p > e)
+ p = e;
+ if (p[-1] != '\n')
+ *p++ = '\n';
+
+ *p++ = '\r';
+ *p++ = 27;
+ *p++ = '[';
+ *p++ = '0';
+ *p++ = 'm';
+
+ add_log_buf(logbuf, lws_ptr_diff(p, logbuf));
+}
+
+
+static int
+sul_compare(const lws_dll2_t *d, const lws_dll2_t *i)
+{
+ lws_usec_t a = ((lws_sorted_usec_list_t *)d)->us;
+ lws_usec_t b = ((lws_sorted_usec_list_t *)i)->us;
+
+ /*
+ * Simply returning (a - b) in an int
+ * may lead to an integer overflow bug
+ */
+
+ if (a > b)
+ return 1;
+ if (a < b)
+ return -1;
+
+ return 0;
+}
+
+void
+lws_sul_schedule(struct lws_context_standalone *ctx, int tsi,
+ lws_sorted_usec_list_t *sul, sul_cb_t _cb, lws_usec_t _us)
+{
+ if (_us == (lws_usec_t)LWS_SET_TIMER_USEC_CANCEL) {
+ lws_sul_cancel(sul);
+ return;
+ }
+
+ lws_dll2_remove(&sul->list);
+
+ sul->cb = _cb;
+ sul->us = lws_now_usecs() + _us;
+
+ lws_dll2_add_sorted(&sul->list, &scheduler, sul_compare);
+}
+
+void
+lws_sul_cancel(lws_sorted_usec_list_t *sul)
+{
+ lws_dll2_remove(&sul->list);
+ sul->us = 0;
+}
+
+
+lws_usec_t
+lws_now_usecs(void)
+{
+ uint32_t a = *((volatile uint32_t*)0xE0001004);
+ if (a < (uint32_t)last_tick_low)
+ ticks_high++;
+ last_tick_low = a;
+
+ return ((((uint64_t)ticks_high)<<32) | (uint64_t)a) / 198;
+}
+
+struct timeval {
+ uint32_t tv_sec; /* seconds */
+ uint32_t tv_usec; /* microseconds */
+};
+
+
+int gettimeofday(struct timeval *tv, void *tx)
+{
+ lws_usec_t u = lws_now_usecs();
+
+ tv->tv_sec = u / 1000000;
+ tv->tv_usec = u - (tv->tv_sec * 1000000);
+}
+
+long long atoll(const char *s)
+{
+ long long l = 0ll;
+ char minus = *s == '-';
+
+ if (minus)
+ s++;
+
+ while (*s) {
+ if (*s < '0' || *s > '9')
+ break;
+ l = (long long)(l * 10ll) + (*s) - '0';
+ s++;
+ }
+
+ if (minus)
+ return 0ll - l;
+
+ return l;
+}
+
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+ lwsl_err("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file ,
+ line, func);
+ for (;;)
+ {}
+}
+
+int getpid(void)
+{
+ return 0;
+}
+
+struct lws_log_cx *
+lwsl_context_get_cx(struct lws_context_standalone *cx)
+{
+ return NULL;
+}
+
+void
+lws_log_prepend_context(struct lws_log_cx *cx, void *obj, char **p, char *e)
+{
+
+}
+
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/sspc/transport-serial.c b/minimal-examples/embedded/rt595/hello_world/project/source/sspc/transport-serial.c
new file mode 100644
index 000000000..287740263
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/source/sspc/transport-serial.c
@@ -0,0 +1,178 @@
+/*
+ * rt595-sspc-binance
+ *
+ * Written in 2010-2021 by Andy Green <andy@warmcat.com>
+ *
+ * This file is made available under the Creative Commons CC0 1.0
+ * Universal Public Domain Dedication.
+ *
+ * The serial port based custom transport, and helpers used by lws_transport
+ */
+
+#include "private.h"
+
+int need_pollout;
+
+/* incoming parsed channel cbs */
+
+static int
+ltm_ch_payload(lws_transport_mux_ch_t *tmc, const uint8_t *buf, size_t len)
+{
+ lwsl_notice("%s\n", __func__);
+ return 0;
+}
+
+static int
+ltm_ch_opens_serial(lws_transport_mux_ch_t *tmc, int determination)
+{
+ lws_transport_mux_t *tm = lws_container_of(tmc->list.owner,
+ lws_transport_mux_t, owner);
+ struct lws_sspc_handle *h = (struct lws_sspc_handle *)tmc->priv;
+
+ assert_is_tm(tm);
+
+ lwsl_sspc_err(h, "%d", determination);
+
+ if (tm->info.txp_cpath.ops_in->event_connect_disposition(h, determination))
+ return -1;
+
+ return 0;
+}
+
+static int
+ltm_ch_closes(lws_transport_mux_ch_t *tmc)
+{
+ lwsl_notice("%s\n", __func__);
+ return 0;
+}
+
+static void
+ltm_txp_req_write(lws_transport_mux_t *tm)
+{
+ tm->info.txp_cpath.ops_onw->req_write(tm->info.txp_cpath.priv_onw);
+}
+
+static int
+ltm_txp_can_write(lws_transport_mux_ch_t *tmc)
+{
+ assert_is_tmch(tmc);
+ return lws_txp_inside_sspc.event_can_write(
+ (struct lws_sspc_handle *)tmc->priv, 2048);
+}
+
+/*
+ * So that we can use the same mux framing parser for both sides, we pass into
+ * the parser an "ops struct" that gets called back to customize response to
+ * mux parser framing.
+ */
+
+static const lws_txp_mux_parse_cbs_t cbs = {
+ .payload = ltm_ch_payload,
+ .ch_opens = ltm_ch_opens_serial,
+ .ch_closes = ltm_ch_closes,
+ .txp_req_write = ltm_txp_req_write,
+ .txp_can_write = ltm_txp_can_write,
+};
+
+void
+serial_handle_events(lws_transport_mux_t *tm)
+{
+ const uint8_t *p;
+ uint8_t chonk[1200];
+ size_t n;
+
+ /* for "POLLOUT" */
+
+ if (need_pollout && vcr_txp_out.lrh == vcr_txp_out.lrt) {
+ size_t cl = sizeof(chonk);
+ need_pollout = 0;
+
+ if (lws_transport_mux_pending(tm, chonk, &cl, &cbs)) {
+#if defined(_DEBUG)
+ lws_transport_path_client_dump(&tm->info.txp_cpath, "cpath");
+#endif
+ tm->info.txp_cpath.ops_onw->_write(
+ tm->info.txp_cpath.priv_onw, chonk, cl);
+
+ return;
+ }
+ }
+}
+
+/*
+ * We get called while an individual SS is trying to connect to the proxy to
+ * be recognized as operational. It's the equivalent of trying to bring up the
+ * Unix Domain socket
+ */
+
+static int
+txp_serial_retry_connect(lws_txp_path_client_t *path,
+ struct lws_sspc_handle *h)
+{
+ lwsl_user("%s\n", __func__);
+
+ if (!path)
+ return 0;
+
+ if (path->ops_onw->event_connect_disposition(h,
+ path->mux->link_state != LWSTM_OPERATIONAL))
+ return -1;
+
+ return 0;
+}
+
+static void
+txp_serial_req_write(lws_transport_priv_t priv)
+{
+ need_pollout = 1;
+}
+
+static int
+txp_serial_write(lws_transport_priv_t priv, uint8_t *buf, size_t len)
+{
+ lwsl_notice("%s: writing %u\n", __func__, (unsigned int)len);
+
+// lwsl_hexdump_level(LLL_WARN, buf, len);
+
+ append_vcring(&vcr_txp_out, buf, len);
+
+ return 0;
+}
+
+static void
+txp_serial_close(lws_transport_priv_t priv)
+{
+#if 0
+ struct lws *wsi = (struct lws *)priv;
+
+ if (!wsi)
+ return;
+
+ lws_set_opaque_user_data(wsi, NULL);
+ lws_wsi_close(wsi, LWS_TO_KILL_ASYNC);
+ *priv = NULL;
+#endif
+}
+
+static void
+txp_serial_stream_up(lws_transport_priv_t priv)
+{
+// struct lws *wsi = (struct lws *)priv;
+
+// lws_set_timeout(wsi, NO_PENDING_TIMEOUT, 0);
+}
+
+/*
+ * This is the lws_transport export for our custom serial transport
+ */
+
+const lws_transport_client_ops_t lws_sss_ops_client_serial = {
+ .name = "txpserial",
+ .event_retry_connect = txp_serial_retry_connect,
+ .req_write = txp_serial_req_write,
+ ._write = txp_serial_write,
+ ._close = txp_serial_close,
+ .event_stream_up = txp_serial_stream_up,
+ .flags = LWS_DSHFLAG_ENABLE_COALESCE,
+ .dsh_splitat = 0,
+};
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/sys/time.h b/minimal-examples/embedded/rt595/hello_world/project/source/sys/time.h
new file mode 100644
index 000000000..e69de29bb
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/sys/types.h b/minimal-examples/embedded/rt595/hello_world/project/source/sys/types.h
new file mode 100644
index 000000000..e69de29bb
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/unistd.h b/minimal-examples/embedded/rt595/hello_world/project/source/unistd.h
new file mode 100644
index 000000000..e69de29bb
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/usb_device_config.h b/minimal-examples/embedded/rt595/hello_world/project/source/usb_device_config.h
new file mode 100644
index 000000000..b62fc83d4
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/source/usb_device_config.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _USB_DEVICE_CONFIG_H_
+#define _USB_DEVICE_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @addtogroup usb_device_configuration
+ * @{
+ */
+
+/*!
+ * @name Hardware instance define
+ * @{
+ */
+
+/*! @brief KHCI instance count */
+#define USB_DEVICE_CONFIG_KHCI (0U)
+
+/*! @brief EHCI instance count */
+#define USB_DEVICE_CONFIG_EHCI (0U)
+
+/*! @brief LPC USB IP3511 FS instance count */
+#define USB_DEVICE_CONFIG_LPCIP3511FS (0U)
+
+/*! @brief LPC USB IP3511 HS instance count */
+#define USB_DEVICE_CONFIG_LPCIP3511HS (1U)
+
+/*! @brief Device instance count, the sum of KHCI and EHCI instance counts*/
+#define USB_DEVICE_CONFIG_NUM \
+ (USB_DEVICE_CONFIG_KHCI + USB_DEVICE_CONFIG_EHCI + USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS)
+
+/* @} */
+
+/*!
+ * @name class instance define
+ * @{
+ */
+
+/*! @brief HID instance count */
+#define USB_DEVICE_CONFIG_HID (0U)
+
+/*! @brief CDC ACM instance count */
+#define USB_DEVICE_CONFIG_CDC_ACM (2U)
+
+/*! @brief MSC instance count */
+#define USB_DEVICE_CONFIG_MSC (0U)
+
+/*! @brief Audio instance count */
+#define USB_DEVICE_CONFIG_AUDIO (0U)
+
+/*! @brief PHDC instance count */
+#define USB_DEVICE_CONFIG_PHDC (0U)
+
+/*! @brief Video instance count */
+#define USB_DEVICE_CONFIG_VIDEO (0U)
+
+/*! @brief CCID instance count */
+#define USB_DEVICE_CONFIG_CCID (0U)
+
+/*! @brief Printer instance count */
+#define USB_DEVICE_CONFIG_PRINTER (0U)
+
+/*! @brief DFU instance count */
+#define USB_DEVICE_CONFIG_DFU (0U)
+
+/* @} */
+
+/*! @brief Whether device is self power. 1U supported, 0U not supported */
+#define USB_DEVICE_CONFIG_SELF_POWER (1U)
+
+/*! @brief How many endpoints are supported in the stack. */
+#define USB_DEVICE_CONFIG_ENDPOINTS (5U)
+
+/*! @brief Whether the device task is enabled. */
+#define USB_DEVICE_CONFIG_USE_TASK (0U)
+
+/*! @brief How many the notification message are supported when the device task is enabled. */
+#define USB_DEVICE_CONFIG_MAX_MESSAGES (8U)
+
+/*! @brief Whether test mode enabled. */
+#define USB_DEVICE_CONFIG_USB20_TEST_MODE (0U)
+
+/*! @brief Whether device CV test is enabled. */
+#define USB_DEVICE_CONFIG_CV_TEST (0U)
+
+/*! @brief Whether device compliance test is enabled. If the macro is enabled,
+ the test mode and CV test macroes will be set.*/
+#define USB_DEVICE_CONFIG_COMPLIANCE_TEST (0U)
+
+#if ((defined(USB_DEVICE_CONFIG_COMPLIANCE_TEST)) && (USB_DEVICE_CONFIG_COMPLIANCE_TEST > 0U))
+
+/*! @brief Undefine the macro USB_DEVICE_CONFIG_USB20_TEST_MODE. */
+#undef USB_DEVICE_CONFIG_USB20_TEST_MODE
+/*! @brief Undefine the macro USB_DEVICE_CONFIG_CV_TEST. */
+#undef USB_DEVICE_CONFIG_CV_TEST
+
+/*! @brief enable the test mode. */
+#define USB_DEVICE_CONFIG_USB20_TEST_MODE (1U)
+
+/*! @brief enable the CV test */
+#define USB_DEVICE_CONFIG_CV_TEST (1U)
+
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
+
+/*! @brief The MAX buffer length for the KHCI DMA workaround.*/
+#define USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH (64U)
+/*! @brief Whether handle the USB KHCI bus error. */
+#define USB_DEVICE_CONFIG_KHCI_ERROR_HANDLING (0U)
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
+/*! @brief How many the DTD are supported. */
+#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U)
+/*! @brief Whether handle the USB EHCI bus error. */
+#define USB_DEVICE_CONFIG_EHCI_ERROR_HANDLING (0U)
+
+/*! @brief Whether the EHCI ID pin detect feature enabled. */
+#define USB_DEVICE_CONFIG_EHCI_ID_PIN_DETECT (0U)
+#endif
+
+/*! @brief Whether the keep alive feature enabled. */
+#define USB_DEVICE_CONFIG_KEEP_ALIVE_MODE (0U)
+
+/*! @brief Whether the transfer buffer is cache-enabled or not. */
+#ifndef USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE
+#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (0U)
+#endif
+/*! @brief Whether the low power mode is enabled or not. */
+#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U)
+
+#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+/*! @brief Whether device remote wakeup supported. 1U supported, 0U not supported */
+#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U)
+
+/*! @brief Whether LPM is supported. 1U supported, 0U not supported */
+#define USB_DEVICE_CONFIG_LPM_L1 (0U)
+#else
+/*! @brief The device remote wakeup is unsupported. */
+#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U)
+#endif
+
+/*! @brief Whether the device detached feature is enabled or not. */
+#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U)
+
+/* @} */
+
+#endif /* _USB_DEVICE_CONFIG_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/usb_device_descriptor.c b/minimal-examples/embedded/rt595/hello_world/project/source/usb_device_descriptor.c
new file mode 100644
index 000000000..f8d41f29b
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/source/usb_device_descriptor.c
@@ -0,0 +1,814 @@
+/*
+ * Copyright 2017 - 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "usb_device_config.h"
+#include "usb.h"
+#include "usb_device.h"
+
+#include "usb_device_class.h"
+#include "usb_device_cdc_acm.h"
+
+#include "usb_device_descriptor.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* msc disk information */
+/* Define endpoint for Vcom class */
+/* cdc virtual com information */
+/* Define endpoint for communication class */
+usb_device_endpoint_struct_t g_cdcVcomCicEndpoints[USB_CDC_VCOM_CIC_ENDPOINT_COUNT] = {
+ {
+ USB_CDC_VCOM_CIC_INTERRUPT_IN_ENDPOINT | (USB_IN << 7U),
+ USB_ENDPOINT_INTERRUPT,
+ FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE,
+ FS_CDC_VCOM_INTERRUPT_IN_INTERVAL,
+ },
+};
+
+/* Define endpoint for data class */
+usb_device_endpoint_struct_t g_cdcVcomDicEndpoints[USB_CDC_VCOM_DIC_ENDPOINT_COUNT] = {
+ {
+ USB_CDC_VCOM_DIC_BULK_IN_ENDPOINT | (USB_IN << 7U),
+ USB_ENDPOINT_BULK,
+ FS_CDC_VCOM_BULK_IN_PACKET_SIZE,
+ 0U,
+ },
+ {
+ USB_CDC_VCOM_DIC_BULK_OUT_ENDPOINT | (USB_OUT << 7U),
+ USB_ENDPOINT_BULK,
+ FS_CDC_VCOM_BULK_OUT_PACKET_SIZE,
+ 0U,
+ },
+};
+
+/* Define interface for communication class */
+usb_device_interface_struct_t g_cdcVcomCicInterface[] = {{USB_CDC_VCOM_CIC_INTERFACE_ALTERNATE_0,
+ {
+ USB_CDC_VCOM_CIC_ENDPOINT_COUNT,
+ g_cdcVcomCicEndpoints,
+ },
+ NULL}};
+
+/* Define interface for data class */
+usb_device_interface_struct_t g_cdcVcomDicInterface[] = {{USB_CDC_VCOM_DIC_INTERFACE_ALTERNATE_0,
+ {
+ USB_CDC_VCOM_DIC_ENDPOINT_COUNT,
+ g_cdcVcomDicEndpoints,
+ },
+ NULL}};
+
+/* Define interfaces for virtual com */
+usb_device_interfaces_struct_t g_cdcVcomInterfaces[USB_CDC_VCOM_INTERFACE_COUNT] = {
+ {USB_CDC_VCOM_CIC_CLASS, USB_CDC_VCOM_CIC_SUBCLASS, USB_CDC_VCOM_CIC_PROTOCOL, USB_CDC_VCOM_CIC_INTERFACE_INDEX,
+ g_cdcVcomCicInterface, sizeof(g_cdcVcomCicInterface) / sizeof(usb_device_interface_struct_t)},
+ {USB_CDC_VCOM_DIC_CLASS, USB_CDC_VCOM_DIC_SUBCLASS, USB_CDC_VCOM_DIC_PROTOCOL, USB_CDC_VCOM_DIC_INTERFACE_INDEX,
+ g_cdcVcomDicInterface, sizeof(g_cdcVcomDicInterface) / sizeof(usb_device_interface_struct_t)},
+};
+
+/* Define configurations for virtual com */
+usb_device_interface_list_t g_UsbDeviceCdcVcomInterfaceList[USB_DEVICE_CONFIGURATION_COUNT] = {
+ {
+ USB_CDC_VCOM_INTERFACE_COUNT,
+ g_cdcVcomInterfaces,
+ },
+};
+
+/* cdc virtual com 2 information */
+/* Define endpoint for communication class */
+usb_device_endpoint_struct_t g_cdcVcomCicEndpoints_2[USB_CDC_VCOM_CIC_ENDPOINT_COUNT_2] = {
+ {
+ USB_CDC_VCOM_CIC_INTERRUPT_IN_ENDPOINT_2 | (USB_IN << 7U),
+ USB_ENDPOINT_INTERRUPT,
+ FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE_2,
+ FS_CDC_VCOM_INTERRUPT_IN_INTERVAL_2,
+ },
+};
+
+/* Define endpoint for data class */
+usb_device_endpoint_struct_t g_cdcVcomDicEndpoints_2[USB_CDC_VCOM_DIC_ENDPOINT_COUNT_2] = {
+ {
+ USB_CDC_VCOM_DIC_BULK_IN_ENDPOINT_2 | (USB_IN << 7U),
+ USB_ENDPOINT_BULK,
+ FS_CDC_VCOM_BULK_IN_PACKET_SIZE,
+ 0U,
+ },
+ {
+ USB_CDC_VCOM_DIC_BULK_OUT_ENDPOINT_2 | (USB_OUT << 7U),
+ USB_ENDPOINT_BULK,
+ FS_CDC_VCOM_BULK_OUT_PACKET_SIZE,
+ 0U,
+ },
+};
+
+/* Define interface for communication class */
+usb_device_interface_struct_t g_cdcVcomCicInterface_2[] = {{USB_CDC_VCOM_CIC_INTERFACE_2_ALTERNATE_0,
+ {
+ USB_CDC_VCOM_CIC_ENDPOINT_COUNT_2,
+ g_cdcVcomCicEndpoints_2,
+ },
+ NULL}};
+
+/* Define interface for data class */
+usb_device_interface_struct_t g_cdcVcomDicInterface_2[] = {{USB_CDC_VCOM_DIC_INTERFACE_2_ALTERNATE_0,
+ {
+ USB_CDC_VCOM_DIC_ENDPOINT_COUNT_2,
+ g_cdcVcomDicEndpoints_2,
+ },
+ NULL}};
+
+/* Define interfaces for virtual com */
+usb_device_interfaces_struct_t g_cdcVcomInterfaces_2[USB_CDC_VCOM_INTERFACE_COUNT_2] = {
+ {USB_CDC_VCOM_CIC_CLASS, USB_CDC_VCOM_CIC_SUBCLASS, USB_CDC_VCOM_CIC_PROTOCOL, USB_CDC_VCOM_CIC_INTERFACE_INDEX_2,
+ g_cdcVcomCicInterface_2, sizeof(g_cdcVcomCicInterface_2) / sizeof(usb_device_interface_struct_t)},
+ {USB_CDC_VCOM_DIC_CLASS, USB_CDC_VCOM_DIC_SUBCLASS, USB_CDC_VCOM_DIC_PROTOCOL, USB_CDC_VCOM_DIC_INTERFACE_INDEX_2,
+ g_cdcVcomDicInterface_2, sizeof(g_cdcVcomDicInterface_2) / sizeof(usb_device_interface_struct_t)},
+};
+
+/* Define configurations for virtual com */
+usb_device_interface_list_t g_UsbDeviceCdcVcomInterfaceList_2[USB_DEVICE_CONFIGURATION_COUNT] = {
+ {
+ USB_CDC_VCOM_INTERFACE_COUNT_2,
+ g_cdcVcomInterfaces_2,
+ },
+};
+
+/* Define class information for virtual com */
+usb_device_class_struct_t g_UsbDeviceCdcVcomConfig[2] = {
+ {
+ g_UsbDeviceCdcVcomInterfaceList,
+ kUSB_DeviceClassTypeCdc,
+ USB_DEVICE_CONFIGURATION_COUNT,
+ },
+ {
+ g_UsbDeviceCdcVcomInterfaceList_2,
+ kUSB_DeviceClassTypeCdc,
+ USB_DEVICE_CONFIGURATION_COUNT,
+ },
+};
+
+/* Define device descriptor */
+USB_DMA_INIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE)
+uint8_t g_UsbDeviceDescriptor[] = {
+ /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_LENGTH_DEVICE,
+ /* DEVICE Descriptor Type */
+ USB_DESCRIPTOR_TYPE_DEVICE,
+ /* USB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). */
+ USB_SHORT_GET_LOW(USB_DEVICE_SPECIFIC_BCD_VERSION),
+ USB_SHORT_GET_HIGH(USB_DEVICE_SPECIFIC_BCD_VERSION),
+ /* Class code (assigned by the USB-IF). */
+ USB_DEVICE_CLASS,
+ /* Subclass code (assigned by the USB-IF). */
+ USB_DEVICE_SUBCLASS,
+ /* Protocol code (assigned by the USB-IF). */
+ USB_DEVICE_PROTOCOL,
+ /* Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid) */
+ USB_CONTROL_MAX_PACKET_SIZE,
+ USB_SHORT_GET_LOW(USB_DEVICE_VID),
+ USB_SHORT_GET_HIGH(USB_DEVICE_VID), /* Vendor ID (assigned by the USB-IF) */
+ USB_SHORT_GET_LOW(USB_DEVICE_PID),
+ USB_SHORT_GET_HIGH(USB_DEVICE_PID), /* Product ID (assigned by the manufacturer) */
+ /* Device release number in binary-coded decimal */
+ USB_SHORT_GET_LOW(USB_DEVICE_DEMO_BCD_VERSION),
+ USB_SHORT_GET_HIGH(USB_DEVICE_DEMO_BCD_VERSION),
+ /* Index of string descriptor describing manufacturer */
+ 0x01,
+ /* Index of string descriptor describing product */
+ 0x02,
+ /* Index of string descriptor describing the device's serial number */
+ 0x03,
+ /* Number of possible configurations */
+ USB_DEVICE_CONFIGURATION_COUNT,
+};
+
+/* Define configuration descriptor */
+USB_DMA_INIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE)
+uint8_t g_UsbDeviceConfigurationDescriptor[] = {
+ /* Configuration Descriptor Size*/
+ USB_DESCRIPTOR_LENGTH_CONFIGURE,
+ /* CONFIGURATION Descriptor Type */
+ USB_DESCRIPTOR_TYPE_CONFIGURE,
+ /* Total length of data returned for this configuration. */
+ USB_SHORT_GET_LOW(USB_DESCRIPTOR_LENGTH_CONFIGURE +
+ (USB_IAD_DESC_SIZE + USB_DESCRIPTOR_LENGTH_INTERFACE + USB_DESCRIPTOR_LENGTH_CDC_HEADER_FUNC +
+ USB_DESCRIPTOR_LENGTH_CDC_CALL_MANAG + USB_DESCRIPTOR_LENGTH_CDC_ABSTRACT +
+ USB_DESCRIPTOR_LENGTH_CDC_UNION_FUNC + USB_DESCRIPTOR_LENGTH_ENDPOINT +
+ USB_DESCRIPTOR_LENGTH_INTERFACE + USB_DESCRIPTOR_LENGTH_ENDPOINT +
+ USB_DESCRIPTOR_LENGTH_ENDPOINT) *
+ USB_DEVICE_CONFIG_CDC_ACM),
+ USB_SHORT_GET_HIGH(USB_DESCRIPTOR_LENGTH_CONFIGURE +
+ (USB_IAD_DESC_SIZE + USB_DESCRIPTOR_LENGTH_INTERFACE + USB_DESCRIPTOR_LENGTH_CDC_HEADER_FUNC +
+ USB_DESCRIPTOR_LENGTH_CDC_CALL_MANAG + USB_DESCRIPTOR_LENGTH_CDC_ABSTRACT +
+ USB_DESCRIPTOR_LENGTH_CDC_UNION_FUNC + USB_DESCRIPTOR_LENGTH_ENDPOINT +
+ USB_DESCRIPTOR_LENGTH_INTERFACE + USB_DESCRIPTOR_LENGTH_ENDPOINT +
+ USB_DESCRIPTOR_LENGTH_ENDPOINT) *
+ USB_DEVICE_CONFIG_CDC_ACM),
+ /* the two cdc interface have almost same interface attribute except for some number index difference etc, so we
+ could multiply by USB_DEVICE_CONFIG_CDC_ACM when calculate length*/
+ /* Number of interfaces supported by this configuration */
+ USB_INTERFACE_COUNT,
+ /* Value to use as an argument to the SetConfiguration() request to select this configuration */
+ USB_COMPOSITE_CONFIGURE_INDEX,
+ /* Index of string descriptor describing this configuration */
+ 0,
+ /* Configuration characteristics D7: Reserved (set to one) D6: Self-powered D5: Remote Wakeup D4...0: Reserved
+ (reset to zero) */
+ (USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_MASK) |
+ (USB_DEVICE_CONFIG_SELF_POWER << USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_SHIFT) |
+ (USB_DEVICE_CONFIG_REMOTE_WAKEUP << USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_SHIFT),
+ /* Maximum power consumption of the USB * device from the bus in this specific * configuration when the device is
+ fully * operational. Expressed in 2 mA units * (i.e., 50 = 100 mA). */
+ USB_DEVICE_MAX_POWER,
+
+ /* Interface Association Descriptor */
+ /* Size of this descriptor in bytes */
+ USB_IAD_DESC_SIZE,
+ /* INTERFACE_ASSOCIATION Descriptor Type */
+ USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION,
+ /* The first interface number associated with this function */
+ 0x00,
+ /* The number of contiguous interfaces associated with this function */
+ 0x02,
+ /* The function belongs to the Communication Device/Interface Class */
+ USB_CDC_VCOM_CIC_CLASS, USB_CDC_VCOM_CIC_SUBCLASS,
+ /* The function uses the No class specific protocol required Protocol */
+ 0x00,
+ /* The Function string descriptor index */
+ 0x02,
+
+ /* Interface Descriptor */
+ USB_DESCRIPTOR_LENGTH_INTERFACE, USB_DESCRIPTOR_TYPE_INTERFACE, USB_CDC_VCOM_CIC_INTERFACE_INDEX, USB_CDC_VCOM_CIC_INTERFACE_ALTERNATE_0,
+ USB_CDC_VCOM_CIC_ENDPOINT_COUNT, USB_CDC_VCOM_CIC_CLASS, USB_CDC_VCOM_CIC_SUBCLASS, USB_CDC_VCOM_CIC_PROTOCOL, 0x00,
+
+ /* CDC Class-Specific descriptor */
+ USB_DESCRIPTOR_LENGTH_CDC_HEADER_FUNC, /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */
+ USB_CDC_HEADER_FUNC_DESC, 0x10,
+ 0x01, /* USB Class Definitions for Communications the Communication specification version 1.10 */
+
+ USB_DESCRIPTOR_LENGTH_CDC_CALL_MANAG, /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */
+ USB_CDC_CALL_MANAGEMENT_FUNC_DESC,
+ 0x01, /*Bit 0: Whether device handle call management itself 1, Bit 1: Whether device can send/receive call
+ management information over a Data Class Interface 0 */
+ 0x01, /* Indicates multiplexed commands are handled via data interface */
+
+ USB_DESCRIPTOR_LENGTH_CDC_ABSTRACT, /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */
+ USB_CDC_ABSTRACT_CONTROL_FUNC_DESC,
+ 0x06, /* Bit 0: Whether device supports the request combination of Set_Comm_Feature, Clear_Comm_Feature, and
+ Get_Comm_Feature 0, Bit 1: Whether device supports the request combination of Set_Line_Coding,
+ Set_Control_Line_State, Get_Line_Coding, and the notification Serial_State 1, Bit ... */
+
+ USB_DESCRIPTOR_LENGTH_CDC_UNION_FUNC, /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */
+ USB_CDC_UNION_FUNC_DESC,
+ USB_CDC_VCOM_CIC_INTERFACE_INDEX, /* The interface number of the Communications or Data Class interface */
+ USB_CDC_VCOM_DIC_INTERFACE_INDEX, /* Interface number of subordinate interface in the Union */
+
+ /*Notification Endpoint descriptor */
+ USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT,
+ USB_CDC_VCOM_CIC_INTERRUPT_IN_ENDPOINT | (USB_IN << 7U), USB_ENDPOINT_INTERRUPT,
+ USB_SHORT_GET_LOW(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE), USB_SHORT_GET_HIGH(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE),
+ FS_CDC_VCOM_INTERRUPT_IN_INTERVAL,
+
+ /* Data Interface Descriptor */
+ USB_DESCRIPTOR_LENGTH_INTERFACE, USB_DESCRIPTOR_TYPE_INTERFACE, USB_CDC_VCOM_DIC_INTERFACE_INDEX, USB_CDC_VCOM_DIC_INTERFACE_ALTERNATE_0,
+ USB_CDC_VCOM_DIC_ENDPOINT_COUNT, USB_CDC_VCOM_DIC_CLASS, USB_CDC_VCOM_DIC_SUBCLASS, USB_CDC_VCOM_DIC_PROTOCOL,
+ 0x00, /* Interface Description String Index*/
+
+ /*Bulk IN Endpoint descriptor */
+ USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT, USB_CDC_VCOM_DIC_BULK_IN_ENDPOINT | (USB_IN << 7U),
+ USB_ENDPOINT_BULK, USB_SHORT_GET_LOW(FS_CDC_VCOM_BULK_IN_PACKET_SIZE),
+ USB_SHORT_GET_HIGH(FS_CDC_VCOM_BULK_IN_PACKET_SIZE), 0x00, /* The polling interval value is every 0 Frames */
+
+ /*Bulk OUT Endpoint descriptor */
+ USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT, USB_CDC_VCOM_DIC_BULK_OUT_ENDPOINT | (USB_OUT << 7U),
+ USB_ENDPOINT_BULK, USB_SHORT_GET_LOW(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE),
+ USB_SHORT_GET_HIGH(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE), 0x00, /* The polling interval value is every 0 Frames */
+
+ /*****VCOM_2 descriptor*****/
+ /* Interface Association Descriptor */
+ /* Size of this descriptor in bytes */
+ USB_IAD_DESC_SIZE,
+ /* INTERFACE_ASSOCIATION Descriptor Type */
+ USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION,
+ /* The first interface number associated with this function */
+ 0x02,
+ /* The number of contiguous interfaces associated with this function */
+ 0x02,
+ /* The function belongs to the Communication Device/Interface Class */
+ USB_CDC_VCOM_CIC_CLASS, USB_CDC_VCOM_CIC_SUBCLASS,
+ /* The function uses the No class specific protocol required Protocol */
+ 0x00,
+ /* The Function string descriptor index */
+ 0x02,
+ /* CDC Interface Descriptor */
+ USB_DESCRIPTOR_LENGTH_INTERFACE, USB_DESCRIPTOR_TYPE_INTERFACE, USB_CDC_VCOM_CIC_INTERFACE_INDEX_2, USB_CDC_VCOM_CIC_INTERFACE_2_ALTERNATE_0,
+ USB_CDC_VCOM_CIC_ENDPOINT_COUNT_2, USB_CDC_VCOM_CIC_CLASS, USB_CDC_VCOM_CIC_SUBCLASS, USB_CDC_VCOM_CIC_PROTOCOL,
+ 0x00,
+
+ /* CDC Class-Specific descriptor */
+ USB_DESCRIPTOR_LENGTH_CDC_HEADER_FUNC, /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */
+ USB_CDC_HEADER_FUNC_DESC, 0x10,
+ 0x01, /* USB Class Definitions for Communications the Communication specification version 1.10 */
+
+ USB_DESCRIPTOR_LENGTH_CDC_CALL_MANAG, /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */
+ USB_CDC_CALL_MANAGEMENT_FUNC_DESC,
+ 0x01, /*Bit 0: Whether device handle call management itself 1, Bit 1: Whether device can send/receive call
+ management information over a Data Class Interface 0 */
+ 0x01, /* Indicates multiplexed commands are handled via data interface */
+
+ USB_DESCRIPTOR_LENGTH_CDC_ABSTRACT, /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */
+ USB_CDC_ABSTRACT_CONTROL_FUNC_DESC,
+ 0x06, /* Bit 0: Whether device supports the request combination of Set_Comm_Feature, Clear_Comm_Feature, and
+ Get_Comm_Feature 0, Bit 1: Whether device supports the request combination of Set_Line_Coding,
+ Set_Control_Line_State, Get_Line_Coding, and the notification Serial_State 1, Bit ... */
+
+ USB_DESCRIPTOR_LENGTH_CDC_UNION_FUNC, /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */
+ USB_CDC_UNION_FUNC_DESC,
+ USB_CDC_VCOM_CIC_INTERFACE_INDEX_2, /* The interface number of the Communications or Data Class interface */
+ USB_CDC_VCOM_DIC_INTERFACE_INDEX_2, /* Interface number of subordinate interface in the Union */
+
+ /*Notification Endpoint descriptor */
+ USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT,
+ USB_CDC_VCOM_CIC_INTERRUPT_IN_ENDPOINT_2 | (USB_IN << 7U), USB_ENDPOINT_INTERRUPT,
+ USB_SHORT_GET_LOW(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE_2),
+ USB_SHORT_GET_HIGH(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE_2), FS_CDC_VCOM_INTERRUPT_IN_INTERVAL_2,
+
+ /* Data Interface Descriptor */
+ USB_DESCRIPTOR_LENGTH_INTERFACE, USB_DESCRIPTOR_TYPE_INTERFACE, USB_CDC_VCOM_DIC_INTERFACE_INDEX_2, USB_CDC_VCOM_DIC_INTERFACE_2_ALTERNATE_0,
+ USB_CDC_VCOM_DIC_ENDPOINT_COUNT_2, USB_CDC_VCOM_DIC_CLASS, USB_CDC_VCOM_DIC_SUBCLASS, USB_CDC_VCOM_DIC_PROTOCOL,
+ 0x00, /* Interface Description String Index*/
+
+ /*Bulk IN Endpoint descriptor */
+ USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT, USB_CDC_VCOM_DIC_BULK_IN_ENDPOINT_2 | (USB_IN << 7U),
+ USB_ENDPOINT_BULK, USB_SHORT_GET_LOW(FS_CDC_VCOM_BULK_IN_PACKET_SIZE_2),
+ USB_SHORT_GET_HIGH(FS_CDC_VCOM_BULK_IN_PACKET_SIZE_2), 0x00, /* The polling interval value is every 0 Frames */
+
+ /*Bulk OUT Endpoint descriptor */
+ USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT,
+ USB_CDC_VCOM_DIC_BULK_OUT_ENDPOINT_2 | (USB_OUT << 7U), USB_ENDPOINT_BULK,
+ USB_SHORT_GET_LOW(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE_2), USB_SHORT_GET_HIGH(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE_2),
+ 0x00, /* The polling interval value is every 0 Frames */
+};
+#if (defined(USB_DEVICE_CONFIG_CV_TEST) && (USB_DEVICE_CONFIG_CV_TEST > 0U))
+USB_DMA_INIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE)
+uint8_t g_UsbDeviceQualifierDescriptor[USB_DESCRIPTOR_LENGTH_DEVICE_QUALITIER] = {
+ USB_DESCRIPTOR_LENGTH_DEVICE_QUALITIER, /* Size of this descriptor in bytes */
+ USB_DESCRIPTOR_TYPE_DEVICE_QUALITIER, /* DEVICE Descriptor Type */
+ USB_SHORT_GET_LOW(USB_DEVICE_SPECIFIC_BCD_VERSION),
+ USB_SHORT_GET_HIGH(USB_DEVICE_SPECIFIC_BCD_VERSION), /* USB Specification Release Number in
+ Binary-Coded Decimal (i.e., 2.10 is 210H). */
+ USB_DEVICE_CLASS, /* Class code (assigned by the USB-IF). */
+ USB_DEVICE_SUBCLASS, /* Subclass code (assigned by the USB-IF). */
+ USB_DEVICE_PROTOCOL, /* Protocol code (assigned by the USB-IF). */
+ USB_CONTROL_MAX_PACKET_SIZE, /* Maximum packet size for endpoint zero
+ (only 8, 16, 32, or 64 are valid) */
+ 0x00U, /* Number of Other-speed Configurations */
+ 0x00U, /* Reserved for future use, must be zero */
+};
+#endif
+/* Define string descriptor */
+USB_DMA_INIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE)
+uint8_t g_UsbDeviceString0[] = {
+ 2U + 2U,
+ USB_DESCRIPTOR_TYPE_STRING,
+ 0x09,
+ 0x04,
+};
+
+USB_DMA_INIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE)
+uint8_t g_UsbDeviceString1[] = {
+ 2U + 2U * 18U, USB_DESCRIPTOR_TYPE_STRING,
+ 'N', 0x00U,
+ 'X', 0x00U,
+ 'P', 0x00U,
+ ' ', 0x00U,
+ 'S', 0x00U,
+ 'E', 0x00U,
+ 'M', 0x00U,
+ 'I', 0x00U,
+ 'C', 0x00U,
+ 'O', 0x00U,
+ 'N', 0x00U,
+ 'D', 0x00U,
+ 'U', 0x00U,
+ 'C', 0x00U,
+ 'T', 0x00U,
+ 'O', 0x00U,
+ 'R', 0x00U,
+ 'S', 0x00U,
+};
+
+USB_DMA_INIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE)
+uint8_t g_UsbDeviceString2[] = {2U + 2U * 18U, USB_DESCRIPTOR_TYPE_STRING,
+ 'U', 0,
+ 'S', 0,
+ 'B', 0,
+ ' ', 0,
+ 'C', 0,
+ 'O', 0,
+ 'M', 0,
+ 'P', 0,
+ 'O', 0,
+ 'S', 0,
+ 'I', 0,
+ 'T', 0,
+ 'E', 0,
+ ' ', 0,
+ 'D', 0,
+ 'E', 0,
+ 'M', 0,
+ 'O', 0};
+
+USB_DMA_INIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE)
+uint8_t g_UsbDeviceString3[] = {2U + 2U * 16U, USB_DESCRIPTOR_TYPE_STRING,
+ '0', 0x00U,
+ '1', 0x00U,
+ '2', 0x00U,
+ '3', 0x00U,
+ '4', 0x00U,
+ '5', 0x00U,
+ '6', 0x00U,
+ '7', 0x00U,
+ '8', 0x00U,
+ '9', 0x00U,
+ 'A', 0x00U,
+ 'B', 0x00U,
+ 'C', 0x00U,
+ 'D', 0x00U,
+ 'E', 0x00U,
+ 'F', 0x00U};
+
+USB_DMA_INIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE)
+uint8_t g_UsbDeviceString4[] = {2U + 2U * 17U, USB_DESCRIPTOR_TYPE_STRING,
+ 'M', 0,
+ 'C', 0,
+ 'U', 0,
+ ' ', 0,
+ 'C', 0,
+ 'D', 0,
+ 'C', 0,
+ ' ', 0,
+ 'C', 0,
+ 'D', 0,
+ 'C', 0,
+ '2', 0,
+ ' ', 0,
+ 'D', 0,
+ 'E', 0,
+ 'M', 0,
+ 'O', 0};
+
+/* Define string descriptor size */
+uint32_t g_UsbDeviceStringDescriptorLength[USB_DEVICE_STRING_COUNT] = {
+ sizeof(g_UsbDeviceString0), sizeof(g_UsbDeviceString1), sizeof(g_UsbDeviceString2), sizeof(g_UsbDeviceString3),
+ sizeof(g_UsbDeviceString4)};
+
+uint8_t *g_UsbDeviceStringDescriptorArray[USB_DEVICE_STRING_COUNT] = {
+ g_UsbDeviceString0, g_UsbDeviceString1, g_UsbDeviceString2, g_UsbDeviceString3, g_UsbDeviceString4};
+
+usb_language_t g_UsbDeviceLanguage[USB_DEVICE_LANGUAGE_COUNT] = {{
+ g_UsbDeviceStringDescriptorArray,
+ g_UsbDeviceStringDescriptorLength,
+ (uint16_t)0x0409,
+}};
+
+usb_language_list_t g_UsbDeviceLanguageList = {
+ g_UsbDeviceString0,
+ sizeof(g_UsbDeviceString0),
+ g_UsbDeviceLanguage,
+ USB_DEVICE_LANGUAGE_COUNT,
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief USB device get device descriptor function.
+ *
+ * This function gets the device descriptor of the USB device.
+ *
+ * @param handle The USB device handle.
+ * @param deviceDescriptor The pointer to the device descriptor structure.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceGetDeviceDescriptor(usb_device_handle handle,
+ usb_device_get_device_descriptor_struct_t *deviceDescriptor)
+{
+ deviceDescriptor->buffer = g_UsbDeviceDescriptor;
+ deviceDescriptor->length = USB_DESCRIPTOR_LENGTH_DEVICE;
+ return kStatus_USB_Success;
+}
+#if (defined(USB_DEVICE_CONFIG_CV_TEST) && (USB_DEVICE_CONFIG_CV_TEST > 0U))
+/* Get device qualifier descriptor request */
+usb_status_t USB_DeviceGetDeviceQualifierDescriptor(
+ usb_device_handle handle, usb_device_get_device_qualifier_descriptor_struct_t *deviceQualifierDescriptor)
+{
+ deviceQualifierDescriptor->buffer = g_UsbDeviceQualifierDescriptor;
+ deviceQualifierDescriptor->length = USB_DESCRIPTOR_LENGTH_DEVICE_QUALITIER;
+ return kStatus_USB_Success;
+}
+#endif
+/*!
+ * @brief USB device get configuration descriptor function.
+ *
+ * This function gets the configuration descriptor of the USB device.
+ *
+ * @param handle The USB device handle.
+ * @param configurationDescriptor The pointer to the configuration descriptor structure.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceGetConfigurationDescriptor(
+ usb_device_handle handle, usb_device_get_configuration_descriptor_struct_t *configurationDescriptor)
+{
+ if (USB_COMPOSITE_CONFIGURE_INDEX > configurationDescriptor->configuration)
+ {
+ configurationDescriptor->buffer = g_UsbDeviceConfigurationDescriptor;
+ configurationDescriptor->length = USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL;
+ return kStatus_USB_Success;
+ }
+ return kStatus_USB_InvalidRequest;
+}
+
+/*!
+ * @brief USB device get string descriptor function.
+ *
+ * This function gets the string descriptor of the USB device.
+ *
+ * @param handle The USB device handle.
+ * @param stringDescriptor Pointer to the string descriptor structure.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceGetStringDescriptor(usb_device_handle handle,
+ usb_device_get_string_descriptor_struct_t *stringDescriptor)
+{
+ if (stringDescriptor->stringIndex == 0)
+ {
+ stringDescriptor->buffer = (uint8_t *)g_UsbDeviceLanguageList.languageString;
+ stringDescriptor->length = g_UsbDeviceLanguageList.stringLength;
+ }
+ else
+ {
+ uint8_t langId = 0;
+ uint8_t langIndex = USB_DEVICE_STRING_COUNT;
+
+ for (; langId < USB_DEVICE_LANGUAGE_COUNT; langId++)
+ {
+ if (stringDescriptor->languageId == g_UsbDeviceLanguageList.languageList[langId].languageId)
+ {
+ if (stringDescriptor->stringIndex < USB_DEVICE_STRING_COUNT)
+ {
+ langIndex = stringDescriptor->stringIndex;
+ }
+ break;
+ }
+ }
+
+ if (USB_DEVICE_STRING_COUNT == langIndex)
+ {
+ return kStatus_USB_InvalidRequest;
+ }
+ stringDescriptor->buffer = (uint8_t *)g_UsbDeviceLanguageList.languageList[langId].string[langIndex];
+ stringDescriptor->length = g_UsbDeviceLanguageList.languageList[langId].length[langIndex];
+ }
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief USB device set speed function.
+ *
+ * This function sets the speed of the USB device.
+ *
+ * Due to the difference of HS and FS descriptors, the device descriptors and configurations need to be updated to match
+ * current speed.
+ * As the default, the device descriptors and configurations are configured by using FS parameters for both EHCI and
+ * KHCI.
+ * When the EHCI is enabled, the application needs to call this function to update device by using current speed.
+ * The updated information includes endpoint max packet size, endpoint interval, etc.
+ *
+ * @param handle The USB device handle.
+ * @param speed Speed type. USB_SPEED_HIGH/USB_SPEED_FULL/USB_SPEED_LOW.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceSetSpeed(usb_device_handle handle, uint8_t speed)
+{
+ usb_descriptor_union_t *ptr1;
+ usb_descriptor_union_t *ptr2;
+
+ ptr1 = (usb_descriptor_union_t *)(&g_UsbDeviceConfigurationDescriptor[0]);
+ ptr2 = (usb_descriptor_union_t *)(&g_UsbDeviceConfigurationDescriptor[USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL - 1]);
+
+ while (ptr1 < ptr2)
+ {
+ if (ptr1->common.bDescriptorType == USB_DESCRIPTOR_TYPE_ENDPOINT)
+ {
+ if (USB_SPEED_HIGH == speed)
+ {
+ if ((USB_CDC_VCOM_CIC_INTERRUPT_IN_ENDPOINT ==
+ (ptr1->endpoint.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)) &&
+ ((ptr1->endpoint.bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) ==
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN))
+ {
+ ptr1->endpoint.bInterval = HS_CDC_VCOM_INTERRUPT_IN_INTERVAL;
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE,
+ ptr1->endpoint.wMaxPacketSize);
+ }
+ else if ((USB_CDC_VCOM_DIC_BULK_IN_ENDPOINT ==
+ (ptr1->endpoint.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)) &&
+ ((ptr1->endpoint.bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) ==
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN))
+ {
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_BULK_IN_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize);
+ }
+ else if ((USB_CDC_VCOM_DIC_BULK_OUT_ENDPOINT ==
+ (ptr1->endpoint.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)) &&
+ ((ptr1->endpoint.bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) ==
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_OUT))
+ {
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_BULK_OUT_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize);
+ }
+ else if ((USB_CDC_VCOM_CIC_INTERRUPT_IN_ENDPOINT_2 ==
+ (ptr1->endpoint.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)) &&
+ ((ptr1->endpoint.bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) ==
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN))
+ {
+ ptr1->endpoint.bInterval = HS_CDC_VCOM_INTERRUPT_IN_INTERVAL_2;
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE_2,
+ ptr1->endpoint.wMaxPacketSize);
+ }
+ else if ((USB_CDC_VCOM_DIC_BULK_IN_ENDPOINT_2 ==
+ (ptr1->endpoint.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)) &&
+ ((ptr1->endpoint.bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) ==
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN))
+ {
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_BULK_IN_PACKET_SIZE_2,
+ ptr1->endpoint.wMaxPacketSize);
+ }
+ else if ((USB_CDC_VCOM_DIC_BULK_OUT_ENDPOINT_2 ==
+ (ptr1->endpoint.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)) &&
+ ((ptr1->endpoint.bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) ==
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_OUT))
+ {
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_BULK_OUT_PACKET_SIZE_2,
+ ptr1->endpoint.wMaxPacketSize);
+ }
+ else
+ {
+ }
+ }
+ else
+ {
+ if ((USB_CDC_VCOM_CIC_INTERRUPT_IN_ENDPOINT ==
+ (ptr1->endpoint.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)) &&
+ ((ptr1->endpoint.bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) ==
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN))
+ {
+ ptr1->endpoint.bInterval = FS_CDC_VCOM_INTERRUPT_IN_INTERVAL;
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE,
+ ptr1->endpoint.wMaxPacketSize);
+ }
+ else if ((USB_CDC_VCOM_DIC_BULK_IN_ENDPOINT ==
+ (ptr1->endpoint.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)) &&
+ ((ptr1->endpoint.bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) ==
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN))
+ {
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_BULK_IN_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize);
+ }
+ else if ((USB_CDC_VCOM_DIC_BULK_OUT_ENDPOINT ==
+ (ptr1->endpoint.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)) &&
+ ((ptr1->endpoint.bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) ==
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_OUT))
+ {
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize);
+ }
+ else if ((USB_CDC_VCOM_CIC_INTERRUPT_IN_ENDPOINT_2 ==
+ (ptr1->endpoint.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)) &&
+ ((ptr1->endpoint.bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) ==
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN))
+ {
+ ptr1->endpoint.bInterval = FS_CDC_VCOM_INTERRUPT_IN_INTERVAL_2;
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE_2,
+ ptr1->endpoint.wMaxPacketSize);
+ }
+ else if ((USB_CDC_VCOM_DIC_BULK_IN_ENDPOINT_2 ==
+ (ptr1->endpoint.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)) &&
+ ((ptr1->endpoint.bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) ==
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN))
+ {
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_BULK_IN_PACKET_SIZE_2,
+ ptr1->endpoint.wMaxPacketSize);
+ }
+ else if ((USB_CDC_VCOM_DIC_BULK_OUT_ENDPOINT_2 ==
+ (ptr1->endpoint.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)) &&
+ ((ptr1->endpoint.bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) ==
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_OUT))
+ {
+ USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE_2,
+ ptr1->endpoint.wMaxPacketSize);
+ }
+ else
+ {
+ }
+ }
+ }
+ ptr1 = (usb_descriptor_union_t *)((uint8_t *)ptr1 + ptr1->common.bLength);
+ }
+
+ for (int i = 0; i < USB_CDC_VCOM_CIC_ENDPOINT_COUNT; i++)
+ {
+ if (USB_SPEED_HIGH == speed)
+ {
+ g_cdcVcomCicEndpoints[i].maxPacketSize = HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE;
+ g_cdcVcomCicEndpoints[i].interval = HS_CDC_VCOM_INTERRUPT_IN_INTERVAL;
+ }
+ else
+ {
+ g_cdcVcomCicEndpoints[i].maxPacketSize = FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE;
+ g_cdcVcomCicEndpoints[i].interval = FS_CDC_VCOM_INTERRUPT_IN_INTERVAL;
+ }
+ }
+
+ for (int i = 0; i < USB_CDC_VCOM_DIC_ENDPOINT_COUNT; i++)
+ {
+ if (USB_SPEED_HIGH == speed)
+ {
+ if (g_cdcVcomDicEndpoints[i].endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK)
+ {
+ g_cdcVcomDicEndpoints[i].maxPacketSize = HS_CDC_VCOM_BULK_IN_PACKET_SIZE;
+ }
+ else
+ {
+ g_cdcVcomDicEndpoints[i].maxPacketSize = HS_CDC_VCOM_BULK_OUT_PACKET_SIZE;
+ }
+ }
+ else
+ {
+ if (g_cdcVcomDicEndpoints[i].endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK)
+ {
+ g_cdcVcomDicEndpoints[i].maxPacketSize = FS_CDC_VCOM_BULK_IN_PACKET_SIZE;
+ }
+ else
+ {
+ g_cdcVcomDicEndpoints[i].maxPacketSize = FS_CDC_VCOM_BULK_OUT_PACKET_SIZE;
+ }
+ }
+ }
+
+ for (int i = 0; i < USB_CDC_VCOM_CIC_ENDPOINT_COUNT_2; i++)
+ {
+ if (USB_SPEED_HIGH == speed)
+ {
+ g_cdcVcomCicEndpoints_2[i].maxPacketSize = HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE_2;
+ g_cdcVcomCicEndpoints_2[i].interval = HS_CDC_VCOM_INTERRUPT_IN_INTERVAL_2;
+ }
+ else
+ {
+ g_cdcVcomCicEndpoints_2[i].maxPacketSize = FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE_2;
+ g_cdcVcomCicEndpoints_2[i].interval = FS_CDC_VCOM_INTERRUPT_IN_INTERVAL_2;
+ }
+ }
+
+ for (int i = 0; i < USB_CDC_VCOM_DIC_ENDPOINT_COUNT_2; i++)
+ {
+ if (USB_SPEED_HIGH == speed)
+ {
+ if (g_cdcVcomDicEndpoints_2[i].endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK)
+ {
+ g_cdcVcomDicEndpoints_2[i].maxPacketSize = HS_CDC_VCOM_BULK_IN_PACKET_SIZE_2;
+ }
+ else
+ {
+ g_cdcVcomDicEndpoints_2[i].maxPacketSize = HS_CDC_VCOM_BULK_OUT_PACKET_SIZE_2;
+ }
+ }
+ else
+ {
+ if (g_cdcVcomDicEndpoints_2[i].endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK)
+ {
+ g_cdcVcomDicEndpoints_2[i].maxPacketSize = FS_CDC_VCOM_BULK_IN_PACKET_SIZE_2;
+ }
+ else
+ {
+ g_cdcVcomDicEndpoints_2[i].maxPacketSize = FS_CDC_VCOM_BULK_OUT_PACKET_SIZE_2;
+ }
+ }
+ }
+
+ return kStatus_USB_Success;
+}
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/usb_device_descriptor.h b/minimal-examples/embedded/rt595/hello_world/project/source/usb_device_descriptor.h
new file mode 100644
index 000000000..51cdc571a
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/source/usb_device_descriptor.h
@@ -0,0 +1,244 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _USB_DEVICE_DESCRIPTOR_H_
+#define _USB_DEVICE_DESCRIPTOR_H_ 1
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define USB_DEVICE_SPECIFIC_BCD_VERSION (0x0200)
+#define USB_DEVICE_DEMO_BCD_VERSION (0x0101U)
+
+#define USB_DEVICE_VID (0x1FC9U)
+#define USB_DEVICE_PID (0x00A3U)
+
+/* Communication Class SubClass Codes */
+#define USB_CDC_DIRECT_LINE_CONTROL_MODEL (0x01)
+#define USB_CDC_ABSTRACT_CONTROL_MODEL (0x02)
+#define USB_CDC_TELEPHONE_CONTROL_MODEL (0x03)
+#define USB_CDC_MULTI_CHANNEL_CONTROL_MODEL (0x04)
+#define USB_CDC_CAPI_CONTROL_MOPDEL (0x05)
+#define USB_CDC_ETHERNET_NETWORKING_CONTROL_MODEL (0x06)
+#define USB_CDC_ATM_NETWORKING_CONTROL_MODEL (0x07)
+#define USB_CDC_WIRELESS_HANDSET_CONTROL_MODEL (0x08)
+#define USB_CDC_DEVICE_MANAGEMENT (0x09)
+#define USB_CDC_MOBILE_DIRECT_LINE_MODEL (0x0A)
+#define USB_CDC_OBEX (0x0B)
+#define USB_CDC_ETHERNET_EMULATION_MODEL (0x0C)
+
+/* Communication Class Protocol Codes */
+#define USB_CDC_NO_CLASS_SPECIFIC_PROTOCOL (0x00) /*also for Data Class Protocol Code */
+#define USB_CDC_AT_250_PROTOCOL (0x01)
+#define USB_CDC_AT_PCCA_101_PROTOCOL (0x02)
+#define USB_CDC_AT_PCCA_101_ANNEX_O (0x03)
+#define USB_CDC_AT_GSM_7_07 (0x04)
+#define USB_CDC_AT_3GPP_27_007 (0x05)
+#define USB_CDC_AT_TIA_CDMA (0x06)
+#define USB_CDC_ETHERNET_EMULATION_PROTOCOL (0x07)
+#define USB_CDC_EXTERNAL_PROTOCOL (0xFE)
+#define USB_CDC_VENDOR_SPECIFIC (0xFF) /*also for Data Class Protocol Code */
+
+/* Data Class Protocol Codes */
+#define USB_CDC_PYHSICAL_INTERFACE_PROTOCOL (0x30)
+#define USB_CDC_HDLC_PROTOCOL (0x31)
+#define USB_CDC_TRANSPARENT_PROTOCOL (0x32)
+#define USB_CDC_MANAGEMENT_PROTOCOL (0x50)
+#define USB_CDC_DATA_LINK_Q931_PROTOCOL (0x51)
+#define USB_CDC_DATA_LINK_Q921_PROTOCOL (0x52)
+#define USB_CDC_DATA_COMPRESSION_V42BIS (0x90)
+#define USB_CDC_EURO_ISDN_PROTOCOL (0x91)
+#define USB_CDC_RATE_ADAPTION_ISDN_V24 (0x92)
+#define USB_CDC_CAPI_COMMANDS (0x93)
+#define USB_CDC_HOST_BASED_DRIVER (0xFD)
+#define USB_CDC_UNIT_FUNCTIONAL (0xFE)
+
+/* Descriptor SubType in Communications Class Functional Descriptors */
+#define USB_CDC_HEADER_FUNC_DESC (0x00)
+#define USB_CDC_CALL_MANAGEMENT_FUNC_DESC (0x01)
+#define USB_CDC_ABSTRACT_CONTROL_FUNC_DESC (0x02)
+#define USB_CDC_DIRECT_LINE_FUNC_DESC (0x03)
+#define USB_CDC_TELEPHONE_RINGER_FUNC_DESC (0x04)
+#define USB_CDC_TELEPHONE_REPORT_FUNC_DESC (0x05)
+#define USB_CDC_UNION_FUNC_DESC (0x06)
+#define USB_CDC_COUNTRY_SELECT_FUNC_DESC (0x07)
+#define USB_CDC_TELEPHONE_MODES_FUNC_DESC (0x08)
+#define USB_CDC_TERMINAL_FUNC_DESC (0x09)
+#define USB_CDC_NETWORK_CHANNEL_FUNC_DESC (0x0A)
+#define USB_CDC_PROTOCOL_UNIT_FUNC_DESC (0x0B)
+#define USB_CDC_EXTENSION_UNIT_FUNC_DESC (0x0C)
+#define USB_CDC_MULTI_CHANNEL_FUNC_DESC (0x0D)
+#define USB_CDC_CAPI_CONTROL_FUNC_DESC (0x0E)
+#define USB_CDC_ETHERNET_NETWORKING_FUNC_DESC (0x0F)
+#define USB_CDC_ATM_NETWORKING_FUNC_DESC (0x10)
+#define USB_CDC_WIRELESS_CONTROL_FUNC_DESC (0x11)
+#define USB_CDC_MOBILE_DIRECT_LINE_FUNC_DESC (0x12)
+#define USB_CDC_MDLM_DETAIL_FUNC_DESC (0x13)
+#define USB_CDC_DEVICE_MANAGEMENT_FUNC_DESC (0x14)
+#define USB_CDC_OBEX_FUNC_DESC (0x15)
+#define USB_CDC_COMMAND_SET_FUNC_DESC (0x16)
+#define USB_CDC_COMMAND_SET_DETAIL_FUNC_DESC (0x17)
+#define USB_CDC_TELEPHONE_CONTROL_FUNC_DESC (0x18)
+#define USB_CDC_OBEX_SERVICE_ID_FUNC_DESC (0x19)
+
+/* usb descriptor length */
+#define USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL (sizeof(g_UsbDeviceConfigurationDescriptor))
+#define USB_CDC_VCOM_REPORT_DESCRIPTOR_LENGTH (33)
+#define USB_IAD_DESC_SIZE (8)
+#define USB_DESCRIPTOR_LENGTH_CDC_HEADER_FUNC (5)
+#define USB_DESCRIPTOR_LENGTH_CDC_CALL_MANAG (5)
+#define USB_DESCRIPTOR_LENGTH_CDC_ABSTRACT (4)
+#define USB_DESCRIPTOR_LENGTH_CDC_UNION_FUNC (5)
+
+#define USB_DEVICE_CONFIGURATION_COUNT (1)
+#define USB_DEVICE_STRING_COUNT (5)
+#define USB_DEVICE_LANGUAGE_COUNT (1)
+#define USB_INTERFACE_COUNT (4)
+
+#define USB_COMPOSITE_CONFIGURE_INDEX (1)
+
+#define USB_MSC_DISK_CLASS (0x08)
+/* scsi command set */
+#define USB_MSC_DISK_SUBCLASS (0x06)
+/* bulk only transport protocol */
+#define USB_MSC_DISK_PROTOCOL (0x50)
+
+/* Configuration, interface and endpoint. */
+#define USB_CDC_VCOM_CIC_CLASS (0x02)
+#define USB_CDC_VCOM_CIC_SUBCLASS (0x02)
+#define USB_CDC_VCOM_CIC_PROTOCOL (0x00)
+#define USB_CDC_VCOM_DIC_CLASS (0x0A)
+#define USB_CDC_VCOM_DIC_SUBCLASS (0x00)
+#define USB_CDC_VCOM_DIC_PROTOCOL (0x00)
+
+#define USB_CDC_VCOM_INTERFACE_COUNT (2)
+#define USB_CDC_VCOM_INTERFACE_COUNT_2 (2)
+#define USB_CDC_VCOM_CIC_INTERFACE_INDEX (0)
+#define USB_CDC_VCOM_DIC_INTERFACE_INDEX (1)
+#define USB_CDC_VCOM_CIC_INTERFACE_INDEX_2 (2)
+#define USB_CDC_VCOM_DIC_INTERFACE_INDEX_2 (3)
+#define USB_CDC_VCOM_CIC_INTERFACE_ALTERNATE_COUNT (1)
+#define USB_CDC_VCOM_DIC_INTERFACE_ALTERNATE_COUNT (1)
+#define USB_CDC_VCOM_CIC_INTERFACE_ALTERNATE_0 (0)
+#define USB_CDC_VCOM_DIC_INTERFACE_ALTERNATE_0 (0)
+#define USB_CDC_VCOM_CIC_INTERFACE_2_ALTERNATE_COUNT (1)
+#define USB_CDC_VCOM_DIC_INTERFACE_2_ALTERNATE_COUNT (1)
+#define USB_CDC_VCOM_CIC_INTERFACE_2_ALTERNATE_0 (0)
+#define USB_CDC_VCOM_DIC_INTERFACE_2_ALTERNATE_0 (0)
+#define USB_CDC_VCOM_CIC_ENDPOINT_COUNT (1)
+#define USB_CDC_VCOM_CIC_ENDPOINT_COUNT_2 (1)
+#define USB_CDC_VCOM_CIC_INTERRUPT_IN_ENDPOINT (1)
+#define USB_CDC_VCOM_CIC_INTERRUPT_IN_ENDPOINT_2 (2)
+#define USB_CDC_VCOM_DIC_ENDPOINT_COUNT (2)
+#define USB_CDC_VCOM_DIC_ENDPOINT_COUNT_2 (2)
+#define USB_CDC_VCOM_DIC_BULK_IN_ENDPOINT (3)
+#define USB_CDC_VCOM_DIC_BULK_OUT_ENDPOINT (3)
+#define USB_CDC_VCOM_DIC_BULK_IN_ENDPOINT_2 (4)
+#define USB_CDC_VCOM_DIC_BULK_OUT_ENDPOINT_2 (4)
+/* Packet size. */
+#define HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE (16)
+#define FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE (16)
+#define HS_CDC_VCOM_INTERRUPT_IN_INTERVAL (0x07) /* 2^(7-1) = 8ms */
+#define FS_CDC_VCOM_INTERRUPT_IN_INTERVAL (0x08)
+/* Packet size. */
+#define HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE_2 (16)
+#define FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE_2 (16)
+#define HS_CDC_VCOM_INTERRUPT_IN_INTERVAL_2 (0x07) /* 2^(7-1) = 8ms */
+#define FS_CDC_VCOM_INTERRUPT_IN_INTERVAL_2 (0x08)
+
+#define HS_CDC_VCOM_BULK_IN_PACKET_SIZE (512)
+#define FS_CDC_VCOM_BULK_IN_PACKET_SIZE (64)
+#define HS_CDC_VCOM_BULK_OUT_PACKET_SIZE (512)
+#define FS_CDC_VCOM_BULK_OUT_PACKET_SIZE (64)
+
+#define HS_CDC_VCOM_BULK_IN_PACKET_SIZE_2 (512)
+#define FS_CDC_VCOM_BULK_IN_PACKET_SIZE_2 (64)
+#define HS_CDC_VCOM_BULK_OUT_PACKET_SIZE_2 (512)
+#define FS_CDC_VCOM_BULK_OUT_PACKET_SIZE_2 (64)
+/* String descriptor length. */
+#define USB_DESCRIPTOR_LENGTH_STRING0 (sizeof(g_UsbDeviceString0))
+#define USB_DESCRIPTOR_LENGTH_STRING1 (sizeof(g_UsbDeviceString1))
+#define USB_DESCRIPTOR_LENGTH_STRING2 (sizeof(g_UsbDeviceString2))
+#define USB_DESCRIPTOR_LENGTH_STRING3 (sizeof(g_UsbDeviceString3))
+#define USB_DESCRIPTOR_LENGTH_STRING4 (sizeof(g_UsbDeviceString4))
+
+#define USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE (0x24)
+#define USB_DESCRIPTOR_TYPE_CDC_CS_ENDPOINT (0x25)
+
+/* Class code. */
+#define USB_DEVICE_CLASS (0xEF)
+#define USB_DEVICE_SUBCLASS (0x02)
+#define USB_DEVICE_PROTOCOL (0x01)
+
+#define USB_DEVICE_MAX_POWER (0x32)
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+/*!
+ * @brief USB device set speed function.
+ *
+ * This function sets the speed of the USB device.
+ *
+ * Due to the difference of HS and FS descriptors, the device descriptors and configurations need to be updated to match
+ * current speed.
+ * As the default, the device descriptors and configurations are configured by using FS parameters for both EHCI and
+ * KHCI.
+ * When the EHCI is enabled, the application needs to call this function to update device by using current speed.
+ * The updated information includes endpoint max packet size, endpoint interval, etc.
+ *
+ * @param handle The USB device handle.
+ * @param speed Speed type. USB_SPEED_HIGH/USB_SPEED_FULL/USB_SPEED_LOW.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceSetSpeed(usb_device_handle handle, uint8_t speed);
+#if (defined(USB_DEVICE_CONFIG_CV_TEST) && (USB_DEVICE_CONFIG_CV_TEST > 0U))
+/* Get device qualifier descriptor request */
+usb_status_t USB_DeviceGetDeviceQualifierDescriptor(
+ usb_device_handle handle, usb_device_get_device_qualifier_descriptor_struct_t *deviceQualifierDescriptor);
+#endif
+/*!
+ * @brief USB device get device descriptor function.
+ *
+ * This function gets the device descriptor of the USB device.
+ *
+ * @param handle The USB device handle.
+ * @param deviceDescriptor The pointer to the device descriptor structure.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceGetDeviceDescriptor(usb_device_handle handle,
+ usb_device_get_device_descriptor_struct_t *deviceDescriptor);
+
+/*!
+ * @brief USB device get configuration descriptor function.
+ *
+ * This function gets the configuration descriptor of the USB device.
+ *
+ * @param handle The USB device handle.
+ * @param configurationDescriptor The pointer to the configuration descriptor structure.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceGetConfigurationDescriptor(
+ usb_device_handle handle, usb_device_get_configuration_descriptor_struct_t *configurationDescriptor);
+
+/*!
+ * @brief USB device get string descriptor function.
+ *
+ * This function gets the string descriptor of the USB device.
+ *
+ * @param handle The USB device handle.
+ * @param stringDescriptor Pointer to the string descriptor structure.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceGetStringDescriptor(usb_device_handle handle,
+ usb_device_get_string_descriptor_struct_t *stringDescriptor);
+
+#endif /* _USB_DEVICE_DESCRIPTOR_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/virtual_com.c b/minimal-examples/embedded/rt595/hello_world/project/source/virtual_com.c
new file mode 100644
index 000000000..5d34434ee
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/source/virtual_com.c
@@ -0,0 +1,485 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <stdio.h>
+#include <stdlib.h>
+/*${standard_header_anchor}*/
+#include "fsl_device_registers.h"
+#include "clock_config.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+
+#include "usb_device_config.h"
+#include "usb.h"
+#include "usb_device.h"
+
+#include "usb_device_class.h"
+#include "usb_device_cdc_acm.h"
+#include "usb_device_ch9.h"
+
+#include "usb_device_descriptor.h"
+#include "composite.h"
+
+#include "private.h"
+#include <string.h>
+
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+#include "usb_phy.h"
+#endif
+
+lws_dll2_owner_t scheduler;
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+extern usb_device_endpoint_struct_t g_cdcVcomDicEndpoints[];
+extern usb_device_endpoint_struct_t g_cdcVcomDicEndpoints_2[];
+extern usb_device_endpoint_struct_t g_cdcVcomCicEndpoints[];
+extern usb_device_endpoint_struct_t g_cdcVcomCicEndpoints_2[];
+extern usb_device_class_struct_t g_UsbDeviceCdcVcomConfig[2];
+/* Line coding of cdc device */
+USB_DMA_INIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE)
+static uint8_t s_lineCoding[USB_DEVICE_CONFIG_CDC_ACM][LINE_CODING_SIZE] = {
+ {/* E.g. 0x00,0xC2,0x01,0x00 : 0x0001C200 is 115200 bits per second */
+ (LINE_CODING_DTERATE >> 0U) & 0x000000FFU, (LINE_CODING_DTERATE >> 8U) & 0x000000FFU,
+ (LINE_CODING_DTERATE >> 16U) & 0x000000FFU, (LINE_CODING_DTERATE >> 24U) & 0x000000FFU, LINE_CODING_CHARFORMAT,
+ LINE_CODING_PARITYTYPE, LINE_CODING_DATABITS},
+ {/* E.g. 0x00,0xC2,0x01,0x00 : 0x0001C200 is 115200 bits per second */
+ (LINE_CODING_DTERATE >> 0U) & 0x000000FFU, (LINE_CODING_DTERATE >> 8U) & 0x000000FFU,
+ (LINE_CODING_DTERATE >> 16U) & 0x000000FFU, (LINE_CODING_DTERATE >> 24U) & 0x000000FFU, LINE_CODING_CHARFORMAT,
+ LINE_CODING_PARITYTYPE, LINE_CODING_DATABITS},
+};
+
+/* Abstract state of cdc device */
+USB_DMA_INIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE)
+static uint8_t s_abstractState[USB_DEVICE_CONFIG_CDC_ACM][COMM_FEATURE_DATA_SIZE] = {
+ {(STATUS_ABSTRACT_STATE >> 0U) & 0x00FFU, (STATUS_ABSTRACT_STATE >> 8U) & 0x00FFU},
+ {(STATUS_ABSTRACT_STATE >> 0U) & 0x00FFU, (STATUS_ABSTRACT_STATE >> 8U) & 0x00FFU},
+};
+
+/* Country code of cdc device */
+USB_DMA_INIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE)
+static uint8_t s_countryCode[USB_DEVICE_CONFIG_CDC_ACM][COMM_FEATURE_DATA_SIZE] = {
+ {(COUNTRY_SETTING >> 0U) & 0x00FFU, (COUNTRY_SETTING >> 8U) & 0x00FFU},
+ {(COUNTRY_SETTING >> 0U) & 0x00FFU, (COUNTRY_SETTING >> 8U) & 0x00FFU},
+};
+
+/* CDC ACM information */
+USB_DMA_INIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE)
+usb_cdc_acm_info_t s_usbCdcAcmInfo[USB_DEVICE_CONFIG_CDC_ACM] = {
+ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 0, 0, 0, 0},
+ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 0, 0, 0, 0},
+};
+/* Data buffer for receiving and sending*/
+USB_DMA_NONINIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE)
+ static uint8_t s_currRecvBuf[USB_DEVICE_CONFIG_CDC_ACM][DATA_BUFF_SIZE];
+USB_DMA_NONINIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE)
+ static uint8_t s_currSendBuf[USB_DEVICE_CONFIG_CDC_ACM][DATA_BUFF_SIZE];
+volatile static uint32_t s_recvSize[USB_DEVICE_CONFIG_CDC_ACM] = {0};
+volatile static uint32_t s_sendSize[USB_DEVICE_CONFIG_CDC_ACM] = {0};
+
+volatile static usb_device_composite_struct_t *g_deviceComposite;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief CDC class specific callback function.
+ *last_tick_low
+ * This function handles the CDC class specific requests.
+ *
+ * @param handle The CDC ACM class handle.
+ * @param event The CDC ACM class event type.
+ * @param param The parameter of the class specific request.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceCdcVcomCallback(class_handle_t handle, uint32_t event, void *param)
+{
+ uint32_t len;
+ uint8_t *uartBitmap;
+ usb_cdc_acm_info_t *acmInfo;
+ usb_device_cdc_acm_request_param_struct_t *acmReqParam;
+ usb_device_endpoint_callback_message_struct_t *epCbParam;
+ volatile usb_cdc_vcom_struct_t *vcomInstance;
+ usb_status_t error = kStatus_USB_InvalidRequest;
+ uint8_t i;
+ acmReqParam = (usb_device_cdc_acm_request_param_struct_t *)param;
+ epCbParam = (usb_device_endpoint_callback_message_struct_t *)param;
+
+ for (i = 0; i < USB_DEVICE_CONFIG_CDC_ACM; i++)
+ {
+ if (handle == g_deviceComposite->cdcVcom[i].cdcAcmHandle)
+ {
+ break;
+ }
+ }
+ if (i >= USB_DEVICE_CONFIG_CDC_ACM)
+ {
+ return error;
+ }
+ vcomInstance = &g_deviceComposite->cdcVcom[i];
+ acmInfo = vcomInstance->usbCdcAcmInfo;
+ switch (event)
+ {
+ case kUSB_DeviceCdcEventSendResponse:
+ {
+ if ((epCbParam->length != 0) && (!(epCbParam->length % vcomInstance->bulkInEndpointMaxPacketSize)))
+ {
+ /* If the last packet is the size of endpoint, then send also zero-ended packet,
+ ** meaning that we want to inform the host that we do not have any additional
+ ** data, so it can flush the output.
+ */
+ error = USB_DeviceCdcAcmSend(handle, vcomInstance->bulkInEndpoint, NULL, 0);
+ }
+ else if ((1 == vcomInstance->attach) && (1 == vcomInstance->startTransactions))
+ {
+ if ((epCbParam->buffer != NULL) || ((epCbParam->buffer == NULL) && (epCbParam->length == 0)))
+ {
+ /* User: add your own code for send complete event */
+ /* Schedule buffer for next receive event */
+ error = USB_DeviceCdcAcmRecv(handle, vcomInstance->bulkOutEndpoint, vcomInstance->currRecvBuf,
+ vcomInstance->bulkOutEndpointMaxPacketSize);
+ }
+ }
+ else
+ {
+ }
+ }
+ break;
+ case kUSB_DeviceCdcEventRecvResponse:
+ {
+ if ((1 == vcomInstance->attach) && (1 == vcomInstance->startTransactions))
+ {
+ vcomInstance->recvSize = epCbParam->length;
+
+ if (!vcomInstance->recvSize)
+ {
+ /* Schedule buffer for next rechttps://community.nxp.com/t5/LPCXpresso-IDE/CDC-BulkIn-in-USB-CDC-Example/td-p/550945eive event */
+ error = USB_DeviceCdcAcmRecv(handle, vcomInstance->bulkOutEndpoint, vcomInstance->currRecvBuf,
+ vcomInstance->bulkOutEndpointMaxPacketSize);
+ }
+ }
+ }
+ break;
+ case kUSB_DeviceCdcEventSerialStateNotif:
+ ((usb_device_cdc_acm_struct_t *)handle)->hasSentState = 0;
+ error = kStatus_USB_Success;
+ break;
+ case kUSB_DeviceCdcEventSendEncapsulatedCommand:
+ break;
+ case kUSB_DeviceCdcEventGetEncapsulatedResponse:
+ break;
+ case kUSB_DeviceCdcEventSetCommFeature:
+ if (USB_DEVICE_CDC_FEATURE_ABSTRACT_STATE == acmReqParam->setupValue)
+ {
+ if (1 == acmReqParam->isSetup)
+ {
+ *(acmReqParam->buffer) = vcomInstance->abstractState;
+ *(acmReqParam->length) = COMM_FEATURE_DATA_SIZE;
+ }
+ else
+ {
+ /* no action, data phase, s_abstractState has been assigned */
+ }
+ error = kStatus_USB_Success;
+ }
+ else if (USB_DEVICE_CDC_FEATURE_COUNTRY_SETTING == acmReqParam->setupValue)
+ {
+ if (1 == acmReqParam->isSetup)
+ {
+ *(acmReqParam->buffer) = vcomInstance->countryCode;
+ *(acmReqParam->length) = COMM_FEATURE_DATA_SIZE;
+ }
+ else
+ {
+ /* no action, data phase, s_countryCode has been assigned */
+ }
+ error = kStatus_USB_Success;
+ }
+ else
+ {
+ /* no action, return kStatus_USB_InvalidRequest */
+ }
+ break;
+ case kUSB_DeviceCdcEventGetCommFeature:
+ if (USB_DEVICE_CDC_FEATURE_ABSTRACT_STATE == acmReqParam->setupValue)
+ {
+ *(acmReqParam->buffer) = vcomInstance->abstractState;
+ *(acmReqParam->length) = COMM_FEATURE_DATA_SIZE;
+ error = kStatus_USB_Success;
+ }
+ else if (USB_DEVICE_CDC_FEATURE_COUNTRY_SETTING == acmReqParam->setupValue)
+ {
+ *(acmReqParam->buffer) = vcomInstance->countryCode;
+ *(acmReqParam->length) = COMM_FEATURE_DATA_SIZE;
+ error = kStatus_USB_Success;
+ }
+ else
+ {
+ /* no action, return kStatus_USB_InvalidRequest */
+ }
+ break;
+ case kUSB_DeviceCdcEventClearCommFeature:
+ break;
+ case kUSB_DeviceCdcEventGetLineCoding:
+ *(acmReqParam->buffer) = vcomInstance->lineCoding;
+ *(acmReqParam->length) = LINE_CODING_SIZE;
+ error = kStatus_USB_Success;
+ break;
+ case kUSB_DeviceCdcEventSetLineCoding:
+ {
+ if (1 == acmReqParam->isSetup)
+ {
+ *(acmReqParam->buffer) = vcomInstance->lineCoding;
+ *(acmReqParam->length) = LINE_CODING_SIZE;
+ }
+ else
+ {
+ /* no action, data phase, s_lineCoding has been assigned */
+ }
+ error = kStatus_USB_Success;
+ }
+ break;
+ case kUSB_DeviceCdcEventSetControlLineState:
+ {
+ error = kStatus_USB_Success;
+ vcomInstance->usbCdcAcmInfo->dteStatus = acmReqParam->setupValue;
+ /* activate/deactivate Tx carrier */
+ if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_CARRIER_ACTIVATION)
+ {
+ acmInfo->uartState |= USB_DEVICE_CDC_UART_STATE_TX_CARRIER;
+ }
+ else
+ {
+ acmInfo->uartState &= (uint16_t)~USB_DEVICE_CDC_UART_STATE_TX_CARRIER;
+ }
+
+ /* activate carrier and DTE. Com port of terminal tool running on PC is open now */
+ if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE)
+ {
+ acmInfo->uartState |= USB_DEVICE_CDC_UART_STATE_RX_CARRIER;
+ }
+ /* Com port of terminal tool running on PC is closed now */
+ else
+ {
+ acmInfo->uartState &= (uint16_t)~USB_DEVICE_CDC_UART_STATE_RX_CARRIER;
+ }
+
+ /* Indicates to DCE if DTE is present or not */
+ acmInfo->dtePresent = (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE) ? true : false;
+
+ /* Initialize the serial state buffer */
+ acmInfo->serialStateBuf[0] = NOTIF_REQUEST_TYPE; /* bmRequestType */
+ acmInfo->serialStateBuf[1] = USB_DEVICE_CDC_NOTIF_SERIAL_STATE; /* bNotification */
+ acmInfo->serialStateBuf[2] = 0x00; /* wValue */
+ acmInfo->serialStateBuf[3] = 0x00;
+ acmInfo->serialStateBuf[4] = 0x00; /* wIndex */
+ acmInfo->serialStateBuf[5] = 0x00;
+ acmInfo->serialStateBuf[6] = UART_BITMAP_SIZE; /* wLength */
+ acmInfo->serialStateBuf[7] = 0x00;
+ /* Notify to host the line state */
+ acmInfo->serialStateBuf[4] = acmReqParam->interfaceIndex;
+ /* Lower byte of UART BITMAP */
+ uartBitmap = (uint8_t *)&acmInfo->serialStateBuf[NOTIF_PACKET_SIZE + UART_BITMAP_SIZE - 2];
+ uartBitmap[0] = acmInfo->uartState & 0xFFu;
+ uartBitmap[1] = (acmInfo->uartState >> 8) & 0xFFu;
+ len = (uint32_t)(NOTIF_PACKET_SIZE + UART_BITMAP_SIZE);
+ if (0 == ((usb_device_cdc_acm_struct_t *)handle)->hasSentState)
+ {
+ error = USB_DeviceCdcAcmSend(handle, vcomInstance->interruptEndpoint, acmInfo->serialStateBuf, len);
+ if (kStatus_USB_Success != error)
+ {
+ usb_echo("kUSB_DeviceCdcEventSetControlLineState error!");
+ }
+ ((usb_device_cdc_acm_struct_t *)handle)->hasSentState = 1;
+ }
+
+ /* Update status */
+ if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_CARRIER_ACTIVATION)
+ {
+ /* To do: CARRIER_ACTIVATED */
+ }
+ else
+ {
+ /* To do: CARRIER_DEACTIVATED */
+ }
+ if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE)
+ {
+ /* DTE_ACTIVATED */
+ if (1 == vcomInstance->attach)
+ {
+ vcomInstance->startTransactions = 1;
+ }
+ }
+ else
+ {
+ /* DTE_DEACTIVATED */
+ if (1 == vcomInstance->attach)
+ {
+ vcomInstance->startTransactions = 0;
+ }
+ }
+ }
+ break;
+ case kUSB_DeviceCdcEventSendBreak:
+ break;
+ default:
+ break;
+ }
+
+ return error;
+}
+
+vcring_t vcr_log, vcr_txp_out, vcr_txp_in;
+
+
+extern usb_device_composite_struct_t g_composite;
+
+/*!
+ * @brief Application task function.
+ *
+ * This function runs the task for application.
+ *
+ * @return None.
+ */
+void USB_DeviceCdcVcomTask(void)
+{
+ usb_status_t error = kStatus_USB_Error;
+ volatile usb_cdc_vcom_struct_t *vci = &g_deviceComposite->cdcVcom[0];
+ const uint8_t *p;
+ size_t n;
+
+ /* emit logs on CDC 0 */
+
+ n = next_chonk(&vcr_log, &p);
+
+ if (vci->attach && vci->startTransactions && n) {
+
+ if (n > vci->bulkInEndpointMaxPacketSize)
+ n = vci->bulkInEndpointMaxPacketSize;
+
+ if (USB_DeviceCdcAcmSend(vci->cdcAcmHandle, vci->bulkInEndpoint, (uint8_t *)p, n) == kStatus_USB_Success)
+ consume_chonk(&vcr_log, n);
+ }
+
+ /* SS transport on CDC 1 */
+
+ vci++;
+ if (!vci->attach || !vci->startTransactions)
+ return;
+
+ if (vci->recvSize &&
+ USB_CANCELLED_TRANSFER_LENGTH != vci->recvSize) {
+ n = space_available(&vcr_txp_in);
+
+ // lwsl_warn("%s: len %u in", __func__, vci->recvSize);
+ // lwsl_hexdump_warn(vci->currRecvBuf, vci->recvSize);
+
+ n = tm->info.txp_cpath.ops_in->event_read(
+ tm->info.txp_cpath.priv_in, vci->currRecvBuf, vci->recvSize);
+ vci->recvSize = 0;
+ USB_DeviceSendRequest(g_composite.deviceHandle, vci->bulkOutEndpoint,0,0);
+ if (n) {
+ /*
+ * The SSS parser can identify the framing is broken,
+ * in that case the transport needs to re-link up
+ */
+ tm->info.txp_cpath.ops_in->lost_coherence(
+ tm->info.txp_cpath.priv_in);
+ }
+
+ }
+
+ n = next_chonk(&vcr_txp_out, &p);
+
+ if (vci->attach && vci->startTransactions && n) {
+
+ if (n > vci->bulkInEndpointMaxPacketSize)
+ n = vci->bulkInEndpointMaxPacketSize;
+
+ if (USB_DeviceCdcAcmSend(vci->cdcAcmHandle, vci->bulkInEndpoint, (uint8_t *)p, n) == kStatus_USB_Success)
+ consume_chonk(&vcr_txp_out, n);
+ }
+}
+
+/*!
+ * @brief Virtual COM device set configuration function.
+ *
+ * This function sets configuration for CDC class.
+ *
+ * @param handle The CDC ACM class handle.
+ * @param configure The CDC ACM class configure index.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceCdcVcomSetConfigure(class_handle_t handle, uint8_t configure)
+{
+ if (USB_COMPOSITE_CONFIGURE_INDEX == configure)
+ {
+ /*endpoint information for cdc 1*/
+ g_deviceComposite->cdcVcom[0].attach = 1;
+
+ g_deviceComposite->cdcVcom[0].interruptEndpoint = USB_CDC_VCOM_CIC_INTERRUPT_IN_ENDPOINT;
+ g_deviceComposite->cdcVcom[0].interruptEndpointMaxPacketSize = g_cdcVcomCicEndpoints[0].maxPacketSize;
+
+ g_deviceComposite->cdcVcom[0].bulkInEndpoint = USB_CDC_VCOM_DIC_BULK_IN_ENDPOINT;
+ g_deviceComposite->cdcVcom[0].bulkInEndpointMaxPacketSize = g_cdcVcomDicEndpoints[0].maxPacketSize;
+
+ g_deviceComposite->cdcVcom[0].bulkOutEndpoint = USB_CDC_VCOM_DIC_BULK_OUT_ENDPOINT;
+ g_deviceComposite->cdcVcom[0].bulkOutEndpointMaxPacketSize = g_cdcVcomDicEndpoints[1].maxPacketSize;
+
+ /* Schedule buffer for receive */
+ USB_DeviceCdcAcmRecv(g_deviceComposite->cdcVcom[0].cdcAcmHandle, g_deviceComposite->cdcVcom[0].bulkOutEndpoint,
+ s_currRecvBuf[0], g_deviceComposite->cdcVcom[0].bulkOutEndpointMaxPacketSize);
+
+ /*endpoint information for cdc 2*/
+ g_deviceComposite->cdcVcom[1].attach = 1;
+
+ g_deviceComposite->cdcVcom[1].interruptEndpoint = USB_CDC_VCOM_CIC_INTERRUPT_IN_ENDPOINT_2;
+ g_deviceComposite->cdcVcom[1].interruptEndpointMaxPacketSize = g_cdcVcomCicEndpoints_2[0].maxPacketSize;
+
+ g_deviceComposite->cdcVcom[1].bulkInEndpoint = USB_CDC_VCOM_DIC_BULK_IN_ENDPOINT_2;
+ g_deviceComposite->cdcVcom[1].bulkInEndpointMaxPacketSize = g_cdcVcomDicEndpoints_2[0].maxPacketSize;
+
+ g_deviceComposite->cdcVcom[1].bulkOutEndpoint = USB_CDC_VCOM_DIC_BULK_OUT_ENDPOINT_2;
+ g_deviceComposite->cdcVcom[1].bulkOutEndpointMaxPacketSize = g_cdcVcomDicEndpoints_2[1].maxPacketSize;
+
+ /* Schedule buffer for receive */
+ USB_DeviceCdcAcmRecv(g_deviceComposite->cdcVcom[1].cdcAcmHandle, g_deviceComposite->cdcVcom[1].bulkOutEndpoint,
+ s_currRecvBuf[1], g_deviceComposite->cdcVcom[1].bulkOutEndpointMaxPacketSize);
+ }
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Virtual COM device initialization function.
+ *
+ * This function initializes the device with the composite device class information.
+ *
+ * @param deviceComposite The pointer to the composite device structure.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceCdcVcomInit(usb_device_composite_struct_t *deviceComposite)
+{
+ g_deviceComposite = deviceComposite;
+ for (uint8_t i = 0; i < USB_DEVICE_CONFIG_CDC_ACM; i++)
+ {
+ g_deviceComposite->cdcVcom[i].lineCoding = (uint8_t *)&s_lineCoding[i];
+ g_deviceComposite->cdcVcom[i].abstractState = (uint8_t *)&s_abstractState[i];
+ g_deviceComposite->cdcVcom[i].countryCode = (uint8_t *)&s_countryCode[i];
+ g_deviceComposite->cdcVcom[i].usbCdcAcmInfo = &s_usbCdcAcmInfo[i];
+ g_deviceComposite->cdcVcom[i].currRecvBuf = (uint8_t *)&s_currRecvBuf[i][0];
+ ;
+ g_deviceComposite->cdcVcom[i].currSendBuf = (uint8_t *)&s_currSendBuf[i][0];
+ }
+ return kStatus_USB_Success;
+}
diff --git a/minimal-examples/embedded/rt595/hello_world/project/source/virtual_com.h b/minimal-examples/embedded/rt595/hello_world/project/source/virtual_com.h
new file mode 100644
index 000000000..6a3cb9d01
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/source/virtual_com.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _USB_CDC_VCOM_H_
+#define _USB_CDC_VCOM_H_ 1
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0)
+#define CONTROLLER_ID kUSB_ControllerEhci0
+#define DATA_BUFF_SIZE HS_CDC_VCOM_BULK_OUT_PACKET_SIZE
+#endif
+#if defined(USB_DEVICE_CONFIG_KHCI) && (USB_DEVICE_CONFIG_KHCI > 0)
+#define CONTROLLER_ID kUSB_ControllerKhci0
+#define DATA_BUFF_SIZE FS_CDC_VCOM_BULK_OUT_PACKET_SIZE
+#endif
+#if defined(USB_DEVICE_CONFIG_LPCIP3511FS) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)
+#define CONTROLLER_ID kUSB_ControllerLpcIp3511Fs0
+#define DATA_BUFF_SIZE FS_CDC_VCOM_BULK_OUT_PACKET_SIZE
+#endif
+
+#if defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)
+#define CONTROLLER_ID kUSB_ControllerLpcIp3511Hs0
+#define DATA_BUFF_SIZE HS_CDC_VCOM_BULK_OUT_PACKET_SIZE
+#endif
+
+#define USB_DEVICE_INTERRUPT_PRIORITY (3U)
+/* Currently configured line coding */
+#define LINE_CODING_SIZE (0x07)
+#define LINE_CODING_DTERATE (115200)
+#define LINE_CODING_CHARFORMAT (0x00)
+#define LINE_CODING_PARITYTYPE (0x00)
+#define LINE_CODING_DATABITS (0x08)
+
+/* Communications feature */
+#define COMM_FEATURE_DATA_SIZE (0x02)
+#define STATUS_ABSTRACT_STATE (0x0000)
+#define COUNTRY_SETTING (0x0000)
+
+/* Notification of serial state */
+#define NOTIF_PACKET_SIZE (0x08)
+#define UART_BITMAP_SIZE (0x02)
+#define NOTIF_REQUEST_TYPE (0xA1)
+/* Define the information relates to abstract control model */
+typedef struct _usb_cdc_acm_info
+{
+ uint8_t serialStateBuf[NOTIF_PACKET_SIZE + UART_BITMAP_SIZE]; /* Serial state buffer of the CDC device to notify the
+ serial state to host. */
+ bool dtePresent; /* A flag to indicate whether DTE is present. */
+ uint16_t breakDuration; /* Length of time in milliseconds of the break signal */
+ uint8_t dteStatus; /* Status of data terminal equipment */
+ uint8_t currentInterface; /* Current interface index. */
+ uint16_t uartState; /* UART state of the CDC device. */
+} usb_cdc_acm_info_t;
+/* Define the types for application */
+typedef struct _usb_cdc_vcom_struct
+{
+ usb_device_handle deviceHandle; /* USB device handle. */
+ class_handle_t cdcAcmHandle; /* USB CDC ACM class handle. */
+ uint8_t *lineCoding; /* Line coding of cdc device */
+ uint8_t *abstractState; /* Abstract state of cdc device */
+ uint8_t *countryCode; /* Country code of cdc device */
+ usb_cdc_acm_info_t *usbCdcAcmInfo; /* CDC ACM information */
+ uint8_t *currRecvBuf; /*receive buffer*/
+ uint8_t *currSendBuf; /*send buffer*/
+ volatile uint32_t recvSize; /*the data length received from host*/
+ volatile uint32_t sendSize; /*the data length to send*/
+ uint16_t bulkOutEndpointMaxPacketSize; /*bulk out endpoint maxpacket size */
+ uint16_t bulkInEndpointMaxPacketSize; /*bulk in endpoint maxpacket size */
+ uint16_t interruptEndpointMaxPacketSize; /*interrupt endpoint maxpacket size */
+ uint8_t attach; /* A flag to indicate whether a usb device is attached. 1: attached, 0: not attached */
+ uint8_t speed; /* Speed of USB device. USB_SPEED_FULL/USB_SPEED_LOW/USB_SPEED_HIGH. */
+ uint8_t startTransactions; /* A flag to indicate whether a CDC device is ready to transmit and receive data. */
+ uint8_t currentConfiguration; /* Current configuration value. */
+ uint8_t currentInterfaceAlternateSetting[USB_CDC_VCOM_INTERFACE_COUNT]; /* Current alternate setting value for each
+ interface. */
+ uint8_t bulkInEndpoint; /*bulk in endpoint number*/
+ uint8_t bulkOutEndpoint; /*bulk out endpoint number*/
+ uint8_t interruptEndpoint; /*interrupt endpoint number*/
+} usb_cdc_vcom_struct_t;
+
+#endif /* _USB_CDC_VCOM_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/startup/startup_mimxrt595s_cm33.c b/minimal-examples/embedded/rt595/hello_world/project/startup/startup_mimxrt595s_cm33.c
new file mode 100644
index 000000000..67c4b5160
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/startup/startup_mimxrt595s_cm33.c
@@ -0,0 +1,856 @@
+//*****************************************************************************
+// MIMXRT595S_cm33 startup code for use with MCUXpresso IDE
+//
+// Version : 180520
+//*****************************************************************************
+//
+// Copyright 2016-2020 NXP
+// All rights reserved.
+//
+// SPDX-License-Identifier: BSD-3-Clause
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC push_options
+#pragma GCC optimize ("Og")
+#endif // (DEBUG)
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+ extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define WEAK_AV __attribute__ ((weak, section(".after_vectors")))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+//*****************************************************************************
+//*****************************************************************************
+// Declaration of external SystemInit function
+//*****************************************************************************
+#if defined (__USE_CMSIS)
+extern void SystemInit(void);
+#endif // (__USE_CMSIS)
+
+//*****************************************************************************
+// Forward declaration of the core exception handlers.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions.
+// If your application is a C++ one, then any interrupt handlers defined
+// in C++ files within in your main application will need to have C linkage
+// rather than C++ linkage. To do this, make sure that you are using extern "C"
+// { .... } around the interrupt handler within your main application code.
+//*****************************************************************************
+ void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SecureFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the application IRQ handlers. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over weak definitions below
+//*****************************************************************************
+WEAK void WDT0_IRQHandler(void);
+WEAK void DMA0_IRQHandler(void);
+WEAK void GPIO_INTA_IRQHandler(void);
+WEAK void GPIO_INTB_IRQHandler(void);
+WEAK void PIN_INT0_IRQHandler(void);
+WEAK void PIN_INT1_IRQHandler(void);
+WEAK void PIN_INT2_IRQHandler(void);
+WEAK void PIN_INT3_IRQHandler(void);
+WEAK void UTICK0_IRQHandler(void);
+WEAK void MRT0_IRQHandler(void);
+WEAK void CTIMER0_IRQHandler(void);
+WEAK void CTIMER1_IRQHandler(void);
+WEAK void SCT0_IRQHandler(void);
+WEAK void CTIMER3_IRQHandler(void);
+WEAK void FLEXCOMM0_IRQHandler(void);
+WEAK void FLEXCOMM1_IRQHandler(void);
+WEAK void FLEXCOMM2_IRQHandler(void);
+WEAK void FLEXCOMM3_IRQHandler(void);
+WEAK void FLEXCOMM4_IRQHandler(void);
+WEAK void FLEXCOMM5_IRQHandler(void);
+WEAK void FLEXCOMM14_IRQHandler(void);
+WEAK void FLEXCOMM15_IRQHandler(void);
+WEAK void ADC0_IRQHandler(void);
+WEAK void Reserved39_IRQHandler(void);
+WEAK void ACMP_IRQHandler(void);
+WEAK void DMIC0_IRQHandler(void);
+WEAK void Reserved42_IRQHandler(void);
+WEAK void HYPERVISOR_IRQHandler(void);
+WEAK void SECURE_VIOLATION_IRQHandler(void);
+WEAK void HWVAD0_IRQHandler(void);
+WEAK void Reserved46_IRQHandler(void);
+WEAK void RNG_IRQHandler(void);
+WEAK void RTC_IRQHandler(void);
+WEAK void DSP_TIE_EXPSTATE1_IRQHandler(void);
+WEAK void MU_A_IRQHandler(void);
+WEAK void PIN_INT4_IRQHandler(void);
+WEAK void PIN_INT5_IRQHandler(void);
+WEAK void PIN_INT6_IRQHandler(void);
+WEAK void PIN_INT7_IRQHandler(void);
+WEAK void CTIMER2_IRQHandler(void);
+WEAK void CTIMER4_IRQHandler(void);
+WEAK void OS_EVENT_IRQHandler(void);
+WEAK void FLEXSPI0_FLEXSPI1_IRQHandler(void);
+WEAK void FLEXCOMM6_IRQHandler(void);
+WEAK void FLEXCOMM7_IRQHandler(void);
+WEAK void USDHC0_IRQHandler(void);
+WEAK void USDHC1_IRQHandler(void);
+WEAK void SGPIO_INTA_IRQHandler(void);
+WEAK void SGPIO_INTB_IRQHandler(void);
+WEAK void I3C0_IRQHandler(void);
+WEAK void USB0_IRQHandler(void);
+WEAK void USB0_NEEDCLK_IRQHandler(void);
+WEAK void WDT1_IRQHandler(void);
+WEAK void USB_PHYDCD_IRQHandler(void);
+WEAK void DMA1_IRQHandler(void);
+WEAK void PUF_IRQHandler(void);
+WEAK void POWERQUAD_IRQHandler(void);
+WEAK void CASPER_IRQHandler(void);
+WEAK void PMU_PMIC_IRQHandler(void);
+WEAK void HASHCRYPT_IRQHandler(void);
+WEAK void FLEXCOMM8_IRQHandler(void);
+WEAK void FLEXCOMM9_IRQHandler(void);
+WEAK void FLEXCOMM10_IRQHandler(void);
+WEAK void FLEXCOMM11_IRQHandler(void);
+WEAK void FLEXCOMM12_IRQHandler(void);
+WEAK void FLEXCOMM13_IRQHandler(void);
+WEAK void FLEXCOMM16_IRQHandler(void);
+WEAK void I3C1_IRQHandler(void);
+WEAK void FLEXIO_IRQHandler(void);
+WEAK void LCDIF_IRQHandler(void);
+WEAK void GPU_IRQHandler(void);
+WEAK void MIPI_IRQHandler(void);
+WEAK void Reserved88_IRQHandler(void);
+WEAK void SDMA_IRQHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the driver IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the driver
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//*****************************************************************************
+void WDT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO_INTA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO_INTB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM14_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM15_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved39_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ACMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMIC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved42_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void HYPERVISOR_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SECURE_VIOLATION_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void HWVAD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved46_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RNG_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DSP_TIE_EXPSTATE1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void MU_A_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void OS_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXSPI0_FLEXSPI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USDHC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USDHC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SGPIO_INTA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SGPIO_INTB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void I3C0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void WDT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB_PHYDCD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PUF_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void POWERQUAD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CASPER_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PMU_PMIC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void HASHCRYPT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM8_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM9_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM10_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM11_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM12_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM13_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM16_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void I3C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void LCDIF_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GPU_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void MIPI_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved88_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SDMA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+
+//*****************************************************************************
+// External declaration for the pointer to the stack top from the Linker Script
+//*****************************************************************************
+extern void _vStackTop(void);
+extern void _image_size(void);
+//*****************************************************************************
+// External declaration for the pointer to the stack base from the Linker Script
+//*****************************************************************************
+extern void _vStackBase(void);
+//*****************************************************************************
+// External declaration for image type and load address from Linker Script
+//*****************************************************************************
+WEAK extern void __imghdr_loadaddress();
+WEAK extern void __imghdr_imagetype();
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//*****************************************************************************
+
+
+
+extern void (* const g_pfnVectors[])(void);
+extern void * __Vectors __attribute__ ((alias ("g_pfnVectors")));
+
+__attribute__ ((used, section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM33
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ MemManage_Handler, // The MPU fault handler
+ BusFault_Handler, // The bus fault handler
+ UsageFault_Handler, // The usage fault handler
+ SecureFault_Handler, // The secure fault handler
+#if (__ARM_FEATURE_CMSE & 0x2)
+ (void (*)())0x280000, // Image length
+#else
+ (void (*)())((unsigned)_image_size), // Image length
+#endif
+ __imghdr_imagetype, // Image type
+ 0, // Reserved
+ SVC_Handler, // SVCall handler
+ DebugMon_Handler, // Debug monitor handler
+ (void (*)())g_pfnVectors, // Image load address
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
+
+ // Chip Level - MIMXRT595S_cm33
+ WDT0_IRQHandler, // 16: Watchdog timer interrupt
+ DMA0_IRQHandler, // 17: DMA interrupt
+ GPIO_INTA_IRQHandler, // 18: GPIO Interrupt A
+ GPIO_INTB_IRQHandler, // 19: GPIO Interrupt B
+ PIN_INT0_IRQHandler, // 20: General Purpose Input/Output interrupt 0
+ PIN_INT1_IRQHandler, // 21: General Purpose Input/Output interrupt 1
+ PIN_INT2_IRQHandler, // 22: General Purpose Input/Output interrupt 2
+ PIN_INT3_IRQHandler, // 23: General Purpose Input/Output interrupt 3
+ UTICK0_IRQHandler, // 24: Micro-tick Timer
+ MRT0_IRQHandler, // 25: Multi-Rate Timer
+ CTIMER0_IRQHandler, // 26: Standard counter/timer CTIMER0
+ CTIMER1_IRQHandler, // 27: Standard counter/timer CTIMER1
+ SCT0_IRQHandler, // 28: SCTimer/PWM
+ CTIMER3_IRQHandler, // 29: Standard counter/timer CTIMER3
+ FLEXCOMM0_IRQHandler, // 30: FlexComm interrupt
+ FLEXCOMM1_IRQHandler, // 31: FlexComm interrupt
+ FLEXCOMM2_IRQHandler, // 32: FlexComm interrupt
+ FLEXCOMM3_IRQHandler, // 33: FlexComm interrupt
+ FLEXCOMM4_IRQHandler, // 34: FlexComm interrupt
+ FLEXCOMM5_IRQHandler, // 35: FlexComm interrupt
+ FLEXCOMM14_IRQHandler, // 36: FlexComm interrupt. Standalone SPI
+ FLEXCOMM15_IRQHandler, // 37: FlexComm interrupt. Standalone I2C
+ ADC0_IRQHandler, // 38: Analog-to-Digital Converter interrupt
+ Reserved39_IRQHandler, // 39: Reserved interrupt
+ ACMP_IRQHandler, // 40: Analog comparator Interrupts
+ DMIC0_IRQHandler, // 41: Digital Microphone Interface interrupt
+ Reserved42_IRQHandler, // 42: Reserved interrupt
+ HYPERVISOR_IRQHandler, // 43: Hypervisor interrupt
+ SECURE_VIOLATION_IRQHandler, // 44: Secure violation interrupt
+ HWVAD0_IRQHandler, // 45: Hardware Voice Activity Detector interrupt
+ Reserved46_IRQHandler, // 46: Reserved interrupt
+ RNG_IRQHandler, // 47: Random Number Generator interrupt
+ RTC_IRQHandler, // 48: Real Time Clock Alarm interrupt OR Wakeup timer interrupt
+ DSP_TIE_EXPSTATE1_IRQHandler, // 49: DSP interrupt
+ MU_A_IRQHandler, // 50: Messaging Unit - Side A
+ PIN_INT4_IRQHandler, // 51: General Purpose Input/Output interrupt 4
+ PIN_INT5_IRQHandler, // 52: General Purpose Input/Output interrupt 5
+ PIN_INT6_IRQHandler, // 53: General Purpose Input/Output interrupt 6
+ PIN_INT7_IRQHandler, // 54: General Purpose Input/Output interrupt 7
+ CTIMER2_IRQHandler, // 55: Standard counter/timer CTIMER2
+ CTIMER4_IRQHandler, // 56: Standard counter/timer CTIMER4
+ OS_EVENT_IRQHandler, // 57: Event timer M33 Wakeup/interrupt
+ FLEXSPI0_FLEXSPI1_IRQHandler, // 58: FlexSPI0_IRQ OR FlexSPI1_IRQ
+ FLEXCOMM6_IRQHandler, // 59: FlexComm interrupt
+ FLEXCOMM7_IRQHandler, // 60: FlexComm interrupt
+ USDHC0_IRQHandler, // 61: USDHC interrupt
+ USDHC1_IRQHandler, // 62: USDHC interrupt
+ SGPIO_INTA_IRQHandler, // 63: Secure GPIO HS interrupt 0
+ SGPIO_INTB_IRQHandler, // 64: Secure GPIO HS interrupt 1
+ I3C0_IRQHandler, // 65: Improved Inter Integrated Circuit 0 interrupt
+ USB0_IRQHandler, // 66: USB device
+ USB0_NEEDCLK_IRQHandler, // 67: USB Activity Wake-up Interrupt
+ WDT1_IRQHandler, // 68: Watchdog timer 1 interrupt
+ USB_PHYDCD_IRQHandler, // 69: USBPHY DCD interrupt
+ DMA1_IRQHandler, // 70: DMA interrupt
+ PUF_IRQHandler, // 71: QuidKey interrupt
+ POWERQUAD_IRQHandler, // 72: Powerquad interrupt
+ CASPER_IRQHandler, // 73: Caspar interrupt
+ PMU_PMIC_IRQHandler, // 74: Power Management Control interrupt
+ HASHCRYPT_IRQHandler, // 75: SHA interrupt
+ FLEXCOMM8_IRQHandler, // 76: FlexComm interrupt
+ FLEXCOMM9_IRQHandler, // 77: FlexComm interrupt
+ FLEXCOMM10_IRQHandler, // 78: FlexComm interrupt
+ FLEXCOMM11_IRQHandler, // 79: FlexComm interrupt
+ FLEXCOMM12_IRQHandler, // 80: FlexComm interrupt
+ FLEXCOMM13_IRQHandler, // 81: FlexComm interrupt
+ FLEXCOMM16_IRQHandler, // 82: FlexComm interrupt
+ I3C1_IRQHandler, // 83: Improved Inter Integrated Circuit 1 interrupt
+ FLEXIO_IRQHandler, // 84: Flexible I/O interrupt
+ LCDIF_IRQHandler, // 85: Liquid Crystal Display interface interrupt
+ GPU_IRQHandler, // 86: Graphics Processor Unit interrupt
+ MIPI_IRQHandler, // 87: MIPI interrupt
+ Reserved88_IRQHandler, // 88: Reserved interrupt
+ SDMA_IRQHandler, // 89: Smart DMA Engine Controller interrupt
+
+
+}; /* End of g_pfnVectors */
+
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+extern void * __VECTOR_TABLE __attribute__ ((alias ("g_pfnVectors")));
+void (* __VECTOR_RAM[sizeof(g_pfnVectors) / 4])(void) __attribute__((aligned(128)));
+unsigned int __RAM_VECTOR_TABLE_SIZE_BYTES = sizeof(g_pfnVectors);
+#endif
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors.init_data")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors.init_bss")))
+void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+__attribute__ ((naked, section(".after_vectors.reset")))
+void ResetISR(void) {
+
+ // Disable interrupts
+ __asm volatile ("cpsid i");
+
+ // Config VTOR & MSPLIM register
+ __asm volatile ("LDR R0, =0xE000ED08 \n"
+ "STR %0, [R0] \n"
+ "LDR R1, [%0] \n"
+ "MSR MSP, R1 \n"
+ "MSR MSPLIM, %1 \n"
+ :
+ : "r"(g_pfnVectors), "r"(_vStackBase)
+ : "r0", "r1");
+
+#if defined (__USE_CMSIS)
+// If __USE_CMSIS defined, then call CMSIS SystemInit code
+ SystemInit();
+
+#endif // (__USE_CMSIS)
+
+ //
+ // Copy the data sections from flash to SRAM.
+ //
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ // Load base address of Global Section Table
+ SectionTableAddr = &__data_section_table;
+
+ // Copy the data sections from flash to SRAM.
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+
+ // At this point, SectionTableAddr = &__bss_section_table;
+ // Zero fill the bss segment
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+
+#if defined (__cplusplus)
+ //
+ // Call C++ library initialisation
+ //
+ __libc_init_array();
+#endif
+
+ // Reenable interrupts
+ __asm volatile ("cpsie i");
+
+#if defined (__REDLIB__)
+ // Call the Redlib library, which in turn calls main()
+ __main();
+#else
+ main();
+#endif
+
+ //
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1) {
+ ;
+ }
+}
+
+//*****************************************************************************
+// Default core exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+WEAK_AV void NMI_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void HardFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void MemManage_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void BusFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void UsageFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void SecureFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void SVC_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void DebugMon_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void PendSV_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void SysTick_Handler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//*****************************************************************************
+WEAK_AV void IntDefaultHandler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+// Default application exception handlers. Override the ones here by defining
+// your own handler routines in your application code. These routines call
+// driver exception handlers or IntDefaultHandler() if no driver exception
+// handler is included.
+//*****************************************************************************
+WEAK void WDT0_IRQHandler(void)
+{ WDT0_DriverIRQHandler();
+}
+
+WEAK void DMA0_IRQHandler(void)
+{ DMA0_DriverIRQHandler();
+}
+
+WEAK void GPIO_INTA_IRQHandler(void)
+{ GPIO_INTA_DriverIRQHandler();
+}
+
+WEAK void GPIO_INTB_IRQHandler(void)
+{ GPIO_INTB_DriverIRQHandler();
+}
+
+WEAK void PIN_INT0_IRQHandler(void)
+{ PIN_INT0_DriverIRQHandler();
+}
+
+WEAK void PIN_INT1_IRQHandler(void)
+{ PIN_INT1_DriverIRQHandler();
+}
+
+WEAK void PIN_INT2_IRQHandler(void)
+{ PIN_INT2_DriverIRQHandler();
+}
+
+WEAK void PIN_INT3_IRQHandler(void)
+{ PIN_INT3_DriverIRQHandler();
+}
+
+WEAK void UTICK0_IRQHandler(void)
+{ UTICK0_DriverIRQHandler();
+}
+
+WEAK void MRT0_IRQHandler(void)
+{ MRT0_DriverIRQHandler();
+}
+
+WEAK void CTIMER0_IRQHandler(void)
+{ CTIMER0_DriverIRQHandler();
+}
+
+WEAK void CTIMER1_IRQHandler(void)
+{ CTIMER1_DriverIRQHandler();
+}
+
+WEAK void SCT0_IRQHandler(void)
+{ SCT0_DriverIRQHandler();
+}
+
+WEAK void CTIMER3_IRQHandler(void)
+{ CTIMER3_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM0_IRQHandler(void)
+{ FLEXCOMM0_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM1_IRQHandler(void)
+{ FLEXCOMM1_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM2_IRQHandler(void)
+{ FLEXCOMM2_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM3_IRQHandler(void)
+{ FLEXCOMM3_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM4_IRQHandler(void)
+{ FLEXCOMM4_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM5_IRQHandler(void)
+{ FLEXCOMM5_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM14_IRQHandler(void)
+{ FLEXCOMM14_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM15_IRQHandler(void)
+{ FLEXCOMM15_DriverIRQHandler();
+}
+
+WEAK void ADC0_IRQHandler(void)
+{ ADC0_DriverIRQHandler();
+}
+
+WEAK void Reserved39_IRQHandler(void)
+{ Reserved39_DriverIRQHandler();
+}
+
+WEAK void ACMP_IRQHandler(void)
+{ ACMP_DriverIRQHandler();
+}
+
+WEAK void DMIC0_IRQHandler(void)
+{ DMIC0_DriverIRQHandler();
+}
+
+WEAK void Reserved42_IRQHandler(void)
+{ Reserved42_DriverIRQHandler();
+}
+
+WEAK void HYPERVISOR_IRQHandler(void)
+{ HYPERVISOR_DriverIRQHandler();
+}
+
+WEAK void SECURE_VIOLATION_IRQHandler(void)
+{ SECURE_VIOLATION_DriverIRQHandler();
+}
+
+WEAK void HWVAD0_IRQHandler(void)
+{ HWVAD0_DriverIRQHandler();
+}
+
+WEAK void Reserved46_IRQHandler(void)
+{ Reserved46_DriverIRQHandler();
+}
+
+WEAK void RNG_IRQHandler(void)
+{ RNG_DriverIRQHandler();
+}
+
+WEAK void RTC_IRQHandler(void)
+{ RTC_DriverIRQHandler();
+}
+
+WEAK void DSP_TIE_EXPSTATE1_IRQHandler(void)
+{ DSP_TIE_EXPSTATE1_DriverIRQHandler();
+}
+
+WEAK void MU_A_IRQHandler(void)
+{ MU_A_DriverIRQHandler();
+}
+
+WEAK void PIN_INT4_IRQHandler(void)
+{ PIN_INT4_DriverIRQHandler();
+}
+
+WEAK void PIN_INT5_IRQHandler(void)
+{ PIN_INT5_DriverIRQHandler();
+}
+
+WEAK void PIN_INT6_IRQHandler(void)
+{ PIN_INT6_DriverIRQHandler();
+}
+
+WEAK void PIN_INT7_IRQHandler(void)
+{ PIN_INT7_DriverIRQHandler();
+}
+
+WEAK void CTIMER2_IRQHandler(void)
+{ CTIMER2_DriverIRQHandler();
+}
+
+WEAK void CTIMER4_IRQHandler(void)
+{ CTIMER4_DriverIRQHandler();
+}
+
+WEAK void OS_EVENT_IRQHandler(void)
+{ OS_EVENT_DriverIRQHandler();
+}
+
+WEAK void FLEXSPI0_FLEXSPI1_IRQHandler(void)
+{ FLEXSPI0_FLEXSPI1_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM6_IRQHandler(void)
+{ FLEXCOMM6_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM7_IRQHandler(void)
+{ FLEXCOMM7_DriverIRQHandler();
+}
+
+WEAK void USDHC0_IRQHandler(void)
+{ USDHC0_DriverIRQHandler();
+}
+
+WEAK void USDHC1_IRQHandler(void)
+{ USDHC1_DriverIRQHandler();
+}
+
+WEAK void SGPIO_INTA_IRQHandler(void)
+{ SGPIO_INTA_DriverIRQHandler();
+}
+
+WEAK void SGPIO_INTB_IRQHandler(void)
+{ SGPIO_INTB_DriverIRQHandler();
+}
+
+WEAK void I3C0_IRQHandler(void)
+{ I3C0_DriverIRQHandler();
+}
+
+WEAK void USB0_IRQHandler(void)
+{ USB0_DriverIRQHandler();
+}
+
+WEAK void USB0_NEEDCLK_IRQHandler(void)
+{ USB0_NEEDCLK_DriverIRQHandler();
+}
+
+WEAK void WDT1_IRQHandler(void)
+{ WDT1_DriverIRQHandler();
+}
+
+WEAK void USB_PHYDCD_IRQHandler(void)
+{ USB_PHYDCD_DriverIRQHandler();
+}
+
+WEAK void DMA1_IRQHandler(void)
+{ DMA1_DriverIRQHandler();
+}
+
+WEAK void PUF_IRQHandler(void)
+{ PUF_DriverIRQHandler();
+}
+
+WEAK void POWERQUAD_IRQHandler(void)
+{ POWERQUAD_DriverIRQHandler();
+}
+
+WEAK void CASPER_IRQHandler(void)
+{ CASPER_DriverIRQHandler();
+}
+
+WEAK void PMU_PMIC_IRQHandler(void)
+{ PMU_PMIC_DriverIRQHandler();
+}
+
+WEAK void HASHCRYPT_IRQHandler(void)
+{ HASHCRYPT_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM8_IRQHandler(void)
+{ FLEXCOMM8_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM9_IRQHandler(void)
+{ FLEXCOMM9_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM10_IRQHandler(void)
+{ FLEXCOMM10_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM11_IRQHandler(void)
+{ FLEXCOMM11_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM12_IRQHandler(void)
+{ FLEXCOMM12_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM13_IRQHandler(void)
+{ FLEXCOMM13_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM16_IRQHandler(void)
+{ FLEXCOMM16_DriverIRQHandler();
+}
+
+WEAK void I3C1_IRQHandler(void)
+{ I3C1_DriverIRQHandler();
+}
+
+WEAK void FLEXIO_IRQHandler(void)
+{ FLEXIO_DriverIRQHandler();
+}
+
+WEAK void LCDIF_IRQHandler(void)
+{ LCDIF_DriverIRQHandler();
+}
+
+WEAK void GPU_IRQHandler(void)
+{ GPU_DriverIRQHandler();
+}
+
+WEAK void MIPI_IRQHandler(void)
+{ MIPI_DriverIRQHandler();
+}
+
+WEAK void Reserved88_IRQHandler(void)
+{ Reserved88_DriverIRQHandler();
+}
+
+WEAK void SDMA_IRQHandler(void)
+{ SDMA_DriverIRQHandler();
+}
+
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC pop_options
+#endif // (DEBUG)
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/device/class/cdc/usb_device_cdc_acm.c b/minimal-examples/embedded/rt595/hello_world/project/usb/device/class/cdc/usb_device_cdc_acm.c
new file mode 100644
index 000000000..4dfec1684
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/device/class/cdc/usb_device_cdc_acm.c
@@ -0,0 +1,931 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016, 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "usb_device_config.h"
+#include "usb.h"
+#include "usb_device.h"
+
+#include "usb_device_class.h"
+
+#if USB_DEVICE_CONFIG_CDC_ACM
+#include "usb_device_cdc_acm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define USB_CDC_ACM_ENTER_CRITICAL() \
+ OSA_SR_ALLOC(); \
+ OSA_ENTER_CRITICAL()
+
+#define USB_CDC_ACM_EXIT_CRITICAL() OSA_EXIT_CRITICAL()
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* CDC ACM device instance */
+
+USB_GLOBAL USB_RAM_ADDRESS_ALIGNMENT(USB_DATA_ALIGN_SIZE) static usb_device_cdc_acm_struct_t
+ g_cdcAcmHandle[USB_DEVICE_CONFIG_CDC_ACM];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Allocates the CDC ACM device handle.
+ *
+ * This function allocates the CDC ACM device handle.
+ *
+ * @param handle The class handle of the CDC ACM class.
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceCdcAcmAllocateHandle(usb_device_cdc_acm_struct_t **handle)
+{
+ uint32_t count;
+ for (count = 0; count < (uint32_t)USB_DEVICE_CONFIG_CDC_ACM; count++)
+ {
+ if (NULL == g_cdcAcmHandle[count].handle)
+ {
+ *handle = &g_cdcAcmHandle[count];
+ return kStatus_USB_Success;
+ }
+ }
+
+ return kStatus_USB_Busy;
+}
+
+/*!
+ * @brief Frees the CDC ACM device handle.
+ *
+ * This function frees the CDC ACM device handle.
+ *
+ * @param handle The class handle of the CDC ACM class.
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceCdcAcmFreeHandle(usb_device_cdc_acm_struct_t *handle)
+{
+ handle->handle = NULL;
+ handle->configStruct = NULL;
+ handle->configuration = 0;
+ handle->alternate = 0;
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Responds to the interrupt in endpoint event.
+ *
+ * This function responds to the interrupt in endpoint event.
+ *
+ * @param handle The device handle of the CDC ACM device.
+ * @param message The pointer to the message of the endpoint callback.
+ * @param callbackParam The pointer to the parameter of the callback.
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceCdcAcmInterruptIn(usb_device_handle handle,
+ usb_device_endpoint_callback_message_struct_t *message,
+ void *callbackParam)
+{
+ usb_device_cdc_acm_struct_t *cdcAcmHandle;
+ usb_status_t error = kStatus_USB_Error;
+ cdcAcmHandle = (usb_device_cdc_acm_struct_t *)callbackParam;
+ if (NULL == cdcAcmHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ cdcAcmHandle->interruptIn.isBusy = 0U;
+
+ if ((NULL != cdcAcmHandle->configStruct) && (NULL != cdcAcmHandle->configStruct->classCallback))
+ {
+ /*classCallback is initialized in classInit of s_UsbDeviceClassInterfaceMap,
+ it is from the second parameter of classInit */
+ error = cdcAcmHandle->configStruct->classCallback((class_handle_t)cdcAcmHandle,
+ kUSB_DeviceCdcEventSerialStateNotif, message);
+ }
+ return error;
+}
+
+/*!
+ * @brief Responds to the bulk in endpoint event.
+ *
+ * This function responds to the bulk in endpoint event.
+ *
+ * @param handle The device handle of the CDC ACM device.
+ * @param message The pointer to the message of the endpoint callback.
+ * @param callbackParam The pointer to the parameter of the callback.
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceCdcAcmBulkIn(usb_device_handle handle,
+ usb_device_endpoint_callback_message_struct_t *message,
+ void *callbackParam)
+{
+ usb_device_cdc_acm_struct_t *cdcAcmHandle;
+ usb_status_t status = kStatus_USB_Error;
+ cdcAcmHandle = (usb_device_cdc_acm_struct_t *)callbackParam;
+
+ if (NULL == cdcAcmHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ cdcAcmHandle->bulkIn.isBusy = 0;
+
+ if ((NULL != cdcAcmHandle->configStruct) && (NULL != cdcAcmHandle->configStruct->classCallback))
+ {
+ /*classCallback is initialized in classInit of s_UsbDeviceClassInterfaceMap,
+ it is from the second parameter of classInit */
+ status = cdcAcmHandle->configStruct->classCallback((class_handle_t)cdcAcmHandle,
+ kUSB_DeviceCdcEventSendResponse, message);
+ }
+ return status;
+}
+
+/*!
+ * @brief Responds to the bulk out endpoint event.
+ *
+ * This function responds to the bulk out endpoint event.
+ *
+ * @param handle The device handle of the CDC ACM device.
+ * @param message The pointer to the message of the endpoint callback.
+ * @param callbackParam The pointer to the parameter of the callback.
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceCdcAcmBulkOut(usb_device_handle handle,
+ usb_device_endpoint_callback_message_struct_t *message,
+ void *callbackParam)
+{
+ usb_device_cdc_acm_struct_t *cdcAcmHandle;
+ usb_status_t status = kStatus_USB_Error;
+ cdcAcmHandle = (usb_device_cdc_acm_struct_t *)callbackParam;
+
+ if (NULL == cdcAcmHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ cdcAcmHandle->bulkOut.isBusy = 0U;
+
+ if ((NULL != cdcAcmHandle->configStruct) && (NULL != cdcAcmHandle->configStruct->classCallback))
+ {
+ /*classCallback is initialized in classInit of s_UsbDeviceClassInterfaceMap,
+ it is from the second parameter of classInit */
+ status = cdcAcmHandle->configStruct->classCallback((class_handle_t)cdcAcmHandle,
+ kUSB_DeviceCdcEventRecvResponse, message);
+ }
+ return status;
+}
+
+/*!
+ * @brief Initializes the endpoints in CDC ACM class.
+ *
+ * This function initializes the endpoints in CDC ACM class.
+ *
+ * @param cdcAcmHandle The class handle of the CDC ACM class.
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceCdcAcmEndpointsInit(usb_device_cdc_acm_struct_t *cdcAcmHandle)
+{
+ usb_device_interface_list_t *interfaceList;
+ usb_device_interface_struct_t *interface = NULL;
+ usb_status_t error = kStatus_USB_Error;
+ uint32_t count;
+ uint32_t index;
+
+ if (NULL == cdcAcmHandle)
+ {
+ return error;
+ }
+
+ /* return error when configuration is invalid (0 or more than the configuration number) */
+ if ((cdcAcmHandle->configuration == 0U) ||
+ (cdcAcmHandle->configuration > cdcAcmHandle->configStruct->classInfomation->configurations))
+ {
+ return error;
+ }
+
+ interfaceList = &cdcAcmHandle->configStruct->classInfomation->interfaceList[cdcAcmHandle->configuration - 1U];
+
+ for (count = 0; count < interfaceList->count; count++)
+ {
+ if (USB_DEVICE_CONFIG_CDC_COMM_CLASS_CODE == interfaceList->interfaces[count].classCode)
+ {
+ for (index = 0; index < interfaceList->interfaces[count].count; index++)
+ {
+ if (interfaceList->interfaces[count].interface[index].alternateSetting == cdcAcmHandle->alternate)
+ {
+ interface = &interfaceList->interfaces[count].interface[index];
+ break;
+ }
+ }
+ cdcAcmHandle->interfaceNumber = interfaceList->interfaces[count].interfaceNumber;
+ break;
+ }
+ }
+ if (NULL == interface)
+ {
+ return error;
+ }
+ cdcAcmHandle->commInterfaceHandle = interface;
+ for (count = 0; count < interface->endpointList.count; count++)
+ {
+ usb_device_endpoint_init_struct_t epInitStruct;
+ usb_device_endpoint_callback_struct_t epCallback;
+ epInitStruct.zlt = 0;
+ epInitStruct.interval = interface->endpointList.endpoint[count].interval;
+ epInitStruct.endpointAddress = interface->endpointList.endpoint[count].endpointAddress;
+ epInitStruct.maxPacketSize = interface->endpointList.endpoint[count].maxPacketSize;
+ epInitStruct.transferType = interface->endpointList.endpoint[count].transferType;
+
+ if ((USB_IN == ((epInitStruct.endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)) &&
+ (USB_ENDPOINT_INTERRUPT == epInitStruct.transferType))
+ {
+ cdcAcmHandle->interruptIn.ep = (epInitStruct.endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_MASK);
+ cdcAcmHandle->interruptIn.isBusy = 0;
+ cdcAcmHandle->interruptIn.pipeDataBuffer = (uint8_t *)USB_INVALID_TRANSFER_BUFFER;
+ cdcAcmHandle->interruptIn.pipeStall = 0U;
+ cdcAcmHandle->interruptIn.pipeDataLen = 0U;
+ epCallback.callbackFn = USB_DeviceCdcAcmInterruptIn;
+ }
+
+ epCallback.callbackParam = cdcAcmHandle;
+
+ error = USB_DeviceInitEndpoint(cdcAcmHandle->handle, &epInitStruct, &epCallback);
+ if (kStatus_USB_Success != error)
+ {
+ return error;
+ }
+ }
+
+ for (count = 0; count < interfaceList->count; count++)
+ {
+ if (USB_DEVICE_CONFIG_CDC_DATA_CLASS_CODE == interfaceList->interfaces[count].classCode)
+ {
+ for (index = 0; index < interfaceList->interfaces[count].count; index++)
+ {
+ if (interfaceList->interfaces[count].interface[index].alternateSetting == cdcAcmHandle->alternate)
+ {
+ interface = &interfaceList->interfaces[count].interface[index];
+ break;
+ }
+ }
+ break;
+ }
+ }
+
+ cdcAcmHandle->dataInterfaceHandle = interface;
+
+ for (count = 0; count < interface->endpointList.count; count++)
+ {
+ usb_device_endpoint_init_struct_t epInitStruct;
+ usb_device_endpoint_callback_struct_t epCallback;
+ epInitStruct.zlt = 0;
+ epInitStruct.interval = interface->endpointList.endpoint[count].interval;
+ epInitStruct.endpointAddress = interface->endpointList.endpoint[count].endpointAddress;
+ epInitStruct.maxPacketSize = interface->endpointList.endpoint[count].maxPacketSize;
+ epInitStruct.transferType = interface->endpointList.endpoint[count].transferType;
+
+ if ((USB_IN == ((epInitStruct.endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)) &&
+ (USB_ENDPOINT_BULK == epInitStruct.transferType))
+ {
+ cdcAcmHandle->bulkIn.ep = (epInitStruct.endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_MASK);
+ cdcAcmHandle->bulkIn.isBusy = 0;
+ cdcAcmHandle->bulkIn.pipeDataBuffer = (uint8_t *)USB_INVALID_TRANSFER_BUFFER;
+ cdcAcmHandle->bulkIn.pipeStall = 0U;
+ cdcAcmHandle->bulkIn.pipeDataLen = 0U;
+ epCallback.callbackFn = USB_DeviceCdcAcmBulkIn;
+ }
+ else if ((USB_OUT == ((epInitStruct.endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)) &&
+ (USB_ENDPOINT_BULK == epInitStruct.transferType))
+ {
+ cdcAcmHandle->bulkOut.ep = (epInitStruct.endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_MASK);
+ cdcAcmHandle->bulkOut.isBusy = 0;
+ cdcAcmHandle->bulkOut.pipeDataBuffer = (uint8_t *)USB_INVALID_TRANSFER_BUFFER;
+ cdcAcmHandle->bulkOut.pipeStall = 0U;
+ cdcAcmHandle->bulkOut.pipeDataLen = 0U;
+ epCallback.callbackFn = USB_DeviceCdcAcmBulkOut;
+ }
+ else
+ {
+ /*no action*/
+ }
+ epCallback.callbackParam = cdcAcmHandle;
+
+ error = USB_DeviceInitEndpoint(cdcAcmHandle->handle, &epInitStruct, &epCallback);
+ }
+ return error;
+}
+
+/*!
+ * @brief De-initializes the endpoints in CDC ACM class.
+ *
+ * This function de-initializes the endpoints in CDC ACM class.
+ *
+ * @param cdcAcmHandle The class handle of the CDC ACM class.
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceCdcAcmEndpointsDeinit(usb_device_cdc_acm_struct_t *cdcAcmHandle)
+{
+ usb_status_t status = kStatus_USB_Error;
+ uint32_t count;
+
+ if ((NULL == cdcAcmHandle->commInterfaceHandle) || (NULL == cdcAcmHandle->dataInterfaceHandle))
+ {
+ return status;
+ }
+ for (count = 0; count < cdcAcmHandle->commInterfaceHandle->endpointList.count; count++)
+ {
+ status = USB_DeviceDeinitEndpoint(
+ cdcAcmHandle->handle, cdcAcmHandle->commInterfaceHandle->endpointList.endpoint[count].endpointAddress);
+ }
+ for (count = 0; count < cdcAcmHandle->dataInterfaceHandle->endpointList.count; count++)
+ {
+ status = USB_DeviceDeinitEndpoint(
+ cdcAcmHandle->handle, cdcAcmHandle->dataInterfaceHandle->endpointList.endpoint[count].endpointAddress);
+ }
+ cdcAcmHandle->commInterfaceHandle = NULL;
+ cdcAcmHandle->dataInterfaceHandle = NULL;
+
+ return status;
+}
+
+/*!
+ * @brief Handles the CDC ACM class event.
+ *
+ * This function responses to various events including the common device events and the class specific events.
+ * For class specific events, it calls the class callback defined in the application to deal with the class specific
+ * event.
+ *
+ * @param handle The class handle of the CDC ACM class.
+ * @param event The event type.
+ * @param param The class handle of the CDC ACM class.
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceCdcAcmEvent(void *handle, uint32_t event, void *param)
+{
+ usb_device_cdc_acm_struct_t *cdcAcmHandle;
+ usb_device_cdc_acm_request_param_struct_t reqParam;
+ usb_status_t error = kStatus_USB_Error;
+ uint32_t count;
+ uint16_t interfaceAlternate;
+ uint8_t *temp8;
+ uint8_t alternate;
+ usb_device_class_event_t eventCode = (usb_device_class_event_t)event;
+ if ((NULL == param) || (NULL == handle))
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ cdcAcmHandle = (usb_device_cdc_acm_struct_t *)handle;
+
+ switch (eventCode)
+ {
+ case kUSB_DeviceClassEventDeviceReset:
+ /* Bus reset, clear the configuration. */
+ cdcAcmHandle->configuration = 0;
+ error = kStatus_USB_Success;
+ break;
+ case kUSB_DeviceClassEventSetConfiguration:
+ temp8 = ((uint8_t *)param);
+ if (NULL == cdcAcmHandle->configStruct)
+ {
+ break;
+ }
+ if (*temp8 == cdcAcmHandle->configuration)
+ {
+ error = kStatus_USB_Success;
+ break;
+ }
+
+ error = USB_DeviceCdcAcmEndpointsDeinit(cdcAcmHandle);
+ cdcAcmHandle->configuration = *temp8;
+ cdcAcmHandle->alternate = 0U;
+ error = USB_DeviceCdcAcmEndpointsInit(cdcAcmHandle);
+ if (kStatus_USB_Success != error)
+ {
+#if 0
+ (void)usb_echo("kUSB_DeviceClassEventSetConfiguration, USB_DeviceInitEndpoint fail\r\n");
+#endif
+ }
+ break;
+ case kUSB_DeviceClassEventSetInterface:
+ if (NULL == cdcAcmHandle->configStruct)
+ {
+ break;
+ }
+
+ interfaceAlternate = *((uint16_t *)param);
+ alternate = (uint8_t)(interfaceAlternate & 0xFFU);
+
+ if (cdcAcmHandle->interfaceNumber != ((uint8_t)(interfaceAlternate >> 8U)))
+ {
+ break;
+ }
+ if (alternate == cdcAcmHandle->alternate)
+ {
+ error = kStatus_USB_Success;
+ break;
+ }
+ error = USB_DeviceCdcAcmEndpointsDeinit(cdcAcmHandle);
+ cdcAcmHandle->alternate = alternate;
+ error = USB_DeviceCdcAcmEndpointsInit(cdcAcmHandle);
+ if (kStatus_USB_Success != error)
+ {
+#if 0
+ (void)usb_echo("kUSB_DeviceClassEventSetInterface, USB_DeviceInitEndpoint fail\r\n");
+#endif
+ }
+ break;
+ case kUSB_DeviceClassEventSetEndpointHalt:
+ if ((NULL == cdcAcmHandle->configStruct) || (NULL == cdcAcmHandle->commInterfaceHandle) ||
+ (NULL == cdcAcmHandle->dataInterfaceHandle))
+ {
+ break;
+ }
+ temp8 = ((uint8_t *)param);
+ for (count = 0; count < cdcAcmHandle->commInterfaceHandle->endpointList.count; count++)
+ {
+ if (*temp8 == cdcAcmHandle->commInterfaceHandle->endpointList.endpoint[count].endpointAddress)
+ {
+ cdcAcmHandle->interruptIn.pipeStall = 1U;
+ error = USB_DeviceStallEndpoint(cdcAcmHandle->handle, *temp8);
+ }
+ }
+ for (count = 0; count < cdcAcmHandle->dataInterfaceHandle->endpointList.count; count++)
+ {
+ if (*temp8 == cdcAcmHandle->dataInterfaceHandle->endpointList.endpoint[count].endpointAddress)
+ {
+ if (USB_IN == (((*temp8) & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT))
+ {
+ cdcAcmHandle->bulkIn.pipeStall = 1U;
+ }
+ else
+ {
+ cdcAcmHandle->bulkOut.pipeStall = 1U;
+ }
+ error = USB_DeviceStallEndpoint(cdcAcmHandle->handle, *temp8);
+ }
+ }
+ break;
+ case kUSB_DeviceClassEventClearEndpointHalt:
+ if ((NULL == cdcAcmHandle->configStruct) || (NULL == cdcAcmHandle->commInterfaceHandle) ||
+ (NULL == cdcAcmHandle->dataInterfaceHandle))
+ {
+ break;
+ }
+ temp8 = ((uint8_t *)param);
+ for (count = 0; count < cdcAcmHandle->commInterfaceHandle->endpointList.count; count++)
+ {
+ if (*temp8 == cdcAcmHandle->commInterfaceHandle->endpointList.endpoint[count].endpointAddress)
+ {
+ error = USB_DeviceUnstallEndpoint(cdcAcmHandle->handle, *temp8);
+ if (USB_IN == (((*temp8) & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT))
+ {
+ if (0U != cdcAcmHandle->interruptIn.pipeStall)
+ {
+ cdcAcmHandle->interruptIn.pipeStall = 0U;
+ if ((uint8_t *)USB_INVALID_TRANSFER_BUFFER != cdcAcmHandle->interruptIn.pipeDataBuffer)
+ {
+ error = USB_DeviceSendRequest(cdcAcmHandle->handle, (cdcAcmHandle->interruptIn.ep),
+ cdcAcmHandle->interruptIn.pipeDataBuffer,
+ cdcAcmHandle->interruptIn.pipeDataLen);
+ if (kStatus_USB_Success != error)
+ {
+ usb_device_endpoint_callback_message_struct_t endpointCallbackMessage;
+ endpointCallbackMessage.buffer = cdcAcmHandle->interruptIn.pipeDataBuffer;
+ endpointCallbackMessage.length = cdcAcmHandle->interruptIn.pipeDataLen;
+ endpointCallbackMessage.isSetup = 0U;
+ (void)USB_DeviceCdcAcmBulkIn(cdcAcmHandle->handle, (void *)&endpointCallbackMessage,
+ handle);
+ }
+ cdcAcmHandle->interruptIn.pipeDataBuffer = (uint8_t *)USB_INVALID_TRANSFER_BUFFER;
+ cdcAcmHandle->interruptIn.pipeDataLen = 0U;
+ }
+ }
+ }
+ }
+ }
+ for (count = 0; count < cdcAcmHandle->dataInterfaceHandle->endpointList.count; count++)
+ {
+ if (*temp8 == cdcAcmHandle->dataInterfaceHandle->endpointList.endpoint[count].endpointAddress)
+ {
+ error = USB_DeviceUnstallEndpoint(cdcAcmHandle->handle, *temp8);
+ if (USB_IN == (((*temp8) & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT))
+ {
+ if (0U != cdcAcmHandle->bulkIn.pipeStall)
+ {
+ cdcAcmHandle->bulkIn.pipeStall = 0U;
+ if ((uint8_t *)USB_INVALID_TRANSFER_BUFFER != cdcAcmHandle->bulkIn.pipeDataBuffer)
+ {
+ error = USB_DeviceSendRequest(cdcAcmHandle->handle, (cdcAcmHandle->bulkIn.ep),
+ cdcAcmHandle->bulkIn.pipeDataBuffer,
+ cdcAcmHandle->bulkIn.pipeDataLen);
+ if (kStatus_USB_Success != error)
+ {
+ usb_device_endpoint_callback_message_struct_t endpointCallbackMessage;
+ endpointCallbackMessage.buffer = cdcAcmHandle->bulkIn.pipeDataBuffer;
+ endpointCallbackMessage.length = cdcAcmHandle->bulkIn.pipeDataLen;
+ endpointCallbackMessage.isSetup = 0U;
+ (void)USB_DeviceCdcAcmBulkIn(cdcAcmHandle->handle, (void *)&endpointCallbackMessage,
+ handle);
+ }
+ cdcAcmHandle->bulkIn.pipeDataBuffer = (uint8_t *)USB_INVALID_TRANSFER_BUFFER;
+ cdcAcmHandle->bulkIn.pipeDataLen = 0U;
+ }
+ }
+ }
+ else
+ {
+ if (0U != cdcAcmHandle->bulkOut.pipeStall)
+ {
+ cdcAcmHandle->bulkOut.pipeStall = 0U;
+ if ((uint8_t *)USB_INVALID_TRANSFER_BUFFER != cdcAcmHandle->bulkOut.pipeDataBuffer)
+ {
+ error = USB_DeviceRecvRequest(cdcAcmHandle->handle, (cdcAcmHandle->bulkOut.ep),
+ cdcAcmHandle->bulkOut.pipeDataBuffer,
+ cdcAcmHandle->bulkOut.pipeDataLen);
+ if (kStatus_USB_Success != error)
+ {
+ usb_device_endpoint_callback_message_struct_t endpointCallbackMessage;
+ endpointCallbackMessage.buffer = cdcAcmHandle->bulkOut.pipeDataBuffer;
+ endpointCallbackMessage.length = cdcAcmHandle->bulkOut.pipeDataLen;
+ endpointCallbackMessage.isSetup = 0U;
+ (void)USB_DeviceCdcAcmBulkOut(cdcAcmHandle->handle,
+ (void *)&endpointCallbackMessage, handle);
+ }
+ cdcAcmHandle->bulkOut.pipeDataBuffer = (uint8_t *)USB_INVALID_TRANSFER_BUFFER;
+ cdcAcmHandle->bulkOut.pipeDataLen = 0U;
+ }
+ }
+ }
+ }
+ }
+ break;
+ case kUSB_DeviceClassEventClassRequest:
+
+ {
+ usb_device_control_request_struct_t *controlRequest = (usb_device_control_request_struct_t *)param;
+
+ if ((controlRequest->setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) !=
+ USB_REQUEST_TYPE_RECIPIENT_INTERFACE)
+ {
+ break;
+ }
+
+ if ((controlRequest->setup->wIndex & 0xFFU) != cdcAcmHandle->interfaceNumber)
+ {
+ break;
+ }
+
+ error = kStatus_USB_InvalidRequest;
+ /* Standard CDC request */
+ reqParam.buffer = &(controlRequest->buffer);
+ reqParam.length = &(controlRequest->length);
+ reqParam.interfaceIndex = controlRequest->setup->wIndex;
+ reqParam.setupValue = controlRequest->setup->wValue;
+ reqParam.isSetup = controlRequest->isSetup;
+ switch (controlRequest->setup->bRequest)
+ {
+ case USB_DEVICE_CDC_REQUEST_SEND_ENCAPSULATED_COMMAND:
+ if (((controlRequest->setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) ==
+ USB_REQUEST_TYPE_DIR_OUT) &&
+ (controlRequest->setup->wLength != 0U))
+ {
+ /* classCallback is initialized in classInit of s_UsbDeviceClassInterfaceMap,
+ it is from the second parameter of classInit */
+ error = cdcAcmHandle->configStruct->classCallback(
+ (class_handle_t)cdcAcmHandle, kUSB_DeviceCdcEventSendEncapsulatedCommand, &reqParam);
+ }
+ break;
+ case USB_DEVICE_CDC_REQUEST_GET_ENCAPSULATED_RESPONSE:
+ if (((controlRequest->setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) ==
+ USB_REQUEST_TYPE_DIR_IN) &&
+ (controlRequest->setup->wLength != 0U))
+ {
+ /* classCallback is initialized in classInit of s_UsbDeviceClassInterfaceMap,
+ it is from the second parameter of classInit */
+ error = cdcAcmHandle->configStruct->classCallback(
+ (class_handle_t)cdcAcmHandle, kUSB_DeviceCdcEventGetEncapsulatedResponse, &reqParam);
+ }
+ break;
+ case USB_DEVICE_CDC_REQUEST_SET_COMM_FEATURE:
+ if (((controlRequest->setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) ==
+ USB_REQUEST_TYPE_DIR_OUT) &&
+ (controlRequest->setup->wLength != 0U))
+ {
+ /* classCallback is initialized in classInit of s_UsbDeviceClassInterfaceMap,
+ it is from the second parameter of classInit */
+ error = cdcAcmHandle->configStruct->classCallback((class_handle_t)cdcAcmHandle,
+ kUSB_DeviceCdcEventSetCommFeature, &reqParam);
+ }
+ break;
+ case USB_DEVICE_CDC_REQUEST_GET_COMM_FEATURE:
+ if (((controlRequest->setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) ==
+ USB_REQUEST_TYPE_DIR_IN) &&
+ (controlRequest->setup->wLength != 0U))
+ {
+ /* classCallback is initialized in classInit of s_UsbDeviceClassInterfaceMap,
+ it is from the second parameter of classInit */
+ error = cdcAcmHandle->configStruct->classCallback((class_handle_t)cdcAcmHandle,
+ kUSB_DeviceCdcEventGetCommFeature, &reqParam);
+ }
+ break;
+ case USB_DEVICE_CDC_REQUEST_CLEAR_COMM_FEATURE:
+ if (((controlRequest->setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) ==
+ USB_REQUEST_TYPE_DIR_OUT) &&
+ (controlRequest->setup->wLength == 0U))
+ {
+ /* classCallback is initialized in classInit of s_UsbDeviceClassInterfaceMap,
+ it is from the second parameter of classInit */
+ error = cdcAcmHandle->configStruct->classCallback(
+ (class_handle_t)cdcAcmHandle, kUSB_DeviceCdcEventClearCommFeature, &reqParam);
+ }
+ break;
+ case USB_DEVICE_CDC_REQUEST_GET_LINE_CODING:
+ if (((controlRequest->setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) ==
+ USB_REQUEST_TYPE_DIR_IN) &&
+ (controlRequest->setup->wLength != 0U))
+ {
+ /* classCallback is initialized in classInit of s_UsbDeviceClassInterfaceMap,
+ it is from the second parameter of classInit */
+ error = cdcAcmHandle->configStruct->classCallback((class_handle_t)cdcAcmHandle,
+ kUSB_DeviceCdcEventGetLineCoding, &reqParam);
+ }
+ break;
+ case USB_DEVICE_CDC_REQUEST_SET_LINE_CODING:
+ if (((controlRequest->setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) ==
+ USB_REQUEST_TYPE_DIR_OUT) &&
+ (controlRequest->setup->wLength != 0U))
+ {
+ /* classCallback is initialized in classInit of s_UsbDeviceClassInterfaceMap,
+ it is from the second parameter of classInit */
+ error = cdcAcmHandle->configStruct->classCallback((class_handle_t)cdcAcmHandle,
+ kUSB_DeviceCdcEventSetLineCoding, &reqParam);
+ }
+ break;
+ case USB_DEVICE_CDC_REQUEST_SET_CONTROL_LINE_STATE:
+ if (((controlRequest->setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) ==
+ USB_REQUEST_TYPE_DIR_OUT) &&
+ (controlRequest->setup->wLength == 0U))
+ {
+ /* classCallback is initialized in classInit of s_UsbDeviceClassInterfaceMap,
+ it is from the second parameter of classInit */
+ error = cdcAcmHandle->configStruct->classCallback(
+ (class_handle_t)cdcAcmHandle, kUSB_DeviceCdcEventSetControlLineState, &reqParam);
+ }
+ break;
+ case USB_DEVICE_CDC_REQUEST_SEND_BREAK:
+ if (((controlRequest->setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) ==
+ USB_REQUEST_TYPE_DIR_OUT) &&
+ (controlRequest->setup->wLength == 0U))
+ {
+ /* classCallback is initialized in classInit of s_UsbDeviceClassInterfaceMap,
+ it is from the second parameter of classInit */
+ error = cdcAcmHandle->configStruct->classCallback((class_handle_t)cdcAcmHandle,
+ kUSB_DeviceCdcEventSendBreak, &reqParam);
+ }
+ break;
+ default:
+ /* no action, return kStatus_USB_InvalidRequest */
+ break;
+ }
+ }
+ break;
+ default:
+ /*no action*/
+ break;
+ }
+ return error;
+}
+
+/*!
+ * @brief Initializes the USB CDC ACM class.
+ *
+ * This function obtains a usb device handle according to the controller id, initializes the CDC ACM class
+ * with the class configure parameters and creates the mutex for each pipe.
+ *
+ * @param controllerId The id of the controller. The value can be choosen from kUSB_ControllerKhci0,
+ * kUSB_ControllerKhci1, kUSB_ControllerEhci0 or kUSB_ControllerEhci1.
+ * @param config The user configuration structure of type usb_device_class_config_struct_t. The user
+ * populates the members of this structure and passes the pointer of this structure
+ * into this function.
+ * @param handle It is out parameter. The class handle of the CDC ACM class.
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceCdcAcmInit(uint8_t controllerId,
+ usb_device_class_config_struct_t *config,
+ class_handle_t *handle)
+{
+ usb_device_cdc_acm_struct_t *cdcAcmHandle;
+ usb_status_t error;
+
+ error = USB_DeviceCdcAcmAllocateHandle(&cdcAcmHandle);
+
+ if (kStatus_USB_Success != error)
+ {
+ return error;
+ }
+
+ error = USB_DeviceClassGetDeviceHandle(controllerId, &cdcAcmHandle->handle);
+
+ if (kStatus_USB_Success != error)
+ {
+ return error;
+ }
+
+ if (NULL == cdcAcmHandle->handle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+ cdcAcmHandle->configStruct = config;
+ cdcAcmHandle->configuration = 0;
+ cdcAcmHandle->alternate = 0xFF;
+
+ cdcAcmHandle->bulkIn.mutex = (osa_mutex_handle_t)&cdcAcmHandle->bulkIn.mutexBuffer[0];
+ if (KOSA_StatusSuccess != OSA_MutexCreate((cdcAcmHandle->bulkIn.mutex)))
+ {
+#if 0
+ (void)usb_echo("mutex create error!");
+#endif
+ }
+ cdcAcmHandle->bulkOut.mutex = (osa_mutex_handle_t)&cdcAcmHandle->bulkOut.mutexBuffer[0];
+ if (KOSA_StatusSuccess != OSA_MutexCreate((cdcAcmHandle->bulkOut.mutex)))
+ {
+#if 0
+ (void)usb_echo("mutex create error!");
+#endif
+ }
+ cdcAcmHandle->interruptIn.mutex = (osa_mutex_handle_t)&cdcAcmHandle->interruptIn.mutexBuffer[0];
+ if (KOSA_StatusSuccess != OSA_MutexCreate((cdcAcmHandle->interruptIn.mutex)))
+ {
+#if 0
+ (void)usb_echo("mutex create error!");
+#endif
+ }
+ *handle = (class_handle_t)cdcAcmHandle;
+ return error;
+}
+
+/*!
+ * @brief De-Initializes the USB CDC ACM class.
+ *
+ * This function destroys the mutex for each pipe, deinit each endpoint of the CDC ACM class and free
+ * the CDC ACM class handle.
+ *
+ * @param handle The class handle of the CDC ACM class.
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceCdcAcmDeinit(class_handle_t handle)
+{
+ usb_device_cdc_acm_struct_t *cdcAcmHandle;
+ usb_status_t error;
+
+ cdcAcmHandle = (usb_device_cdc_acm_struct_t *)handle;
+
+ if (NULL == cdcAcmHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+ if (KOSA_StatusSuccess != OSA_MutexDestroy((cdcAcmHandle->bulkIn.mutex)))
+ {
+#if 0
+ (void)usb_echo("mutex destroy error!");
+#endif
+ }
+ if (KOSA_StatusSuccess != OSA_MutexDestroy((cdcAcmHandle->bulkOut.mutex)))
+ {
+#if 0
+ (void)usb_echo("mutex destroy error!");
+#endif
+ }
+ if (KOSA_StatusSuccess != OSA_MutexDestroy((cdcAcmHandle->interruptIn.mutex)))
+ {
+#if 0
+ (void)usb_echo("mutex destroy error!");
+#endif
+ }
+ error = USB_DeviceCdcAcmEndpointsDeinit(cdcAcmHandle);
+ (void)USB_DeviceCdcAcmFreeHandle(cdcAcmHandle);
+ return error;
+}
+
+/*!
+ * @brief Prime the endpoint to send packet to host.
+ *
+ * This function checks whether the endpoint is sending packet, then it primes the endpoint
+ * with the buffer address and the buffer length if the pipe is not busy. Otherwise, it ignores this transfer by
+ * returning an error code.
+ *
+ * @param handle The class handle of the CDC ACM class.
+ * @param ep The endpoint number of the transfer.
+ * @param buffer The pointer to the buffer to be transferred.
+ * @param length The length of the buffer to be transferred.
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceCdcAcmSend(class_handle_t handle, uint8_t ep, uint8_t *buffer, uint32_t length)
+{
+ usb_device_cdc_acm_struct_t *cdcAcmHandle;
+ usb_status_t status = kStatus_USB_Error;
+ usb_device_cdc_acm_pipe_t *cdcAcmPipe = NULL;
+
+ if (NULL == handle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+ cdcAcmHandle = (usb_device_cdc_acm_struct_t *)handle;
+
+ if (cdcAcmHandle->bulkIn.ep == ep)
+ {
+ cdcAcmPipe = &(cdcAcmHandle->bulkIn);
+ }
+ else if (cdcAcmHandle->interruptIn.ep == ep)
+ {
+ cdcAcmPipe = &(cdcAcmHandle->interruptIn);
+ }
+ else
+ {
+ /*no action*/
+ }
+
+ if (NULL != cdcAcmPipe)
+ {
+ if (1U == cdcAcmPipe->isBusy)
+ {
+ return kStatus_USB_Busy;
+ }
+ cdcAcmPipe->isBusy = 1U;
+
+ if (0u != cdcAcmPipe->pipeStall)
+ {
+ cdcAcmPipe->pipeDataBuffer = buffer;
+ cdcAcmPipe->pipeDataLen = length;
+ return kStatus_USB_Success;
+ }
+
+ status = USB_DeviceSendRequest(cdcAcmHandle->handle, ep, buffer, length);
+ if (kStatus_USB_Success != status)
+ {
+ cdcAcmPipe->isBusy = 0U;
+ }
+ }
+ return status;
+}
+
+/*!
+ * @brief Prime the endpoint to receive packet from host.
+ *
+ * This function checks whether the endpoint is receiving packet, then it primes the endpoint
+ * with the buffer address and the buffer length if the pipe is not busy. Otherwise, it ignores this transfer by
+ * returning an error code.
+ *
+ * @param handle The class handle of the CDC ACM class.
+ * @param ep The endpoint number of the transfer.
+ * @param buffer The pointer to the buffer to be transferred.
+ * @param length The length of the buffer to be transferred.
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceCdcAcmRecv(class_handle_t handle, uint8_t ep, uint8_t *buffer, uint32_t length)
+{
+ usb_device_cdc_acm_struct_t *cdcAcmHandle;
+ usb_status_t status;
+ if (NULL == handle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+ cdcAcmHandle = (usb_device_cdc_acm_struct_t *)handle;
+
+ if (1U == cdcAcmHandle->bulkOut.isBusy)
+ {
+ return kStatus_USB_Busy;
+ }
+ cdcAcmHandle->bulkOut.isBusy = 1U;
+
+ if (0U != cdcAcmHandle->bulkOut.pipeStall)
+ {
+ cdcAcmHandle->bulkOut.pipeDataBuffer = buffer;
+ cdcAcmHandle->bulkOut.pipeDataLen = length;
+ return kStatus_USB_Success;
+ }
+
+ status = USB_DeviceRecvRequest(cdcAcmHandle->handle, ep, buffer, length);
+ if (kStatus_USB_Success != status)
+ {
+ cdcAcmHandle->bulkOut.isBusy = 0U;
+ }
+ return status;
+}
+
+#endif /* USB_DEVICE_CONFIG_CDC_ACM */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/device/class/cdc/usb_device_cdc_acm.h b/minimal-examples/embedded/rt595/hello_world/project/usb/device/class/cdc/usb_device_cdc_acm.h
new file mode 100644
index 000000000..1577c8043
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/device/class/cdc/usb_device_cdc_acm.h
@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016,2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _USB_DEVICE_CDC_ACM_H_
+#define _USB_DEVICE_CDC_ACM_H_
+
+/*!
+ * @addtogroup cdc_acm
+ * @{
+ */
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+#define USB_DEVICE_CONFIG_CDC_ACM_MAX_INSTANCE (1U) /*!< The maximum number of CDC device instance. */
+#define USB_DEVICE_CONFIG_CDC_COMM_CLASS_CODE (0x02U) /*!< The CDC communication class code. */
+#define USB_DEVICE_CONFIG_CDC_DATA_CLASS_CODE (0x0AU) /*!< The CDC data class code. */
+
+#define USB_DEVICE_CDC_REQUEST_SEND_ENCAPSULATED_COMMAND \
+ (0x00) /*!< The CDC class request code for SEND_ENCAPSULATED_COMMAND. */
+#define USB_DEVICE_CDC_REQUEST_GET_ENCAPSULATED_RESPONSE \
+ (0x01) /*!< The CDC class request code for GET_ENCAPSULATED_RESPONSE. */
+#define USB_DEVICE_CDC_REQUEST_SET_COMM_FEATURE (0x02) /*!< The CDC class request code for SET_COMM_FEATURE. */
+#define USB_DEVICE_CDC_REQUEST_GET_COMM_FEATURE (0x03) /*!< The CDC class request code for GET_COMM_FEATURE. */
+#define USB_DEVICE_CDC_REQUEST_CLEAR_COMM_FEATURE (0x04) /*!< The CDC class request code for CLEAR_COMM_FEATURE. */
+#define USB_DEVICE_CDC_REQUEST_SET_AUX_LINE_STATE (0x10) /*!< The CDC class request code for SET_AUX_LINE_STATE. */
+#define USB_DEVICE_CDC_REQUEST_SET_HOOK_STATE (0x11) /*!< The CDC class request code for SET_HOOK_STATE. */
+#define USB_DEVICE_CDC_REQUEST_PULSE_SETUP (0x12) /*!< The CDC class request code for PULSE_SETUP. */
+#define USB_DEVICE_CDC_REQUEST_SEND_PULSE (0x13) /*!< The CDC class request code for SEND_PULSE. */
+#define USB_DEVICE_CDC_REQUEST_SET_PULSE_TIME (0x14) /*!< The CDC class request code for SET_PULSE_TIME. */
+#define USB_DEVICE_CDC_REQUEST_RING_AUX_JACK (0x15) /*!< The CDC class request code for RING_AUX_JACK. */
+#define USB_DEVICE_CDC_REQUEST_SET_LINE_CODING (0x20) /*!< The CDC class request code for SET_LINE_CODING. */
+#define USB_DEVICE_CDC_REQUEST_GET_LINE_CODING (0x21) /*!< The CDC class request code for GET_LINE_CODING. */
+#define USB_DEVICE_CDC_REQUEST_SET_CONTROL_LINE_STATE \
+ (0x22) /*!< The CDC class request code for SET_CONTROL_LINE_STATE. */
+#define USB_DEVICE_CDC_REQUEST_SEND_BREAK (0x23) /*!< The CDC class request code for SEND_BREAK. */
+#define USB_DEVICE_CDC_REQUEST_SET_RINGER_PARAMS (0x30) /*!< The CDC class request code for SET_RINGER_PARAMS. */
+#define USB_DEVICE_CDC_REQUEST_GET_RINGER_PARAMS (0x31) /*!< The CDC class request code for GET_RINGER_PARAMS. */
+#define USB_DEVICE_CDC_REQUEST_SET_OPERATION_PARAM (0x32) /*!< The CDC class request code for SET_OPERATION_PARAM. */
+#define USB_DEVICE_CDC_REQUEST_GET_OPERATION_PARAM (0x33) /*!< The CDC class request code for GET_OPERATION_PARAM. */
+#define USB_DEVICE_CDC_REQUEST_SET_LINE_PARAMS (0x34) /*!< The CDC class request code for SET_LINE_PARAMS. */
+#define USB_DEVICE_CDC_REQUEST_GET_LINE_PARAMS (0x35) /*!< The CDC class request code for GET_LINE_PARAMS. */
+#define USB_DEVICE_CDC_REQUEST_DIAL_DIGITS (0x36) /*!< The CDC class request code for DIAL_DIGITS. */
+#define USB_DEVICE_CDC_REQUEST_SET_UNIT_PARAMETER (0x37) /*!< The CDC class request code for SET_UNIT_PARAMETER. */
+#define USB_DEVICE_CDC_REQUEST_GET_UNIT_PARAMETER (0x38) /*!< The CDC class request code for GET_UNIT_PARAMETER. */
+#define USB_DEVICE_CDC_REQUEST_CLEAR_UNIT_PARAMETER \
+ (0x39) /*!< The CDC class request code for CLEAR_UNIT_PARAMETER. */
+#define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS \
+ (0x40) /*!< The CDC class request code for SET_ETHERNET_MULTICAST_FILTERS. */
+#define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_POW_PATTER_FILTER \
+ (0x41) /*!< The CDC class request code for SET_ETHERNET_POW_PATTER_FILTER. */
+#define USB_DEVICE_CDC_REQUEST_GET_ETHERNET_POW_PATTER_FILTER \
+ (0x42) /*!< The CDC class request code for GET_ETHERNET_POW_PATTER_FILTER. */
+#define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_PACKET_FILTER \
+ (0x43) /*!< The CDC class request code for SET_ETHERNET_PACKET_FILTER. */
+#define USB_DEVICE_CDC_REQUEST_GET_ETHERNET_STATISTIC \
+ (0x44) /*!< The CDC class request code for GET_ETHERNET_STATISTIC. */
+#define USB_DEVICE_CDC_REQUEST_SET_ATM_DATA_FORMAT (0x50) /*!< The CDC class request code for SET_ATM_DATA_FORMAT. */
+#define USB_DEVICE_CDC_REQUEST_GET_ATM_DEVICE_STATISTICS \
+ (0x51) /*!< The CDC class request code for GET_ATM_DEVICE_STATISTICS. */
+#define USB_DEVICE_CDC_REQUEST_SET_ATM_DEFAULT_VC (0x52) /*!< The CDC class request code for SET_ATM_DEFAULT_VC. */
+#define USB_DEVICE_CDC_REQUEST_GET_ATM_VC_STATISTICS \
+ (0x53) /*!< The CDC class request code for GET_ATM_VC_STATISTICS. */
+#define USB_DEVICE_CDC_REQUEST_MDLM_SPECIFIC_REQUESTS_MASK \
+ (0x7F) /*!< The CDC class request code for MDLM_SPECIFIC_REQUESTS_MASK. */
+
+#define USB_DEVICE_CDC_NOTIF_NETWORK_CONNECTION (0x00) /*!< The CDC class notify code for NETWORK_CONNECTION. */
+#define USB_DEVICE_CDC_NOTIF_RESPONSE_AVAIL (0x01) /*!< The CDC class notify code for RESPONSE_AVAIL. */
+#define USB_DEVICE_CDC_NOTIF_AUX_JACK_HOOK_STATE (0x08) /*!< The CDC class notify code for AUX_JACK_HOOK_STATE. */
+#define USB_DEVICE_CDC_NOTIF_RING_DETECT (0x09) /*!< The CDC class notify code for RING_DETECT. */
+#define USB_DEVICE_CDC_NOTIF_SERIAL_STATE (0x20) /*!< The CDC class notify code for SERIAL_STATE. */
+#define USB_DEVICE_CDC_NOTIF_CALL_STATE_CHANGE (0x28) /*!< The CDC class notify code for CALL_STATE_CHANGE. */
+#define USB_DEVICE_CDC_NOTIF_LINE_STATE_CHANGE (0x29) /*!< The CDC class notify code for LINE_STATE_CHANGE. */
+#define USB_DEVICE_CDC_NOTIF_CONNECTION_SPEED_CHANGE \
+ (0x2A) /*!< The CDC class notify code for CONNECTION_SPEED_CHANGE. */
+
+#define USB_DEVICE_CDC_FEATURE_ABSTRACT_STATE (0x01) /*!< The CDC class feature select code for ABSTRACT_STATE. */
+#define USB_DEVICE_CDC_FEATURE_COUNTRY_SETTING (0x02) /*!< The CDC class feature select code for COUNTRY_SETTING. */
+
+#define USB_DEVICE_CDC_CONTROL_SIG_BITMAP_CARRIER_ACTIVATION \
+ (0x02) /*!< The CDC class control signal bitmap value for CARRIER_ACTIVATION. */
+#define USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE \
+ (0x01) /*!< The CDC class control signal bitmap value for DTE_PRESENCE. */
+#define USB_DEVICE_CDC_UART_STATE_RX_CARRIER (0x01) /*!< The UART state bitmap value of RX_CARRIER. */
+#define USB_DEVICE_CDC_UART_STATE_TX_CARRIER (0x02) /*!< The UART state bitmap value of TX_CARRIER. */
+#define USB_DEVICE_CDC_UART_STATE_BREAK (0x04) /*!< The UART state bitmap value of BREAK. */
+#define USB_DEVICE_CDC_UART_STATE_RING_SIGNAL (0x08) /*!< The UART state bitmap value of RING_SIGNAL. */
+#define USB_DEVICE_CDC_UART_STATE_FRAMING (0x10) /*!< The UART state bitmap value of FRAMING. */
+#define USB_DEVICE_CDC_UART_STATE_PARITY (0x20) /*!< The UART state bitmap value of PARITY. */
+#define USB_DEVICE_CDC_UART_STATE_OVERRUN (0x40) /*!< The UART state bitmap value of OVERRUN. */
+
+/*! @brief Definition of CDC class event. */
+typedef enum _usb_device_cdc_acm_event
+{
+ kUSB_DeviceCdcEventSendResponse = 0x01, /*!< This event indicates the bulk send transfer is complete or cancelled etc. */
+ kUSB_DeviceCdcEventRecvResponse, /*!< This event indicates the bulk receive transfer is complete or cancelled etc.. */
+ kUSB_DeviceCdcEventSerialStateNotif, /*!< This event indicates the serial state has been sent to the host. */
+ kUSB_DeviceCdcEventSendEncapsulatedCommand, /*!< This event indicates the device received the
+ SEND_ENCAPSULATED_COMMAND request. */
+ kUSB_DeviceCdcEventGetEncapsulatedResponse, /*!< This event indicates the device received the
+ GET_ENCAPSULATED_RESPONSE request. */
+ kUSB_DeviceCdcEventSetCommFeature, /*!< This event indicates the device received the SET_COMM_FEATURE request. */
+ kUSB_DeviceCdcEventGetCommFeature, /*!< This event indicates the device received the GET_COMM_FEATURE request. */
+ kUSB_DeviceCdcEventClearCommFeature, /*!< This event indicates the device received the CLEAR_COMM_FEATURE request.
+ */
+ kUSB_DeviceCdcEventGetLineCoding, /*!< This event indicates the device received the GET_LINE_CODING request. */
+ kUSB_DeviceCdcEventSetLineCoding, /*!< This event indicates the device received the SET_LINE_CODING request. */
+ kUSB_DeviceCdcEventSetControlLineState, /*!< This event indicates the device received the SET_CONTRL_LINE_STATE
+ request. */
+ kUSB_DeviceCdcEventSendBreak /*!< This event indicates the device received the SEND_BREAK request. */
+} usb_device_cdc_acm_event_t;
+
+/*! @brief Definition of parameters for CDC ACM request. */
+typedef struct _usb_device_cdc_acm_request_param_struct
+{
+ uint8_t **buffer; /*!< The pointer to the address of the buffer for CDC class request. */
+ uint32_t *length; /*!< The pointer to the length of the buffer for CDC class request. */
+ uint16_t interfaceIndex; /*!< The interface index of the setup packet. */
+ uint16_t setupValue; /*!< The wValue field of the setup packet. */
+ uint8_t isSetup; /*!< The flag indicates if it is a setup packet, 1: yes, 0: no. */
+} usb_device_cdc_acm_request_param_struct_t;
+
+/*! @brief Definition of pipe structure. */
+typedef struct _usb_device_cdc_acm_pipe
+{
+ osa_mutex_handle_t mutex; /*!< The mutex of the pipe. */
+ uint32_t mutexBuffer[(OSA_MUTEX_HANDLE_SIZE + 3)/4];
+ uint8_t *pipeDataBuffer; /*!< pipe data buffer backup when stall */
+ uint32_t pipeDataLen; /*!< pipe data length backup when stall */
+ uint8_t pipeStall; /*!< pipe is stall */
+ uint8_t ep; /*!< The endpoint number of the pipe. */
+ uint8_t isBusy; /*!< 1: The pipe is transferring packet, 0: The pipe is idle. */
+} usb_device_cdc_acm_pipe_t;
+
+/*! @brief Definition of structure for CDC ACM device. */
+typedef struct _usb_device_cdc_acm_struct
+{
+ usb_device_handle handle; /*!< The handle of the USB device. */
+ usb_device_class_config_struct_t *configStruct; /*!< The class configure structure. */
+ usb_device_interface_struct_t *commInterfaceHandle; /*!< The CDC communication interface handle. */
+ usb_device_interface_struct_t *dataInterfaceHandle; /*!< The CDC data interface handle. */
+ usb_device_cdc_acm_pipe_t bulkIn; /*!< The bulk in pipe for sending packet to host. */
+ usb_device_cdc_acm_pipe_t bulkOut; /*!< The bulk out pipe for receiving packet from host. */
+ usb_device_cdc_acm_pipe_t interruptIn; /*!< The interrupt in pipe for notifying the device state to host. */
+ uint8_t configuration; /*!< The current configuration value. */
+ uint8_t interfaceNumber; /*!< The current interface number. */
+ uint8_t alternate; /*!< The alternate setting value of the interface. */
+ uint8_t hasSentState; /*!< 1: The device has primed the state in interrupt pipe, 0: Not primed the state. */
+} usb_device_cdc_acm_struct_t;
+
+/*******************************************************************************
+* API
+******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name USB CDC ACM Class Driver
+ * @{
+ */
+/*!
+ * @brief Initializes the USB CDC ACM class.
+ *
+ * This function obtains a USB device handle according to the controller ID, initializes the CDC ACM class
+ * with the class configure parameters and creates the mutex for each pipe.
+ *
+ * @param controllerId The ID of the controller. The value can be chosen from the kUSB_ControllerKhci0,
+ * kUSB_ControllerKhci1, kUSB_ControllerEhci0, or kUSB_ControllerEhci1.
+ * @param config The user configuration structure of type usb_device_class_config_struct_t. The user
+ * populates the members of this structure and passes the pointer of this structure
+ * into this function.
+ * @param handle It is out parameter. The class handle of the CDC ACM class.
+ * @return A USB error code or kStatus_USB_Success.
+ * @retval kStatus_USB_Success The CDC ACM class is initialized successfully.
+ * @retval kStatus_USB_Busy No CDC ACM device handle available for allocation.
+ * @retval kStatus_USB_InvalidHandle The CDC ACM device handle allocation failure.
+ * @retval kStatus_USB_InvalidParameter The USB device handle allocation failure.
+ */
+extern usb_status_t USB_DeviceCdcAcmInit(uint8_t controllerId,
+ usb_device_class_config_struct_t *config,
+ class_handle_t *handle);
+/*!
+ * @brief Deinitializes the USB CDC ACM class.
+ *
+ * This function destroys the mutex for each pipe, deinitializes each endpoint of the CDC ACM class and frees
+ * the CDC ACM class handle.
+ *
+ * @param handle The class handle of the CDC ACM class.
+ * @return A USB error code or kStatus_USB_Success.
+ * @retval kStatus_USB_Success The CDC ACM class is de-initialized successfully.
+ * @retval kStatus_USB_Error The endpoint deinitialization failure.
+ * @retval kStatus_USB_InvalidHandle The CDC ACM device handle or the CDC ACM class handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The endpoint number of the CDC ACM class handle is invalid.
+ */
+extern usb_status_t USB_DeviceCdcAcmDeinit(class_handle_t handle);
+/*!
+ * @brief Handles the CDC ACM class event.
+ *
+ * This function responds to various events including the common device events and the class-specific events.
+ * For class-specific events, it calls the class callback defined in the application to deal with the class-specific
+ * event.
+ *
+ * @param handle The class handle of the CDC ACM class.
+ * @param event The event type.
+ * @param param The class handle of the CDC ACM class.
+ * @return A USB error code or kStatus_USB_Success.
+ * @retval kStatus_USB_Success The CDC ACM class is de-initialized successfully.
+ * @retval kStatus_USB_Error The configure structure of the CDC ACM class handle is invalid.
+ * @retval kStatus_USB_InvalidHandle The CDC ACM device handle or the CDC ACM class handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The endpoint number of the CDC ACM class handle is invalid.
+ * @retval Others The error code returned by class callback in application.
+ */
+extern usb_status_t USB_DeviceCdcAcmEvent(void *handle, uint32_t event, void *param);
+
+/*!
+ * @brief Primes the endpoint to send packet to host.
+ *
+ * This function checks whether the endpoint is sending packet, then it primes the endpoint
+ * with the buffer address and the buffer length if the pipe is not busy. Otherwise, it ignores this transfer by
+ * returning an error code.
+ *
+ * @param handle The class handle of the CDC ACM class.
+ * @param ep The endpoint number of the transfer.
+ * @param buffer The pointer to the buffer to be transferred.
+ * @param length The length of the buffer to be transferred.
+ * @return A USB error code or kStatus_USB_Success.
+ * @retval kStatus_USB_Success Prime to send packet successfully.
+ * @retval kStatus_USB_Busy The endpoint is busy in transferring.
+ * @retval kStatus_USB_InvalidHandle The CDC ACM device handle or the CDC ACM class handle is invalid.
+ * @retval kStatus_USB_ControllerNotFound The controller interface is invalid.
+ *
+ * @note The function can only be called in the same context.
+ */
+extern usb_status_t USB_DeviceCdcAcmSend(class_handle_t handle, uint8_t ep, uint8_t *buffer, uint32_t length);
+/*!
+ * @brief Primes the endpoint to receive packet from host.
+ *
+ * This function checks whether the endpoint is receiving packet, then it primes the endpoint
+ * with the buffer address and the buffer length if the pipe is not busy. Otherwise, it ignores this transfer by
+ * returning an error code.
+ *
+ * @param handle The class handle of the CDC ACM class.
+ * @param ep The endpoint number of the transfer.
+ * @param buffer The pointer to the buffer to be transferred.
+ * @param length The length of the buffer to be transferred.
+ * @return A USB error code or kStatus_USB_Success.
+ * @retval kStatus_USB_Success Prime to receive packet successfully.
+ * @retval kStatus_USB_Busy The endpoint is busy in transferring.
+ * @retval kStatus_USB_InvalidHandle The CDC ACM device handle or the CDC ACM class handle is invalid.
+ * @retval kStatus_USB_ControllerNotFound The controller interface is invalid.
+ *
+ * @note The function can only be called in the same context.
+ */
+extern usb_status_t USB_DeviceCdcAcmRecv(class_handle_t handle, uint8_t ep, uint8_t *buffer, uint32_t length);
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _USB_DEVICE_CDC_ACM_H_ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/device/class/usb_device_class.c b/minimal-examples/embedded/rt595/hello_world/project/usb/device/class/usb_device_class.c
new file mode 100644
index 000000000..71e4049dc
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/device/class/usb_device_class.c
@@ -0,0 +1,595 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "usb_device_config.h"
+#include "usb.h"
+
+#include "usb_device.h"
+#include "usb_device_ch9.h"
+#include "usb_device_class.h"
+
+#if ((defined(USB_DEVICE_CONFIG_NUM)) && (USB_DEVICE_CONFIG_NUM > 0U))
+/* Include the class drivers according to the usb_device_config.h. */
+#if ((defined(USB_DEVICE_CONFIG_HID)) && (USB_DEVICE_CONFIG_HID > 0U))
+#include "usb_device_hid.h"
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_CDC_ACM)) && (USB_DEVICE_CONFIG_CDC_ACM > 0U))
+#include "usb_device_cdc_acm.h"
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_MSC)) && (USB_DEVICE_CONFIG_MSC > 0U))
+#include "usb_device_msc.h"
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_MTP)) && (USB_DEVICE_CONFIG_MTP > 0U))
+#include "usb_device_mtp.h"
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_AUDIO)) && (USB_DEVICE_CONFIG_AUDIO > 0U))
+#include "usb_device_audio.h"
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_PHDC)) && (USB_DEVICE_CONFIG_PHDC > 0U))
+#include "usb_device_phdc.h"
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_VIDEO)) && (USB_DEVICE_CONFIG_VIDEO > 0U))
+#include "usb_device_video.h"
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_PRINTER)) && (USB_DEVICE_CONFIG_PRINTER > 0U))
+#include "usb_device_printer.h"
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_DFU)) && (USB_DEVICE_CONFIG_DFU > 0U))
+#include "usb_device_dfu.h"
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_CCID)) && (USB_DEVICE_CONFIG_CCID > 0U))
+#include "usb_device_ccid.h"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static usb_status_t USB_DeviceClassAllocateHandle(uint8_t controllerId, usb_device_common_class_struct_t **handle);
+static usb_status_t USB_DeviceClassFreeHandle(uint8_t controllerId);
+static usb_status_t USB_DeviceClassGetHandleByControllerId(uint8_t controllerId,
+ usb_device_common_class_struct_t **handle);
+static usb_status_t USB_DeviceClassGetHandleByDeviceHandle(usb_device_handle deviceHandle,
+ usb_device_common_class_struct_t **handle);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* The device class driver list. */
+static const usb_device_class_map_t s_UsbDeviceClassInterfaceMap[] = {
+#if ((defined(USB_DEVICE_CONFIG_HID)) && (USB_DEVICE_CONFIG_HID > 0U))
+ {USB_DeviceHidInit, USB_DeviceHidDeinit, USB_DeviceHidEvent, kUSB_DeviceClassTypeHid},
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_CDC_ACM)) && (USB_DEVICE_CONFIG_CDC_ACM > 0U))
+ {USB_DeviceCdcAcmInit, USB_DeviceCdcAcmDeinit, USB_DeviceCdcAcmEvent, kUSB_DeviceClassTypeCdc},
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_MSC)) && (USB_DEVICE_CONFIG_MSC > 0U))
+ {USB_DeviceMscInit, USB_DeviceMscDeinit, USB_DeviceMscEvent, kUSB_DeviceClassTypeMsc},
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_MTP)) && (USB_DEVICE_CONFIG_MTP > 0U))
+ {USB_DeviceMtpInit, USB_DeviceMtpDeinit, USB_DeviceMtpEvent, kUSB_DeviceClassTypeMtp},
+#endif
+
+#if ((defined USB_DEVICE_CONFIG_AUDIO) && (USB_DEVICE_CONFIG_AUDIO > 0U))
+ {USB_DeviceAudioInit, USB_DeviceAudioDeinit, USB_DeviceAudioEvent, kUSB_DeviceClassTypeAudio},
+#endif
+
+#if ((defined USB_DEVICE_CONFIG_PHDC) && (USB_DEVICE_CONFIG_PHDC > 0U))
+ {USB_DevicePhdcInit, USB_DevicePhdcDeinit, USB_DevicePhdcEvent, kUSB_DeviceClassTypePhdc},
+#endif
+
+#if ((defined USB_DEVICE_CONFIG_VIDEO) && (USB_DEVICE_CONFIG_VIDEO > 0U))
+ {USB_DeviceVideoInit, USB_DeviceVideoDeinit, USB_DeviceVideoEvent, kUSB_DeviceClassTypeVideo},
+#endif
+
+#if ((defined USB_DEVICE_CONFIG_PRINTER) && (USB_DEVICE_CONFIG_PRINTER > 0U))
+ {USB_DevicePrinterInit, USB_DevicePrinterDeinit, USB_DevicePrinterEvent, kUSB_DeviceClassTypePrinter},
+#endif
+
+#if ((defined USB_DEVICE_CONFIG_DFU) && (USB_DEVICE_CONFIG_DFU > 0U))
+ {USB_DeviceDfuInit, USB_DeviceDfuDeinit, USB_DeviceDfuEvent, kUSB_DeviceClassTypeDfu},
+#endif
+
+#if ((defined USB_DEVICE_CONFIG_CCID) && (USB_DEVICE_CONFIG_CCID > 0U))
+ {USB_DeviceCcidInit, USB_DeviceCcidDeinit, USB_DeviceCcidEvent, kUSB_DeviceClassTypeCcid},
+#endif
+
+ /* please make sure the following member is in the end of s_UsbDeviceClassInterfaceMap*/
+ {(usb_device_class_init_call_t)NULL, (usb_device_class_deinit_call_t)NULL, (usb_device_class_event_callback_t)NULL,
+ (usb_device_class_type_t)0},
+};
+
+USB_GLOBAL USB_RAM_ADDRESS_ALIGNMENT(USB_DATA_ALIGN_SIZE) static usb_device_common_class_struct_t
+ s_UsbDeviceCommonClassStruct[USB_DEVICE_CONFIG_NUM];
+USB_GLOBAL USB_RAM_ADDRESS_ALIGNMENT(USB_DATA_ALIGN_SIZE) static uint8_t
+ s_UsbDeviceSetupBuffer[USB_DEVICE_CONFIG_NUM][USB_DATA_ALIGN_SIZE_MULTIPLE(USB_SETUP_PACKET_SIZE)];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Allocate a device common class handle.
+ *
+ * This function allocates a a device common class handle.
+ *
+ * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t.
+ * @param handle It is out parameter, is used to return pointer of the device common class handle to the
+ * caller.
+ *
+ * @retval kStatus_USB_Success Get a device handle successfully.
+ * @retval kStatus_USB_Busy Cannot allocate a common class handle.
+ * @retval kStatus_USB_Error The common class has been initialized.
+ */
+static usb_status_t USB_DeviceClassAllocateHandle(uint8_t controllerId, usb_device_common_class_struct_t **handle)
+{
+ uint32_t count;
+ OSA_SR_ALLOC();
+
+ OSA_ENTER_CRITICAL();
+ /* Check the controller is initialized or not. */
+ for (count = 0U; count < USB_DEVICE_CONFIG_NUM; count++)
+ {
+ if ((NULL != s_UsbDeviceCommonClassStruct[count].handle) &&
+ (controllerId == s_UsbDeviceCommonClassStruct[count].controllerId))
+ {
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_Error;
+ }
+ }
+ /* Get a free common class handle. */
+ for (count = 0U; count < USB_DEVICE_CONFIG_NUM; count++)
+ {
+ if (NULL == s_UsbDeviceCommonClassStruct[count].handle)
+ {
+ s_UsbDeviceCommonClassStruct[count].controllerId = controllerId;
+ s_UsbDeviceCommonClassStruct[count].setupBuffer = s_UsbDeviceSetupBuffer[count];
+ *handle = &s_UsbDeviceCommonClassStruct[count];
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_Success;
+ }
+ }
+
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_Busy;
+}
+
+/*!
+ * @brief Free a device common class handle.
+ *
+ * This function frees a device common class handle.
+ *
+ * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t.
+ *
+ * @retval kStatus_USB_Success Free device handle successfully.
+ * @retval kStatus_USB_InvalidParameter The common class can not be found.
+ */
+static usb_status_t USB_DeviceClassFreeHandle(uint8_t controllerId)
+{
+ uint32_t count = 0U;
+ OSA_SR_ALLOC();
+
+ OSA_ENTER_CRITICAL();
+ for (; count < USB_DEVICE_CONFIG_NUM; count++)
+ {
+ if ((NULL != s_UsbDeviceCommonClassStruct[count].handle) &&
+ (controllerId == s_UsbDeviceCommonClassStruct[count].controllerId))
+ {
+ s_UsbDeviceCommonClassStruct[count].handle = NULL;
+ s_UsbDeviceCommonClassStruct[count].configList = (usb_device_class_config_list_struct_t *)NULL;
+ s_UsbDeviceCommonClassStruct[count].controllerId = 0U;
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_Success;
+ }
+ }
+ OSA_EXIT_CRITICAL();
+
+ return kStatus_USB_InvalidParameter;
+}
+
+/*!
+ * @brief Get the device common class handle according to the controller id.
+ *
+ * This function gets the device common class handle according to the controller id.
+ *
+ * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t.
+ * @param handle It is out parameter, is used to return pointer of the device common class handle to the
+ * caller.
+ *
+ * @retval kStatus_USB_Success Free device handle successfully.
+ * @retval kStatus_USB_InvalidParameter The common class can not be found.
+ */
+static usb_status_t USB_DeviceClassGetHandleByControllerId(uint8_t controllerId,
+ usb_device_common_class_struct_t **handle)
+{
+ uint32_t count = 0U;
+ OSA_SR_ALLOC();
+
+ OSA_ENTER_CRITICAL();
+ for (; count < USB_DEVICE_CONFIG_NUM; count++)
+ {
+ if ((NULL != s_UsbDeviceCommonClassStruct[count].handle) &&
+ (controllerId == s_UsbDeviceCommonClassStruct[count].controllerId))
+ {
+ *handle = &s_UsbDeviceCommonClassStruct[count];
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_Success;
+ }
+ }
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_InvalidParameter;
+}
+
+/*!
+ * @brief Get the device common class handle according to the device handle.
+ *
+ * This function gets the device common class handle according to the device handle.
+ *
+ * @param deviceHandle The device handle, got from the USB_DeviceInit.
+ * @param handle It is out parameter, is used to return pointer of the device common class handle to the
+ * caller.
+ *
+ * @retval kStatus_USB_Success Free device handle successfully.
+ * @retval kStatus_USB_InvalidParameter The common class can not be found.
+ */
+static usb_status_t USB_DeviceClassGetHandleByDeviceHandle(usb_device_handle deviceHandle,
+ usb_device_common_class_struct_t **handle)
+{
+ uint32_t count = 0U;
+ OSA_SR_ALLOC();
+
+ OSA_ENTER_CRITICAL();
+ for (; count < USB_DEVICE_CONFIG_NUM; count++)
+ {
+ if (deviceHandle == s_UsbDeviceCommonClassStruct[count].handle)
+ {
+ *handle = &s_UsbDeviceCommonClassStruct[count];
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_Success;
+ }
+ }
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_InvalidParameter;
+}
+
+/*!
+ * @brief Get the device handle according to the controller id.
+ *
+ * This function gets the device handle according to the controller id.
+ *
+ * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t.
+ * @param handle It is out parameter, is used to return pointer of the device handle to the caller.
+ *
+ * @retval kStatus_USB_Success Free device handle successfully.
+ * @retval kStatus_USB_InvalidParameter The device handle not be found.
+ */
+usb_status_t USB_DeviceClassGetDeviceHandle(uint8_t controllerId, usb_device_handle *handle)
+{
+ uint32_t count = 0U;
+ OSA_SR_ALLOC();
+
+ OSA_ENTER_CRITICAL();
+ for (; count < USB_DEVICE_CONFIG_NUM; count++)
+ {
+ if ((NULL != s_UsbDeviceCommonClassStruct[count].handle) &&
+ (controllerId == s_UsbDeviceCommonClassStruct[count].controllerId))
+ {
+ *handle = s_UsbDeviceCommonClassStruct[count].handle;
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_Success;
+ }
+ }
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_InvalidParameter;
+}
+
+/*!
+ * @brief Handle the event passed to the class drivers.
+ *
+ * This function handles the event passed to the class drivers.
+ *
+ * @param handle The device handle, got from the USB_DeviceInit.
+ * @param event The event codes. Please refer to the enumeration usb_device_class_event_t.
+ * @param param The param type is determined by the event code.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ * @retval kStatus_USB_Success A valid request has been handled.
+ * @retval kStatus_USB_InvalidParameter The device handle not be found.
+ * @retval kStatus_USB_InvalidRequest The request is invalid, and the control pipe will be stalled by the caller.
+ */
+usb_status_t USB_DeviceClassEvent(usb_device_handle handle, usb_device_class_event_t event, void *param)
+{
+ usb_device_common_class_struct_t *classHandle;
+ uint8_t mapIndex;
+ uint8_t classIndex;
+ usb_status_t errorReturn;
+ usb_status_t status = kStatus_USB_Error;
+
+ if (NULL == param)
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+
+ /* Get the common class handle according to the device handle. */
+ errorReturn = USB_DeviceClassGetHandleByDeviceHandle(handle, &classHandle);
+ if (kStatus_USB_Success != errorReturn)
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+
+ for (classIndex = 0U; classIndex < classHandle->configList->count; classIndex++)
+ {
+ for (mapIndex = 0U; mapIndex < (ARRAY_SIZE(s_UsbDeviceClassInterfaceMap) - 1U); mapIndex++)
+ {
+ if (s_UsbDeviceClassInterfaceMap[mapIndex].type ==
+ classHandle->configList->config[classIndex].classInfomation->type)
+ {
+ /* Call class event callback of supported class */
+ errorReturn = s_UsbDeviceClassInterfaceMap[mapIndex].classEventCallback(
+ (void *)classHandle->configList->config[classIndex].classHandle, event, param);
+ /* Return the error code kStatus_USB_InvalidRequest immediately, when a class returns
+ * kStatus_USB_InvalidRequest. */
+ if (kStatus_USB_InvalidRequest == errorReturn)
+ {
+ return kStatus_USB_InvalidRequest;
+ }
+ /* For composite device, it should return kStatus_USB_Success once a valid request has been handled */
+ if (kStatus_USB_Success == errorReturn)
+ {
+ status = kStatus_USB_Success;
+ }
+ break;
+ }
+ }
+ }
+
+ return status;
+}
+
+/*!
+ * @brief Handle the common class callback.
+ *
+ * This function handles the common class callback.
+ *
+ * @param handle The device handle, got from the USB_DeviceInit.
+ * @param event The event codes. Please refer to the enumeration usb_device_event_t.
+ * @param param The param type is determined by the event code.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceClassCallback(usb_device_handle handle, uint32_t event, void *param)
+{
+ usb_device_common_class_struct_t *classHandle;
+ usb_status_t status;
+
+ /* Get the common class handle according to the device handle. */
+ status = USB_DeviceClassGetHandleByDeviceHandle(handle, &classHandle);
+ if (kStatus_USB_Success != status)
+ {
+ return status;
+ }
+
+ if ((uint32_t)kUSB_DeviceEventBusReset == event)
+ {
+ /* Initialize the control pipes */
+ (void)USB_DeviceControlPipeInit(handle, classHandle);
+
+ /* Notify the classes the USB bus reset signal detected. */
+ (void)USB_DeviceClassEvent(handle, kUSB_DeviceClassEventDeviceReset, classHandle);
+ }
+
+ /* Call the application device callback function. deviceCallback is from the second parameter of
+ USB_DeviceClassInit */
+ status = classHandle->configList->deviceCallback(handle, event, param);
+ return status;
+}
+
+/*!
+ * @brief Initialize the common class and the supported classes.
+ *
+ * This function is used to initialize the common class and the supported classes.
+ *
+ * @param[in] controllerId The controller id of the USB IP. Please refer to the enumeration #usb_controller_index_t.
+ * @param[in] configList The class configurations. The pointer must point to the global variable.
+ * Please refer to the structure #usb_device_class_config_list_struct_t.
+ * @param[out] handle It is out parameter, is used to return pointer of the device handle to the caller.
+ * The value of parameter is a pointer points the device handle, and this design is used to
+ * make simple device align with composite device. For composite device, there are many
+ * kinds of class handle, but there is only one device handle. So the handle points to
+ * a device instead of a class. And the class handle can be got from the
+ * #usb_device_class_config_struct_t::classHandle after the function successfully.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceClassInit(
+ uint8_t controllerId, /*!< [IN] Controller ID */
+ usb_device_class_config_list_struct_t *configList, /*!< [IN] Pointer to class configuration list */
+ usb_device_handle *handle /*!< [OUT] Pointer to the device handle */
+)
+{
+ usb_device_common_class_struct_t *classHandle;
+ usb_status_t error;
+ uint8_t mapIndex;
+ uint8_t classIndex;
+
+ if ((NULL == handle) || (NULL == configList) || ((usb_device_callback_t)NULL == configList->deviceCallback))
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+
+ /* Allocate a common class driver handle. */
+ error = USB_DeviceClassAllocateHandle(controllerId, &classHandle);
+ if (kStatus_USB_Success != error)
+ {
+ return error;
+ }
+ /* Save the configuration list */
+ classHandle->configList = configList;
+
+ /* Initialize the device stack. */
+ error = USB_DeviceInit(controllerId, USB_DeviceClassCallback, &classHandle->handle);
+
+ if (kStatus_USB_Success != error)
+ {
+ (void)USB_DeviceDeinit(classHandle->handle);
+ (void)USB_DeviceClassFreeHandle(controllerId);
+ return error;
+ }
+
+ /* Initialize the all supported classes according to the configuration list. */
+ for (classIndex = 0U; classIndex < classHandle->configList->count; classIndex++)
+ {
+ for (mapIndex = 0U; mapIndex < (sizeof(s_UsbDeviceClassInterfaceMap) / sizeof(usb_device_class_map_t));
+ mapIndex++)
+ {
+ if (classHandle->configList->config[classIndex].classInfomation->type ==
+ s_UsbDeviceClassInterfaceMap[mapIndex].type)
+ {
+ (void)s_UsbDeviceClassInterfaceMap[mapIndex].classInit(
+ controllerId, &classHandle->configList->config[classIndex],
+ &classHandle->configList->config[classIndex].classHandle);
+ }
+ }
+ }
+
+ *handle = classHandle->handle;
+ return error;
+}
+
+/*!
+ * @brief De-initialize the common class and the supported classes.
+ *
+ * This function is used to de-initialize the common class and the supported classes.
+ *
+ * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceClassDeinit(uint8_t controllerId /*!< [IN] Controller ID */
+)
+{
+ usb_device_common_class_struct_t *classHandle;
+ usb_status_t error;
+ uint8_t mapIndex;
+ uint8_t classIndex;
+
+ /* Get the common class handle according to the controller id. */
+ error = USB_DeviceClassGetHandleByControllerId(controllerId, &classHandle);
+
+ if (kStatus_USB_Success != error)
+ {
+ return error;
+ }
+
+ /* De-initialize the all supported classes according to the configuration list. */
+ for (classIndex = 0U; classIndex < classHandle->configList->count; classIndex++)
+ {
+ for (mapIndex = 0U; mapIndex < (sizeof(s_UsbDeviceClassInterfaceMap) / sizeof(usb_device_class_map_t));
+ mapIndex++)
+ {
+ if (classHandle->configList->config[classIndex].classInfomation->type ==
+ s_UsbDeviceClassInterfaceMap[mapIndex].type)
+ {
+ (void)s_UsbDeviceClassInterfaceMap[mapIndex].classDeinit(
+ classHandle->configList->config[classIndex].classHandle);
+ }
+ }
+ }
+
+ /* De-initialize the USB device stack. */
+ error = USB_DeviceDeinit(classHandle->handle);
+ if (kStatus_USB_Success == error)
+ {
+ /* Free the common class handle. */
+ (void)USB_DeviceClassFreeHandle(controllerId);
+ }
+ return error;
+}
+
+/*!
+ * @brief Get the USB bus speed.
+ *
+ * This function is used to get the USB bus speed.
+ *
+ * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t.
+ * @param speed It is an OUT parameter, return current speed of the controller.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceClassGetSpeed(uint8_t controllerId, /*!< [IN] Controller ID */
+ uint8_t *speed /*!< [OUT] Current speed */
+)
+{
+ usb_device_common_class_struct_t *classHandle;
+ usb_status_t error;
+
+ /* Get the common class handle according to the controller id. */
+ error = USB_DeviceClassGetHandleByControllerId(controllerId, &classHandle);
+
+ if (kStatus_USB_Success != error)
+ {
+ return error;
+ }
+
+ /* Get the current speed. */
+ error = USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusSpeed, speed);
+
+ return error;
+}
+
+#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U)
+/*!
+ * @brief Get the USB SOF count.
+ *
+ * This function is used to get the USB SOF count.
+ *
+ * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t.
+ * @param currentFrameCount It is an OUT parameter, return current sof count of the controller.
+ * HS: micro frame count, FS: frame count
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceClassGetCurrentFrameCount(uint8_t controllerId, /*!< [IN] Controller ID */
+ uint32_t *currentFrameCount /*!< [OUT] Current frame count */
+)
+{
+ usb_device_common_class_struct_t *classHandle;
+ usb_status_t error;
+
+ /* Get the common class handle according to the controller id. */
+ error = USB_DeviceClassGetHandleByControllerId(controllerId, &classHandle);
+
+ if (kStatus_USB_Success != error)
+ {
+ return error;
+ }
+
+ /* Get the current frame count. */
+ error = USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusGetCurrentFrameCount, currentFrameCount);
+
+ return error;
+}
+#endif /* USB_DEVICE_CONFIG_GET_SOF_COUNT */
+
+#endif /* USB_DEVICE_CONFIG_NUM */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/device/class/usb_device_class.h b/minimal-examples/embedded/rt595/hello_world/project/usb/device/class/usb_device_class.h
new file mode 100644
index 000000000..6589ccc31
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/device/class/usb_device_class.h
@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __USB_DEVICE_CLASS_H__
+#define __USB_DEVICE_CLASS_H__
+
+/*!
+ * @addtogroup usb_device_class_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Macro to define class handle */
+typedef void *class_handle_t;
+
+/*! @brief Available class types. */
+typedef enum _usb_usb_device_class_type
+{
+ kUSB_DeviceClassTypeHid = 1U,
+ kUSB_DeviceClassTypeCdc,
+ kUSB_DeviceClassTypeMsc,
+ kUSB_DeviceClassTypeMtp,
+ kUSB_DeviceClassTypeAudio,
+ kUSB_DeviceClassTypePhdc,
+ kUSB_DeviceClassTypeVideo,
+ kUSB_DeviceClassTypePrinter,
+ kUSB_DeviceClassTypeDfu,
+ kUSB_DeviceClassTypeCcid,
+} usb_device_class_type_t;
+
+/*! @brief Available common class events. */
+typedef enum _usb_device_class_event
+{
+ kUSB_DeviceClassEventClassRequest = 1U,
+ kUSB_DeviceClassEventDeviceReset,
+ kUSB_DeviceClassEventSetConfiguration,
+ kUSB_DeviceClassEventSetInterface,
+ kUSB_DeviceClassEventSetEndpointHalt,
+ kUSB_DeviceClassEventClearEndpointHalt,
+} usb_device_class_event_t;
+
+/*!
+ * @brief Obtains the endpoint data structure.
+ *
+ * Define the endpoint data structure.
+ *
+ */
+typedef struct _usb_device_endpoint_struct
+{
+ uint8_t endpointAddress; /*!< Endpoint address*/
+ uint8_t transferType; /*!< Endpoint transfer type*/
+ uint16_t maxPacketSize; /*!< Endpoint maximum packet size */
+ uint8_t interval; /*!< Endpoint interval*/
+} usb_device_endpoint_struct_t;
+
+/*!
+ * @brief Obtains the endpoint group.
+ *
+ * Structure representing endpoints and the number of endpoints that the user wants.
+ *
+ */
+typedef struct _usb_device_endpoint_list
+{
+ uint8_t count; /*!< How many endpoints in current interface*/
+ usb_device_endpoint_struct_t *endpoint; /*!< Endpoint structure list*/
+} usb_device_endpoint_list_t;
+
+/*!
+ * @brief Obtains the interface list data structure.
+ *
+ * Structure representing an interface.
+ *
+ */
+typedef struct _usb_device_interface_struct
+{
+ uint8_t alternateSetting; /*!< Alternate setting number*/
+ usb_device_endpoint_list_t endpointList; /*!< Endpoints of the interface*/
+ void *classSpecific; /*!< Class specific structure handle*/
+} usb_device_interface_struct_t;
+
+/*!
+ * @brief Obtains the interface data structure.
+ *
+ * Structure representing interface.
+ *
+ */
+typedef struct _usb_device_interfaces_struct
+{
+ uint8_t classCode; /*!< Class code of the interface*/
+ uint8_t subclassCode; /*!< Subclass code of the interface*/
+ uint8_t protocolCode; /*!< Protocol code of the interface*/
+ uint8_t interfaceNumber; /*!< Interface number*/
+ usb_device_interface_struct_t *interface; /*!< Interface structure list*/
+ uint8_t count; /*!< Number of interfaces in the current interface*/
+} usb_device_interfaces_struct_t;
+
+/*!
+ * @brief Obtains the interface group.
+ *
+ * Structure representing how many interfaces in one class type.
+ *
+ */
+typedef struct _usb_device_interface_list
+{
+ uint8_t count; /*!< Number of interfaces of the class*/
+ usb_device_interfaces_struct_t *interfaces; /*!< All interfaces*/
+} usb_device_interface_list_t;
+
+/*!
+ * @brief Obtains the class data structure.
+ *
+ * Structure representing how many configurations in one class type.
+ *
+ */
+typedef struct _usb_device_class_struct
+{
+ usb_device_interface_list_t *interfaceList; /*!< Interfaces of the class*/
+ usb_device_class_type_t type; /*!< Class type*/
+ uint8_t configurations; /*!< Number of configurations of the class*/
+} usb_device_class_struct_t;
+
+/*callback function pointer structure for application to provide class parameters*/
+typedef usb_status_t (*usb_device_class_callback_t)(class_handle_t classHandle,
+ uint32_t callbackEvent,
+ void *eventParam);
+
+/*!
+ * @brief Obtains the device class information structure.
+ *
+ * Structure representing the device class information. This structure only can be stored in RAM space.
+ *
+ */
+typedef struct _usb_device_class_config_struct
+{
+ usb_device_class_callback_t classCallback; /*!< Class callback function to handle the device status-related event
+ for the specified type of class*/
+ class_handle_t classHandle; /*!< The class handle of the class, filled by the common driver.*/
+ usb_device_class_struct_t *classInfomation; /*!< Detailed information of the class*/
+} usb_device_class_config_struct_t;
+
+/*!
+ * @brief Obtains the device class configuration structure.
+ *
+ * Structure representing the device class configuration information.
+ *
+ */
+typedef struct _usb_device_class_config_list_struct
+{
+ usb_device_class_config_struct_t *config; /*!< Array of class configuration structures */
+ usb_device_callback_t deviceCallback; /*!< Device callback function */
+ uint8_t count; /*!< Number of class supported */
+} usb_device_class_config_list_struct_t;
+
+/*!
+ * @brief Obtains the control request structure.
+ *
+ * This structure is used to pass the control request information.
+ * The structure is used in following two cases.
+ * 1. Case one, the host wants to send data to the device in the control data stage: @n
+ * a. If a setup packet is received, the structure is used to pass the setup packet data and wants to get the
+ * buffer to receive data sent from the host.
+ * The field isSetup is 1.
+ * The length is the requested buffer length.
+ * The buffer is filled by the class or application by using the valid buffer address.
+ * The setup is the setup packet address.
+ * b. If the data received is sent by the host, the structure is used to pass the data buffer address and the
+ * data
+ * length sent by the host.
+ * In this way, the field isSetup is 0.
+ * The buffer is the address of the data sent from the host.
+ * The length is the received data length.
+ * The setup is the setup packet address. @n
+ * 2. Case two, the host wants to get data from the device in control data stage: @n
+ * If the setup packet is received, the structure is used to pass the setup packet data and wants to get the
+ * data buffer address to send data to the host.
+ * The field isSetup is 1.
+ * The length is the requested data length.
+ * The buffer is filled by the class or application by using the valid buffer address.
+ * The setup is the setup packet address.
+ *
+ */
+typedef struct _usb_device_control_request_struct
+{
+ usb_setup_struct_t *setup; /*!< The pointer of the setup packet data. */
+ uint8_t *buffer; /*!< Pass the buffer address. */
+ uint32_t length; /*!< Pass the buffer length or requested length. */
+ uint8_t isSetup; /*!< Indicates whether a setup packet is received. */
+} usb_device_control_request_struct_t;
+
+/*! @brief Obtains the control get descriptor request common structure. */
+typedef struct _usb_device_get_descriptor_common_struct
+{
+ uint8_t *buffer; /*!< Pass the buffer address. */
+ uint32_t length; /*!< Pass the buffer length. */
+} usb_device_get_descriptor_common_struct_t;
+
+/*! @brief Obtains the control get device descriptor request structure. */
+typedef struct _usb_device_get_device_descriptor_struct
+{
+ uint8_t *buffer; /*!< Pass the buffer address. */
+ uint32_t length; /*!< Pass the buffer length. */
+} usb_device_get_device_descriptor_struct_t;
+
+/*! @brief Obtains the control get device qualifier descriptor request structure. */
+typedef struct _usb_device_get_device_qualifier_descriptor_struct
+{
+ uint8_t *buffer; /*!< Pass the buffer address. */
+ uint32_t length; /*!< Pass the buffer length. */
+} usb_device_get_device_qualifier_descriptor_struct_t;
+
+/*! @brief Obtains the control get configuration descriptor request structure. */
+typedef struct _usb_device_get_configuration_descriptor_struct
+{
+ uint8_t *buffer; /*!< Pass the buffer address. */
+ uint32_t length; /*!< Pass the buffer length. */
+ uint8_t configuration; /*!< The configuration number. */
+} usb_device_get_configuration_descriptor_struct_t;
+
+/*! @brief Obtains the control get bos descriptor request structure. */
+typedef struct _usb_device_get_bos_descriptor_struct
+{
+ uint8_t *buffer; /*!< Pass the buffer address. */
+ uint32_t length; /*!< Pass the buffer length. */
+} usb_device_get_bos_descriptor_struct_t;
+
+/*! @brief Obtains the control get string descriptor request structure. */
+typedef struct _usb_device_get_string_descriptor_struct
+{
+ uint8_t *buffer; /*!< Pass the buffer address. */
+ uint32_t length; /*!< Pass the buffer length. */
+ uint16_t languageId; /*!< Language ID. */
+ uint8_t stringIndex; /*!< String index. */
+} usb_device_get_string_descriptor_struct_t;
+
+/*! @brief Obtains the control get HID descriptor request structure. */
+typedef struct _usb_device_get_hid_descriptor_struct
+{
+ uint8_t *buffer; /*!< Pass the buffer address. */
+ uint32_t length; /*!< Pass the buffer length. */
+ uint8_t interfaceNumber; /*!< The interface number. */
+} usb_device_get_hid_descriptor_struct_t;
+
+/*! @brief Obtains the control get HID report descriptor request structure. */
+typedef struct _usb_device_get_hid_report_descriptor_struct
+{
+ uint8_t *buffer; /*!< Pass the buffer address. */
+ uint32_t length; /*!< Pass the buffer length. */
+ uint8_t interfaceNumber; /*!< The interface number. */
+} usb_device_get_hid_report_descriptor_struct_t;
+
+/*! @brief Obtains the control get HID physical descriptor request structure. */
+typedef struct _usb_device_get_hid_physical_descriptor_struct
+{
+ uint8_t *buffer; /*!< Pass the buffer address. */
+ uint32_t length; /*!< Pass the buffer length. */
+ uint8_t index; /*!< Physical index */
+ uint8_t interfaceNumber; /*!< The interface number. */
+} usb_device_get_hid_physical_descriptor_struct_t;
+
+/*! @brief Obtains the control get descriptor request common union. */
+typedef union _usb_device_get_descriptor_common_union
+{
+ usb_device_get_descriptor_common_struct_t commonDescriptor; /*!< Common structure. */
+ usb_device_get_device_descriptor_struct_t deviceDescriptor; /*!< The structure to get device descriptor. */
+ usb_device_get_device_qualifier_descriptor_struct_t
+ deviceQualifierDescriptor; /*!< The structure to get device qualifier descriptor. */
+ usb_device_get_configuration_descriptor_struct_t
+ configurationDescriptor; /*!< The structure to get configuration descriptor. */
+ usb_device_get_string_descriptor_struct_t stringDescriptor; /*!< The structure to get string descriptor. */
+ usb_device_get_hid_descriptor_struct_t hidDescriptor; /*!< The structure to get HID descriptor. */
+ usb_device_get_hid_report_descriptor_struct_t
+ hidReportDescriptor; /*!< The structure to get HID report descriptor. */
+ usb_device_get_hid_physical_descriptor_struct_t
+ hidPhysicalDescriptor; /*!< The structure to get HID physical descriptor. */
+} usb_device_get_descriptor_common_union_t;
+
+/*! @brief Define function type for class device instance initialization */
+typedef usb_status_t (*usb_device_class_init_call_t)(uint8_t controllerId,
+ usb_device_class_config_struct_t *classConfig,
+ class_handle_t *classHandle);
+/*! @brief Define function type for class device instance deinitialization, internal */
+typedef usb_status_t (*usb_device_class_deinit_call_t)(class_handle_t handle);
+/*! @brief Define function type for class device instance Event change */
+typedef usb_status_t (*usb_device_class_event_callback_t)(void *classHandle, uint32_t event, void *param);
+
+/*! @brief Define class driver interface structure. */
+typedef struct _usb_device_class_map
+{
+ usb_device_class_init_call_t classInit; /*!< Class driver initialization- entry of the class driver */
+ usb_device_class_deinit_call_t classDeinit; /*!< Class driver de-initialization*/
+ usb_device_class_event_callback_t classEventCallback; /*!< Class driver event callback*/
+ usb_device_class_type_t type; /*!< Class type*/
+} usb_device_class_map_t;
+
+/*! @brief Structure holding common class state information */
+typedef struct _usb_device_common_class_struct
+{
+ usb_device_handle handle; /*!< USB device handle*/
+ usb_device_class_config_list_struct_t *configList; /*!< USB device configure list*/
+ uint8_t *setupBuffer; /*!< Setup packet data buffer*/
+ uint16_t standardTranscationBuffer; /*!<
+ * This variable is used in:
+ * get status request
+ * get configuration request
+ * get interface request
+ * set interface request
+ * get sync frame request
+ */
+ uint8_t controllerId; /*!< Controller ID*/
+} usb_device_common_class_struct_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the common class and the supported classes.
+ *
+ * This function is used to initialize the common class and the supported classes.
+ *
+ * @param[in] controllerId The controller ID of the USB IP. See the enumeration #usb_controller_index_t.
+ * @param[in] configList The class configurations. The pointer must point to the global variable.
+ * See the structure #usb_device_class_config_list_struct_t.
+ * @param[out] handle A parameter used to return pointer of the device handle to the caller.
+ * The value of the parameter is a pointer to the device handle. This design is used to
+ * make a simple device align with the composite device. For the composite device, there are
+ * many
+ * kinds of class handles. However, there is only one device handle. Therefore, the handle
+ * points to
+ * a device instead of a class. The class handle can be received from the
+ * #usb_device_class_config_struct_t::classHandle after the function successfully.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceClassInit(uint8_t controllerId,
+ usb_device_class_config_list_struct_t *configList,
+ usb_device_handle *handle);
+
+/*!
+ * @brief Deinitializes the common class and the supported classes.
+ *
+ * This function is used to deinitialize the common class and the supported classes.
+ *
+ * @param[in] controllerId The controller ID of the USB IP. See the enumeration #usb_controller_index_t.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceClassDeinit(uint8_t controllerId);
+
+/*!
+ * @brief Gets the USB bus speed.
+ *
+ * This function is used to get the USB bus speed.
+ *
+ * @param[in] controllerId The controller ID of the USB IP. See the enumeration #usb_controller_index_t.
+ * @param[out] speed It is an OUT parameter, which returns the current speed of the controller.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceClassGetSpeed(uint8_t controllerId, uint8_t *speed);
+
+/*!
+ * @brief Handles the event passed to the class drivers.
+ *
+ * This function handles the event passed to the class drivers.
+ *
+ * @param[in] handle The device handle received from the #USB_DeviceInit.
+ * @param[in] event The event codes. See the enumeration #usb_device_class_event_t.
+ * @param[in,out] param The parameter type is determined by the event code.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ * @retval kStatus_USB_Success A valid request has been handled.
+ * @retval kStatus_USB_InvalidParameter The device handle not be found.
+ * @retval kStatus_USB_InvalidRequest The request is invalid, and the control pipe is stalled by the caller.
+ */
+usb_status_t USB_DeviceClassEvent(usb_device_handle handle, usb_device_class_event_t event, void *param);
+
+/*!
+ * @brief Handles the common class callback.
+ *
+ * This function handles the common class callback.
+ *
+ * @param[in] handle The device handle received from the #USB_DeviceInit.
+ * @param[in] event The event codes. See the enumeration #usb_device_event_t.
+ * @param[in,out] param The parameter type is determined by the event code.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceClassCallback(usb_device_handle handle, uint32_t event, void *param);
+
+/*!
+ * @brief Gets the device handle according to the controller ID.
+ *
+ * This function gets the device handle according to the controller ID.
+ *
+ * @param[in] controllerId The controller ID of the USB IP. See the enumeration #usb_controller_index_t.
+ * @param[out] handle An out parameter used to return the pointer of the device handle to the caller.
+ *
+ * @retval kStatus_USB_Success Get device handle successfully.
+ * @retval kStatus_USB_InvalidParameter The device handle can't be found.
+ */
+usb_status_t USB_DeviceClassGetDeviceHandle(uint8_t controllerId, usb_device_handle *handle);
+
+#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U)
+/*!
+ * @brief Get the USB SOF count.
+ *
+ * This function is used to get the USB SOF count.
+ *
+ * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t.
+ * @param currentFrameCount It is an OUT parameter, return current sof count of the controller.
+ * HS: micro frame count, FS: frame count
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceClassGetCurrentFrameCount(uint8_t controllerId, /*!< [IN] Controller ID */
+ uint32_t *currentFrameCount /*!< [OUT] Current frame count */
+);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __USB_DEVICE_CLASS_H__ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/device/include/usb_device.h b/minimal-examples/embedded/rt595/hello_world/project/usb/device/include/usb_device.h
new file mode 100644
index 000000000..d3262a638
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/device/include/usb_device.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __USB_DEVICE_H__
+#define __USB_DEVICE_H__
+
+#include "usb.h"
+
+/*!
+ * @addtogroup usb_device_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Defines Get/Set status Types */
+typedef enum _usb_device_status
+{
+ kUSB_DeviceStatusTestMode = 1U, /*!< Test mode */
+ kUSB_DeviceStatusSpeed, /*!< Current speed */
+ kUSB_DeviceStatusOtg, /*!< OTG status */
+ kUSB_DeviceStatusDevice, /*!< Device status */
+ kUSB_DeviceStatusEndpoint, /*!< Endpoint state usb_device_endpoint_status_t */
+ kUSB_DeviceStatusDeviceState, /*!< Device state */
+ kUSB_DeviceStatusAddress, /*!< Device address */
+ kUSB_DeviceStatusSynchFrame, /*!< Current frame */
+ kUSB_DeviceStatusBus, /*!< Bus status */
+ kUSB_DeviceStatusBusSuspend, /*!< Bus suspend */
+ kUSB_DeviceStatusBusSleep, /*!< Bus suspend */
+ kUSB_DeviceStatusBusResume, /*!< Bus resume */
+ kUSB_DeviceStatusRemoteWakeup, /*!< Remote wakeup state */
+ kUSB_DeviceStatusBusSleepResume, /*!< Bus resume */
+#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U)
+ kUSB_DeviceStatusGetCurrentFrameCount, /*!< Get current frame count */
+#endif
+} usb_device_status_t;
+
+/*! @brief Defines USB 2.0 device state */
+typedef enum _usb_device_state
+{
+ kUSB_DeviceStateConfigured = 0U, /*!< Device state, Configured*/
+ kUSB_DeviceStateAddress, /*!< Device state, Address*/
+ kUSB_DeviceStateDefault, /*!< Device state, Default*/
+ kUSB_DeviceStateAddressing, /*!< Device state, Address setting*/
+ kUSB_DeviceStateTestMode, /*!< Device state, Test mode*/
+} usb_device_state_t;
+
+/*! @brief Defines endpoint state */
+typedef enum _usb_endpoint_status
+{
+ kUSB_DeviceEndpointStateIdle = 0U, /*!< Endpoint state, idle*/
+ kUSB_DeviceEndpointStateStalled, /*!< Endpoint state, stalled*/
+} usb_device_endpoint_status_t;
+
+/*! @brief Control endpoint index */
+#define USB_CONTROL_ENDPOINT (0U)
+/*! @brief Control endpoint maxPacketSize */
+#define USB_CONTROL_MAX_PACKET_SIZE (64U)
+
+#if (USB_DEVICE_CONFIG_EHCI && (USB_CONTROL_MAX_PACKET_SIZE != (64U)))
+#error For high speed, USB_CONTROL_MAX_PACKET_SIZE must be 64!!!
+#endif
+
+/*! @brief The setup packet size of USB control transfer. */
+#define USB_SETUP_PACKET_SIZE (8U)
+/*! @brief USB endpoint mask */
+#define USB_ENDPOINT_NUMBER_MASK (0x0FU)
+
+/*! @brief uninitialized value */
+#define USB_UNINITIALIZED_VAL_32 (0xFFFFFFFFU)
+
+/*! @brief the endpoint callback length of cancelled transfer */
+#define USB_CANCELLED_TRANSFER_LENGTH (0xFFFFFFFFU)
+
+/*! @brief invalid tranfer buffer addresss */
+#define USB_INVALID_TRANSFER_BUFFER (0xFFFFFFFEU)
+
+#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U)
+/* USB device IP3511 max frame count */
+#define USB_DEVICE_IP3511_MAX_FRAME_COUNT (0x000007FFU)
+/* USB device EHCI max frame count */
+#define USB_DEVICE_EHCI_MAX_FRAME_COUNT (0x00003FFFU)
+/* USB device EHCI max frame count */
+#define USB_DEVICE_KHCI_MAX_FRAME_COUNT (0x000007FFU)
+
+/*! @brief usb device controller max frame count */
+#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
+#define USB_DEVICE_MAX_FRAME_COUNT (USB_DEVICE_KHCI_MAX_FRAME_COUNT)
+#elif (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \
+ ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)))
+#define USB_DEVICE_MAX_FRAME_COUNT (USB_DEVICE_IP3511_MAX_FRAME_COUNT)
+#elif ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
+#define USB_DEVICE_MAX_FRAME_COUNT (USB_DEVICE_EHCI_MAX_FRAME_COUNT)
+#endif
+#endif
+
+/*! @brief Available common EVENT types in device callback */
+typedef enum _usb_device_event
+{
+ kUSB_DeviceEventBusReset = 1U, /*!< USB bus reset signal detected */
+ kUSB_DeviceEventSuspend, /*!< USB bus suspend signal detected */
+ kUSB_DeviceEventResume, /*!< USB bus resume signal detected. The resume signal is driven by itself or a host */
+ kUSB_DeviceEventSleeped, /*!< USB bus LPM suspend signal detected */
+ kUSB_DeviceEventLPMResume, /*!< USB bus LPM resume signal detected. The resume signal is driven by itself or a host
+ */
+ kUSB_DeviceEventError, /*!< An error is happened in the bus. */
+ kUSB_DeviceEventDetach, /*!< USB device is disconnected from a host. */
+ kUSB_DeviceEventAttach, /*!< USB device is connected to a host. */
+ kUSB_DeviceEventSetConfiguration, /*!< Set configuration. */
+ kUSB_DeviceEventSetInterface, /*!< Set interface. */
+
+ kUSB_DeviceEventGetDeviceDescriptor, /*!< Get device descriptor. */
+ kUSB_DeviceEventGetConfigurationDescriptor, /*!< Get configuration descriptor. */
+ kUSB_DeviceEventGetStringDescriptor, /*!< Get string descriptor. */
+ kUSB_DeviceEventGetHidDescriptor, /*!< Get HID descriptor. */
+ kUSB_DeviceEventGetHidReportDescriptor, /*!< Get HID report descriptor. */
+ kUSB_DeviceEventGetHidPhysicalDescriptor, /*!< Get HID physical descriptor. */
+ kUSB_DeviceEventGetBOSDescriptor, /*!< Get configuration descriptor. */
+ kUSB_DeviceEventGetDeviceQualifierDescriptor, /*!< Get device qualifier descriptor. */
+ kUSB_DeviceEventVendorRequest, /*!< Vendor request. */
+ kUSB_DeviceEventSetRemoteWakeup, /*!< Enable or disable remote wakeup function. */
+ kUSB_DeviceEventGetConfiguration, /*!< Get current configuration index */
+ kUSB_DeviceEventGetInterface, /*!< Get current interface alternate setting value */
+ kUSB_DeviceEventSetBHNPEnable,
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U))
+ kUSB_DeviceEventDcdDetectionfinished, /*!< The DCD detection finished */
+#endif
+} usb_device_event_t;
+
+/*! @brief Endpoint callback message structure */
+typedef struct _usb_device_endpoint_callback_message_struct
+{
+ uint8_t *buffer; /*!< Transferred buffer */
+ uint32_t length; /*!< Transferred data length */
+ uint8_t isSetup; /*!< Is in a setup phase */
+} usb_device_endpoint_callback_message_struct_t;
+
+/*!
+ * @brief Endpoint callback function typedef.
+ *
+ * This callback function is used to notify the upper layer what the transfer result is.
+ * This callback pointer is passed when a specified endpoint is initialized by calling API #USB_DeviceInitEndpoint.
+ *
+ * @param handle The device handle. It equals to the value returned from #USB_DeviceInit.
+ * @param message The result of a transfer, which includes transfer buffer, transfer length, and whether is in a
+ * setup phase.
+ * phase for control pipe.
+ * @param callbackParam The parameter for this callback. It is same with
+ * usb_device_endpoint_callback_struct_t::callbackParam.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+typedef usb_status_t (*usb_device_endpoint_callback_t)(usb_device_handle handle,
+ usb_device_endpoint_callback_message_struct_t *message,
+ void *callbackParam);
+
+/*!
+ * @brief Device callback function typedef.
+ *
+ * This callback function is used to notify the upper layer that the device status has changed.
+ * This callback pointer is passed by calling API #USB_DeviceInit.
+ *
+ * @param handle The device handle. It equals the value returned from #USB_DeviceInit.
+ * @param callbackEvent The callback event type. See enumeration #usb_device_event_t.
+ * @param eventParam The event parameter for this callback. The parameter type is determined by the callback event.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+typedef usb_status_t (*usb_device_callback_t)(usb_device_handle handle, uint32_t callbackEvent, void *eventParam);
+
+/*! @brief Endpoint callback structure */
+typedef struct _usb_device_endpoint_callback_struct
+{
+ usb_device_endpoint_callback_t callbackFn; /*!< Endpoint callback function*/
+ void *callbackParam; /*!< Parameter for callback function*/
+ uint8_t isBusy;
+} usb_device_endpoint_callback_struct_t;
+
+/*! @brief Endpoint initialization structure */
+typedef struct _usb_device_endpoint_init_struct
+{
+ uint16_t maxPacketSize; /*!< Endpoint maximum packet size */
+ uint8_t endpointAddress; /*!< Endpoint address*/
+ uint8_t transferType; /*!< Endpoint transfer type*/
+ uint8_t zlt; /*!< ZLT flag*/
+ uint8_t interval; /*!< Endpoint interval*/
+} usb_device_endpoint_init_struct_t;
+
+/*! @brief Endpoint status structure */
+typedef struct _usb_device_endpoint_status_struct
+{
+ uint8_t endpointAddress; /*!< Endpoint address */
+ uint16_t endpointStatus; /*!< Endpoint status : idle or stalled */
+} usb_device_endpoint_status_struct_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @name USB device APIs
+ * @{
+ */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Initializes the USB device stack.
+ *
+ * This function initializes the USB device module specified by the controllerId.
+ *
+ * @param[in] controllerId The controller ID of the USB IP. See the enumeration #usb_controller_index_t.
+ * @param[in] deviceCallback Function pointer of the device callback.
+ * @param[out] handle It is an out parameter used to return the pointer of the device handle to the caller.
+ *
+ * @retval kStatus_USB_Success The device is initialized successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer.
+ * @retval kStatus_USB_Busy Cannot allocate a device handle.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller id.
+ * @retval kStatus_USB_InvalidControllerInterface The controller driver interfaces is invalid. There is an empty
+ * interface entity.
+ * @retval kStatus_USB_Error The macro USB_DEVICE_CONFIG_ENDPOINTS is more than the IP's endpoint number.
+ * Or, the device has been initialized.
+ * Or, the mutex or message queue is created failed.
+ */
+extern usb_status_t USB_DeviceInit(uint8_t controllerId,
+ usb_device_callback_t deviceCallback,
+ usb_device_handle *handle);
+
+/*!
+ * @brief Enables the device functionality.
+ *
+ * The function enables the device functionality, so that the device can be recognized by the host when the device
+ * detects that it has been connected to a host.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device is run successfully.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid.
+ *
+ */
+extern usb_status_t USB_DeviceRun(usb_device_handle handle);
+
+/*!
+ * @brief Disables the device functionality.
+ *
+ * The function disables the device functionality. After this function called, even if the device is detached to the
+ * host,
+ * it can't work.
+ *
+ * @param[in] handle The device handle received from #USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device is stopped successfully.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid.
+ */
+extern usb_status_t USB_DeviceStop(usb_device_handle handle);
+
+/*!
+ * @brief De-initializes the device controller.
+ *
+ * The function de-initializes the device controller specified by the handle.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device is stopped successfully.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid.
+ */
+extern usb_status_t USB_DeviceDeinit(usb_device_handle handle);
+
+/*!
+ * @brief Sends data through a specified endpoint.
+ *
+ * The function is used to send data through a specified endpoint.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] endpointAddress Endpoint index.
+ * @param[in] buffer The memory address to hold the data need to be sent. The function is not reentrant.
+ * @param[in] length The data length need to be sent.
+ *
+ * @retval kStatus_USB_Success The send request is sent successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error The device is doing reset.
+ *
+ * @note The return value indicates whether the sending request is successful or not. The transfer done is notified by
+ * the
+ * corresponding callback function.
+ * Currently, only one transfer request can be supported for one specific endpoint.
+ * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application
+ * should implement a queue on the application level.
+ * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint
+ * callback).
+ */
+extern usb_status_t USB_DeviceSendRequest(usb_device_handle handle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Receives data through a specified endpoint.
+ *
+ * The function is used to receive data through a specified endpoint. The function is not reentrant.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] endpointAddress Endpoint index.
+ * @param[in] buffer The memory address to save the received data.
+ * @param[in] length The data length want to be received.
+ *
+ * @retval kStatus_USB_Success The receive request is sent successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error The device is doing reset.
+ *
+ * @note The return value indicates whether the receiving request is successful or not. The transfer done is notified by
+ * the
+ * corresponding callback function.
+ * Currently, only one transfer request can be supported for one specific endpoint.
+ * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application
+ * should implement a queue on the application level.
+ * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint
+ * callback).
+ */
+extern usb_status_t USB_DeviceRecvRequest(usb_device_handle handle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Cancels the pending transfer in a specified endpoint.
+ *
+ * The function is used to cancel the pending transfer in a specified endpoint.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The transfer is cancelled.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer or the controller handle is invalid.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+extern usb_status_t USB_DeviceCancel(usb_device_handle handle, uint8_t endpointAddress);
+
+/*!
+ * @brief Initializes a specified endpoint.
+ *
+ * The function is used to initialize a specified endpoint. The corresponding endpoint callback is also initialized.
+ *
+ * @param[in] handle The device handle received from #USB_DeviceInit.
+ * @param[in] epInit Endpoint initialization structure. See the structure usb_device_endpoint_init_struct_t.
+ * @param[in] epCallback Endpoint callback structure. See the structure
+ * usb_device_endpoint_callback_struct_t.
+ *
+ * @retval kStatus_USB_Success The endpoint is initialized successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The epInit or epCallback is NULL pointer. Or the endpoint number is
+ * more than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+extern usb_status_t USB_DeviceInitEndpoint(usb_device_handle handle,
+ usb_device_endpoint_init_struct_t *epInit,
+ usb_device_endpoint_callback_struct_t *epCallback);
+
+/*!
+ * @brief Deinitializes a specified endpoint.
+ *
+ * The function is used to deinitializes a specified endpoint.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The endpoint is de-initialized successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+extern usb_status_t USB_DeviceDeinitEndpoint(usb_device_handle handle, uint8_t endpointAddress);
+
+/*!
+ * @brief Stalls a specified endpoint.
+ *
+ * The function is used to stall a specified endpoint.
+ *
+ * @param[in] handle The device handle received from #USB_DeviceInit.
+ * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The endpoint is stalled successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+extern usb_status_t USB_DeviceStallEndpoint(usb_device_handle handle, uint8_t endpointAddress);
+
+/*!
+ * @brief Un-stall a specified endpoint.
+ *
+ * The function is used to unstall a specified endpoint.
+ *
+ * @param[in] handle The device handle received from #USB_DeviceInit.
+ * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The endpoint is un-stalled successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+extern usb_status_t USB_DeviceUnstallEndpoint(usb_device_handle handle, uint8_t endpointAddress);
+
+/*!
+ * @brief Gets the status of the selected item.
+ *
+ * The function is used to get the status of the selected item.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] type The selected item. See the structure #usb_device_status_t.
+ * @param[out] param The parameter type is determined by the selected item.
+ *
+ * @retval kStatus_USB_Success Get status successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The parameter is NULL pointer.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error Unsupported type.
+ */
+extern usb_status_t USB_DeviceGetStatus(usb_device_handle handle, usb_device_status_t type, void *param);
+
+/*!
+ * @brief Sets the status of the selected item.
+ *
+ * The function is used to set the status of the selected item.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] type The selected item. See the structure #usb_device_status_t.
+ * @param[in] param The parameter type is determined by the selected item.
+ *
+ * @retval kStatus_USB_Success Set status successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error Unsupported type or the parameter is NULL pointer.
+ */
+extern usb_status_t USB_DeviceSetStatus(usb_device_handle handle, usb_device_status_t type, void *param);
+
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U))
+/*!
+ * @brief Enable the device dcd module.
+ *
+ * The function enable the device dcd module.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device could run.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid.
+ *
+ */
+extern usb_status_t USB_DeviceDcdEnable(usb_device_handle handle);
+
+/*!
+ * @brief Disable the device dcd module.
+ *
+ * The function disable the device dcd module.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The dcd is reset and stopped.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid.
+ *
+ */
+extern usb_status_t USB_DeviceDcdDisable(usb_device_handle handle);
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_USE_TASK)) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+/*!
+ * @brief Device task function.
+ *
+ * The function is used to handle the controller message.
+ * This function should not be called in the application directly.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+extern void USB_DeviceTaskFunction(void *deviceHandle);
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
+#if ((defined(USB_DEVICE_CONFIG_USE_TASK)) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+/*!
+ * @brief Device KHCI task function.
+ *
+ * The function is used to handle the KHCI controller message.
+ * In the bare metal environment, this function should be called periodically in the main function.
+ * In the RTOS environment, this function should be used as a function entry to create a task.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+#define USB_DeviceKhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle)
+#endif
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
+#if ((defined(USB_DEVICE_CONFIG_USE_TASK)) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+/*!
+ * @brief Device EHCI task function.
+ *
+ * The function is used to handle the EHCI controller message.
+ * In the bare metal environment, this function should be called periodically in the main function.
+ * In the RTOS environment, this function should be used as a function entry to create a task.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+#define USB_DeviceEhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle)
+#endif
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U))
+#if (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))
+/*!
+ * @brief Device ehci DCD ISR function.
+ *
+ * The function is the ehci DCD interrupt service routine.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+extern void USB_DeviceEhciIsrHSDCDFunction(void *deviceHandle);
+#endif
+#endif
+#endif
+
+#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \
+ ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)))
+#if ((defined(USB_DEVICE_CONFIG_USE_TASK)) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+/*!
+ * @brief Device LPC ip3511 controller task function.
+ *
+ * The function is used to handle the LPC ip3511 controller message.
+ * In the bare metal environment, this function should be called periodically in the main function.
+ * In the RTOS environment, this function should be used as a function entry to create a task.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+#define USB_DeviceLpcIp3511TaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle)
+#endif
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U))
+#if (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))
+/*!
+ * @brief Device IP3511 DCD ISR function.
+ *
+ * The function is the IP3511 DCD interrupt service routine.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+extern void USB_DeviceLpcIp3511IsrDCDFunction(void *deviceHandle);
+#endif
+#endif
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
+/*!
+ * @brief Device KHCI ISR function.
+ *
+ * The function is the KHCI interrupt service routine.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+extern void USB_DeviceKhciIsrFunction(void *deviceHandle);
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U))
+#if (defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U))
+#if 0U /* it is not implemented yet */
+/*!
+ * @brief Device KHCI DCD ISR function.
+ *
+ * The function is the KHCI DCD interrupt service routine.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+extern void USB_DeviceDcdIsrFunction(void *deviceHandle);
+#endif
+#endif
+#endif
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
+/*!
+ * @brief Device EHCI ISR function.
+ *
+ * The function is the EHCI interrupt service routine.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+extern void USB_DeviceEhciIsrFunction(void *deviceHandle);
+#endif
+
+#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \
+ ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)))
+/*!
+ * @brief Device LPC USB ISR function.
+ *
+ * The function is the LPC USB interrupt service routine.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+extern void USB_DeviceLpcIp3511IsrFunction(void *deviceHandle);
+#endif
+
+#if (((defined(USB_DEVICE_CONFIG_DWC3)) && (USB_DEVICE_CONFIG_DWC3 > 0U)) || \
+ ((defined(USB_DEVICE_CONFIG_DWC3)) && (USB_DEVICE_CONFIG_DWC3 > 0U)))
+/*!
+ * @brief Device USB DWC3 ISR function.
+ *
+ * The function is the USB interrupt service routine.
+ *
+ * @param[in] deviceHandle The device handle got from #USB_DeviceInit.
+ */
+extern void USB_DeviceDwc3IsrFunction(void *deviceHandle);
+#endif
+
+/*!
+ * @brief Gets the device stack version function.
+ *
+ * The function is used to get the device stack version.
+ *
+ * @param[out] version The version structure pointer to keep the device stack version.
+ *
+ */
+extern void USB_DeviceGetVersion(uint32_t *version);
+
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) || \
+ (((defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U))))
+/*!
+ * @brief Update the hardware tick.
+ *
+ * The function is used to update the hardware tick.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] tick Current hardware tick(uint is ms).
+ *
+ */
+extern usb_status_t USB_DeviceUpdateHwTick(usb_device_handle handle, uint64_t tick);
+#endif
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* __USB_DEVICE_H__ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/lpcip3511/usb_device_lpcip3511.c b/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/lpcip3511/usb_device_lpcip3511.c
new file mode 100644
index 000000000..2776c6855
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/lpcip3511/usb_device_lpcip3511.c
@@ -0,0 +1,2567 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2017,2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "usb_device_config.h"
+#include "usb.h"
+#include "usb_device.h"
+#include "fsl_device_registers.h"
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \
+ ((defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)))
+#include "usb_hsdcd.h"
+#endif
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U))
+#include "usb_phy.h"
+#endif
+#endif
+#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \
+ ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)))
+#include "usb_device_dci.h"
+#include "usb_device_lpcip3511.h"
+
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+
+#define USB_LPC3511IP_INTSTAT_DEV_INT_MASK USBHSD_INTSTAT_DEV_INT_MASK
+#define USB_LPC3511IP_INTSTAT_FRAME_INT_MASK USBHSD_INTSTAT_FRAME_INT_MASK
+
+#define USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AO_MASK USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AI_MASK USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK
+
+#define USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_MASK USBHSD_DEVCMDSTAT_LPM_REWP_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_SHIFT USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT
+
+#define USB_LPC3511IP_DEVCMDSTAT_Speed_MASK USBHSD_DEVCMDSTAT_Speed_MASK
+
+#define USB_LPC3511IP_DEVCMDSTAT_DCON_MASK USBHSD_DEVCMDSTAT_DCON_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_DEV_EN_MASK USBHSD_DEVCMDSTAT_DEV_EN_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_LPM_SUP_MASK USBHSD_DEVCMDSTAT_LPM_SUP_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_LPM_SUS_MASK USBHSD_DEVCMDSTAT_LPM_SUS_MASK
+
+#define USB_LPC3511IP_USB_LPM_HIRD_SW USBHSD_LPM_HIRD_SW
+
+#define USB_LPC3511IP_DEVCMDSTAT_DEV_ADDR_MASK USBHSD_DEVCMDSTAT_DEV_ADDR_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_DSUS_MASK USBHSD_DEVCMDSTAT_DSUS_MASK
+#define USB_LPC3511IP_INFO_ERR_CODE_MASK USBHSD_INFO_ERR_CODE_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_SETUP_MASK USBHSD_DEVCMDSTAT_SETUP_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_DRES_C_MASK USBHSD_DEVCMDSTAT_DRES_C_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_DSUS_C_MASK USBHSD_DEVCMDSTAT_DSUS_C_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_DCON_C_MASK USBHSD_DEVCMDSTAT_DCON_C_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_VBUS_DEBOUNCED_MASK USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK
+#define USB_LPC3511IP_INFO_FRAME_NR_MASK USBHSD_INFO_FRAME_NR_MASK
+#define USB_LPC3511IP_INFO_FRAME_NR_SHIFT USBHSD_INFO_FRAME_NR_SHIFT
+#else
+#define USB_LPC3511IP_INTSTAT_DEV_INT_MASK USB_INTSTAT_DEV_INT_MASK
+#define USB_LPC3511IP_INTSTAT_FRAME_INT_MASK USB_INTSTAT_FRAME_INT_MASK
+
+#define USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AO_MASK USB_DEVCMDSTAT_INTONNAK_AO_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AI_MASK USB_DEVCMDSTAT_INTONNAK_AI_MASK
+
+#define USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_MASK USB_DEVCMDSTAT_LPM_REWP_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_SHIFT USB_DEVCMDSTAT_LPM_REWP_SHIFT
+
+#define USB_LPC3511IP_DEVCMDSTAT_DCON_MASK USB_DEVCMDSTAT_DCON_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_DEV_EN_MASK USB_DEVCMDSTAT_DEV_EN_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_LPM_SUP_MASK USB_DEVCMDSTAT_LPM_SUP_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_LPM_SUP_MASK USB_DEVCMDSTAT_LPM_SUP_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_LPM_SUS_MASK USB_DEVCMDSTAT_LPM_SUS_MASK
+
+#define USB_LPC3511IP_USB_LPM_HIRD_SW USB_LPM_HIRD_SW
+
+#define USB_LPC3511IP_DEVCMDSTAT_DEV_ADDR_MASK USB_DEVCMDSTAT_DEV_ADDR_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_DSUS_MASK USB_DEVCMDSTAT_DSUS_MASK
+#define USB_LPC3511IP_INFO_ERR_CODE_MASK USB_INFO_ERR_CODE_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_SETUP_MASK USB_DEVCMDSTAT_SETUP_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_DRES_C_MASK USB_DEVCMDSTAT_DRES_C_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_DSUS_C_MASK USB_DEVCMDSTAT_DSUS_C_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_DCON_C_MASK USB_DEVCMDSTAT_DCON_C_MASK
+#define USB_LPC3511IP_DEVCMDSTAT_VBUS_DEBOUNCED_MASK USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK
+#define USB_LPC3511IP_INFO_FRAME_NR_MASK USB_INFO_FRAME_NR_MASK
+#define USB_LPC3511IP_INFO_FRAME_NR_SHIFT USB_INFO_FRAME_NR_SHIFT
+#endif
+
+#define USB_LPC3511IP_USB_LPM_ADPPROBE_MASK (0x00100000u)
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* on Aruba IP3511 (USB0 FS), there are 8 physical EPs, on IP3511 HS (USB1 FS), there are 10 physical EPs. */
+#define USB_LPC3511IP_MAX_PHY_ENDPOINT_MASK (0xFFFFu)
+
+/*! @brief endpoint command status, buffer address offset */
+#define USB_LPC3511IPHS_ENDPOINT_BUFFER_ADDRESS_OFFSET_MASK (0x000007FFu)
+#define USB_LPC3511IPHS_ENDPOINT_BUFFER_NBYTES_SHIFT (11)
+#define USB_LPC3511IPHS_ENDPOINT_BUFFER_NBYTES_MASK (0x03FFF800u)
+#define USB_LPC3511IPFS_ENDPOINT_BUFFER_ADDRESS_OFFSET_MASK (0x0000FFFFu)
+#define USB_LPC3511IPFS_ENDPOINT_BUFFER_NBYTES_SHIFT (16)
+#define USB_LPC3511IPFS_ENDPOINT_BUFFER_NBYTES_MASK (0x03FF0000u)
+
+#define USB_LPC3511IP_ENDPOINT_ENDPOINT_TYPE_MASK (0x01UL << 26)
+#define USB_LPC3511IP_ENDPOINT_RFTV_MASK (0x01UL << 27)
+#define USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK (0x01UL << 28)
+#define USB_LPC3511IP_ENDPOINT_STALL_MASK (0x01UL << 29)
+#define USB_LPC3511IP_ENDPOINT_STALL_SHIFT (29)
+#define USB_LPC3511IP_ENDPOINT_DISABLE_MASK (0x01UL << 30)
+#define USB_LPC3511IP_ENDPOINT_ACTIVE_MASK (0x01UL << 31)
+#define USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT (26)
+
+#define USB_LPC3511IP_DEVCMDSTAT_INTERRUPT_WC_MASK (0x0F000000u)
+
+#define USB_LPC3511IP_ENDPOINT_SET_ENDPOINT_AND(lpcState, index, odd, value) \
+ *((volatile uint32_t *)(((uint32_t)((lpcState)->epCommandStatusList)) | ((uint32_t)(index) << 3) | \
+ ((((uint32_t)(odd)) & 1UL) << 2U))) &= (value)
+
+/*! @brief Set endpoint command/status value */
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+#define USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpcState, index, odd, value, NBytes, address) \
+ \
+ *((volatile uint32_t *)(((uint32_t)((lpcState)->epCommandStatusList)) | ((uint32_t)(index) << 3) | \
+ (((((uint32_t)(odd)) & 1UL)) << 2U))) = \
+ ((0U != lpc3511IpState->controllerSpeed) ? \
+ \
+ ((uint32_t)(value) | ((uint32_t)(NBytes) << USB_LPC3511IPHS_ENDPOINT_BUFFER_NBYTES_SHIFT) | \
+ (((uint32_t)(address) >> 6) & USB_LPC3511IPHS_ENDPOINT_BUFFER_ADDRESS_OFFSET_MASK)) : \
+ \
+ ((uint32_t)(value) | ((uint32_t)(NBytes) << USB_LPC3511IPFS_ENDPOINT_BUFFER_NBYTES_SHIFT) | \
+ (((uint32_t)(address) >> 6) & USB_LPC3511IPFS_ENDPOINT_BUFFER_ADDRESS_OFFSET_MASK)))
+#else
+#define USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpcState, index, odd, value, NBytes, address) \
+ \
+ *((volatile uint32_t *)(((uint32_t)((lpcState)->epCommandStatusList)) | ((uint32_t)(index) << 3) | \
+ (((((uint32_t)(odd)) & 1U)) << 2U))) = \
+ ((uint32_t)(value) | ((uint32_t)(NBytes) << USB_LPC3511IPFS_ENDPOINT_BUFFER_NBYTES_SHIFT) | \
+ (((uint32_t)(address) >> 6) & USB_LPC3511IPFS_ENDPOINT_BUFFER_ADDRESS_OFFSET_MASK))
+#endif
+
+#define USB_LPC3511IP_ENDPOINT_DES_INDEX(endpoint) \
+ (((((endpoint)) & 0x0FU) << 1) + \
+ ((0U != ((endpoint)&USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK)) ? (1U) : (0U)))
+
+#define USB_LPC3511IP_GET_MULTIPLE_OF_64(n) ((((uint32_t)n) + 63U) & 0xFFFFFFC0U)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static usb_status_t USB_DeviceLpc3511IpTransaction(usb_device_lpc3511ip_state_struct_t *lpc3511IpState,
+ usb_device_lpc3511ip_endpoint_state_struct_t *epState,
+ uint8_t endpointIndex);
+static usb_status_t USB_DeviceLpc3511IpControlPreSetDeviceAddress(usb_device_controller_handle controllerHandle,
+ void *param);
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* define the reserved buffer for endpoint max packet copy */
+#define SETUP_TRANSFER_DATA_SIZE (64U) /* The actual size is 8. Here use 64 aligned to 64-byte boundaries. */
+#define CONTROL_TRANSFER_DATA_SIZE (64U) /* The maximum size in the control data stage. */
+#define ZERO_TRANSFER_DATA_SIZE (64U) /* The actual size is 4. Here use 64 aligned to 64-byte boundaries. */
+#define SETUP_TRANSFER_DATA_OFFSET (0U)
+#define CONTROL_TRANSFER_DATA_OFFSET (SETUP_TRANSFER_DATA_SIZE >> 2U)
+#define ZERO_TRANSFER_DATA_OFFSET ((SETUP_TRANSFER_DATA_SIZE + CONTROL_TRANSFER_DATA_SIZE) >> 2U)
+#define RESERVED_EP_DATA_OFFSET \
+ ((SETUP_TRANSFER_DATA_SIZE + CONTROL_TRANSFER_DATA_SIZE + ZERO_TRANSFER_DATA_SIZE) >> 2U)
+
+#define ENDPOINT_RESERVED_BUFFER_ADDRESS ((uint8_t *)&s_SetupAndEpReservedData[0])
+
+#if defined(USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)
+USB_GLOBAL USB_RAM_ADDRESS_ALIGNMENT(64) static uint32_t
+ s_SetupAndEpReservedData[(USB_DEVICE_IP3511_BITS_FOR_RESERVED_BUFFER << 6U) >> 2U];
+static uint8_t s_EpReservedBufferBits[(USB_DEVICE_IP3511_BITS_FOR_RESERVED_BUFFER + 7U) / 8U];
+#else
+USB_GLOBAL USB_RAM_ADDRESS_ALIGNMENT(64) static uint32_t
+ s_SetupAndEpReservedData[USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS][RESERVED_EP_DATA_OFFSET];
+#endif
+
+static usb_device_lpc3511ip_state_struct_t
+ s_UsbDeviceLpc3511IpState[USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS];
+
+/* LPC3511IP controller driver instances and endpoint command/status list, EPLISTSTART's value is the buffer pointer. */
+#if ((USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS) == 1U)
+USB_CONTROLLER_DATA USB_RAM_ADDRESS_ALIGNMENT(256) static uint32_t
+ s_EpCommandStatusList1[((USB_DEVICE_IP3511_ENDPOINTS_NUM)) * 4];
+#define LPC_CONTROLLER_ENDPOINT_LIST_ARRAY \
+ { \
+ &s_EpCommandStatusList1[0] \
+ }
+
+#elif ((USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS) == 2U)
+USB_CONTROLLER_DATA USB_RAM_ADDRESS_ALIGNMENT(256) static uint32_t
+ s_EpCommandStatusList1[(USB_DEVICE_IP3511_ENDPOINTS_NUM)*4];
+USB_CONTROLLER_DATA USB_RAM_ADDRESS_ALIGNMENT(256) static uint32_t
+ s_EpCommandStatusList2[(USB_DEVICE_IP3511_ENDPOINTS_NUM)*4];
+#define LPC_CONTROLLER_ENDPOINT_LIST_ARRAY \
+ { \
+ &s_EpCommandStatusList1[0], &s_EpCommandStatusList2[0] \
+ }
+
+#else
+#error "increase the instance count."
+#endif
+
+#if (defined USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)
+#if (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY == (USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS))
+#define USB_DEVICE_IP3511_ALL_IP_SUPPORT_RESERVED_BUFFER 1U
+#elif ((USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY == USB_DEVICE_CONFIG_LPCIP3511FS) && \
+ (!USB_DEVICE_CONFIG_LPCIP3511HS))
+#define USB_DEVICE_IP3511_ALL_IP_SUPPORT_RESERVED_BUFFER 1U
+#elif ((USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY == USB_DEVICE_CONFIG_LPCIP3511HS) && \
+ (!USB_DEVICE_CONFIG_LPCIP3511FS))
+#define USB_DEVICE_IP3511_ALL_IP_SUPPORT_RESERVED_BUFFER 1U
+#else
+#define USB_DEVICE_IP3511_ALL_IP_SUPPORT_RESERVED_BUFFER 0U
+#endif
+
+#else
+#define USB_DEVICE_IP3511_ALL_IP_SUPPORT_RESERVED_BUFFER 0U
+
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if (defined USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)
+
+static inline uint8_t USB_DeviceLpcIp3511MaxPacketNeedCopy(usb_device_lpc3511ip_state_struct_t *lpc3511IpState)
+{
+#if (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY == (USB_DEVICE_CONFIG_LPCIP3511HS + USB_DEVICE_CONFIG_LPCIP3511FS))
+ return 1U;
+#elif (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY == USB_DEVICE_CONFIG_LPCIP3511HS)
+ return (lpc3511IpState->controllerSpeed);
+#elif (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY == USB_DEVICE_CONFIG_LPCIP3511FS)
+#if (defined USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS)
+ if (0U != lpc3511IpState->controllerSpeed)
+ {
+ return 0U;
+ }
+ else
+ {
+ return 1U;
+ }
+#else
+ return 1U;
+#endif
+#endif
+}
+
+static uint8_t *USB_DeviceLpcIp3511MallocMaxPacketBuffer(uint32_t multile64)
+{
+ uint32_t bitsIndex;
+ uint32_t numIndex;
+ OSA_SR_ALLOC();
+
+ multile64 = ((multile64 + 63U) / 64U);
+ bitsIndex = 0U;
+ OSA_ENTER_CRITICAL();
+ do
+ {
+ numIndex = 0U;
+ for (; numIndex < multile64; ++numIndex)
+ {
+ if (bitsIndex >= USB_DEVICE_IP3511_BITS_FOR_RESERVED_BUFFER)
+ {
+ OSA_EXIT_CRITICAL();
+ return NULL; /* fail */
+ }
+ if (0U != (s_EpReservedBufferBits[(bitsIndex / 8U)] &
+ (uint8_t)(0x01U << (bitsIndex & 0x00000007U)))) /* has allocated */
+ {
+ bitsIndex++;
+ break;
+ }
+ bitsIndex++;
+ }
+ } while (numIndex < multile64);
+
+ if (numIndex >= multile64)
+ {
+ /* set the bits */
+ for (numIndex = 0U; numIndex < multile64; ++numIndex)
+ {
+ s_EpReservedBufferBits[((bitsIndex - multile64 + numIndex) / 8U)] |=
+ (uint8_t)(0x01U << ((bitsIndex - multile64 + numIndex) & 0x00000007U));
+ }
+ OSA_EXIT_CRITICAL();
+ return ENDPOINT_RESERVED_BUFFER_ADDRESS + ((bitsIndex - multile64) * 64U);
+ }
+ else
+ {
+ OSA_EXIT_CRITICAL();
+ return NULL;
+ }
+}
+
+static void USB_DeviceLpcIp3511ReleaseMaxPacketBuffer(uint8_t *buffer, uint32_t bufferSize)
+{
+ uint32_t bitsIndex;
+ int32_t temp;
+ uint8_t bitsNum;
+ OSA_SR_ALLOC();
+
+ if ((buffer < ENDPOINT_RESERVED_BUFFER_ADDRESS) ||
+ (buffer >= (ENDPOINT_RESERVED_BUFFER_ADDRESS + USB_DEVICE_IP3511_ENDPOINT_RESERVED_BUFFER_SIZE)))
+ {
+ return;
+ }
+ /*misra 10.8*/
+ temp = ((buffer - ENDPOINT_RESERVED_BUFFER_ADDRESS) / 64);
+ bitsIndex = (uint32_t)temp;
+
+ OSA_ENTER_CRITICAL();
+ for (bitsNum = 0; bitsNum < ((bufferSize + 63U) / 64U); ++bitsNum)
+ {
+ s_EpReservedBufferBits[((bitsIndex + bitsNum) / 8U)] &=
+ (uint8_t)(~(0x01U << ((bitsIndex + bitsNum) & 0x00000007U))); /* clear the bit */
+ }
+ OSA_EXIT_CRITICAL();
+}
+#endif
+
+static usb_device_lpc3511ip_endpoint_state_struct_t *USB_DeviceLpc3511IpGetEndpointStateStruct(
+ usb_device_lpc3511ip_state_struct_t *lpc3511IpState, uint8_t endpointIndex)
+{
+ if (endpointIndex <= ((uint32_t)USB_DEVICE_IP3511_ENDPOINTS_NUM * 2U))
+ {
+ return &(lpc3511IpState->endpointState[endpointIndex]);
+ }
+
+ return NULL;
+}
+
+/*!
+ * @brief Write the command/status entry to start a transfer.
+ *
+ * The function is used to start a transfer by writing the command/status entry.
+ *
+ * @param lpc3511IpState Pointer of the controller state structure.
+ * @param endpoint Endpoint number.
+ * @param direction The direction of the endpoint, 0U - USB_OUT, 1U - USB_IN.
+ * @param buffer The memory address to save the received data, or the memory address to hold the data need to
+ * be sent.
+ * @param length The length of the data.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceLpc3511IpEndpointPrime(usb_device_lpc3511ip_state_struct_t *lpc3511IpState,
+ usb_device_lpc3511ip_endpoint_state_struct_t *epState,
+ uint8_t endpointIndex,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ uint8_t odd;
+
+ OSA_SR_ALLOC();
+
+ /* Enter critical */
+ OSA_ENTER_CRITICAL();
+
+ /* Flag the endpoint is busy. */
+ epState->stateUnion.stateBitField.transferring = 1U;
+
+#if ((defined(USB_DEVICE_IP3511HS_CONTROL_OUT_NYET_WORKAROUND)) && \
+ (USB_DEVICE_IP3511HS_CONTROL_OUT_NYET_WORKAROUND > 0U))
+ if (((endpointIndex >> 1U) == USB_ENDPOINT_CONTROL) && ((endpointIndex & 0x01U) == 0x00U) && (0U == length))
+ {
+ length = 65U;
+ }
+#endif
+
+ /* update the endpoint status */
+ epState->transferPrimedLength += length;
+#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE)
+ if ((endpointIndex >> 1U) != USB_ENDPOINT_CONTROL)
+ {
+ odd = (uint8_t)epState->stateUnion.stateBitField.producerOdd;
+ epState->stateUnion.stateBitField.doubleBufferBusy++;
+ epState->stateUnion.stateBitField.producerOdd ^= 1U;
+ }
+ else
+#endif
+ {
+ odd = 0U;
+ }
+ epState->epBufferStatusUnion[odd].epBufferStatusField.transactionLength = (uint16_t)length;
+
+ /* when receive the zero length packet, the controller will set 4 bytes buffer as 0x00 */
+ if (buffer == NULL)
+ {
+ buffer = lpc3511IpState->zeroTransactionData;
+ }
+
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(
+ lpc3511IpState, endpointIndex, odd,
+ (epState->stateUnion.stateBitField.epControlDefault << USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT) |
+ USB_LPC3511IP_ENDPOINT_ACTIVE_MASK,
+ length, (uint32_t)buffer);
+ if (0U != (epState->stateUnion.stateBitField.epControlDefault &
+ ((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT)))
+ {
+ epState->stateUnion.stateBitField.epControlDefault &=
+ (~((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT));
+ }
+ /* Exit critical */
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_Success;
+}
+
+#if 0
+/*!
+ * @brief Prime a next setup transfer.
+ *
+ * The function is used to prime a buffer in control out pipe to wait for receiving the host's setup packet.
+ *
+ * @param lpc3511IpState Pointer of the controller state structure.
+ *
+ */
+static void USB_DeviceLpc3511IpPrimeNextSetup(usb_device_lpc3511ip_state_struct_t *lpc3511IpState)
+{
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpc3511IpState, 0, 1, 0, 8, lpc3511IpState->setupData);
+}
+#endif
+
+/*!
+ * @brief reset ip3511.
+ *
+ * @param lpc3511IpState Pointer of the controller state structure.
+ *
+ */
+static void USB_DeviceLpc3511IpSetDefaultState(usb_device_lpc3511ip_state_struct_t *lpc3511IpState)
+{
+ uint32_t index = 0;
+ uint8_t usbAddress;
+ usb_status_t error = kStatus_USB_Error;
+ /* zero the command/status list buffer and disable all endpoints */
+ for (index = 0; index < 4U; ++index)
+ {
+ lpc3511IpState->epCommandStatusList[index] = 0x00000000U;
+ }
+ for (index = 4U; index < (uint32_t)USB_DEVICE_IP3511_ENDPOINTS_NUM * 4U; ++index)
+ {
+ lpc3511IpState->epCommandStatusList[index] = USB_LPC3511IP_ENDPOINT_DISABLE_MASK;
+ }
+
+ /* set address as 0 */
+ usbAddress = 0U;
+ error = USB_DeviceLpc3511IpControlPreSetDeviceAddress(lpc3511IpState, &usbAddress);
+ if (kStatus_USB_Success == error)
+ {
+ /*no action, just for misra4.7*/
+ }
+ lpc3511IpState->registerBase->EPLISTSTART = (uint32_t)lpc3511IpState->epCommandStatusList;
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+ if (0U != lpc3511IpState->controllerSpeed)
+ {
+ if ((USBHSD_DATABUFSTART_DA_BUF_MASK & (uint32_t)lpc3511IpState->setupData) !=
+ lpc3511IpState->registerBase->DATABUFSTART)
+ {
+ /* please use the dedicated ram */
+ }
+ }
+ else
+#endif
+ {
+ /* all data buffer is in the same 4M range with this setup data buffer */
+ lpc3511IpState->registerBase->DATABUFSTART = (uint32_t)lpc3511IpState->setupData;
+ }
+ /* reset registers */
+ lpc3511IpState->registerBase->EPINUSE = 0x0;
+ lpc3511IpState->registerBase->EPSKIP = 0x0;
+/* enable all double-buffer */
+#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE)
+ lpc3511IpState->registerBase->EPBUFCFG = USB_LPC3511IP_MAX_PHY_ENDPOINT_MASK;
+#else
+ lpc3511IpState->registerBase->EPBUFCFG = 0x00000000U;
+#endif
+ /* clear interrupts
+ * don't clear DEV_INT because the vbus valid interrupt may occurs with keeping usb connected and reseting device.
+ */
+ lpc3511IpState->registerBase->INTSTAT =
+ (USB_LPC3511IP_INTSTAT_FRAME_INT_MASK | USB_LPC3511IP_MAX_PHY_ENDPOINT_MASK);
+ /* enable interrupts */
+ lpc3511IpState->registerBase->INTEN = USB_LPC3511IP_INTSTAT_DEV_INT_MASK | USB_LPC3511IP_MAX_PHY_ENDPOINT_MASK;
+
+ /* Clear reset flag */
+ lpc3511IpState->isResetting = 0U;
+}
+
+/* Config and Enable endpoint */
+static usb_status_t USB_DeviceLpc3511IpEndpointInit(usb_device_lpc3511ip_state_struct_t *lpc3511IpState,
+ usb_device_endpoint_init_struct_t *epInit)
+{
+ uint8_t endpointIndex = USB_LPC3511IP_ENDPOINT_DES_INDEX(epInit->endpointAddress);
+ usb_device_lpc3511ip_endpoint_state_struct_t *epState =
+ USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, endpointIndex);
+ uint16_t maxPacketSize = epInit->maxPacketSize;
+#if (defined USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)
+ uint32_t allocateLength;
+ uint8_t *maxPacketBuffer;
+#endif
+
+ /* clear the endpoint status bits */
+ epState->stateUnion.state = 0x00000000U;
+ lpc3511IpState->registerBase->EPINUSE &= (~((uint32_t)(0x01UL << endpointIndex)));
+ /* Save the max packet size of the endpoint */
+ epState->stateUnion.stateBitField.maxPacketSize = maxPacketSize;
+ /* Set the ZLT field */
+ epState->stateUnion.stateBitField.zlt = epInit->zlt;
+ epState->stateUnion.stateBitField.endpointType = epInit->transferType;
+
+ /* get the endpoint default control value */
+ if (USB_ENDPOINT_ISOCHRONOUS == epInit->transferType)
+ {
+ epState->stateUnion.stateBitField.epControlDefault =
+ (USB_LPC3511IP_ENDPOINT_ENDPOINT_TYPE_MASK >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT);
+ }
+#if (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U))
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+ else if (
+#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))
+ (0U == (lpc3511IpState->hsInterruptIssue)) &&
+#endif
+ (0U != lpc3511IpState->controllerSpeed) && (USB_ENDPOINT_INTERRUPT == epInit->transferType))
+ {
+ epState->stateUnion.stateBitField.epControlDefault =
+ ((USB_LPC3511IP_ENDPOINT_ENDPOINT_TYPE_MASK | USB_LPC3511IP_ENDPOINT_RFTV_MASK) >>
+ USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT);
+ }
+#endif
+#endif
+ else
+ {
+ epState->stateUnion.stateBitField.epControlDefault = 0x00U;
+ }
+ /* set the command/status value */
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(
+ lpc3511IpState, endpointIndex, 0U,
+ (epState->stateUnion.stateBitField.epControlDefault << USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT), 0U, 0U);
+ if ((epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK) == USB_CONTROL_ENDPOINT)
+ {
+ if (0U == (epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK))
+ {
+ /* Prime setup packet when the endpoint is control out endpoint. */
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpc3511IpState, 0U, 1U, 0U, 0U, (uint32_t)lpc3511IpState->setupData);
+ }
+ }
+ else
+ {
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(
+ lpc3511IpState, endpointIndex, 1U,
+ (epState->stateUnion.stateBitField.epControlDefault << USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT), 0U,
+ 0U);
+ }
+ if ((endpointIndex >> 1) != USB_CONTROL_ENDPOINT)
+ {
+ /* toggle reset for the toggle */
+ epState->stateUnion.stateBitField.epControlDefault |=
+ ((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT);
+ }
+
+ epState->epPacketBuffer = NULL;
+ if ((endpointIndex >> 1U) == USB_CONTROL_ENDPOINT) /* control endpoint */
+ {
+ epState->epPacketBuffer = lpc3511IpState->controlData;
+ }
+#if (defined USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)
+ else
+ {
+ if (0U != USB_DeviceLpcIp3511MaxPacketNeedCopy(lpc3511IpState))
+ {
+#if ((defined(USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX)) && \
+ (USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX > 0U))
+ if ((USB_ENDPOINT_BULK == epInit->transferType) && ((endpointIndex & 0x01U) == 0x00U))
+ {
+ allocateLength = USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX;
+ }
+ else
+ {
+ allocateLength = USB_LPC3511IP_GET_MULTIPLE_OF_64(maxPacketSize);
+ }
+#else
+ allocateLength = USB_LPC3511IP_GET_MULTIPLE_OF_64(maxPacketSize);
+#endif
+#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE)
+ allocateLength *= 2U;
+#endif
+ maxPacketBuffer = USB_DeviceLpcIp3511MallocMaxPacketBuffer(allocateLength);
+ if (maxPacketBuffer == NULL)
+ {
+ return kStatus_USB_AllocFail;
+ }
+ epState->epPacketBuffer = maxPacketBuffer;
+ }
+ }
+#endif
+#if (defined(USB_DEVICE_CONFIG_ROOT2_TEST) && (USB_DEVICE_CONFIG_ROOT2_TEST > 0U))
+ epState->stateUnion.stateBitField.isOpened = 1U;
+#endif
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief De-initialize a specified endpoint.
+ *
+ * The function is used to de-initialize a specified endpoint.
+ * Current transfer of the endpoint will be canceled and the specified endpoint will be disabled.
+ *
+ * @param lpc3511IpState Pointer of the controller state structure.
+ * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceLpc3511IpEndpointDeinit(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, uint8_t ep)
+{
+ uint8_t endpointIndex = USB_LPC3511IP_ENDPOINT_DES_INDEX(ep);
+ usb_device_lpc3511ip_endpoint_state_struct_t *epState =
+ USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, endpointIndex);
+
+ /* Cancel the transfer of the endpoint */
+ (void)USB_DeviceLpc3511IpCancel(lpc3511IpState, ep);
+
+#if (defined USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)
+ if (0U != USB_DeviceLpcIp3511MaxPacketNeedCopy(lpc3511IpState))
+ {
+ if ((endpointIndex >> 1U) != USB_CONTROL_ENDPOINT) /* control endpoint */
+ {
+#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE)
+#if ((defined(USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX)) && \
+ (USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX > 0U))
+ if ((USB_ENDPOINT_BULK == epState->stateUnion.stateBitField.endpointType) &&
+ ((endpointIndex & 0x01U) == 0x00U))
+ {
+ USB_DeviceLpcIp3511ReleaseMaxPacketBuffer(
+ epState->epPacketBuffer,
+ USB_LPC3511IP_GET_MULTIPLE_OF_64(USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX * 2U));
+ }
+ else
+ {
+ USB_DeviceLpcIp3511ReleaseMaxPacketBuffer(
+ epState->epPacketBuffer,
+ USB_LPC3511IP_GET_MULTIPLE_OF_64(epState->stateUnion.stateBitField.maxPacketSize) * 2U);
+ }
+#else
+ USB_DeviceLpcIp3511ReleaseMaxPacketBuffer(
+ epState->epPacketBuffer,
+ USB_LPC3511IP_GET_MULTIPLE_OF_64(epState->stateUnion.stateBitField.maxPacketSize) * 2U);
+#endif
+#else
+ USB_DeviceLpcIp3511ReleaseMaxPacketBuffer(epState->epPacketBuffer,
+ epState->stateUnion.stateBitField.maxPacketSize);
+#endif
+ }
+ epState->epPacketBuffer = NULL;
+ }
+#endif
+
+ /* reset the double buffer */
+ lpc3511IpState->registerBase->EPINUSE &= ~((uint32_t)(0x01UL << endpointIndex));
+ /* Disable the endpoint */
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpc3511IpState, endpointIndex, 0U, USB_LPC3511IP_ENDPOINT_DISABLE_MASK, 0U, 0U);
+ /* Clear the max packet size */
+ epState->stateUnion.stateBitField.maxPacketSize = 0U;
+#if (defined(USB_DEVICE_CONFIG_ROOT2_TEST) && (USB_DEVICE_CONFIG_ROOT2_TEST > 0U))
+ /* Clear the endpoint open status */
+ epState->stateUnion.stateBitField.isOpened = 0U;
+#endif
+
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Stall a specified endpoint.
+ *
+ * The function is used to stall a specified endpoint.
+ * Current transfer of the endpoint will be canceled and the specified endpoint will be stalled.
+ *
+ * @param lpc3511IpState Pointer of the controller state structure.
+ * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceLpc3511IpEndpointStall(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, uint8_t ep)
+{
+ uint8_t endpointIndex = USB_LPC3511IP_ENDPOINT_DES_INDEX(ep);
+ usb_device_lpc3511ip_endpoint_state_struct_t *epState;
+ OSA_SR_ALLOC();
+
+ /* stall the endpoint */
+ if ((ep & USB_ENDPOINT_NUMBER_MASK) == USB_CONTROL_ENDPOINT)
+ {
+ epState = USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, 0);
+ epState->stateUnion.stateBitField.stalled = 1U;
+ epState = USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, 1);
+ epState->stateUnion.stateBitField.stalled = 1U;
+ /* Enter critical */
+ OSA_ENTER_CRITICAL();
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpc3511IpState, 0, 0U, USB_LPC3511IP_ENDPOINT_STALL_MASK, 0U, 0U);
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpc3511IpState, 1, 0U, USB_LPC3511IP_ENDPOINT_STALL_MASK, 0U, 0U);
+ /* Exit critical */
+ OSA_EXIT_CRITICAL();
+ /* cancel the transfer in the endpoint */
+ (void)USB_DeviceLpc3511IpCancel(lpc3511IpState, 0);
+ /* cancel the transfer in the endpoint */
+ (void)USB_DeviceLpc3511IpCancel(lpc3511IpState, 0x80);
+ }
+ else
+ {
+ epState = USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, endpointIndex);
+ /* Set endpoint stall flag. */
+ epState->stateUnion.stateBitField.stalled = 1U;
+ /* lpc3511IpState->registerBase->EPINUSE &= (~(0x01u << endpointIndex)); */
+ /* stall the endpoint */
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpc3511IpState, endpointIndex, 0U, USB_LPC3511IP_ENDPOINT_STALL_MASK, 0U,
+ 0U);
+ if ((ep & USB_ENDPOINT_NUMBER_MASK) != USB_CONTROL_ENDPOINT)
+ {
+ /* toggle reset for the toggle */
+ epState->stateUnion.stateBitField.epControlDefault |=
+ ((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT);
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpc3511IpState, endpointIndex, 1U, USB_LPC3511IP_ENDPOINT_STALL_MASK,
+ 0U, 0U);
+ }
+#if (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)) && \
+ (!(defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)))
+#else
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))
+ if (0U != lpc3511IpState->hsInterruptIssue)
+ {
+#endif
+ if ((0U != lpc3511IpState->controllerSpeed) &&
+ (USB_ENDPOINT_INTERRUPT == epState->stateUnion.stateBitField.endpointType))
+ {
+ lpc3511IpState->registerBase->DEVCMDSTAT |=
+ (USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AO_MASK | USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AI_MASK);
+ epState->stateUnion.stateBitField.epControlDefault &=
+ (~((USB_LPC3511IP_ENDPOINT_ENDPOINT_TYPE_MASK | USB_LPC3511IP_ENDPOINT_RFTV_MASK) >>
+ USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT));
+ }
+#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))
+ }
+#endif
+#endif
+#endif
+
+ /* cancel the transfer in the endpoint */
+ (void)USB_DeviceLpc3511IpCancel(lpc3511IpState, ep);
+ }
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Un-stall a specified endpoint.
+ *
+ * The function is used to un-stall a specified endpoint.
+ * Current transfer of the endpoint will be canceled and the specified endpoint will be un-stalled.
+ *
+ * @param lpc3511IpState Pointer of the controller state structure.
+ * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceLpc3511IpEndpointUnstall(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, uint8_t ep)
+{
+ uint8_t endpointIndex = USB_LPC3511IP_ENDPOINT_DES_INDEX(ep);
+ usb_device_lpc3511ip_endpoint_state_struct_t *epState =
+ USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, endpointIndex);
+
+ /* Clear the endpoint stall state, the hardware resets the endpoint
+ * toggle to one for both directions when a setup token is received */
+ epState->stateUnion.stateBitField.stalled = 0U;
+
+ /* unstall the endpoint for double buffers */
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT_AND(lpc3511IpState, endpointIndex, 0, (~USB_LPC3511IP_ENDPOINT_STALL_MASK));
+ if ((ep & USB_ENDPOINT_NUMBER_MASK) != USB_CONTROL_ENDPOINT)
+ {
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT_AND(lpc3511IpState, endpointIndex, 1, (~USB_LPC3511IP_ENDPOINT_STALL_MASK));
+
+ /* toggle reset for the toggle */
+ epState->stateUnion.stateBitField.epControlDefault |=
+ ((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT);
+#if (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)) && \
+ (!(defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)))
+#else
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))
+ if (0U != lpc3511IpState->hsInterruptIssue)
+ {
+#endif
+ if ((0U != lpc3511IpState->controllerSpeed) &&
+ (USB_ENDPOINT_INTERRUPT == epState->stateUnion.stateBitField.endpointType))
+ {
+ epState->stateUnion.stateBitField.epControlDefault &=
+ (~((USB_LPC3511IP_ENDPOINT_ENDPOINT_TYPE_MASK | USB_LPC3511IP_ENDPOINT_RFTV_MASK) >>
+ USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT));
+ }
+#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))
+ }
+#endif
+#endif
+#endif
+ }
+
+ if (0U != epState->stateUnion.stateBitField.stallPrimed)
+ {
+ epState->stateUnion.stateBitField.stallPrimed = 0u;
+ (void)USB_DeviceLpc3511IpTransaction(lpc3511IpState, epState, endpointIndex);
+ }
+ /* cancel the transfer in the endpoint */
+ (void)USB_DeviceLpc3511IpCancel(lpc3511IpState, ep);
+ return kStatus_USB_Success;
+}
+
+#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+/*!
+ * @brief Un-stall a specified endpoint.
+ *
+ * The function is used to un-stall a specified endpoint.
+ * Current transfer of the endpoint will be canceled and the specified endpoint will be un-stalled.
+ *
+ * @param lpc3511IpState Pointer of the controller state structure.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceLpc3511IpInterruptSuspend(usb_device_lpc3511ip_state_struct_t *lpc3511IpState)
+{
+ usb_device_callback_message_struct_t message;
+
+ message.buffer = (uint8_t *)NULL;
+ message.code = (uint8_t)kUSB_DeviceNotifySuspend;
+ message.length = 0U;
+ message.isSetup = 0U;
+
+ /* Notify up layer the USB suspend signal detected. */
+ (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message);
+
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Un-stall a specified endpoint.
+ *
+ * The function is used to un-stall a specified endpoint.
+ * Current transfer of the endpoint will be canceled and the specified endpoint will be un-stalled.
+ *
+ * @param lpc3511IpState Pointer of the controller state structure.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceLpc3511IpInterruptResume(usb_device_lpc3511ip_state_struct_t *lpc3511IpState)
+{
+ usb_device_callback_message_struct_t message;
+
+ message.buffer = (uint8_t *)NULL;
+ message.code = (uint8_t)kUSB_DeviceNotifyResume;
+ message.length = 0U;
+ message.isSetup = 0U;
+
+ /* Notify up layer the USB suspend signal detected. */
+ (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message);
+
+ return kStatus_USB_Success;
+}
+#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U))
+/*!
+ * @brief Un-stall a specified endpoint.
+ *
+ * The function is used to un-stall a specified endpoint.
+ * Current transfer of the endpoint will be canceled and the specified endpoint will be un-stalled.
+ *
+ * @param lpc3511IpState Pointer of the controller state structure.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceLpc3511IpInterruptLPMSleep(usb_device_lpc3511ip_state_struct_t *lpc3511IpState)
+{
+ usb_device_callback_message_struct_t message;
+
+ message.buffer = &lpc3511IpState->lpmRemoteWakeUp;
+ message.code = (uint8_t)kUSB_DeviceNotifyLPMSleep;
+ message.length = 0U;
+ message.isSetup = 0U;
+
+ lpc3511IpState->lpmRemoteWakeUp =
+ (uint8_t)((lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_MASK) >>
+ USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_SHIFT);
+
+ /* Notify up layer the USB suspend signal detected. */
+ (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message);
+
+ return kStatus_USB_Success;
+}
+
+#endif
+#endif
+
+/* need copy the data before the trasaction buffer is used again */
+static void USB_DeviceLpc3511IpDoPreviousTransactionMemcpy(usb_device_lpc3511ip_state_struct_t *lpc3511IpState,
+ usb_device_lpc3511ip_endpoint_state_struct_t *epState,
+ uint32_t length,
+ uint8_t endpointIndex,
+ uint8_t odd)
+{
+ uint8_t *destBuffer;
+ uint8_t *sourceBuffer;
+
+#if ((defined(USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY > 0U))
+ /*control out doesn't support buffer toggle*/
+ if (0U == endpointIndex)
+ {
+ odd = 0u;
+ }
+#if USB_DEVICE_IP3511_ALL_IP_SUPPORT_RESERVED_BUFFER
+ if ((0U != epState->epBufferStatusUnion[odd].epBufferStatusField.epPacketCopyed) && (length > 0U) &&
+ ((endpointIndex & 0x01U) == 0U))
+#else
+ if ((0U != USB_DeviceLpcIp3511MaxPacketNeedCopy(lpc3511IpState)) &&
+ (0U != epState->epBufferStatusUnion[odd].epBufferStatusField.epPacketCopyed) && (length > 0U) &&
+ ((endpointIndex & 0x01U) == 0U))
+#endif
+#else
+ /* control data buffer align is used */
+ if (((endpointIndex >> 1U) == USB_CONTROL_ENDPOINT) &&
+ (epState->epBufferStatusUnion[odd].epBufferStatusField.epPacketCopyed) && (length > 0U) &&
+ ((endpointIndex & 0x01u) == 0U))
+#endif
+ {
+#if ((defined(USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER)) && (USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER > 0U))
+ destBuffer = &(epState->transferBuffer[epState->transferDone - length]);
+#else
+ destBuffer = &(epState->transferBuffer[epState->transferDone]);
+#endif
+#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE)
+#if (defined USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX) && \
+ (USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX)
+ if ((USB_ENDPOINT_BULK == epState->stateUnion.stateBitField.endpointType) && ((endpointIndex & 0x01U) == 0x00U))
+ {
+ sourceBuffer = epState->epPacketBuffer + odd * USB_LPC3511IP_GET_MULTIPLE_OF_64(
+ USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX);
+ }
+ else
+ {
+ sourceBuffer = epState->epPacketBuffer +
+ odd * USB_LPC3511IP_GET_MULTIPLE_OF_64(epState->stateUnion.stateBitField.maxPacketSize);
+ }
+#else
+ sourceBuffer = epState->epPacketBuffer +
+ odd * USB_LPC3511IP_GET_MULTIPLE_OF_64(epState->stateUnion.stateBitField.maxPacketSize);
+#endif
+#else
+ sourceBuffer = epState->epPacketBuffer;
+#endif
+ (void)memcpy(destBuffer, sourceBuffer, length);
+ }
+}
+
+static uint32_t USB_DeviceLpc3511IpTokenUpdate(usb_device_lpc3511ip_state_struct_t *lpc3511IpState,
+ usb_device_lpc3511ip_endpoint_state_struct_t *epState,
+ uint8_t endpointIndex,
+ uint8_t changedOdd)
+{
+ uint32_t length;
+ uint8_t odd;
+
+#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE)
+ if (0U != changedOdd)
+ {
+ odd = (uint8_t)epState->stateUnion.stateBitField.consumerOdd;
+ epState->stateUnion.stateBitField.consumerOdd ^= 1U;
+ epState->stateUnion.stateBitField.doubleBufferBusy--;
+ }
+ else
+#endif
+ {
+ odd = 0U;
+ }
+
+/* for OUT packet, compute the actual packet size. */
+#if ((defined(FSL_FEATURE_USB_VERSION) && (FSL_FEATURE_USB_VERSION >= 200U)) || \
+ (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)))
+#else
+ if ((endpointIndex & 0x01U) == 0x00u) /* OUT */
+#endif
+ {
+ /* get the transaction length */
+ length = *(lpc3511IpState->epCommandStatusList + endpointIndex * 2U + odd);
+
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+ if (0U != lpc3511IpState->controllerSpeed)
+ {
+ length =
+ (length & USB_LPC3511IPHS_ENDPOINT_BUFFER_NBYTES_MASK) >> USB_LPC3511IPHS_ENDPOINT_BUFFER_NBYTES_SHIFT;
+ }
+ else
+#endif
+ {
+ length =
+ (length & USB_LPC3511IPFS_ENDPOINT_BUFFER_NBYTES_MASK) >> USB_LPC3511IPFS_ENDPOINT_BUFFER_NBYTES_SHIFT;
+ }
+ length = epState->epBufferStatusUnion[odd].epBufferStatusField.transactionLength - length;
+ }
+#if ((defined(FSL_FEATURE_USB_VERSION) && (FSL_FEATURE_USB_VERSION >= 200U)) || \
+ (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)))
+#else
+ else /* for IN packet, if there is no error, the packet lenght is the primed length. */
+ {
+ /* don't judge the actual packet size */
+ length = epState->epBufferStatusUnion[odd].epBufferStatusField.transactionLength;
+ }
+#endif
+
+#if !((defined(USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER)) && (USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER > 0U))
+ USB_DeviceLpc3511IpDoPreviousTransactionMemcpy(lpc3511IpState, epState, length, endpointIndex, odd);
+#endif
+ /* update the transferred length */
+ epState->transferDone += length;
+
+ return length;
+}
+
+static void USB_DeviceLpc3511IpInterruptToken(usb_device_lpc3511ip_state_struct_t *lpc3511IpState,
+ uint8_t endpointIndex,
+ uint8_t isSetup,
+ uint32_t errorStatus)
+{
+ usb_device_callback_message_struct_t message;
+ uint32_t length;
+ uint32_t remainLength;
+ usb_setup_struct_t *setupPacket;
+ void *temp;
+ usb_device_lpc3511ip_endpoint_state_struct_t *epState =
+ USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, endpointIndex);
+#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE)
+ uint32_t len = 0;
+#endif
+
+#if (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)) && \
+ (!(defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)))
+#else
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))
+ if (0U != lpc3511IpState->hsInterruptIssue)
+ {
+#endif
+ if ((0U != (epState->stateUnion.stateBitField.epControlDefault &
+ ((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT))) &&
+ (USB_ENDPOINT_INTERRUPT == epState->stateUnion.stateBitField.endpointType) &&
+ (0U != lpc3511IpState->controllerSpeed) &&
+ (0U != (lpc3511IpState->epCommandStatusList[epState->stateUnion.stateBitField.consumerOdd +
+ (((uint32_t)endpointIndex) * 2U)] &
+ USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK)))
+ {
+ if (0U == (lpc3511IpState->registerBase->EPTOGGLE & ((uint32_t)(0x01UL << endpointIndex))))
+ {
+ uint32_t index;
+ length = 0U;
+ for (index = 0U; index < ((uint32_t)USB_DEVICE_IP3511_ENDPOINTS_NUM) * 4U; ++index)
+ {
+ if ((0U !=
+ (lpc3511IpState->epCommandStatusList[index] & USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK)) &&
+ (USB_ENDPOINT_INTERRUPT ==
+ lpc3511IpState->endpointState[index / 2U].stateUnion.stateBitField.endpointType))
+ {
+ length++;
+ }
+ }
+
+ if (length <= 1U)
+ {
+ lpc3511IpState->registerBase->DEVCMDSTAT &=
+ ~(USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AO_MASK | USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AI_MASK);
+ }
+ epState->stateUnion.stateBitField.epControlDefault &=
+ (~((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT));
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+ /* high-speed */
+ epState->stateUnion.stateBitField.epControlDefault |=
+ ((USB_LPC3511IP_ENDPOINT_RFTV_MASK | USB_LPC3511IP_ENDPOINT_ENDPOINT_TYPE_MASK) >>
+ USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT);
+ (void)USB_DeviceLpc3511IpTransaction(lpc3511IpState, epState, endpointIndex);
+#endif
+ }
+ return;
+ }
+#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))
+ }
+#endif
+#endif
+#endif
+
+ if ((0U == isSetup) && (0U == epState->stateUnion.stateBitField.transferring))
+ {
+ return;
+ }
+ if (0U != isSetup)
+ {
+ message.length = 8U;
+ message.buffer = (lpc3511IpState->setupData);
+ /* clear the primed control transactions */
+ if (0U != (epState->stateUnion.stateBitField.transferring))
+ {
+ epState->stateUnion.stateBitField.transferring = 0U;
+ if (0U != (lpc3511IpState->epCommandStatusList[0] & USB_LPC3511IP_ENDPOINT_ACTIVE_MASK))
+ {
+ (void)USB_DeviceLpc3511IpCancel(lpc3511IpState, USB_CONTROL_ENDPOINT);
+ }
+ }
+ if (0U != (lpc3511IpState->endpointState[1].stateUnion.stateBitField.transferring))
+ {
+ lpc3511IpState->endpointState[1].stateUnion.stateBitField.transferring = 0U;
+ if (0U != (lpc3511IpState->epCommandStatusList[2] & USB_LPC3511IP_ENDPOINT_ACTIVE_MASK))
+ {
+ (void)USB_DeviceLpc3511IpCancel(lpc3511IpState, (0x80u | USB_CONTROL_ENDPOINT));
+ }
+ }
+
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT_AND(
+ lpc3511IpState, 0, 0, (~(USB_LPC3511IP_ENDPOINT_STALL_MASK | USB_LPC3511IP_ENDPOINT_ACTIVE_MASK)));
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT_AND(
+ lpc3511IpState, 1, 0, (~(USB_LPC3511IP_ENDPOINT_STALL_MASK | USB_LPC3511IP_ENDPOINT_ACTIVE_MASK)));
+
+ lpc3511IpState->registerBase->INTSTAT = 0x03u; /* clear interrupt */
+ /* W1 to clear the setup flag */
+ lpc3511IpState->registerBase->DEVCMDSTAT |= USB_LPC3511IP_DEVCMDSTAT_SETUP_MASK;
+ }
+ else
+ {
+ length = 0U;
+#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE)
+ if (0U != (lpc3511IpState->epCommandStatusList[epState->stateUnion.stateBitField.consumerOdd +
+ (((uint32_t)endpointIndex) * 2U)] &
+ USB_LPC3511IP_ENDPOINT_ACTIVE_MASK))
+ {
+ return;
+ }
+#else
+ if (0U != (lpc3511IpState->epCommandStatusList[endpointIndex * 2U] & USB_LPC3511IP_ENDPOINT_ACTIVE_MASK))
+ {
+ return;
+ }
+#endif
+
+#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE)
+ if ((endpointIndex >> 1U) != USB_CONTROL_ENDPOINT)
+ {
+ len = USB_DeviceLpc3511IpTokenUpdate(lpc3511IpState, epState, endpointIndex, 1U);
+ length += len;
+
+ if ((epState->stateUnion.stateBitField.doubleBufferBusy > 0U) &&
+ (0U == (lpc3511IpState->epCommandStatusList[epState->stateUnion.stateBitField.consumerOdd +
+ (((uint32_t)endpointIndex) * 2U)] &
+ USB_LPC3511IP_ENDPOINT_ACTIVE_MASK)))
+ {
+#if ((defined(USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER)) && (USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER > 0U))
+ USB_DeviceLpc3511IpDoPreviousTransactionMemcpy(
+ lpc3511IpState, epState, len, endpointIndex,
+ (uint8_t)(epState->stateUnion.stateBitField.consumerOdd ^ 1U));
+#endif
+ len = USB_DeviceLpc3511IpTokenUpdate(lpc3511IpState, epState, endpointIndex, 1U);
+ length += len;
+ }
+ }
+ else
+#endif
+ {
+ length = USB_DeviceLpc3511IpTokenUpdate(lpc3511IpState, epState, endpointIndex, 0U);
+ len = length;
+ }
+
+ /* update remaining length */
+ remainLength = epState->transferLength - epState->transferDone;
+
+ /* Whether the transfer is completed or not.
+ * The transfer is completed when one of the following conditions meet:
+ * 1. The remaining length is zero.
+ * 2. The length of current tansaction is not the multiple of max packet size.
+ */
+ if ((length > 0U) && (0U == (length % epState->stateUnion.stateBitField.maxPacketSize)) && (remainLength > 0U))
+ {
+#if ((defined(USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER)) && (USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER > 0U))
+ if ((endpointIndex >> 1U) == USB_CONTROL_ENDPOINT)
+ {
+ /* do memcpy firstly */
+ USB_DeviceLpc3511IpDoPreviousTransactionMemcpy(lpc3511IpState, epState, len, endpointIndex, 0U);
+ (void)USB_DeviceLpc3511IpTransaction(lpc3511IpState, epState, endpointIndex);
+ }
+ else
+ {
+ (void)USB_DeviceLpc3511IpTransaction(lpc3511IpState, epState, endpointIndex);
+
+ USB_DeviceLpc3511IpDoPreviousTransactionMemcpy(
+ lpc3511IpState, epState, len, endpointIndex,
+ (uint8_t)(epState->stateUnion.stateBitField.consumerOdd ^ 1U));
+ }
+#else
+ (void)USB_DeviceLpc3511IpTransaction(lpc3511IpState, epState, endpointIndex);
+#endif
+ return;
+ }
+ else
+ {
+ epState->stateUnion.stateBitField.transferring = 0U;
+ message.length = epState->transferDone;
+ message.buffer = epState->transferBuffer;
+
+ /* process ZLT
+ * 1. IN endpoint;
+ * 2. transfer length is the multiple of max packet size.
+ */
+ if ((0U != (endpointIndex & 0x01U)) && (0U != length) &&
+ (0U == (length % epState->stateUnion.stateBitField.maxPacketSize)))
+ {
+ if ((endpointIndex >> 1U) == USB_CONTROL_ENDPOINT)
+ {
+ temp = (void *)(&(lpc3511IpState->setupData[0]));
+ setupPacket = (usb_setup_struct_t *)temp;
+ /*
+ * Send ZLT transaction if setup transfer and the required length is longer than actual length
+ */
+ if (USB_SHORT_FROM_LITTLE_ENDIAN(setupPacket->wLength) > epState->transferLength)
+ {
+ (void)USB_DeviceLpc3511IpEndpointPrime(lpc3511IpState, epState, 1U, NULL, 0U);
+ return;
+ }
+ }
+ else if ((0U != epState->stateUnion.stateBitField.zlt))
+ {
+ (void)USB_DeviceLpc3511IpEndpointPrime(lpc3511IpState, epState, endpointIndex, NULL, 0U);
+ return;
+ }
+ else
+ {
+ /*no action*/
+ }
+ }
+ }
+ }
+
+ message.isSetup = isSetup;
+ message.code = ((uint8_t)(endpointIndex >> 1) | (uint8_t)(((endpointIndex & 0x01U) << 0x07U)));
+
+#if ((defined(USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER)) && (USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER > 0U))
+ USB_DeviceLpc3511IpDoPreviousTransactionMemcpy(lpc3511IpState, epState, len, endpointIndex,
+ (uint8_t)(epState->stateUnion.stateBitField.consumerOdd ^ 1U));
+#endif
+ /* Notify the up layer the controller status changed. */
+ (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message);
+}
+
+/*!
+ * @brief Handle the USB bus reset interrupt.
+ *
+ * The function is used to handle the USB bus reset interrupt.
+ *
+ * @param lpc3511IpState Pointer of the controller state structure.
+ *
+ */
+static void USB_DeviceLpc3511IpInterruptReset(usb_device_lpc3511ip_state_struct_t *lpc3511IpState)
+{
+ usb_device_callback_message_struct_t message;
+
+ /* Set reset flag */
+ lpc3511IpState->isResetting = 1U;
+
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+ if (0U != lpc3511IpState->controllerSpeed)
+ {
+ if (((lpc3511IpState->registerBase->DEVCMDSTAT & USBHSD_DEVCMDSTAT_Speed_MASK) >>
+ USBHSD_DEVCMDSTAT_Speed_SHIFT) == 0x02U)
+ {
+ lpc3511IpState->deviceSpeed = USB_SPEED_HIGH;
+ }
+ else if (((lpc3511IpState->registerBase->DEVCMDSTAT & USBHSD_DEVCMDSTAT_Speed_MASK) >>
+ USBHSD_DEVCMDSTAT_Speed_SHIFT) == 0x01U)
+ {
+ lpc3511IpState->deviceSpeed = USB_SPEED_FULL;
+ }
+ else
+ {
+ /*no action*/
+ }
+ }
+ else
+#endif
+ {
+ lpc3511IpState->deviceSpeed = USB_SPEED_FULL;
+ }
+
+ message.buffer = (uint8_t *)NULL;
+ message.code = (uint8_t)kUSB_DeviceNotifyBusReset;
+ message.length = 0U;
+ message.isSetup = 0U;
+ /* Notify up layer the USB bus reset signal detected. */
+ (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message);
+}
+
+#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE))
+/*!
+ * @brief Handle detach interrupt.
+ *
+ * The function is used to handle the detach interrupt.
+ *
+ * @param lpc3511IpState Pointer of the controller state structure.
+ *
+ */
+static void USB_DeviceLpc3511IpInterruptDetach(usb_device_lpc3511ip_state_struct_t *lpc3511IpState)
+{
+ usb_device_callback_message_struct_t message;
+
+ message.buffer = (uint8_t *)NULL;
+ message.code = (uint8_t)kUSB_DeviceNotifyDetach;
+ message.length = 0U;
+ message.isSetup = 0U;
+
+ /* Notify up layer the USB VBUS falling signal detected. */
+ (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message);
+}
+
+/*!
+ * @brief Handle Attach interrupt.
+ *
+ * The function is used to handle the attach interrupt.
+ *
+ * @param lpc3511IpState Pointer of the controller state structure.
+ *
+ */
+static void USB_DeviceLpc3511IpInterruptAttach(usb_device_lpc3511ip_state_struct_t *lpc3511IpState)
+{
+ usb_device_callback_message_struct_t message;
+
+ message.buffer = (uint8_t *)NULL;
+ message.code = (uint8_t)kUSB_DeviceNotifyAttach;
+ message.length = 0U;
+ message.isSetup = 0U;
+
+ /* Notify up layer the USB VBUS rising signal detected. */
+ (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message);
+}
+#endif
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))
+/* The device dcd callback */
+static usb_hsdcd_status_t USB_DeviceLpcIp3511IsrHSDCDCallback(void *handle, uint32_t event, void *param)
+{
+ usb_hsdcd_status_t error = kStatus_hsdcd_Success;
+ usb_device_callback_message_struct_t message;
+ usb_device_lpc3511ip_state_struct_t *lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)handle;
+
+ if (lpc3511IpState == NULL)
+ {
+ return kStatus_hsdcd_Error;
+ }
+
+ /*messsgae buffer contain event information*/
+ message.buffer = (uint8_t *)param;
+ message.length = 0U;
+ message.isSetup = 0U;
+ message.code = (uint8_t)kUSB_DeviceNotifyDcdDetectFinished;
+ (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message);
+ return error;
+}
+
+void USB_DeviceLpcIp3511IsrDCDFunction(void *deviceHandle)
+{
+ usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle;
+ usb_device_lpc3511ip_state_struct_t *lpc3511IpState;
+ if (NULL == deviceHandle)
+ {
+ return;
+ }
+ lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)(handle->controllerHandle);
+ USB_HSDcdIsrFunction(lpc3511IpState->dcdHandle);
+}
+#endif
+usb_status_t USB_DeviceLpc3511IpInit(uint8_t controllerId,
+ usb_device_handle handle,
+ usb_device_controller_handle *controllerHandle)
+{
+ usb_device_lpc3511ip_state_struct_t *lpc3511IpState = NULL;
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U))
+ uint32_t ip3511FsBases[] = USB_BASE_ADDRS;
+#endif
+ uint32_t *endpointListArray[] = LPC_CONTROLLER_ENDPOINT_LIST_ARRAY;
+
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))
+ uint32_t hsdcd_base[] = USBHSDCD_BASE_ADDRS;
+ USBHSDCD_Type *base;
+ usb_hsdcd_config_struct_t dcdParamConfig;
+ usb_hsdcd_status_t dcdError = kStatus_hsdcd_Success;
+#endif
+
+ uint32_t ip3511HsBases[] = USBHSD_BASE_ADDRS;
+ if ((controllerId >= (uint8_t)kUSB_ControllerLpcIp3511Hs0) &&
+ (controllerId <= (uint8_t)kUSB_ControllerLpcIp3511Hs1))
+ {
+ if (((uint32_t)controllerId - (uint32_t)kUSB_ControllerLpcIp3511Hs0) >=
+ (sizeof(ip3511HsBases) / sizeof(uint32_t)))
+ {
+ return kStatus_USB_ControllerNotFound;
+ }
+ lpc3511IpState = &s_UsbDeviceLpc3511IpState[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0 +
+ USB_DEVICE_CONFIG_LPCIP3511FS];
+#if (!(defined(USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)))
+ lpc3511IpState->controlData =
+ (uint8_t *)&s_SetupAndEpReservedData[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0 +
+ USB_DEVICE_CONFIG_LPCIP3511FS][CONTROL_TRANSFER_DATA_OFFSET];
+ lpc3511IpState->setupData =
+ (uint8_t *)&s_SetupAndEpReservedData[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0 +
+ USB_DEVICE_CONFIG_LPCIP3511FS][SETUP_TRANSFER_DATA_OFFSET];
+ lpc3511IpState->zeroTransactionData =
+ (uint8_t *)&s_SetupAndEpReservedData[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0 +
+ USB_DEVICE_CONFIG_LPCIP3511FS][ZERO_TRANSFER_DATA_OFFSET];
+#endif
+ /* set the endpoint list */
+ lpc3511IpState->epCommandStatusList =
+ endpointListArray[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0 + USB_DEVICE_CONFIG_LPCIP3511FS];
+ /* get the ip base address */
+ lpc3511IpState->registerBase =
+ (USB_LPC3511IP_Type *)ip3511HsBases[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0];
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))
+ base = (USBHSDCD_Type *)hsdcd_base[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0];
+ dcdParamConfig.dcdCallback = USB_DeviceLpcIp3511IsrHSDCDCallback;
+ dcdParamConfig.dcdCallbackParam = (void *)lpc3511IpState;
+ dcdError = USB_HSDCD_Init(base, &dcdParamConfig, &lpc3511IpState->dcdHandle);
+ if (kStatus_hsdcd_Success != dcdError)
+ {
+ return kStatus_USB_Error;
+ }
+#endif
+ }
+ else
+#endif
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U))
+ {
+ /* get the controller instance */
+ if ((controllerId < (uint8_t)kUSB_ControllerLpcIp3511Fs0) ||
+ ((controllerId - (uint8_t)kUSB_ControllerLpcIp3511Fs0) >= (uint8_t)USB_DEVICE_CONFIG_LPCIP3511FS) ||
+ (((uint32_t)controllerId - (uint32_t)kUSB_ControllerLpcIp3511Fs0) >=
+ (sizeof(ip3511FsBases) / sizeof(uint32_t))))
+ {
+ return kStatus_USB_ControllerNotFound;
+ }
+ lpc3511IpState = &s_UsbDeviceLpc3511IpState[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Fs0];
+#if (!(defined(USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)))
+ lpc3511IpState->controlData =
+ (uint8_t *)&s_SetupAndEpReservedData[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Fs0]
+ [CONTROL_TRANSFER_DATA_OFFSET];
+ lpc3511IpState->setupData =
+ (uint8_t *)&s_SetupAndEpReservedData[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Fs0]
+ [SETUP_TRANSFER_DATA_OFFSET];
+ lpc3511IpState->zeroTransactionData =
+ (uint8_t *)&s_SetupAndEpReservedData[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Fs0]
+ [ZERO_TRANSFER_DATA_OFFSET];
+#endif
+ /* set the endpoint list */
+ lpc3511IpState->epCommandStatusList = endpointListArray[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Fs0];
+ /* get the ip base address */
+ lpc3511IpState->registerBase =
+ (USB_LPC3511IP_Type *)ip3511FsBases[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Fs0];
+ }
+#else
+ {
+ return kStatus_USB_ControllerNotFound;
+ }
+#endif
+
+ lpc3511IpState->controllerId = controllerId;
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+ if ((lpc3511IpState->controllerId >= (uint8_t)kUSB_ControllerLpcIp3511Hs0) &&
+ (lpc3511IpState->controllerId <= (uint8_t)kUSB_ControllerLpcIp3511Hs1))
+ {
+ lpc3511IpState->controllerSpeed = 1U;
+#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))
+ lpc3511IpState->hsInterruptIssue = ((Chip_GetVersion() == FSL_ROM_VERSION_1B) ? 0U : 1U);
+#endif
+ }
+ else
+ {
+ lpc3511IpState->controllerSpeed = 0U;
+ }
+#endif
+
+#if defined(USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)
+ lpc3511IpState->controlData = USB_DeviceLpcIp3511MallocMaxPacketBuffer(CONTROL_TRANSFER_DATA_SIZE);
+ lpc3511IpState->setupData = USB_DeviceLpcIp3511MallocMaxPacketBuffer(SETUP_TRANSFER_DATA_SIZE);
+ lpc3511IpState->zeroTransactionData = USB_DeviceLpcIp3511MallocMaxPacketBuffer(ZERO_TRANSFER_DATA_SIZE);
+#endif
+
+ /* disable the controller */
+ lpc3511IpState->registerBase->DEVCMDSTAT &=
+ (~(USB_LPC3511IP_DEVCMDSTAT_DCON_MASK | USB_LPC3511IP_DEVCMDSTAT_DEV_EN_MASK |
+ USB_LPC3511IP_DEVCMDSTAT_LPM_SUP_MASK));
+ /* reset and enalbe the controller */
+ USB_DeviceLpc3511IpSetDefaultState(lpc3511IpState);
+ /* enable USB */
+ lpc3511IpState->registerBase->DEVCMDSTAT |= (USB_LPC3511IP_DEVCMDSTAT_DEV_EN_MASK
+#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+#else
+ | USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK
+#endif
+ );
+#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U))
+ lpc3511IpState->registerBase->DEVCMDSTAT |= USB_LPC3511IP_DEVCMDSTAT_LPM_SUP_MASK;
+ lpc3511IpState->registerBase->LPM |= USB_LPC3511IP_USB_LPM_HIRD_SW(4);
+ lpc3511IpState->registerBase->DEVCMDSTAT &= ~(USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK);
+#endif
+ lpc3511IpState->deviceHandle = handle;
+ *controllerHandle = lpc3511IpState;
+
+ return kStatus_USB_Success;
+}
+
+usb_status_t USB_DeviceLpc3511IpDeinit(usb_device_controller_handle controllerHandle)
+{
+ usb_device_lpc3511ip_state_struct_t *lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)controllerHandle;
+ uint32_t usbAddress;
+ usb_status_t status = kStatus_USB_Success;
+ if (controllerHandle == NULL)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+ /* Clear all interrupt flags. */
+ lpc3511IpState->registerBase->INTSTAT = (USB_LPC3511IP_INTSTAT_DEV_INT_MASK | USB_LPC3511IP_INTSTAT_FRAME_INT_MASK |
+ USB_LPC3511IP_MAX_PHY_ENDPOINT_MASK);
+ /* Disable all interrupts. */
+ lpc3511IpState->registerBase->INTEN = 0U;
+ /* Clear device address. */
+ usbAddress = 0U;
+ status = USB_DeviceLpc3511IpControlPreSetDeviceAddress(controllerHandle, &usbAddress);
+ if (kStatus_USB_Success == status)
+ {
+ /*no action, just for misra4.7*/
+ }
+#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U))
+ lpc3511IpState->registerBase->DEVCMDSTAT &= ~USB_LPC3511IP_DEVCMDSTAT_LPM_SUP_MASK;
+#endif
+ /* disable the controller */
+ lpc3511IpState->registerBase->DEVCMDSTAT &=
+ (~(USB_LPC3511IP_DEVCMDSTAT_DCON_MASK | USB_LPC3511IP_DEVCMDSTAT_DEV_EN_MASK |
+ USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK));
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))
+ (void)USB_HSDCD_Deinit(lpc3511IpState->dcdHandle);
+#endif
+
+#if defined(USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)
+ USB_DeviceLpcIp3511ReleaseMaxPacketBuffer(lpc3511IpState->controlData, CONTROL_TRANSFER_DATA_SIZE);
+ USB_DeviceLpcIp3511ReleaseMaxPacketBuffer(lpc3511IpState->setupData, SETUP_TRANSFER_DATA_SIZE);
+ USB_DeviceLpcIp3511ReleaseMaxPacketBuffer(lpc3511IpState->zeroTransactionData, ZERO_TRANSFER_DATA_SIZE);
+#endif
+
+ return status;
+}
+
+static usb_status_t USB_DeviceLpc3511IpGetActualBufferAndPrime(usb_device_lpc3511ip_state_struct_t *lpc3511IpState,
+ usb_device_lpc3511ip_endpoint_state_struct_t *epState,
+ uint8_t endpointIndex,
+ uint8_t changedOdd)
+{
+ uint8_t *destBuffer;
+ uint8_t *actualBuffer;
+ uint32_t length;
+ uint8_t odd;
+ uint8_t index;
+
+#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE)
+ if (0U != changedOdd)
+ {
+ odd = (uint8_t)epState->stateUnion.stateBitField.producerOdd;
+ }
+ else
+#endif
+ {
+ odd = 0;
+ }
+ actualBuffer = epState->transferBuffer + epState->transferPrimedLength;
+ length = epState->transferLength - epState->transferPrimedLength;
+ /* Data length needs to less than max packet size. */
+#if ((defined(USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX)) && \
+ (USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX > 0U))
+ if ((USB_ENDPOINT_BULK == epState->stateUnion.stateBitField.endpointType) && ((endpointIndex & 0x01U) == 0x00U))
+ {
+ if (length > USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX)
+ {
+ length = USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX;
+ }
+ }
+ else
+ {
+ if (length > epState->stateUnion.stateBitField.maxPacketSize)
+ {
+ length = epState->stateUnion.stateBitField.maxPacketSize;
+ }
+ }
+#else
+ if (length > epState->stateUnion.stateBitField.maxPacketSize)
+ {
+ length = epState->stateUnion.stateBitField.maxPacketSize;
+ }
+#endif
+
+ epState->epBufferStatusUnion[odd].epBufferStatusField.epPacketCopyed = 0;
+
+ index = (endpointIndex & 0x01u); /* index mean IN endpoint here */
+ if (length > 0U)
+ {
+#if ((defined(USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY > 0U))
+/* if all the enabled IP support the reserved buffer, then don't need the judgement. */
+#if (!USB_DEVICE_IP3511_ALL_IP_SUPPORT_RESERVED_BUFFER)
+#define USB_DEVICE_IP3511_NEED_CHECK_BUFFER (1u)
+ /* lengt > 0 && ((buffer not align with 64) || (buffer is not in the deticated ram))) */
+ if (USB_DeviceLpcIp3511MaxPacketNeedCopy(lpc3511IpState))
+#endif
+#else
+#define USB_DEVICE_IP3511_NEED_CHECK_BUFFER (1u)
+ /* align the buffer for control transfer */
+ if (((endpointIndex >> 1U) == USB_CONTROL_ENDPOINT))
+#endif
+ {
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+#if ((defined(FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)) && (FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS))
+ uint32_t bufferValue = (uint32_t)actualBuffer;
+#if ((defined(__SAUREGION_PRESENT)) && (__SAUREGION_PRESENT > 0U))
+ bufferValue &= (0xEFFFFFFFu); /* bit28 is the secure address label */
+#endif
+#endif
+#endif
+ /* not 64 bytes align || not in the dedicated ram || ( OUT && not mutiple of 4 ) */
+ if ((((uint32_t)actualBuffer & 0x0000003FU) != 0U) ||
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+#if ((defined(FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)) && (FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS))
+ (
+#endif
+#endif
+ (((uint32_t)actualBuffer & 0xFFC00000U) !=
+ (lpc3511IpState->registerBase->DATABUFSTART & 0xFFC00000U))
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+#if ((defined(FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)) && (FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS))
+
+ || ((0U != lpc3511IpState->controllerSpeed) &&
+ ((bufferValue < (uint32_t)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS) ||
+ (bufferValue >
+ ((uint32_t)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS + (uint32_t)FSL_FEATURE_USBHSD_USB_RAM))))
+#endif
+#endif
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+#if ((defined(FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)) && (FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS))
+ )
+#endif
+#endif
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+ || ((0U != lpc3511IpState->controllerSpeed) && (0U == index) &&
+ (length != epState->stateUnion.stateBitField.maxPacketSize)))
+#else
+ )
+#endif
+ {
+ epState->epBufferStatusUnion[odd].epBufferStatusField.epPacketCopyed = 1U;
+/* usb copy buffer for this packet */
+#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE)
+#if ((defined(USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX)) && \
+ (USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX > 0U))
+ if ((USB_ENDPOINT_BULK == epState->stateUnion.stateBitField.endpointType) &&
+ ((endpointIndex & 0x01U) == 0x00U))
+ {
+ destBuffer = (uint8_t *)(epState->epPacketBuffer +
+ (odd * USB_LPC3511IP_GET_MULTIPLE_OF_64(
+ USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX)));
+ }
+ else
+ {
+ destBuffer = (uint8_t *)(epState->epPacketBuffer +
+ (odd * USB_LPC3511IP_GET_MULTIPLE_OF_64(
+ epState->stateUnion.stateBitField.maxPacketSize)));
+ }
+#else
+ destBuffer =
+ (uint8_t *)(epState->epPacketBuffer + (odd * USB_LPC3511IP_GET_MULTIPLE_OF_64(
+ epState->stateUnion.stateBitField.maxPacketSize)));
+#endif
+#else
+ destBuffer = (uint8_t *)(epState->epPacketBuffer);
+#endif
+ if (0U != index) /* USB_IN */
+ {
+ (void)memcpy(destBuffer, actualBuffer, length);
+ }
+ else
+ {
+#if ((defined(FSL_FEATURE_USB_VERSION) && (FSL_FEATURE_USB_VERSION >= 200U)) || \
+ (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)))
+#else
+#if ((defined(USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX)) && \
+ (USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX > 0U))
+ if (length < epState->stateUnion.stateBitField.maxPacketSize)
+ {
+ length = epState->stateUnion.stateBitField.maxPacketSize;
+ }
+ else
+ {
+ length = ((length + epState->stateUnion.stateBitField.maxPacketSize - 1) /
+ epState->stateUnion.stateBitField.maxPacketSize) *
+ (epState->stateUnion.stateBitField.maxPacketSize);
+ }
+#else
+ length = epState->stateUnion.stateBitField.maxPacketSize;
+#endif
+#endif
+ }
+ actualBuffer = destBuffer;
+ }
+ }
+#if (defined USB_DEVICE_IP3511_NEED_CHECK_BUFFER) && (USB_DEVICE_IP3511_NEED_CHECK_BUFFER)
+ else /* cannot do memory copy */
+ {
+ /* not 64 bytes align || not in the dedicated ram || ( OUT && HS && not mutiple of 4 ) */
+ if ((((uint32_t)actualBuffer & 0x0000003FU) != 0U) ||
+ (((uint32_t)actualBuffer & 0xFFC00000U) != (lpc3511IpState->registerBase->DATABUFSTART & 0xFFC00000U))
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+ || ((0U != lpc3511IpState->controllerSpeed) && (0U == index) && ((length & 0x00000003u) != 0U)))
+#else
+ )
+#endif
+ {
+ return kStatus_USB_Error;
+ }
+ }
+#endif
+ }
+
+ /* Send/Receive data when the device is not resetting. */
+ if (0U == lpc3511IpState->isResetting)
+ {
+ return USB_DeviceLpc3511IpEndpointPrime(lpc3511IpState, epState, endpointIndex, actualBuffer, length);
+ }
+ else
+ {
+ return kStatus_USB_Error;
+ }
+}
+static usb_status_t USB_DeviceLpc3511IpTransaction(usb_device_lpc3511ip_state_struct_t *lpc3511IpState,
+ usb_device_lpc3511ip_endpoint_state_struct_t *epState,
+ uint8_t endpointIndex)
+{
+ usb_status_t status = kStatus_USB_Error;
+ OSA_SR_ALLOC();
+
+#if (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)) && \
+ (!(defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)))
+#else
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))
+ if (lpc3511IpState->hsInterruptIssue)
+ {
+#endif
+ /* high-speed */
+ if ((0U != (epState->stateUnion.stateBitField.epControlDefault &
+ ((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT))) &&
+ (USB_ENDPOINT_INTERRUPT == epState->stateUnion.stateBitField.endpointType) &&
+ (0U != lpc3511IpState->controllerSpeed))
+ {
+ /* users can use NVIC to disable/enable the USB interrupt to improve the system performance */
+ OSA_ENTER_CRITICAL();
+
+ lpc3511IpState->registerBase->DEVCMDSTAT |=
+ (USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AO_MASK | USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AI_MASK);
+
+#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE)
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(
+ lpc3511IpState, endpointIndex, epState->stateUnion.stateBitField.producerOdd,
+ (epState->stateUnion.stateBitField.epControlDefault << USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT) |
+ (epState->stateUnion.stateBitField.stalled << USB_LPC3511IP_ENDPOINT_STALL_SHIFT),
+ 0U, (uint32_t)lpc3511IpState->zeroTransactionData);
+#else
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(
+ lpc3511IpState, endpointIndex, 0,
+ (epState->stateUnion.stateBitField.epControlDefault << USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT) |
+ (epState->stateUnion.stateBitField.stalled << USB_LPC3511IP_ENDPOINT_STALL_SHIFT),
+ 0U, (uint32_t)lpc3511IpState->zeroTransactionData);
+#endif
+ /* users can use NVIC to disable/enable the USB interrupt to improve the system performance */
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_Success;
+ }
+#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))
+ }
+#endif
+#endif
+#endif
+
+ /* Enter critical */
+ OSA_ENTER_CRITICAL();
+ if (0U != epState->stateUnion.stateBitField.stalled)
+ {
+ if ((endpointIndex >> 1U) != USB_ENDPOINT_CONTROL)
+ {
+ epState->stateUnion.stateBitField.stallPrimed = 1u;
+ status = kStatus_USB_Success;
+ }
+ status = kStatus_USB_Error;
+ OSA_EXIT_CRITICAL();
+ return status;
+ }
+ OSA_EXIT_CRITICAL();
+
+ /* 1. transfer size is 0; 2. All are primed */
+ if ((epState->transferLength <= epState->transferPrimedLength) && (epState->transferLength != 0U))
+ {
+ return kStatus_USB_Success;
+ }
+#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE)
+ if ((endpointIndex >> 1U) != USB_CONTROL_ENDPOINT)
+ {
+ /* disable endpoint interrupts, users can use NVIC to disable/enable the USB interrupt to improve the system
+ * performance */
+ OSA_ENTER_CRITICAL();
+ /* lpc3511IpState->registerBase->INTEN &= (uint32_t)(~(USB_LPC3511IP_MAX_PHY_ENDPOINT_MASK)); */
+#if ((defined(USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER)) && (USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER > 0U))
+ /* for out endpoint,only use buffer toggle, disable prime double buffer at the same time*/
+ /*host send data less than maxpacket size and in endpoint prime length more more than maxpacketsize, there will
+ * be state mismtach*/
+ if (0U == (endpointIndex & 0x1U))
+ {
+ status = USB_DeviceLpc3511IpGetActualBufferAndPrime(lpc3511IpState, epState, endpointIndex, 1U);
+ }
+ else
+#endif
+ {
+ do
+ {
+ status = USB_DeviceLpc3511IpGetActualBufferAndPrime(lpc3511IpState, epState, endpointIndex, 1U);
+ if (status != kStatus_USB_Success)
+ {
+ break;
+ }
+ } while ((epState->transferLength > epState->transferPrimedLength) &&
+ (epState->stateUnion.stateBitField.doubleBufferBusy < 2U));
+ }
+ /* enable endpoint interrupt again, users can use NVIC to disable/enable the USB interrupt to improve the system
+ * performance */
+ OSA_EXIT_CRITICAL();
+ }
+ else
+#endif
+ {
+ status = USB_DeviceLpc3511IpGetActualBufferAndPrime(lpc3511IpState, epState, endpointIndex, 0U);
+ }
+ return status;
+}
+
+usb_status_t USB_DeviceLpc3511IpSend(usb_device_controller_handle controllerHandle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ usb_device_lpc3511ip_state_struct_t *lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)controllerHandle;
+ uint8_t endpointIndex = USB_LPC3511IP_ENDPOINT_DES_INDEX(endpointAddress);
+ usb_device_lpc3511ip_endpoint_state_struct_t *epState =
+ USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, endpointIndex);
+
+ if (1U == epState->stateUnion.stateBitField.transferring)
+ {
+ return kStatus_USB_Error;
+ }
+
+ /* Save the transfer information */
+ epState->transferDone = 0U;
+ epState->transferBuffer = buffer;
+ epState->transferLength = length;
+ epState->transferPrimedLength = 0U;
+
+ return USB_DeviceLpc3511IpTransaction(lpc3511IpState, epState, endpointIndex);
+
+/* prime the control setup transfer if it is control in endpoint and data length is zero
+ * For IP3511 there is no need to prime, the buffer is always in the command/status list
+ */
+#if 0
+ if ((0U == length) && (USB_CONTROL_ENDPOINT == (endpointAddress & USB_ENDPOINT_NUMBER_MASK)))
+ {
+ USB_DeviceLpc3511IpPrimeNextSetup(lpc3511IpState);
+ }
+#endif
+}
+
+usb_status_t USB_DeviceLpc3511IpRecv(usb_device_controller_handle controllerHandle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ return USB_DeviceLpc3511IpSend(controllerHandle, endpointAddress, buffer, length);
+}
+
+usb_status_t USB_DeviceLpc3511IpCancel(usb_device_controller_handle controllerHandle, uint8_t ep)
+{
+ /* users can use NVIC to disable/enable the USB interrupt to improve the system performance */
+ OSA_SR_ALLOC();
+
+ usb_device_lpc3511ip_state_struct_t *lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)controllerHandle;
+ usb_device_callback_message_struct_t message;
+ uint8_t endpointIndex = USB_LPC3511IP_ENDPOINT_DES_INDEX(ep);
+ usb_device_lpc3511ip_endpoint_state_struct_t *epState =
+ USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, endpointIndex);
+
+ /* disable endpoint interrupts, users can use NVIC to disable/enable the USB interrupt to improve the system
+ * performance */
+ OSA_ENTER_CRITICAL();
+ /* Cancel the transfer and notify the up layer when the endpoint is busy. */
+ if ((0U != epState->stateUnion.stateBitField.transferring)
+#if (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)) && \
+ (!(defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)))
+#else
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+ || (
+#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))
+ (0U != lpc3511IpState->hsInterruptIssue) &&
+#endif
+ (0U != (epState->stateUnion.stateBitField.epControlDefault &
+ ((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT))) &&
+ (USB_ENDPOINT_INTERRUPT == epState->stateUnion.stateBitField.endpointType) &&
+ (0U != lpc3511IpState->controllerSpeed) &&
+ (0U != (lpc3511IpState->epCommandStatusList[epState->stateUnion.stateBitField.consumerOdd +
+ (((uint32_t)endpointIndex) * 2U)] &
+ USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK)) &&
+ (0U == (lpc3511IpState->registerBase->EPTOGGLE & ((uint32_t)(0x01UL << endpointIndex)))))
+#endif
+#endif
+ )
+ {
+#if (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)) && \
+ (!(defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)))
+#else
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))
+ if (0U != lpc3511IpState->hsInterruptIssue)
+ {
+#endif
+ epState->stateUnion.stateBitField.epControlDefault &=
+ (~((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT));
+#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))
+ }
+#endif
+#endif
+#endif
+ if ((((lpc3511IpState->epCommandStatusList[(uint32_t)endpointIndex * 2U] &
+ USB_LPC3511IP_ENDPOINT_ACTIVE_MASK) != 0U) &&
+ ((lpc3511IpState->epCommandStatusList[(uint32_t)endpointIndex * 2U] &
+ USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) != 0U)) ||
+ (((lpc3511IpState->epCommandStatusList[(uint32_t)endpointIndex * 2U + 1U] &
+ USB_LPC3511IP_ENDPOINT_ACTIVE_MASK) != 0U) &&
+ ((lpc3511IpState->epCommandStatusList[(uint32_t)endpointIndex * 2U + 1U] &
+ USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) != 0U)))
+ {
+ epState->stateUnion.stateBitField.epControlDefault |=
+ ((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT);
+ }
+
+ if ((lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_DCON_MASK) != 0U)
+ {
+ while (1U == 1U)
+ {
+ if ((lpc3511IpState->epCommandStatusList[(uint32_t)endpointIndex * 2U +
+ ((lpc3511IpState->registerBase->EPINUSE &
+ (((uint32_t)0x00000001U << endpointIndex))) >>
+ endpointIndex)] &
+ USB_LPC3511IP_ENDPOINT_ACTIVE_MASK) != 0U)
+ {
+ /* cancel the transfer in the endpoint command/status */
+ lpc3511IpState->registerBase->EPSKIP |= ((uint32_t)0x00000001U << endpointIndex);
+ while (((lpc3511IpState->registerBase->EPSKIP & ((uint32_t)0x00000001U << endpointIndex)) != 0U) &&
+ ((lpc3511IpState->epCommandStatusList[(uint32_t)endpointIndex * 2U +
+ ((lpc3511IpState->registerBase->EPINUSE &
+ (((uint32_t)0x00000001U << endpointIndex))) >>
+ endpointIndex)] &
+ USB_LPC3511IP_ENDPOINT_ACTIVE_MASK) != 0U))
+ {
+ }
+ if ((lpc3511IpState->registerBase->EPSKIP & ((uint32_t)0x00000001U << endpointIndex)) != 0U)
+ {
+ lpc3511IpState->registerBase->EPSKIP &= (~((uint32_t)0x00000001U << endpointIndex));
+ }
+ }
+
+ if (((lpc3511IpState->epCommandStatusList[endpointIndex * 2U] & USB_LPC3511IP_ENDPOINT_ACTIVE_MASK) !=
+ 0U) ||
+ ((lpc3511IpState->epCommandStatusList[endpointIndex * 2U + 1U] &
+ USB_LPC3511IP_ENDPOINT_ACTIVE_MASK) != 0U))
+ {
+ if ((lpc3511IpState->registerBase->EPINUSE & (((uint32_t)0x00000001U << endpointIndex))) != 0U)
+ {
+ lpc3511IpState->registerBase->EPINUSE &= ~((uint32_t)0x00000001U << endpointIndex);
+ }
+ else
+ {
+ lpc3511IpState->registerBase->EPINUSE |= ((uint32_t)0x00000001U << endpointIndex);
+ }
+ }
+ else
+ {
+ break;
+ }
+ }
+ }
+ else
+ {
+ /* Make sure the device is detached from host, host will not send any transaction to device.
+ * Then the endpoint status entry can be modified directly by software.
+ */
+ lpc3511IpState->epCommandStatusList[endpointIndex * 2U] = USB_LPC3511IP_ENDPOINT_DISABLE_MASK;
+ lpc3511IpState->epCommandStatusList[endpointIndex * 2U + 1U] = USB_LPC3511IP_ENDPOINT_DISABLE_MASK;
+ }
+
+ epState->stateUnion.stateBitField.transferring = 0U;
+ epState->stateUnion.stateBitField.producerOdd =
+ ((lpc3511IpState->registerBase->EPINUSE & ((uint32_t)((uint32_t)0x00000001U << endpointIndex))) >>
+ endpointIndex);
+ epState->stateUnion.stateBitField.consumerOdd =
+ ((lpc3511IpState->registerBase->EPINUSE & ((uint32_t)((uint32_t)0x00000001U << endpointIndex))) >>
+ endpointIndex);
+ epState->stateUnion.stateBitField.doubleBufferBusy = 0U;
+ /* clear interrupt status, enable endpoint interrupt again */
+ lpc3511IpState->registerBase->INTSTAT = ((uint32_t)0x00000001U << endpointIndex);
+
+ /* users can use NVIC to disable/enable the USB interrupt to improve the system performance */
+ OSA_EXIT_CRITICAL();
+
+ message.length = USB_CANCELLED_TRANSFER_LENGTH;
+ message.buffer = epState->transferBuffer;
+ message.code = ep;
+ message.isSetup = 0U;
+ (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message);
+ }
+ else
+ {
+ /* users can use NVIC to disable/enable the USB interrupt to improve the system performance */
+ OSA_EXIT_CRITICAL();
+ }
+ return kStatus_USB_Success;
+}
+
+/*seperate this function from USB_DeviceLpc3511IpControl for misra17.2 recursive */
+static usb_status_t USB_DeviceLpc3511IpControlPreSetDeviceAddress(usb_device_controller_handle controllerHandle,
+ void *param)
+{
+ usb_device_lpc3511ip_state_struct_t *lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)controllerHandle;
+ usb_status_t error = kStatus_USB_Error;
+ uint32_t tmp32Value;
+ uint8_t tmp8Value;
+ if (NULL != param)
+ {
+ tmp8Value = *((uint8_t *)param);
+ tmp32Value = lpc3511IpState->registerBase->DEVCMDSTAT;
+ tmp32Value &= (~USB_LPC3511IP_DEVCMDSTAT_DEV_ADDR_MASK);
+ tmp32Value |= ((uint32_t)tmp8Value & USB_LPC3511IP_DEVCMDSTAT_DEV_ADDR_MASK);
+ lpc3511IpState->registerBase->DEVCMDSTAT = tmp32Value;
+ error = kStatus_USB_Success;
+ }
+ return error;
+}
+
+usb_status_t USB_DeviceLpc3511IpControl(usb_device_controller_handle controllerHandle,
+ usb_device_control_type_t type,
+ void *param)
+{
+ usb_device_lpc3511ip_state_struct_t *lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)controllerHandle;
+ usb_status_t error = kStatus_USB_Error;
+ uint32_t tmp32Value;
+ uint8_t tmp8Value;
+#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U)
+ uint32_t *tmp32Pointer;
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ usb_device_struct_t *deviceHandle;
+#endif
+ usb_device_lpc3511ip_endpoint_state_struct_t *epState;
+
+ if (controllerHandle == NULL)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ deviceHandle = (usb_device_struct_t *)lpc3511IpState->deviceHandle;
+#endif
+
+ switch (type)
+ {
+ case kUSB_DeviceControlRun:
+#if ((defined(USB_DEVICE_CONFIG_ROOT2_TEST)) && (USB_DEVICE_CONFIG_ROOT2_TEST > 0U))
+ lpc3511IpState->registerBase->DEVCMDSTAT |= ((USB_LPC3511IP_DEVCMDSTAT_DCON_MASK) | (0x1 << 21));
+#else
+ lpc3511IpState->registerBase->DEVCMDSTAT |= (USB_LPC3511IP_DEVCMDSTAT_DCON_MASK);
+#endif
+ lpc3511IpState->registerBase->DEVCMDSTAT &= ~(USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK);
+ break;
+
+ case kUSB_DeviceControlStop:
+ lpc3511IpState->registerBase->DEVCMDSTAT |= USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK;
+ lpc3511IpState->registerBase->DEVCMDSTAT &= (~USB_LPC3511IP_DEVCMDSTAT_DCON_MASK);
+ break;
+
+ case kUSB_DeviceControlEndpointInit:
+ if (NULL != param)
+ {
+ error = USB_DeviceLpc3511IpEndpointInit(lpc3511IpState, (usb_device_endpoint_init_struct_t *)param);
+ }
+ break;
+
+ case kUSB_DeviceControlEndpointDeinit:
+ if (NULL != param)
+ {
+ tmp8Value = *((uint8_t *)param);
+ error = USB_DeviceLpc3511IpEndpointDeinit(lpc3511IpState, tmp8Value);
+ }
+ break;
+
+ case kUSB_DeviceControlEndpointStall:
+ if (NULL != param)
+ {
+ tmp8Value = *((uint8_t *)param);
+ error = USB_DeviceLpc3511IpEndpointStall(lpc3511IpState, tmp8Value);
+ }
+ break;
+
+ case kUSB_DeviceControlEndpointUnstall:
+ if (NULL != param)
+ {
+ tmp8Value = *((uint8_t *)param);
+ error = USB_DeviceLpc3511IpEndpointUnstall(lpc3511IpState, tmp8Value);
+ }
+ break;
+
+ case kUSB_DeviceControlGetDeviceStatus:
+ if (NULL != param)
+ {
+ *((uint16_t *)param) =
+ (USB_DEVICE_CONFIG_SELF_POWER << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT))
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ | ((uint16_t)(((uint32_t)deviceHandle->remotewakeup)
+ << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT)))
+#endif
+ ;
+ error = kStatus_USB_Success;
+ }
+ break;
+
+ case kUSB_DeviceControlGetEndpointStatus:
+ if (NULL != param)
+ {
+ usb_device_endpoint_status_struct_t *endpointStatus = (usb_device_endpoint_status_struct_t *)param;
+
+ if ((((endpointStatus->endpointAddress) & USB_ENDPOINT_NUMBER_MASK)) <
+ (uint8_t)USB_DEVICE_IP3511_ENDPOINTS_NUM)
+ {
+ epState = USB_DeviceLpc3511IpGetEndpointStateStruct(
+ lpc3511IpState, USB_LPC3511IP_ENDPOINT_DES_INDEX(endpointStatus->endpointAddress));
+#if (defined(USB_DEVICE_CONFIG_ROOT2_TEST) && (USB_DEVICE_CONFIG_ROOT2_TEST > 0U))
+ if (0U == epState->stateUnion.stateBitField.isOpened)
+ {
+ error = kStatus_USB_InvalidRequest;
+ }
+ else
+ {
+ endpointStatus->endpointStatus = (uint16_t)((epState->stateUnion.stateBitField.stalled == 1U) ?
+ kUSB_DeviceEndpointStateStalled :
+ kUSB_DeviceEndpointStateIdle);
+ error = kStatus_USB_Success;
+ }
+#else
+ endpointStatus->endpointStatus =
+ (uint16_t)((epState->stateUnion.stateBitField.stalled == 1U) ? kUSB_DeviceEndpointStateStalled :
+ kUSB_DeviceEndpointStateIdle);
+ error = kStatus_USB_Success;
+#endif
+ }
+#if (defined(USB_DEVICE_CONFIG_ROOT2_TEST) && (USB_DEVICE_CONFIG_ROOT2_TEST > 0U))
+ else
+ {
+ error = kStatus_USB_InvalidRequest;
+ }
+#endif
+ }
+ break;
+
+ case kUSB_DeviceControlPreSetDeviceAddress:
+ error = USB_DeviceLpc3511IpControlPreSetDeviceAddress(controllerHandle, param);
+ if (kStatus_USB_Success == error)
+ {
+ /*no action, just for misra4.7*/
+ }
+ break;
+
+ case kUSB_DeviceControlSetDeviceAddress:
+ error = kStatus_USB_Success;
+ break;
+
+ case kUSB_DeviceControlGetSynchFrame:
+#if (defined(USB_DEVICE_CONFIG_ROOT2_TEST) && (USB_DEVICE_CONFIG_ROOT2_TEST > 0U))
+ if (NULL != param)
+ {
+ usb_device_endpoint_status_struct_t *endpointStatus = (usb_device_endpoint_status_struct_t *)param;
+ if ((((endpointStatus->endpointAddress) & USB_ENDPOINT_NUMBER_MASK)) <
+ (uint8_t)USB_DEVICE_IP3511_ENDPOINTS_NUM)
+ {
+ epState = USB_DeviceLpc3511IpGetEndpointStateStruct(
+ lpc3511IpState, USB_LPC3511IP_ENDPOINT_DES_INDEX(endpointStatus->endpointAddress));
+ /* In configured state (should stall in other states), device must STALL status stage of Synch Frame
+ * Request with Invalid wIndex */
+ if (0U == epState->stateUnion.stateBitField.isOpened)
+ {
+ error = kStatus_USB_InvalidRequest;
+ }
+ else
+ {
+ error = kStatus_USB_Success;
+ }
+ }
+ else
+ {
+ error = kStatus_USB_InvalidRequest;
+ }
+ }
+#endif
+ break;
+
+#if defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)
+ case kUSB_DeviceControlResume:
+ /* todo: turn on USB clock and enable the USB clock source */
+ lpc3511IpState->registerBase->DEVCMDSTAT |= USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK;
+ lpc3511IpState->registerBase->DEVCMDSTAT &= ~USB_LPC3511IP_DEVCMDSTAT_DSUS_MASK;
+ while (0U != (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_DSUS_MASK))
+ {
+ }
+ /* the W1C bits */
+ lpc3511IpState->registerBase->DEVCMDSTAT &=
+ ~(USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK | USB_LPC3511IP_DEVCMDSTAT_INTERRUPT_WC_MASK);
+ error = kStatus_USB_Success;
+ break;
+#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U))
+ case kUSB_DeviceControlSleepResume:
+ /* todo: turn on USB clock and enable the USB clock source */
+ lpc3511IpState->registerBase->DEVCMDSTAT |= USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK;
+ lpc3511IpState->registerBase->DEVCMDSTAT &= ~USB_LPC3511IP_DEVCMDSTAT_LPM_SUS_MASK;
+ while (0U != (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_LPM_SUS_MASK))
+ {
+ __NOP();
+ }
+ /* the W1C bits */
+ lpc3511IpState->registerBase->DEVCMDSTAT &=
+ ~(USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK | USB_LPC3511IP_DEVCMDSTAT_INTERRUPT_WC_MASK);
+ error = kStatus_USB_Success;
+ break;
+#endif
+ case kUSB_DeviceControlGetRemoteWakeUp:
+ *((uint8_t *)param) =
+ (uint8_t)((lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_MASK) >>
+ USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_SHIFT);
+ break;
+#endif /* USB_DEVICE_CONFIG_REMOTE_WAKEUP */
+
+ case kUSB_DeviceControlSetDefaultStatus:
+ for (tmp32Value = 0U; tmp32Value < (uint32_t)USB_DEVICE_IP3511_ENDPOINTS_NUM; tmp32Value++)
+ {
+ (void)USB_DeviceLpc3511IpEndpointDeinit(lpc3511IpState, (uint8_t)(tmp32Value | (USB_IN << 0x07U)));
+ (void)USB_DeviceLpc3511IpEndpointDeinit(lpc3511IpState, (uint8_t)(tmp32Value | (USB_OUT << 0x07U)));
+ }
+ USB_DeviceLpc3511IpSetDefaultState(lpc3511IpState);
+ error = kStatus_USB_Success;
+ break;
+
+ case kUSB_DeviceControlGetSpeed:
+ if (NULL != param)
+ {
+ *((uint8_t *)param) = lpc3511IpState->deviceSpeed;
+ error = kStatus_USB_Success;
+ }
+ break;
+ case kUSB_DeviceControlGetOtgStatus:
+ break;
+ case kUSB_DeviceControlSetOtgStatus:
+ break;
+#if (defined(USB_DEVICE_CONFIG_USB20_TEST_MODE) && (USB_DEVICE_CONFIG_USB20_TEST_MODE > 0U))
+ case kUSB_DeviceControlSetTestMode:
+ if (NULL != param)
+ {
+ tmp8Value = *((uint8_t *)param);
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+ lpc3511IpState->registerBase->DEVCMDSTAT |=
+ ((uint32_t)(tmp8Value) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT);
+#endif
+ error = kStatus_USB_Success;
+ }
+ break;
+#endif
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))
+ case kUSB_DeviceControlDcdEnable:
+ if (kStatus_hsdcd_Success == USB_HSDCD_Control(lpc3511IpState->dcdHandle, kUSB_DeviceHSDcdEnable, NULL))
+ {
+ error = kStatus_USB_Success;
+ }
+ break;
+ case kUSB_DeviceControlDcdDisable:
+ if (kStatus_hsdcd_Success == USB_HSDCD_Control(lpc3511IpState->dcdHandle, kUSB_DeviceHSDcdDisable, NULL))
+ {
+ error = kStatus_USB_Success;
+ }
+ break;
+ case kUSB_DeviceControlUpdateHwTick:
+ /*udpate 1ms time tick*/
+ error = kStatus_USB_Success;
+ break;
+
+#endif
+#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U)
+ case kUSB_DeviceControlGetCurrentFrameCount:
+ if (NULL != param)
+ {
+ tmp32Pointer = (uint32_t *)param;
+ if (USB_SPEED_HIGH == lpc3511IpState->deviceSpeed) /* if high speed, change to use microframe count */
+ {
+ *tmp32Pointer =
+ ((uint32_t)(((lpc3511IpState->registerBase->INFO >> USB_LPC3511IP_INFO_FRAME_NR_SHIFT) &
+ USB_LPC3511IP_INFO_FRAME_NR_MASK) &
+ (USB_DEVICE_MAX_FRAME_COUNT))) *
+ 8U;
+ }
+ else
+ {
+ *tmp32Pointer =
+ ((uint32_t)(((lpc3511IpState->registerBase->INFO >> USB_LPC3511IP_INFO_FRAME_NR_SHIFT) &
+ USB_LPC3511IP_INFO_FRAME_NR_MASK) &
+ (USB_DEVICE_MAX_FRAME_COUNT)));
+ }
+ error = kStatus_USB_Success;
+ }
+ break;
+#endif
+ default:
+ /*no action*/
+ break;
+ }
+
+ return error;
+}
+
+void USB_DeviceLpcIp3511IsrFunction(void *deviceHandle)
+{
+ usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle;
+ usb_device_lpc3511ip_state_struct_t *lpc3511IpState;
+ uint32_t interruptStatus;
+ uint32_t usbErrorCode;
+ uint32_t devState;
+
+ if (NULL == deviceHandle)
+ {
+ return;
+ }
+
+ lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)(handle->controllerHandle);
+ /* get and clear interrupt status */
+ interruptStatus = lpc3511IpState->registerBase->INTSTAT;
+ lpc3511IpState->registerBase->INTSTAT = interruptStatus;
+ interruptStatus &= lpc3511IpState->registerBase->INTEN;
+
+ usbErrorCode = (lpc3511IpState->registerBase->INFO & USB_LPC3511IP_INFO_ERR_CODE_MASK);
+
+ /* device status change interrupt */
+ if (0U != (interruptStatus & USB_LPC3511IP_INTSTAT_DEV_INT_MASK))
+ {
+ /* get and clear device state change status */
+ devState = lpc3511IpState->registerBase->DEVCMDSTAT;
+ devState &= ~(USB_LPC3511IP_DEVCMDSTAT_SETUP_MASK);
+ lpc3511IpState->registerBase->DEVCMDSTAT = (devState | USB_LPC3511IP_DEVCMDSTAT_INTERRUPT_WC_MASK);
+
+ /* For HS: there is interrupt with DEV_INT=1, OTG_C=1 and ADPPROBE=1 when vbus rising.
+ * For FS: there is no interrupt when vbus rising. The only way is: check the VBUS_DEBOUNCED in the DRES_C
+ * interrupt with DCON set.
+ */
+#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE))
+ if ((0U == lpc3511IpState->deviceState) &&
+ ((0U != (devState & USB_LPC3511IP_DEVCMDSTAT_VBUS_DEBOUNCED_MASK))
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+ || ((0U != (lpc3511IpState->registerBase->LPM & USB_LPC3511IP_USB_LPM_ADPPROBE_MASK)) &&
+ (1U == lpc3511IpState->controllerSpeed))
+#endif
+ ))
+ {
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+#if ((defined(USB_DEVICE_IP3511HS_LPM_ADPPROBE_ATTACH_DEBOUNCE_COUNT)) && \
+ (USB_DEVICE_IP3511HS_LPM_ADPPROBE_ATTACH_DEBOUNCE_COUNT > 0U))
+ /* add one little debounce for HS's attach detection because ADPPROBE is undebounced value */
+ uint32_t debounceCount = USB_DEVICE_IP3511HS_LPM_ADPPROBE_ATTACH_DEBOUNCE_COUNT;
+ if (1U == lpc3511IpState->controllerSpeed)
+ {
+ while ((0U != debounceCount) && (0U == (devState & USB_LPC3511IP_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)))
+ {
+ if (0U == (lpc3511IpState->registerBase->LPM & USB_LPC3511IP_USB_LPM_ADPPROBE_MASK))
+ {
+ break;
+ }
+ debounceCount--;
+ }
+ }
+
+ if ((debounceCount == 0U) || (0U != (devState & USB_LPC3511IP_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)))
+#endif
+#endif
+ {
+ lpc3511IpState->deviceState = 1U;
+ USB_DeviceLpc3511IpInterruptAttach(lpc3511IpState);
+#if (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) && \
+ (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U))
+ (void)USB_HSDCD_Control(lpc3511IpState->dcdHandle, kUSB_DeviceHSDcdRun, NULL);
+#endif
+ }
+ }
+ /* For HS: there is interrupt with DEV_INT=1, OTG_C=1 and ADPPROBE=0 when vbus falling.
+ * For HS and FS: there is interrupt when vbus falling if DCON is set.
+ */
+ else if ((1U == lpc3511IpState->deviceState) &&
+ (((0U != (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_DCON_MASK)) &&
+ (0U == (devState & USB_LPC3511IP_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)))
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+ || ((0U == (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_DCON_MASK)) &&
+ (0U == (lpc3511IpState->registerBase->LPM & USB_LPC3511IP_USB_LPM_ADPPROBE_MASK)) &&
+ (1U == lpc3511IpState->controllerSpeed))
+#endif
+ ))
+ {
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U))
+#if ((defined USB_DEVICE_IP3511HS_FORCE_EXIT_HS_MODE_ENABLE) && (USB_DEVICE_IP3511HS_FORCE_EXIT_HS_MODE_ENABLE > 0U))
+ uint32_t delay = 100000U;
+#endif
+#endif
+#endif
+ lpc3511IpState->deviceState = 0U;
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U))
+#if ((defined USB_DEVICE_IP3511HS_FORCE_EXIT_HS_MODE_ENABLE) && (USB_DEVICE_IP3511HS_FORCE_EXIT_HS_MODE_ENABLE > 0U))
+ /* wait at least 125us to let the host to detect the detach */
+ USB_PhyDeviceForceEnterFSMode(lpc3511IpState->controllerId, 1);
+ while (delay--)
+ {
+ __NOP();
+ }
+ USB_PhyDeviceForceEnterFSMode(lpc3511IpState->controllerId, 0);
+#endif
+#endif
+#endif
+ USB_DeviceLpc3511IpInterruptDetach(lpc3511IpState);
+ }
+ else
+ {
+ /*no action*/
+ }
+#endif
+
+ /* reset change */
+ if (0U != (devState & USB_LPC3511IP_DEVCMDSTAT_DRES_C_MASK))
+ {
+ USB_DeviceLpc3511IpInterruptReset(lpc3511IpState);
+ }
+
+/* Suspend/Resume */
+#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+ if (0U != (devState & USB_LPC3511IP_DEVCMDSTAT_DSUS_C_MASK))
+ {
+ if (0U != (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_DSUS_MASK))
+ {
+ (void)USB_DeviceLpc3511IpInterruptSuspend(lpc3511IpState);
+ }
+#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U))
+ else if (0U != (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_LPM_SUS_MASK))
+ {
+ (void)USB_DeviceLpc3511IpInterruptLPMSleep(lpc3511IpState);
+ }
+#endif
+ else
+ {
+ (void)USB_DeviceLpc3511IpInterruptResume(lpc3511IpState);
+ }
+ }
+
+#endif
+
+#if 0U /* some soc don't support this bit, need check according to the feature macro */
+ /* OTG Status change */
+ if (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_OTG_C_MASK)
+ {
+ }
+#endif
+ }
+
+ /* endpoint transfers interrupt */
+ if (0U != (interruptStatus & USB_LPC3511IP_MAX_PHY_ENDPOINT_MASK))
+ {
+ devState = 0; /* devState means index here */
+ if (0U != (interruptStatus & 0x01U)) /* control OUT */
+ {
+ if (0U != (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_SETUP_MASK))
+ {
+ devState = 2U;
+ if ((lpc3511IpState->endpointState[0].stateUnion.stateBitField.stalled == 1U) ||
+ (lpc3511IpState->endpointState[1].stateUnion.stateBitField.stalled == 1U))
+ {
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT_AND(
+ lpc3511IpState, 0, 0,
+ (~(USB_LPC3511IP_ENDPOINT_STALL_MASK | USB_LPC3511IP_ENDPOINT_ACTIVE_MASK)));
+ USB_LPC3511IP_ENDPOINT_SET_ENDPOINT_AND(
+ lpc3511IpState, 1, 0,
+ (~(USB_LPC3511IP_ENDPOINT_STALL_MASK | USB_LPC3511IP_ENDPOINT_ACTIVE_MASK)));
+ lpc3511IpState->endpointState[0].stateUnion.stateBitField.stalled = 0U;
+ lpc3511IpState->endpointState[1].stateUnion.stateBitField.stalled = 0U;
+ }
+
+ /* todo: setup token interrupt */
+ USB_DeviceLpc3511IpInterruptToken(lpc3511IpState, 0U, 1, usbErrorCode);
+ }
+ }
+
+ for (; devState < ((uint32_t)USB_DEVICE_IP3511_ENDPOINTS_NUM * 2U); ++devState)
+ {
+ /* check the endpoint interrupt */
+ if (0U != (interruptStatus & (0x01UL << devState)))
+ {
+ USB_DeviceLpc3511IpInterruptToken(lpc3511IpState, (uint8_t)devState, 0U, usbErrorCode);
+ }
+ }
+ }
+
+#if 0U
+ if (interruptStatus & USB_LPC3511IP_INTSTAT_FRAME_INT_MASK)
+ {
+ }
+#endif
+}
+
+#endif
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/lpcip3511/usb_device_lpcip3511.h b/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/lpcip3511/usb_device_lpcip3511.h
new file mode 100644
index 000000000..72e602bd0
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/lpcip3511/usb_device_lpcip3511.h
@@ -0,0 +1,318 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __USB_DEVICE_LPC3511IP_H__
+#define __USB_DEVICE_LPC3511IP_H__
+
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup usb_device_controller_lpcip3511_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* For bulk out endpoint in high speed mode, use long length data transfer to decrease the Ping packet count to increase
+ * bulk bandwidth */
+/* The bigger this macro's value is, the higher bandwidth bulk out endpoint has. However, you need to set a reasonable
+ * value for this macro based on RAM size of Soc. If this macro's value is too big, link may be failed. */
+/* Note that please set this value as integral multiple of 512U. When using USB RAM, you also can decrease the
+ * USB_DEVICE_IP3511_USB_RAM_IN_USE_SIZE within a reasonable range to use more USB RAM */
+#if (((defined(USB_DEVICE_CONFIG_MSC)) && (USB_DEVICE_CONFIG_MSC > 0U)) && \
+ ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)))
+#define USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX (0U)
+#endif
+
+/* During enumeration for high speed, IP3511HS responds NYET to the host(HUAWEI smartphone P20, Kirin 970 platform) for
+ OUT transaction in the status stage of control transfer. \ The host can not handle NYET respond in this case. Then
+ this leads to enumeration failure. This workaround is used to fix this issue, which force the prime length is 65
+ bytes. This workaround is disabled by default */
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+#define USB_DEVICE_IP3511HS_CONTROL_OUT_NYET_WORKAROUND (0U)
+#endif
+
+/*! @brief Prime all the double endpoint buffer at the same time, if the transfer length is larger than max packet size.
+ */
+#define USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE (1U)
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+#define USB_LPC3511IP_Type USBHSD_Type
+#define USB_DEVICE_IP3511_ENDPOINTS_NUM FSL_FEATURE_USBHSD_EP_NUM
+#define USB_DEVICE_IP3511_USB_RAM_SIZE FSL_FEATURE_USBHSD_USB_RAM
+#else
+#define USB_LPC3511IP_Type USB_Type
+#define USB_DEVICE_IP3511_ENDPOINTS_NUM FSL_FEATURE_USB_EP_NUM
+#if ((defined(FSL_FEATURE_USB_USB_RAM)) && (FSL_FEATURE_USB_USB_RAM > 0U))
+#define USB_DEVICE_IP3511_USB_RAM_SIZE FSL_FEATURE_USB_USB_RAM
+#endif
+#endif
+
+/*! @brief Use the macro to represent the USB RAM that has been used. The remaining USB RAM will be used by the
+ controller driver. If application needs to allocate variables into the USB RAM, please increase the macro or link
+ may fail. Likewise, if requiring to assign more USB RAM to the controller driver, please decrease the macro.
+ When USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX is used, USB_DEVICE_IP3511_USB_RAM_IN_USE_SIZE can be
+ decreased within a reasonable range to use more USB RAM. */
+#define USB_DEVICE_IP3511_USB_RAM_IN_USE_SIZE (3U * 1024U)
+/*! @brief The reserved buffer size, the buffer is for the memory copy if the application transfer buffer is
+ ((not 64 bytes alignment) || (not in the USB RAM) || (HS && OUT && not multiple of the maximum packet size)) */
+#if ((defined(USB_DEVICE_IP3511_USB_RAM_SIZE)) && (USB_DEVICE_IP3511_USB_RAM_SIZE > 0U))
+#define USB_DEVICE_IP3511_ENDPOINT_RESERVED_BUFFER_SIZE \
+ ((uint32_t)USB_DEVICE_IP3511_USB_RAM_SIZE - USB_DEVICE_IP3511_USB_RAM_IN_USE_SIZE)
+#else
+#if ((defined(USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX)) && \
+ (USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX > 0U))
+/* if use USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX (>0U), need to increase the reserved buffer size */
+#define USB_DEVICE_IP3511_ENDPOINT_RESERVED_BUFFER_SIZE \
+ ((5U * 1024U) + (USB_DEVICE_IP3511HS_BULK_OUT_ONE_TIME_TRANSFER_SIZE_MAX / 512U) * 512U)
+#else
+#define USB_DEVICE_IP3511_ENDPOINT_RESERVED_BUFFER_SIZE (5U * 1024U)
+#endif
+#endif
+
+/*! @brief Use one bit to represent one reserved 64 bytes to allocate the buffer by uint of 64 bytes. */
+#define USB_DEVICE_IP3511_BITS_FOR_RESERVED_BUFFER ((USB_DEVICE_IP3511_ENDPOINT_RESERVED_BUFFER_SIZE + 63U) / 64U)
+/*! @brief How many IPs support the reserved buffer */
+#define USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY (USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS)
+
+/* for out endpoint,only use buffer toggle, disable prime double buffer at the same time*/
+/*host send data less than maxpacket size and in endpoint prime length more more than maxpacketsize, there will be state
+ * mismtach*/
+#if USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE
+#define USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER (1U)
+#else
+#define USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER (0U)
+#endif
+
+#define USB_DEVICE_IP3511HS_LPM_ADPPROBE_ATTACH_DEBOUNCE_COUNT (3)
+
+/* if FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE is true:
+ * Enable this macro to exit HS mode automatically if the user case is:
+ * host and device keep cable connected, and host turn off vbus to simulate detachment.
+ * If user disconnects the cable, there is no issue and don't need enable this macro.
+ * There is one delay in the isr if enable this macro.
+ */
+#define USB_DEVICE_IP3511HS_FORCE_EXIT_HS_MODE_ENABLE (0u)
+
+/*! @brief Endpoint state structure */
+typedef struct _usb_device_lpc3511ip_endpoint_state_struct
+{
+ uint8_t *transferBuffer; /*!< Address of buffer containing the data to be transmitted */
+ uint32_t transferLength; /*!< Length of data to transmit. */
+ uint32_t transferDone; /*!< The data length has been transferred*/
+ uint32_t transferPrimedLength; /*!< it may larger than transferLength, because the primed length may larger than the
+ transaction length. */
+ uint8_t *epPacketBuffer; /*!< The max packet buffer for copying*/
+ union
+ {
+ uint32_t state; /*!< The state of the endpoint */
+ struct
+ {
+ uint32_t maxPacketSize : 11U; /*!< The maximum packet size of the endpoint */
+ uint32_t stalled : 1U; /*!< The endpoint is stalled or not */
+ uint32_t transferring : 1U; /*!< The endpoint is transferring */
+ uint32_t zlt : 1U; /*!< zlt flag */
+ uint32_t stallPrimed : 1U;
+ uint32_t epPacketCopyed : 1U; /*!< whether use the copy buffer */
+ uint32_t epControlDefault : 5u; /*!< The EP command/status 26~30 bits */
+ uint32_t doubleBufferBusy : 2U; /*!< How many buffers are primed, for control endpoint it is not used */
+ uint32_t producerOdd : 1U; /*!< When priming one transaction, prime to this endpoint buffer */
+ uint32_t consumerOdd : 1U; /*!< When transaction is done, read result from this endpoint buffer */
+ uint32_t endpointType : 2U;
+#if (defined(USB_DEVICE_CONFIG_ROOT2_TEST) && (USB_DEVICE_CONFIG_ROOT2_TEST > 0U))
+ uint32_t isOpened : 1U; /*!< whether the endpoint is initialized */
+ uint32_t reserved1 : 4U;
+#else
+ uint32_t reserved1 : 5U;
+#endif
+ } stateBitField;
+ } stateUnion;
+ union
+ {
+ uint16_t epBufferStatus;
+ /* If double buff is disable, only epBufferStatusUnion[0] is used;
+ For control endpoint, only epBufferStatusUnion[0] is used. */
+ struct
+ {
+ uint16_t transactionLength : 15U;
+ uint16_t epPacketCopyed : 1U;
+ } epBufferStatusField;
+ } epBufferStatusUnion[2];
+} usb_device_lpc3511ip_endpoint_state_struct_t;
+
+/*! @brief LPC USB controller (IP3511) state structure */
+typedef struct _usb_device_lpc3511ip_state_struct
+{
+ /*!< control data buffer, must align with 64 */
+ uint8_t *controlData;
+ /*!< 8 bytes' setup data, must align with 64 */
+ uint8_t *setupData;
+ /*!< 4 bytes for zero length transaction, must align with 64 */
+ uint8_t *zeroTransactionData;
+ /* Endpoint state structures */
+ usb_device_lpc3511ip_endpoint_state_struct_t endpointState[(USB_DEVICE_IP3511_ENDPOINTS_NUM * 2)];
+ usb_device_handle deviceHandle; /*!< (4 bytes) Device handle used to identify the device object belongs to */
+ USB_LPC3511IP_Type *registerBase; /*!< (4 bytes) ip base address */
+ volatile uint32_t *epCommandStatusList; /* endpoint list */
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))
+ void *dcdHandle; /*!< Dcd handle used to identify the device object belongs to */
+#endif
+ uint8_t controllerId; /*!< Controller ID */
+ uint8_t isResetting; /*!< Is doing device reset or not */
+ uint8_t deviceSpeed; /*!< some controller support the HS */
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+ uint8_t controllerSpeed;
+#endif
+#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE))
+ uint8_t deviceState; /*!< Is device attached,1 attached,0 detached */
+#endif
+#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U))
+ uint8_t lpmRemoteWakeUp;
+#endif
+#endif
+#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))
+#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \
+ (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))
+ uint8_t hsInterruptIssue;
+#endif
+#endif
+} usb_device_lpc3511ip_state_struct_t;
+
+/*!
+ * @name USB device controller (IP3511) functions
+ * @{
+ */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the USB device controller instance.
+ *
+ * This function initializes the USB device controller module specified by the controllerId.
+ *
+ * @param[in] controllerId The controller ID of the USB IP. See the enumeration type usb_controller_index_t.
+ * @param[in] handle Pointer of the device handle used to identify the device object belongs to.
+ * @param[out] controllerHandle An out parameter used to return the pointer of the device controller handle to the
+ * caller.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceLpc3511IpInit(uint8_t controllerId,
+ usb_device_handle handle,
+ usb_device_controller_handle *controllerHandle);
+
+/*!
+ * @brief Deinitializes the USB device controller instance.
+ *
+ * This function deinitializes the USB device controller module.
+ *
+ * @param[in] controllerHandle Pointer of the device controller handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceLpc3511IpDeinit(usb_device_controller_handle controllerHandle);
+
+/*!
+ * @brief Sends data through a specified endpoint.
+ *
+ * This function sends data through a specified endpoint.
+ *
+ * @param[in] controllerHandle Pointer of the device controller handle.
+ * @param[in] endpointAddress Endpoint index.
+ * @param[in] buffer The memory address to hold the data need to be sent.
+ * @param[in] length The data length need to be sent.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ *
+ * @note The return value indicates whether the sending request is successful or not. The transfer completion is
+ * notified by the
+ * corresponding callback function.
+ * Currently, only one transfer request can be supported for a specific endpoint.
+ * If there is a specific requirement to support multiple transfer requests for a specific endpoint, the application
+ * should implement a queue in the application level.
+ * The subsequent transfer can begin only when the previous transfer is done (a notification is obtained through the
+ * endpoint
+ * callback).
+ */
+usb_status_t USB_DeviceLpc3511IpSend(usb_device_controller_handle controllerHandle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Receives data through a specified endpoint.
+ *
+ * This function receives data through a specified endpoint.
+ *
+ * @param[in] controllerHandle Pointer of the device controller handle.
+ * @param[in] endpointAddress Endpoint index.
+ * @param[in] buffer The memory address to save the received data.
+ * @param[in] length The data length to be received.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ *
+ * @note The return value indicates whether the receiving request is successful or not. The transfer completion is
+ * notified by the
+ * corresponding callback function.
+ * Currently, only one transfer request can be supported for a specific endpoint.
+ * If there is a specific requirement to support multiple transfer requests for a specific endpoint, the application
+ * should implement a queue in the application level.
+ * The subsequent transfer can begin only when the previous transfer is done (a notification is obtained through the
+ * endpoint
+ * callback).
+ */
+usb_status_t USB_DeviceLpc3511IpRecv(usb_device_controller_handle controllerHandle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Cancels the pending transfer in a specified endpoint.
+ *
+ * The function is used to cancel the pending transfer in a specified endpoint.
+ *
+ * @param[in] controllerHandle ointer of the device controller handle.
+ * @param[in] ep Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceLpc3511IpCancel(usb_device_controller_handle controllerHandle, uint8_t ep);
+
+/*!
+ * @brief Controls the status of the selected item.
+ *
+ * The function is used to control the status of the selected item.
+ *
+ * @param[in] controllerHandle Pointer of the device controller handle.
+ * @param[in] type The selected item. Please refer to enumeration type usb_device_control_type_t.
+ * @param[in,out] param The parameter type is determined by the selected item.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceLpc3511IpControl(usb_device_controller_handle controllerHandle,
+ usb_device_control_type_t type,
+ void *param);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* __USB_DEVICE_LPC3511IP_H__ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_ch9.c b/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_ch9.c
new file mode 100644
index 000000000..02258ec3e
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_ch9.c
@@ -0,0 +1,1135 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "usb_device_config.h"
+#include "usb.h"
+
+#include "usb_device.h"
+#include "usb_device_dci.h"
+#include "usb_device_class.h"
+#include "usb_device_ch9.h"
+#if ((defined(USB_DEVICE_CONFIG_NUM)) && (USB_DEVICE_CONFIG_NUM > 0U))
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Standard request callback function typedef.
+ *
+ * This function is used to handle the standard request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+typedef usb_status_t (*usb_standard_request_callback_t)(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static usb_status_t USB_DeviceCh9GetStatus(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+static usb_status_t USB_DeviceCh9SetClearFeature(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+
+static usb_status_t USB_DeviceCh9SetAddress(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+static usb_status_t USB_DeviceCh9GetDescriptor(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+static usb_status_t USB_DeviceCh9GetConfiguration(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+static usb_status_t USB_DeviceCh9SetConfiguration(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+static usb_status_t USB_DeviceCh9GetInterface(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+static usb_status_t USB_DeviceCh9SetInterface(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+static usb_status_t USB_DeviceCh9SynchFrame(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* The function list to handle the standard request. */
+static const usb_standard_request_callback_t s_UsbDeviceStandardRequest[] = {
+ USB_DeviceCh9GetStatus,
+ USB_DeviceCh9SetClearFeature,
+ (usb_standard_request_callback_t)NULL,
+ USB_DeviceCh9SetClearFeature,
+ (usb_standard_request_callback_t)NULL,
+ USB_DeviceCh9SetAddress,
+ USB_DeviceCh9GetDescriptor,
+ (usb_standard_request_callback_t)NULL,
+ USB_DeviceCh9GetConfiguration,
+ USB_DeviceCh9SetConfiguration,
+ USB_DeviceCh9GetInterface,
+ USB_DeviceCh9SetInterface,
+ USB_DeviceCh9SynchFrame,
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Handle get status request.
+ *
+ * This function is used to handle get status request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The request is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9GetStatus(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ usb_status_t error = kStatus_USB_InvalidRequest;
+ uint8_t state = 0U;
+
+ if (((setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) != USB_REQUEST_TYPE_DIR_IN) || (setup->wValue != 0U) ||
+ (setup->wLength != 2U))
+ {
+ return error;
+ }
+
+ (void)USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if (((uint8_t)kUSB_DeviceStateAddress != state) && ((uint8_t)kUSB_DeviceStateConfigured != state))
+ {
+ return error;
+ }
+
+ if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_DEVICE)
+ {
+#if (defined(USB_DEVICE_CONFIG_OTG) && (USB_DEVICE_CONFIG_OTG))
+ if (setup->wIndex == USB_REQUEST_STANDARD_GET_STATUS_OTG_STATUS_SELECTOR)
+ {
+ error =
+ USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusOtg, &classHandle->standardTranscationBuffer);
+ classHandle->standardTranscationBuffer = USB_SHORT_TO_LITTLE_ENDIAN(classHandle->standardTranscationBuffer);
+ /* The device status length must be USB_DEVICE_STATUS_SIZE. */
+ *length = 1;
+ }
+ else /* Get the device status */
+ {
+#endif
+ error = USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusDevice,
+ &classHandle->standardTranscationBuffer);
+ classHandle->standardTranscationBuffer =
+ classHandle->standardTranscationBuffer & USB_GET_STATUS_DEVICE_MASK;
+ classHandle->standardTranscationBuffer = USB_SHORT_TO_LITTLE_ENDIAN(classHandle->standardTranscationBuffer);
+ /* The device status length must be USB_DEVICE_STATUS_SIZE. */
+ *length = USB_DEVICE_STATUS_SIZE;
+#if (defined(USB_DEVICE_CONFIG_OTG) && (USB_DEVICE_CONFIG_OTG))
+ }
+#endif
+ }
+ else if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_INTERFACE)
+ {
+#if ((defined(USB_DEVICE_CONFIG_ROOT2_TEST)) && (USB_DEVICE_CONFIG_ROOT2_TEST > 0U))
+ if (((uint8_t)kUSB_DeviceStateAddress == state) ||
+ (((uint8_t)kUSB_DeviceStateConfigured == state) && (0U == setup->wIndex)))
+ {
+ /* In valid address state, device must stall the status stage for get status (interface) request.
+ In configured state, device must stall the status stage for get status (interface 0) request */
+ return error;
+ }
+#endif
+ /* Get the interface status */
+ error = kStatus_USB_Success;
+ classHandle->standardTranscationBuffer = 0U;
+ /* The interface status length must be USB_INTERFACE_STATUS_SIZE. */
+ *length = USB_INTERFACE_STATUS_SIZE;
+ }
+ else if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_ENDPOINT)
+ {
+#if ((defined(USB_DEVICE_CONFIG_ROOT2_TEST)) && (USB_DEVICE_CONFIG_ROOT2_TEST > 0U))
+ if ((USB_CONTROL_ENDPOINT != (setup->wIndex & USB_ENDPOINT_NUMBER_MASK)) &&
+ ((uint8_t)kUSB_DeviceStateAddress == state))
+ {
+ /* In valid address, device must stall the status stage for get status (EP) request for no-control endpoint
+ */
+ return error;
+ }
+#endif
+ /* Get the endpoint status */
+ usb_device_endpoint_status_struct_t endpointStatus;
+ endpointStatus.endpointAddress = (uint8_t)setup->wIndex;
+ endpointStatus.endpointStatus = (uint16_t)kUSB_DeviceEndpointStateIdle;
+ error = USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusEndpoint, &endpointStatus);
+ classHandle->standardTranscationBuffer = endpointStatus.endpointStatus & USB_GET_STATUS_ENDPOINT_MASK;
+ classHandle->standardTranscationBuffer = USB_SHORT_TO_LITTLE_ENDIAN(classHandle->standardTranscationBuffer);
+ /* The endpoint status length must be USB_INTERFACE_STATUS_SIZE. */
+ *length = USB_ENDPOINT_STATUS_SIZE;
+ }
+ else
+ {
+ /*no action*/
+ }
+ *buffer = (uint8_t *)&classHandle->standardTranscationBuffer;
+
+ return error;
+}
+
+/*!
+ * @brief Handle set or clear device feature request.
+ *
+ * This function is used to handle set or clear device feature request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The request is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9SetClearFeature(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ usb_status_t error = kStatus_USB_InvalidRequest;
+ uint8_t state = 0U;
+ uint8_t isSet = 0U;
+
+ if (((setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) != USB_REQUEST_TYPE_DIR_OUT) || (setup->wLength != 0U))
+ {
+ return error;
+ }
+
+ (void)USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if (((uint8_t)kUSB_DeviceStateAddress != state) && ((uint8_t)kUSB_DeviceStateConfigured != state))
+ {
+ return error;
+ }
+
+ /* Identify the request is set or clear the feature. */
+ if (USB_REQUEST_STANDARD_SET_FEATURE == setup->bRequest)
+ {
+ isSet = 1U;
+ }
+
+ if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_DEVICE)
+ {
+ /* Set or Clear the device feature. */
+ if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_REMOTE_WAKEUP == setup->wValue)
+ {
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ USB_DeviceSetStatus(classHandle->handle, kUSB_DeviceStatusRemoteWakeup, &isSet);
+#endif
+ /* Set or Clear the device remote wakeup feature. */
+ error = USB_DeviceClassCallback(classHandle->handle, (uint32_t)kUSB_DeviceEventSetRemoteWakeup, &isSet);
+ }
+#if ((defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)) || \
+ (defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) && \
+ (defined(USB_DEVICE_CONFIG_USB20_TEST_MODE) && (USB_DEVICE_CONFIG_USB20_TEST_MODE > 0U))
+ else if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_TEST_MODE == setup->wValue)
+ {
+ state = kUSB_DeviceStateTestMode;
+ error = USB_DeviceSetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state);
+ }
+#endif
+#if (defined(USB_DEVICE_CONFIG_OTG) && (USB_DEVICE_CONFIG_OTG))
+ else if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_B_HNP_ENABLE == setup->wValue)
+ {
+ error = USB_DeviceClassCallback(classHandle->handle, kUSB_DeviceEventSetBHNPEnable, &isSet);
+ }
+#endif
+ else
+ {
+ }
+ }
+ else if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_ENDPOINT)
+ {
+ /* Set or Clear the endpoint feature. */
+ if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT == setup->wValue)
+ {
+#if ((defined(USB_DEVICE_CONFIG_ROOT2_TEST)) && (USB_DEVICE_CONFIG_ROOT2_TEST > 0U))
+ if ((USB_CONTROL_ENDPOINT != (setup->wIndex & USB_ENDPOINT_NUMBER_MASK)) &&
+ (kUSB_DeviceStateConfigured != state))
+ {
+ /* In no-configured state, device must stall the status stage for clear/set feature halt requests for
+ * no-control endpoint */
+ return error;
+ }
+ else
+ {
+ /* In configured state, device must stall the status stage for clear/set feature halt for no-initialized
+ EP. For contol EP, device must accept status stage of Set Feature Halt (Endpoint 80) in Addressed
+ State */
+ usb_device_endpoint_status_struct_t endpointStatus;
+ endpointStatus.endpointAddress = (uint8_t)setup->wIndex;
+ error = USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusEndpoint, &endpointStatus);
+ if (kStatus_USB_Success != error)
+ {
+ return error;
+ }
+ }
+#else
+ if (USB_CONTROL_ENDPOINT == (setup->wIndex & USB_ENDPOINT_NUMBER_MASK))
+ {
+ /* Set or Clear the control endpoint status(halt or not). */
+ if (0U != isSet)
+ {
+ (void)USB_DeviceStallEndpoint(classHandle->handle, (uint8_t)setup->wIndex);
+ }
+ else
+ {
+ (void)USB_DeviceUnstallEndpoint(classHandle->handle, (uint8_t)setup->wIndex);
+ }
+ }
+#endif
+ /* Set or Clear the endpoint status feature. */
+ if (0U != isSet)
+ {
+ error = USB_DeviceClassEvent(classHandle->handle, kUSB_DeviceClassEventSetEndpointHalt, &setup->wIndex);
+ }
+ else
+ {
+ error =
+ USB_DeviceClassEvent(classHandle->handle, kUSB_DeviceClassEventClearEndpointHalt, &setup->wIndex);
+ }
+ }
+ else
+ {
+ /*no action*/
+ }
+ }
+ else
+ {
+ /*no action*/
+ }
+
+ return error;
+}
+
+/*!
+ * @brief Handle set address request.
+ *
+ * This function is used to handle set address request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The request is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state.
+ */
+static usb_status_t USB_DeviceCh9SetAddress(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ usb_status_t error = kStatus_USB_InvalidRequest;
+ uint8_t state = 0U;
+
+ if (((setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) != USB_REQUEST_TYPE_DIR_OUT) ||
+ ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) != USB_REQUEST_TYPE_RECIPIENT_DEVICE) ||
+ (setup->wIndex != 0U) || (setup->wLength != 0U))
+ {
+ return error;
+ }
+
+ (void)USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if (((uint8_t)kUSB_DeviceStateAddressing != state) && ((uint8_t)kUSB_DeviceStateAddress != state) &&
+ ((uint8_t)kUSB_DeviceStateDefault != state)
+#if ((defined(USB_DEVICE_CONFIG_ROOT2_TEST)) && (USB_DEVICE_CONFIG_ROOT2_TEST > 0U))
+#else
+ && ((uint8_t)kUSB_DeviceStateConfigured != state)
+#endif
+ )
+ {
+ return error;
+ }
+
+ if ((uint8_t)kUSB_DeviceStateAddressing != state)
+ {
+ /* If the device address is not setting, pass the address and the device state will change to
+ * kUSB_DeviceStateAddressing internally. */
+ state = (uint8_t)(setup->wValue & 0xFFU);
+#if ((defined(USB_DEVICE_CONFIG_ROOT2_TEST)) && (USB_DEVICE_CONFIG_ROOT2_TEST > 0U))
+ /* Setting the address to 128 or above should not be allowed. */
+ if (state >= 0x80U)
+ {
+ return error;
+ }
+#endif
+ error = USB_DeviceSetStatus(classHandle->handle, kUSB_DeviceStatusAddress, &state);
+ }
+ else
+ {
+ /* If the device address is setting, set device address and the address will be write into the controller
+ * internally. */
+ error = USB_DeviceSetStatus(classHandle->handle, kUSB_DeviceStatusAddress, NULL);
+ /* And then change the device state to kUSB_DeviceStateAddress. */
+ if (kStatus_USB_Success == error)
+ {
+ state = (uint8_t)kUSB_DeviceStateAddress;
+ error = USB_DeviceSetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state);
+ }
+ }
+
+ return error;
+}
+
+/*!
+ * @brief Handle get descriptor request.
+ *
+ * This function is used to handle get descriptor request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The request is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9GetDescriptor(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ usb_device_get_descriptor_common_union_t commonDescriptor;
+ usb_status_t error = kStatus_USB_InvalidRequest;
+ uint8_t state = 0U;
+ uint8_t descriptorType = (uint8_t)((setup->wValue & 0xFF00U) >> 8U);
+ uint8_t descriptorIndex = (uint8_t)((setup->wValue & 0x00FFU));
+
+ if ((setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) != USB_REQUEST_TYPE_DIR_IN)
+ {
+ return error;
+ }
+
+ (void)USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if (((uint8_t)kUSB_DeviceStateAddress != state) && ((uint8_t)kUSB_DeviceStateConfigured != state) &&
+ ((uint8_t)kUSB_DeviceStateDefault != state))
+ {
+ return error;
+ }
+ commonDescriptor.commonDescriptor.length = setup->wLength;
+ if (USB_DESCRIPTOR_TYPE_DEVICE == descriptorType)
+ {
+ /* Get the device descriptor */
+ if (((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_DEVICE) &&
+ (descriptorIndex == 0U) && (setup->wIndex == 0U))
+ {
+ error = USB_DeviceClassCallback(classHandle->handle, (uint32_t)kUSB_DeviceEventGetDeviceDescriptor,
+ &commonDescriptor.deviceDescriptor);
+ }
+ }
+ else if (USB_DESCRIPTOR_TYPE_CONFIGURE == descriptorType)
+ {
+ /* Get the configuration descriptor */
+ if (((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_DEVICE) &&
+ (setup->wIndex == 0U))
+ {
+ commonDescriptor.configurationDescriptor.configuration = descriptorIndex;
+ error = USB_DeviceClassCallback(classHandle->handle, (uint32_t)kUSB_DeviceEventGetConfigurationDescriptor,
+ &commonDescriptor.configurationDescriptor);
+ }
+ }
+ else if (USB_DESCRIPTOR_TYPE_STRING == descriptorType)
+ {
+ /* Get the string descriptor */
+ if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_DEVICE)
+ {
+ commonDescriptor.stringDescriptor.stringIndex = descriptorIndex;
+ commonDescriptor.stringDescriptor.languageId = setup->wIndex;
+ error = USB_DeviceClassCallback(classHandle->handle, (uint32_t)kUSB_DeviceEventGetStringDescriptor,
+ &commonDescriptor.stringDescriptor);
+ }
+ }
+#if (defined(USB_DEVICE_CONFIG_HID) && (USB_DEVICE_CONFIG_HID > 0U))
+ else if (USB_DESCRIPTOR_TYPE_HID == descriptorType)
+ {
+ /* Get the hid descriptor */
+ if (((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_INTERFACE) &&
+ (descriptorIndex == 0U))
+ {
+ commonDescriptor.hidDescriptor.interfaceNumber = (uint8_t)setup->wIndex;
+ error = USB_DeviceClassCallback(classHandle->handle, (uint32_t)kUSB_DeviceEventGetHidDescriptor,
+ &commonDescriptor.hidDescriptor);
+ }
+ }
+ else if (USB_DESCRIPTOR_TYPE_HID_REPORT == descriptorType)
+ {
+ /* Get the hid report descriptor */
+ if (((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_INTERFACE) &&
+ (descriptorIndex == 0U))
+ {
+ commonDescriptor.hidReportDescriptor.interfaceNumber = (uint8_t)setup->wIndex;
+ error = USB_DeviceClassCallback(classHandle->handle, (uint32_t)kUSB_DeviceEventGetHidReportDescriptor,
+ &commonDescriptor.hidReportDescriptor);
+ }
+ }
+ else if (USB_DESCRIPTOR_TYPE_HID_PHYSICAL == descriptorType)
+ {
+ /* Get the hid physical descriptor */
+ if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_INTERFACE)
+ {
+ commonDescriptor.hidPhysicalDescriptor.index = descriptorIndex;
+ commonDescriptor.hidPhysicalDescriptor.interfaceNumber = (uint8_t)setup->wIndex;
+ error = USB_DeviceClassCallback(classHandle->handle, (uint32_t)kUSB_DeviceEventGetHidPhysicalDescriptor,
+ &commonDescriptor.hidPhysicalDescriptor);
+ }
+ }
+#endif
+#if (defined(USB_DEVICE_CONFIG_CV_TEST) && (USB_DEVICE_CONFIG_CV_TEST > 0U))
+ else if (USB_DESCRIPTOR_TYPE_DEVICE_QUALITIER == descriptorType)
+ {
+ /* Get the device descriptor */
+ if (((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_DEVICE) &&
+ (descriptorIndex == 0U) && (setup->wIndex == 0U))
+ {
+ error = USB_DeviceClassCallback(classHandle->handle, (uint32_t)kUSB_DeviceEventGetDeviceQualifierDescriptor,
+ &commonDescriptor.deviceDescriptor);
+ }
+ }
+#endif
+#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U))
+ else if (USB_DESCRIPTOR_TYPE_BOS == descriptorType)
+ {
+ /* Get the configuration descriptor */
+ if (((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_DEVICE) &&
+ (setup->wIndex == 0U))
+ {
+ commonDescriptor.configurationDescriptor.configuration = descriptorIndex;
+ error = USB_DeviceClassCallback(classHandle->handle, (uint32_t)kUSB_DeviceEventGetBOSDescriptor,
+ &commonDescriptor.configurationDescriptor);
+ }
+ }
+#endif
+ else
+ {
+ }
+ *buffer = commonDescriptor.commonDescriptor.buffer;
+ *length = commonDescriptor.commonDescriptor.length;
+ return error;
+}
+
+/*!
+ * @brief Handle get current configuration request.
+ *
+ * This function is used to handle get current configuration request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The request is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9GetConfiguration(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ uint8_t state = 0U;
+
+ if (((setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) != USB_REQUEST_TYPE_DIR_IN) ||
+ ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) != USB_REQUEST_TYPE_RECIPIENT_DEVICE) ||
+ (setup->wValue != 0U) || (setup->wIndex != 0U) || (setup->wLength != 1U))
+ {
+ return kStatus_USB_InvalidRequest;
+ }
+
+ (void)USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if (((uint8_t)kUSB_DeviceStateAddress != state) && (((uint8_t)kUSB_DeviceStateConfigured != state)))
+ {
+ return kStatus_USB_InvalidRequest;
+ }
+
+ *length = USB_CONFIGURE_SIZE;
+ *buffer = (uint8_t *)&classHandle->standardTranscationBuffer;
+ return USB_DeviceClassCallback(classHandle->handle, (uint8_t)kUSB_DeviceEventGetConfiguration,
+ &classHandle->standardTranscationBuffer);
+}
+
+/*!
+ * @brief Handle set current configuration request.
+ *
+ * This function is used to handle set current configuration request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The request is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9SetConfiguration(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ uint8_t state = 0U;
+
+ if (((setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) != USB_REQUEST_TYPE_DIR_OUT) ||
+ ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) != USB_REQUEST_TYPE_RECIPIENT_DEVICE) ||
+ (setup->wIndex != 0U) || (setup->wLength != 0U))
+ {
+ return kStatus_USB_InvalidRequest;
+ }
+
+ (void)USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if (((uint8_t)kUSB_DeviceStateAddress != state) && ((uint8_t)kUSB_DeviceStateConfigured != state))
+ {
+ return kStatus_USB_InvalidRequest;
+ }
+
+ /* The device state is changed to kUSB_DeviceStateConfigured */
+ state = (uint8_t)kUSB_DeviceStateConfigured;
+ (void)USB_DeviceSetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state);
+ if (0U == setup->wValue)
+ {
+ /* If the new configuration is zero, the device state is changed to kUSB_DeviceStateAddress */
+ state = (uint8_t)kUSB_DeviceStateAddress;
+ (void)USB_DeviceSetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state);
+ }
+
+ /* Notify the class layer the configuration is changed */
+ (void)USB_DeviceClassEvent(classHandle->handle, kUSB_DeviceClassEventSetConfiguration, &setup->wValue);
+ /* Notify the application the configuration is changed */
+ return USB_DeviceClassCallback(classHandle->handle, (uint32_t)kUSB_DeviceEventSetConfiguration, &setup->wValue);
+}
+
+/*!
+ * @brief Handle get the alternate setting of a interface request.
+ *
+ * This function is used to handle get the alternate setting of a interface request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The request is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9GetInterface(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ usb_status_t error = kStatus_USB_InvalidRequest;
+ uint8_t state = 0U;
+
+ if (((setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) != USB_REQUEST_TYPE_DIR_IN) ||
+ ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) != USB_REQUEST_TYPE_RECIPIENT_INTERFACE) ||
+ (setup->wValue != 0U) || (setup->wLength != 1U))
+ {
+ return error;
+ }
+
+ (void)USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if (state != (uint8_t)kUSB_DeviceStateConfigured)
+ {
+ return error;
+ }
+ *length = USB_INTERFACE_SIZE;
+ *buffer = (uint8_t *)&classHandle->standardTranscationBuffer;
+ classHandle->standardTranscationBuffer = (uint16_t)(((uint32_t)setup->wIndex & 0xFFU) << 8U);
+ /* The Bit[15~8] is used to save the interface index, and the alternate setting will be saved in Bit[7~0] by
+ * application. */
+ error = USB_DeviceClassCallback(classHandle->handle, (uint32_t)kUSB_DeviceEventGetInterface,
+ &classHandle->standardTranscationBuffer);
+ classHandle->standardTranscationBuffer = USB_SHORT_TO_LITTLE_ENDIAN(classHandle->standardTranscationBuffer);
+ return error;
+}
+
+/*!
+ * @brief Handle set the alternate setting of a interface request.
+ *
+ * This function is used to handle set the alternate setting of a interface request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The request is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9SetInterface(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ uint8_t state = 0U;
+
+ if (((setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) != USB_REQUEST_TYPE_DIR_OUT) ||
+ ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) != USB_REQUEST_TYPE_RECIPIENT_INTERFACE) ||
+ (setup->wLength != 0U))
+ {
+ return kStatus_USB_InvalidRequest;
+ }
+
+ (void)USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if (state != (uint8_t)kUSB_DeviceStateConfigured)
+ {
+ return kStatus_USB_InvalidRequest;
+ }
+ classHandle->standardTranscationBuffer = ((setup->wIndex & 0xFFU) << 8U) | (setup->wValue & 0xFFU);
+ /* Notify the class driver the alternate setting of the interface is changed. */
+ /* The Bit[15~8] is used to save the interface index, and the alternate setting is saved in Bit[7~0]. */
+ (void)USB_DeviceClassEvent(classHandle->handle, kUSB_DeviceClassEventSetInterface,
+ &classHandle->standardTranscationBuffer);
+ /* Notify the application the alternate setting of the interface is changed. */
+ /* The Bit[15~8] is used to save the interface index, and the alternate setting will is saved in Bit[7~0]. */
+ return USB_DeviceClassCallback(classHandle->handle, (uint32_t)kUSB_DeviceEventSetInterface,
+ &classHandle->standardTranscationBuffer);
+}
+
+/*!
+ * @brief Handle get sync frame request.
+ *
+ * This function is used to handle get sync frame request.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @retval kStatus_USB_Success The request is handled successfully.
+ * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state,
+ * or, the request is unsupported.
+ */
+static usb_status_t USB_DeviceCh9SynchFrame(usb_device_common_class_struct_t *classHandle,
+ usb_setup_struct_t *setup,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ usb_status_t error = kStatus_USB_InvalidRequest;
+ uint8_t state = 0U;
+
+ if (((setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) != USB_REQUEST_TYPE_DIR_IN) ||
+ ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) != USB_REQUEST_TYPE_RECIPIENT_ENDPOINT) ||
+ (setup->wValue != 0U) || (setup->wLength != 2U))
+ {
+ return error;
+ }
+
+ (void)USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if (state != (uint8_t)kUSB_DeviceStateConfigured)
+ {
+ return error;
+ }
+ /* Synch frame is not implemented by any MS devices. Expected response from device will be STALL until a device
+ exists that supports this command. At that time this script will need to be updated to support a
+ response other than STALL */
+#if (defined(USB_DEVICE_CONFIG_ROOT2_TEST) && (USB_DEVICE_CONFIG_ROOT2_TEST > 0U))
+ return error;
+#else
+ classHandle->standardTranscationBuffer = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wIndex);
+ /* Get the sync frame value */
+ error =
+ USB_DeviceGetStatus(classHandle->handle, kUSB_DeviceStatusSynchFrame, &classHandle->standardTranscationBuffer);
+ *buffer = (uint8_t *)&classHandle->standardTranscationBuffer;
+ *length = sizeof(classHandle->standardTranscationBuffer);
+ return error;
+#endif
+}
+
+/*!
+ * @brief Send the response to the host.
+ *
+ * This function is used to send the response to the host.
+ *
+ * There are two cases this function will be called.
+ * Case one when a setup packet is received in control endpoint callback function:
+ * 1. If there is not data phase in the setup transfer, the function will prime an IN transfer with the data
+ * length is zero for status phase.
+ * 2. If there is an IN data phase, the function will prime an OUT transfer with the actual length to need to
+ * send for data phase. And then prime an IN transfer with the data length is zero for status phase.
+ * 3. If there is an OUT data phase, the function will prime an IN transfer with the actual length to want to
+ * receive for data phase.
+ *
+ * Case two when is not a setup packet received in control endpoint callback function:
+ * 1. The function will prime an IN transfer with data length is zero for status phase.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param setup The pointer of the setup packet.
+ * @param error The error code returned from the standard request function.
+ * @param stage The stage of the control transfer.
+ * @param buffer It is an out parameter, is used to save the buffer address to response the host's request.
+ * @param length It is an out parameter, the data length.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceControlCallbackFeedback(usb_device_handle handle,
+ usb_setup_struct_t *setup,
+ usb_status_t error,
+ usb_device_control_read_write_sequence_t stage,
+ uint8_t **buffer,
+ uint32_t *length)
+{
+ usb_status_t status;
+
+ if (kStatus_USB_InvalidRequest == error)
+ {
+ /* Stall the control pipe when the request is unsupported. */
+ status = USB_DeviceStallEndpoint(handle, (uint8_t)USB_CONTROL_ENDPOINT);
+ }
+ else
+ {
+ if (*length > setup->wLength)
+ {
+ *length = setup->wLength;
+ }
+
+ if (kStatus_USB_Success == error)
+ {
+ status = USB_DeviceSendRequest(handle, (USB_CONTROL_ENDPOINT), *buffer, *length);
+ }
+ else
+ {
+ status = USB_DeviceSendRequest(handle, (USB_CONTROL_ENDPOINT), (uint8_t *)NULL, 0U);
+ }
+
+ if ((kStatus_USB_Success == status) &&
+ (USB_REQUEST_TYPE_DIR_IN == (setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK)))
+ {
+ status = USB_DeviceRecvRequest(handle, (USB_CONTROL_ENDPOINT), (uint8_t *)NULL, 0U);
+ }
+ }
+
+ return status;
+}
+
+/*!
+ * @brief Control endpoint callback function.
+ *
+ * This callback function is used to notify uplayer the transfser result of a transfer.
+ * This callback pointer is passed when a specified endpoint initialized by calling API USB_DeviceInitEndpoint.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The result of a transfer, includes transfer buffer, transfer length and whether is in setup
+ * phase for control pipe.
+ * @param callbackParam The parameter for this callback. It is same with
+ * usb_device_endpoint_callback_struct_t::callbackParam.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceControlCallback(usb_device_handle handle,
+ usb_device_endpoint_callback_message_struct_t *message,
+ void *callbackParam)
+{
+ usb_setup_struct_t *deviceSetup, *setup;
+ usb_device_common_class_struct_t *classHandle;
+ uint8_t *buffer = (uint8_t *)NULL;
+ uint32_t length = 0U;
+ void *temp;
+ usb_status_t status = kStatus_USB_InvalidRequest;
+ uint8_t state = 0U;
+
+ /* endpoint callback length is USB_CANCELLED_TRANSFER_LENGTH (0xFFFFFFFFU) when transfer is canceled */
+ if ((USB_CANCELLED_TRANSFER_LENGTH == message->length) || (NULL == callbackParam))
+ {
+ return status;
+ }
+
+ classHandle = (usb_device_common_class_struct_t *)callbackParam;
+ temp = (void *)&classHandle->setupBuffer[0];
+ deviceSetup = (usb_setup_struct_t *)temp;
+ (void)USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
+
+ if (0U != message->isSetup)
+ {
+ if ((USB_SETUP_PACKET_SIZE != message->length) || (NULL == message->buffer))
+ {
+ /* If a invalid setup is received, the control pipes should be de-init and init again.
+ * Due to the IP can not meet this require, it is reserved for feature.
+ */
+ /*
+ USB_DeviceDeinitEndpoint(handle,
+ USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT));
+ USB_DeviceDeinitEndpoint(handle,
+ USB_CONTROL_ENDPOINT | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT));
+ USB_DeviceControlPipeInit(handle, callbackParam);
+ */
+ return status;
+ }
+ /* Receive a setup request */
+ temp = (void *)(message->buffer);
+ setup = (usb_setup_struct_t *)temp;
+
+ /* Copy the setup packet to the application buffer */
+ deviceSetup->wValue = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wValue);
+ deviceSetup->wIndex = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wIndex);
+ deviceSetup->wLength = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wLength);
+ deviceSetup->bRequest = setup->bRequest;
+ deviceSetup->bmRequestType = setup->bmRequestType;
+
+ /* Check the invalid value */
+ if ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) > USB_REQUEST_TYPE_RECIPIENT_OTHER)
+ {
+ (void)USB_DeviceControlCallbackFeedback(handle, deviceSetup, kStatus_USB_InvalidRequest,
+ kUSB_DeviceControlPipeSetupStage, NULL, NULL);
+ return status;
+ }
+
+ if ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_MASK) == USB_REQUEST_TYPE_TYPE_STANDARD)
+ {
+ /* Handle the standard request, only handle the request in request array. */
+ if (deviceSetup->bRequest < (sizeof(s_UsbDeviceStandardRequest) / 4U))
+ {
+ if (s_UsbDeviceStandardRequest[deviceSetup->bRequest] != (usb_standard_request_callback_t)NULL)
+ {
+ status =
+ s_UsbDeviceStandardRequest[deviceSetup->bRequest](classHandle, deviceSetup, &buffer, &length);
+ }
+ }
+ }
+ else
+ {
+ if ((0U != deviceSetup->wLength) &&
+ ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_OUT))
+ {
+ /* Class or vendor request with the OUT data phase. */
+ if ((0U != deviceSetup->wLength) &&
+ ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_MASK) == USB_REQUEST_TYPE_TYPE_CLASS))
+ {
+ /* Get data buffer to receive the data from the host. */
+ usb_device_control_request_struct_t controlRequest;
+ controlRequest.buffer = (uint8_t *)NULL;
+ controlRequest.isSetup = 1U;
+ controlRequest.setup = deviceSetup;
+ controlRequest.length = deviceSetup->wLength;
+ status = USB_DeviceClassEvent(handle, kUSB_DeviceClassEventClassRequest, &controlRequest);
+ length = controlRequest.length;
+ buffer = controlRequest.buffer;
+ }
+ else if ((0U != deviceSetup->wLength) &&
+ ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_MASK) == USB_REQUEST_TYPE_TYPE_VENDOR))
+ {
+ /* Get data buffer to receive the data from the host. */
+ usb_device_control_request_struct_t controlRequest;
+ controlRequest.buffer = (uint8_t *)NULL;
+ controlRequest.isSetup = 1U;
+ controlRequest.setup = deviceSetup;
+ controlRequest.length = deviceSetup->wLength;
+ status = USB_DeviceClassCallback(handle, (uint32_t)kUSB_DeviceEventVendorRequest, &controlRequest);
+ length = controlRequest.length;
+ buffer = controlRequest.buffer;
+ }
+ else
+ {
+ /*no action*/
+ }
+ if (kStatus_USB_Success == status)
+ {
+ /* Prime an OUT transfer */
+ if (length > deviceSetup->wLength)
+ {
+ length = deviceSetup->wLength;
+ }
+ status = USB_DeviceRecvRequest(handle, USB_CONTROL_ENDPOINT, buffer, length);
+ return status;
+ }
+ else
+ {
+ /* Other error codes, will stall control endpoint */
+ status = kStatus_USB_InvalidRequest;
+ }
+ }
+ else
+ {
+ /* Class or vendor request with the IN data phase. */
+ if (((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_MASK) == USB_REQUEST_TYPE_TYPE_CLASS))
+ {
+ /* Get data buffer to response the host. */
+ usb_device_control_request_struct_t controlRequest;
+ controlRequest.buffer = (uint8_t *)NULL;
+ controlRequest.isSetup = 1U;
+ controlRequest.setup = deviceSetup;
+ controlRequest.length = deviceSetup->wLength;
+ status = USB_DeviceClassEvent(handle, kUSB_DeviceClassEventClassRequest, &controlRequest);
+ length = controlRequest.length;
+ buffer = controlRequest.buffer;
+ }
+ else if (((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_MASK) == USB_REQUEST_TYPE_TYPE_VENDOR))
+ {
+ /* Get data buffer to response the host. */
+ usb_device_control_request_struct_t controlRequest;
+ controlRequest.buffer = (uint8_t *)NULL;
+ controlRequest.isSetup = 1U;
+ controlRequest.setup = deviceSetup;
+ controlRequest.length = deviceSetup->wLength;
+ status = USB_DeviceClassCallback(handle, (uint32_t)kUSB_DeviceEventVendorRequest, &controlRequest);
+ length = controlRequest.length;
+ buffer = controlRequest.buffer;
+ }
+ else
+ {
+ /*no action*/
+ }
+ }
+ }
+ /* Buffer that is equal to NULL means the application or classs driver does not prepare a buffer for
+ sending or receiving the data, so control endpoint will be stalled here. */
+ if ((0U != length) && (NULL == buffer))
+ {
+ status = kStatus_USB_InvalidRequest;
+ }
+ /* Send the response to the host. */
+ status = USB_DeviceControlCallbackFeedback(handle, deviceSetup, status, kUSB_DeviceControlPipeSetupStage,
+ &buffer, &length);
+ }
+ else if ((uint8_t)kUSB_DeviceStateAddressing == state)
+ {
+ if (USB_REQUEST_STANDARD_SET_ADDRESS == deviceSetup->bRequest)
+ {
+ /* Set the device address to controller. */
+ status = s_UsbDeviceStandardRequest[deviceSetup->bRequest](classHandle, deviceSetup, &buffer, &length);
+ }
+ }
+#if ((defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)) || \
+ (defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) && \
+ (defined(USB_DEVICE_CONFIG_USB20_TEST_MODE) && (USB_DEVICE_CONFIG_USB20_TEST_MODE > 0U))
+ else if ((uint8_t)kUSB_DeviceStateTestMode == state)
+ {
+ uint8_t portTestControl = (uint8_t)(deviceSetup->wIndex >> 8);
+ /* Set the controller.into test mode. */
+ status = USB_DeviceSetStatus(handle, kUSB_DeviceStatusTestMode, &portTestControl);
+ }
+#endif
+ else if ((0U != message->length) && (0U != deviceSetup->wLength) &&
+ ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_OUT))
+ {
+ if (((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_MASK) == USB_REQUEST_TYPE_TYPE_CLASS))
+ {
+ /* Data received in OUT phase, and notify the class driver. */
+ usb_device_control_request_struct_t controlRequest;
+ controlRequest.buffer = message->buffer;
+ controlRequest.isSetup = 0U;
+ controlRequest.setup = deviceSetup;
+ controlRequest.length = message->length;
+ status = USB_DeviceClassEvent(handle, kUSB_DeviceClassEventClassRequest, &controlRequest);
+ }
+ else if (((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_MASK) == USB_REQUEST_TYPE_TYPE_VENDOR))
+ {
+ /* Data received in OUT phase, and notify the application. */
+ usb_device_control_request_struct_t controlRequest;
+ controlRequest.buffer = message->buffer;
+ controlRequest.isSetup = 0U;
+ controlRequest.setup = deviceSetup;
+ controlRequest.length = message->length;
+ status = USB_DeviceClassCallback(handle, (uint32_t)kUSB_DeviceEventVendorRequest, &controlRequest);
+ }
+ else
+ {
+ /*no action*/
+ }
+ /* Send the response to the host. */
+ status = USB_DeviceControlCallbackFeedback(handle, deviceSetup, status, kUSB_DeviceControlPipeDataStage,
+ &buffer, &length);
+ }
+ else
+ {
+ /*no action*/
+ }
+ return status;
+}
+
+/*!
+ * @brief Control endpoint initialization function.
+ *
+ * This callback function is used to initialize the control pipes.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param param The up layer handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceControlPipeInit(usb_device_handle handle, void *param)
+{
+ usb_device_endpoint_init_struct_t epInitStruct;
+ usb_device_endpoint_callback_struct_t epCallback;
+ usb_status_t status;
+
+ epCallback.callbackFn = USB_DeviceControlCallback;
+ epCallback.callbackParam = param;
+
+ epInitStruct.zlt = 1U;
+ epInitStruct.transferType = USB_ENDPOINT_CONTROL;
+ epInitStruct.interval = 0;
+ epInitStruct.endpointAddress = USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT);
+ epInitStruct.maxPacketSize = USB_CONTROL_MAX_PACKET_SIZE;
+ /* Initialize the control IN pipe */
+ status = USB_DeviceInitEndpoint(handle, &epInitStruct, &epCallback);
+
+ if (kStatus_USB_Success != status)
+ {
+ return status;
+ }
+ epInitStruct.endpointAddress = USB_CONTROL_ENDPOINT | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT);
+ /* Initialize the control OUT pipe */
+ status = USB_DeviceInitEndpoint(handle, &epInitStruct, &epCallback);
+
+ if (kStatus_USB_Success != status)
+ {
+ (void)USB_DeviceDeinitEndpoint(
+ handle, USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT));
+ return status;
+ }
+
+ return kStatus_USB_Success;
+}
+#endif /* USB_DEVICE_CONFIG_NUM */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_ch9.h b/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_ch9.h
new file mode 100644
index 000000000..e26d357a3
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_ch9.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __USB_DEVICE_CH9_H__
+#define __USB_DEVICE_CH9_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!
+ * @addtogroup usb_device_ch9
+ * @{
+ */
+/*! @brief Defines USB device status size when the host request to get device status */
+#define USB_DEVICE_STATUS_SIZE (0x02U)
+
+/*! @brief Defines USB device interface status size when the host request to get interface status */
+#define USB_INTERFACE_STATUS_SIZE (0x02U)
+
+/*! @brief Defines USB device endpoint status size when the host request to get endpoint status */
+#define USB_ENDPOINT_STATUS_SIZE (0x02U)
+
+/*! @brief Defines USB device configuration size when the host request to get current configuration */
+#define USB_CONFIGURE_SIZE (0X01U)
+
+/*! @brief Defines USB device interface alternate setting size when the host request to get interface alternate setting
+ */
+#define USB_INTERFACE_SIZE (0X01U)
+
+/*! @brief Defines USB device status mask */
+#define USB_GET_STATUS_DEVICE_MASK (0x03U)
+
+/*! @brief Defines USB device interface status mask */
+#define USB_GET_STATUS_INTERFACE_MASK (0x03U)
+
+/*! @brief Defines USB device endpoint status mask */
+#define USB_GET_STATUS_ENDPOINT_MASK (0x03U)
+
+/*! @brief Control read and write sequence */
+typedef enum _usb_device_control_read_write_sequence
+{
+ kUSB_DeviceControlPipeSetupStage = 0U, /*!< Setup stage */
+ kUSB_DeviceControlPipeDataStage, /*!< Data stage */
+ kUSB_DeviceControlPipeStatusStage, /*!< status stage */
+} usb_device_control_read_write_sequence_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Initializes the control pipes.
+ *
+ * The function is used to initialize the control pipes. This function should be called when event
+ * kUSB_DeviceEventBusReset is received.
+ *
+ * @param[in] handle The device handle.
+ * @param[in] param The event parameter.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+extern usb_status_t USB_DeviceControlPipeInit(usb_device_handle handle, void *param);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __USB_DEVICE_CH9_H__ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_dci.c b/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_dci.c
new file mode 100644
index 000000000..4bd791039
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_dci.c
@@ -0,0 +1,1399 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2017,2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "usb_device_config.h"
+#include "usb.h"
+
+#include "usb_device.h"
+#include "usb_device_dci.h"
+
+#include "fsl_device_registers.h"
+
+#if ((defined(USB_DEVICE_CONFIG_NUM)) && (USB_DEVICE_CONFIG_NUM > 0U))
+
+#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
+#include "usb_device_khci.h"
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
+#include "usb_device_ehci.h"
+#endif
+
+#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \
+ ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)))
+#include "usb_device_lpcip3511.h"
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_DWC3)) && (USB_DEVICE_CONFIG_DWC3 > 0U))
+#include "usb_device_dwc3.h"
+#endif
+
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
+#include "fsl_cache.h"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "middleware.usb.device_stack"
+#endif
+
+#if defined __CORTEX_M && (__CORTEX_M == 7U)
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
+#warning USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE is not supported.
+#endif
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static usb_status_t USB_DeviceAllocateHandle(uint8_t controllerId, usb_device_struct_t **handle);
+static usb_status_t USB_DeviceFreeHandle(usb_device_struct_t *handle);
+static usb_status_t USB_DeviceGetControllerInterface(
+ uint8_t controllerId, const usb_device_controller_interface_struct_t **controllerInterface);
+static usb_status_t USB_DeviceTransfer(usb_device_handle handle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length);
+static usb_status_t USB_DeviceControl(usb_device_handle handle, usb_device_control_type_t type, void *param);
+static usb_status_t USB_DeviceResetNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message);
+#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+static usb_status_t USB_DeviceSuspendNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message);
+static usb_status_t USB_DeviceResumeNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message);
+#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U))
+static usb_status_t USB_DeviceSleepNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message);
+
+#endif
+#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */
+#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U))
+static usb_status_t USB_DeviceDetachNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message);
+static usb_status_t USB_DeviceAttachNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message);
+#endif
+static usb_status_t USB_DeviceNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+USB_GLOBAL static usb_device_struct_t s_UsbDevice[USB_DEVICE_CONFIG_NUM];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Allocate a device handle.
+ *
+ * This function allocates a device handle.
+ *
+ * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t.
+ * @param handle It is out parameter, is used to return pointer of the device handle to the caller.
+ *
+ * @retval kStatus_USB_Success Get a device handle successfully.
+ * @retval kStatus_USB_Busy Cannot allocate a device handle.
+ * @retval kStatus_USB_Error The device has been initialized.
+ */
+static usb_status_t USB_DeviceAllocateHandle(uint8_t controllerId, usb_device_struct_t **handle)
+{
+ uint32_t count;
+ OSA_SR_ALLOC();
+
+ OSA_ENTER_CRITICAL();
+ /* Check the controller is initialized or not. */
+ for (count = 0U; count < USB_DEVICE_CONFIG_NUM; count++)
+ {
+ if ((NULL != s_UsbDevice[count].controllerHandle) && (controllerId == s_UsbDevice[count].controllerId))
+ {
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_Error;
+ }
+ }
+ /* Get a free device handle. */
+ for (count = 0U; count < USB_DEVICE_CONFIG_NUM; count++)
+ {
+ if (NULL == s_UsbDevice[count].controllerHandle)
+ {
+ s_UsbDevice[count].controllerId = controllerId;
+ *handle = &s_UsbDevice[count];
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_Success;
+ }
+ }
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_Busy;
+}
+
+/*!
+ * @brief Free a device handle.
+ *
+ * This function frees a device handle.
+ *
+ * @param handle The device handle.
+ *
+ * @retval kStatus_USB_Success Free device handle successfully.
+ */
+static usb_status_t USB_DeviceFreeHandle(usb_device_struct_t *handle)
+{
+ OSA_SR_ALLOC();
+
+ OSA_ENTER_CRITICAL();
+ handle->controllerHandle = NULL;
+ handle->controllerId = 0U;
+ OSA_EXIT_CRITICAL();
+ return kStatus_USB_Success;
+}
+
+#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
+/* KHCI device driver interface */
+static const usb_device_controller_interface_struct_t s_UsbDeviceKhciInterface = {
+ USB_DeviceKhciInit, USB_DeviceKhciDeinit, USB_DeviceKhciSend,
+ USB_DeviceKhciRecv, USB_DeviceKhciCancel, USB_DeviceKhciControl};
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
+/* EHCI device driver interface */
+static const usb_device_controller_interface_struct_t s_UsbDeviceEhciInterface = {
+ USB_DeviceEhciInit, USB_DeviceEhciDeinit, USB_DeviceEhciSend,
+ USB_DeviceEhciRecv, USB_DeviceEhciCancel, USB_DeviceEhciControl};
+#endif
+
+#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \
+ ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)))
+/* EHCI device driver interface */
+static const usb_device_controller_interface_struct_t s_UsbDeviceLpc3511IpInterface = {
+ USB_DeviceLpc3511IpInit, USB_DeviceLpc3511IpDeinit, USB_DeviceLpc3511IpSend,
+ USB_DeviceLpc3511IpRecv, USB_DeviceLpc3511IpCancel, USB_DeviceLpc3511IpControl};
+#endif
+
+#if ((defined(USB_DEVICE_CONFIG_DWC3)) && (USB_DEVICE_CONFIG_DWC3 > 0U))
+/* EHCI device driver interface */
+static const usb_device_controller_interface_struct_t s_UsbDeviceDwc3Interface = {
+ USB_DeviceDwc3Init, USB_DeviceDwc3Deinit, USB_DeviceDwc3Send,
+ USB_DeviceDwc3Recv, USB_DeviceDwc3Cancel, USB_DeviceDwc3Control};
+#endif
+
+/*!
+ * @brief Get the controller interface handle.
+ *
+ * This function is used to get the controller interface handle.
+ *
+ * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t.
+ * @param controllerInterface It is out parameter, is used to return pointer of the device controller handle to the
+ * caller.
+ *
+ * @retval kStatus_USB_Success Get a device handle successfully.
+ * @retval kStatus_USB_ControllerNotFound The controller id is invalid.
+ */
+static usb_status_t USB_DeviceGetControllerInterface(
+ uint8_t controllerId, const usb_device_controller_interface_struct_t **controllerInterface)
+{
+ usb_status_t error = kStatus_USB_ControllerNotFound;
+ usb_controller_index_t controlerIndex = (usb_controller_index_t)controllerId;
+
+#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U))
+ /* Get the KHCI controller driver interface */
+ if ((kUSB_ControllerKhci0 == controlerIndex) || (kUSB_ControllerKhci1 == controlerIndex))
+ {
+ *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceKhciInterface;
+ error = kStatus_USB_Success;
+ }
+#endif
+#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U))
+ /* Get the EHCI controller driver interface */
+ if ((kUSB_ControllerEhci0 == controlerIndex) || (kUSB_ControllerEhci1 == controlerIndex))
+ {
+ *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceEhciInterface;
+ error = kStatus_USB_Success;
+ }
+#endif
+#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \
+ ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)))
+ /* Get the EHCI controller driver interface */
+ if ((kUSB_ControllerLpcIp3511Fs0 == controlerIndex) || (kUSB_ControllerLpcIp3511Fs1 == controlerIndex) ||
+ (kUSB_ControllerLpcIp3511Hs0 == controlerIndex) || (kUSB_ControllerLpcIp3511Hs1 == controlerIndex))
+ {
+ *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceLpc3511IpInterface;
+ error = kStatus_USB_Success;
+ }
+#endif
+#if ((defined(USB_DEVICE_CONFIG_DWC3)) && (USB_DEVICE_CONFIG_DWC3 > 0U))
+ /* Get the EHCI controller driver interface */
+ if ((kUSB_ControllerDwc30 == controlerIndex) || (kUSB_ControllerDwc31 == controlerIndex))
+ {
+ *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceDwc3Interface;
+ error = kStatus_USB_Success;
+ }
+#endif
+
+ return error;
+}
+
+/*!
+ * @brief Start a new transfer.
+ *
+ * This function is used to start a new transfer.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param endpointAddress Endpoint address. Bit7 is direction, 0U - USB_OUT, 1U - USB_IN.
+ * @param buffer The memory address to be transferred, or the memory address to hold the data need to be
+ * sent.
+ * @param length The length of the data.
+ *
+ * @retval kStatus_USB_Success Get a device handle successfully.
+ * @retval kStatus_USB_InvalidHandle The device handle is invalid.
+ * @retval kStatus_USB_ControllerNotFound The controller interface is not found.
+ * @retval kStatus_USB_Error The device is doing reset.
+ */
+static usb_status_t USB_DeviceTransfer(usb_device_handle handle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle;
+ usb_status_t status;
+ uint8_t endpoint = endpointAddress & USB_ENDPOINT_NUMBER_MASK;
+ uint8_t direction = (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT;
+ OSA_SR_ALLOC();
+
+ if (NULL == deviceHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ if (NULL != deviceHandle->controllerInterface)
+ {
+ if (0U != deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy)
+ {
+ return kStatus_USB_Busy;
+ }
+ OSA_ENTER_CRITICAL();
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 1U;
+ OSA_EXIT_CRITICAL();
+ if (0U != (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK))
+ {
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
+ if (0U != length)
+ {
+ DCACHE_CleanByRange((uint32_t)buffer, length);
+ }
+#endif
+ /* Call the controller send interface, the callbackFn is initialized in
+ USB_DeviceGetControllerInterface */
+ status = deviceHandle->controllerInterface->deviceSend(deviceHandle->controllerHandle, endpointAddress,
+ buffer, length);
+ }
+ else
+ {
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
+ if (length)
+ {
+ DCACHE_CleanInvalidateByRange((uint32_t)buffer, length);
+ }
+#endif
+ /* Call the controller receive interface, the callbackFn is initialized in
+ USB_DeviceGetControllerInterface */
+ status = deviceHandle->controllerInterface->deviceRecv(deviceHandle->controllerHandle, endpointAddress,
+ buffer, length);
+ }
+ if (kStatus_USB_Success != status)
+ {
+ OSA_ENTER_CRITICAL();
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U;
+ OSA_EXIT_CRITICAL();
+ }
+ }
+ else
+ {
+ status = kStatus_USB_ControllerNotFound;
+ }
+ return status;
+}
+
+/*!
+ * @brief Control the status of the selected item.
+ *
+ * This function is used to control the status of the selected item..
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param type The control type, please refer to the enumeration usb_device_control_type_t.
+ * @param param The param type is determined by the selected item.
+ *
+ * @retval kStatus_USB_Success Get a device handle successfully.
+ * @retval kStatus_USB_InvalidHandle The device handle is invalid.
+ * @retval kStatus_USB_ControllerNotFound The controller interface is not found.
+ * @retval kStatus_USB_Error Unsupported type.
+ * Or, the param is NULL pointer.
+ */
+static usb_status_t USB_DeviceControl(usb_device_handle handle, usb_device_control_type_t type, void *param)
+{
+ usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle;
+ usb_status_t status;
+
+ if (NULL == deviceHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ if (NULL != deviceHandle->controllerInterface)
+ {
+ /* Call the controller control interface. the controllerInterface is initialized in
+ USB_DeviceGetControllerInterface */
+ status = deviceHandle->controllerInterface->deviceControl(deviceHandle->controllerHandle, type, param);
+ }
+ else
+ {
+ status = kStatus_USB_ControllerNotFound;
+ }
+ return status;
+}
+
+/*!
+ * @brief Handle the reset notification.
+ *
+ * This function is used to handle the reset notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @retval kStatus_USB_Success Get a device handle successfully.
+ */
+static usb_status_t USB_DeviceResetNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ uint32_t count;
+
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ OSA_SR_ALLOC();
+#endif
+
+ handle->isResetting = 1U;
+
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ /* Clear remote wakeup feature */
+ handle->remotewakeup = 0U;
+#endif
+
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ OSA_ENTER_CRITICAL();
+ handle->epCallbackDirectly = 1U;
+ OSA_EXIT_CRITICAL();
+#endif
+ /* Set the controller to default status. */
+ (void)USB_DeviceControl(handle, kUSB_DeviceControlSetDefaultStatus, NULL);
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ OSA_ENTER_CRITICAL();
+ handle->epCallbackDirectly = 0U;
+ OSA_EXIT_CRITICAL();
+#endif
+
+ handle->state = (uint8_t)kUSB_DeviceStateDefault;
+ handle->deviceAddress = 0U;
+
+ for (count = 0U; count < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); count++)
+ {
+ handle->epCallback[count].callbackFn = (usb_device_endpoint_callback_t)NULL;
+ handle->epCallback[count].callbackParam = NULL;
+ handle->epCallback[count].isBusy = 0U;
+ }
+
+ /* Call device callback to notify the application that the USB bus reset signal detected.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ (void)handle->deviceCallback(handle, kUSB_DeviceEventBusReset, NULL);
+
+ handle->isResetting = 0U;
+ return kStatus_USB_Success;
+}
+
+#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+/*!
+ * @brief Handle the suspend notification.
+ *
+ * This function is used to handle the suspend notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceSuspendNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the USB bus suspend signal detected.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+
+ return handle->deviceCallback(handle, kUSB_DeviceEventSuspend, NULL);
+}
+
+/*!
+ * @brief Handle the resume notification.
+ *
+ * This function is used to handle the resume notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceResumeNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the USB bus resume signal detected.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventResume, NULL);
+}
+#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U))
+/*!
+ * @brief Handle the suspend notification.
+ *
+ * This function is used to handle the suspend notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceSleepNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the USB bus suspend signal detected.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+
+ (void)USB_DeviceSetStatus(handle, kUSB_DeviceStatusRemoteWakeup, message->buffer);
+
+ return handle->deviceCallback(handle, kUSB_DeviceEventSleeped, NULL);
+}
+#endif
+
+#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */
+
+#if (defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U))
+static usb_status_t USB_DeviceErrorNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the USB bus error signal detected.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventError, NULL);
+}
+#endif /* USB_DEVICE_CONFIG_ERROR_HANDLING */
+
+#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U))
+/*!
+ * @brief Handle the detach notification.
+ *
+ * This function is used to handle the detach notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceDetachNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the device is disconnected from a host.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventDetach, NULL);
+}
+
+/*!
+ * @brief Handle the attach notification.
+ *
+ * This function is used to handle the attach notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceAttachNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the device is connected to a host.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventAttach, NULL);
+}
+#endif
+
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U))
+
+/*!
+ * @brief Handle the DCP detection finished notification.
+ *
+ * This function is used to notify detection notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+
+static usb_status_t USB_DeviceDcdDetectFinihsedNotification(usb_device_struct_t *handle,
+ usb_device_callback_message_struct_t *message)
+{
+ /* Call device callback to notify the application that the DCP facility is detected.
+ the deviceCallback is the second parameter of USB_DeviceInit */
+ return handle->deviceCallback(handle, kUSB_DeviceEventDcdDetectionfinished, message->buffer);
+}
+#endif
+
+/*!
+ * @brief Handle the attach notification.
+ *
+ * This function is used to handle the attach notification.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+static usb_status_t USB_DeviceNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message)
+{
+ uint8_t endpoint = message->code & USB_ENDPOINT_NUMBER_MASK;
+ uint8_t direction = (message->code & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT;
+ usb_status_t status = kStatus_USB_Error;
+ usb_device_notification_t deviceNotify = (usb_device_notification_t)message->code;
+ switch (deviceNotify)
+ {
+ case kUSB_DeviceNotifyBusReset:
+ status = USB_DeviceResetNotification(handle, message);
+ break;
+#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
+ case kUSB_DeviceNotifySuspend:
+ status = USB_DeviceSuspendNotification(handle, message);
+ break;
+ case kUSB_DeviceNotifyResume:
+ status = USB_DeviceResumeNotification(handle, message);
+ break;
+#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U))
+ case kUSB_DeviceNotifyLPMSleep:
+ status = USB_DeviceSleepNotification(handle, message);
+ break;
+#endif
+#endif
+
+#if (defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U))
+ case kUSB_DeviceNotifyError:
+ status = USB_DeviceErrorNotification(handle, message);
+ break;
+#endif
+
+#if USB_DEVICE_CONFIG_DETACH_ENABLE
+ case kUSB_DeviceNotifyDetach:
+ status = USB_DeviceDetachNotification(handle, message);
+ break;
+ case kUSB_DeviceNotifyAttach:
+ status = USB_DeviceAttachNotification(handle, message);
+ break;
+#endif
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U))
+ case kUSB_DeviceNotifyDcdDetectFinished:
+ status = USB_DeviceDcdDetectFinihsedNotification(handle, message);
+ break;
+#endif
+
+ default:
+ if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS)
+ {
+ if (NULL != handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn)
+ {
+ usb_device_endpoint_callback_message_struct_t endpointCallbackMessage;
+ endpointCallbackMessage.buffer = message->buffer;
+ endpointCallbackMessage.length = message->length;
+ endpointCallbackMessage.isSetup = message->isSetup;
+ if (0U != message->isSetup)
+ {
+ handle->epCallback[0].isBusy = 0U;
+ handle->epCallback[1].isBusy = 0U;
+ }
+ else
+ {
+ handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U;
+ }
+ /* Call endpoint callback, callbackFn is in the third parameter of USB_DeviceInitEndpoint */
+ status = handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn(
+ handle, &endpointCallbackMessage,
+ handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam);
+ }
+ }
+ break;
+ }
+ return status;
+}
+
+/*!
+ * @brief Notify the device that the controller status changed.
+ *
+ * This function is used to notify the device that the controller status changed.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceNotificationTrigger(void *handle, void *msg)
+{
+ usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle;
+ usb_device_callback_message_struct_t *message = (usb_device_callback_message_struct_t *)msg;
+
+ if ((NULL == msg) || (NULL == handle))
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ /* The device callback is invalid or not. */
+ if (NULL == deviceHandle->deviceCallback)
+ {
+ return kStatus_USB_Error;
+ }
+
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ if (0U != deviceHandle->epCallbackDirectly)
+ {
+ if ((0U != (message->code & USB_ENDPOINT_NUMBER_MASK)) && (0U == (message->code & 0x70U)))
+ {
+ return USB_DeviceNotification(deviceHandle, message);
+ }
+ }
+
+ /* Add the message to message queue when the device task is enabled. */
+ if (KOSA_StatusSuccess != OSA_MsgQPut(deviceHandle->notificationQueue, (osa_msg_handle_t)message))
+ {
+ return kStatus_USB_Busy;
+ }
+ return kStatus_USB_Success;
+#else
+ /* Handle the notification by calling USB_DeviceNotification. */
+ return USB_DeviceNotification(deviceHandle, message);
+#endif
+}
+
+/*!
+ * @brief Initialize the USB device stack.
+ *
+ * This function initializes the USB device module specified by the controllerId.
+ *
+ * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t.
+ * @param deviceCallback Function pointer of the device callback.
+ * @param handle It is out parameter, is used to return pointer of the device handle to the caller.
+ *
+ * @retval kStatus_USB_Success The device is initialized successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer.
+ * @retval kStatus_USB_Busy Cannot allocate a device handle.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller id.
+ * @retval kStatus_USB_InvalidControllerInterface The controller driver interfaces is invaild, There is an empty
+ * interface entity.
+ * @retval kStatus_USB_Error The macro USB_DEVICE_CONFIG_ENDPOINTS is more than IP's endpoint number.
+ * Or, the device has been initialized.
+ * Or, the message queue is created failed.
+ */
+usb_status_t USB_DeviceInit(uint8_t controllerId, usb_device_callback_t deviceCallback, usb_device_handle *handle)
+{
+ usb_device_struct_t *deviceHandle = NULL;
+ usb_status_t error;
+ uint32_t count;
+
+ if (NULL == handle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ /* Allocate a device handle by using the controller id. */
+ error = USB_DeviceAllocateHandle(controllerId, &deviceHandle);
+
+ if (kStatus_USB_Success != error)
+ {
+ return error;
+ }
+
+ /* Save the device callback */
+ deviceHandle->deviceCallback = deviceCallback;
+ /* Save the controller id */
+ deviceHandle->controllerId = controllerId;
+ /* Clear the device address */
+ deviceHandle->deviceAddress = 0U;
+ /* Clear the device reset state */
+ deviceHandle->isResetting = 0U;
+
+ /* Initialize the endpoints */
+ for (count = 0U; count < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); count++)
+ {
+ deviceHandle->epCallback[count].callbackFn = (usb_device_endpoint_callback_t)NULL;
+ deviceHandle->epCallback[count].callbackParam = NULL;
+ deviceHandle->epCallback[count].isBusy = 0U;
+ }
+
+ /* Get the controller interface according to the controller id */
+ error = USB_DeviceGetControllerInterface(controllerId, &deviceHandle->controllerInterface);
+ if (kStatus_USB_Success != error)
+ {
+ (void)USB_DeviceFreeHandle(deviceHandle);
+ return error;
+ }
+ if (NULL == deviceHandle->controllerInterface)
+ {
+ (void)USB_DeviceFreeHandle(deviceHandle);
+ return kStatus_USB_ControllerNotFound;
+ }
+ if (((usb_device_controller_init_t)NULL == deviceHandle->controllerInterface->deviceInit) ||
+ ((usb_device_controller_deinit_t)NULL == deviceHandle->controllerInterface->deviceDeinit) ||
+ ((usb_device_controller_send_t)NULL == deviceHandle->controllerInterface->deviceSend) ||
+ ((usb_device_controller_recv_t)NULL == deviceHandle->controllerInterface->deviceRecv) ||
+ ((usb_device_controller_cancel_t)NULL == deviceHandle->controllerInterface->deviceCancel) ||
+ ((usb_device_controller_control_t)NULL == deviceHandle->controllerInterface->deviceControl))
+ {
+ (void)USB_DeviceFreeHandle(deviceHandle);
+ return kStatus_USB_InvalidControllerInterface;
+ }
+
+#if USB_DEVICE_CONFIG_USE_TASK
+ /* Create a message queue when the device handle is enabled. */
+ deviceHandle->notificationQueue = (osa_msgq_handle_t)&deviceHandle->notificationQueueBuffer[0];
+ if (KOSA_StatusSuccess !=
+ OSA_MsgQCreate(deviceHandle->notificationQueue, USB_DEVICE_CONFIG_MAX_MESSAGES, USB_DEVICE_MESSAGES_SIZE))
+ {
+ (void)USB_DeviceDeinit(deviceHandle);
+ return kStatus_USB_Error;
+ }
+#endif
+
+ *handle = deviceHandle;
+
+ /* Initialize the controller, the callbackFn is initialized in USB_DeviceGetControllerInterface */
+ error = deviceHandle->controllerInterface->deviceInit(controllerId, deviceHandle, &deviceHandle->controllerHandle);
+ if (kStatus_USB_Success != error)
+ {
+ (void)USB_DeviceDeinit(deviceHandle);
+ *handle = NULL;
+ return error;
+ }
+ /* Set the device to deafult state */
+ deviceHandle->state = (uint8_t)kUSB_DeviceStateDefault;
+
+ return error;
+}
+
+/*!
+ * @brief Enable the device functionality.
+ *
+ * The function enables the device functionality, so that the device can be recognized by the host when the device
+ * detects that it has been connected to a host.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device is run successfully.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid.
+ *
+ */
+usb_status_t USB_DeviceRun(usb_device_handle handle)
+{
+ return USB_DeviceControl(handle, kUSB_DeviceControlRun, NULL);
+}
+/*!
+ * @brief Disable the device functionality.
+ *
+ * The function disables the device functionality, after this function called, even the device is detached to the host,
+ * and the device can't work.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device is stopped successfully.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid.
+ */
+usb_status_t USB_DeviceStop(usb_device_handle handle)
+{
+ return USB_DeviceControl(handle, kUSB_DeviceControlStop, NULL);
+}
+/*!
+ * @brief De-initialize the device controller.
+ *
+ * The function de-initializes the device controller specified by the handle.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device is stopped successfully.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid.
+ */
+usb_status_t USB_DeviceDeinit(usb_device_handle handle)
+{
+ usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle;
+
+ if (NULL == deviceHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+ /* De-initialize the controller */
+ if (NULL != deviceHandle->controllerInterface)
+ {
+ /* the callbackFn is initialized in USB_DeviceGetControllerInterface */
+ (void)deviceHandle->controllerInterface->deviceDeinit(deviceHandle->controllerHandle);
+ deviceHandle->controllerInterface = (usb_device_controller_interface_struct_t *)NULL;
+ }
+
+#if USB_DEVICE_CONFIG_USE_TASK
+ /* Destroy the message queue. */
+ if (NULL != deviceHandle->notificationQueue)
+ {
+ (void)OSA_MsgQDestroy(deviceHandle->notificationQueue);
+ deviceHandle->notificationQueue = NULL;
+ }
+#endif
+
+ /* Free the device handle. */
+ (void)USB_DeviceFreeHandle(deviceHandle);
+ return kStatus_USB_Success;
+}
+
+/*!
+ * @brief Send data through a specified endpoint.
+ *
+ * The function is used to send data through a specified endpoint.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param endpointAddress Endpoint index.
+ * @param buffer The memory address to hold the data need to be sent.
+ * @param length The data length need to be sent.
+ *
+ * @retval kStatus_USB_Success The send request is sent successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_Busy Cannot allocate dtds for current transfer in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error The device is doing reset.
+ *
+ * @note The return value just means if the sending request is successful or not; the transfer done is notified by the
+ * corresponding callback function.
+ * Currently, only one transfer request can be supported for one specific endpoint.
+ * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application
+ * should implement a queue in the application level.
+ * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint
+ * callback).
+ */
+usb_status_t USB_DeviceSendRequest(usb_device_handle handle, uint8_t endpointAddress, uint8_t *buffer, uint32_t length)
+{
+ return USB_DeviceTransfer(
+ handle,
+ (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT),
+ buffer, length);
+}
+
+/*!
+ * @brief Receive data through a specified endpoint.
+ *
+ * The function is used to receive data through a specified endpoint.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param endpointAddress Endpoint index.
+ * @param buffer The memory address to save the received data.
+ * @param length The data length want to be received.
+ *
+ * @retval kStatus_USB_Success The receive request is sent successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_Busy Cannot allocate dtds for current transfer in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error The device is doing reset.
+ *
+ * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the
+ * corresponding callback function.
+ * Currently, only one transfer request can be supported for one specific endpoint.
+ * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application
+ * should implement a queue in the application level.
+ * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint
+ * callback).
+ */
+usb_status_t USB_DeviceRecvRequest(usb_device_handle handle, uint8_t endpointAddress, uint8_t *buffer, uint32_t length)
+{
+ return USB_DeviceTransfer(
+ handle,
+ (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT),
+ buffer, length);
+}
+
+/*!
+ * @brief Cancel the pending transfer in a specified endpoint.
+ *
+ * The function is used to cancel the pending transfer in a specified endpoint.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The transfer is cancelled.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+usb_status_t USB_DeviceCancel(usb_device_handle handle, uint8_t endpointAddress)
+{
+ usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle;
+ usb_status_t status;
+
+ if (NULL == deviceHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ if (NULL != deviceHandle->controllerInterface)
+ {
+ /* the callbackFn is initialized in USB_DeviceGetControllerInterface */
+ status = deviceHandle->controllerInterface->deviceCancel(deviceHandle->controllerHandle, endpointAddress);
+ }
+ else
+ {
+ status = kStatus_USB_ControllerNotFound;
+ }
+ return status;
+}
+
+/*!
+ * @brief Initialize a specified endpoint.
+ *
+ * The function is used to initialize a specified endpoint and the corresponding endpoint callback is also initialized.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param epInit Endpoint initialization structure. Please refer to the structure usb_device_endpoint_init_struct_t.
+ * @param epCallback Endpoint callback structure. Please refer to the structure
+ * usb_device_endpoint_callback_struct_t.
+ *
+ * @retval kStatus_USB_Success The endpoint is initialized successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The epInit or epCallback is NULL pointer. Or the endpoint number is
+ * not less than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+usb_status_t USB_DeviceInitEndpoint(usb_device_handle handle,
+ usb_device_endpoint_init_struct_t *epInit,
+ usb_device_endpoint_callback_struct_t *epCallback)
+{
+ usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle;
+ uint8_t endpoint;
+ uint8_t direction;
+
+ if (NULL == deviceHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ if ((NULL == epInit) || (NULL == epCallback))
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+
+ endpoint = epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK;
+ direction = (epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT;
+
+ if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS)
+ {
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn = epCallback->callbackFn;
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam =
+ epCallback->callbackParam;
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U;
+ }
+ else
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+ return USB_DeviceControl(handle, kUSB_DeviceControlEndpointInit, epInit);
+}
+
+/*!
+ * @brief De-initizlize a specified endpoint.
+ *
+ * The function is used to de-initizlize a specified endpoint.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The endpoint is de-initialized successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+usb_status_t USB_DeviceDeinitEndpoint(usb_device_handle handle, uint8_t endpointAddress)
+{
+ usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle;
+ uint8_t endpoint = endpointAddress & USB_ENDPOINT_NUMBER_MASK;
+ uint8_t direction = (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >>
+ USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT;
+ usb_status_t status;
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ OSA_SR_ALLOC();
+#endif
+
+ if (NULL == deviceHandle)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ OSA_ENTER_CRITICAL();
+ deviceHandle->epCallbackDirectly = 1U;
+ OSA_EXIT_CRITICAL();
+#endif
+ status = USB_DeviceControl(handle, kUSB_DeviceControlEndpointDeinit, &endpointAddress);
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ OSA_ENTER_CRITICAL();
+ deviceHandle->epCallbackDirectly = 0U;
+ OSA_EXIT_CRITICAL();
+#endif
+
+ if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS)
+ {
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn =
+ (usb_device_endpoint_callback_t)NULL;
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam = NULL;
+ deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U;
+ }
+ else
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+ return status;
+}
+
+/*!
+ * @brief Stall a specified endpoint.
+ *
+ * The function is used to stall a specified endpoint.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The endpoint is stalled successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+usb_status_t USB_DeviceStallEndpoint(usb_device_handle handle, uint8_t endpointAddress)
+{
+ if ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) < USB_DEVICE_CONFIG_ENDPOINTS)
+ {
+ return USB_DeviceControl(handle, kUSB_DeviceControlEndpointStall, &endpointAddress);
+ }
+ else
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+}
+
+/*!
+ * @brief Un-stall a specified endpoint.
+ *
+ * The function is used to un-stall a specified endpoint.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT.
+ *
+ * @retval kStatus_USB_Success The endpoint is un-stalled successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ */
+usb_status_t USB_DeviceUnstallEndpoint(usb_device_handle handle, uint8_t endpointAddress)
+{
+ if ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) < USB_DEVICE_CONFIG_ENDPOINTS)
+ {
+ return USB_DeviceControl(handle, kUSB_DeviceControlEndpointUnstall, &endpointAddress);
+ }
+ else
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+}
+
+/*!
+ * @brief Get the status of the selected item.
+ *
+ * The function is used to get the status of the selected item.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param type The selected item. Please refer to the structure usb_device_status_t.
+ * @param param The param type is determined by the selected item.
+ *
+ * @retval kStatus_USB_Success Get status successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_InvalidParameter The param is NULL pointer.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error Unsupported type.
+ */
+usb_status_t USB_DeviceGetStatus(usb_device_handle handle, usb_device_status_t type, void *param)
+{
+ uint8_t *temp8;
+ usb_status_t status = kStatus_USB_Error;
+
+ if (NULL == param)
+ {
+ return kStatus_USB_InvalidParameter;
+ }
+ switch (type)
+ {
+#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U)
+ case kUSB_DeviceStatusGetCurrentFrameCount:
+ status = USB_DeviceControl(handle, kUSB_DeviceControlGetCurrentFrameCount, param);
+ break;
+#endif
+ case kUSB_DeviceStatusSpeed:
+ status = USB_DeviceControl(handle, kUSB_DeviceControlGetSpeed, param);
+ break;
+ case kUSB_DeviceStatusOtg:
+ status = USB_DeviceControl(handle, kUSB_DeviceControlGetOtgStatus, param);
+ break;
+ case kUSB_DeviceStatusDeviceState:
+ temp8 = (uint8_t *)param;
+ status = kStatus_USB_Success;
+ *temp8 = ((usb_device_struct_t *)handle)->state;
+ break;
+ case kUSB_DeviceStatusAddress:
+ temp8 = (uint8_t *)param;
+ status = kStatus_USB_Success;
+ *temp8 = ((usb_device_struct_t *)handle)->deviceAddress;
+ break;
+ case kUSB_DeviceStatusDevice:
+ status = USB_DeviceControl(handle, kUSB_DeviceControlGetDeviceStatus, param);
+ break;
+ case kUSB_DeviceStatusEndpoint:
+ status = USB_DeviceControl(handle, kUSB_DeviceControlGetEndpointStatus, param);
+ break;
+ case kUSB_DeviceStatusSynchFrame:
+ status = USB_DeviceControl(handle, kUSB_DeviceControlGetSynchFrame, param);
+ break;
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ case kUSB_DeviceStatusRemoteWakeup:
+ temp8 = (uint8_t *)param;
+ status = kStatus_USB_Success;
+ *temp8 = ((usb_device_struct_t *)handle)->remotewakeup;
+ break;
+#endif
+ default:
+ /*no action*/
+ break;
+ }
+ return status;
+}
+
+/*!
+ * @brief Set the status of the selected item.
+ *
+ * The function is used to set the status of the selected item.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ * @param type The selected item. Please refer to the structure usb_device_status_t.
+ * @param param The param type is determined by the selected item.
+ *
+ * @retval kStatus_USB_Success Set status successfully.
+ * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_Error Unsupported type, or the param is NULL pointer.
+ */
+usb_status_t USB_DeviceSetStatus(usb_device_handle handle, usb_device_status_t type, void *param)
+{
+ usb_status_t status = kStatus_USB_Error;
+ switch (type)
+ {
+#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) || \
+ (defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) && \
+ (defined(USB_DEVICE_CONFIG_USB20_TEST_MODE) && (USB_DEVICE_CONFIG_USB20_TEST_MODE > 0U))
+ case kUSB_DeviceStatusTestMode:
+ status = USB_DeviceControl(handle, kUSB_DeviceControlSetTestMode, param);
+ break;
+#endif
+ case kUSB_DeviceStatusOtg:
+ status = USB_DeviceControl(handle, kUSB_DeviceControlSetOtgStatus, param);
+ break;
+ case kUSB_DeviceStatusDeviceState:
+ if (NULL != param)
+ {
+ status = kStatus_USB_Success;
+ ((usb_device_struct_t *)handle)->state = (uint8_t)(*(uint8_t *)param);
+ }
+ break;
+ case kUSB_DeviceStatusAddress:
+ if ((uint8_t)kUSB_DeviceStateAddressing != ((usb_device_struct_t *)handle)->state)
+ {
+ if (NULL != param)
+ {
+ status = kStatus_USB_Success;
+ ((usb_device_struct_t *)handle)->deviceAddress = (uint8_t)(*(uint8_t *)param);
+ ((usb_device_struct_t *)handle)->state = (uint8_t)kUSB_DeviceStateAddressing;
+ status = USB_DeviceControl(handle, kUSB_DeviceControlPreSetDeviceAddress,
+ &((usb_device_struct_t *)handle)->deviceAddress);
+ }
+ }
+ else
+ {
+ status = USB_DeviceControl(handle, kUSB_DeviceControlSetDeviceAddress,
+ &((usb_device_struct_t *)handle)->deviceAddress);
+ }
+ break;
+ case kUSB_DeviceStatusBusResume:
+ status = USB_DeviceControl(handle, kUSB_DeviceControlResume, param);
+ break;
+ case kUSB_DeviceStatusBusSleepResume:
+ status = USB_DeviceControl(handle, kUSB_DeviceControlSleepResume, param);
+ break;
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ case kUSB_DeviceStatusRemoteWakeup:
+ if (NULL != param)
+ {
+ status = kStatus_USB_Success;
+ ((usb_device_struct_t *)handle)->remotewakeup = (uint8_t)(*(uint8_t *)param);
+ }
+ break;
+#endif
+ case kUSB_DeviceStatusBusSuspend:
+ status = USB_DeviceControl(handle, kUSB_DeviceControlSuspend, param);
+ break;
+ case kUSB_DeviceStatusBusSleep:
+ status = USB_DeviceControl(handle, kUSB_DeviceControlSleep, param);
+ break;
+ default:
+ /*no action*/
+ break;
+ }
+ return status;
+}
+
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U))
+/*!
+ * @brief Enable the device dcd module.
+ *
+ * The function enable the device dcd module.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The device could run.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid.
+ *
+ */
+usb_status_t USB_DeviceDcdEnable(usb_device_handle handle)
+{
+ return USB_DeviceControl(handle, kUSB_DeviceControlDcdEnable, NULL);
+}
+/*!
+ * @brief Disable the device dcd module.
+ *
+ * The function disable the device dcd module.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ *
+ * @retval kStatus_USB_Success The dcd is reset and stopped.
+ * @retval kStatus_USB_ControllerNotFound Cannot find the controller.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid.
+ *
+ */
+usb_status_t USB_DeviceDcdDisable(usb_device_handle handle)
+{
+ return USB_DeviceControl(handle, kUSB_DeviceControlDcdDisable, NULL);
+}
+#endif
+
+#if USB_DEVICE_CONFIG_USE_TASK
+/*!
+ * @brief Device task function.
+ *
+ * The function is used to handle controller message.
+ * This function should not be called in application directly.
+ *
+ * @param handle The device handle got from USB_DeviceInit.
+ */
+void USB_DeviceTaskFunction(void *deviceHandle)
+{
+ usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle;
+ usb_device_callback_message_struct_t message;
+
+ if (NULL != deviceHandle)
+ {
+ message.buffer = NULL;
+ message.length = 0U;
+ message.code = 0U;
+ message.isSetup = 0U;
+ /* Get the message from the queue */
+ if (KOSA_StatusSuccess ==
+ OSA_MsgQGet(handle->notificationQueue, (osa_msg_handle_t)&message, USB_OSA_WAIT_TIMEOUT))
+ {
+ /* Handle the message */
+ (void)USB_DeviceNotification(handle, &message);
+ }
+ }
+}
+#endif
+
+/*!
+ * @brief Get device stack version function.
+ *
+ * The function is used to get device stack version.
+ *
+ * @param[out] version The version structure pointer to keep the device stack version.
+ *
+ */
+void USB_DeviceGetVersion(uint32_t *version)
+{
+ if (NULL != version)
+ {
+ *version =
+ (uint32_t)USB_MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX);
+ }
+}
+
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) || \
+ (((defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U))))
+/*!
+ * @brief Update the hardware tick.
+ *
+ * The function is used to update the hardware tick.
+ *
+ * @param[in] handle The device handle got from #USB_DeviceInit.
+ * @param[in] tick Current hardware tick.
+ *
+ */
+usb_status_t USB_DeviceUpdateHwTick(usb_device_handle handle, uint64_t tick)
+{
+ usb_device_struct_t *deviceHandle;
+ usb_status_t status = kStatus_USB_Success;
+#if (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) && \
+ (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U))
+#elif (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U))
+ /* fix misra 11.8 */
+ uint64_t tempValue;
+#endif
+
+ if (handle == NULL)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+ deviceHandle = (usb_device_struct_t *)handle;
+
+ deviceHandle->hwTick = tick;
+#if (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) && \
+ (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U))
+#ifndef USBHSDCD_IRQS
+ status = USB_DeviceControl(handle, kUSB_DeviceControlUpdateHwTick, (void *)(&deviceHandle->hwTick));
+#endif
+#elif (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \
+ (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U))
+ tempValue = deviceHandle->hwTick;
+ status = USB_DeviceControl(handle, kUSB_DeviceControlUpdateHwTick, (void *)(&tempValue));
+#endif
+ return status;
+}
+#endif
+#endif /* USB_DEVICE_CONFIG_NUM */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_dci.h b/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_dci.h
new file mode 100644
index 000000000..d8f9555f4
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/device/source/usb_device_dci.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __USB_DEVICE_DCI_H__
+#define __USB_DEVICE_DCI_H__
+
+/*!
+ * @addtogroup usb_device_controller_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Macro to define controller handle */
+#define usb_device_controller_handle usb_device_handle
+#define USB_DEVICE_MESSAGES_SIZE \
+ (sizeof(uint32_t) * (1U + (sizeof(usb_device_callback_message_struct_t) - 1U) / sizeof(uint32_t)))
+/*! @brief Available notify types for device notification */
+typedef enum _usb_device_notification
+{
+ kUSB_DeviceNotifyBusReset = 0x10U, /*!< Reset signal detected */
+ kUSB_DeviceNotifySuspend, /*!< Suspend signal detected */
+ kUSB_DeviceNotifyResume, /*!< Resume signal detected */
+ kUSB_DeviceNotifyLPMSleep, /*!< LPM signal detected */
+ kUSB_DeviceNotifyLPMResume, /*!< Resume signal detected */
+ kUSB_DeviceNotifyError, /*!< Errors happened in bus */
+ kUSB_DeviceNotifyDetach, /*!< Device disconnected from a host */
+ kUSB_DeviceNotifyAttach, /*!< Device connected to a host */
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U))
+ kUSB_DeviceNotifyDcdDetectFinished, /*!< Device charger detection finished */
+#endif
+} usb_device_notification_t;
+
+/*! @brief Device notification message structure */
+typedef struct _usb_device_callback_message_struct
+{
+ uint8_t *buffer; /*!< Transferred buffer */
+ uint32_t length; /*!< Transferred data length */
+ uint8_t code; /*!< Notification code */
+ uint8_t isSetup; /*!< Is in a setup phase */
+} usb_device_callback_message_struct_t;
+
+/*! @brief Control type for controller */
+typedef enum _usb_device_control_type
+{
+ kUSB_DeviceControlRun = 0U, /*!< Enable the device functionality */
+ kUSB_DeviceControlStop, /*!< Disable the device functionality */
+ kUSB_DeviceControlEndpointInit, /*!< Initialize a specified endpoint */
+ kUSB_DeviceControlEndpointDeinit, /*!< De-initialize a specified endpoint */
+ kUSB_DeviceControlEndpointStall, /*!< Stall a specified endpoint */
+ kUSB_DeviceControlEndpointUnstall, /*!< Un-stall a specified endpoint */
+ kUSB_DeviceControlGetDeviceStatus, /*!< Get device status */
+ kUSB_DeviceControlGetEndpointStatus, /*!< Get endpoint status */
+ kUSB_DeviceControlSetDeviceAddress, /*!< Set device address */
+ kUSB_DeviceControlGetSynchFrame, /*!< Get current frame */
+ kUSB_DeviceControlResume, /*!< Drive controller to generate a resume signal in USB bus */
+ kUSB_DeviceControlSleepResume, /*!< Drive controller to generate a LPM resume signal in USB bus */
+ kUSB_DeviceControlSuspend, /*!< Drive controller to enter into suspend mode */
+ kUSB_DeviceControlSleep, /*!< Drive controller to enter into sleep mode */
+ kUSB_DeviceControlSetDefaultStatus, /*!< Set controller to default status */
+ kUSB_DeviceControlGetSpeed, /*!< Get current speed */
+ kUSB_DeviceControlGetOtgStatus, /*!< Get OTG status */
+ kUSB_DeviceControlSetOtgStatus, /*!< Set OTG status */
+ kUSB_DeviceControlSetTestMode, /*!< Drive xCHI into test mode */
+ kUSB_DeviceControlGetRemoteWakeUp, /*!< Get flag of LPM Remote Wake-up Enabled by USB host. */
+#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U))
+ kUSB_DeviceControlDcdDisable, /*!< disable dcd module function. */
+ kUSB_DeviceControlDcdEnable, /*!< enable dcd module function. */
+#endif
+ kUSB_DeviceControlPreSetDeviceAddress, /*!< Pre set device address */
+ kUSB_DeviceControlUpdateHwTick, /*!< update hardware tick */
+#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U)
+ kUSB_DeviceControlGetCurrentFrameCount, /*!< Get current frame count */
+#endif
+} usb_device_control_type_t;
+
+/*! @brief USB device controller initialization function typedef */
+typedef usb_status_t (*usb_device_controller_init_t)(uint8_t controllerId,
+ usb_device_handle handle,
+ usb_device_controller_handle *controllerHandle);
+
+/*! @brief USB device controller de-initialization function typedef */
+typedef usb_status_t (*usb_device_controller_deinit_t)(usb_device_controller_handle controllerHandle);
+
+/*! @brief USB device controller send data function typedef */
+typedef usb_status_t (*usb_device_controller_send_t)(usb_device_controller_handle controllerHandle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*! @brief USB device controller receive data function typedef */
+typedef usb_status_t (*usb_device_controller_recv_t)(usb_device_controller_handle controllerHandle,
+ uint8_t endpointAddress,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*! @brief USB device controller cancel transfer function in a specified endpoint typedef */
+typedef usb_status_t (*usb_device_controller_cancel_t)(usb_device_controller_handle controllerHandle,
+ uint8_t endpointAddress);
+
+/*! @brief USB device controller control function typedef */
+typedef usb_status_t (*usb_device_controller_control_t)(usb_device_controller_handle controllerHandle,
+ usb_device_control_type_t command,
+ void *param);
+
+/*! @brief USB device controller interface structure */
+typedef struct _usb_device_controller_interface_struct
+{
+ usb_device_controller_init_t deviceInit; /*!< Controller initialization */
+ usb_device_controller_deinit_t deviceDeinit; /*!< Controller de-initialization */
+ usb_device_controller_send_t deviceSend; /*!< Controller send data */
+ usb_device_controller_recv_t deviceRecv; /*!< Controller receive data */
+ usb_device_controller_cancel_t deviceCancel; /*!< Controller cancel transfer */
+ usb_device_controller_control_t deviceControl; /*!< Controller control */
+} usb_device_controller_interface_struct_t;
+
+/*! @brief USB device status structure */
+typedef struct _usb_device_struct
+{
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) || \
+ (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U))
+ volatile uint64_t hwTick; /*!< Current hw tick(ms)*/
+#endif
+ usb_device_controller_handle controllerHandle; /*!< Controller handle */
+ const usb_device_controller_interface_struct_t *controllerInterface; /*!< Controller interface handle */
+#if USB_DEVICE_CONFIG_USE_TASK
+ OSA_MSGQ_HANDLE_DEFINE(notificationQueueBuffer,
+ USB_DEVICE_CONFIG_MAX_MESSAGES,
+ USB_DEVICE_MESSAGES_SIZE); /*!< Message queue buffer*/
+ osa_msgq_handle_t notificationQueue; /*!< Message queue*/
+#endif
+ usb_device_callback_t deviceCallback; /*!< Device callback function pointer */
+ usb_device_endpoint_callback_struct_t
+ epCallback[USB_DEVICE_CONFIG_ENDPOINTS << 1U]; /*!< Endpoint callback function structure */
+ uint8_t deviceAddress; /*!< Current device address */
+ uint8_t controllerId; /*!< Controller ID */
+ uint8_t state; /*!< Current device state */
+#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U))
+ uint8_t remotewakeup; /*!< Remote wakeup is enabled or not */
+#endif
+ uint8_t isResetting; /*!< Is doing device reset or not */
+#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U))
+ uint8_t epCallbackDirectly; /*!< Whether call ep callback directly when the task is enabled */
+#endif
+} usb_device_struct_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+/*!
+ * @brief Notify the device that the controller status changed.
+ *
+ * This function is used to notify the device that the controller status changed.
+ *
+ * @param handle The device handle. It equals the value returned from USB_DeviceInit.
+ * @param message The device callback message handle.
+ *
+ * @return A USB error code or kStatus_USB_Success.
+ */
+usb_status_t USB_DeviceNotificationTrigger(void *handle, void *msg);
+/*! @}*/
+
+#endif /* __USB_DEVICE_DCI_H__ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/example/usb_device_composite_cdc_vcom_cdc_vcom/inf/cdc.cat b/minimal-examples/embedded/rt595/hello_world/project/usb/example/usb_device_composite_cdc_vcom_cdc_vcom/inf/cdc.cat
new file mode 100644
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literal 0
HcmV?d00001
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/example/usb_device_composite_cdc_vcom_cdc_vcom/inf/fsl_ucwxp.inf b/minimal-examples/embedded/rt595/hello_world/project/usb/example/usb_device_composite_cdc_vcom_cdc_vcom/inf/fsl_ucwxp.inf
new file mode 100644
index 000000000..2a758308c
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/example/usb_device_composite_cdc_vcom_cdc_vcom/inf/fsl_ucwxp.inf
@@ -0,0 +1,109 @@
+;
+; Copyright 2016 - 2018 NXP
+; All rights reserved.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+[Version]
+Signature="$Windows NT$"
+Class=Ports
+ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}
+Provider=%MFGNAME%
+CatalogFile=%MFGFILENAME%.cat
+DriverVer=02/16/2011,1.0
+
+[Manufacturer]
+%MFGNAME%=DeviceList, NTamd64
+
+[DestinationDirs]
+DefaultDestDir=12
+
+
+;------------------------------------------------------------------------------
+; Windows 2000/XP/Vista-32bit Sections
+;------------------------------------------------------------------------------
+
+[DriverInstall.nt]
+include=mdmcpq.inf
+AddReg=DriverInstall.nt.AddReg
+
+[DriverInstall.nt.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,%DRIVERFILENAME%.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[DriverInstall.nt.Services]
+AddService=usbser, 0x00000002, DriverService.nt
+
+[DriverService.nt]
+DisplayName=%SERVICE%
+ServiceType=1
+StartType=3
+ErrorControl=1
+ServiceBinary=%12%\%DRIVERFILENAME%.sys
+
+;------------------------------------------------------------------------------
+; Vista-64bit Sections
+;------------------------------------------------------------------------------
+
+[DriverInstall.NTamd64]
+include=mdmcpq.inf
+AddReg=DriverInstall.NTamd64.AddReg
+
+[DriverInstall.NTamd64.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,%DRIVERFILENAME%.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[DriverInstall.NTamd64.Services]
+AddService=usbser, 0x00000002, DriverService.NTamd64
+
+[DriverService.NTamd64]
+DisplayName=%SERVICE%
+ServiceType=1
+StartType=3
+ErrorControl=1
+ServiceBinary=%12%\%DRIVERFILENAME%.sys
+
+
+;------------------------------------------------------------------------------
+; Vendor and Product ID Definitions
+;------------------------------------------------------------------------------
+; When developing your USB device, the VID and PID used in the PC side
+; application program and the firmware on the microcontroller must match.
+; Modify the below line to use your VID and PID. Use the format as shown below.
+; Note: One INF file can be used for multiple devices with different VID and PIDs.
+; For each supported device, append ",USB\VID_xxxx&PID_yyyy" to the end of the line.
+;------------------------------------------------------------------------------
+[SourceDisksFiles]
+[SourceDisksNames]
+[DeviceList]
+%DESCRIPTION%=DriverInstall, USB\VID_1FC9&PID_0094
+%DESCRIPTION%=DriverInstall, USB\VID_1FC9&PID_009E&MI_00
+%DESCRIPTION%=DriverInstall, USB\VID_1FC9&PID_009F&MI_00
+%DESCRIPTION%=DriverInstall, USB\VID_1FC9&PID_00A3&MI_00
+%DESCRIPTION%=DriverInstall, USB\VID_1FC9&PID_00A6&MI_03
+%DESCRIPTION%=DriverInstall, USB\VID_1FC9&PID_00A7&MI_04
+
+[DeviceList.NTamd64]
+%DESCRIPTION% = DriverInstall, USB\VID_1FC9&PID_0094
+%DESCRIPTION% = DriverInstall, USB\VID_1FC9&PID_009E&MI_00
+%DESCRIPTION% = DriverInstall, USB\VID_1FC9&PID_009F&MI_00
+%DESCRIPTION% = DriverInstall, USB\VID_1FC9&PID_00A3&MI_00
+%DESCRIPTION% = DriverInstall, USB\VID_1FC9&PID_00A6&MI_03
+%DESCRIPTION% = DriverInstall, USB\VID_1FC9&PID_00A7&MI_04
+
+;------------------------------------------------------------------------------
+; String Definitions
+;------------------------------------------------------------------------------
+;Modify these strings to customize your device
+;------------------------------------------------------------------------------
+[Strings]
+MFGFILENAME="CDC"
+DRIVERFILENAME ="usbser"
+MFGNAME="NXP"
+INSTDISK="NXP CDC Driver Installer"
+DESCRIPTION="Virtual Com Port"
+SERVICE="NXP Virtual COM Driver"
+
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/include/usb.h b/minimal-examples/embedded/rt595/hello_world/project/usb/include/usb.h
new file mode 100644
index 000000000..483d8a1f3
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/include/usb.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __USB_H__
+#define __USB_H__
+
+#include <stdint.h>
+#include <stdio.h>
+#include "fsl_common.h"
+#include "fsl_os_abstraction.h"
+#include "usb_misc.h"
+#include "usb_spec.h"
+
+/*!
+ * @addtogroup usb_drv
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Defines USB stack major version */
+#define USB_STACK_VERSION_MAJOR (2UL)
+/*! @brief Defines USB stack minor version */
+#define USB_STACK_VERSION_MINOR (8UL)
+/*! @brief Defines USB stack bugfix version */
+#define USB_STACK_VERSION_BUGFIX (0U)
+
+/*! @brief USB stack version definition */
+#define USB_MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/*! @brief USB stack component version definition, changed with component in yaml together */
+#define USB_STACK_COMPONENT_VERSION \
+ MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX)
+
+/*
+ * Component ID used by tools
+ *
+ * FSL_COMPONENT_ID "middleware.usb.stack_common"
+ */
+
+/*! @brief USB error code */
+typedef enum _usb_status
+{
+ kStatus_USB_Success = 0x00U, /*!< Success */
+ kStatus_USB_Error, /*!< Failed */
+
+ kStatus_USB_Busy, /*!< Busy */
+ kStatus_USB_InvalidHandle, /*!< Invalid handle */
+ kStatus_USB_InvalidParameter, /*!< Invalid parameter */
+ kStatus_USB_InvalidRequest, /*!< Invalid request */
+ kStatus_USB_ControllerNotFound, /*!< Controller cannot be found */
+ kStatus_USB_InvalidControllerInterface, /*!< Invalid controller interface */
+
+ kStatus_USB_NotSupported, /*!< Configuration is not supported */
+ kStatus_USB_Retry, /*!< Enumeration get configuration retry */
+ kStatus_USB_TransferStall, /*!< Transfer stalled */
+ kStatus_USB_TransferFailed, /*!< Transfer failed */
+ kStatus_USB_AllocFail, /*!< Allocation failed */
+ kStatus_USB_LackSwapBuffer, /*!< Insufficient swap buffer for KHCI */
+ kStatus_USB_TransferCancel, /*!< The transfer cancelled */
+ kStatus_USB_BandwidthFail, /*!< Allocate bandwidth failed */
+ kStatus_USB_MSDStatusFail, /*!< For MSD, the CSW status means fail */
+ kStatus_USB_EHCIAttached,
+ kStatus_USB_EHCIDetached,
+ kStatus_USB_DataOverRun, /*!< The amount of data returned by the endpoint exceeded
+ either the size of the maximum data packet allowed
+ from the endpoint or the remaining buffer size. */
+} usb_status_t;
+
+/*! @brief USB host handle type define */
+typedef void *usb_host_handle;
+
+/*! @brief USB device handle type define. For device stack it is the whole device handle; for host stack it is the
+ * attached device instance handle*/
+typedef void *usb_device_handle;
+
+/*! @brief USB OTG handle type define */
+typedef void *usb_otg_handle;
+
+/*! @brief USB controller ID */
+typedef enum _usb_controller_index
+{
+ kUSB_ControllerKhci0 = 0U, /*!< KHCI 0U */
+ kUSB_ControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved
+ to be used in the future. */
+ kUSB_ControllerEhci0 = 2U, /*!< EHCI 0U */
+ kUSB_ControllerEhci1 = 3U, /*!< EHCI 1U, Currently, there are no platforms which have two EHCI IPs, this is reserved
+ to be used in the future. */
+
+ kUSB_ControllerLpcIp3511Fs0 = 4U, /*!< LPC USB IP3511 FS controller 0 */
+ kUSB_ControllerLpcIp3511Fs1 = 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which have two IP3511
+ IPs, this is reserved to be used in the future. */
+
+ kUSB_ControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */
+ kUSB_ControllerLpcIp3511Hs1 = 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which have two IP3511
+ IPs, this is reserved to be used in the future. */
+
+ kUSB_ControllerOhci0 = 8U, /*!< OHCI 0U */
+ kUSB_ControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs, this is reserved
+ to be used in the future. */
+
+ kUSB_ControllerIp3516Hs0 = 10U, /*!< IP3516HS 0U */
+ kUSB_ControllerIp3516Hs1 = 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two IP3516HS IPs,
+ this is reserved to be used in the future. */
+ kUSB_ControllerDwc30 = 12U, /*!< DWC3 0U */
+ kUSB_ControllerDwc31 = 13U, /*!< DWC3 1U Currently, there are no platforms which have two Dwc IPs, this is reserved
+ to be used in the future.*/
+} usb_controller_index_t;
+
+/**
+ * @brief USB stack version fields
+ */
+typedef struct _usb_version
+{
+ uint8_t major; /*!< Major */
+ uint8_t minor; /*!< Minor */
+ uint8_t bugfix; /*!< Bug fix */
+} usb_version_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*! @} */
+
+#endif /* __USB_H__ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/include/usb_misc.h b/minimal-examples/embedded/rt595/hello_world/project/usb/include/usb_misc.h
new file mode 100644
index 000000000..af134c889
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/include/usb_misc.h
@@ -0,0 +1,502 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __USB_MISC_H__
+#define __USB_MISC_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Define big endian */
+#define USB_BIG_ENDIAN (0U)
+/*! @brief Define little endian */
+#define USB_LITTLE_ENDIAN (1U)
+
+/*! @brief Define current endian */
+#ifndef ENDIANNESS
+#define ENDIANNESS USB_LITTLE_ENDIAN
+#endif
+/*! @brief Define default timeout value */
+#if (defined(USE_RTOS) && (USE_RTOS > 0))
+#define USB_OSA_WAIT_TIMEOUT (osaWaitForever_c)
+#else
+#define USB_OSA_WAIT_TIMEOUT (0U)
+#endif /* (defined(USE_RTOS) && (USE_RTOS > 0)) */
+
+/*! @brief Define USB printf */
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+extern int DbgConsole_Printf(const char *fmt_s, ...);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#if defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE < 1)
+#define usb_echo printf
+#else
+#define usb_echo DbgConsole_Printf
+#endif
+
+#if defined(__ICCARM__)
+
+#ifndef STRUCT_PACKED
+#define STRUCT_PACKED __packed
+#endif
+
+#ifndef STRUCT_UNPACKED
+#define STRUCT_UNPACKED
+#endif
+
+#elif defined(__GNUC__)
+
+#ifndef STRUCT_PACKED
+#define STRUCT_PACKED
+#endif
+
+#ifndef STRUCT_UNPACKED
+#define STRUCT_UNPACKED __attribute__((__packed__))
+#endif
+
+#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION))
+
+#ifndef STRUCT_PACKED
+#define STRUCT_PACKED _Pragma("pack(1U)")
+#endif
+
+#ifndef STRUCT_UNPACKED
+#define STRUCT_UNPACKED _Pragma("pack()")
+#endif
+
+#elif (defined(__DSC__) || defined(__CW__))
+
+#ifndef STRUCT_PACKED
+#define STRUCT_PACKED
+#endif
+
+#ifndef STRUCT_UNPACKED
+#define STRUCT_UNPACKED __attribute__((packed))
+#endif
+#endif
+
+#define USB_SHORT_GET_LOW(x) (((uint16_t)x) & 0xFFU)
+#define USB_SHORT_GET_HIGH(x) ((uint8_t)(((uint16_t)x) >> 8U) & 0xFFU)
+
+#define USB_LONG_GET_BYTE0(x) ((uint8_t)(((uint32_t)(x))) & 0xFFU)
+#define USB_LONG_GET_BYTE1(x) ((uint8_t)(((uint32_t)(x)) >> 8U) & 0xFFU)
+#define USB_LONG_GET_BYTE2(x) ((uint8_t)(((uint32_t)(x)) >> 16U) & 0xFFU)
+#define USB_LONG_GET_BYTE3(x) ((uint8_t)(((uint32_t)(x)) >> 24U) & 0xFFU)
+
+#define USB_MEM4_ALIGN_MASK (0x03U)
+
+/* accessory macro */
+#define USB_MEM4_ALIGN(n) ((n + 3U) & (0xFFFFFFFCu))
+#define USB_MEM32_ALIGN(n) ((n + 31U) & (0xFFFFFFE0u))
+#define USB_MEM64_ALIGN(n) ((n + 63U) & (0xFFFFFFC0u))
+
+/* big/little endian */
+#define SWAP2BYTE_CONST(n) ((((n)&0x00FFU) << 8U) | (((n)&0xFF00U) >> 8U))
+#define SWAP4BYTE_CONST(n) \
+ ((((n)&0x000000FFU) << 24U) | (((n)&0x0000FF00U) << 8U) | (((n)&0x00FF0000U) >> 8U) | (((n)&0xFF000000U) >> 24U))
+
+#define USB_ASSIGN_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \
+ { \
+ *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \
+ *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \
+ *((uint8_t *)&(n) + 2) = *((uint8_t *)&(m) + 2); \
+ *((uint8_t *)&(n) + 3) = *((uint8_t *)&(m) + 3); \
+ }
+
+#define USB_ASSIGN_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \
+ { \
+ *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \
+ *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \
+ }
+
+#define USB_ASSIGN_MACRO_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \
+ { \
+ *((uint8_t *)&(n)) = (uint8_t)m; \
+ *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \
+ *((uint8_t *)&(n) + 2) = (uint8_t)(m >> 16); \
+ *((uint8_t *)&(n) + 3) = (uint8_t)(m >> 24); \
+ }
+
+#define USB_ASSIGN_MACRO_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \
+ { \
+ *((uint8_t *)&(n)) = (uint8_t)m; \
+ *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \
+ }
+
+#if (ENDIANNESS == USB_BIG_ENDIAN)
+
+#define USB_SHORT_TO_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n)
+#define USB_LONG_TO_LITTLE_ENDIAN(n) SWAP4BYTE_CONST(n)
+#define USB_SHORT_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n)
+#define USB_LONG_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n)
+
+#define USB_SHORT_TO_BIG_ENDIAN(n) (n)
+#define USB_LONG_TO_BIG_ENDIAN(n) (n)
+#define USB_SHORT_FROM_BIG_ENDIAN(n) (n)
+#define USB_LONG_FROM_BIG_ENDIAN(n) (n)
+
+#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[3] = (uint8_t)((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ m[2] = (uint8_t)((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ m[1] = (uint8_t)((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ m[0] = (uint8_t)(((uint32_t)(n)) & 0xFFU); \
+ }
+
+#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \
+ ((uint32_t)((((uint32_t)n[3]) << 24U) | (((uint32_t)n[2]) << 16U) | (((uint32_t)n[1]) << 8U) | \
+ (((uint32_t)n[0]) << 0U)))
+
+#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[0] = ((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ m[1] = ((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ m[2] = ((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ m[3] = (((uint32_t)(n)) & 0xFFU); \
+ }
+
+#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \
+ ((uint32_t)((((uint32_t)n[0]) << 24U) | (((uint32_t)n[1]) << 16U) | (((uint32_t)n[2]) << 8U) | \
+ (((uint32_t)n[3]) << 0U)))
+
+#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[1] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ m[0] = (((uint16_t)(n)) & 0xFFU); \
+ }
+
+#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[1]) << 8U) | (((uint16_t)n[0]) << 0U)))
+
+#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[0] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ m[1] = (((uint16_t)(n)) & 0xFFU); \
+ }
+
+#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[0]) << 8U) | (((uint16_t)n[1]) << 0U)))
+
+#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \
+ { \
+ *((uint8_t *)&(m) + 3) = ((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ *((uint8_t *)&(m) + 2) = ((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ *((uint8_t *)&(m) + 1) = ((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ *((uint8_t *)&(m) + 0) = (((uint32_t)(n)) & 0xFFU); \
+ }
+
+#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \
+ ((uint32_t)(((uint32_t)(*((uint8_t *)&(n) + 3)) << 24U) | ((uint32_t)(*((uint8_t *)&(n) + 2)) << 16U) | \
+ ((uint32_t)(*((uint8_t *)&(n) + 1)) << 8U) | ((uint32_t)(*((uint8_t *)&(n))) << 0U)))
+
+#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \
+ { \
+ *((uint8_t *)&(m) + 1) = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ *((uint8_t *)&(m)) = ((((uint16_t)(n))) & 0xFFU); \
+ }
+
+#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) \
+ ((uint16_t)((uint16_t)(*((uint8_t *)&(n) + 1)) << 8U) | ((uint16_t)(*((uint8_t *)&(n)))))
+
+#else
+
+#define USB_SHORT_TO_LITTLE_ENDIAN(n) (n)
+#define USB_LONG_TO_LITTLE_ENDIAN(n) (n)
+#define USB_SHORT_FROM_LITTLE_ENDIAN(n) (n)
+#define USB_LONG_FROM_LITTLE_ENDIAN(n) (n)
+
+#define USB_SHORT_TO_BIG_ENDIAN(n) SWAP2BYTE_CONST(n)
+#define USB_LONG_TO_BIG_ENDIAN(n) SWAP4BYTE_CONST(n)
+#define USB_SHORT_FROM_BIG_ENDIAN(n) SWAP2BYTE_CONST(n)
+#define USB_LONG_FROM_BIG_ENDIAN(n) SWAP4BYTE_CONST(n)
+
+#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[3] = (uint8_t)((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ m[2] = (uint8_t)((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ m[1] = (uint8_t)((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ m[0] = (uint8_t)(((uint32_t)(n)) & 0xFFU); \
+ }
+
+#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \
+ ((uint32_t)((((uint32_t)n[3]) << 24U) | (((uint32_t)n[2]) << 16U) | (((uint32_t)n[1]) << 8U) | \
+ (((uint32_t)n[0]) << 0U)))
+
+#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[0] = ((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ m[1] = ((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ m[2] = ((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ m[3] = (((uint32_t)(n)) & 0xFFU); \
+ }
+
+#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \
+ ((uint32_t)((((uint32_t)n[0]) << 24U) | (((uint32_t)n[1]) << 16U) | (((uint32_t)n[2]) << 8U) | \
+ (((uint32_t)n[3]) << 0U)))
+
+#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[1] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ m[0] = (((uint16_t)(n)) & 0xFFU); \
+ }
+
+#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[1]) << 8U) | (((uint16_t)n[0]) << 0U)))
+
+#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[0] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ m[1] = (((uint16_t)(n)) & 0xFFU); \
+ }
+
+#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[0]) << 8U) | (((uint16_t)n[1]) << 0U)))
+
+#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \
+ { \
+ *((uint8_t *)&(m) + 3) = ((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ *((uint8_t *)&(m) + 2) = ((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ *((uint8_t *)&(m) + 1) = ((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ *((uint8_t *)&(m) + 0) = (((uint32_t)(n)) & 0xFFU); \
+ }
+
+#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \
+ ((uint32_t)(((uint32_t)(*((uint8_t *)&(n) + 3)) << 24U) | ((uint32_t)(*((uint8_t *)&(n) + 2)) << 16U) | \
+ ((uint32_t)(*((uint8_t *)&(n) + 1)) << 8U) | ((uint32_t)(*((uint8_t *)&(n))) << 0U)))
+
+#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \
+ { \
+ *((uint8_t *)&(m) + 1) = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ *((uint8_t *)&(m)) = ((((uint16_t)(n))) & 0xFFU); \
+ }
+
+#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) \
+ ((uint16_t)(((uint16_t)(*(((uint8_t *)&(n)) + 1)) << 8U) | ((uint16_t)(*((uint8_t *)&(n))))))
+
+#endif
+
+/*
+ * The following MACROs (USB_GLOBAL, USB_BDT, USB_RAM_ADDRESS_ALIGNMENT, etc) are only used for USB device stack.
+ * The USB device global variables are put into the section m_usb_global and m_usb_bdt
+ * by using the MACRO USB_GLOBAL and USB_BDT. In this way, the USB device
+ * global variables can be linked into USB dedicated RAM by USB_STACK_USE_DEDICATED_RAM.
+ * The MACRO USB_STACK_USE_DEDICATED_RAM is used to decide the USB stack uses dedicated RAM or not. The value of
+ * the macro can be set as 0, USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL, or USB_STACK_DEDICATED_RAM_TYPE_BDT.
+ * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL means USB device global variables, including USB_BDT and
+ * USB_GLOBAL, are put into the USB dedicated RAM. This feature can only be enabled when the USB dedicated RAM
+ * is not less than 2K Bytes.
+ * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT means USB device global variables, only including USB_BDT, are put
+ * into the USB dedicated RAM, the USB_GLOBAL will be put into .bss section. This feature is used for some SOCs,
+ * the USB dedicated RAM size is not more than 512 Bytes.
+ */
+#define USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL 1
+#define USB_STACK_DEDICATED_RAM_TYPE_BDT 2
+
+#if defined(__ICCARM__)
+
+#define USB_WEAK_VAR __attribute__((weak))
+#define USB_WEAK_FUN __attribute__((weak))
+/* disable misra 19.13 */
+_Pragma("diag_suppress=Pm120")
+#define USB_ALIGN_PRAGMA(x) _Pragma(#x)
+ _Pragma("diag_default=Pm120")
+
+#define USB_RAM_ADDRESS_ALIGNMENT(n) USB_ALIGN_PRAGMA(data_alignment = n)
+ _Pragma("diag_suppress=Pm120")
+#define USB_LINK_SECTION_PART(str) _Pragma(#str)
+#define USB_LINK_DMA_INIT_DATA(sec) USB_LINK_SECTION_PART(location = #sec)
+#define USB_LINK_USB_GLOBAL _Pragma("location = \"m_usb_global\"")
+#define USB_LINK_USB_BDT _Pragma("location = \"m_usb_bdt\"")
+#define USB_LINK_USB_GLOBAL_BSS
+#define USB_LINK_USB_BDT_BSS
+ _Pragma("diag_default=Pm120")
+#define USB_LINK_DMA_NONINIT_DATA _Pragma("location = \"m_usb_dma_noninit_data\"")
+#define USB_LINK_NONCACHE_NONINIT_DATA _Pragma("location = \"NonCacheable\"")
+#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION))
+
+#define USB_WEAK_VAR __attribute__((weak))
+#define USB_WEAK_FUN __attribute__((weak))
+#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n)))
+#define USB_LINK_DMA_INIT_DATA(sec) __attribute__((section(#sec)))
+#if defined(__CC_ARM)
+#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global"))) __attribute__((zero_init))
+#else
+#define USB_LINK_USB_GLOBAL __attribute__((section(".bss.m_usb_global")))
+#endif
+#if defined(__CC_ARM)
+#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt"))) __attribute__((zero_init))
+#else
+#define USB_LINK_USB_BDT __attribute__((section(".bss.m_usb_bdt")))
+#endif
+#define USB_LINK_USB_GLOBAL_BSS
+#define USB_LINK_USB_BDT_BSS
+#if defined(__CC_ARM)
+#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data"))) __attribute__((zero_init))
+#else
+#define USB_LINK_DMA_NONINIT_DATA __attribute__((section(".bss.m_usb_dma_noninit_data")))
+#endif
+#if defined(__CC_ARM)
+#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable"))) __attribute__((zero_init))
+#else
+#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section(".bss.NonCacheable")))
+#endif
+
+#elif defined(__GNUC__)
+
+#define USB_WEAK_VAR __attribute__((weak))
+#define USB_WEAK_FUN __attribute__((weak))
+#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n)))
+#define USB_LINK_DMA_INIT_DATA(sec) __attribute__((section(#sec)))
+#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global, \"aw\", %nobits @")))
+#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt, \"aw\", %nobits @")))
+#define USB_LINK_USB_GLOBAL_BSS
+#define USB_LINK_USB_BDT_BSS
+#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data, \"aw\", %nobits @")))
+#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable, \"aw\", %nobits @")))
+
+#elif (defined(__DSC__) && defined(__CW__))
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#define USB_WEAK_VAR __attribute__((weak))
+#define USB_WEAK_FUN __attribute__((weak))
+#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n)))
+#define USB_LINK_USB_BDT_BSS
+#define USB_LINK_USB_GLOBAL_BSS
+#else
+#error The tool-chain is not supported.
+#endif
+
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \
+ (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE))
+
+#if ((defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)) && (defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
+#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#elif (defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))
+#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, 0)
+#elif (defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))
+#define USB_CACHE_LINESIZE MAX(0, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#else
+#define USB_CACHE_LINESIZE 4U
+#endif
+
+#else
+#define USB_CACHE_LINESIZE 4U
+#endif
+
+#if (USB_CACHE_LINESIZE > 4U)
+#define USB_DATA_ALIGN_SIZE USB_CACHE_LINESIZE
+#else
+/* Change the USB_DATA_ALIGN_SIZE to 4, For the lpcip3511 driver, the lpcip3511 driver will do the memcpy for the
+ transfer buffer that is not in the USB dedicated RAM or not aligned to 64-byte boundaries. Hence the changes do not
+ bring the risk and improve the RAM usage rate but cause the lower perfromance. If requiring a higher performance on
+ the lpcip3511 platform, please change the macro to 64 and put the transfer buffer into the USB dedicated RAM. */
+#define USB_DATA_ALIGN_SIZE 4U
+#endif
+
+/* Due to the change of USB_DATA_ALIGN_SIZE from 64 to 4 on the lpcip3511 platform, the size of variables defined by
+ using this marco may be smaller on the lpcip3511 platform. If users don't want the lpcip3511 driver to do memcpy,
+ please use the macro to define the transfer buffer and change the USB_DATA_ALIGN_SIZE to 64 and put the transfer
+ buffer into the USB dedicated RAM. */
+#define USB_DATA_ALIGN_SIZE_MULTIPLE(n) (((n) + USB_DATA_ALIGN_SIZE - 1U) & (~(USB_DATA_ALIGN_SIZE - 1U)))
+
+#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL)
+
+#define USB_GLOBAL USB_LINK_USB_GLOBAL
+#define USB_BDT USB_LINK_USB_BDT
+
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \
+ (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE))
+#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA
+#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data)
+#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
+#else
+#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE))
+#define USB_DMA_DATA_NONINIT_SUB USB_LINK_NONCACHE_NONINIT_DATA
+#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(NonCacheable.init)
+#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
+#else
+#define USB_DMA_DATA_NONINIT_SUB
+#define USB_DMA_DATA_INIT_SUB
+#define USB_CONTROLLER_DATA USB_LINK_USB_GLOBAL
+#endif
+#endif
+
+#elif defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT)
+
+#define USB_BDT USB_LINK_USB_BDT
+
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \
+ (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE))
+#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA
+#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA
+#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data)
+#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
+#else
+#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE))
+#define USB_GLOBAL USB_LINK_NONCACHE_NONINIT_DATA
+#define USB_DMA_DATA_NONINIT_SUB USB_LINK_NONCACHE_NONINIT_DATA
+#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(NonCacheable.init)
+#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
+#else
+#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS
+#define USB_DMA_DATA_NONINIT_SUB
+#define USB_DMA_DATA_INIT_SUB
+#define USB_CONTROLLER_DATA
+#endif
+#endif
+
+#else
+
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \
+ (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE))
+
+#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA
+#define USB_BDT USB_LINK_NONCACHE_NONINIT_DATA
+#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA
+#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data)
+#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
+
+#else
+
+#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE))
+#define USB_GLOBAL USB_LINK_NONCACHE_NONINIT_DATA
+#define USB_BDT USB_LINK_NONCACHE_NONINIT_DATA
+#define USB_DMA_DATA_NONINIT_SUB USB_LINK_NONCACHE_NONINIT_DATA
+#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(NonCacheable.init)
+#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
+#else
+#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS
+#define USB_BDT USB_LINK_USB_BDT_BSS
+#define USB_DMA_DATA_NONINIT_SUB
+#define USB_DMA_DATA_INIT_SUB
+#define USB_CONTROLLER_DATA
+#endif
+
+#endif
+
+#endif
+
+#define USB_DMA_NONINIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_NONINIT_SUB
+#define USB_DMA_INIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_INIT_SUB
+
+#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \
+ (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE))
+#define USB_DMA_DATA_NONCACHEABLE USB_LINK_NONCACHE_NONINIT_DATA
+
+#else
+#define USB_DMA_DATA_NONCACHEABLE
+#endif
+
+#define USB_GLOBAL_DEDICATED_RAM USB_LINK_USB_GLOBAL
+
+/* #define USB_RAM_ADDRESS_NONCACHEREG_ALIGNMENT(n, var) AT_NONCACHEABLE_SECTION_ALIGN(var, n) */
+/* #define USB_RAM_ADDRESS_NONCACHEREG(var) AT_NONCACHEABLE_SECTION(var) */
+
+#endif /* __USB_MISC_H__ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/include/usb_spec.h b/minimal-examples/embedded/rt595/hello_world/project/usb/include/usb_spec.h
new file mode 100644
index 000000000..a642bd518
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/include/usb_spec.h
@@ -0,0 +1,299 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __USB_SPEC_H__
+#define __USB_SPEC_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* USB speed (the value cannot be changed because EHCI QH use the value directly)*/
+#define USB_SPEED_FULL (0x00U)
+#define USB_SPEED_LOW (0x01U)
+#define USB_SPEED_HIGH (0x02U)
+#define USB_SPEED_SUPER (0x04U)
+
+/* Set up packet structure */
+typedef struct _usb_setup_struct
+{
+ uint8_t bmRequestType;
+ uint8_t bRequest;
+ uint16_t wValue;
+ uint16_t wIndex;
+ uint16_t wLength;
+} usb_setup_struct_t;
+
+/* USB standard descriptor endpoint type */
+#define USB_ENDPOINT_CONTROL (0x00U)
+#define USB_ENDPOINT_ISOCHRONOUS (0x01U)
+#define USB_ENDPOINT_BULK (0x02U)
+#define USB_ENDPOINT_INTERRUPT (0x03U)
+
+/* USB standard descriptor transfer direction (cannot change the value because iTD use the value directly) */
+#define USB_OUT (0U)
+#define USB_IN (1U)
+
+/* USB standard descriptor length */
+#define USB_DESCRIPTOR_LENGTH_DEVICE (0x12U)
+#define USB_DESCRIPTOR_LENGTH_CONFIGURE (0x09U)
+#define USB_DESCRIPTOR_LENGTH_INTERFACE (0x09U)
+#define USB_DESCRIPTOR_LENGTH_ENDPOINT (0x07U)
+#define USB_DESCRIPTOR_LENGTH_ENDPOINT_COMPANION (0x06U)
+#define USB_DESCRIPTOR_LENGTH_DEVICE_QUALITIER (0x0AU)
+#define USB_DESCRIPTOR_LENGTH_OTG_DESCRIPTOR (5U)
+#define USB_DESCRIPTOR_LENGTH_BOS_DESCRIPTOR (5U)
+#define USB_DESCRIPTOR_LENGTH_DEVICE_CAPABILITY_USB20_EXTENSION (0x07U)
+#define USB_DESCRIPTOR_LENGTH_DEVICE_CAPABILITY_SUPERSPEED (0x0AU)
+
+/* USB Device Capability Type Codes */
+#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_WIRELESS (0x01U)
+#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_USB20_EXTENSION (0x02U)
+#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_SUPERSPEED (0x03U)
+
+/* USB standard descriptor type */
+#define USB_DESCRIPTOR_TYPE_DEVICE (0x01U)
+#define USB_DESCRIPTOR_TYPE_CONFIGURE (0x02U)
+#define USB_DESCRIPTOR_TYPE_STRING (0x03U)
+#define USB_DESCRIPTOR_TYPE_INTERFACE (0x04U)
+#define USB_DESCRIPTOR_TYPE_ENDPOINT (0x05U)
+#define USB_DESCRIPTOR_TYPE_DEVICE_QUALITIER (0x06U)
+#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION (0x07U)
+#define USB_DESCRIPTOR_TYPE_INTERFAACE_POWER (0x08U)
+#define USB_DESCRIPTOR_TYPE_OTG (0x09U)
+#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION (0x0BU)
+#define USB_DESCRIPTOR_TYPE_BOS (0x0F)
+#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY (0x10)
+
+#define USB_DESCRIPTOR_TYPE_HID (0x21U)
+#define USB_DESCRIPTOR_TYPE_HID_REPORT (0x22U)
+#define USB_DESCRIPTOR_TYPE_HID_PHYSICAL (0x23U)
+
+#define USB_DESCRIPTOR_TYPE_ENDPOINT_COMPANION (0x30U)
+
+/* USB standard request type */
+#define USB_REQUEST_TYPE_DIR_MASK (0x80U)
+#define USB_REQUEST_TYPE_DIR_SHIFT (7U)
+#define USB_REQUEST_TYPE_DIR_OUT (0x00U)
+#define USB_REQUEST_TYPE_DIR_IN (0x80U)
+
+#define USB_REQUEST_TYPE_TYPE_MASK (0x60U)
+#define USB_REQUEST_TYPE_TYPE_SHIFT (5U)
+#define USB_REQUEST_TYPE_TYPE_STANDARD (0U)
+#define USB_REQUEST_TYPE_TYPE_CLASS (0x20U)
+#define USB_REQUEST_TYPE_TYPE_VENDOR (0x40U)
+
+#define USB_REQUEST_TYPE_RECIPIENT_MASK (0x1FU)
+#define USB_REQUEST_TYPE_RECIPIENT_SHIFT (0U)
+#define USB_REQUEST_TYPE_RECIPIENT_DEVICE (0x00U)
+#define USB_REQUEST_TYPE_RECIPIENT_INTERFACE (0x01U)
+#define USB_REQUEST_TYPE_RECIPIENT_ENDPOINT (0x02U)
+#define USB_REQUEST_TYPE_RECIPIENT_OTHER (0x03U)
+
+/* USB standard request */
+#define USB_REQUEST_STANDARD_GET_STATUS (0x00U)
+#define USB_REQUEST_STANDARD_CLEAR_FEATURE (0x01U)
+#define USB_REQUEST_STANDARD_SET_FEATURE (0x03U)
+#define USB_REQUEST_STANDARD_SET_ADDRESS (0x05U)
+#define USB_REQUEST_STANDARD_GET_DESCRIPTOR (0x06U)
+#define USB_REQUEST_STANDARD_SET_DESCRIPTOR (0x07U)
+#define USB_REQUEST_STANDARD_GET_CONFIGURATION (0x08U)
+#define USB_REQUEST_STANDARD_SET_CONFIGURATION (0x09U)
+#define USB_REQUEST_STANDARD_GET_INTERFACE (0x0AU)
+#define USB_REQUEST_STANDARD_SET_INTERFACE (0x0BU)
+#define USB_REQUEST_STANDARD_SYNCH_FRAME (0x0CU)
+
+/* USB standard request GET Status */
+#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT (0U)
+#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT (1U)
+
+#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_MASK (0x01U)
+#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_SHIFT (0U)
+
+#define USB_REQUEST_STANDARD_GET_STATUS_OTG_STATUS_SELECTOR (0xF000U)
+
+/* USB standard request CLEAR/SET feature */
+#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT (0U)
+#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_REMOTE_WAKEUP (1U)
+#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_TEST_MODE (2U)
+#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_B_HNP_ENABLE (3U)
+#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_HNP_SUPPORT (4U)
+#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_ALT_HNP_SUPPORT (5U)
+
+/* USB standard descriptor configure bmAttributes */
+#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_MASK (0x80U)
+#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_SHIFT (7U)
+
+#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_MASK (0x40U)
+#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_SHIFT (6U)
+
+#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_MASK (0x20U)
+#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_SHIFT (5U)
+
+/* USB standard descriptor endpoint bmAttributes */
+#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK (0x80U)
+#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT (7U)
+#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_OUT (0U)
+#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN (0x80U)
+
+#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_MASK (0x0FU)
+#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_SHFIT (0U)
+
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_TYPE_MASK (0x03U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_NUMBER_SHFIT (0U)
+
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_MASK (0x0CU)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SHFIT (2U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_NO_SYNC (0x00U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ASYNC (0x04U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ADAPTIVE (0x08U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SYNC (0x0CU)
+
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_MASK (0x30U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_SHFIT (4U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_DATA_ENDPOINT (0x00U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_FEEDBACK_ENDPOINT (0x10U)
+#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_IMPLICIT_FEEDBACK_DATA_ENDPOINT (0x20U)
+
+#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK (0x07FFu)
+#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK (0x1800u)
+#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_SHFIT (11U)
+
+/* USB standard descriptor otg bmAttributes */
+#define USB_DESCRIPTOR_OTG_ATTRIBUTES_SRP_MASK (0x01u)
+#define USB_DESCRIPTOR_OTG_ATTRIBUTES_HNP_MASK (0x02u)
+#define USB_DESCRIPTOR_OTG_ATTRIBUTES_ADP_MASK (0x04u)
+
+/* USB standard descriptor device capability usb20 extension bmAttributes */
+#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_MASK (0x02U)
+#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_SHIFT (1U)
+#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_MASK (0x04U)
+#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_SHIFT (2U)
+
+/* Language structure */
+typedef struct _usb_language
+{
+ uint8_t **string; /* The Strings descriptor array */
+ uint32_t *length; /* The strings descriptor length array */
+ uint16_t languageId; /* The language id of current language */
+} usb_language_t;
+
+typedef struct _usb_language_list
+{
+ uint8_t *languageString; /* The String 0U pointer */
+ uint32_t stringLength; /* The String 0U Length */
+ usb_language_t *languageList; /* The language list */
+ uint8_t count; /* The language count */
+} usb_language_list_t;
+
+typedef struct _usb_descriptor_common
+{
+ uint8_t bLength; /* Size of this descriptor in bytes */
+ uint8_t bDescriptorType; /* DEVICE Descriptor Type */
+ uint8_t bData[1]; /* Data */
+} usb_descriptor_common_t;
+
+typedef struct _usb_descriptor_device
+{
+ uint8_t bLength; /* Size of this descriptor in bytes */
+ uint8_t bDescriptorType; /* DEVICE Descriptor Type */
+ uint8_t bcdUSB[2]; /* UUSB Specification Release Number in Binary-Coded Decimal, e.g. 0x0200U */
+ uint8_t bDeviceClass; /* Class code */
+ uint8_t bDeviceSubClass; /* Sub-Class code */
+ uint8_t bDeviceProtocol; /* Protocol code */
+ uint8_t bMaxPacketSize0; /* Maximum packet size for endpoint zero */
+ uint8_t idVendor[2]; /* Vendor ID (assigned by the USB-IF) */
+ uint8_t idProduct[2]; /* Product ID (assigned by the manufacturer) */
+ uint8_t bcdDevice[2]; /* Device release number in binary-coded decimal */
+ uint8_t iManufacturer; /* Index of string descriptor describing manufacturer */
+ uint8_t iProduct; /* Index of string descriptor describing product */
+ uint8_t iSerialNumber; /* Index of string descriptor describing the device serial number */
+ uint8_t bNumConfigurations; /* Number of possible configurations */
+} usb_descriptor_device_t;
+
+typedef struct _usb_descriptor_configuration
+{
+ uint8_t bLength; /* Descriptor size in bytes = 9U */
+ uint8_t bDescriptorType; /* CONFIGURATION type = 2U or 7U */
+ uint8_t wTotalLength[2]; /* Length of concatenated descriptors */
+ uint8_t bNumInterfaces; /* Number of interfaces, this configuration. */
+ uint8_t bConfigurationValue; /* Value to set this configuration. */
+ uint8_t iConfiguration; /* Index to configuration string */
+ uint8_t bmAttributes; /* Configuration characteristics */
+ uint8_t bMaxPower; /* Maximum power from bus, 2 mA units */
+} usb_descriptor_configuration_t;
+
+typedef struct _usb_descriptor_interface
+{
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bInterfaceNumber;
+ uint8_t bAlternateSetting;
+ uint8_t bNumEndpoints;
+ uint8_t bInterfaceClass;
+ uint8_t bInterfaceSubClass;
+ uint8_t bInterfaceProtocol;
+ uint8_t iInterface;
+} usb_descriptor_interface_t;
+
+typedef struct _usb_descriptor_endpoint
+{
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bEndpointAddress;
+ uint8_t bmAttributes;
+ uint8_t wMaxPacketSize[2];
+ uint8_t bInterval;
+} usb_descriptor_endpoint_t;
+
+typedef struct _usb_descriptor_endpoint_companion
+{
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bMaxBurst;
+ uint8_t bmAttributes;
+ uint8_t wBytesPerInterval[2];
+} usb_descriptor_endpoint_companion_t;
+
+typedef struct _usb_descriptor_binary_device_object_store
+{
+ uint8_t bLength; /* Descriptor size in bytes = 5U */
+ uint8_t bDescriptorType; /* BOS Descriptor type = 0FU*/
+ uint8_t wTotalLength[2]; /*Length of this descriptor and all of its sub descriptors*/
+ uint8_t bNumDeviceCaps; /*The number of separate device capability descriptors in the BOS*/
+} usb_descriptor_bos_t;
+
+typedef struct _usb_descriptor_usb20_extension
+{
+ uint8_t bLength; /* Descriptor size in bytes = 7U */
+ uint8_t bDescriptorType; /* DEVICE CAPABILITY Descriptor type = 0x10U*/
+ uint8_t bDevCapabilityType; /*Length of this descriptor and all of its sub descriptors*/
+ uint8_t bmAttributes[4]; /*Bitmap encoding of supported device level features.*/
+} usb_descriptor_usb20_extension_t;
+typedef struct _usb_descriptor_super_speed_device_capability
+{
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bDevCapabilityType;
+ uint8_t bmAttributes;
+ uint8_t wSpeedsSupported[2];
+ uint8_t bFunctionalitySupport;
+ uint8_t bU1DevExitLat;
+ uint8_t wU2DevExitLat[2];
+} usb_bos_device_capability_susperspeed_desc_t;
+typedef union _usb_descriptor_union
+{
+ usb_descriptor_common_t common; /* Common descriptor */
+ usb_descriptor_device_t device; /* Device descriptor */
+ usb_descriptor_configuration_t configuration; /* Configuration descriptor */
+ usb_descriptor_interface_t interface; /* Interface descriptor */
+ usb_descriptor_endpoint_t endpoint; /* Endpoint descriptor */
+ usb_descriptor_endpoint_companion_t endpointCompanion; /* Endpoint companion descriptor */
+} usb_descriptor_union_t;
+
+#endif /* __USB_SPEC_H__ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/phy/usb_phy.c b/minimal-examples/embedded/rt595/hello_world/project/usb/phy/usb_phy.c
new file mode 100644
index 000000000..4e078b2e7
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/phy/usb_phy.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "usb.h"
+#include "fsl_device_registers.h"
+
+#include "usb_phy.h"
+
+void *USB_EhciPhyGetBase(uint8_t controllerId)
+{
+ void *usbPhyBase = NULL;
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+ uint32_t instance;
+ uint32_t newinstance = 0;
+ uint32_t usbphy_base_temp[] = USBPHY_BASE_ADDRS;
+ uint32_t usbphy_base[] = USBPHY_BASE_ADDRS;
+ uint32_t *temp;
+ if (controllerId < (uint8_t)kUSB_ControllerEhci0)
+ {
+ return NULL;
+ }
+
+ if ((controllerId == (uint8_t)kUSB_ControllerEhci0) || (controllerId == (uint8_t)kUSB_ControllerEhci1))
+ {
+ controllerId = controllerId - (uint8_t)kUSB_ControllerEhci0;
+ }
+ else if ((controllerId == (uint8_t)kUSB_ControllerLpcIp3511Hs0) ||
+ (controllerId == (uint8_t)kUSB_ControllerLpcIp3511Hs1))
+ {
+ controllerId = controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0;
+ }
+ else if ((controllerId == (uint8_t)kUSB_ControllerIp3516Hs0) || (controllerId == (uint8_t)kUSB_ControllerIp3516Hs1))
+ {
+ controllerId = controllerId - (uint8_t)kUSB_ControllerIp3516Hs0;
+ }
+ else
+ {
+ /*no action*/
+ }
+
+ for (instance = 0; instance < (sizeof(usbphy_base_temp) / sizeof(usbphy_base_temp[0])); instance++)
+ {
+ if (0U != usbphy_base_temp[instance])
+ {
+ usbphy_base[newinstance++] = usbphy_base_temp[instance];
+ }
+ }
+ if (controllerId > newinstance)
+ {
+ return NULL;
+ }
+ temp = (uint32_t *)usbphy_base[controllerId];
+ usbPhyBase = (void *)temp;
+#endif
+ return usbPhyBase;
+}
+
+/*!
+ * @brief ehci phy initialization.
+ *
+ * This function initialize ehci phy IP.
+ *
+ * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
+ * @param[in] freq the external input clock.
+ * for example: if the external input clock is 16M, the parameter freq should be 16000000.
+ *
+ * @retval kStatus_USB_Success cancel successfully.
+ * @retval kStatus_USB_Error the freq value is incorrect.
+ */
+uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig)
+{
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+ USBPHY_Type *usbPhyBase;
+
+ usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
+ if (NULL == usbPhyBase)
+ {
+ return (uint8_t)kStatus_USB_Error;
+ }
+
+#if ((defined FSL_FEATURE_SOC_ANATOP_COUNT) && (FSL_FEATURE_SOC_ANATOP_COUNT > 0U))
+ ANATOP->HW_ANADIG_REG_3P0.RW =
+ (ANATOP->HW_ANADIG_REG_3P0.RW &
+ (~(ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x1F) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_ILIMIT_MASK))) |
+ ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x17) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_LINREG_MASK;
+ ANATOP->HW_ANADIG_USB2_CHRG_DETECT.SET =
+ ANATOP_HW_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK | ANATOP_HW_ANADIG_USB2_CHRG_DETECT_EN_B_MASK;
+#endif
+
+#if (defined USB_ANALOG)
+ USB_ANALOG->INSTANCE[controllerId - (uint8_t)kUSB_ControllerEhci0].CHRG_DETECT_SET =
+ USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(1) | USB_ANALOG_CHRG_DETECT_EN_B(1);
+#endif
+
+#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
+
+ usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
+#endif
+ usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */
+ usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */
+ /* PWD register provides overall control of the PHY power state */
+ usbPhyBase->PWD = 0U;
+ if (((uint8_t)kUSB_ControllerIp3516Hs0 == controllerId) || ((uint8_t)kUSB_ControllerIp3516Hs1 == controllerId) ||
+ ((uint8_t)kUSB_ControllerLpcIp3511Hs0 == controllerId) ||
+ ((uint8_t)kUSB_ControllerLpcIp3511Hs1 == controllerId))
+ {
+ usbPhyBase->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK;
+ usbPhyBase->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK;
+ }
+ if (NULL != phyConfig)
+ {
+ /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */
+ usbPhyBase->TX =
+ ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) |
+ (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) |
+ USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM)));
+ }
+#endif
+
+ return (uint8_t)kStatus_USB_Success;
+}
+
+/*!
+ * @brief ehci phy initialization for suspend and resume.
+ *
+ * This function initialize ehci phy IP for suspend and resume.
+ *
+ * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
+ * @param[in] freq the external input clock.
+ * for example: if the external input clock is 16M, the parameter freq should be 16000000.
+ *
+ * @retval kStatus_USB_Success cancel successfully.
+ * @retval kStatus_USB_Error the freq value is incorrect.
+ */
+uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig)
+{
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+ USBPHY_Type *usbPhyBase;
+
+ usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
+ if (NULL == usbPhyBase)
+ {
+ return (uint8_t)kStatus_USB_Error;
+ }
+
+#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
+ usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
+#endif
+
+#if ((defined USBPHY_CTRL_AUTORESUME_EN_MASK) && (USBPHY_CTRL_AUTORESUME_EN_MASK > 0U))
+ usbPhyBase->CTRL_CLR |= USBPHY_CTRL_AUTORESUME_EN_MASK;
+#else
+ usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK;
+#endif
+ usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK;
+ usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */
+ usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */
+ /* PWD register provides overall control of the PHY power state */
+ usbPhyBase->PWD = 0U;
+#if (defined USBPHY_ANACTRL_PFD_CLKGATE_MASK)
+ /* now the 480MHz USB clock is up, then configure fractional divider after PLL with PFD
+ * pfd clock = 480MHz*18/N, where N=18~35
+ * Please note that USB1PFDCLK has to be less than 180MHz for RUN or HSRUN mode
+ */
+ usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24); /* N=24 */
+ usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(1); /* div by 4 */
+
+ usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK;
+ usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK;
+ while (0U == (usbPhyBase->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK))
+ {
+ }
+#endif
+ if (NULL != phyConfig)
+ {
+ /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */
+ usbPhyBase->TX =
+ ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) |
+ (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) |
+ USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM)));
+ }
+#endif
+
+ return (uint8_t)kStatus_USB_Success;
+}
+
+/*!
+ * @brief ehci phy de-initialization.
+ *
+ * This function de-initialize ehci phy IP.
+ *
+ * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
+ */
+void USB_EhciPhyDeinit(uint8_t controllerId)
+{
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+ USBPHY_Type *usbPhyBase;
+
+ usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
+ if (NULL == usbPhyBase)
+ {
+ return;
+ }
+#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
+ usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* power down PLL */
+ usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* disable USB clock output from USB PHY PLL */
+#endif
+ usbPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* set to 1U to gate clocks */
+#endif
+}
+
+/*!
+ * @brief ehci phy disconnect detection enable or disable.
+ *
+ * This function enable/disable host ehci disconnect detection.
+ *
+ * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
+ * @param[in] enable
+ * 1U - enable;
+ * 0U - disable;
+ */
+void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable)
+{
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+ USBPHY_Type *usbPhyBase;
+
+ usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
+ if (NULL == usbPhyBase)
+ {
+ return;
+ }
+
+ if (0U != enable)
+ {
+ usbPhyBase->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK;
+ }
+ else
+ {
+ usbPhyBase->CTRL &= (~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK);
+ }
+#endif
+}
+
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U))
+void USB_PhyDeviceForceEnterFSMode(uint8_t controllerId, uint8_t enable)
+{
+ USBPHY_Type *usbPhyBase;
+
+ usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
+ if (NULL == usbPhyBase)
+ {
+ return;
+ }
+
+ if (0U != enable)
+ {
+ uint32_t delay = 1000000;
+ usbPhyBase->DEBUG0_CLR = USBPHY_DEBUG0_CLKGATE_MASK;
+ while ((0U != (usbPhyBase->USB1_VBUS_DET_STAT & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)) && (0U != delay))
+ {
+ delay--;
+ }
+ usbPhyBase->USB1_LOOPBACK_SET = USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK;
+ }
+ else
+ {
+ usbPhyBase->DEBUG0_CLR = USBPHY_DEBUG0_CLKGATE_MASK;
+ usbPhyBase->USB1_LOOPBACK_CLR = USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK;
+ }
+}
+#endif
+#endif
diff --git a/minimal-examples/embedded/rt595/hello_world/project/usb/phy/usb_phy.h b/minimal-examples/embedded/rt595/hello_world/project/usb/phy/usb_phy.h
new file mode 100644
index 000000000..014740711
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/usb/phy/usb_phy.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __USB_PHY_H__
+#define __USB_PHY_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+typedef struct _usb_phy_config_struct
+{
+ uint8_t D_CAL; /* Decode to trim the nominal 17.78mA current source */
+ uint8_t TXCAL45DP; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DP output pin */
+ uint8_t TXCAL45DM; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DM output pin */
+} usb_phy_config_struct_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+/*!
+ * @brief EHCI PHY get USB phy bass address.
+ *
+ * This function is used to get USB phy bass address.
+ *
+ * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t.
+ *
+ * @retval USB phy bass address.
+ */
+extern void *USB_EhciPhyGetBase(uint8_t controllerId);
+
+/*!
+ * @brief EHCI PHY initialization.
+ *
+ * This function initializes the EHCI PHY IP.
+ *
+ * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t.
+ * @param[in] freq The external input clock.
+ *
+ * @retval kStatus_USB_Success Cancel successfully.
+ * @retval kStatus_USB_Error The freq value is incorrect.
+ */
+extern uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig);
+
+/*!
+ * @brief ehci phy initialization for suspend and resume.
+ *
+ * This function initialize ehci phy IP for suspend and resume.
+ *
+ * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
+ * @param[in] freq the external input clock.
+ * for example: if the external input clock is 16M, the parameter freq should be 16000000.
+ *
+ * @retval kStatus_USB_Success cancel successfully.
+ * @retval kStatus_USB_Error the freq value is incorrect.
+ */
+extern uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig);
+
+/*!
+ * @brief EHCI PHY deinitialization.
+ *
+ * This function deinitializes the EHCI PHY IP.
+ *
+ * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t.
+ */
+extern void USB_EhciPhyDeinit(uint8_t controllerId);
+
+/*!
+ * @brief EHCI PHY disconnect detection enable or disable.
+ *
+ * This function enable/disable the host EHCI disconnect detection.
+ *
+ * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t.
+ * @param[in] enable
+ * 1U - enable;
+ * 0U - disable;
+ */
+extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable);
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U))
+/*!
+ * @brief Force the PHY enter FS Mode
+ *
+ * on RT500 and RT600, the device doesn't enter FS Mode after vbus is invalide and the controller works as HS.
+ *
+ * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t.
+ * @param[in] enable
+ * 1U - enable;
+ * 0U - disable;
+ */
+extern void USB_PhyDeviceForceEnterFSMode(uint8_t controllerId, uint8_t enable);
+#endif
+#endif
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __USB_PHY_H__ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/utilities/fsl_assert.c b/minimal-examples/embedded/rt595/hello_world/project/utilities/fsl_assert.c
new file mode 100644
index 000000000..d2cbe28ef
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/utilities/fsl_assert.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+
+#ifndef NDEBUG
+#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__))
+void __aeabi_assert(const char *failedExpr, const char *file, int line)
+{
+#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE
+ PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+#else
+ (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+#endif
+
+ for (;;)
+ {
+ __BKPT(0);
+ }
+}
+#elif (defined(__GNUC__))
+#if defined(__REDLIB__)
+void __assertion_failed(char *failedExpr)
+{
+ (void)PRINTF("ASSERT ERROR \" %s \n", failedExpr);
+ for (;;)
+ {
+ __BKPT(0);
+ }
+}
+#else
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+ (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line,
+ func);
+ for (;;)
+ {
+ __BKPT(0);
+ }
+}
+#endif /* defined(__REDLIB__) */
+#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */
+#endif /* NDEBUG */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/utilities/fsl_debug_console.c b/minimal-examples/embedded/rt595/hello_world/project/utilities/fsl_debug_console.c
new file mode 100644
index 000000000..790610fba
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/utilities/fsl_debug_console.c
@@ -0,0 +1,1877 @@
+/*
+ * Copyright 2017-2018, 2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdarg.h>
+#include <stdlib.h>
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#include <stdio.h>
+#endif
+#include <math.h>
+#include "fsl_debug_console.h"
+#include "fsl_adapter_uart.h"
+
+/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */
+#if defined(__CC_ARM)
+#pragma diag_suppress 1256
+#endif /* __CC_ARM */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief This definition is maximum line that debugconsole can scanf each time.*/
+#define IO_MAXLINE 20U
+
+/*! @brief The overflow value.*/
+#ifndef HUGE_VAL
+#define HUGE_VAL (99.e99)
+#endif /* HUGE_VAL */
+
+/*! @brief State structure storing debug console. */
+typedef struct DebugConsoleState
+{
+ uint8_t uartHandleBuffer[HAL_UART_HANDLE_SIZE];
+ hal_uart_status_t (*putChar)(hal_uart_handle_t handle,
+ const uint8_t *data,
+ size_t length); /*!< put char function pointer */
+ hal_uart_status_t (*getChar)(hal_uart_handle_t handle,
+ uint8_t *data,
+ size_t length); /*!< get char function pointer */
+ serial_port_type_t type; /*!< The initialized port of the debug console. */
+} debug_console_state_t;
+
+/*! @brief Type of KSDK printf function pointer. */
+typedef int (*PUTCHAR_FUNC)(int a);
+
+#if PRINTF_ADVANCED_ENABLE
+/*! @brief Specification modifier flags for printf. */
+enum _debugconsole_printf_flag
+{
+ kPRINTF_Minus = 0x01U, /*!< Minus FLag. */
+ kPRINTF_Plus = 0x02U, /*!< Plus Flag. */
+ kPRINTF_Space = 0x04U, /*!< Space Flag. */
+ kPRINTF_Zero = 0x08U, /*!< Zero Flag. */
+ kPRINTF_Pound = 0x10U, /*!< Pound Flag. */
+ kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */
+ kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */
+ kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */
+ kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */
+};
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Specification modifier flags for scanf. */
+enum _debugconsole_scanf_flag
+{
+ kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */
+ kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */
+ kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */
+ kSCANF_DestString = 0x8U, /*!< Destination String FLag. */
+ kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */
+ kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */
+ kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */
+ kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */
+#if SCANF_ADVANCED_ENABLE
+ kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */
+ kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */
+ kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */
+ kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */
+#endif /* SCANF_ADVANCED_ENABLE */
+#if SCANF_FLOAT_ENABLE
+ kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */
+#endif /*SCANF_FLOAT_ENABLE */
+ kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Debug UART state information. */
+static debug_console_state_t s_debugConsole;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if SDK_DEBUGCONSOLE
+static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt, va_list ap);
+static int DbgConsole_ScanfFormattedData(const char *line_ptr, char *format, va_list args_ptr);
+#endif /* SDK_DEBUGCONSOLE */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/
+
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq)
+{
+ hal_uart_config_t usrtConfig;
+
+ if (kSerialPort_Uart != device)
+ {
+ return kStatus_Fail;
+ }
+
+ /* Set debug console to initialized to avoid duplicated initialized operation. */
+ s_debugConsole.type = device;
+
+ usrtConfig.srcClock_Hz = clkSrcFreq;
+ usrtConfig.baudRate_Bps = baudRate;
+ usrtConfig.parityMode = kHAL_UartParityDisabled;
+ usrtConfig.stopBitCount = kHAL_UartOneStopBit;
+ usrtConfig.enableRx = 1U;
+ usrtConfig.enableTx = 1U;
+ usrtConfig.enableRxRTS = 0U;
+ usrtConfig.enableTxCTS = 0U;
+ usrtConfig.instance = instance;
+#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
+ usrtConfig.txFifoWatermark = 0U;
+ usrtConfig.rxFifoWatermark = 0U;
+#endif
+ /* Enable clock and initial UART module follow user configure structure. */
+ (void)HAL_UartInit((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], &usrtConfig);
+ /* Set the function pointer for send and receive for this kind of device. */
+ s_debugConsole.putChar = HAL_UartSendBlocking;
+ s_debugConsole.getChar = HAL_UartReceiveBlocking;
+
+ return kStatus_Success;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Deinit(void)
+{
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return kStatus_Success;
+ }
+
+ (void)HAL_UartDeinit((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0]);
+
+ s_debugConsole.type = kSerialPort_None;
+
+ return kStatus_Success;
+}
+#endif /* DEBUGCONSOLE_REDIRECT_TO_SDK */
+
+#if SDK_DEBUGCONSOLE
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Printf(const char *fmt_s, ...)
+{
+ va_list ap;
+ int result;
+
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+ va_start(ap, fmt_s);
+ result = DbgConsole_PrintfFormattedData(DbgConsole_Putchar, fmt_s, ap);
+ va_end(ap);
+
+ return result;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Putchar(int ch)
+{
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+ (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1);
+
+ return 1;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Scanf(char *fmt_ptr, ...)
+{
+ /* Plus one to store end of string char */
+ char temp_buf[IO_MAXLINE + 1];
+ va_list ap;
+ int32_t i;
+ char result;
+
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+ va_start(ap, fmt_ptr);
+ temp_buf[0] = '\0';
+
+ i = 0;
+ while (true)
+ {
+ if (i >= (int32_t)IO_MAXLINE)
+ {
+ break;
+ }
+
+ result = (char)DbgConsole_Getchar();
+ temp_buf[i] = result;
+
+ if ((result == '\r') || (result == '\n'))
+ {
+ /* End of Line. */
+ if (i == 0)
+ {
+ temp_buf[i] = '\0';
+ i = -1;
+ }
+ else
+ {
+ break;
+ }
+ }
+
+ i++;
+ }
+
+ if (i == (int32_t)IO_MAXLINE)
+ {
+ temp_buf[i] = '\0';
+ }
+ else
+ {
+ temp_buf[i + 1] = '\0';
+ }
+ result = (char)DbgConsole_ScanfFormattedData(temp_buf, fmt_ptr, ap);
+ va_end(ap);
+
+ return (int)result;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Getchar(void)
+{
+ char ch;
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+ while (kStatus_HAL_UartSuccess !=
+ s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1))
+ {
+ return -1;
+ }
+
+ return (int)ch;
+}
+
+/*************Code for process formatted data*******************************/
+/*!
+ * @brief Scanline function which ignores white spaces.
+ *
+ * @param[in] s The address of the string pointer to update.
+ * @return String without white spaces.
+ */
+static uint32_t DbgConsole_ScanIgnoreWhiteSpace(const char **s)
+{
+ uint8_t count = 0;
+ char c;
+
+ c = **s;
+ while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f'))
+ {
+ count++;
+ (*s)++;
+ c = **s;
+ }
+ return count;
+}
+
+/*!
+ * @brief This function puts padding character.
+ *
+ * @param[in] c Padding character.
+ * @param[in] curlen Length of current formatted string .
+ * @param[in] width Width of expected formatted string.
+ * @param[in] count Number of characters.
+ * @param[in] func_ptr Function to put character out.
+ */
+static void DbgConsole_PrintfPaddingCharacter(
+ char c, int32_t curlen, int32_t width, int32_t *count, PUTCHAR_FUNC func_ptr)
+{
+ int32_t i;
+
+ for (i = curlen; i < width; i++)
+ {
+ (void)func_ptr(c);
+ (*count)++;
+ }
+}
+
+/*!
+ * @brief Converts a radix number to a string and return its length.
+ *
+ * @param[in] numstr Converted string of the number.
+ * @param[in] nump Pointer to the number.
+ * @param[in] neg Polarity of the number.
+ * @param[in] radix The radix to be converted to.
+ * @param[in] use_caps Used to identify %x/X output format.
+
+ * @return Length of the converted string.
+ */
+static int32_t DbgConsole_ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps)
+{
+#if PRINTF_ADVANCED_ENABLE
+ int64_t a;
+ int64_t b;
+ int64_t c;
+
+ uint64_t ua;
+ uint64_t ub;
+ uint64_t uc;
+#else
+ int32_t a;
+ int32_t b;
+ int32_t c;
+
+ uint32_t ua;
+ uint32_t ub;
+ uint32_t uc;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+ int32_t nlen;
+ char *nstrp;
+
+ nlen = 0;
+ nstrp = numstr;
+ *nstrp++ = '\0';
+
+#if !(PRINTF_ADVANCED_ENABLE > 0)
+ neg = 0;
+#endif
+
+ if (0 != neg)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ a = *(int64_t *)nump;
+#else
+ a = *(int32_t *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ if (a == 0)
+ {
+ *nstrp = '0';
+ ++nlen;
+ return nlen;
+ }
+ while (a != 0)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ b = (int64_t)a / (int64_t)radix;
+ c = (int64_t)a - ((int64_t)b * (int64_t)radix);
+ if (c < 0)
+ {
+ c = (int64_t)'0' - c;
+ }
+#else
+ b = a / radix;
+ c = a - (b * radix);
+ if (c < 0)
+ {
+ c = (int32_t)'0' - c;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ else
+ {
+ c = c + '0';
+ }
+ a = b;
+ *nstrp++ = (char)c;
+ ++nlen;
+ }
+ }
+ else
+ {
+#if PRINTF_ADVANCED_ENABLE
+ ua = *(uint64_t *)nump;
+#else
+ ua = *(uint32_t *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ if (ua == 0U)
+ {
+ *nstrp = '0';
+ ++nlen;
+ return nlen;
+ }
+ while (ua != 0U)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ ub = (uint64_t)ua / (uint64_t)radix;
+ uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix);
+#else
+ ub = ua / (uint32_t)radix;
+ uc = ua - (ub * (uint32_t)radix);
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+ if (uc < 10U)
+ {
+ uc = uc + '0';
+ }
+ else
+ {
+ uc = uc - 10U + (use_caps ? 'A' : 'a');
+ }
+ ua = ub;
+ *nstrp++ = (char)uc;
+ ++nlen;
+ }
+ }
+ return nlen;
+}
+
+#if PRINTF_FLOAT_ENABLE
+/*!
+ * @brief Converts a floating radix number to a string and return its length.
+ *
+ * @param[in] numstr Converted string of the number.
+ * @param[in] nump Pointer to the number.
+ * @param[in] radix The radix to be converted to.
+ * @param[in] precision_width Specify the precision width.
+
+ * @return Length of the converted string.
+ */
+static int32_t DbgConsole_ConvertFloatRadixNumToString(char *numstr,
+ void *nump,
+ int32_t radix,
+ uint32_t precision_width)
+{
+ int32_t a;
+ int32_t b;
+ int32_t c;
+ uint32_t i;
+ double fa;
+ double dc;
+ double fb;
+ double r;
+ double fractpart;
+ double intpart;
+
+ int32_t nlen;
+ char *nstrp;
+ nlen = 0;
+ nstrp = numstr;
+ *nstrp++ = '\0';
+ r = *(double *)nump;
+ if (0.0 == r)
+ {
+ *nstrp = '0';
+ ++nlen;
+ return nlen;
+ }
+ fractpart = modf((double)r, (double *)&intpart);
+ /* Process fractional part. */
+ for (i = 0; i < precision_width; i++)
+ {
+ fractpart *= (double)radix;
+ }
+ if (r >= 0.0)
+ {
+ fa = fractpart + (double)0.5;
+ if (fa >= pow((double)10, (double)precision_width))
+ {
+ intpart++;
+ }
+ }
+ else
+ {
+ fa = fractpart - (double)0.5;
+ if (fa <= -pow((double)10, (double)precision_width))
+ {
+ intpart--;
+ }
+ }
+ for (i = 0; i < precision_width; i++)
+ {
+ fb = fa / (double)radix;
+ dc = (fa - (double)(int64_t)fb * (double)radix);
+ c = (int32_t)dc;
+ if (c < 0)
+ {
+ c = (int32_t)'0' - c;
+ }
+ else
+ {
+ c = c + '0';
+ }
+ fa = fb;
+ *nstrp++ = (char)c;
+ ++nlen;
+ }
+ *nstrp++ = (char)'.';
+ ++nlen;
+ a = (int32_t)intpart;
+ if (a == 0)
+ {
+ *nstrp++ = '0';
+ ++nlen;
+ }
+ else
+ {
+ while (a != 0)
+ {
+ b = (int32_t)a / (int32_t)radix;
+ c = (int32_t)a - ((int32_t)b * (int32_t)radix);
+ if (c < 0)
+ {
+ c = (int32_t)'0' - c;
+ }
+ else
+ {
+ c = c + '0';
+ }
+ a = b;
+ *nstrp++ = (char)c;
+ ++nlen;
+ }
+ }
+ return nlen;
+}
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*!
+ * @brief This function outputs its parameters according to a formatted string.
+ *
+ * @note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * @param[in] func_ptr Function to put character out.
+ * @param[in] fmt_ptr Format string for printf.
+ * @param[in] args_ptr Arguments to printf.
+ *
+ * @return Number of characters
+ */
+static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt, va_list ap)
+{
+ /* va_list ap; */
+ const char *p;
+ char c;
+
+ char vstr[33];
+ char *vstrp = NULL;
+ int32_t vlen = 0;
+
+ bool done;
+ int32_t count = 0;
+
+ uint32_t field_width;
+ uint32_t precision_width;
+ char *sval;
+ int32_t cval;
+ bool use_caps;
+ uint8_t radix = 0;
+
+#if PRINTF_ADVANCED_ENABLE
+ uint32_t flags_used;
+ char schar;
+ bool dschar;
+ int64_t ival;
+ uint64_t uval = 0;
+ bool valid_precision_width;
+#else
+ int32_t ival;
+ uint32_t uval = 0;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if PRINTF_FLOAT_ENABLE
+ double fval;
+#endif /* PRINTF_FLOAT_ENABLE */
+
+ /* Start parsing apart the format string and display appropriate formats and data. */
+ p = fmt;
+ while (true)
+ {
+ if ('\0' == *p)
+ {
+ break;
+ }
+ c = *p;
+ /*
+ * All formats begin with a '%' marker. Special chars like
+ * '\n' or '\t' are normally converted to the appropriate
+ * character by the __compiler__. Thus, no need for this
+ * routine to account for the '\' character.
+ */
+ if (c != '%')
+ {
+ (void)func_ptr(c);
+ count++;
+ p++;
+ /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */
+ continue;
+ }
+
+ use_caps = true;
+
+#if PRINTF_ADVANCED_ENABLE
+ /* First check for specification modifier flags. */
+ flags_used = 0;
+ done = false;
+ while (!done)
+ {
+ switch (*++p)
+ {
+ case '-':
+ flags_used |= (uint32_t)kPRINTF_Minus;
+ break;
+ case '+':
+ flags_used |= (uint32_t)kPRINTF_Plus;
+ break;
+ case ' ':
+ flags_used |= (uint32_t)kPRINTF_Space;
+ break;
+ case '0':
+ flags_used |= (uint32_t)kPRINTF_Zero;
+ break;
+ case '#':
+ flags_used |= (uint32_t)kPRINTF_Pound;
+ break;
+ default:
+ /* We've gone one char too far. */
+ --p;
+ done = true;
+ break;
+ }
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+ /* Next check for minimum field width. */
+ field_width = 0;
+ done = false;
+ while (!done)
+ {
+ c = *++p;
+ if ((c >= '0') && (c <= '9'))
+ {
+ field_width = (field_width * 10U) + ((uint32_t)c - (uint32_t)'0');
+ }
+#if PRINTF_ADVANCED_ENABLE
+ else if (c == '*')
+ {
+ field_width = (uint32_t)va_arg(ap, uint32_t);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ else
+ {
+ /* We've gone one char too far. */
+ --p;
+ done = true;
+ }
+ }
+ /* Next check for the width and precision field separator. */
+#if (PRINTF_ADVANCED_ENABLE || PRINTF_FLOAT_ENABLE)
+ precision_width = 6U; /* MISRA C-2012 Rule 2.2 */
+#endif
+#if PRINTF_ADVANCED_ENABLE
+ valid_precision_width = false;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ if (*++p == '.')
+ {
+ /* Must get precision field width, if present. */
+ precision_width = 0U;
+ done = false;
+ while (!done)
+ {
+ c = *++p;
+ if ((c >= '0') && (c <= '9'))
+ {
+ precision_width = (precision_width * 10U) + ((uint32_t)c - (uint32_t)'0');
+#if PRINTF_ADVANCED_ENABLE
+ valid_precision_width = true;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+#if PRINTF_ADVANCED_ENABLE
+ else if (c == '*')
+ {
+ precision_width = (uint32_t)va_arg(ap, uint32_t);
+ valid_precision_width = true;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ else
+ {
+ /* We've gone one char too far. */
+ --p;
+ done = true;
+ }
+ }
+ }
+ else
+ {
+ /* We've gone one char too far. */
+ --p;
+ }
+#if PRINTF_ADVANCED_ENABLE
+ /*
+ * Check for the length modifier.
+ */
+ switch (/* c = */ *++p)
+ {
+ case 'h':
+ if (*++p != 'h')
+ {
+ flags_used |= (uint32_t)kPRINTF_LengthShortInt;
+ --p;
+ }
+ else
+ {
+ flags_used |= (uint32_t)kPRINTF_LengthChar;
+ }
+ break;
+ case 'l':
+ if (*++p != 'l')
+ {
+ flags_used |= (uint32_t)kPRINTF_LengthLongInt;
+ --p;
+ }
+ else
+ {
+ flags_used |= (uint32_t)kPRINTF_LengthLongLongInt;
+ }
+ break;
+ default:
+ /* we've gone one char too far */
+ --p;
+ break;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ /* Now we're ready to examine the format. */
+ c = *++p;
+ {
+ if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') ||
+ (c == 'b') || (c == 'p') || (c == 'u'))
+ {
+ if ((c == 'd') || (c == 'i'))
+ {
+#if PRINTF_ADVANCED_ENABLE
+ if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt))
+ {
+ ival = (int64_t)va_arg(ap, int64_t);
+ }
+ else
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ ival = (int32_t)va_arg(ap, int32_t);
+ }
+ vlen = DbgConsole_ConvertRadixNumToString(vstr, &ival, 1, 10, use_caps);
+ vstrp = &vstr[vlen];
+#if PRINTF_ADVANCED_ENABLE
+ if (ival < 0)
+ {
+ schar = '-';
+ ++vlen;
+ }
+ else
+ {
+ if (0U != (flags_used & (uint32_t)kPRINTF_Plus))
+ {
+ schar = '+';
+ ++vlen;
+ }
+ else
+ {
+ if (0U != (flags_used & (uint32_t)kPRINTF_Space))
+ {
+ schar = ' ';
+ ++vlen;
+ }
+ else
+ {
+ schar = '\0';
+ }
+ }
+ }
+ dschar = false;
+ /* Do the ZERO pad. */
+ if (0U != (flags_used & (uint32_t)kPRINTF_Zero))
+ {
+ if ('\0' != schar)
+ {
+ (void)func_ptr(schar);
+ count++;
+ }
+ dschar = true;
+
+ DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr);
+ vlen = (int32_t)field_width;
+ }
+ else
+ {
+ if (0U == (flags_used & (uint32_t)kPRINTF_Minus))
+ {
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+ if ('\0' != schar)
+ {
+ (void)func_ptr(schar);
+ count++;
+ }
+ dschar = true;
+ }
+ }
+ /* The string was built in reverse order, now display in correct order. */
+ if ((!dschar) && ('\0' != schar))
+ {
+ (void)func_ptr(schar);
+ count++;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+
+#if PRINTF_FLOAT_ENABLE
+ if ((c == 'f') || (c == 'F'))
+ {
+ fval = (double)va_arg(ap, double);
+ vlen = DbgConsole_ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width);
+ vstrp = &vstr[vlen];
+
+#if PRINTF_ADVANCED_ENABLE
+ if (fval < 0.0)
+ {
+ schar = '-';
+ ++vlen;
+ }
+ else
+ {
+ if (0U != (flags_used & (uint32_t)kPRINTF_Plus))
+ {
+ schar = '+';
+ ++vlen;
+ }
+ else
+ {
+ if (0U != (flags_used & (uint32_t)kPRINTF_Space))
+ {
+ schar = ' ';
+ ++vlen;
+ }
+ else
+ {
+ schar = '\0';
+ }
+ }
+ }
+ dschar = false;
+ if (0U != (flags_used & (uint32_t)kPRINTF_Zero))
+ {
+ if ('\0' != schar)
+ {
+ (void)func_ptr(schar);
+ count++;
+ }
+ dschar = true;
+ DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr);
+ vlen = (int32_t)field_width;
+ }
+ else
+ {
+ if (0U == (flags_used & (uint32_t)kPRINTF_Minus))
+ {
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+ if ('\0' != schar)
+ {
+ (void)func_ptr(schar);
+ count++;
+ }
+ dschar = true;
+ }
+ }
+ if ((!dschar) && ('\0' != schar))
+ {
+ (void)func_ptr(schar);
+ count++;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+#endif /* PRINTF_FLOAT_ENABLE */
+ if ((c == 'X') || (c == 'x'))
+ {
+ if (c == 'x')
+ {
+ use_caps = false;
+ }
+#if PRINTF_ADVANCED_ENABLE
+ if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt))
+ {
+ uval = (uint64_t)va_arg(ap, uint64_t);
+ }
+ else
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ uval = (uint32_t)va_arg(ap, uint32_t);
+ }
+ vlen = DbgConsole_ConvertRadixNumToString(vstr, &uval, 0, 16, use_caps);
+ vstrp = &vstr[vlen];
+
+#if PRINTF_ADVANCED_ENABLE
+ dschar = false;
+ if (0U != (flags_used & (uint32_t)kPRINTF_Zero))
+ {
+ if (0U != (flags_used & (uint32_t)kPRINTF_Pound))
+ {
+ (void)func_ptr('0');
+ (void)func_ptr((use_caps ? 'X' : 'x'));
+ count += 2;
+ /*vlen += 2;*/
+ dschar = true;
+ }
+ DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr);
+ vlen = (int32_t)field_width;
+ }
+ else
+ {
+ if (0U == (flags_used & (uint32_t)kPRINTF_Pound))
+ {
+ if (0U != (flags_used & (uint32_t)kPRINTF_Pound))
+ {
+ vlen += 2;
+ }
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+ if (0U != (flags_used & (uint32_t)kPRINTF_Pound))
+ {
+ (void)func_ptr('0');
+ (void)func_ptr(use_caps ? 'X' : 'x');
+ count += 2;
+
+ dschar = true;
+ }
+ }
+ }
+
+ if ((0U != (flags_used & (uint32_t)kPRINTF_Pound)) && (!dschar))
+ {
+ (void)func_ptr('0');
+ (void)func_ptr(use_caps ? 'X' : 'x');
+ count += 2;
+ vlen += 2;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+ if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u'))
+ {
+#if PRINTF_ADVANCED_ENABLE
+ if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt))
+ {
+ uval = (uint64_t)va_arg(ap, uint64_t);
+ }
+ else
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ uval = (uint32_t)va_arg(ap, uint32_t);
+ }
+ switch (c)
+ {
+ case 'o':
+ radix = 8;
+ break;
+ case 'b':
+ radix = 2;
+ break;
+ case 'p':
+ radix = 16;
+ break;
+ case 'u':
+ radix = 10;
+ break;
+ default:
+ /* MISRA C-2012 Rule 16.4 */
+ break;
+ }
+ vlen = DbgConsole_ConvertRadixNumToString(vstr, &uval, 0, (int32_t)radix, use_caps);
+ vstrp = &vstr[vlen];
+#if PRINTF_ADVANCED_ENABLE
+ if (0U != (flags_used & (uint32_t)kPRINTF_Zero))
+ {
+ DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr);
+ vlen = (int32_t)field_width;
+ }
+ else
+ {
+ if (0U == (flags_used & (uint32_t)kPRINTF_Minus))
+ {
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+ }
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+#if !PRINTF_ADVANCED_ENABLE
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+#endif /* !PRINTF_ADVANCED_ENABLE */
+ if (vstrp != NULL)
+ {
+ while ('\0' != *vstrp)
+ {
+ (void)func_ptr(*vstrp--);
+ count++;
+ }
+ }
+#if PRINTF_ADVANCED_ENABLE
+ if (0U != (flags_used & (uint32_t)kPRINTF_Minus))
+ {
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+ else if (c == 'c')
+ {
+ cval = (int32_t)va_arg(ap, uint32_t);
+ (void)func_ptr(cval);
+ count++;
+ }
+ else if (c == 's')
+ {
+ sval = (char *)va_arg(ap, char *);
+ if (NULL != sval)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ if (valid_precision_width)
+ {
+ vlen = (int32_t)precision_width;
+ }
+ else
+ {
+ vlen = (int32_t)strlen(sval);
+ }
+#else
+ vlen = (int32_t)strlen(sval);
+#endif /* PRINTF_ADVANCED_ENABLE */
+#if PRINTF_ADVANCED_ENABLE
+ if (0U == (flags_used & (uint32_t)kPRINTF_Minus))
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+ }
+
+#if PRINTF_ADVANCED_ENABLE
+ if (valid_precision_width)
+ {
+ while (('\0' != *sval) && (vlen > 0))
+ {
+ (void)func_ptr(*sval++);
+ count++;
+ vlen--;
+ }
+ /* In case that vlen sval is shorter than vlen */
+ vlen = (int32_t)precision_width - vlen;
+ }
+ else
+ {
+#endif /* PRINTF_ADVANCED_ENABLE */
+ while ('\0' != *sval)
+ {
+ (void)func_ptr(*sval++);
+ count++;
+ }
+#if PRINTF_ADVANCED_ENABLE
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if PRINTF_ADVANCED_ENABLE
+ if (0U != (flags_used & (uint32_t)kPRINTF_Minus))
+ {
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+ }
+ else
+ {
+ (void)func_ptr(c);
+ count++;
+ }
+ }
+ p++;
+ }
+ return count;
+}
+
+/*!
+ * @brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * @param[in] line_ptr The input line of ASCII data.
+ * @param[in] format Format first points to the format string.
+ * @param[in] args_ptr The list of parameters.
+ *
+ * @return Number of input items converted and assigned.
+ * @retval IO_EOF When line_ptr is empty string "".
+ */
+static int DbgConsole_ScanfFormattedData(const char *line_ptr, char *format, va_list args_ptr)
+{
+ uint8_t base;
+ int8_t neg;
+ /* Identifier for the format string. */
+ char *c = format;
+ char temp;
+ char *buf;
+ /* Flag telling the conversion specification. */
+ uint32_t flag = 0;
+ /* Filed width for the matching input streams. */
+ uint32_t field_width;
+ /* How many arguments are assigned except the suppress. */
+ uint32_t nassigned = 0;
+ bool match_failure = false;
+ /* How many characters are read from the input streams. */
+ uint32_t n_decode = 0;
+
+ int32_t val;
+
+ const char *s;
+ /* Identifier for the input string. */
+ const char *p = line_ptr;
+
+#if SCANF_FLOAT_ENABLE
+ double fnum = 0.0;
+#endif /* SCANF_FLOAT_ENABLE */
+
+ /* Return EOF error before any conversion. */
+ if (*p == '\0')
+ {
+ return -1;
+ }
+
+ /* Decode directives. */
+ while (('\0' != (*c)) && ('\0' != (*p)))
+ {
+ /* Ignore all white-spaces in the format strings. */
+ if (0U != DbgConsole_ScanIgnoreWhiteSpace((const char **)(void *)&c))
+ {
+ n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);
+ }
+ else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%')))
+ {
+ /* Ordinary characters. */
+ c++;
+ if (*p == *c)
+ {
+ n_decode++;
+ p++;
+ c++;
+ }
+ else
+ {
+ /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream.
+ * However, it is deserted now. */
+ break;
+ }
+ }
+ else
+ {
+ /* convernsion specification */
+ c++;
+ /* Reset. */
+ flag = 0;
+ field_width = 0;
+ base = 0;
+
+ /* Loop to get full conversion specification. */
+ while (('\0' != *c) && (0U == (flag & (uint32_t)kSCANF_DestMask)))
+ {
+ switch (*c)
+ {
+#if SCANF_ADVANCED_ENABLE
+ case '*':
+ if (0U != (flag & (uint32_t)kSCANF_Suppress))
+ {
+ /* Match failure. */
+ match_failure = true;
+ break;
+ }
+ flag |= (uint32_t)kSCANF_Suppress;
+ c++;
+ break;
+ case 'h':
+ if (0U != (flag & (uint32_t)kSCANF_LengthMask))
+ {
+ /* Match failure. */
+ match_failure = true;
+ break;
+ }
+
+ if (c[1] == 'h')
+ {
+ flag |= (uint32_t)kSCANF_LengthChar;
+ c++;
+ }
+ else
+ {
+ flag |= (uint32_t)kSCANF_LengthShortInt;
+ }
+ c++;
+ break;
+ case 'l':
+ if (0U != (flag & (uint32_t)kSCANF_LengthMask))
+ {
+ /* Match failure. */
+ match_failure = true;
+ break;
+ }
+
+ if (c[1] == 'l')
+ {
+ flag |= (uint32_t)kSCANF_LengthLongLongInt;
+ c++;
+ }
+ else
+ {
+ flag |= (uint32_t)kSCANF_LengthLongInt;
+ }
+ c++;
+ break;
+#endif /* SCANF_ADVANCED_ENABLE */
+#if SCANF_FLOAT_ENABLE
+ case 'L':
+ if (flag & (uint32_t)kSCANF_LengthMask)
+ {
+ /* Match failure. */
+ match_failure = true;
+ break;
+ }
+ flag |= (uint32_t)kSCANF_LengthLongLongDouble;
+ c++;
+ break;
+#endif /* SCANF_FLOAT_ENABLE */
+ case '0':
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+ if (0U != field_width)
+ {
+ /* Match failure. */
+ match_failure = true;
+ break;
+ }
+ do
+ {
+ field_width = field_width * 10U + ((uint32_t)*c - (uint32_t)'0');
+ c++;
+ } while ((*c >= '0') && (*c <= '9'));
+ break;
+ case 'd':
+ base = 10;
+ flag |= (uint32_t)kSCANF_TypeSinged;
+ flag |= (uint32_t)kSCANF_DestInt;
+ c++;
+ break;
+ case 'u':
+ base = 10;
+ flag |= (uint32_t)kSCANF_DestInt;
+ c++;
+ break;
+ case 'o':
+ base = 8;
+ flag |= (uint32_t)kSCANF_DestInt;
+ c++;
+ break;
+ case 'x':
+ case 'X':
+ base = 16;
+ flag |= (uint32_t)kSCANF_DestInt;
+ c++;
+ break;
+ case 'i':
+ base = 0;
+ flag |= (uint32_t)kSCANF_DestInt;
+ c++;
+ break;
+#if SCANF_FLOAT_ENABLE
+ case 'a':
+ case 'A':
+ case 'e':
+ case 'E':
+ case 'f':
+ case 'F':
+ case 'g':
+ case 'G':
+ flag |= kSCANF_DestFloat;
+ c++;
+ break;
+#endif /* SCANF_FLOAT_ENABLE */
+ case 'c':
+ flag |= (uint32_t)kSCANF_DestChar;
+ if (0U == field_width)
+ {
+ field_width = 1;
+ }
+ c++;
+ break;
+ case 's':
+ flag |= (uint32_t)kSCANF_DestString;
+ c++;
+ break;
+ default:
+ /* Match failure. */
+ match_failure = true;
+ break;
+ }
+
+ /* Match failure. */
+ if (match_failure)
+ {
+ return (int)nassigned;
+ }
+ }
+
+ if (0U == (flag & (uint32_t)kSCANF_DestMask))
+ {
+ /* Format strings are exhausted. */
+ return (int)nassigned;
+ }
+
+ if (0U == field_width)
+ {
+ /* Large than length of a line. */
+ field_width = 99;
+ }
+
+ /* Matching strings in input streams and assign to argument. */
+ switch (flag & (uint32_t)kSCANF_DestMask)
+ {
+ case (uint32_t)kSCANF_DestChar:
+ s = (const char *)p;
+ buf = va_arg(args_ptr, char *);
+ while (((field_width--) > 0U) && ('\0' != *p))
+ {
+ if (0U == (flag & (uint32_t)kSCANF_Suppress))
+ {
+ *buf++ = *p++;
+ }
+ else
+ {
+ p++;
+ }
+ n_decode++;
+ }
+
+ if ((0U == (flag & (uint32_t)kSCANF_Suppress)) && (s != p))
+ {
+ nassigned++;
+ }
+ break;
+ case (uint32_t)kSCANF_DestString:
+ n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);
+ s = p;
+ buf = va_arg(args_ptr, char *);
+ while ((field_width-- > 0U) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') &&
+ (*p != '\r') && (*p != '\v') && (*p != '\f'))
+ {
+ if (0U != (flag & (uint32_t)kSCANF_Suppress))
+ {
+ p++;
+ }
+ else
+ {
+ *buf++ = *p++;
+ }
+ n_decode++;
+ }
+
+ if ((0U == (flag & (uint32_t)kSCANF_Suppress)) && (s != p))
+ {
+ /* Add NULL to end of string. */
+ *buf = '\0';
+ nassigned++;
+ }
+ break;
+ case (uint32_t)kSCANF_DestInt:
+ n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);
+ s = p;
+ val = 0;
+ if ((base == 0U) || (base == 16U))
+ {
+ if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X')))
+ {
+ base = 16U;
+ if (field_width >= 1U)
+ {
+ p += 2;
+ n_decode += 2U;
+ field_width -= 2U;
+ }
+ }
+ }
+
+ if (base == 0U)
+ {
+ if (s[0] == '0')
+ {
+ base = 8U;
+ }
+ else
+ {
+ base = 10U;
+ }
+ }
+
+ neg = 1;
+ switch (*p)
+ {
+ case '-':
+ neg = -1;
+ n_decode++;
+ p++;
+ field_width--;
+ break;
+ case '+':
+ neg = 1;
+ n_decode++;
+ p++;
+ field_width--;
+ break;
+ default:
+ /* MISRA C-2012 Rule 16.4 */
+ break;
+ }
+
+ while ((field_width-- > 0U) && (*p > '\0'))
+ {
+ if ((*p <= '9') && (*p >= '0'))
+ {
+ temp = *p - '0' + (char)0;
+ }
+ else if ((*p <= 'f') && (*p >= 'a'))
+ {
+ temp = *p - 'a' + (char)10;
+ }
+ else if ((*p <= 'F') && (*p >= 'A'))
+ {
+ temp = *p - 'A' + (char)10;
+ }
+ else
+ {
+ temp = (char)base;
+ }
+
+ if ((uint8_t)temp >= base)
+ {
+ break;
+ }
+ else
+ {
+ val = (int32_t)base * val + (int32_t)temp;
+ }
+ p++;
+ n_decode++;
+ }
+ val *= neg;
+ if (0U == (flag & (uint32_t)kSCANF_Suppress))
+ {
+#if SCANF_ADVANCED_ENABLE
+ switch (flag & (uint32_t)kSCANF_LengthMask)
+ {
+ case (uint32_t)kSCANF_LengthChar:
+ if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+ {
+ *va_arg(args_ptr, signed char *) = (signed char)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned char *) = (unsigned char)val;
+ }
+ break;
+ case (uint32_t)kSCANF_LengthShortInt:
+ if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+ {
+ *va_arg(args_ptr, signed short *) = (signed short)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned short *) = (unsigned short)val;
+ }
+ break;
+ case (uint32_t)kSCANF_LengthLongInt:
+ if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+ {
+ *va_arg(args_ptr, signed long int *) = (signed long int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val;
+ }
+ break;
+ case (uint32_t)kSCANF_LengthLongLongInt:
+ if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+ {
+ *va_arg(args_ptr, signed long long int *) = (signed long long int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val;
+ }
+ break;
+ default:
+ /* The default type is the type int. */
+ if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+ {
+ *va_arg(args_ptr, signed int *) = (signed int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
+ }
+ break;
+ }
+#else
+ /* The default type is the type int. */
+ if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+ {
+ *va_arg(args_ptr, signed int *) = (signed int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
+ }
+#endif /* SCANF_ADVANCED_ENABLE */
+ nassigned++;
+ }
+ break;
+#if SCANF_FLOAT_ENABLE
+ case (uint32_t)kSCANF_DestFloat:
+ n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);
+ fnum = strtod(p, (char **)&s);
+
+ if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL))
+ {
+ break;
+ }
+
+ n_decode += (int)(s) - (int)(p);
+ p = s;
+ if (0U == (flag & (uint32_t)kSCANF_Suppress))
+ {
+ if (0U != (flag & (uint32_t)kSCANF_LengthLongLongDouble))
+ {
+ *va_arg(args_ptr, double *) = fnum;
+ }
+ else
+ {
+ *va_arg(args_ptr, float *) = (float)fnum;
+ }
+ nassigned++;
+ }
+ break;
+#endif /* SCANF_FLOAT_ENABLE */
+ default:
+ /* Match failure. */
+ match_failure = true;
+ break;
+ }
+
+ /* Match failure. */
+ if (match_failure)
+ {
+ return (int)nassigned;
+ }
+ }
+ }
+ return (int)nassigned;
+}
+#endif /* SDK_DEBUGCONSOLE */
+
+/*************Code to support toolchain's printf, scanf *******************************/
+/* These function __write and __read is used to support IAR toolchain to printf and scanf*/
+#if (defined(__ICCARM__))
+#if defined(SDK_DEBUGCONSOLE_UART)
+#pragma weak __write
+size_t __write(int handle, const unsigned char *buffer, size_t size);
+size_t __write(int handle, const unsigned char *buffer, size_t size)
+{
+ size_t ret;
+ if (NULL == buffer)
+ {
+ /*
+ * This means that we should flush internal buffers. Since we don't we just return.
+ * (Remember, "handle" == -1 means that all handles should be flushed.)
+ */
+ ret = (size_t)0;
+ }
+ else if ((handle != 1) && (handle != 2))
+ {
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure.
+ */
+ ret = (size_t)-1;
+ }
+ else if (kSerialPort_None == s_debugConsole.type)
+ {
+ /* Do nothing if the debug UART is not initialized. */
+ ret = (size_t)-1;
+ }
+ else
+ {
+ /* Send data. */
+ (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], buffer, size);
+ ret = size;
+ }
+ return ret;
+}
+
+#pragma weak __read
+size_t __read(int handle, unsigned char *buffer, size_t size);
+size_t __read(int handle, unsigned char *buffer, size_t size)
+{
+ size_t ret;
+ /* This function only reads from "standard in", for all other file handles it returns failure. */
+ if (handle != 0)
+ {
+ ret = ((size_t)-1);
+ }
+ else if (kSerialPort_None == s_debugConsole.type)
+ {
+ /* Do nothing if the debug UART is not initialized. */
+ ret = ((size_t)-1);
+ }
+ else
+ {
+ /* Receive data. */
+ (void)s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], buffer, size);
+ ret = size;
+ }
+ return ret;
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* support LPC Xpresso with RedLib */
+#elif (defined(__REDLIB__))
+
+#if (defined(SDK_DEBUGCONSOLE_UART))
+int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)
+{
+ if (NULL == buffer)
+ {
+ /* return -1 if error. */
+ return -1;
+ }
+
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+ if ((handle != 1) && (handle != 2))
+ {
+ return -1;
+ }
+
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+
+ /* Send data. */
+ (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size);
+
+ return 0;
+}
+
+int __attribute__((weak)) __sys_readc(void)
+{
+ char tmp;
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+
+ /* Receive data. */
+ s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)&tmp, sizeof(tmp));
+
+ return tmp;
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#if defined(SDK_DEBUGCONSOLE_UART)
+#if defined(__CC_ARM)
+struct __FILE
+{
+ int handle;
+ /*
+ * Whatever you require here. If the only file you are using is standard output using printf() for debugging,
+ * no file handling is required.
+ */
+};
+#endif
+
+/* FILE is typedef in stdio.h. */
+#pragma weak __stdout
+#pragma weak __stdin
+FILE __stdout;
+FILE __stdin;
+
+#pragma weak fputc
+int fputc(int ch, FILE *f)
+{
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+
+ /* Send data. */
+ (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1);
+ return 1;
+}
+
+#pragma weak fgetc
+int fgetc(FILE *f)
+{
+ char ch;
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+
+ /* Receive data. */
+ s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1);
+ return ch;
+}
+
+/*
+ * Terminate the program, passing a return code back to the user.
+ * This function may not return.
+ */
+void _sys_exit(int returncode)
+{
+ while (1)
+ {
+ }
+}
+
+/*
+ * Writes a character to the output channel. This function is used
+ * for last-resort error message output.
+ */
+void _ttywrch(int ch)
+{
+ char ench = ch;
+ /* Send data. */
+ s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ench), 1);
+}
+
+char *_sys_command_string(char *cmd, int len)
+{
+ return (cmd);
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* These function __write_r and __read_r are used to support Xtensa Clang toolchain to printf and scanf */
+#elif defined(__XTENSA__) && defined(__XT_CLANG__)
+#if defined(SDK_DEBUGCONSOLE_UART)
+
+int __attribute__((weak)) _write_r(void *ptr, int handle, char *buffer, int size);
+int __attribute__((weak)) _write_r(void *ptr, int handle, char *buffer, int size)
+{
+ if (NULL == buffer)
+ {
+ /* return -1 if error. */
+ return -1;
+ }
+
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+ if ((handle != 1) && (handle != 2))
+ {
+ return -1;
+ }
+
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+
+ /* Send data. */
+ (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size);
+
+ return size;
+}
+
+int __attribute__((weak)) _read_r(void *ptr, int handle, char *buffer, int size);
+int __attribute__((weak)) _read_r(void *ptr, int handle, char *buffer, int size)
+{
+ /* This function only reads from "standard in", for all other file handles it returns failure. */
+ if (handle != 0)
+ {
+ return -1;
+ }
+
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+
+ /* Receive data. */
+ (void)s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size);
+ return size;
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/
+#elif (defined(__GNUC__))
+
+#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \
+ (defined(__MCUXPRESSO) && (defined(SDK_DEBUGCONSOLE_UART))))
+int __attribute__((weak)) _write(int handle, char *buffer, int size);
+int __attribute__((weak)) _write(int handle, char *buffer, int size)
+{
+ if (NULL == buffer)
+ {
+ /* return -1 if error. */
+ return -1;
+ }
+
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+ if ((handle != 1) && (handle != 2))
+ {
+ return -1;
+ }
+
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+
+ /* Send data. */
+ (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size);
+
+ return size;
+}
+
+int __attribute__((weak)) _read(int handle, char *buffer, int size);
+int __attribute__((weak)) _read(int handle, char *buffer, int size)
+{
+ /* This function only reads from "standard in", for all other file handles it returns failure. */
+ if (handle != 0)
+ {
+ return -1;
+ }
+
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+
+ /* Receive data. */
+ (void)s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size);
+ return size;
+}
+#endif
+
+#endif /* __ICCARM__ */
diff --git a/minimal-examples/embedded/rt595/hello_world/project/utilities/fsl_debug_console.h b/minimal-examples/embedded/rt595/hello_world/project/utilities/fsl_debug_console.h
new file mode 100644
index 000000000..755b434fe
--- /dev/null
+++ b/minimal-examples/embedded/rt595/hello_world/project/utilities/fsl_debug_console.h
@@ -0,0 +1,224 @@
+/*
+ * Copyright 2017-2018, 2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Debug console shall provide input and output functions to scan and print formatted data.
+ * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
+ * - [flags] :'-', '+', '#', ' ', '0'
+ * - [width]: number (0,1...)
+ * - [.precision]: number (0,1...)
+ * - [length]: do not support
+ * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
+ * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
+ * - [*]: is supported.
+ * - [width]: number (0,1...)
+ * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
+ * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
+ */
+
+#ifndef _FSL_DEBUGCONSOLE_H_
+#define _FSL_DEBUGCONSOLE_H_
+
+#include "fsl_common.h"
+
+/*
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */
+#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */
+#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */
+#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */
+
+/*! @brief Definition to select sdk or toolchain printf, scanf. */
+#ifndef SDK_DEBUGCONSOLE
+#define SDK_DEBUGCONSOLE DEBUGCONSOLE_REDIRECT_TO_SDK
+#endif
+
+#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
+#include <stdio.h>
+#endif
+
+/*! @brief Definition to printf the float number. */
+#ifndef PRINTF_FLOAT_ENABLE
+#define PRINTF_FLOAT_ENABLE 0U
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*! @brief Definition to scanf the float number. */
+#ifndef SCANF_FLOAT_ENABLE
+#define SCANF_FLOAT_ENABLE 0U
+#endif /* SCANF_FLOAT_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for printf. */
+#ifndef PRINTF_ADVANCED_ENABLE
+#define PRINTF_ADVANCED_ENABLE 0U
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for scanf. */
+#ifndef SCANF_ADVANCED_ENABLE
+#define SCANF_ADVANCED_ENABLE 0U
+#endif /* SCANF_ADVANCED_ENABLE */
+
+/*! @brief Definition to select redirect toolchain printf, scanf to uart or not.
+ *
+ * if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf.
+ * if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf.
+ * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function.
+ */
+#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */
+#define PRINTF
+#define SCANF
+#define PUTCHAR
+#define GETCHAR
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */
+#define PRINTF DbgConsole_Printf
+#define SCANF DbgConsole_Scanf
+#define PUTCHAR DbgConsole_Putchar
+#define GETCHAR DbgConsole_Getchar
+#elif SDK_DEBUGCONSOLE == \
+ DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ */
+#define PRINTF printf
+#define SCANF scanf
+#define PUTCHAR putchar
+#define GETCHAR getchar
+#endif /* SDK_DEBUGCONSOLE */
+
+typedef enum _serial_port_type
+{
+ kSerialPort_None = 0U, /*!< Serial port is none */
+ kSerialPort_Uart = 1U, /*!< Serial port UART */
+} serial_port_type_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @name Initialization*/
+/* @{ */
+
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
+/*!
+ * @brief Initializes the peripheral used for debug messages.
+ *
+ * Call this function to enable debug log messages to be output via the specified peripheral,
+ * frequency of peripheral source clock, and base address at the specified baud rate.
+ * After this function has returned, stdout and stdin are connected to the selected peripheral.
+ *
+ * @param instance The instance of the module.If the device is kSerialPort_Uart,
+ * the instance is UART peripheral instance. The UART hardware peripheral
+ * type is determined by UART adapter. For example, if the instance is 1,
+ * if the lpuart_adapter.c is added to the current project, the UART periheral
+ * is LPUART1.
+ * If the uart_adapter.c is added to the current project, the UART periheral
+ * is UART1.
+ * @param baudRate The desired baud rate in bits per second.
+ * @param device Low level device type for the debug console, can be one of the following.
+ * @arg kSerialPort_Uart.
+ * @param clkSrcFreq Frequency of peripheral source clock.
+ *
+ * @return Indicates whether initialization was successful or not.
+ * @retval kStatus_Success Execution successfully
+ * @retval kStatus_Fail Execution failure
+ */
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq);
+
+/*!
+ * @brief De-initializes the peripheral used for debug messages.
+ *
+ * Call this function to disable debug log messages to be output via the specified peripheral
+ * base address and at the specified baud rate.
+ *
+ * @return Indicates whether de-initialization was successful or not.
+ */
+status_t DbgConsole_Deinit(void);
+
+#else
+/*!
+ * Use an error to replace the DbgConsole_Init when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
+ * SDK_DEBUGCONSOLE_UART is not defined.
+ */
+static inline status_t DbgConsole_Init(uint8_t instance,
+ uint32_t baudRate,
+ serial_port_type_t device,
+ uint32_t clkSrcFreq)
+{
+ (void)instance;
+ (void)baudRate;
+ (void)device;
+ (void)clkSrcFreq;
+ return (status_t)kStatus_Fail;
+}
+/*!
+ * Use an error to replace the DbgConsole_Deinit when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
+ * SDK_DEBUGCONSOLE_UART is not defined.
+ */
+static inline status_t DbgConsole_Deinit(void)
+{
+ return (status_t)kStatus_Fail;
+}
+
+#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */
+
+#if SDK_DEBUGCONSOLE
+/*!
+ * @brief Writes formatted output to the standard output stream.
+ *
+ * Call this function to write a formatted output to the standard output stream.
+ *
+ * @param fmt_s Format control string.
+ * @return Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_Printf(const char *fmt_s, ...);
+
+/*!
+ * @brief Writes a character to stdout.
+ *
+ * Call this function to write a character to stdout.
+ *
+ * @param ch Character to be written.
+ * @return Returns the character written.
+ */
+int DbgConsole_Putchar(int ch);
+
+/*!
+ * @brief Reads formatted data from the standard input stream.
+ *
+ * Call this function to read formatted data from the standard input stream.
+ *
+ * @param fmt_ptr Format control string.
+ * @return Returns the number of fields successfully converted and assigned.
+ */
+int DbgConsole_Scanf(char *fmt_ptr, ...);
+
+/*!
+ * @brief Reads a character from standard input.
+ *
+ * Call this function to read a character from standard input.
+ *
+ * @return Returns the character read.
+ */
+int DbgConsole_Getchar(void);
+
+#endif /* SDK_DEBUGCONSOLE */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_DEBUGCONSOLE_H_ */