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https://github.com/warmcat/libwebsockets.git
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e3743d47b4
This provides an alternative esp32-specific SPI driver with ops that can be swapped in place of the gpio bitbang one. The pinmux info and lws gpio driver and other data in the spi bitbang struct are used as-is by the DMA one. New ops are provided which are able to allocate and free DMA-able memory so the device drivers can prepare directly usable buffers. Bounce through to DMA-able buffers is also transparently supported.
89 lines
3.1 KiB
C
89 lines
3.1 KiB
C
/*
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* Generic I2C ops
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*
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* Copyright (C) 2019 - 2020 Andy Green <andy@warmcat.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* This is like an abstract class for spi, a real implementation provides
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* functions for the ops that use the underlying OS arrangements.
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*
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* It uses descriptor / queuing semantics but eg the GPIO BB implementantion is
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* synchronous.
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*/
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#if !defined(__LWS_SPI_H__)
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#define __LWS_SPI_H__
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#include <stdint.h>
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#include <stddef.h>
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typedef int (*lws_spi_cb_t)(void *opaque);
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enum {
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LWSSPIMODE_CPOL = (1 << 0),
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LWSSPIMODE_CPHA = (1 << 1),
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LWS_SPI_BUSMODE_CLK_IDLE_LOW_SAMP_RISING = 0,
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LWS_SPI_BUSMODE_CLK_IDLE_HIGH_SAMP_RISING = LWSSPIMODE_CPOL,
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LWS_SPI_BUSMODE_CLK_IDLE_LOW_SAMP_FALLING = LWSSPIMODE_CPHA,
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LWS_SPI_BUSMODE_CLK_IDLE_HIGH_SAMP_FALLING = LWSSPIMODE_CPHA |
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LWSSPIMODE_CPOL,
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LWS_SPI_TXN_HALF_DUPLEX_DISCRETE = 0,
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/**< separate MISO and MOSI, but only either MISO or MOSI has data at
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* one time... i2c style in SPI */
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LWS_SPI_FLAG_DATA_CONTINUE = (1 << 0),
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/**< leave without finalizing the SPI transaction */
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LWS_SPI_FLAG_DC_CMD_IS_HIGH = (1 << 1),
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/**< It's normally 0 for cmd phase, invert with this flag */
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LWS_SPI_FLAG_DMA_BOUNCE_NOT_NEEDED = (1 << 2),
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/**< It's normally 0 for cmd phase, invert with this flag */
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};
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typedef struct lws_spi_desc {
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const uint8_t *src;
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const uint8_t *data;
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uint8_t *dest;
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void *opaque;
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lws_spi_cb_t completion_cb;
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uint16_t count_cmd;
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uint16_t count_write;
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uint16_t count_read;
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uint8_t txn_type;
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uint8_t channel;
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uint8_t flags;
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} lws_spi_desc_t;
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typedef struct lws_spi_ops {
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int (*init)(const struct lws_spi_ops *ctx);
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int (*queue)(const struct lws_spi_ops *ctx, const lws_spi_desc_t *desc);
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void * (*alloc_dma)(const struct lws_spi_ops *ctx, size_t size);
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void (*free_dma)(const struct lws_spi_ops *ctx, void **p);
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int (*in_flight)(const struct lws_spi_ops *ctx);
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uint32_t spi_clk_hz;
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uint8_t bus_mode;
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} lws_spi_ops_t;
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LWS_VISIBLE LWS_EXTERN int
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lws_spi_table_issue(const lws_spi_ops_t *spi_ops, uint32_t flags, const uint8_t *p, size_t len);
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#endif
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