add function to detect processor features
This commit is contained in:
Stefan Lankes
parent
926f818e83
commit
7a15541d82
2 changed files with 218 additions and 7 deletions
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@ -46,6 +46,65 @@
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extern "C" {
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#endif
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// feature list 1
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#define CPU_FEATURE_FPU (1 << 0)
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#define CPU_FEATURE_MSR (1 << 5)
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#define CPU_FEATURE_APIC (1 << 9)
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#define CPU_FEATURE_MMX (1 << 23)
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#define CPU_FEATURE_FXSR (1 << 24)
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#define CPU_FEATURE_SSE (1 << 25)
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#define CPU_FEATURE_SSE2 (1 << 26)
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// feature list 2
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#define CPU_FEATURE_X2APIC (1 << 21)
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#define CPU_FEATURE_AVX (1 << 28)
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#define CPU_FEATURE_HYPERVISOR (1 << 31)
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typedef struct {
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uint32_t feature1, feature2;
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} cpu_info_t;
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extern cpu_info_t cpu_info;
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// determine the cpu features
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int cpu_detection(void);
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inline static uint32_t has_fpu(void) {
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return (cpu_info.feature1 & CPU_FEATURE_FPU);
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}
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inline static uint32_t has_msr(void) {
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return (cpu_info.feature1 & CPU_FEATURE_MSR);
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}
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inline static uint32_t has_apic(void) {
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return (cpu_info.feature1 & CPU_FEATURE_APIC);
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}
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inline static uint32_t has_fxsr(void) {
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return (cpu_info.feature1 & CPU_FEATURE_FXSR);
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}
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inline static uint32_t has_sse(void) {
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return (cpu_info.feature1 & CPU_FEATURE_SSE);
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}
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inline static uint32_t has_sse2(void) {
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return (cpu_info.feature1 & CPU_FEATURE_SSE2);
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}
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inline static uint32_t has_x2apic(void) {
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return (cpu_info.feature2 & CPU_FEATURE_X2APIC);
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}
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inline static uint32_t has_avx(void) {
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return (cpu_info.feature2 & CPU_FEATURE_AVX);
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}
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inline static uint32_t on_hypervisor(void) {
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return (cpu_info.feature2 & CPU_FEATURE_HYPERVISOR);
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}
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/** @brief Read out time stamp counter
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*
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* The rdtsc asm command puts a 64 bit time stamp value
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@ -60,15 +119,54 @@ inline static uint64_t rdtsc(void)
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return x;
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}
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/** @brief Read cr3 register
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* @return cr3's value
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/** @brief Read MSR
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*
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* The asm instruction rdmsr which stands for "Read from model specific register"
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* is used here.
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*
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* @param msr The parameter which rdmsr assumes in ECX
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* @return The value rdmsr put into EDX:EAX
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*/
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static inline size_t read_cr3(void) {
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inline static uint64_t rdmsr(uint32_t msr) {
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uint32_t low, high;
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asm volatile ("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
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return ((uint64_t)high << 32) | low;
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}
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/** @brief Write a value to a Machine-Specific Registers (MSR)
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*
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* The asm instruction wrmsr which stands for "Write to model specific register"
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* is used here.
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*
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* @param msr The MSR identifier
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* @param value Value, which will be store in the MSR
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*/
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inline static void wrmsr(uint32_t msr, uint64_t value)
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{
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uint32_t low = value & 0xFFFFFFFF;
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uint32_t high = value >> 32;
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asm volatile("wrmsr" :: "a"(low), "c"(msr), "d"(high));
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}
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/** @brief Read cr0 register
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* @return cr0's value
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*/
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static inline size_t read_cr0(void) {
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size_t val;
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asm volatile("mov %%cr3, %0" : "=r"(val));
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asm volatile("mov %%cr0, %0" : "=r"(val));
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return val;
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}
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/** @brief Write a value into cr0 register
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* @param val The value you want to write into cr0
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*/
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static inline void write_cr0(size_t val) {
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asm volatile("mov %0, %%cr0" : : "r"(val));
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}
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/** @brief Read cr2 register
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* @return cr2's value
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*/
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@ -85,6 +183,15 @@ static inline void write_cr2(size_t val) {
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asm volatile("mov %0, %%cr2" : : "r"(val));
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}
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/** @brief Read cr3 register
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* @return cr3's value
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*/
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static inline size_t read_cr3(void) {
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size_t val;
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asm volatile("mov %%cr3, %0" : "=r"(val));
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return val;
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}
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/** @brief Write a value into cr3 register
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* @param val The value you want to write into cr3
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*/
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@ -92,6 +199,22 @@ static inline void write_cr3(size_t val) {
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asm volatile("mov %0, %%cr3" : : "r"(val));
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}
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/** @brief Read cr4 register
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* @return cr4's value
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*/
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static inline size_t read_cr4(void) {
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size_t val;
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asm volatile("mov %%cr4, %0" : "=r"(val));
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return val;
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}
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/** @brief Write a value into cr4 register
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* @param val The value you want to write into cr4
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*/
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static inline void write_cr4(size_t val) {
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asm volatile("mov %0, %%cr4" : : "r"(val));
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}
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/** @brief Flush cache
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*
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* The wbinvd asm instruction which stands for "Write back and invalidate"
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@ -130,12 +253,30 @@ inline static void invalid_cache(void) {
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asm volatile ("invd");
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}
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/* Force strict CPU ordering */
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typedef void (*func_memory_barrier)(void);
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/// Force strict CPU ordering, serializes load and store operations.
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inline static void mb(void) { asm volatile("mfence" ::: "memory"); }
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extern func_memory_barrier mb;
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/// Force strict CPU ordering, serializes load operations.
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inline static void rmb(void) { asm volatile("lfence" ::: "memory"); }
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extern func_memory_barrier rmb;
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/// Force strict CPU ordering, serializes store operations.
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inline static void wmb(void) { asm volatile("sfence" ::: "memory"); }
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extern func_memory_barrier wmb;
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/** @brief Read out CPU ID
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*
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* The cpuid asm-instruction does fill some information into registers and
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* this function fills those register values into the given uint32_t vars.\n
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*
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* @param code Input parameter for the cpuid instruction. Take a look into the intel manual.
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* @param a EAX value will be stores here
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* @param b EBX value will be stores here
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* @param c ECX value will be stores here
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* @param d EDX value will be stores here
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*/
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inline static void cpuid(uint32_t code, uint32_t* a, uint32_t* b, uint32_t* c, uint32_t* d) {
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asm volatile ("cpuid" : "=a"(*a), "=b"(*b), "=c"(*c), "=d"(*d) : "0"(code), "2"(*c));
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}
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/** @brief Read EFLAGS
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*
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@ -209,6 +350,7 @@ static inline size_t lsb(size_t i)
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inline static int system_init(void)
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{
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gdt_install();
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cpu_detection();
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#ifdef CONFIG_PCI
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pci_init();
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#endif
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@ -32,8 +32,22 @@
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#include <eduos/processor.h>
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#include <eduos/tasks.h>
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cpu_info_t cpu_info = { 0, 0 };
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static uint32_t cpu_freq = 0;
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static void default_mb(void)
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{
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asm volatile ("lock; addl $0,0(%%esp)" ::: "memory", "cc");
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}
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func_memory_barrier mb = default_mb;
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func_memory_barrier rmb = default_mb;
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func_memory_barrier wmb = default_mb;
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static void mfence(void) { asm volatile("mfence" ::: "memory"); }
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static void lfence(void) { asm volatile("lfence" ::: "memory"); }
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static void sfence(void) { asm volatile("sfence" ::: "memory"); }
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uint32_t detect_cpu_frequency(void)
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{
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uint64_t start, end, diff;
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@ -62,6 +76,61 @@ uint32_t detect_cpu_frequency(void)
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return cpu_freq;
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}
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int cpu_detection(void) {
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uint32_t a, b;
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size_t cr4;
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uint8_t first_time = 0;
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if (!cpu_info.feature1) {
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first_time = 1;
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cpuid(1, &a, &b, &cpu_info.feature2, &cpu_info.feature1);
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}
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cr4 = read_cr4();
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if (has_fxsr())
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cr4 |= 0x200; // set the OSFXSR bit
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if (has_sse())
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cr4 |= 0x400; // set the OSXMMEXCPT bit
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write_cr4(cr4);
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if (first_time && has_sse())
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wmb = sfence;
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if (first_time && has_sse2()) {
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rmb = lfence;
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mb = mfence;
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}
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if (first_time && has_avx())
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kprintf(
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"The CPU owns the Advanced Vector Extensions (AVX). However, eduOS doesn't support AVX!\n");
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if (has_fpu()) {
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if (first_time)
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kputs("Found and initialized FPU!\n");
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asm volatile ("fninit");
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}
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if (first_time && on_hypervisor()) {
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uint32_t c, d;
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char vendor_id[13];
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kprintf("eduOS is running on a hypervisor!\n");
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cpuid(0x40000000, &a, &b, &c, &d);
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memcpy(vendor_id, &b, 4);
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memcpy(vendor_id + 4, &c, 4);
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memcpy(vendor_id + 8, &d, 4);
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vendor_id[12] = '\0';
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kprintf("Hypervisor Vendor Id: %s\n", vendor_id);
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kprintf("Maximum input value for hypervisor: 0x%x\n", a);
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}
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return 0;
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}
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uint32_t get_cpu_frequency(void)
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{
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if (cpu_freq > 0)
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