From 9b4714113a2b0783dd4850114e1d57cc851e6f85 Mon Sep 17 00:00:00 2001
From: Steffen Vogel <post@steffenvogel.de>
Date: Thu, 21 Aug 2014 20:14:59 +0200
Subject: [PATCH] added functions to handle TLB invalidation and control
 register access

---
 arch/x86/include/asm/processor.h | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index e814be5..6b9db1d 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -66,6 +66,22 @@ static inline size_t read_cr3(void) {
 	return val;
 }
 
+/** @brief Read cr2 register
+ * @return cr2's value
+ */
+static inline size_t read_cr2(void) {
+	size_t val;
+	asm volatile("mov %%cr2, %0" : "=r"(val));
+	return val;
+}
+
+/** @brief Write a value into cr2 register
+ * @param val The value you want to write into cr2
+ */
+static inline void write_cr2(size_t val) {
+	asm volatile("mov %0, %%cr2" : : "r"(val));
+}
+
 /** @brief Write a value into cr3 register
  * @param val The value you want to write into cr3
  */
@@ -73,7 +89,6 @@ static inline void write_cr3(size_t val) {
 	asm volatile("mov %0, %%cr3" : : "r"(val));
 }
 
-
 /** @brief Flush cache
  *
  * The wbinvd asm instruction which stands for "Write back and invalidate"
@@ -95,6 +110,14 @@ static inline void flush_tlb(void)
 		write_cr3(val);
 }
 
+/** @brief Flush a specific page entry in TLB
+ * @param addr The (virtual) address of the page to flush
+ */
+static inline void tlb_flush_one_page(size_t addr)
+{
+	asm volatile("invlpg (%0)" : : "r"(addr) : "memory");
+}
+
 /** @brief Invalidate cache
  *
  * The invd asm instruction which invalidates cache without writing back