reduce the number of interrupts, some cleanups
This commit is contained in:
Stefan Lankes
parent
dabd33f37c
commit
a945d498d7
1 changed files with 47 additions and 15 deletions
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@ -45,10 +45,14 @@
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*/
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#define UART_RX 0 /* In: Receive buffer */
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#define UART_IIR 2 /* In: Interrupt ID Register */
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#define UART_TX 0 /* Out: Transmit buffer */
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#define UART_IER 1 /* Out: Interrupt Enable Register */
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#define UART_FCR 2 /* Out: FIFO Control Register */
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#define UART_IIR 2 /* In: Interrupt ID Register */
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#define UART_MCR 4 /* Out: Modem Control Register */
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#define UART_DLL 0 /* Out: Divisor Latch Low */
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#define UART_DLM 1 /* Out: Divisor Latch High */
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#define UART_LCR 3 /* Out: Line Control Register */
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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@ -68,10 +72,6 @@
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#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
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#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
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#define UART_DLL 0 /* Out: Divisor Latch Low */
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#define UART_DLM 1 /* Out: Divisor Latch High */
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#define UART_LCR 3 /* Out: Line Control Register */
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_LCR_SBC 0x40 /* Set break control */
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#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
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@ -80,6 +80,16 @@
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#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */
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#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
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#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
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#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
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#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
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#define UART_MCR_OUT2 0x08 /* Out2 complement */
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#define UART_MCR_OUT1 0x04 /* Out1 complement */
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#define UART_MCR_RTS 0x02 /* RTS complement */
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#define UART_MCR_DTR 0x01 /* DTR complement */
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static uint8_t mmio = 0;
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static uint32_t iobase = 0;
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static tid_t id;
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@ -87,18 +97,32 @@ static mailbox_uint8_t input_queue;
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static inline unsigned char read_from_uart(uint32_t off)
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{
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uint8_t c, flag;
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flag = irq_nested_disable();
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if (mmio)
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return *((const volatile unsigned char*) (iobase + off));
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c = *((const volatile unsigned char*) (iobase + off));
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else
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return inportb(iobase + off);
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c = inportb(iobase + off);
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irq_nested_enable(flag);
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return c;
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}
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static void write_to_uart(uint32_t off, unsigned char c)
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{
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uint8_t flag;
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flag = irq_nested_disable();
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if (mmio)
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*((volatile unsigned char*) (iobase + off)) = c;
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else
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outportb(iobase + off, c);
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irq_nested_enable(flag);
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}
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@ -139,6 +163,7 @@ static void uart_handler(struct state *s)
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unsigned char c = read_from_uart(UART_IIR);
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while (!(c & UART_IIR_NO_INT)) {
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kprintf("c = 0x%x\n", c);
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if (c & UART_IIR_RDI) {
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c = uart_getchar();
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@ -174,13 +199,21 @@ static void uart_config(void)
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*/
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write_to_uart(UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1);
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/* disable interrupts */
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write_to_uart(UART_IER, 0);
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/* DTR + RTS */
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write_to_uart(UART_MCR, UART_MCR_DTR|UART_MCR_RTS);
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/*
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* 8bit word length
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* 1 stop bit
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* no partity
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* set DLAB=1
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*/
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char lcr = UART_LCR_WLEN8 | UART_LCR_DLAB;
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char lcr = UART_LCR_WLEN8;
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write_to_uart(UART_LCR, lcr);
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lcr = read_from_uart(UART_LCR) | UART_LCR_DLAB;
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write_to_uart(UART_LCR, lcr);
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/*
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@ -194,7 +227,7 @@ static void uart_config(void)
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write_to_uart(UART_LCR, lcr & (~UART_LCR_DLAB));
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/* enable interrupt */
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write_to_uart(UART_IER, UART_IER_RDI | UART_IER_RLSI | UART_IER_THRI);
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write_to_uart(UART_IER, UART_IER_RDI /*| UART_IER_RLSI | UART_IER_THRI*/);
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int err = create_kernel_task(&id, uart_thread, NULL, HIGH_PRIO);
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if (BUILTIN_EXPECT(err, 0))
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@ -220,18 +253,17 @@ int uart_init(void)
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Lsuccess:
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if (pci_info.type[0]) {
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// we use COM1
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mmio = 0;
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//iobase = pci_info.base[bar];
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//irq_install_handler(32+pci_info.irq, uart_handler);
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iobase = 0x3F8;
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irq_install_handler(32+4, uart_handler);
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iobase = pci_info.base[bar];
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irq_install_handler(32+pci_info.irq, uart_handler);
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//iobase = 0x3F8;
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//irq_install_handler(32+4, uart_handler);
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kprintf("UART uses io address 0x%x\n", iobase);
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} else {
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mmio = 1;
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iobase = 0x9010b000; //pci_info.base[0];
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//irq_install_handler(32+pci_info.irq, uart_handler);
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irq_install_handler(32+pci_info.irq, uart_handler);
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page_map(iobase & PAGE_MASK, iobase & PAGE_MASK, 1, PG_GLOBAL | PG_RW | PG_PCD);
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kprintf("UART uses mmio address 0x%x\n", iobase);
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