add basic support of an UART device
This commit is contained in:
Stefan Lankes
parent
8648ca0dfe
commit
df0b192e21
10 changed files with 494 additions and 7 deletions
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@ -29,8 +29,7 @@ GDBFLAGS = -x debug.gdb
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QEMU = qemu-system-i386
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QEMUFLAGS = -smp 2 -monitor stdio \
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-net nic,model=rtl8139 \
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-net user,hostfwd=tcp::12345-:7 \
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-serial tcp::12346,server,nowait
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-net user,hostfwd=tcp::12345-:7
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INCLUDE = -I$(TOPDIR)/include -I$(TOPDIR)/arch/$(ARCH)/include
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# Compiler options for final code
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@ -73,6 +72,9 @@ veryclean: clean
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qemu: $(NAME).elf
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$(QEMU) $(QEMUFLAGS) -kernel $(NAME).elf
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uart: $(NAME).elf
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$(QEMU) -chardev null,id=tS0 -device pci-serial,chardev=tS0 -serial tcp::4555,server $(QEMUFLAGS) -kernel $(NAME).elf
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debug: $(NAME).elf
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$(TERM) -e $(GDB) $(GDBFLAGS) &
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$(QEMU) $(QEMUFLAGS) -s -S -kernel $(NAME).elf
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@ -88,6 +88,9 @@ Overview of all branches
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Add support of paging. See http://www.noteblok.net/2014/06/14/bachelor
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for a detailed description.
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6. stage6 - Add UART support
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Add basic support of a serial device
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Usefull Links
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-------------
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0. http://www.gnu.org/software/grub/manual/multiboot/
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49
arch/x86/include/asm/pci.h
Normal file
49
arch/x86/include/asm/pci.h
Normal file
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@ -0,0 +1,49 @@
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/**
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* @author Stefan Lankes
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* @file arch/x86/include/asm/pci.h
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* @brief functions related to PCI initialization and information
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*
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* This file contains a procedure to initialize the PCI environment
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* and functions to access information about specific PCI devices.
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*/
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#ifndef __ARCH_PCI_H__
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#define __ARCH_PCI_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct {
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uint32_t base[6];
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uint32_t size[6];
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uint32_t irq;
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} pci_info_t;
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/** @brief Initialize the PCI environment
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*/
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int pci_init(void);
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/** @brief Determine the IObase address and the interrupt number of a specific device
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*
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* @param vendor_id The device's vendor ID
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* @param device_id the device's ID
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* @param info Pointer to the record pci_info_t where among other the IObase address will be stored
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*
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* @return
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* - 0 on success
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* - -EINVAL (-22) on failure
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*/
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int pci_get_device_info(uint32_t vendor_id, uint32_t device_id, pci_info_t* info);
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/** @brief Print information of existing pci adapters
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*
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* @return 0 in any case
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*/
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int print_pci_adapters(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -38,6 +38,9 @@
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#include <eduos/stddef.h>
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#include <asm/gdt.h>
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#ifdef CONFIG_PCI
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#include <asm/pci.h>
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#endif
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#ifdef __cplusplus
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extern "C" {
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@ -206,6 +209,9 @@ static inline size_t lsb(size_t i)
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inline static int system_init(void)
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{
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gdt_install();
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#ifdef CONFIG_PCI
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pci_init();
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#endif
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return 0;
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}
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67
arch/x86/include/asm/uart.h
Normal file
67
arch/x86/include/asm/uart.h
Normal file
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@ -0,0 +1,67 @@
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/*
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* Copyright (c) 2014, Stefan Lankes, RWTH Aachen University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @author Stefan Lankes
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* @file arch/x86/include/asm/uart.h
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* @brief UART related code
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*/
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#ifndef __ARCH_UART_H__
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#define __ARCH_UART_H__
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#include <eduos/stddef.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @brief Initialize UART output
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*
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* @return Returns 0 on success
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*/
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int uart_init(void);
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/** @brief Simple string output on a serial device.
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*
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* If you want a new line you will have to "\\n".
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*
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* @return Length of output in bytes
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*/
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int uart_puts(const char *text);
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/** @brief Simple character output on a serial device.
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*
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* @return The original input character casted to int
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*/
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int uart_putchar(unsigned char c);
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -1,4 +1,4 @@
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C_source := tasks.c vga.c gdt.c irq.c idt.c isrs.c timer.c processor.c
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C_source := tasks.c vga.c gdt.c irq.c idt.c isrs.c timer.c processor.c uart.c pci.c
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ASM_source := entry.asm string32.asm
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MODULE := arch_x86_kernel
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187
arch/x86/kernel/pci.c
Normal file
187
arch/x86/kernel/pci.c
Normal file
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@ -0,0 +1,187 @@
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#include <eduos/stdio.h>
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#include <eduos/string.h>
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#include <eduos/errno.h>
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#include <asm/irqflags.h>
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#include <asm/io.h>
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#ifdef CONFIG_PCI
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#include <asm/pci.h>
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#include "pcihdr.h"
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/*
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* PCI configuration registers
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*/
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#define PCI_CFID 0x00 /* Configuration ID */
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#define PCI_CFCS 0x04 /* Configurtion Command/Status */
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#define PCI_CFRV 0x08 /* Configuration Revision */
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#define PCI_CFLT 0x0c /* Configuration Latency Timer */
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#define PCI_CBIO 0x10 /* Configuration Base IO Address */
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#define PCI_CFIT 0x3c /* Configuration Interrupt */
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#define PCI_CFDA 0x40 /* Configuration Driver Area */
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#define PHYS_IO_MEM_START 0
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#define PCI_MEM 0
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#define PCI_INTA 0
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#define PCI_NSLOTS 22
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#define PCI_NBUS 0
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#define PCI_CONF_ADDR_REG 0xcf8
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#define PCI_CONF_FRWD_REG 0xcf8
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#define PCI_CONF_DATA_REG 0xcfc
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#define PCI_IO_CONF_START 0xc000
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#define MAX_BUS 16
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#define MAX_SLOTS 32
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static uint32_t mechanism = 0;
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static uint32_t adapters[MAX_BUS][MAX_SLOTS] = {[0 ... MAX_BUS-1][0 ... MAX_SLOTS-1] = -1};
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static void pci_conf_write(uint32_t bus, uint32_t slot, uint32_t off, uint32_t val)
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{
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if (mechanism == 1) {
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outportl(PCI_CONF_FRWD_REG, bus);
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outportl(PCI_CONF_ADDR_REG, 0xf0);
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outportl(PCI_IO_CONF_START | (slot << 8) | off, val);
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} else {
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outportl(PCI_CONF_ADDR_REG,
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(0x80000000 | (bus << 16) | (slot << 11) | off));
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outportl(PCI_CONF_DATA_REG, val);
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}
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}
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static uint32_t pci_conf_read(uint32_t bus, uint32_t slot, uint32_t off)
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{
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uint32_t data = -1;
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outportl(PCI_CONF_ADDR_REG,
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(0x80000000 | (bus << 16) | (slot << 11) | off));
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data = inportl(PCI_CONF_DATA_REG);
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if ((data == 0xffffffff) && (slot < 0x10)) {
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outportl(PCI_CONF_FRWD_REG, bus);
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outportl(PCI_CONF_ADDR_REG, 0xf0);
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data = inportl(PCI_IO_CONF_START | (slot << 8) | off);
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if (data == 0xffffffff)
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return data;
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if (!mechanism)
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mechanism = 1;
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} else if (!mechanism)
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mechanism = 2;
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return data;
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}
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static inline uint32_t pci_what_irq(uint32_t bus, uint32_t slot)
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{
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return pci_conf_read(bus, slot, PCI_CFIT) & 0xFF;
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}
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static inline uint32_t pci_what_iobase(uint32_t bus, uint32_t slot, uint32_t nr)
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{
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return pci_conf_read(bus, slot, PCI_CBIO + nr*4) & 0xFFFFFFFC;
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}
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static inline uint32_t pci_what_size(uint32_t bus, uint32_t slot, uint32_t nr)
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{
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uint32_t tmp, ret;
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// backup the original value
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tmp = pci_conf_read(bus, slot, PCI_CBIO + nr*4);
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// determine size
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pci_conf_write(bus, slot, PCI_CBIO + nr*4, 0xFFFFFFFF);
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ret = ~pci_conf_read(bus, slot, PCI_CBIO + nr*4) + 1;
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// restore original value
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pci_conf_write(bus, slot, PCI_CBIO + nr*4, tmp);
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return ret;
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}
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int pci_init(void)
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{
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uint32_t slot, bus;
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for (bus = 0; bus < MAX_BUS; bus++)
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for (slot = 0; slot < MAX_SLOTS; slot++)
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adapters[bus][slot] = pci_conf_read(bus, slot, PCI_CFID);
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return 0;
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}
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int pci_get_device_info(uint32_t vendor_id, uint32_t device_id, pci_info_t* info)
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{
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uint32_t slot, bus, i;
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if (!info)
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return -EINVAL;
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if (!mechanism)
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pci_init();
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for (bus = 0; bus < MAX_BUS; bus++) {
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for (slot = 0; slot < MAX_SLOTS; slot++) {
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if (adapters[bus][slot] != -1) {
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if (((adapters[bus][slot] & 0xffff) == vendor_id) &&
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(((adapters[bus][slot] & 0xffff0000) >> 16) == device_id)) {
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for(i=0; i<6; i++) {
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info->base[i] = pci_what_iobase(bus, slot, i);
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info->size[i] = (info->base[i]) ? pci_what_size(bus, slot, i) : 0;
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}
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info->irq = pci_what_irq(bus, slot);
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return 0;
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}
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}
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}
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}
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return -EINVAL;
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}
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int print_pci_adapters(void)
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{
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uint32_t slot, bus;
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uint32_t i, counter = 0;
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if (!mechanism)
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pci_init();
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for (bus = 0; bus < MAX_BUS; bus++) {
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for (slot = 0; slot < MAX_SLOTS; slot++) {
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if (adapters[bus][slot] != -1) {
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counter++;
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kprintf("%d) Vendor ID: 0x%x Device Id: 0x%x\n",
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counter, adapters[bus][slot] & 0xffff,
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(adapters[bus][slot] & 0xffff0000) >> 16);
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for (i=0; i<PCI_VENTABLE_LEN; i++) {
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if ((adapters[bus][slot] & 0xffff) ==
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(uint32_t)PciVenTable[i].VenId)
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kprintf("\tVendor is %s\n",
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PciVenTable[i].VenShort);
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}
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for (i=0; i<PCI_DEVTABLE_LEN; i++) {
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if ((adapters[bus][slot] & 0xffff) ==
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(uint32_t)PciDevTable[i].VenId) {
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if (((adapters[bus][slot] & 0xffff0000) >> 16) ==
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PciDevTable[i].DevId) {
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kprintf
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("\tChip: %s ChipDesc: %s\n",
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PciDevTable[i].Chip,
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PciDevTable[i].ChipDesc);
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}
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}
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}
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}
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}
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}
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return 0;
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}
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#endif
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166
arch/x86/kernel/uart.c
Normal file
166
arch/x86/kernel/uart.c
Normal file
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@ -0,0 +1,166 @@
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/*
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* Copyright (c) 2014, Stefan Lankes, RWTH Aachen University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <eduos/stdio.h>
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#include <eduos/string.h>
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#include <asm/io.h>
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#include <asm/uart.h>
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#include <asm/irq.h>
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#include <asm/irqflags.h>
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#include <asm/vga.h>
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#ifdef CONFIG_PCI
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#include <asm/pci.h>
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#endif
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#ifdef CONFIG_UART
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#define UART_RX 0 /* In: Receive buffer */
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#define UART_TX 0 /* Out: Transmit buffer */
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#define UART_IER 1 /* Out: Interrupt Enable Register */
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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#define UART_FCR 2 /* Out: FIFO Control Register */
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#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
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#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
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#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
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#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
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#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
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#define UART_DLL 0 /* Out: Divisor Latch Low */
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#define UART_DLM 1 /* Out: Divisor Latch High */
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#define UART_LCR 3 /* Out: Line Control Register */
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_LCR_SBC 0x40 /* Set break control */
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#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
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#define UART_LCR_EPAR 0x10 /* Even parity select */
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#define UART_LCR_PARITY 0x08 /* Parity Enable */
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#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */
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#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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static uint32_t iobase = 0;
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unsigned char uart_getchar(void)
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{
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return inportb(iobase + UART_RX);
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}
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/* Handles all UART's interrupt */
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static void uart_handler(struct state *s)
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{
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vga_puts("UART interrupt\n");
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}
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/* Puts a single character on a serial device */
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int uart_putchar(unsigned char c)
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{
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if (!iobase)
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return 0;
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outportb(iobase + UART_TX, c);
|
||||
|
||||
return (int) c;
|
||||
}
|
||||
|
||||
/* Uses the routine above to output a string... */
|
||||
int uart_puts(const char *text)
|
||||
{
|
||||
size_t i, len = strlen(text);
|
||||
|
||||
if (!iobase)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
uart_putchar(text[i]);
|
||||
|
||||
return i-1;
|
||||
}
|
||||
|
||||
static void uart_config(void)
|
||||
{
|
||||
/*
|
||||
* enable FIFOs
|
||||
* clear RX and TX FIFO
|
||||
* set irq trigger to 8 bytes
|
||||
*/
|
||||
outportb(iobase + UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1);
|
||||
|
||||
/*
|
||||
* 8bit word length
|
||||
* 1 stop bit
|
||||
* no partity
|
||||
* set DLAB=1
|
||||
*/
|
||||
char lcr = UART_LCR_WLEN8 | UART_LCR_DLAB;
|
||||
outportb(iobase + UART_LCR, lcr);
|
||||
|
||||
/*
|
||||
* set baudrate to 115200 (on qemu)
|
||||
*/
|
||||
outportb(iobase + UART_DLL, 0x01);
|
||||
outportb(iobase + UART_DLM, 0x00);
|
||||
|
||||
/* set DLAB=0 */
|
||||
outportb(iobase + UART_LCR, lcr & (~UART_LCR_DLAB));
|
||||
|
||||
/* enable interrupt */
|
||||
outportb(iobase + UART_IER, UART_IER_RDI | UART_IER_RLSI | UART_IER_THRI);
|
||||
}
|
||||
|
||||
int uart_init(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
pci_info_t pci_info;
|
||||
|
||||
// Searching for Intel's UART device
|
||||
if (pci_get_device_info(0x8086, 0x0936, &pci_info) == 0) {
|
||||
iobase = pci_info.base[0];
|
||||
goto Lsuccess;
|
||||
}
|
||||
// Searching for Qemu's UART device
|
||||
if (pci_get_device_info(0x1b36, 0x0002, &pci_info) == 0) {
|
||||
iobase = 0x03f8;
|
||||
goto Lsuccess;
|
||||
}
|
||||
|
||||
return -1;
|
||||
|
||||
Lsuccess:
|
||||
irq_install_handler(32+pci_info.irq, uart_handler);
|
||||
|
||||
// configure uart
|
||||
uart_config();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -45,6 +45,8 @@ extern "C" {
|
|||
#define BYTE_ORDER LITTLE_ENDIAN
|
||||
|
||||
#define CONFIG_VGA
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_UART
|
||||
|
||||
#define BUILTIN_EXPECT(exp, b) __builtin_expect((exp), (b))
|
||||
//#define BUILTIN_EXPECT(exp, b) (exp)
|
||||
|
|
|
|||
|
|
@ -29,12 +29,16 @@
|
|||
#include <eduos/string.h>
|
||||
#include <eduos/stdarg.h>
|
||||
#include <eduos/spinlock.h>
|
||||
#include <asm/uart.h>
|
||||
#include <asm/vga.h>
|
||||
|
||||
static spinlock_irqsave_t olock = SPINLOCK_IRQSAVE_INIT;
|
||||
|
||||
int koutput_init(void)
|
||||
{
|
||||
#ifdef CONFIG_UART
|
||||
uart_init();
|
||||
#endif
|
||||
#ifdef CONFIG_VGA
|
||||
vga_init();
|
||||
#endif
|
||||
|
|
@ -45,6 +49,9 @@ int koutput_init(void)
|
|||
int kputchar(int c)
|
||||
{
|
||||
spinlock_irqsave_lock(&olock);
|
||||
#ifdef CONFIG_UART
|
||||
uart_putchar(c);
|
||||
#endif
|
||||
#ifdef CONFIG_VGA
|
||||
vga_putchar(c);
|
||||
#endif
|
||||
|
|
@ -55,12 +62,10 @@ int kputchar(int c)
|
|||
|
||||
int kputs(const char *str)
|
||||
{
|
||||
#ifdef CONFIG_VGA
|
||||
int i;
|
||||
|
||||
for(i=0; str[i] != '\0'; i++)
|
||||
vga_putchar((int) str[i]);
|
||||
kputchar((int) str[i]);
|
||||
|
||||
return i;
|
||||
#else
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue