271 lines
7.4 KiB
NASM
271 lines
7.4 KiB
NASM
;
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; Copyright (c) 2010, Stefan Lankes, RWTH Aachen University
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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; * Neither the name of the University nor the names of its contributors
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; may be used to endorse or promote products derived from this software
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; without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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; DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
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; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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; This is the kernel's entry point. We could either call main here,
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; or we can use this to setup the stack or other nice stuff, like
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; perhaps setting up the GDT and segments. Please note that interrupts
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; are disabled at this point: More on interrupts later!
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%include "config.inc"
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[BITS 32]
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; We use a special name to map this section at the begin of our kernel
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; => Multiboot needs its magic number at the begin of the kernel
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SECTION .mboot
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global start
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start:
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jmp stublet
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; This part MUST be 4byte aligned, so we solve that issue using 'ALIGN 4'
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ALIGN 4
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mboot:
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; Multiboot macros to make a few lines more readable later
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MULTIBOOT_PAGE_ALIGN equ 1<<0
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MULTIBOOT_MEMORY_INFO equ 1<<1
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MULTIBOOT_HEADER_MAGIC equ 0x1BADB002
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MULTIBOOT_HEADER_FLAGS equ MULTIBOOT_PAGE_ALIGN | MULTIBOOT_MEMORY_INFO
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MULTIBOOT_CHECKSUM equ -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS)
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; This is the GRUB Multiboot header. A boot signature
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dd MULTIBOOT_HEADER_MAGIC
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dd MULTIBOOT_HEADER_FLAGS
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dd MULTIBOOT_CHECKSUM
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SECTION .text
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ALIGN 4
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stublet:
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; initialize stack pointer
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mov esp, boot_stack
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add esp, KERNEL_STACK_SIZE-16
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; initialize cpu features
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call cpu_init
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; interpret multiboot information
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extern multiboot_init
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push ebx
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call multiboot_init
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add esp, 4
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; jump to the boot processors's C code
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extern main
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call main
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jmp $
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global cpu_init
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cpu_init:
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mov eax, cr0
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; enable caching, disable paging and fpu emulation
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and eax, 0x1ffffffb
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; ...and turn on FPU exceptions
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or eax, 0x22
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mov cr0, eax
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; clears the current pgd entry
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xor eax, eax
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mov cr3, eax
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; at this stage, we disable the SSE support
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mov eax, cr4
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and eax, 0xfffbf9ff
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mov cr4, eax
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ret
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; This will set up our new segment registers. We need to do
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; something special in order to set CS. We do what is called a
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; far jump. A jump that includes a segment as well as an offset.
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; This is declared in C as 'extern void gdt_flush();'
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global gdt_flush
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extern gp
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gdt_flush:
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lgdt [gp]
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mov ax, 0x10
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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jmp 0x08:flush2
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flush2:
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ret
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; The first 32 interrupt service routines (isr) entries correspond to exceptions.
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; Some exceptions will push an error code onto the stack which is specific to
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; the exception caused. To decrease the complexity, we handle this by pushing a
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; dummy error code of 0 onto the stack for any ISR that doesn't push an error
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; code already.
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;
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; ISRs are registered as "Interrupt Gate".
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; Therefore, the interrupt flag (IF) is already cleared.
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; NASM macro which pushs also an pseudo error code
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%macro isrstub_pseudo_error 1
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global isr%1
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isr%1:
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push byte 0 ; pseudo error code
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push byte %1
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jmp common_stub
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%endmacro
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; Similar to isrstub_pseudo_error, but without pushing
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; a pseudo error code => The error code is already
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; on the stack.
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%macro isrstub 1
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global isr%1
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isr%1:
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push byte %1
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jmp common_stub
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%endmacro
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; create isr entries, where the number after the
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; pseudo error code represents following interrupts
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; 0: Divide By Zero Exception
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; 1: Debug Exception
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; 2: Non Maskable Interrupt Exception
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; 3: Int 3 Exception
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; 4: INTO Exception
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; 5: Out of Bounds Exception
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; 6: Invalid Opcode Exception
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; 7: Coprocessor Not Available Exception
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%assign i 0
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%rep 8
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isrstub_pseudo_error i
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%assign i i+1
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%endrep
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; 8: Double Fault Exception (With Error Code!)
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isrstub 8
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; 9: Coprocessor Segment Overrun Exception
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isrstub_pseudo_error 9
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; 10: Bad TSS Exception (With Error Code!)
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; 11: Segment Not Present Exception (With Error Code!)
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; 12: Stack Fault Exception (With Error Code!)
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; 13: General Protection Fault Exception (With Error Code!)
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; 14: Page Fault Exception (With Error Code!)
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%assign i 10
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%rep 5
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isrstub i
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%assign i i+1
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%endrep
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; 15: Reserved Exception
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; 16: Floating Point Exception
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; 17: Alignment Check Exception
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; 18: Machine Check Exceptio
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; 19-31: Reserved
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%assign i 15
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%rep 17
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isrstub_pseudo_error i
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%assign i i+1
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%endrep
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; NASM macro for asynchronous interrupts (no exceptions)
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%macro irqstub 1
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global irq%1
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irq%1:
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push byte 0 ; pseudo error code
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push byte 32+%1
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jmp common_stub
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%endmacro
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; create entries for the interrupts 0 to 23
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%assign i 0
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%rep 24
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irqstub i
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%assign i i+1
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%endrep
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extern irq_handler
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extern get_current_stack
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extern finish_task_switch
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extern set_kernel_stack
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global switch_context
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ALIGN 4
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switch_context:
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; create on the stack a pseudo interrupt
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; afterwards, we switch to the task with iret
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; we already in kernel space => no pushing of SS required
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mov eax, [esp+4] ; on the stack is already the address to store the old esp
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pushf ; push controll register
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push DWORD 0x8 ; CS
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push DWORD rollback ; EIP
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push DWORD 0x0 ; Interrupt number
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push DWORD 0x00edbabe ; Error code
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pusha ; push all general purpose registers...
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push 0x10 ; kernel data segment
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push 0x10 ; kernel data segment
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jmp common_switch
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ALIGN 4
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rollback:
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ret
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ALIGN 4
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common_stub:
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pusha
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push es
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push ds
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mov ax, 0x10
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mov es, ax
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mov ds, ax
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; use the same handler for interrupts and exceptions
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push esp
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call irq_handler
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add esp, 4
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cmp eax, 0
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je no_context_switch
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common_switch:
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mov [eax], esp ; store old esp
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call get_current_stack ; get new esp
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xchg eax, esp
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; set task switched flag
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mov eax, cr0
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or eax, 8
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mov cr0, eax
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; set esp0 in the task state segment
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call set_kernel_stack
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; call cleanup code
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call finish_task_switch
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no_context_switch:
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pop ds
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pop es
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popa
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add esp, 8
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iret
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global boot_stack
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ALIGN 4096
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boot_stack:
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TIMES (KERNEL_STACK_SIZE) DB 0xcd
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SECTION .note.GNU-stack noalloc noexec nowrite progbits
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