198 lines
5.3 KiB
C
198 lines
5.3 KiB
C
/*
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* Copyright (c) 2010, Stefan Lankes, RWTH Aachen University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @author Stefan Lankes
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* @file arch/x86/include/asm/processor.h
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* @brief CPU-specific functions
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*
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* This file contains structures and functions related to CPU-specific assembler commands.
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*/
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#ifndef __ARCH_PROCESSOR_H__
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#define __ARCH_PROCESSOR_H__
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#include <eduos/stddef.h>
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#include <asm/gdt.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @brief Read out time stamp counter
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*
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* The rdtsc asm command puts a 64 bit time stamp value
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* into EDX:EAX.
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*
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* @return The 64 bit time stamp value
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*/
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inline static uint64_t rdtsc(void)
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{
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uint64_t x;
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asm volatile ("rdtsc" : "=A" (x));
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return x;
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}
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/** @brief Flush cache
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*
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* The wbinvd asm instruction which stands for "Write back and invalidate"
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* is used here
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*/
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inline static void flush_cache(void) {
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asm volatile ("wbinvd" : : : "memory");
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}
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/** @brief Invalidate cache
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*
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* The invd asm instruction which invalidates cache without writing back
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* is used here
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*/
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inline static void invalid_cache(void) {
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asm volatile ("invd");
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}
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/// Force strict CPU ordering, serializes load and store operations.
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inline static void mb(void) { asm volatile("mfence" ::: "memory"); }
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/// Force strict CPU ordering, serializes load operations.
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inline static void rmb(void) { asm volatile("lfence" ::: "memory"); }
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/// Force strict CPU ordering, serializes store operations.
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inline static void wmb(void) { asm volatile("sfence" ::: "memory"); }
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/** @brief Read EFLAGS
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*
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* @return The EFLAGS value
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*/
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static inline uint32_t read_eflags(void)
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{
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uint32_t result;
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asm volatile ("pushf; pop %0" : "=r"(result));
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return result;
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}
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/** @brief search the first most significant bit
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*
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* @param i source operand
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* @return
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* - first bit, which is set in the source operand
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* - invalid value, if not bit ist set
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*/
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static inline size_t msb(size_t i)
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{
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size_t ret;
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if (!i)
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return (sizeof(size_t)*8);
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asm volatile ("bsr %1, %0" : "=r"(ret) : "r"(i) : "cc");
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return ret;
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}
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/** @brief search the least significant bit
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*
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* @param i source operand
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* @return
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* - first bit, which is set in the source operand
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* - invalid value, if not bit ist set
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*/
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static inline size_t lsb(size_t i)
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{
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size_t ret;
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if (!i)
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return (sizeof(size_t)*8);
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asm volatile ("bsf %1, %0" : "=r"(ret) : "r"(i) : "cc");
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return ret;
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}
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/// A one-instruction-do-nothing
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#define NOP1 asm volatile ("nop")
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/// A two-instruction-do-nothing
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#define NOP2 asm volatile ("nop;nop")
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/// A four-instruction-do-nothing
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#define NOP4 asm volatile ("nop;nop;nop;nop")
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/// A eight-instruction-do-nothing
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#define NOP8 asm volatile ("nop;nop;nop;nop;nop;nop;nop;nop")
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/// The PAUSE instruction provides a hint to the processor that the code sequence is a spin-wait loop.
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#define PAUSE asm volatile ("pause")
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/// The HALT instruction stops the processor until the next interrupt arrives
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#define HALT asm volatile ("hlt")
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/** @brief Init several subsystems
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*
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* This function calls the initialization procedures for:
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* - GDT
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* - APIC
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* - PCI [if configured]
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*
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* @return 0 in any case
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*/
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inline static int system_init(void)
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{
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gdt_install();
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return 0;
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}
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/** @brief Detect and read out CPU frequency
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*
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* @return The CPU frequency in MHz
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*/
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uint32_t detect_cpu_frequency(void);
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/** @brief Read out CPU frequency if detected before
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*
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* If you did not issue the detect_cpu_frequency() function before,
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* this function will call it implicitly.
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*
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* @return The CPU frequency in MHz
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*/
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uint32_t get_cpu_frequency(void);
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/** @brief Busywait an microseconds interval of time
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* @param usecs The time to wait in microseconds
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*/
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void udelay(uint32_t usecs);
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/** @brief System calibration
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*
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* This procedure will detect the CPU frequency and calibrate the APIC timer.
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*
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* @return 0 in any case.
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*/
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inline static int system_calibration(void)
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{
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detect_cpu_frequency();
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return 0;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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