From 00e045e76065e9437fd44f643dcd0a55cbbf9691 Mon Sep 17 00:00:00 2001 From: VNSL Durga Date: Wed, 5 Aug 2015 18:50:18 +0530 Subject: [PATCH] xilskey:Added API for clk calculations. Removed redundant code by adding common API for clock calculations. Signed-off-by: VNSL Durga Reviewed-by: Harini Katakam --- .../xilskey/src/include/xilskey_utils.h | 16 +++- lib/sw_services/xilskey/src/xilskey_bbram.c | 21 +---- lib/sw_services/xilskey/src/xilskey_epl.c | 77 +++++----------- lib/sw_services/xilskey/src/xilskey_eps.c | 34 +------ lib/sw_services/xilskey/src/xilskey_utils.c | 89 +++++++++++++++---- 5 files changed, 113 insertions(+), 124 deletions(-) diff --git a/lib/sw_services/xilskey/src/include/xilskey_utils.h b/lib/sw_services/xilskey/src/include/xilskey_utils.h index ee5f6b92..c7579ef1 100644 --- a/lib/sw_services/xilskey/src/include/xilskey_utils.h +++ b/lib/sw_services/xilskey/src/include/xilskey_utils.h @@ -45,6 +45,11 @@ * 2.00 hk 23/01/14 Corrected PL voltage checks to VCCINT and VCCAUX. * CR#768077. * Changed PS efuse error codes for voltage out of range +* 3.00 vns 31/07/15 Added Xilskey_Timer_Intialise API and modified +* prototype of XilSKey_Efuse_StartTimer +* Modified efuse PS macro +* XSK_EFUSEPS_RSA_KEY_HASH_STRING_SIZE to +* XSK_EFUSEPL_RSA_KEY_HASH_STRING_SIZE * *****************************************************************************/ @@ -55,6 +60,11 @@ /************************** Constant Definitions ****************************/ /**************************** Type Definitions ******************************/ /***************** Macros (Inline Functions) Definitions ********************/ +#ifdef XPAR_XSK_MICROBLAZE_PLATFORM +#define XSK_MICROBLAZE_PLATFORM +#else +#define XSK_ARM_PLATFORM +#endif /** * The following constants map to the XPAR parameters created in the * xparameters.h file. They are defined here such that a user can easily @@ -254,7 +264,7 @@ /** * PS eFUSE RSA key Hash size in characters */ -#define XSK_EFUSEPL_RSA_KEY_HASH_STRING_SIZE (64) +#define XSK_EFUSEPS_RSA_KEY_HASH_STRING_SIZE (64) /************************** Variable Definitions ****************************/ /** * XADC Structure @@ -440,7 +450,7 @@ typedef enum { /************************** Function Prototypes *****************************/ u32 XilSKey_EfusePs_XAdcInit (void ); void XilSKey_EfusePs_XAdcReadTemperatureAndVoltage(XSKEfusePs_XAdc *XAdcInstancePtr); -void XilSKey_Efuse_StartTimer(u32 RefClk); +void XilSKey_Efuse_StartTimer(); u64 XilSKey_Efuse_GetTime(); void XilSKey_Efuse_SetTimeOut(volatile u64* t, u64 us); u8 XilSKey_Efuse_IsTimerExpired(u64 t); @@ -455,7 +465,7 @@ u32 XilSKey_Efuse_IsValidChar(const char *c); u32 XilSKey_Efuse_ConvertStringToHexLE(const char * Str, u8 * Buf, u32 Len); u32 XilSKey_Efuse_ConvertStringToHexBE(const char * Str, u8 * Buf, u32 Len); u32 XilSKey_Efuse_ValidateKey(const char *Key, u32 Len); - +u32 Xilskey_Timer_Intialise(); /***************************************************************************/ diff --git a/lib/sw_services/xilskey/src/xilskey_bbram.c b/lib/sw_services/xilskey/src/xilskey_bbram.c index 7f0f2262..a5600d28 100644 --- a/lib/sw_services/xilskey/src/xilskey_bbram.c +++ b/lib/sw_services/xilskey/src/xilskey_bbram.c @@ -43,6 +43,7 @@ * Ver Who Date Changes * ----- ---- -------- -------------------------------------------------------- * 1.01a hk 09/18/13 First release +* 3.00 vns 31/07/15 Removed redundant code to initialise timer. * ****************************************************************************/ /***************************** Include Files *********************************/ @@ -102,8 +103,6 @@ extern void Bbram_DeInit(void); *****************************************************************************/ int XilSKey_Bbram_Program(XilSKey_Bbram *InstancePtr) { - u32 ArmPllFdiv; - u32 ArmClkDivisor; u32 RefClk; int Status; @@ -111,22 +110,8 @@ int XilSKey_Bbram_Program(XilSKey_Bbram *InstancePtr) return XST_FAILURE; } - /** - * Extract PLL FDIV value from ARM PLL Control Register - */ - ArmPllFdiv = (Xil_In32(XSK_ARM_PLL_CTRL_REG)>>12 & 0x7F); - - /** - * Extract Clock divisor value from ARM Clock Control Register - */ - ArmClkDivisor = (Xil_In32(XSK_ARM_CLK_CTRL_REG)>>8 & 0x3F); - - /** - * Initialize the variables - */ - RefClk = ((XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ * ArmClkDivisor)/ - ArmPllFdiv); - + /* Get timer values */ + RefClk = Xilskey_Timer_Intialise(); /* * Initialize and start the timer */ diff --git a/lib/sw_services/xilskey/src/xilskey_epl.c b/lib/sw_services/xilskey/src/xilskey_epl.c index 6a177b83..247d0128 100644 --- a/lib/sw_services/xilskey/src/xilskey_epl.c +++ b/lib/sw_services/xilskey/src/xilskey_epl.c @@ -198,8 +198,6 @@ u32 XilSKey_EfusePl_Program(XilSKey_EPl *InstancePtr) u8 CtrlData[XSK_EFUSEPL_ARRAY_FUSE_CNTRL_MAX_BITS]={0}; u32 Index = 0; u32 Status; - u32 RefClk; - u32 ArmPllFDiv,ArmClkDivisor; ErrorCode = XSK_EFUSEPL_ERROR_NONE; @@ -209,22 +207,10 @@ u32 XilSKey_EfusePl_Program(XilSKey_EPl *InstancePtr) if(!(InstancePtr->SystemInitDone)) { - /** - * Extract PLL FDIV value from ARM PLL Control Register - */ - ArmPllFDiv = (Xil_In32(XSK_ARM_PLL_CTRL_REG)>>12 & 0x7F); - - /** - * Extract Clock divisor value from ARM Clock Control Register - */ - ArmClkDivisor = (Xil_In32(XSK_ARM_CLK_CTRL_REG)>>8 & 0x3F); - - /** - * Initialize the variables - */ - RefClk = ((XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ * - ArmClkDivisor)/ ArmPllFDiv); +#ifdef XSK_ARM_PLATFORM + u32 RefClk; + RefClk = Xilskey_Timer_Intialise(); /** * Return error if the reference clock frequency is not in * between 20 & 60MHz @@ -239,13 +225,18 @@ u32 XilSKey_EfusePl_Program(XilSKey_EPl *InstancePtr) * server using the passed info. */ - XilSKey_Efuse_StartTimer(RefClk); + XilSKey_Efuse_StartTimer(); Status = XilSKey_EfusePs_XAdcInit(); if(Status != XST_SUCCESS) { ErrorCode = Status; return (XSK_EFUSEPL_ERROR_XADC + ErrorCode); + } +#else + if (Xilskey_Timer_Intialise() == XST_FAILURE) { + return (XSK_EFUSEPL_ERROR_TIMER_INTIALISE_ULTRA); } +#endif /** * Start using the Jtag server to read the JTAG ID and * compare with the stored ID, if it not matches return with @@ -1086,12 +1077,8 @@ void XilSKey_EfusePl_CalculateEcc(u8 *RowData, u8 *ECCData) *****************************************************************************/ u32 XilSKey_EfusePl_ReadStatus(XilSKey_EPl *InstancePtr, u32 *StatusBits) { - u32 RefClk; - u32 ArmPllFdiv; - u32 ArmClkDivisor; unsigned int RowData; - u32 Status; - XSKEfusePs_XAdc PL_XAdc; + XSKEfusePs_XAdc PL_XAdc = {0}; if(NULL == InstancePtr) { return XSK_EFUSEPL_ERROR_PL_STRUCT_NULL; @@ -1100,21 +1087,13 @@ u32 XilSKey_EfusePl_ReadStatus(XilSKey_EPl *InstancePtr, u32 *StatusBits) if(!(InstancePtr->SystemInitDone)) { - /** - * Extract PLL FDIV value from ARM PLL Control Register - */ - ArmPllFdiv = (Xil_In32(XSK_ARM_PLL_CTRL_REG)>>12 & 0x7F); - - /** - * Extract Clock divisor value from ARM Clock Control Register - */ - ArmClkDivisor = (Xil_In32(XSK_ARM_CLK_CTRL_REG)>>8 & 0x3F); - +#ifdef XSK_ARM_PLATFORM + u32 RefClk; + u32 Status; /** * Initialize the variables */ - RefClk = ((XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ * ArmClkDivisor)/ - ArmPllFdiv); + RefClk = Xilskey_Timer_Intialise(); /** * Return error if the reference clock frequency is not in @@ -1129,13 +1108,14 @@ u32 XilSKey_EfusePl_ReadStatus(XilSKey_EPl *InstancePtr, u32 *StatusBits) * Initialize the timer, XADC and jtag server */ - XilSKey_Efuse_StartTimer(RefClk); + XilSKey_Efuse_StartTimer(); Status = XilSKey_EfusePs_XAdcInit(); if(Status != XST_SUCCESS) { ErrorCode = Status; return (XSK_EFUSEPL_ERROR_XADC + ErrorCode); } +#endif if(JtagServerInit(InstancePtr) != XST_SUCCESS) { return XSK_EFUSEPL_ERROR_JTAG_SERVER_INIT; @@ -1201,9 +1181,6 @@ u32 XilSKey_EfusePl_ReadStatus(XilSKey_EPl *InstancePtr, u32 *StatusBits) *****************************************************************************/ u32 XilSKey_EfusePl_ReadKey(XilSKey_EPl *InstancePtr) { - u32 RefClk; - u32 ArmPllFdiv; - u32 ArmClkDivisor; u32 RowCount; unsigned int RowData; u32 KeyCnt; @@ -1217,21 +1194,9 @@ u32 XilSKey_EfusePl_ReadKey(XilSKey_EPl *InstancePtr) if(!(InstancePtr->SystemInitDone)) { - /** - * Extract PLL FDIV value from ARM PLL Control Register - */ - ArmPllFdiv = (Xil_In32(XSK_ARM_PLL_CTRL_REG)>>12 & 0x7F); - - /** - * Extract Clock divisor value from ARM Clock Control Register - */ - ArmClkDivisor = (Xil_In32(XSK_ARM_CLK_CTRL_REG)>>8 & 0x3F); - - /** - * Initialize the variables - */ - RefClk = ((XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ * ArmClkDivisor)/ - ArmPllFdiv); +#ifdef XSK_ARM_PLATFORM + u32 RefClk; + RefClk = Xilskey_Timer_Intialise(); /** * Return error if the reference clock frequency is not in @@ -1246,14 +1211,14 @@ u32 XilSKey_EfusePl_ReadKey(XilSKey_EPl *InstancePtr) * Initialize the timer and jtag server */ - XilSKey_Efuse_StartTimer(RefClk); + XilSKey_Efuse_StartTimer(); Status = XilSKey_EfusePs_XAdcInit(); if(Status != XST_SUCCESS) { ErrorCode = Status; return (XSK_EFUSEPL_ERROR_XADC + ErrorCode); } - +#endif if(JtagServerInit(InstancePtr) != XST_SUCCESS) { return XSK_EFUSEPL_ERROR_JTAG_SERVER_INIT; } diff --git a/lib/sw_services/xilskey/src/xilskey_eps.c b/lib/sw_services/xilskey/src/xilskey_eps.c index a03ac65d..03fd8585 100644 --- a/lib/sw_services/xilskey/src/xilskey_eps.c +++ b/lib/sw_services/xilskey/src/xilskey_eps.c @@ -45,7 +45,7 @@ * 1.02a hk 10/28/13 Added API to read status register.PR# 735957 * 2.00 hk 23/01/14 Changed PS efuse error codes for voltage out of range. * 2.1 sk 04/03/15 Initialized RSAKeyReadback with Zeros CR# 829723. -* +* 3.00 vns 31/07/15 Removed redundant code to initialise timer. * *****************************************************************************/ @@ -96,7 +96,6 @@ u32 XilSKey_EfusePs_Write(XilSKey_EPs *InstancePtr) { u32 Status, StatusRedundantBit, RetValue; u32 RefClk; - u32 ArmPllFDiv,ArmClkDivisor; RetValue = XST_SUCCESS; @@ -105,20 +104,7 @@ u32 XilSKey_EfusePs_Write(XilSKey_EPs *InstancePtr) return XSK_EFUSEPS_ERROR_PS_STRUCT_NULL; } - /** - * Extract PLL FDIV value from ARM PLL Control Register - */ - ArmPllFDiv = (Xil_In32(XSK_ARM_PLL_CTRL_REG)>>12 & 0x7F); - /** - * Extract Clock divisor value from ARM Clock Control Register - */ - ArmClkDivisor = (Xil_In32(XSK_ARM_CLK_CTRL_REG)>>8 & 0x3F); - - /** - * Initialize the variables - */ - RefClk = ((XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ * ArmClkDivisor)/ - ArmPllFDiv); + RefClk = Xilskey_Timer_Intialise(); /** * Check the variables @@ -316,7 +302,6 @@ u32 XilSKey_EfusePs_Read(XilSKey_EPs *InstancePtr) u32 Status, RetValue; u32 RefClk; - u32 ArmPllFDiv,ArmClkDivisor; u32 Index; RetValue = XST_SUCCESS; @@ -334,20 +319,7 @@ u32 XilSKey_EfusePs_Read(XilSKey_EPs *InstancePtr) InstancePtr->RsaKeyReadback[Index] = 0; } - /** - * Extract PLL FDIV value from ARM PLL Control Register - */ - ArmPllFDiv = (Xil_In32(XSK_ARM_PLL_CTRL_REG)>>12 & 0x7F); - /** - * Extract Clock divisor value from ARM Clock Control Register - */ - ArmClkDivisor = (Xil_In32(XSK_ARM_CLK_CTRL_REG)>>8 & 0x3F); - - /** - * Initialize the variables - */ - RefClk = ((XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ * ArmClkDivisor)/ - ArmPllFDiv); + RefClk = Xilskey_Timer_Intialise(); /** * Check the variables diff --git a/lib/sw_services/xilskey/src/xilskey_utils.c b/lib/sw_services/xilskey/src/xilskey_utils.c index c0b22387..8e9360bc 100644 --- a/lib/sw_services/xilskey/src/xilskey_utils.c +++ b/lib/sw_services/xilskey/src/xilskey_utils.c @@ -45,6 +45,8 @@ * 2.00 hk 22/01/14 Corrected PL voltage checks to VCCINT and VCCAUX. * CR#768077 * 2.1 kvn 04/01/15 Fixed warnings. CR#716453. +* 3.00 vns 31/07/15 Added efuse functionality for Ultrascale. +* *****************************************************************************/ /***************************** Include Files ********************************/ @@ -235,24 +237,10 @@ void XilSKey_EfusePs_XAdcReadTemperatureAndVoltage(XSKEfusePs_XAdc *XAdcInstance * @note None. * *****************************************************************************/ -void XilSKey_Efuse_StartTimer(u32 RefClk) +void XilSKey_Efuse_StartTimer() { - u32 arm_pll_fdiv,arm_clk_divisor; - TimerTicksfor100ns = 0; +#ifdef XSK_ARM_PLATFORM /** - * Extract PLL FDIV value from ARM PLL Control Register - */ - arm_pll_fdiv = (Xil_In32(XSK_ARM_PLL_CTRL_REG)>>12 & 0x7F); - /** - * Extract Clock divisor value from ARM Clock Control Register - */ - arm_clk_divisor = (Xil_In32(XSK_ARM_CLK_CTRL_REG)>>8 & 0x3F); - /** - * Calculate the Timer ticks per 100ns - */ - TimerTicksfor100ns = - (((RefClk * arm_pll_fdiv)/arm_clk_divisor)/2)/10000000; - /** * Disable the Timer counter */ Xil_Out32(XSK_GLOBAL_TIMER_CTRL_REG,0); @@ -268,6 +256,7 @@ void XilSKey_Efuse_StartTimer(u32 RefClk) * Enable the Timer counter */ Xil_Out32(XSK_GLOBAL_TIMER_CTRL_REG,0x1); +#endif } /****************************************************************************/ @@ -773,3 +762,71 @@ u32 XilSKey_Efuse_IsValidChar(const char *c) return XST_SUCCESS; } } +/****************************************************************************/ +/** + * This API intialises the Timer based on platform + * + * @param None. + * + * @return RefClk will be returned. + * + * @note None. + * + ****************************************************************************/ +u32 Xilskey_Timer_Intialise() +{ + + u32 RefClk; + +#ifdef XSK_ARM_PLATFORM + TimerTicksfor100ns = 0; + u32 ArmPllFdiv; + u32 ArmClkDivisor; + /** + * Extract PLL FDIV value from ARM PLL Control Register + */ + ArmPllFdiv = (Xil_In32(XSK_ARM_PLL_CTRL_REG)>>12 & 0x7F); + + /** + * Extract Clock divisor value from ARM Clock Control Register + */ + ArmClkDivisor = (Xil_In32(XSK_ARM_CLK_CTRL_REG)>>8 & 0x3F); + + /** + * Initialize the variables + */ + RefClk = ((XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ * ArmClkDivisor)/ + ArmPllFdiv); + + /** + * Calculate the Timer ticks per 100ns + */ + TimerTicksfor100ns = + (((RefClk * ArmPllFdiv)/ArmClkDivisor)/2)/10000000; +#else + + u32 Status; + TimerTicksfor500ns = 0; + + RefClk = XSK_EFUSEPL_CLCK_FREQ_ULTRA; + + Status = XTmrCtr_Initialize(&XTmrCtrInst, XTMRCTR_DEVICE_ID); + if (Status == XST_FAILURE) { + return XST_FAILURE; + } + /* + * Perform a self-test to ensure that the hardware was built + * correctly. + */ + Status = XTmrCtr_SelfTest(&XTmrCtrInst, XSK_TMRCTR_NUM); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + TimerTicksfor500ns = XSK_EFUSEPL_CLCK_FREQ_ULTRA/200000; + +#endif + + return RefClk; + +}