Copyright � 1995-2014 Xilinx, Inc. All rights reserved.
+ + \ No newline at end of file diff --git a/XilinxProcessorIPLib/drivers/ttcps/examples/xttcps_intr_example.c b/XilinxProcessorIPLib/drivers/ttcps/examples/xttcps_intr_example.c new file mode 100755 index 00000000..e635962d --- /dev/null +++ b/XilinxProcessorIPLib/drivers/ttcps/examples/xttcps_intr_example.c @@ -0,0 +1,666 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xttcps_intr_example.c +* +* This file contains a example using two timer counters in the Triple Timer +* Counter (TTC) module in the Ps block in interrupt mode. +* +* The example proceeds using interleaving interrupt handling from both +* timer counters. One timer counter, Ticker, counts how many interrupts +* has occurred to it, and updates a flag for another timer counter upon +* a given threshold. Another timer counter, PWM, waits for the flag set +* from the Ticker, and increases its duty cycle. When the duty cycle of +* PWM reaches 100, the example terminates. +* +* @note +* The example may take seconds to minutes to finish. A small setting of +* PWM_DELTA_DUTY gives a long running time, while a large setting makes +* the example finishes faster. +* +*+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ---- ------ -------- --------------------------------------------- +* 1.00 drg/jz 01/23/10 First release +*+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ---- ------ -------- --------------------------------------------- +* 1.00 drg/jz 01/23/10 First release +*+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xstatus.h" +#include "xttcps.h" +#include "xil_printf.h" + +/************************** Constant Definitions *****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are only defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define PCLK_FREQ_HZ XPAR_XTTCPS_0_CLOCK_HZ /* Input freq */ +#define TTC_NUM_DEVICES XPAR_XTTCPS_NUM_INSTANCES + +#define TABLE_OFFSET 6 +#define MAX_LOOP_COUNT 0xFFFF + +/**************************** Type Definitions *******************************/ + +typedef struct { + u32 OutputHz; /* The frequency the timer should output on the + waveout pin */ + u8 OutputDutyCycle; /* The duty cycle of the output wave as a + percentage */ + u8 PrescalerValue; /* Value of the prescaler in the Count Control + register */ +} TmrCntrSetup; + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +static int TmrCtrLowLevelExample(u8 SettingsTableOffset); + +/************************** Variable Definitions *****************************/ + +/* + * Convert from a 0-2 index to the correct timer counter number as defined in + * xttcps_hw.h + */ +static u32 TimerCounterBaseAddr[] = { + XPS_TTC0_BASEADDR, + XPS_TTC1_BASEADDR +}; + +/* + * A table of the actual prescaler setting based on the prescaler value from + * 0-15. The setting is 2^(prescaler value + 1). Use a table to avoid doing + * powers at run time. + * A Prescaler value of 16, means use no prescaler, or a prescaler value of 1. + */ +static u32 PrescalerSettings[] = { + 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, + 32768, 65536, 1 +}; + +static TmrCntrSetup SettingsTable[] = { + /* Table offset of 0 */ + {10, 50, 6}, + {10, 25, 6}, + {10, 75, 6}, + + /* Table offset of 3 */ + {100, 50, 3}, + {200, 25, 2}, + {400, 12.5, 1}, + + /* Table offset of 6 */ + {500, 50, 1}, + {1000, 50, 0}, + {5000, 50, 16}, + + /* Table offset of 9 */ + {10000, 50, 16}, + {50000, 50, 16}, + {100000, 50, 16}, + + /* Table offset of 12 */ + {500000, 50, 16}, + {1000000, 50, 16}, + {5000000, 50, 16}, + /* Note: at greater than 1 MHz the timer reload is noticeable. */ + +}; + +#define SETTINGS_TABLE_SIZE (sizeof(SettingsTable)/sizeof(TmrCntrSetup)) + +/*****************************************************************************/ +/** +* +* This function is the main function of the Timer/Counter example. +* +* @param None +* +* @return XST_SUCCESS to indicate success, else XST_FAILURE to indicate +* a Failure. +* +* @note None. +* +*****************************************************************************/ +int main(void) +{ + int Status; + + xil_printf("TTC Lowlevel Example Test \r\n"); + + /* + * Run the Timer Counter - Low Level example. + */ + Status = TmrCtrLowLevelExample(TABLE_OFFSET); + if (Status != XST_SUCCESS) { + xil_printf("TTC Lowlevel Example Test Failed\r\n"); + return XST_FAILURE; + } + + xil_printf("Successfully ran TTC Lowlevel Example Test\r\n"); + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* This function does a minimal test on the timer counter device and +* the low level driver as a design example. The purpose of this function is +* to illustrate how to use the XTtcPs low level driver. +* +* +* @param SettingsTableOffset is an offset into the settings table. This +* allows multiple counter setups to be kept and swapped easily. +* +* @return XST_SUCCESS to indicate success, else XST_FAILURE to indicate +* a Failure. +* +* @note +* +* This function contains a loop which waits for the value of a timer counter +* to change. If the hardware is not working correctly, this function may not +* return. +* +****************************************************************************/ +int TmrCtrLowLevelExample(u8 SettingsTableOffset) +{ + u32 RegValue; + u32 LoopCount; + u32 TmrCtrBaseAddress; + u32 IntervalValue, MatchValue; + TmrCntrSetup *CurrSetup; + + /* + * Assert on the value of constants calculated above + * Because the counters are 16 bits, no value can be greater than 65535 + */ + if ((SettingsTableOffset + 2) > SETTINGS_TABLE_SIZE) { + return XST_FAILURE; + } + + for (LoopCount = 0; LoopCount < TTC_NUM_DEVICES; LoopCount++) { + /* + * Set the timer counter number to use + */ + TmrCtrBaseAddress = TimerCounterBaseAddr[LoopCount]; + + /* And get the setup for that counter + */ + CurrSetup = &SettingsTable[SettingsTableOffset + LoopCount]; + + /* + * Set the Clock Control Register + */ + if (16 > CurrSetup->PrescalerValue) { + /* Use the clock prescaler */ + RegValue = + (CurrSetup-> + PrescalerValue << + XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) & + XTTCPS_CLK_CNTRL_PS_VAL_MASK; + RegValue |= XTTCPS_CLK_CNTRL_PS_EN_MASK; + } + else { + /* Do not use the clock prescaler */ + RegValue = 0; + } + XTtcPs_WriteReg(TmrCtrBaseAddress, XTTCPS_CLK_CNTRL_OFFSET, + RegValue); + + + /* + * Set the Interval register. This determines the frequency of + * the waveform. The counter will be reset to 0 each time this + * value is reached. + */ + IntervalValue = PCLK_FREQ_HZ / + (u32) (PrescalerSettings[CurrSetup->PrescalerValue] * + CurrSetup->OutputHz); + + /* + * Make sure the value is not to large or too small + */ + if ((65535 < IntervalValue) || (4 > IntervalValue)) { + return XST_FAILURE; + } + + XTtcPs_WriteReg(TmrCtrBaseAddress, + XTTCPS_INTERVAL_VAL_OFFSET, IntervalValue); + + /* + * Set the Match register. This determines the duty cycle of the + * waveform. The waveform output will be toggle each time this + * value is reached. + */ + MatchValue = (IntervalValue * CurrSetup->OutputDutyCycle) / 100; + + /* + * Make sure the value is not to large or too small + */ + if ((65535 < MatchValue) || (4 > MatchValue)) { + return XST_FAILURE; + } + XTtcPs_WriteReg(TmrCtrBaseAddress, XTTCPS_MATCH_0_OFFSET, + MatchValue); + + /* + * Set the Counter Control Register + */ + RegValue = + ~(XTTCPS_CNT_CNTRL_DIS_MASK | + XTTCPS_CNT_CNTRL_EN_WAVE_MASK) & + (XTTCPS_CNT_CNTRL_INT_MASK | + XTTCPS_CNT_CNTRL_MATCH_MASK | + XTTCPS_CNT_CNTRL_RST_MASK); + XTtcPs_WriteReg(TmrCtrBaseAddress, XTTCPS_CNT_CNTRL_OFFSET, + RegValue); + + /* + * Write to the Interrupt enable register. The status flags are + * not active if this is not done. + */ + XTtcPs_WriteReg(TmrCtrBaseAddress, XTTCPS_IER_OFFSET, + XTTCPS_IXR_INTERVAL_MASK); + } + + LoopCount = 0; + while (LoopCount < MAX_LOOP_COUNT) { + + /* + * Read the status register for debugging + */ + RegValue = + XTtcPs_ReadReg(TmrCtrBaseAddress, XTTCPS_ISR_OFFSET); + + /* + * Write the status register to clear the flags + */ + XTtcPs_WriteReg(TmrCtrBaseAddress, XTTCPS_ISR_OFFSET, + RegValue); + + if (0 != (XTTCPS_IXR_INTERVAL_MASK & RegValue)) { + LoopCount++; + /* + * Count the number of output cycles so the program will + * eventually exit. Otherwise it would stay in this loop + * indefinitely. + */ + } + } + + return XST_SUCCESS; +} diff --git a/XilinxProcessorIPLib/drivers/ttcps/examples/xttcps_rtc_example.c b/XilinxProcessorIPLib/drivers/ttcps/examples/xttcps_rtc_example.c new file mode 100755 index 00000000..4796091f --- /dev/null +++ b/XilinxProcessorIPLib/drivers/ttcps/examples/xttcps_rtc_example.c @@ -0,0 +1,490 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xttcps_rtc_example.c +* +* This example uses one timer/counter to make a real time clock. The number of +* minutes and seconds is displayed on the console. +* +* +* @note +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ---- ------ -------- --------------------------------------------- +* 1.00 drg/jz 01/23/10 First release +*+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- ------------------------------------------------- +* 1.00a drg/jz 01/21/10 First release +* +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xttcps.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + + +/*****************************************************************************/ +/** +* +* Initializes a specific XTtcPs instance such that the driver is ready to use. +* This function initializes a single timer counter in the triple timer counter +* function block. +* +* The state of the device after initialization is: +* - Overflow Mode +* - Internal (pclk) selected +* - Counter disabled +* - All Interrupts disabled +* - Output waveforms disabled +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param ConfigPtr is a reference to a structure containing information +* about a specific TTC device. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. The caller is responsible for keeping the address +* mapping from EffectiveAddr to the device physical base address +* unchanged once this function is invoked. Unexpected errors may +* occur if the address mapping changes after this function is +* called. If address translation is not used, then use +* ConfigPtr->BaseAddress for this parameter, passing the physical +* address instead. +* +* @return +* +* - XST_SUCCESS if the initialization is successful. +* - XST_DEVICE_IS_STARTED if the device is started. It must be +* stopped to re-initialize. +* +* @note Device has to be stopped first to call this function to +* initialize it. +* +******************************************************************************/ +int XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr, + u32 EffectiveAddr) +{ + /* + * Assert to validate input arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + /* + * Set some default values + */ + InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; + InstancePtr->Config.BaseAddress = EffectiveAddr; + InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz; + + /* + * If the timer counter has already started, return an error + * Device should be stopped first. + */ + if(XTtcPs_IsStarted(InstancePtr)) { + return XST_DEVICE_IS_STARTED; + } + + /* + * Reset the count control register to it's default value. + */ + XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, + XTTCPS_CNT_CNTRL_OFFSET, + XTTCPS_CNT_CNTRL_RESET_VALUE); + + /* + * Reset the rest of the registers to the default values. + */ + XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, + XTTCPS_CLK_CNTRL_OFFSET, 0x00); + XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, + XTTCPS_INTERVAL_VAL_OFFSET, 0x00); + XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, + XTTCPS_MATCH_1_OFFSET, 0x00); + XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, + XTTCPS_MATCH_2_OFFSET, 0x00); + XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, + XTTCPS_MATCH_2_OFFSET, 0x00); + XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, + XTTCPS_IER_OFFSET, 0x00); + XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, + XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK); + + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + /* + * Reset the counter value + */ + XTtcPs_ResetCounterValue(InstancePtr); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function is used to set the match registers. There are three match +* registers. +* +* The match 0 register is special. If the waveform output mode is enabled, the +* waveform will change polarity when the count matches the value in the match 0 +* register. The polarity of the waveform output can also be set using the +* XTtcPs_SetOptions() function. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param MatchIndex is the index to the match register to be set. +* Valid values are 0, 1, or 2. +* @param Value is the 16-bit value to be set in the match register. +* +* @return None +* +* @note None +* +****************************************************************************/ +void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value) +{ + /* + * Assert to validate input arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(MatchIndex < XTTCPS_NUM_MATCH_REG); + + /* + * Write the value to the correct match register with MatchIndex + */ + XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, + XTtcPs_Match_N_Offset(MatchIndex), Value); +} + +/*****************************************************************************/ +/** +* +* This function is used to get the value of the match registers. There are +* three match registers. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param MatchIndex is the index to the match register to be set. +* Valid values are 0, 1, or 2. +* +* @return None +* +* @note None +* +****************************************************************************/ +u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex) +{ + u32 MatchReg; + + /* + * Assert to validate input arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(MatchIndex < XTTCPS_NUM_MATCH_REG); + + MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, + XTtcPs_Match_N_Offset(MatchIndex)); + + return (u16) MatchReg; +} + +/*****************************************************************************/ +/** +* +* This function sets the prescaler enable bit and if needed sets the prescaler +* bits in the control register. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param PrescalerValue is a number from 0-16 that sets the prescaler +* to use. +* If the parameter is 0 - 15, use a prescaler on the clock of +* 2^(PrescalerValue+1), or 2-65536. +* If the parameter is XTTCPS_CLK_CNTRL_PS_DISABLE, do not use a +* prescaler. +* +* @return None +* +* @note None +* +****************************************************************************/ +void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue) +{ + u32 ClockReg; + + /* + * Assert to validate input arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(PrescalerValue <= XTTCPS_CLK_CNTRL_PS_DISABLE); + + /* + * Read the clock control register + */ + ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, + XTTCPS_CLK_CNTRL_OFFSET); + + /* + * Clear all of the prescaler control bits in the register + */ + ClockReg &= + ~(XTTCPS_CLK_CNTRL_PS_VAL_MASK | XTTCPS_CLK_CNTRL_PS_EN_MASK); + + if (PrescalerValue < XTTCPS_CLK_CNTRL_PS_DISABLE) { + /* + * Set the prescaler value and enable prescaler + */ + ClockReg |= (PrescalerValue << XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) & + XTTCPS_CLK_CNTRL_PS_VAL_MASK; + ClockReg |= XTTCPS_CLK_CNTRL_PS_EN_MASK; + } + + /* + * Write the register with the new values. + */ + XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, + XTTCPS_CLK_CNTRL_OFFSET, ClockReg); +} + +/*****************************************************************************/ +/** +* +* This function gets the input clock prescaler +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +*
+* @return The value(n) from which the prescalar value is calculated +* as 2^(n+1). Some example values are given below : +* +* Value Prescaler +* 0 2 +* 1 4 +* N 2^(n+1) +* 15 65536 +* 16 1 +*+* +* @note None. +* +****************************************************************************/ +u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr) +{ + u32 ClockReg; + + /* + * Assert to validate input arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the clock control register + */ + ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, + XTTCPS_CLK_CNTRL_OFFSET); + + if (0 == (ClockReg & XTTCPS_CLK_CNTRL_PS_EN_MASK)) { + /* + * Prescaler is disabled. Return the correct flag value + */ + return XTTCPS_CLK_CNTRL_PS_DISABLE; + } + + return ((ClockReg & XTTCPS_CLK_CNTRL_PS_VAL_MASK) >> + XTTCPS_CLK_CNTRL_PS_VAL_SHIFT); +} + +/*****************************************************************************/ +/** +* +* This function calculates the interval value as well as the prescaler value +* for a given frequency. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param Freq is the requested output frequency for the device. +* @param Interval is the interval value for the given frequency, +* it is the output value for this function. +* @param Prescaler is the prescaler value for the given frequency, +* it is the output value for this function. +* +* @return None. +* +* @note +* Upon successful calculation for the given frequency, Interval and Prescaler +* carry the settings for the timer counter; Upon unsuccessful calculation, +* Interval and Prescaler are set to 0xFF(FF) for their maximum values to +* signal the caller of failure. Therefore, caller needs to check the return +* interval or prescaler values for whether the function has succeeded. +* +****************************************************************************/ +void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq, + u16 *Interval, u8 *Prescaler) +{ + u8 TmpPrescaler; + u32 TempValue; + u32 InputClock; + + InputClock = InstancePtr->Config.InputClockHz; + /* + * Find the smallest prescaler that will work for a given frequency. The + * smaller the prescaler, the larger the count and the more accurate the + * PWM setting. + */ + TempValue = InputClock/ Freq; + + if (TempValue < 4) { + /* + * The frequency is too high, it is too close to the input + * clock value. Use maximum values to signal caller. + */ + *Interval = 0xFFFF; + *Prescaler = 0xFF; + return; + } + + /* + * First, do we need a prescaler or not? + */ + if (65536 > TempValue) { + /* + * We do not need a prescaler, so set the values appropriately + */ + *Interval = TempValue; + *Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE; + return; + } + + + for (TmpPrescaler = 0; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE; + TmpPrescaler++) { + TempValue = InputClock/ (Freq * (1 << (TmpPrescaler + 1))); + + /* + * The first value less than 2^16 is the best bet + */ + if (65536 > TempValue) { + /* + * Set the values appropriately + */ + *Interval = TempValue; + *Prescaler = TmpPrescaler; + return; + } + } + + /* Can not find interval values that work for the given frequency. + * Return maximum values to signal caller. + */ + *Interval = 0XFFFF; + *Prescaler = 0XFF; + return; +} diff --git a/XilinxProcessorIPLib/drivers/ttcps/src/xttcps.h b/XilinxProcessorIPLib/drivers/ttcps/src/xttcps.h new file mode 100755 index 00000000..b99336e2 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/ttcps/src/xttcps.h @@ -0,0 +1,407 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xttcps.h +* +* This is the driver for one 16-bit timer counter in the Triple Timer Counter +* (TTC) module in the Ps block. +* +* The TTC module provides three independent timer/counter modules that can each +* be clocked using either the system clock (pclk) or an externally driven +* clock (ext_clk). In addition, each counter can independently prescale its +* selected clock input (divided by 2 to 65536). Counters can be set to +* decrement or increment. +* +* Each of the counters can be programmed to generate interrupt pulses: +* . At a regular, predefined period, that is on a timed interval +* . When the counter registers overflow +* . When the count matches any one of the three 'match' registers +* +* Therefore, up to six different events can trigger a timer interrupt: three +* match interrupts, an overflow interrupt, an interval interrupt and an event +* timer interrupt. Note that the overflow interrupt and the interval interrupt +* are mutually exclusive. +* +* Initialization & Configuration +* +* An XTtcPs_Config structure is used to configure a driver instance. +* Information in the XTtcPs_Config structure is the hardware properties +* about the device. +* +* A driver instance is initialized through +* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr +* is a pointer to the XTtcPs_Config structure, it can be looked up statically +* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The +* EffectiveAddr can be the static base address of the device or virtual +* mapped address if address translation is supported. +* +* Interrupts +* +* Interrupt handler is not provided by the driver, as handling of interrupt +* is application specific. +* +* @note +* The default setting for a timer/counter is: +* - Overflow Mode +* - Internal clock (pclk) selected +* - Counter disabled +* - All Interrupts disabled +* - Output waveforms disabled +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- ----------------------------------------------------- +* 1.00a drg/jz 01/20/10 First release.. +* 2.0 adk 12/10/13 Updated as per the New Tcl API's +* 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp +*+* +******************************************************************************/ + +#ifndef XTTCPS_H /* prevent circular inclusions */ +#define XTTCPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xttcps_hw.h" +#include "xstatus.h" + +/************************** Constant Definitions *****************************/ + +/** @name Configuration options + * + * Options for the device. Each of the options is bit field, so more than one + * options can be specified. + * + * @{ + */ +#define XTTCPS_OPTION_EXTERNAL_CLK 0x0001 /**< External clock source */ +#define XTTCPS_OPTION_CLK_EDGE_NEG 0x0002 /**< Clock on trailing edge for + external clock*/ +#define XTTCPS_OPTION_INTERVAL_MODE 0x0004 /**< Interval mode */ +#define XTTCPS_OPTION_DECREMENT 0x0008 /**< Decrement the counter */ +#define XTTCPS_OPTION_MATCH_MODE 0x0010 /**< Match mode */ +#define XTTCPS_OPTION_WAVE_DISABLE 0x0020 /**< No waveform output */ +#define XTTCPS_OPTION_WAVE_POLARITY 0x0040 /**< Waveform polarity */ +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID for device */ + u32 BaseAddress; /**< Base address for device */ + u32 InputClockHz; /**< Input clock frequency */ +} XTtcPs_Config; + +/** + * The XTtcPs driver instance data. The user is required to allocate a + * variable of this type for each PS timer/counter device in the system. A + * pointer to a variable of this type is then passed to various driver API + * functions. + */ +typedef struct { + XTtcPs_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ +} XTtcPs; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/* + * Internal helper macros + */ +#define InstReadReg(InstancePtr, RegOffset) \ + (Xil_In32(((InstancePtr)->Config.BaseAddress) + (RegOffset))) + +#define InstWriteReg(InstancePtr, RegOffset, Data) \ + (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (RegOffset), (Data))) + +/*****************************************************************************/ +/** +* +* This function starts the counter/timer without resetting the counter value. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_Start(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_Start(InstancePtr) \ + InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \ + ~XTTCPS_CNT_CNTRL_DIS_MASK)) + +/*****************************************************************************/ +/** +* +* This function stops the counter/timer. This macro may be called at any time +* to stop the counter. The counter holds the last value until it is reset, +* restarted or enabled. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_Stop(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_Stop(InstancePtr) \ + InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \ + XTTCPS_CNT_CNTRL_DIS_MASK)) + +/*****************************************************************************/ +/** +* +* This function checks whether the timer counter has already started. +* +* @param InstancePtr is a pointer to the XTtcPs instance +* +* @return Non-zero if the device has started, '0' otherwise. +* +* @note C-style signature: +* int XTtcPs_IsStarted(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_IsStarted(InstancePtr) \ + (int)((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \ + XTTCPS_CNT_CNTRL_DIS_MASK) == 0) + +/*****************************************************************************/ +/** +* +* This function returns the current 16-bit counter value. It may be called at +* any time. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return 16-bit counter value. +* +* @note C-style signature: +* u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_GetCounterValue(InstancePtr) \ + (u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET) + +/*****************************************************************************/ +/** +* +* This function sets the interval value to be used in interval mode. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param Value is the 16-bit value to be set in the interval register. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value) +* +****************************************************************************/ +#define XTtcPs_SetInterval(InstancePtr, Value) \ + InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value)) + +/*****************************************************************************/ +/** +* +* This function gets the interval value from the interval register. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return 16-bit interval value +* +* @note C-style signature: +* u16 XTtcPs_GetInterval(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_GetInterval(InstancePtr) \ + (u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET) + +/*****************************************************************************/ +/** +* +* This macro resets the count register. It may be called at any time. The +* counter is reset to either 0 or 0xFFFF, or the interval value, depending on +* the increment/decrement mode. The state of the counter, as started or +* stopped, is not affected by calling reset. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_ResetCounterValue(InstancePtr) \ + InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \ + XTTCPS_CNT_CNTRL_RST_MASK)) + +/*****************************************************************************/ +/** +* +* This function enables the interrupts. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param InterruptMask defines which interrupt should be enabled. +* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*. +* This is a bit mask, all set bits will be enabled, cleared bits +* will not be disabled. +* +* @return None. +* +* @note +* C-style signature: +* void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask) +* +******************************************************************************/ +#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask) \ + InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) | \ + (InterruptMask))) + +/*****************************************************************************/ +/** +* +* This function disables the interrupts. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param InterruptMask defines which interrupt should be disabled. +* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*. +* This is a bit mask, all set bits will be disabled, cleared bits +* will not be disabled. +* +* @return None. +* +* @note +* C-style signature: +* void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask) +* +******************************************************************************/ +#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \ + InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) & \ + ~(InterruptMask))) + +/*****************************************************************************/ +/** +* +* This function reads the interrupt status. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None. +* +* @note C-style signature: +* u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr) +* +******************************************************************************/ +#define XTtcPs_GetInterruptStatus(InstancePtr) \ + InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET) + +/*****************************************************************************/ +/** +* +* This function clears the interrupt status. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param InterruptMask defines which interrupt should be cleared. +* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*. +* This is a bit mask, all set bits will be cleared, cleared bits +* will not be cleared. +* +* @return None. +* +* @note +* C-style signature: +* void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask) +* +******************************************************************************/ +#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \ + InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \ + (InterruptMask)) + + +/************************** Function Prototypes ******************************/ + +/* + * Initialization functions in xttcps_sinit.c + */ +XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId); + +/* + * Required functions, in xttcps.c + */ +int XTtcPs_CfgInitialize(XTtcPs *InstancePtr, + XTtcPs_Config * ConfigPtr, u32 EffectiveAddr); + +void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value); +u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex); + +void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue); +u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr); + +void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq, + u16 *Interval, u8 *Prescaler); + +/* + * Functions for options, in file xttcps_options.c + */ +int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options); +u32 XTtcPs_GetOptions(XTtcPs *InstancePtr); + +/* + * Function for self-test, in file xttcps_selftest.c + */ +int XTtcPs_SelfTest(XTtcPs *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/XilinxProcessorIPLib/drivers/ttcps/src/xttcps_g.c b/XilinxProcessorIPLib/drivers/ttcps/src/xttcps_g.c new file mode 100755 index 00000000..d9e69544 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/ttcps/src/xttcps_g.c @@ -0,0 +1,119 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xttcps_g.c +* +* This file contains a configuration table where each entry is the +* configuration information for one timer counter device in the system. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- ----------------------------------------------- +* 1.00a drg/jz 01/21/10 First release +* 2.00 hk 22/01/14 Added check for picking instances other than +* default. +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xttcps.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Prototypes ******************************/ + +/** + * This table contains configuration information for each TTC device + * in the system. + */ +XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES] = { + { + XPAR_XTTCPS_0_DEVICE_ID, /* Device ID for instance */ + XPAR_XTTCPS_0_BASEADDR, /* Device base address */ + XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ /* Device input clock frequency */ + }, +#ifdef XPAR_XTTCPS_1_DEVICE_ID + { + XPAR_XTTCPS_1_DEVICE_ID, /* Device ID for instance */ + XPAR_XTTCPS_1_BASEADDR, /* Device base address */ + XPAR_XTTCPS_1_CLOCK_HZ /* Device input clock frequency */ + }, +#endif + +#ifdef XPAR_XTTCPS_2_DEVICE_ID + { + XPAR_XTTCPS_2_DEVICE_ID, /* Device ID for instance */ + XPAR_XTTCPS_2_BASEADDR, /* Device base address */ + XPAR_XTTCPS_2_CLOCK_HZ /* Device input clock frequency */ + }, +#endif + +#ifdef XPAR_XTTCPS_3_DEVICE_ID + { + XPAR_XTTCPS_3_DEVICE_ID, /* Device ID for instance */ + XPAR_XTTCPS_3_BASEADDR, /* Device base address */ + XPAR_XTTCPS_3_CLOCK_HZ /* Device input clock frequency */ + }, +#endif + +#ifdef XPAR_XTTCPS_4_DEVICE_ID + { + XPAR_XTTCPS_4_DEVICE_ID, /* Device ID for instance */ + XPAR_XTTCPS_4_BASEADDR, /* Device base address */ + XPAR_XTTCPS_4_CLOCK_HZ /* Device input clock frequency */ + }, +#endif + +#ifdef XPAR_XTTCPS_5_DEVICE_ID + { + XPAR_XTTCPS_5_DEVICE_ID, /* Device ID for instance */ + XPAR_XTTCPS_5_BASEADDR, /* Device base address */ + XPAR_XTTCPS_5_CLOCK_HZ /* Device input clock frequency */ + }, +#endif +}; diff --git a/XilinxProcessorIPLib/drivers/ttcps/src/xttcps_hw.h b/XilinxProcessorIPLib/drivers/ttcps/src/xttcps_hw.h new file mode 100755 index 00000000..1c223226 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/ttcps/src/xttcps_hw.h @@ -0,0 +1,208 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xttcps_hw.h +* +* This file defines the hardware interface to one of the three timer counters +* in the Ps block. +* +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- ------------------------------------------------- +* 1.00a drg/jz 01/21/10 First release +* +*+* +******************************************************************************/ + +#ifndef XTTCPS_HW_H /* prevent circular inclusions */ +#define XTTCPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets from the base address of the device. + * + * @{ + */ +#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000 /**< Clock Control Register */ +#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000C /**< Counter Control Register*/ +#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018 /**< Current Counter Value */ +#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024 /**< Interval Count Value */ +#define XTTCPS_MATCH_0_OFFSET 0x00000030 /**< Match 1 value */ +#define XTTCPS_MATCH_1_OFFSET 0x0000003C /**< Match 2 value */ +#define XTTCPS_MATCH_2_OFFSET 0x00000048 /**< Match 3 value */ +#define XTTCPS_ISR_OFFSET 0x00000054 /**< Interrupt Status Register */ +#define XTTCPS_IER_OFFSET 0x00000060 /**< Interrupt Enable Register */ +/* @} */ + +/** @name Clock Control Register + * Clock Control Register definitions + * @{ + */ +#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001 /**< Prescale enable */ +#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001E /**< Prescale value */ +#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1 /**< Prescale shift */ +#define XTTCPS_CLK_CNTRL_PS_DISABLE 16 /**< Prescale disable */ +#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020 /**< Clock source */ +#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040 /**< External Clock edge */ +/* @} */ + +/** @name Counter Control Register + * Counter Control Register definitions + * @{ + */ +#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001 /**< Disable the counter */ +#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002 /**< Interval mode */ +#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004 /**< Decrement mode */ +#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008 /**< Match mode */ +#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010 /**< Reset counter */ +#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020 /**< Enable waveform */ +#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040 /**< Waveform polarity */ +#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021 /**< Reset value */ +/* @} */ + +/** @name Current Counter Value Register + * Current Counter Value Register definitions + * @{ + */ +#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFF /**< 16-bit counter value */ +/* @} */ + +/** @name Interval Value Register + * Interval Value Register is the maximum value the counter will count up or + * down to. + * @{ + */ +#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFF /**< 16-bit Interval value*/ +/* @} */ + +/** @name Match Registers + * Definitions for Match registers, each timer counter has three match + * registers. + * @{ + */ +#define XTTCPS_MATCH_MASK 0x0000FFFF /**< 16-bit Match value */ +#define XTTCPS_NUM_MATCH_REG 3 /**< Num of Match reg */ +/* @} */ + +/** @name Interrupt Registers + * Following register bit mask is for all interrupt registers. + * + * @{ + */ +#define XTTCPS_IXR_INTERVAL_MASK 0x00000001 /**< Interval Interrupt */ +#define XTTCPS_IXR_MATCH_0_MASK 0x00000002 /**< Match 1 Interrupt */ +#define XTTCPS_IXR_MATCH_1_MASK 0x00000004 /**< Match 2 Interrupt */ +#define XTTCPS_IXR_MATCH_2_MASK 0x00000008 /**< Match 3 Interrupt */ +#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010 /**< Counter Overflow */ +#define XTTCPS_IXR_ALL_MASK 0x0000001F /**< All valid Interrupts */ +/* @} */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given Timer Counter register. +* +* @param BaseAddress is the base address of the timer counter device. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XTtcPs_ReadReg(BaseAddress, RegOffset) \ + (Xil_In32((BaseAddress) + (RegOffset))) + +/****************************************************************************/ +/** +* +* Write the given Timer Counter register. +* +* @param BaseAddress is the base address of the timer counter device. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset, +* u32 Data) +* +*****************************************************************************/ +#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \ + (Xil_Out32((BaseAddress) + (RegOffset), (Data))) + +/****************************************************************************/ +/** +* +* Calculate a match register offset using the Match Register index. +* +* @param MatchIndex is the 0-2 value of the match register +* +* @return MATCH_N_OFFSET. +* +* @note C-style signature: +* u32 XTtcPs_Match_N_Offset(u8 MatchIndex) +* +*****************************************************************************/ +#define XTtcPs_Match_N_Offset(MatchIndex) \ + (XTTCPS_MATCH_0_OFFSET + (12 * (MatchIndex))) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif +#endif /* end of protection macro */ diff --git a/XilinxProcessorIPLib/drivers/ttcps/src/xttcps_options.c b/XilinxProcessorIPLib/drivers/ttcps/src/xttcps_options.c new file mode 100755 index 00000000..b4ae573f --- /dev/null +++ b/XilinxProcessorIPLib/drivers/ttcps/src/xttcps_options.c @@ -0,0 +1,232 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xttcps_options.c +* +* This file contains functions to get or set option features for the device. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- --------------------------------------------- +* 1.00a drg/jz 01/21/10 First release +* 1.01a nm 03/05/2012 Removed break statement after return to remove +* compilation warnings. +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xttcps.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Definitions *****************************/ + +/* + * Create the table of options which are processed to get/set the device + * options. These options are table driven to allow easy maintenance and + * expansion of the options. + */ +typedef struct { + u32 Option; + u32 Mask; + u32 Register; +} OptionsMap; + +static OptionsMap TmrCtrOptionsTable[] = { + {XTTCPS_OPTION_EXTERNAL_CLK, XTTCPS_CLK_CNTRL_SRC_MASK, + XTTCPS_CLK_CNTRL_OFFSET}, + {XTTCPS_OPTION_CLK_EDGE_NEG, XTTCPS_CLK_CNTRL_EXT_EDGE_MASK, + XTTCPS_CLK_CNTRL_OFFSET}, + {XTTCPS_OPTION_INTERVAL_MODE, XTTCPS_CNT_CNTRL_INT_MASK, + XTTCPS_CNT_CNTRL_OFFSET}, + {XTTCPS_OPTION_DECREMENT, XTTCPS_CNT_CNTRL_DECR_MASK, + XTTCPS_CNT_CNTRL_OFFSET}, + {XTTCPS_OPTION_MATCH_MODE, XTTCPS_CNT_CNTRL_MATCH_MASK, + XTTCPS_CNT_CNTRL_OFFSET}, + {XTTCPS_OPTION_WAVE_DISABLE, XTTCPS_CNT_CNTRL_EN_WAVE_MASK, + XTTCPS_CNT_CNTRL_OFFSET}, + {XTTCPS_OPTION_WAVE_POLARITY, XTTCPS_CNT_CNTRL_POL_WAVE_MASK, + XTTCPS_CNT_CNTRL_OFFSET}, +}; + +#define XTTCPS_NUM_TMRCTR_OPTIONS (sizeof(TmrCtrOptionsTable) / \ + sizeof(OptionsMap)) + +/*****************************************************************************/ +/** +* +* This function sets the options for the TTC device. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param Options contains the specified options to be set. This is a bit +* mask where a 1 means to turn the option on, and a 0 means to +* turn the option off. One or more bit values may be contained +* in the mask. See the bit definitions named XTTCPS_*_OPTION in +* the file xttcps.h. +* +* @return +* - XST_SUCCESS if options are successfully set. +* - XST_FAILURE if any of the options are unknown. +* +* @note None +* +******************************************************************************/ +int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options) +{ + u32 CountReg; + u32 ClockReg; + unsigned Index; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, + XTTCPS_CLK_CNTRL_OFFSET); + CountReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, + XTTCPS_CNT_CNTRL_OFFSET); + + /* + * Loop through the options table, turning the option on or off + * depending on whether the bit is set in the incoming options flag. + */ + for (Index = 0; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) { + if (Options & TmrCtrOptionsTable[Index].Option) { + + switch (TmrCtrOptionsTable[Index].Register) { + + case XTTCPS_CLK_CNTRL_OFFSET: + /* Add option */ + ClockReg |= TmrCtrOptionsTable[Index].Mask; + break; + + case XTTCPS_CNT_CNTRL_OFFSET: + /* Add option */ + CountReg |= TmrCtrOptionsTable[Index].Mask; + break; + + default: + return XST_FAILURE; + } + } + else { + switch (TmrCtrOptionsTable[Index].Register) { + + case XTTCPS_CLK_CNTRL_OFFSET: + /* Remove option*/ + ClockReg &= ~TmrCtrOptionsTable[Index].Mask; + break; + + case XTTCPS_CNT_CNTRL_OFFSET: + /* Remove option*/ + CountReg &= ~TmrCtrOptionsTable[Index].Mask; + break; + + default: + return XST_FAILURE; + } + } + } + + /* + * Now write the registers. Leave it to the upper layers to restart the + * device. + */ + XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, + XTTCPS_CLK_CNTRL_OFFSET, ClockReg); + XTtcPs_WriteReg(InstancePtr->Config.BaseAddress, + XTTCPS_CNT_CNTRL_OFFSET, CountReg); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function gets the settings for the options for the TTC device. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return +* +* The return u32 contains the specified options that are set. This is a bit +* mask where a '1' means the option is on, and a'0' means the option is off. +* One or more bit values may be contained in the mask. See the bit definitions +* named XTTCPS_*_OPTION in the file xttcps.h. +* +* @note None. +* +******************************************************************************/ +u32 XTtcPs_GetOptions(XTtcPs *InstancePtr) +{ + u32 OptionsFlag = 0; + u32 Register; + unsigned Index; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + /* + * Loop through the options table to determine which options are set + */ + for (Index = 0; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) { + /* + * Get the control register to determine which options are + * currently set. + */ + Register = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, + TmrCtrOptionsTable[Index]. + Register); + + if (Register & TmrCtrOptionsTable[Index].Mask) { + OptionsFlag |= TmrCtrOptionsTable[Index].Option; + } + } + + return OptionsFlag; +} diff --git a/XilinxProcessorIPLib/drivers/ttcps/src/xttcps_selftest.c b/XilinxProcessorIPLib/drivers/ttcps/src/xttcps_selftest.c new file mode 100755 index 00000000..c81f2dc3 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/ttcps/src/xttcps_selftest.c @@ -0,0 +1,102 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xttcps_selftest.c +* +* This file contains the implementation of self test function for the +* XTtcPs driver. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- --------------------------------------------- +* 1.00a drg/jz 01/21/10 First release +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xttcps.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Definitions *****************************/ + + +/*****************************************************************************/ +/** +* +* Runs a self-test on the driver/device. +* +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return +* +* - XST_SUCCESS if successful +* - XST_FAILURE indicates a register did not read or write correctly +* +* @note This test fails if it is not called right after initialization. +* +******************************************************************************/ +int XTtcPs_SelfTest(XTtcPs *InstancePtr) +{ + u32 TempReg; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * All the TTC registers should be in their default state right now. + */ + TempReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, + XTTCPS_CNT_CNTRL_OFFSET); + if (XTTCPS_CNT_CNTRL_RESET_VALUE != TempReg) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} diff --git a/XilinxProcessorIPLib/drivers/ttcps/src/xttcps_sinit.c b/XilinxProcessorIPLib/drivers/ttcps/src/xttcps_sinit.c new file mode 100755 index 00000000..8a69cc10 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/ttcps/src/xttcps_sinit.c @@ -0,0 +1,94 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xttcps_sinit.c +* +* The implementation of the XTtcPs driver's static initialization functionality. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- --------------------------------------------- +* 1.00a drg/jz 01/21/10 First release +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xttcps.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +extern XTtcPs_Config XTtcPs_ConfigTable[]; + +/*****************************************************************************/ +/** +* +* Looks up the device configuration based on the unique device ID. A table +* contains the configuration info for each device in the system. +* +* @param DeviceId contains the unique ID of the device +* +* @return +* +* A pointer to the configuration found or NULL if the specified device ID was +* not found. See xttcps.h for the definition of XTtcPs_Config. +* +* @note None. +* +******************************************************************************/ +XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId) +{ + XTtcPs_Config *CfgPtr = NULL; + unsigned Index; + + for (Index = 0; Index < XPAR_XTTCPS_NUM_INSTANCES; Index++) { + if (XTtcPs_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XTtcPs_ConfigTable[Index]; + break; + } + } + + return CfgPtr; +}