From 062b550ad670f53a9b77af8a68789724c84c4c52 Mon Sep 17 00:00:00 2001 From: Andrei-Liviu Simion Date: Tue, 30 Jun 2015 15:56:20 -0700 Subject: [PATCH] dp: Fixed typos. Signed-off-by: Andrei-Liviu Simion --- XilinxProcessorIPLib/drivers/dp/src/xdp.c | 22 ++++++++-------- XilinxProcessorIPLib/drivers/dp/src/xdp.h | 2 +- .../drivers/dp/src/xdp_edid.c | 2 +- XilinxProcessorIPLib/drivers/dp/src/xdp_hw.h | 26 +++++++++---------- XilinxProcessorIPLib/drivers/dp/src/xdp_mst.c | 4 +-- XilinxProcessorIPLib/drivers/dp/src/xdp_spm.c | 2 +- 6 files changed, 29 insertions(+), 29 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdp.c b/XilinxProcessorIPLib/drivers/dp/src/xdp.c index 18680004..73733284 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdp.c +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp.c @@ -407,7 +407,7 @@ u32 XDp_TxEstablishLink(XDp *InstancePtr) return XST_FAILURE; } - /* Reenable main link after training if required. */ + /* Re-enable main link after training if required. */ if (ReenableMainLink) { XDp_TxEnableMainLink(InstancePtr); } @@ -417,8 +417,8 @@ u32 XDp_TxEstablishLink(XDp *InstancePtr) /******************************************************************************/ /** - * This function checks if the reciever's DisplayPort Configuration Data (DPCD) - * indicates the reciever has achieved and maintained clock recovery, channel + * This function checks if the receiver's DisplayPort Configuration Data (DPCD) + * indicates the receiver has achieved and maintained clock recovery, channel * equalization, symbol lock, and interlane alignment for all lanes currently in * use. * @@ -1424,7 +1424,7 @@ void XDp_TxSetPhyPolarityLane(XDp *InstancePtr, u8 Lane, u8 Polarity) /******************************************************************************/ /** - * This function checks if the reciever's internal registers indicate that link + * This function checks if the receiver's internal registers indicate that link * training has complete. That is, training has achieved channel equalization, * symbol lock, and interlane alignment for all lanes currently in use. * @@ -2047,7 +2047,7 @@ static u32 XDp_TxRunTraining(XDp *InstancePtr) * - XDP_TX_TS_CHANNEL_EQUALIZATION if the clock recovery sequence * completed successfully. * - XDP_TX_TS_FAILURE if writing the drive settings to the RX - * device was unsuccesful. + * device was unsuccessful. * - XDP_TX_TS_ADJUST_LINK_RATE if the clock recovery sequence * did not complete successfully. * @@ -2158,7 +2158,7 @@ static XDp_TxTrainingState XDp_TxTrainingStateClockRecovery(XDp *InstancePtr) * @return The next training state: * - XDP_TX_TS_SUCCESS if training succeeded. * - XDP_TX_TS_FAILURE if writing the drive settings to the RX - * device was unsuccesful. + * device was unsuccessful. * - XDP_TX_TS_ADJUST_LINK_RATE if, after 5 loop iterations, the * channel equalization sequence did not complete successfully. * @@ -2214,8 +2214,8 @@ static XDp_TxTrainingState XDp_TxTrainingStateChannelEqualization( break; } - /* Check that all lanes stihave accomplished channel - * equalization, symbol lock, and interlane alignment. */ + /* Check if all lanes have accomplished channel equalization, + * symbol lock, and interlane alignment. */ Status = XDp_TxCheckChannelEqualization(InstancePtr, InstancePtr->TxInstance.LinkConfig.LaneCount); if (Status == XST_SUCCESS) { @@ -2232,8 +2232,8 @@ static XDp_TxTrainingState XDp_TxTrainingStateChannelEqualization( IterationCount++; } - /* Tried MaxIteration times with no success. Try a reduced bitrate - * first, then reduce the number of lanes. */ + /* Tried 5 times with no success. Try a reduced bitrate first, then + * reduce the number of lanes. */ return XDP_TX_TS_ADJUST_LINK_RATE; } @@ -2673,7 +2673,7 @@ static u32 XDp_TxAdjVswingPreemp(XDp *InstancePtr) /* Verify that the voltage swing and pre-emphasis combination is * allowed. Some combinations will result in a differential peak-to-peak - * voltage that is outside the permissable range. See the VESA + * voltage that is outside the permissible range. See the VESA * DisplayPort v1.2 Specification, section 3.1.5.2. * The valid combinations are: * PE=0 PE=1 PE=2 PE=3 diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdp.h b/XilinxProcessorIPLib/drivers/dp/src/xdp.h index 1cf5dec7..21234d0b 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdp.h +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp.h @@ -168,7 +168,7 @@ * depending on whether a an HPD event on an HPD pulse event occurred. * * The DisplayPort TX's XDP_TX_INTERRUPT_STATUS register indicates the type of - * interrupt that has occured, and the XDp_TxInterruptHandler will use this + * interrupt that has occurred, and the XDp_TxInterruptHandler will use this * information to decide which handler to call. An HPD event is identified if * bit XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is * identified from the XDP_TX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit. diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdp_edid.c b/XilinxProcessorIPLib/drivers/dp/src/xdp_edid.c index 3313a0f3..bbf2bbbc 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdp_edid.c +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp_edid.c @@ -323,7 +323,7 @@ u32 XDp_TxGetDispIdDataBlock(u8 *DisplayIdRaw, u8 SectionTag, u8 **DataBlockPtr) for (Index = XDP_TX_DISPID_PAYLOAD_START; Index < DispIdSize; Index++) { DataBlock = &DisplayIdRaw[Index]; - /* Check if the tag mataches the current section data block. */ + /* Check if the tag matches the current section data block. */ if (DataBlock[XDP_TX_DISPID_DB_SEC_TAG] == SectionTag) { *DataBlockPtr = DataBlock; return XST_SUCCESS; diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdp_hw.h b/XilinxProcessorIPLib/drivers/dp/src/xdp_hw.h index ab9fb30b..89085b02 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdp_hw.h +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp_hw.h @@ -122,14 +122,14 @@ #define XDP_TX_USER_FIFO_OVERFLOW 0x110 /**< Indicates an overflow in user FIFO. */ #define XDP_TX_INTERRUPT_SIG_STATE 0x130 /**< The raw signal values for - interupt events. */ + interrupt events. */ #define XDP_TX_AUX_REPLY_DATA 0x134 /**< Reply data received during the AUX reply. */ #define XDP_TX_AUX_REPLY_CODE 0x138 /**< Reply code received from the most recent AUX command. */ #define XDP_TX_AUX_REPLY_COUNT 0x13C /**< Number of reply - transactions receieved + transactions received over AUX. */ #define XDP_TX_INTERRUPT_STATUS 0x140 /**< Status for interrupt events. */ @@ -265,7 +265,7 @@ #define XDP_TX_PHY_POSTCURSOR_LANE_3 0x258 /**< Controls the post-cursor level. */ #define XDP_TX_PHY_STATUS 0x280 /**< Current PHY status. */ -#define XDP_TX_GT_DRP_COMMAND 0x2A0 /**< Provides acces to the GT +#define XDP_TX_GT_DRP_COMMAND 0x2A0 /**< Provides access to the GT DRP ports. */ #define XDP_TX_GT_DRP_READ_DATA 0x2A4 /**< Provides access to GT DRP read data. */ @@ -1292,7 +1292,7 @@ updated internally. */ #define XDP_RX_MISC_CTRL_LONG_I2C_USE_DEFER_MASK \ 0x2 /**< When set, the long I2C - write data transfwers + write data transfers are responded to using DEFER instead of partial ACKs. */ @@ -1749,7 +1749,7 @@ 0x40000000 /**< Configure RX_PHY_POLARITY for lane 3. */ #define XDP_RX_PHY_CONFIG_GT_ALL_RESET_MASK \ - 0x00000003 /**< Rest GT and PHY. */ + 0x00000003 /**< Reset GT and PHY. */ /* 0x208: PHY_STATUS */ #define XDP_RX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK \ 0x00000003 /**< Reset done for lanes @@ -1792,17 +1792,17 @@ 0x00008000 /**< RX voltage low on lane 3. */ #define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_0_MASK \ - 0x00010000 /**< Lane aligment status for - lane 0. */ + 0x00010000 /**< Lane alignment status + for lane 0. */ #define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_1_MASK \ - 0x00020000 /**< Lane aligment status for - lane 1. */ + 0x00020000 /**< Lane alignment status + for lane 1. */ #define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_2_MASK \ - 0x00040000 /**< Lane aligment status for - lane 2. */ + 0x00040000 /**< Lane alignment status + for lane 2. */ #define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_3_MASK \ - 0x00080000 /**< Lane aligment status for - lane 3. */ + 0x00080000 /**< Lane alignment status + for lane 3. */ #define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_0_MASK \ 0x00100000 /**< Symbol lock status for lane 0. */ diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdp_mst.c b/XilinxProcessorIPLib/drivers/dp/src/xdp_mst.c index ba0f99ef..88e3627f 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdp_mst.c +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp_mst.c @@ -94,7 +94,7 @@ typedef struct message in the transaction. */ u8 EndOfMsgTransaction; /**< This message is the last sideband message in the transaction. */ - u8 MsgSequenceNum; /**< Identifies invidiual message + u8 MsgSequenceNum; /**< Identifies individual message transactions to a given DisplayPort device. */ u8 Crc; /**< The cyclic-redundancy check (CRC) @@ -2892,7 +2892,7 @@ static u32 XDp_RxSetRemoteIicReadReply(XDp *InstancePtr, XDp_SidebandMsg *Msg) /******************************************************************************/ /** * This function will set and format a sideband message structure for replying - * with a NAK + * with a NACK. * * @param Msg is a pointer to the message to be formatted. * diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdp_spm.c b/XilinxProcessorIPLib/drivers/dp/src/xdp_spm.c index a898dfc1..a689cb9c 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdp_spm.c +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp_spm.c @@ -886,7 +886,7 @@ static void XDp_TxCalculateTs(XDp *InstancePtr, u8 Stream, u8 BitsPerPixel) ((double)BitsPerPixel / 8); LinkBw = (LinkConfig->LaneCount * LinkConfig->LinkRate * 27); - /* Calculate the payload bandiwdth number (PBN). */ + /* Calculate the payload bandwidth number (PBN). */ InstancePtr->TxInstance.MstStreamConfig[Stream - 1].MstPbn = 1.006 * PeakPixelBw * ((double)64 / 54); /* Ceil - round up if required, avoiding overhead of math.h. */