diff --git a/XilinxProcessorIPLib/drivers/vphy/data/vphy.tcl b/XilinxProcessorIPLib/drivers/vphy/data/vphy.tcl
index 349ddd50..cd8b2422 100755
--- a/XilinxProcessorIPLib/drivers/vphy/data/vphy.tcl
+++ b/XilinxProcessorIPLib/drivers/vphy/data/vphy.tcl
@@ -31,9 +31,9 @@
 ##*****************************************************************************/
 
 proc generate {drv_handle} {
-    xdefine_include_file $drv_handle "xparameters.h" "XVPHY" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "Transceiver" "C_Tx_No_Of_Channels" "C_Rx_No_Of_Channels" "C_Tx_Protocol" "C_Rx_Protocol" "C_TX_REFCLK_SEL" "C_RX_REFCLK_SEL" "C_TX_PLL_SELECTION" "C_RX_PLL_SELECTION" "C_NIDRU" "C_NIDRU_REFCLK_SEL"
-    ::hsi::utils::define_config_file $drv_handle "xvphy_g.c" "XVphy" "DEVICE_ID" "C_BASEADDR" "TRANSCEIVER" "C_Tx_No_Of_Channels" "C_Rx_No_Of_Channels" "C_Tx_Protocol" "C_Rx_Protocol" "C_TX_REFCLK_SEL" "C_RX_REFCLK_SEL" "C_TX_PLL_SELECTION" "C_RX_PLL_SELECTION" "C_NIDRU" "C_NIDRU_REFCLK_SEL"
-    xdefine_canonical_xpars $drv_handle "xparameters.h" "VPHY" "DEVICE_ID" "C_BASEADDR" "Transceiver" "C_Tx_No_Of_Channels" "C_Rx_No_Of_Channels" "C_Tx_Protocol" "C_Rx_Protocol" "C_TX_REFCLK_SEL" "C_RX_REFCLK_SEL" "C_TX_PLL_SELECTION" "C_RX_PLL_SELECTION" "C_NIDRU" "C_NIDRU_REFCLK_SEL"
+    xdefine_include_file $drv_handle "xparameters.h" "XVPHY" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "Transceiver" "C_Tx_No_Of_Channels" "C_Rx_No_Of_Channels" "C_Tx_Protocol" "C_Rx_Protocol" "C_TX_REFCLK_SEL" "C_RX_REFCLK_SEL" "C_TX_PLL_SELECTION" "C_RX_PLL_SELECTION" "C_NIDRU" "C_NIDRU_REFCLK_SEL" "C_INPUT_PIXELS_PER_CLOCK"
+    ::hsi::utils::define_config_file $drv_handle "xvphy_g.c" "XVphy" "DEVICE_ID" "C_BASEADDR" "TRANSCEIVER" "C_Tx_No_Of_Channels" "C_Rx_No_Of_Channels" "C_Tx_Protocol" "C_Rx_Protocol" "C_TX_REFCLK_SEL" "C_RX_REFCLK_SEL" "C_TX_PLL_SELECTION" "C_RX_PLL_SELECTION" "C_NIDRU" "C_NIDRU_REFCLK_SEL" "C_INPUT_PIXELS_PER_CLOCK"
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "VPHY" "DEVICE_ID" "C_BASEADDR" "Transceiver" "C_Tx_No_Of_Channels" "C_Rx_No_Of_Channels" "C_Tx_Protocol" "C_Rx_Protocol" "C_TX_REFCLK_SEL" "C_RX_REFCLK_SEL" "C_TX_PLL_SELECTION" "C_RX_PLL_SELECTION" "C_NIDRU" "C_NIDRU_REFCLK_SEL" "C_INPUT_PIXELS_PER_CLOCK"
 }
 
 #
diff --git a/XilinxProcessorIPLib/drivers/vphy/src/xvphy.h b/XilinxProcessorIPLib/drivers/vphy/src/xvphy.h
index 73b766f1d..f4ac5084 100644
--- a/XilinxProcessorIPLib/drivers/vphy/src/xvphy.h
+++ b/XilinxProcessorIPLib/drivers/vphy/src/xvphy.h
@@ -508,6 +508,8 @@ typedef struct {
 	u8 DruIsPresent;		/**< A data recovery unit (DRU) exists
 						in the design .*/
 	XVphy_PllRefClkSelType DruRefClkSel; /**< DRU REFCLK selection. */
+	XVidC_PixelsPerClock Ppc;	/**< Number of input pixels per
+						 clock. */
 } XVphy_Config;
 
 /* Forward declaration. */
diff --git a/XilinxProcessorIPLib/drivers/vphy/src/xvphy_g.c b/XilinxProcessorIPLib/drivers/vphy/src/xvphy_g.c
index 7192a467..3af04334 100644
--- a/XilinxProcessorIPLib/drivers/vphy/src/xvphy_g.c
+++ b/XilinxProcessorIPLib/drivers/vphy/src/xvphy_g.c
@@ -59,6 +59,7 @@ XVphy_Config XVphy_ConfigTable[] =
 		XPAR_VID_PHY_CONTROLLER_0_TX_PLL_SELECTION,
 		XPAR_VID_PHY_CONTROLLER_0_RX_PLL_SELECTION,
 		XPAR_VID_PHY_CONTROLLER_0_NIDRU,
-		XPAR_VID_PHY_CONTROLLER_0_NIDRU_REFCLK_SEL
+		XPAR_VID_PHY_CONTROLLER_0_NIDRU_REFCLK_SEL,
+		XPAR_VID_PHY_CONTROLLER_0_INPUT_PIXELS_PER_CLOCK
 	}
 };