diff --git a/XilinxProcessorIPLib/drivers/zdma/data/zdma.mdd b/XilinxProcessorIPLib/drivers/zdma/data/zdma.mdd
new file mode 100755
index 00000000..417b62c2
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/zdma/data/zdma.mdd
@@ -0,0 +1,42 @@
+###############################################################################
+#
+# Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+OPTION psf_version = 2.1;
+
+BEGIN driver zdma
+
+ OPTION supported_peripherals = (psu_zdma);
+ OPTION driver_state = ACTIVE;
+ OPTION copyfiles = all;
+ OPTION VERSION = 1.0;
+ OPTION NAME = zdma;
+
+END driver
diff --git a/XilinxProcessorIPLib/drivers/zdma/data/zdma.tcl b/XilinxProcessorIPLib/drivers/zdma/data/zdma.tcl
new file mode 100755
index 00000000..b7357113
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/zdma/data/zdma.tcl
@@ -0,0 +1,51 @@
+###############################################################################
+#
+# Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+##############################################################################
+#
+# Modification History
+#
+# Ver Who Date Changes
+# ----- ---- -------- -----------------------------------------------
+# 1.0 vnsld 2/24/15 First release
+#
+##############################################################################
+
+#uses "xillib.tcl"
+
+proc generate {drv_handle} {
+ ::hsi::utils::define_zynq_include_file $drv_handle "xparameters.h" "XZDma" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_DMA_MODE" "C_S_AXI_HIGHADDR" "C_ZDMA_CLK_FREQ_HZ"
+
+ ::hsi::utils::define_zynq_config_file $drv_handle "xzdma_g.c" "XZDma" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_DMA_MODE"
+
+ ::hsi::utils::define_zynq_canonical_xpars $drv_handle "xparameters.h" "XZDma" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_DMA_MODE" "C_S_AXI_HIGHADDR" "C_ZDMA_CLK_FREQ_HZ"
+
+}
diff --git a/XilinxProcessorIPLib/drivers/zdma/src/Makefile b/XilinxProcessorIPLib/drivers/zdma/src/Makefile
new file mode 100644
index 00000000..9cd37252
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/zdma/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner zdma_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling zdma"
+
+zdma_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: zdma_includes
+
+zdma_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/XilinxProcessorIPLib/drivers/zdma/src/xzdma.c b/XilinxProcessorIPLib/drivers/zdma/src/xzdma.c
new file mode 100644
index 00000000..23ea3c08
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/zdma/src/xzdma.c
@@ -0,0 +1,1267 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma.c
+*
+* This file contains the implementation of the interface functions for ZDMA
+* driver. Refer to the header file xzdma.h for more detailed information.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ------------------------------------------------------
+* 1.0 vns 2/27/15 First release
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xzdma.h"
+
+/************************** Function Prototypes ******************************/
+
+static void StubCallBack(void *CallBackRef, u32 Mask);
+static void StubDoneCallBack(void *CallBackRef);
+static void XZDma_SimpleMode(XZDma *InstancePtr, XZDma_Transfer *Data);
+static void XZDma_ScatterGather(XZDma *InstancePtr, XZDma_Transfer *Data,
+ u32 Num);
+static void XZDma_LinearMode(XZDma *InstancePtr, XZDma_Transfer *Data,
+ XZDma_LiDscr *SrcDscrPtr,XZDma_LiDscr *DstDscrPtr, u8 IsLast);
+static void XZDma_ConfigLinear(XZDma_LiDscr *DscrPtr, u64 Addr, u32 Size,
+ u32 CtrlValue);
+static void XZDma_LinkedListMode(XZDma *InstancePtr, XZDma_Transfer *Data,
+ XZDma_LlDscr *SrcDscrPtr,XZDma_LlDscr *DstDscrPtr, u8 IsLast);
+static void XZDma_ConfigLinkedList(XZDma_LlDscr *DscrPtr, u64 Addr, u32 Size,
+ u32 CtrlValue, u64 NextDscrAddr);
+static void XZDma_Enable(XZDma *InstancePtr);
+static void XZDma_GetConfigurations(XZDma *InstancePtr);
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function initializes an ZDMA core. This function must be called
+* prior to using an ZDMA core. Initialization of an ZDMA includes setting
+* up the instance data and ensuring the hardware is in a quiescent state and
+* resets all the hardware configurations.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param CfgPtr is a reference to a structure containing information
+* about a specific XZDma instance.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the
+* address mapping from EffectiveAddr to the device physical
+* base address unchanged once this function is invoked.
+* Unexpected errors may occur if the address mapping changes
+* after this function is called. If address translation is not
+* used, pass in the physical address instead.
+*
+* @return
+* - XST_SUCCESS if initialization was successful.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XZDma_CfgInitialize(XZDma *InstancePtr, XZDma_Config *CfgPtr,
+ u32 EffectiveAddr)
+{
+
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(CfgPtr != NULL);
+ Xil_AssertNonvoid(EffectiveAddr != ((u32)0x00));
+
+ InstancePtr->Config.BaseAddress = CfgPtr->BaseAddress;
+ InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+ InstancePtr->Config.DmaType = CfgPtr->DmaType;
+
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+ InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY);
+
+ InstancePtr->IsSgDma = FALSE;
+ InstancePtr->Mode = XZDMA_NORMAL_MODE;
+ InstancePtr->IntrMask = 0x00U;
+ InstancePtr->ChannelState = XZDMA_IDLE;
+
+ /*
+ * Set all handlers to stub values, let user configure this
+ * data later
+ */
+ InstancePtr->DoneHandler =
+ (XZDma_DoneHandler)((void *)StubDoneCallBack);
+ InstancePtr->ErrorHandler =
+ (XZDma_ErrorHandler)((void *)StubCallBack);
+
+ XZDma_Reset(InstancePtr);
+ XZDma_GetConfigurations(InstancePtr);
+
+ return (XST_SUCCESS);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the pointer type and mode in which ZDMA needs to transfer
+* the data.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param IsSgDma is a variable which specifies whether transfer has to
+* to be done in scatter gather mode or simple mode.
+* - TRUE - Scatter gather pointer type
+* - FALSE - Simple pointer type
+* @param Mode is the type of the mode in which data has to be initiated
+* - XZDMA_NORMAL_MODE - Normal data transfer from source to
+* destination (Valid for both Scatter
+* gather and simple types)
+* - XZDMA_WRONLY_MODE - Write only mode (Valid only for Simple)
+* - XZDMA_RDONLY_MODE - Read only mode (Valid only for Simple)
+*
+* @return
+* - XST_SUCCESS - If mode has been set successfully.
+* - XST_FAILURE - If mode has not been set.
+*
+* @note Mode cannot be changed while ZDMA is not in IDLE state.
+*
+******************************************************************************/
+s32 XZDma_SetMode(XZDma *InstancePtr, u8 IsSgDma, XZDma_Mode Mode)
+{
+ u32 Data;
+ s32 Status;
+
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid((IsSgDma == TRUE) || (IsSgDma == FALSE));
+ Xil_AssertNonvoid(Mode <= XZDMA_RDONLY_MODE);
+
+ if (InstancePtr->ChannelState != XZDMA_IDLE) {
+ Status = XST_FAILURE;
+ }
+ else {
+ Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_CTRL0_OFFSET);
+ /* Simple mode */
+ if (IsSgDma != TRUE) {
+ Data = (Data & (~XZDMA_CTRL0_POINT_TYPE_MASK));
+ if (Mode == XZDMA_NORMAL_MODE) {
+ Data &= (~XZDMA_CTRL0_MODE_MASK);
+ }
+ else if (Mode == XZDMA_WRONLY_MODE) {
+ Data |= XZDMA_CTRL0_WRONLY_MASK;
+ }
+ else {
+ Data |= XZDMA_CTRL0_RDONLY_MASK;
+ }
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_CTRL0_OFFSET, Data);
+ InstancePtr->IsSgDma = FALSE;
+ InstancePtr->Mode = Mode;
+ }
+
+ else {
+ if (Mode != XZDMA_NORMAL_MODE) {
+ Status = XST_FAILURE;
+ }
+ else {
+ Data |= (XZDMA_CTRL0_POINT_TYPE_MASK);
+ Data &= ~(XZDMA_CTRL0_MODE_MASK);
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_CTRL0_OFFSET, Data);
+
+ InstancePtr->IsSgDma = TRUE;
+ InstancePtr->Mode = Mode;
+ }
+ }
+ Status = XST_SUCCESS;
+ }
+
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the descriptor type and descriptor pointer's start address
+* of both source and destination based on the memory allocated by user and also
+* calculates no of descriptors(BDs) can be created in the allocated memory.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param TypeOfDscr is a variable which specifies descriptor type
+* whether Linear or linked list type of descriptor.
+* - XZDMA_LINEAR - Linear type of descriptor.
+* - XZDMA_LINKEDLIST- Linked list type of descriptor.
+* @param Dscr_MemPtr is a pointer to the allocated memory for creating
+* descriptors. It Should be aligned to 64 bytes.
+*
+* @param NoOfBytes specifies the number of bytes allocated for
+* descriptors
+*
+* @return The Count of the descriptors can be created.
+*
+* @note User should allocate the memory for descriptors which should
+* be capable of how many transfers he wish to do in one start.
+* For Linear mode each descriptor needs 128 bit memory so for
+* one data transfer it requires 2*128 = 256 bits i.e. 32 bytes
+* Similarly for Linked list mode for each descriptor it needs
+* 256 bit, so for one data transfer it require 2*256 = 512 bits
+* i.e. 64 bytes.
+*
+******************************************************************************/
+u32 XZDma_CreateBDList(XZDma *InstancePtr, XZDma_DscrType TypeOfDscr,
+ UINTPTR Dscr_MemPtr, u32 NoOfBytes)
+{
+ XZDma_LiDscr *LocalLinearPtr = (XZDma_LiDscr *)(void *)Dscr_MemPtr;
+ XZDma_LlDscr *LocalLinklistPtr = (XZDma_LlDscr *)(void *)Dscr_MemPtr;
+
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid((TypeOfDscr == XZDMA_LINEAR) ||
+ (TypeOfDscr == XZDMA_LINKEDLIST));
+ Xil_AssertNonvoid(Dscr_MemPtr != 0x00);
+ Xil_AssertNonvoid(NoOfBytes != 0x00U);
+
+ InstancePtr->Descriptor.DscrType = TypeOfDscr;
+
+ if (TypeOfDscr == XZDMA_LINEAR) {
+ InstancePtr->Descriptor.SrcDscrPtr = (void *)Dscr_MemPtr;
+ LocalLinearPtr = ((LocalLinearPtr + (NoOfBytes >> 1)) + 1U);
+ InstancePtr->Descriptor.DstDscrPtr = (void *)LocalLinearPtr;
+ InstancePtr->Descriptor.DscrCount =
+ (NoOfBytes >> 1) / sizeof(XZDma_LiDscr);
+ }
+ else {
+ InstancePtr->Descriptor.SrcDscrPtr = (void *)Dscr_MemPtr;
+ LocalLinklistPtr =
+ ((LocalLinklistPtr + (NoOfBytes >> 1)) + 1U);
+ InstancePtr->Descriptor.DstDscrPtr = (void *)LocalLinklistPtr;
+ InstancePtr->Descriptor.DscrCount =
+ (NoOfBytes >> 1) / sizeof(XZDma_LlDscr);
+ }
+
+ Xil_DCacheInvalidateRange((INTPTR)Dscr_MemPtr, NoOfBytes);
+
+ return (InstancePtr->Descriptor.DscrCount);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the data attributes and control configurations of a
+* ZDMA core based on the inputs provided.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param Configure is a pointer to the XZDma_ChDataConfig structure
+* which has all the configuration fields.
+* The fields of the structure are:
+* - OverFetch - Allows over fetch or not
+* - 0 - Not allowed to over-fetch on SRC
+* - 1 - Allowed to over-fetch on SRC
+* - SrcIssue - Outstanding transaction on SRC
+* - Range is 1 to 32
+* - SrcBurstType - Burst Type for SRC AXI transaction
+* - XZDMA_FIXED_BURST - Fixed burst
+* - XZDMA_INCR_BURST - Incremental burst
+* - SrcBurstLen - AXI Length for Data Read.
+* - Range of values is (1,2,4,8,16).
+* - DstBurstType - Burst Type for SRC AXI transaction
+* - XZDMA_FIXED_BURST - Fixed burst
+* - XZDMA_INCR_BURST - Incremental burst
+* - DstBurstLen - AXI Length for Data write.
+* - Range of values is (1,2,4,8,16).
+* - SrcCache - AXI cache bits for Data read
+* - SrcQos - Configurable QoS bits for AXI Data read
+* - DstCache - AXI cache bits for Data write
+* - DstQos - configurable QoS bits for AXI Data write
+*
+* @return
+* - XST_FAILURE If ZDMA Core is not in Idle state and
+* - XST_SUCCESS If Configurations are made successfully
+*
+* @note
+* - These configurations will last till we modify or Reset
+* by XZDma_Reset(XZDma *InstancePtr).
+* - Configurations should be modified only when ZDMA channel
+* is IDLE this can be confirmed by using
+* XZDma_ChannelState(XZDma *InstancePtr) API.
+*
+******************************************************************************/
+s32 XZDma_SetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure)
+{
+ u32 Data;
+ s32 Status;
+
+ /* Verify arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Configure != NULL);
+
+ if (InstancePtr->ChannelState != XZDMA_IDLE) {
+ Status = XST_FAILURE;
+ }
+ else {
+ InstancePtr->DataConfig.DstBurstType = Configure->DstBurstType;
+ InstancePtr->DataConfig.DstBurstLen = Configure->DstBurstLen;
+ InstancePtr->DataConfig.SrcBurstType = Configure->SrcBurstType;
+ InstancePtr->DataConfig.SrcBurstLen = Configure->SrcBurstLen;
+ InstancePtr->DataConfig.OverFetch = Configure->OverFetch;
+ InstancePtr->DataConfig.SrcIssue = Configure->SrcIssue;
+ InstancePtr->DataConfig.SrcCache = Configure->SrcCache;
+ InstancePtr->DataConfig.SrcQos = Configure->SrcQos;
+ InstancePtr->DataConfig.DstCache = Configure->DstCache;
+ InstancePtr->DataConfig.DstQos = Configure->DstQos;
+
+ /* Setting over fetch */
+ Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_CTRL0_OFFSET);
+
+ Data |= (((u32)(Configure->OverFetch) <<
+ XZDMA_CTRL0_OVR_FETCH_SHIFT) &
+ XZDMA_CTRL0_OVR_FETCH_MASK);
+
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_CTRL0_OFFSET, Data);
+
+ /* Setting source issue */
+ Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_CTRL1_OFFSET);
+ Data = (u32)(Configure->SrcIssue & XZDMA_CTRL1_SRC_ISSUE_MASK);
+
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_CTRL1_OFFSET, Data);
+
+ /* Setting Burst length and burst type */
+ Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_DATA_ATTR_OFFSET);
+ Data = (Data & (~(XZDMA_DATA_ATTR_ARBURST_MASK |
+ XZDMA_DATA_ATTR_ARLEN_MASK |
+ XZDMA_DATA_ATTR_AWBURST_MASK |
+ XZDMA_DATA_ATTR_AWLEN_MASK |
+ XZDMA_DATA_ATTR_ARCACHE_MASK |
+ XZDMA_DATA_ATTR_AWCACHE_MASK |
+ XZDMA_DATA_ATTR_AWQOS_MASK |
+ XZDMA_DATA_ATTR_ARQOS_MASK)));
+
+ Data |= ((((u32)(Configure->SrcBurstType) <<
+ XZDMA_DATA_ATTR_ARBURST_SHIFT) &
+ XZDMA_DATA_ATTR_ARBURST_MASK) |
+ (((u32)(Configure->SrcCache) <<
+ XZDMA_DATA_ATTR_ARCACHE_SHIFT) &
+ XZDMA_DATA_ATTR_ARCACHE_MASK) |
+ (((u32)(Configure->SrcQos) <<
+ XZDMA_DATA_ATTR_ARQOS_SHIFT) &
+ XZDMA_DATA_ATTR_ARQOS_MASK) |
+ (((u32)(Configure->SrcBurstLen) <<
+ XZDMA_DATA_ATTR_ARLEN_SHIFT) &
+ XZDMA_DATA_ATTR_ARLEN_MASK) |
+ (((u32)(Configure->DstBurstType) <<
+ XZDMA_DATA_ATTR_AWBURST_SHIFT) &
+ XZDMA_DATA_ATTR_AWBURST_MASK) |
+ (((u32)(Configure->DstCache) <<
+ XZDMA_DATA_ATTR_AWCACHE_SHIFT) &
+ XZDMA_DATA_ATTR_AWCACHE_MASK) |
+ (((u32)(Configure->DstQos) <<
+ XZDMA_DATA_ATTR_AWQOS_SHIFT) &
+ XZDMA_DATA_ATTR_AWQOS_MASK) |
+ (((u32)(Configure->DstBurstLen)) &
+ XZDMA_DATA_ATTR_AWLEN_MASK));
+
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_DATA_ATTR_OFFSET, Data);
+ Status = XST_SUCCESS;
+ }
+
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the data attributes and control configurations of a
+* ZDMA core.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param Configure is a pointer to the XZDma_ChDataConfig structure
+* which has all the configuration fields.
+* The fields of the structure are:
+* - OverFetch - Allows over fetch or not
+* - 0 - Not allowed to over-fetch on SRC
+* - 1 - Allowed to over-fetch on SRC
+* - SrcIssue - Outstanding transaction on SRC
+* - Range is 1 to 32
+* - SrcBurstType - Burst Type for SRC AXI transaction
+* - XZDMA_FIXED_BURST - Fixed burst
+* - XZDMA_INCR_BURST - Incremental burst
+* - SrcBurstLen - AXI Length for Data Read.
+* - Can be max of 16 to be compatible with AXI3
+* - DstBurstType - Burst Type for SRC AXI transaction
+* - XZDMA_FIXED_BURST - Fixed burst
+* - XZDMA_INCR_BURST - Incremental burst
+* - DstBurstLen - AXI Length for Data write.
+* - Can be max of 16 to be compatible with AXI3
+* - SrcCache - AXI cache bits for Data read
+* - SrcQos - Configurable QoS bits for AXI Data read
+* - DstCache - AXI cache bits for Data write
+* - DstQos - Configurable QoS bits for AXI Data write
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XZDma_GetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure)
+{
+
+ /* Verify arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Configure != NULL);
+
+ Configure->SrcBurstType = InstancePtr->DataConfig.SrcBurstType;
+ Configure->SrcCache = InstancePtr->DataConfig.SrcCache;
+ Configure->SrcQos = InstancePtr->DataConfig.SrcQos;
+ Configure->SrcBurstLen = InstancePtr->DataConfig.SrcBurstLen;
+
+ Configure->DstBurstType = InstancePtr->DataConfig.DstBurstType;
+ Configure->DstCache = InstancePtr->DataConfig.DstCache;
+ Configure->DstQos = InstancePtr->DataConfig.DstQos;
+ Configure->DstBurstLen = InstancePtr->DataConfig.DstBurstLen;
+
+ Configure->OverFetch = InstancePtr->DataConfig.OverFetch;
+ Configure->SrcIssue = InstancePtr->DataConfig.SrcIssue;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the descriptor attributes based on the inputs provided
+* in the structure.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param Configure is a pointer to the XZDma_ChDscrConfig structure
+* which has all the configuration fields.
+* The fields of the structure are:
+* - AxCoherent - AXI transactions generated for the descriptor.
+* - 0 - Non coherent
+* - 1 - Coherent
+* - AXCache - AXI cache bit used for DSCR fetch
+* (both on SRC and DST Side)
+* - AXQos - QoS bit used for DSCR fetch
+* (both on SRC and DST Side)
+*
+* @return
+* - XST_FAILURE If ZDMA core is not in Idle state and
+* - XST_SUCCESS If Configurations are made successfully
+*
+* @note None.
+*
+******************************************************************************/
+s32 XZDma_SetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure)
+{
+ u32 Data;
+ s32 Status;
+
+ /* Verify arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Configure != NULL);
+
+ if (InstancePtr->ChannelState != XZDMA_IDLE) {
+ Status = XST_FAILURE;
+ }
+
+ else {
+ InstancePtr->DscrConfig.AXCache = Configure->AXCache;
+ InstancePtr->DscrConfig.AXQos = Configure->AXQos;
+ InstancePtr->DscrConfig.AxCoherent = Configure->AxCoherent;
+
+ Data = ((((u32)(Configure->AxCoherent) <<
+ XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT) &
+ XZDMA_DSCR_ATTR_AXCOHRNT_MASK) |
+ (((u32)(Configure->AXCache) <<
+ XZDMA_DSCR_ATTR_AXCACHE_SHIFT) &
+ XZDMA_DSCR_ATTR_AXCACHE_MASK) |
+ (((u32)Configure->AXQos) &
+ XZDMA_DSCR_ATTR_AXQOS_MASK));
+
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_DSCR_ATTR_OFFSET, Data);
+
+ Status = XST_SUCCESS;
+ }
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the descriptor attributes of the channel.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param Configure is a pointer to the XZDma_ChDscrConfig structure
+* which has all the configuration fields.
+* The fields of the structure are:
+* - AxCoherent - AXI transactions generated for the descriptor.
+* - 0 - Non coherent
+* - 1 - Coherent
+* - AXCache - AXI cache bit used for DSCR fetch
+* (both on SRC and DST Side)
+* - AXQos - QoS bit used for DSCR fetch
+* (both on SRC and DST Side)
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XZDma_GetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure)
+{
+
+ /* Verify arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Configure != NULL);
+
+ Configure->AXCache = InstancePtr->DscrConfig.AXCache;
+ Configure->AXQos = InstancePtr->DscrConfig.AXQos;
+ Configure->AxCoherent = InstancePtr->DscrConfig.AxCoherent;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function preloads the buffers which will be used in write only mode.
+* In write only mode the data in the provided buffer will be written in
+* destination address for specified size.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param Buffer is a pointer to an array of 64/128 bit data.
+* i.e. pointer to 32 bit array of size 2/4
+* - Array of Size 2 for ADMA
+* - Array of Size 4 for GDMA
+*
+* @return None.
+*
+* @note Valid only in simple mode.
+* Prior to call this function ZDMA instance should be set in
+* Write only mode by using
+* XZDma_SetMode(XZDma *InstancePtr, u8 IsSgDma,
+* XZDma_Mode Mode)
+* To initiate data transfer after this API need to call
+* XZDma_Start(XZDma *InstancePtr, XZDma_Transfer *Data, u32 Num)
+* In which only destination fields has to be filled.
+*
+******************************************************************************/
+void XZDma_WOData(XZDma *InstancePtr, u32 *Buffer)
+{
+ u32 *LocBuf = Buffer;
+
+ /* Verify arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Buffer != NULL);
+
+ if (InstancePtr->Config.DmaType == (u8)0) {
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_WR_ONLY_WORD0_OFFSET, *LocBuf);
+ LocBuf++;
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_WR_ONLY_WORD1_OFFSET, *LocBuf);
+ LocBuf++;
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_WR_ONLY_WORD2_OFFSET, *LocBuf);
+ LocBuf++;
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_WR_ONLY_WORD3_OFFSET, *LocBuf);
+ }
+
+ else {
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_WR_ONLY_WORD0_OFFSET, *LocBuf);
+ LocBuf++;
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_WR_ONLY_WORD1_OFFSET, *LocBuf);
+ }
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resume the paused state of ZDMA core and starts the transfer
+* from where it has paused.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return None.
+*
+* @note Valid only for scatter gather mode.
+*
+******************************************************************************/
+void XZDma_Resume(XZDma *InstancePtr)
+{
+ u32 Value;
+
+ /* Verify arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsSgDma == TRUE);
+ Xil_AssertVoid(InstancePtr->ChannelState == XZDMA_PAUSE);
+
+ Value = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_CTRL0_OFFSET) & (~XZDMA_CTRL0_CONT_ADDR_MASK);
+ Value |= XZDMA_CTRL0_CONT_MASK;
+ InstancePtr->ChannelState = XZDMA_BUSY;
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_CTRL0_OFFSET, Value);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resets the ZDMA core.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return None.
+*
+* @note This function resets all the configurations made previously.
+* Disables all the interrupts and clears interrupt status.
+*
+*****************************************************************************/
+void XZDma_Reset(XZDma *InstancePtr)
+{
+
+ /* Verify arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->ChannelState == XZDMA_IDLE);
+
+ /* Disable's the channel */
+ XZDma_DisableCh(InstancePtr);
+
+ /* Disables all interrupts */
+ XZDma_DisableIntr(InstancePtr, XZDMA_IXR_ALL_INTR_MASK);
+ XZDma_IntrClear(InstancePtr, XZDMA_IXR_ALL_INTR_MASK);
+ InstancePtr->IntrMask = 0x00U;
+
+ /* All configurations are being reset */
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL0_OFFSET,
+ XZDMA_CTRL0_RESET_VALUE);
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL1_OFFSET,
+ XZDMA_CTRL1_RESET_VALUE);
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_DATA_ATTR_OFFSET, XZDMA_DATA_ATTR_RESET_VALUE);
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_DSCR_ATTR_OFFSET, XZDMA_DSCR_ATTR_RESET_VALUE);
+
+ /* Clears total byte */
+ XZDma_TotalByteClear(InstancePtr);
+
+ /* Clears interrupt count of both source and destination channels */
+ (void)XZDma_GetSrcIntrCnt(InstancePtr);
+ (void)XZDma_GetDstIntrCnt(InstancePtr);
+
+ InstancePtr->ChannelState = XZDMA_IDLE;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the state of ZDMA core.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return This function returns state of ZDMA core
+* - XZDMA_IDLE - If ZDMA core is in idle state.
+* - XZDMA_PAUSE - If ZDMA is in paused state.
+* - XZDMA_BUSY - If ZDMA is in busy state.
+* @note None.
+* C-style signature:
+* XZDmaState XZDma_ChannelState(XZDma *InstancePtr)
+*
+******************************************************************************/
+XZDmaState XZDma_ChannelState(XZDma *InstancePtr)
+{
+ XZDmaState Status;
+ u32 Value;
+
+ /* Verify arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ Value = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+ (XZDMA_CH_STS_OFFSET)) & (XZDMA_STS_ALL_MASK);
+
+ if ((Value == XZDMA_STS_DONE_MASK) ||
+ (Value == XZDMA_STS_DONE_ERR_MASK)) {
+ Status = XZDMA_IDLE;
+ }
+ else if (Value == XZDMA_STS_PAUSE_MASK) {
+ Status = XZDMA_PAUSE;
+ }
+ else {
+ Status = XZDMA_BUSY;
+ }
+
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets all the required fields for initiating data transfer. Data
+* transfer elements needs to be passed through structure pointer.
+* Data transfer can be done in any of the three modes (simple, Linear or Linked
+* List) based on the selected mode but before calling this API make sure that
+* ZDMA is in Idle state.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param Data is a pointer of array to the XZDma_Transfer structure which
+* has all the configuration fields for initiating data transfer.
+* The fields of the structure are:
+* - SrcAddr - Source address
+* - DstAddr - Destination address
+* - Size - size of the data to be transferred in bytes
+* - SrcCoherent - AXI transactions generated to process the
+* descriptor payload for source channel
+* - 0 - Non coherent
+* - 1 - Coherent
+* - DstCoherent - AXI transactions generated to process the
+* descriptor payload for destination channel
+* - 0 - Non coherent
+* - 1 - Coherent
+* - Pause - Valid only for scatter gather mode.
+* Will pause after completion of this descriptor.
+* @param Num specifies number of array elements of Data pointer.
+* - For simple mode Num should be equal to 1
+* - For Scatter gather mode (either linear or linked list) Num
+* can be any choice. (But based on which memory should be
+* allocated by Application) It should be less than the return
+* value of XZDma_CreateBDList.
+*
+* @return
+* - XST_SUCCESS - if ZDMA initiated the transfer.
+* - XST_FAILURE - if ZDMA has not initiated data transfer.
+*
+* @note After Pause to resume the transfer need to use the following
+* API
+* - XZDma_Resume
+* User should provide allocated memory and descriptor type in
+* scatter gather mode through the following API before calling
+* the start API.
+* - XZDma_SetDescriptorType(XZDma *InstancePtr,
+* XZDma_DscrType TypeOfDscr, UINTPTR Dscr_MemPtr,
+* u32 NoOfBytes)
+*
+******************************************************************************/
+s32 XZDma_Start(XZDma *InstancePtr, XZDma_Transfer *Data, u32 Num)
+{
+ s32 Status;
+
+ /* Verify arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Data != NULL);
+ Xil_AssertNonvoid(Num != 0x00U);
+
+ if ((InstancePtr->ChannelState == XZDMA_BUSY) &&
+ (Num >= InstancePtr->Descriptor.DscrCount)) {
+ Status = XST_FAILURE;
+ }
+ else {
+ if (InstancePtr->IsSgDma != TRUE) {
+ XZDma_SimpleMode(InstancePtr, Data);
+ Status = XST_SUCCESS;
+ }
+ else {
+
+ XZDma_ScatterGather(InstancePtr, Data, Num);
+ Status = XST_SUCCESS;
+ }
+
+ XZDma_Enable(InstancePtr);
+ }
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in simple mode.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param Data is a pointer of array to the XZDma_Transfer structure
+* which has all the configuration fields for initiating data
+* transfer.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void XZDma_SimpleMode(XZDma *InstancePtr, XZDma_Transfer *Data)
+{
+
+ u32 Value;
+
+ /* Verify arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Data != NULL);
+
+ XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+ XZDMA_CH_SRC_DSCR_WORD0_OFFSET,
+ (Data->SrcAddr & XZDMA_WORD0_LSB_MASK));
+ XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+ XZDMA_CH_SRC_DSCR_WORD1_OFFSET,
+ (((u64)Data->SrcAddr >> XZDMA_WORD1_MSB_SHIFT) &
+ XZDMA_WORD1_MSB_MASK));
+
+ XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+ XZDMA_CH_DST_DSCR_WORD0_OFFSET,
+ (Data->DstAddr & XZDMA_WORD0_LSB_MASK));
+ XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+ XZDMA_CH_DST_DSCR_WORD1_OFFSET,
+ (((u64)Data->DstAddr >> XZDMA_WORD1_MSB_SHIFT) &
+ XZDMA_WORD1_MSB_MASK));
+
+ XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+ XZDMA_CH_SRC_DSCR_WORD2_OFFSET,
+ (Data->Size & XZDMA_WORD2_SIZE_MASK));
+ XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+ XZDMA_CH_DST_DSCR_WORD2_OFFSET,
+ (Data->Size & XZDMA_WORD2_SIZE_MASK));
+
+ Value = (u32)(Data->SrcCoherent & XZDMA_WORD3_COHRNT_MASK);
+ XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+ XZDMA_CH_SRC_DSCR_WORD3_OFFSET, Value);
+
+ Value = (u32)(Data->DstCoherent & XZDMA_WORD3_COHRNT_MASK);
+ XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+ XZDMA_CH_DST_DSCR_WORD3_OFFSET, Value);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in scatter gather mode.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param Data is a pointer of array to the XZDma_Transfer structure
+* which has all the configuration fields for initiating data
+* transfer.
+* @param Num specifies number of array elements of Data pointer.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void XZDma_ScatterGather(XZDma *InstancePtr, XZDma_Transfer *Data,
+ u32 Num)
+{
+ u32 Count = 0x00U;
+ u8 Last;
+ XZDma_Transfer *LocalData = Data;
+ XZDma_LiDscr *LiSrcDscr =
+ (XZDma_LiDscr *)(void *)(InstancePtr->Descriptor.SrcDscrPtr);
+ XZDma_LiDscr *LiDstDscr =
+ (XZDma_LiDscr *)(void *)(InstancePtr->Descriptor.DstDscrPtr);
+ XZDma_LlDscr *LlSrcDscr =
+ (XZDma_LlDscr *)(void *)(InstancePtr->Descriptor.SrcDscrPtr);
+ XZDma_LlDscr *LlDstDscr =
+ (XZDma_LlDscr *)(void *)(InstancePtr->Descriptor.DstDscrPtr);
+
+ /* Verify arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Data != NULL);
+ Xil_AssertVoid(Num != 0x00U);
+
+ if (InstancePtr->Descriptor.DscrType == XZDMA_LINEAR) {
+ Last = FALSE;
+ do {
+ if (Count == (Num- 1)) {
+ Last = TRUE;
+ }
+ XZDma_LinearMode(InstancePtr, LocalData, LiSrcDscr,
+ LiDstDscr, Last);
+ Count++;
+ LiSrcDscr++;
+ LiDstDscr++;
+ LocalData++;
+ } while(Count < Num);
+ }
+ else {
+ Last = FALSE;
+ do {
+ if (Count == (Num - 1)) {
+ Last = TRUE;
+ }
+ XZDma_LinkedListMode(InstancePtr, LocalData, LlSrcDscr,
+ LlDstDscr, Last);
+ Count++;
+ LlDstDscr++;
+ LlSrcDscr++;
+ LocalData++;
+ } while(Count < Num);
+ }
+
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_SRC_START_LSB_OFFSET,
+ ((UINTPTR)(InstancePtr->Descriptor.SrcDscrPtr) &
+ XZDMA_WORD0_LSB_MASK));
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_SRC_START_MSB_OFFSET,
+ (((u64)(UINTPTR)(InstancePtr->Descriptor.SrcDscrPtr) >>
+ XZDMA_WORD1_MSB_SHIFT) & XZDMA_WORD1_MSB_MASK));
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_DST_START_LSB_OFFSET,
+ ((UINTPTR)(InstancePtr->Descriptor.DstDscrPtr) &
+ XZDMA_WORD0_LSB_MASK));
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_DST_START_MSB_OFFSET,
+ (((u64)(UINTPTR)(InstancePtr->Descriptor.DstDscrPtr) >>
+ XZDMA_WORD1_MSB_SHIFT) & XZDMA_WORD1_MSB_MASK));
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in Linear descriptor type.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param Data is a pointer of array to the XZDma_Transfer structure which
+* has all the configuration fields for initiating data transfer.
+* @param SrcDscrPtr is descriptor pointer of source in which Data fields
+* has to be filled.
+* @param DstDscrPtr is descriptor pointer of destination in which Data
+* fields has to be filled.
+* @param IsLast specifies whether provided descriptor pointer is last
+* one or not.
+* - XZDMA_TRUE - If descriptor is last
+* - XZDMA_FALSE - If descriptor is not last
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void XZDma_LinearMode(XZDma *InstancePtr, XZDma_Transfer *Data,
+ XZDma_LiDscr *SrcDscrPtr, XZDma_LiDscr *DstDscrPtr, u8 IsLast)
+{
+ u32 Value;
+
+ /* Verify arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Data != NULL);
+ Xil_AssertVoid(SrcDscrPtr != NULL);
+ Xil_AssertVoid(DstDscrPtr != NULL);
+ Xil_AssertVoid((IsLast == TRUE) || (IsLast == FALSE));
+
+ if (Data->Pause == TRUE) {
+ Value = XZDMA_WORD3_CMD_PAUSE_MASK;
+ }
+ else if (IsLast == TRUE) {
+ Value = XZDMA_WORD3_CMD_STOP_MASK;
+ }
+ else {
+ Value = XZDMA_WORD3_CMD_NXTVALID_MASK;
+ }
+ if (Data->SrcCoherent == TRUE) {
+ Value |= XZDMA_WORD3_COHRNT_MASK;
+ }
+
+ XZDma_ConfigLinear(SrcDscrPtr, (u64)Data->SrcAddr, Data->Size, Value);
+
+ Value = 0U;
+
+ if (Data->DstCoherent == TRUE) {
+ Value |= XZDMA_WORD3_COHRNT_MASK;
+ }
+
+ XZDma_ConfigLinear(DstDscrPtr, (u64)Data->DstAddr, Data->Size, Value);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in Linear descriptor type.
+*
+* @param DscrPtr is a pointer to source/destination descriptor.
+* @param Addr is a 64 bit variable which denotes the address of data.
+* @param Size specifies the amount of the data to be transferred.
+* @param CtrlValue contains all the control fields of descriptor.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void XZDma_ConfigLinear(XZDma_LiDscr *DscrPtr, u64 Addr, u32 Size,
+ u32 CtrlValue)
+{
+ /* Verify arguments */
+ Xil_AssertVoid(DscrPtr != NULL);
+ Xil_AssertVoid(Addr != 0x00U);
+
+ DscrPtr->Address = Addr;
+ DscrPtr->Size = Size & XZDMA_WORD2_SIZE_MASK;
+ DscrPtr->Cntl = CtrlValue;
+
+ Xil_DCacheFlushRange((UINTPTR)DscrPtr, sizeof(XZDma_LlDscr));
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in Linked list descriptor type.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param Data is a pointer of array to the XZDma_Transfer structure which
+* has all the configuration fields for initiating data transfer.
+* @param SrcDscrPtr is descriptor pointer of source in which Data fields
+* has to be filled.
+* @param DstDscrPtr is descriptor pointer of destination in which Data
+* fields has to be filled.
+* @param IsLast specifies whether provided descriptor pointer is last
+* one or not.
+* - TRUE - If descriptor is last
+* - FALSE - If descriptor is not last
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void XZDma_LinkedListMode(XZDma *InstancePtr, XZDma_Transfer *Data,
+ XZDma_LlDscr *SrcDscrPtr,XZDma_LlDscr *DstDscrPtr, u8 IsLast)
+{
+ u32 Value;
+ XZDma_LlDscr *NextSrc = SrcDscrPtr;
+ XZDma_LlDscr *NextDst = DstDscrPtr;
+ u64 NextSrcAdrs = 0x00U;
+ u64 NextDstAdrs = 0x00U;
+
+ /* Verify arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Data != NULL);
+ Xil_AssertVoid(SrcDscrPtr != NULL);
+ Xil_AssertVoid(DstDscrPtr != NULL);
+ Xil_AssertVoid((IsLast == TRUE) || (IsLast == FALSE));
+
+ NextDst++;
+ NextSrc++;
+
+ if (Data->Pause == TRUE) {
+ Value = XZDMA_WORD3_CMD_PAUSE_MASK;
+ if (IsLast != TRUE) {
+ NextSrcAdrs = (u64)(UINTPTR)NextSrc;
+ NextDstAdrs = (u64)(UINTPTR)NextDst;
+ }
+ }
+ else if (IsLast == TRUE) {
+ Value = XZDMA_WORD3_CMD_STOP_MASK;
+ }
+ else {
+ Value = XZDMA_WORD3_CMD_NXTVALID_MASK;
+ NextSrcAdrs = (u64)(UINTPTR)NextSrc;
+ NextDstAdrs = (u64)(UINTPTR)NextDst;
+ }
+ if (Data->SrcCoherent == TRUE) {
+ Value |= XZDMA_WORD3_COHRNT_MASK;
+ }
+
+ XZDma_ConfigLinkedList(SrcDscrPtr, (u64)Data->SrcAddr,
+ Data->Size, Value, NextSrcAdrs);
+
+ Value = 0U;
+
+ if (Data->DstCoherent == TRUE) {
+ Value |= XZDMA_WORD3_COHRNT_MASK;
+ }
+
+ XZDma_ConfigLinkedList(DstDscrPtr, (u64)Data->DstAddr,
+ Data->Size, Value, NextDstAdrs);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in Linked list descriptor type.
+*
+* @param DscrPtr is a pointer to source/destination descriptor.
+* @param Addr is a 64 bit variable which denotes the address of data.
+* @param Size specifies the amount of the data to be transferred.
+* @param CtrlValue contains all the control fields of descriptor.
+* @param NextDscrAddr is the address of next descriptor.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void XZDma_ConfigLinkedList(XZDma_LlDscr *DscrPtr, u64 Addr, u32 Size,
+ u32 CtrlValue, u64 NextDscrAddr)
+{
+ /* Verify arguments */
+ Xil_AssertVoid(DscrPtr != NULL);
+ Xil_AssertVoid(Addr != 0x00U);
+
+ DscrPtr->Address = Addr;
+ DscrPtr->Size = Size & XZDMA_WORD2_SIZE_MASK;
+ DscrPtr->Cntl = CtrlValue;
+ DscrPtr->NextDscr = NextDscrAddr;
+ DscrPtr->Reserved = 0U;
+
+ Xil_DCacheFlushRange((UINTPTR)DscrPtr, sizeof(XZDma_LlDscr));
+}
+
+/*****************************************************************************/
+/**
+* This static function enable's all the interrupts which user intended to
+* enable and enables the ZDMA channel for initiating data transfer.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+
+static void XZDma_Enable(XZDma *InstancePtr)
+{
+ /* Verify arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_IEN_OFFSET,
+ (InstancePtr->IntrMask & XZDMA_IXR_ALL_INTR_MASK));
+ InstancePtr->ChannelState = XZDMA_BUSY;
+ XZDma_EnableCh(InstancePtr);
+
+}
+
+/*****************************************************************************/
+/**
+* This static function gets all the reset configurations of ZDMA.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void XZDma_GetConfigurations(XZDma *InstancePtr)
+{
+ /* Verify arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ InstancePtr->DataConfig.SrcIssue = (u8)XZDMA_CTRL1_SRC_ISSUE_MASK;
+ InstancePtr->DataConfig.SrcBurstType = XZDMA_INCR_BURST;
+ InstancePtr->DataConfig.SrcBurstLen = 0xFU;
+ InstancePtr->DataConfig.OverFetch = 1U;
+ InstancePtr->DataConfig.DstBurstType = XZDMA_INCR_BURST;
+ InstancePtr->DataConfig.DstBurstLen = 0xFU;
+ InstancePtr->DataConfig.SrcCache = 0x2U;
+ InstancePtr->DataConfig.DstCache = 0x2U;
+ InstancePtr->DataConfig.SrcQos = 0x0U;
+ InstancePtr->DataConfig.DstQos = 0x0U;
+
+ InstancePtr->DscrConfig.AXCache = 0U;
+ InstancePtr->DscrConfig.AXQos = 0U;
+ InstancePtr->DscrConfig.AxCoherent = 0U;
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine is a stub for the asynchronous callbacks. The stub is here in
+* case the upper layer forgot to set the handlers. On initialization, All
+* handlers are set to this callback. It is considered an error for this
+* handler to be invoked.
+*
+* @param CallBackRef is a callback reference passed in by the upper
+* layer when setting the callback functions, and passed back to
+* the upper layer when the callback is invoked.
+* @param Mask is the type of the interrupts to enable. Use OR'ing of
+* XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
+* this parameter value.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void StubCallBack(void *CallBackRef, u32 Mask)
+{
+ /* Verify arguments. */
+ Xil_AssertVoid(CallBackRef != NULL);
+ Xil_AssertVoid(Mask != (u32)0x00);
+ Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine is a stub for the DMA done callback. The stub is here in
+* case the upper layer forgot to set the handlers. On initialization, Done
+* handler are set to this callback.
+*
+* @param CallBackRef is a callback reference passed in by the upper
+* layer when setting the callback functions, and passed back to
+* the upper layer when the callback is invoked.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void StubDoneCallBack(void *CallBackRef)
+{
+ /* Verify arguments. */
+ Xil_AssertVoid(CallBackRef != NULL);
+ Xil_AssertVoidAlways();
+}
diff --git a/XilinxProcessorIPLib/drivers/zdma/src/xzdma.h b/XilinxProcessorIPLib/drivers/zdma/src/xzdma.h
new file mode 100644
index 00000000..0d0e6342
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/zdma/src/xzdma.h
@@ -0,0 +1,667 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* ZDMA is a general purpose DMA designed to support memory to memory and memory
+* to IO buffer transfers. ALTO has two instance of general purpose ZDMA.
+* One is located in FPD (full power domain) which is GDMA and other is located
+* in LPD (low power domain) which is ADMA.
+*
+* GMDA & ADMA are configured each with 8 DMA channels and and each channel can
+* be programmed secure or non-secure.
+* Each channel is divided into two functional sides, Source (Read) and
+* Destination (Write). Each DMA channel can be independently programmed
+* in one of following DMA modes.
+* - Simple DMA
+* - Normal data transfer from source to destination.
+* - Write Only mode.
+* - Read Only mode.
+* - Scatter Gather DMA
+* - Only Normal mode it can't support other two modes.
+* In Scatter gather descriptor can be of 3 types
+* - Linear descriptor.
+* - Linked list descriptor
+* - Hybrid descriptor (Combination of both Linear and Linked list)
+* Our driver will not support Hybrid type of descriptor.
+*
+* Initialization & Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the ZDMA core.
+*
+* XZDma_CfgInitialize() API is used to initialize the ZDMA core.
+* The user needs to first call the XZDma_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to the
+* XZDma_CfgInitialize() API.
+*
+* Interrupts
+* The driver provides an interrupt handler XZDma_IntrHandler for handling
+* the interrupt from the ZDMA core. The users of this driver have to
+* register this handler with the interrupt system and provide the callback
+* functions by using XZDma_SetCallBack API. In this version Descriptor done
+* option is disabled.
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XZDma driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* @file xzdma.h
+*
+* This header file contains identifiers and register-level driver functions (or
+* macros), range macros, structure typedefs that can be used to access the
+* Xilinx ZDMA core instance.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ------------------------------------------------------
+* 1.0 vns 2/27/15 First release
+*
+*
+******************************************************************************/
+#ifndef XZDMA_H_
+#define XZDMA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xzdma_hw.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_cache.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/** @name ZDMA Handler Types
+ * @{
+ */
+typedef enum {
+ XZDMA_HANDLER_DONE, /**< For Done Handler */
+ XZDMA_HANDLER_ERROR, /**< For Error Handler */
+} XZDma_Handler;
+/*@}*/
+
+/** @name ZDMA Descriptors Types
+ * @{
+ */
+typedef enum {
+ XZDMA_LINEAR, /**< Linear descriptor */
+ XZDMA_LINKEDLIST, /**< Linked list descriptor */
+} XZDma_DscrType;
+/*@}*/
+
+/** @name ZDMA Operation modes
+ * @{
+ */
+typedef enum {
+ XZDMA_NORMAL_MODE, /**< Normal transfer from source to
+ * destination*/
+ XZDMA_WRONLY_MODE, /**< Write only mode */
+ XZDMA_RDONLY_MODE /**< Read only mode */
+} XZDma_Mode;
+/*@}*/
+
+/** @name ZDMA state
+ * @{
+ */
+typedef enum {
+ XZDMA_IDLE, /**< ZDMA is in Idle state */
+ XZDMA_PAUSE, /**< Paused state */
+ XZDMA_BUSY, /**< Busy state */
+} XZDmaState;
+/*@}*/
+
+/** @name ZDMA AXI Burst type
+ * @{
+ */
+typedef enum {
+ XZDMA_FIXED_BURST = 0, /**< Fixed burst type */
+ XZDMA_INCR_BURST /**< Increment burst type */
+} XZDma_BurstType;
+/*@}*/
+
+/******************************************************************************/
+/**
+* This typedef contains scatter gather descriptor fields for ZDMA core.
+*/
+typedef struct {
+ void *SrcDscrPtr; /**< Source Descriptor pointer */
+ void *DstDscrPtr; /**< Destination Descriptor pointer */
+ u32 DscrCount; /**< Count of descriptors available */
+ XZDma_DscrType DscrType;/**< Type of descriptor either Linear or
+ * Linked list type */
+} XZDma_Descriptor;
+
+/******************************************************************************/
+/**
+* This typedef contains scatter gather descriptor fields for ZDMA core.
+*/
+typedef struct {
+ u64 Address; /**< Address */
+ u32 Size; /**< Word2, Size of data */
+ u32 Cntl; /**< Word3 Control data */
+ u64 NextDscr; /**< Address of next descriptor */
+ u64 Reserved; /**< Reserved address */
+} __attribute__ ((packed)) XZDma_LlDscr;
+
+/******************************************************************************/
+/**
+* This typedef contains Linear descriptor fields for ZDMA core.
+*/
+typedef struct {
+ u64 Address; /**< Address */
+ u32 Size; /**< Word3, Size of data */
+ u32 Cntl; /**< Word4, control data */
+} __attribute__ ((packed)) XZDma_LiDscr;
+
+/******************************************************************************/
+/**
+*
+* This typedef contains the data configurations of ZDMA core
+*/
+typedef struct {
+ u8 OverFetch; /**< Enable Over fetch */
+ u8 SrcIssue; /**< Outstanding transactions for Source */
+ XZDma_BurstType SrcBurstType;
+ /**< Burst type for SRC */
+ u8 SrcBurstLen; /**< AXI length for data read */
+ XZDma_BurstType DstBurstType;
+ /**< Burst type for DST */
+ u8 DstBurstLen; /**< AXI length for data write */
+ u8 SrcCache; /**< AXI cache bits for data read */
+ u8 SrcQos; /**< AXI QOS bits for data read */
+ u8 DstCache; /**< AXI cache bits for data write */
+ u8 DstQos; /**< AXI QOS bits for data write */
+} XZDma_DataConfig;
+
+/******************************************************************************/
+/**
+*
+* This typedef contains the descriptor configurations of ZDMA core
+*/
+typedef struct{
+ u8 AxCoherent; /**< AXI transactions are coherent or non-coherent */
+ u8 AXCache; /**< AXI cache for DSCR fetch */
+ u8 AXQos; /**< Qos bit for DSCR fetch */
+} XZDma_DscrConfig;
+
+/******************************************************************************/
+/**
+* Callback type for Completion of all data transfers.
+*
+* @param CallBackRef is a callback reference passed in by the upper layer
+* when setting the callback functions, and passed back to the
+* upper layer when the callback is invoked.
+*******************************************************************************/
+typedef void (*XZDma_DoneHandler) (void *CallBackRef);
+
+/******************************************************************************/
+/**
+* Callback type for all error interrupts.
+*
+* @param CallBackRef is a callback reference passed in by the upper layer
+* when setting the callback functions, and passed back to the
+* upper layer when the callback is invoked.
+* @param ErrorMask is a bit mask indicating the cause of the error. Its
+* value equals 'OR'ing one or more XZDMA_IXR_* values defined in
+* xzdma_hw.h
+****************************************************************************/
+typedef void (*XZDma_ErrorHandler) (void *CallBackRef, u32 ErrorMask);
+
+/**
+* This typedef contains configuration information for a ZDMA core
+* Each ZDMA core should have a configuration structure associated.
+*/
+typedef struct {
+ u16 DeviceId; /**< Device Id of ZDMA */
+ u32 BaseAddress; /**< BaseAddress of ZDMA */
+ u8 DmaType; /**< Type of DMA */
+} XZDma_Config;
+
+/******************************************************************************/
+/**
+*
+* The XZDma driver instance data structure. A pointer to an instance data
+* structure is passed around by functions to refer to a specific driver
+* instance.
+*/
+typedef struct {
+ XZDma_Config Config; /**< Hardware configuration */
+ u32 IsReady; /**< Device and the driver instance
+ * are initialized */
+ u32 IntrMask; /**< Mask for enabling interrupts */
+
+ XZDma_Mode Mode; /**< Mode of ZDMA core to be operated */
+ u8 IsSgDma; /**< Is ZDMA core is in scatter gather or
+ * not will be specified */
+ XZDma_Descriptor Descriptor; /**< It contains information about
+ * descriptors */
+
+ XZDma_DoneHandler DoneHandler; /**< Call back for transfer
+ * done interrupt */
+ void *DoneRef; /**< To be passed to the done
+ * interrupt callback */
+
+ XZDma_ErrorHandler ErrorHandler;/**< Call back for error
+ * interrupt */
+ void *ErrorRef; /**< To be passed to the error
+ * interrupt callback */
+ XZDma_DataConfig DataConfig; /**< Current configurations */
+ XZDma_DscrConfig DscrConfig; /**< Current configurations */
+ XZDmaState ChannelState; /**< ZDMA channel is busy */
+
+} XZDma;
+
+/******************************************************************************/
+/**
+*
+* This typedef contains the fields for transfer of data.
+*/
+typedef struct {
+ UINTPTR SrcAddr; /**< Source address */
+ UINTPTR DstAddr; /**< Destination Address */
+ u32 Size; /**< Size of the data to be transferred */
+ u8 SrcCoherent; /**< Source coherent */
+ u8 DstCoherent; /**< Destination coherent */
+ u8 Pause; /**< Will pause data transmission after
+ * this transfer only for SG mode */
+} XZDma_Transfer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* This function returns interrupt status read from Interrupt Status Register.
+* Use the XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to interpret the
+* returned value.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return The pending interrupts of the ZDMA core.
+* Use the masks specified in xzdma_hw.h to interpret
+* the returned value.
+* @note
+* C-style signature:
+* void XZDma_IntrGetStatus(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_IntrGetStatus(InstancePtr) \
+ XZDma_ReadReg((InstancePtr)->Config.BaseAddress, XZDMA_CH_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears interrupt(s). Every bit set in Interrupt Status
+* Register indicates that a specific type of interrupt is occurring, and this
+* function clears one or more interrupts by writing a bit mask to Interrupt
+* Clear Register.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param Mask is the type of the interrupts to enable. Use OR'ing of
+* XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
+* this parameter value.
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XZDma_IntrClear(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_IntrClear(InstancePtr, Mask) \
+ XZDma_WriteReg( (InstancePtr)->Config.BaseAddress, \
+ XZDMA_CH_ISR_OFFSET, ((u32)(Mask) & (u32)XZDMA_IXR_ALL_INTR_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function returns interrupt mask to know which interrupts are
+* enabled and which of them were disabled.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return The current interrupt mask. The mask indicates which interrupts
+* are enabled/disabled.
+* 0 bit represents .....corresponding interrupt is enabled.
+* 1 bit represents .....Corresponding interrupt is disabled.
+*
+* @note
+* C-style signature:
+* void XZDma_GetIntrMask(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_GetIntrMask(InstancePtr) \
+ XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+ (u32)(XZDMA_CH_IMR_OFFSET))
+
+/*****************************************************************************/
+/**
+*
+* This function enables individual interrupts of the ZDMA core by updating
+* the Interrupt Enable register.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param Mask is the type of the interrupts to enable. Use OR'ing of
+* XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
+* this parameter value.
+*
+* @return None.
+*
+* @note The existing enabled interrupt(s) will remain enabled.
+* C-style signature:
+* void XZDma_EnableIntr(XZDma *InstancePtr, u32 Mask)
+*
+******************************************************************************/
+#define XZDma_EnableIntr(InstancePtr, Mask) \
+ (InstancePtr)->IntrMask = ((InstancePtr)->IntrMask | (Mask))
+
+/*****************************************************************************/
+/**
+*
+* This function disables individual interrupts of the ZDMA core by updating
+* the Interrupt Disable register.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+* @param Mask is the type of the interrupts to disable. Use OR'ing of
+* XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
+* this parameter value.
+*
+* @return None.
+*
+* @note The existing disabled interrupt(s) will remain disabled.
+* C-style signature:
+* void XZDma_DisableIntr(XZDma *InstancePtr, u32 Mask)
+*
+******************************************************************************/
+#define XZDma_DisableIntr(InstancePtr, Mask) \
+ XZDma_WriteReg( (InstancePtr)->Config.BaseAddress, \
+ XZDMA_CH_IDS_OFFSET, \
+ ((u32)XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XZDMA_CH_IDS_OFFSET) | ((u32)(Mask) & (u32)XZDMA_IXR_ALL_INTR_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function returns source current payload address under process
+* of ZDMA core.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return None.
+*
+* @note This address may not be precise due to ZDMA pipeline structure
+* C-style signature:
+* u64 XZDma_SrcCurPyld(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_SrcCurPyld(InstancePtr) \
+ ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XZDMA_CH_SRC_CUR_PYLD_LSB_OFFSET)) | \
+ ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XZDMA_CH_SRC_CUR_PYLD_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
+
+/*****************************************************************************/
+/**
+*
+* This function returns destination current payload address under process
+* of ZDMA core.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return None.
+*
+* @note This address may not be precise due to ZDMA pipeline structure
+* C-style signature:
+* u64 XZDma_DstCurPyld(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_DstCurPyld(InstancePtr) \
+ ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XZDMA_CH_DST_CUR_PYLD_LSB_OFFSET)) | \
+ ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XZDMA_CH_DST_CUR_PYLD_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
+
+/*****************************************************************************/
+/**
+*
+* This function returns source descriptor current payload address under
+* process of ZDMA core.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return None.
+*
+* @note This address may not be precise due to ZDMA pipeline structure
+* C-style signature:
+* u64 XZDma_SrcDscrCurPyld(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_SrcDscrCurPyld(InstancePtr) \
+ ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XZDMA_CH_SRC_CUR_DSCR_LSB_OFFSET)) | \
+ ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XZDMA_CH_SRC_CUR_DSCR_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
+
+
+/*****************************************************************************/
+/**
+*
+* This function returns destination descriptor current payload address under
+* process of ZDMA core.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return None.
+*
+* @note This address may not be precise due to ZDMA pipeline structure
+* C-style signature:
+* u64 XZDma_DstDscrCurPyld(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_DstDscrCurPyld(InstancePtr) \
+ ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XZDMA_CH_DST_CUR_DSCR_LSB_OFFSET)) | \
+ ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XZDMA_CH_DST_CUR_DSCR_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the count of total bytes transferred through core
+* since last clear in ZDMA core.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XZDma_GetTotalByte(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_GetTotalByte(InstancePtr) \
+ XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XZDMA_CH_TOTAL_BYTE_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the count of total bytes transferred in ZDMA core.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XZDma_TotalByteClear(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_TotalByteClear(InstancePtr) \
+ XZDma_WriteReg((InstancePtr)->Config.BaseAddress, \
+ (XZDMA_CH_TOTAL_BYTE_OFFSET), (XZDMA_WRITE_TO_CLEAR_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the total number of Interrupt count for source after last
+* call of this API.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return None.
+*
+* @note Once this API is called then count will become zero.
+* C-style signature:
+* void XZDma_GetSrcIntrCnt(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_GetSrcIntrCnt(InstancePtr) \
+ XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XZDMA_CH_IRQ_SRC_ACCT_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function gets the total number of Interrupt count for destination
+* after last call of this API.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return None.
+*
+* @note Once this API is called then count will become zero.
+* C-style signature:
+* void XZDma_GetDstIntrCnt(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_GetDstIntrCnt(InstancePtr) \
+ XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XZDMA_CH_IRQ_DST_ACCT_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function Enable's the ZDMA core for initiating the data transfer once the
+* data transfer completes it will be automatically disabled.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return None.
+*
+* @note None.
+* C-style signature:
+* void XZDma_EnableCh(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_EnableCh(InstancePtr) \
+ XZDma_WriteReg((InstancePtr)->Config.BaseAddress, \
+ (XZDMA_CH_CTRL2_OFFSET), (XZDMA_CH_CTRL2_EN_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function Disable's the ZDMA core.
+*
+* @param InstancePtr is a pointer to the XZDma instance.
+*
+* @return None.
+*
+* @note None.
+* C-style signature:
+* void XZDma_DisableCh(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_DisableCh(InstancePtr) \
+ XZDma_WriteReg((InstancePtr)->Config.BaseAddress,\
+ (XZDMA_CH_CTRL2_OFFSET), (XZDMA_CH_CTRL2_DIS_MASK))
+
+/************************ Prototypes of functions **************************/
+
+XZDma_Config *XZDma_LookupConfig(u16 DeviceId);
+
+s32 XZDma_CfgInitialize(XZDma *InstancePtr, XZDma_Config *CfgPtr,
+ u32 EffectiveAddr);
+s32 XZDma_SetMode(XZDma *InstancePtr, u8 IsSgDma, XZDma_Mode Mode);
+u32 XZDma_CreateBDList(XZDma *InstancePtr, XZDma_DscrType TypeOfDscr,
+ UINTPTR Dscr_MemPtr, u32 NoOfBytes);
+s32 XZDma_SetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure);
+void XZDma_GetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure);
+s32 XZDma_SetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure);
+void XZDma_GetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure);
+s32 XZDma_Start(XZDma *InstancePtr, XZDma_Transfer *Data, u32 Num);
+void XZDma_WOData(XZDma *InstancePtr, u32 *Buffer);
+void XZDma_Resume(XZDma *InstancePtr);
+void XZDma_Reset(XZDma *InstancePtr);
+XZDmaState XZDma_ChannelState(XZDma *InstancePtr);
+
+s32 XZDma_SelfTest(XZDma *InstancePtr);
+
+void XZDma_IntrHandler(void *Instance);
+s32 XZDma_SetCallBack(XZDma *InstancePtr, XZDma_Handler HandlerType,
+ void *CallBackFunc, void *CallBackRef);
+
+/*@}*/
+
+#ifdef __cplusplus
+}
+
+#endif
+
+#endif /* XZDMA_H_ */
diff --git a/XilinxProcessorIPLib/drivers/zdma/src/xzdma_g.c b/XilinxProcessorIPLib/drivers/zdma/src/xzdma_g.c
new file mode 100644
index 00000000..392de5dd
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/zdma/src/xzdma_g.c
@@ -0,0 +1,129 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xzdma.h"
+
+/*
+* The configuration table for devices
+*/
+
+XZDma_Config XZDma_ConfigTable[] =
+{
+ {
+ XPAR_PSU_ADMA_CH0_DEVICE_ID,
+ XPAR_PSU_ADMA_CH0_BASEADDR,
+ XPAR_PSU_ADMA_CH0_DMA_MODE
+ },
+ {
+ XPAR_PSU_ADMA_CH1_DEVICE_ID,
+ XPAR_PSU_ADMA_CH1_BASEADDR,
+ XPAR_PSU_ADMA_CH1_DMA_MODE
+ },
+ {
+ XPAR_PSU_ADMA_CH2_DEVICE_ID,
+ XPAR_PSU_ADMA_CH2_BASEADDR,
+ XPAR_PSU_ADMA_CH2_DMA_MODE
+ },
+ {
+ XPAR_PSU_ADMA_CH3_DEVICE_ID,
+ XPAR_PSU_ADMA_CH3_BASEADDR,
+ XPAR_PSU_ADMA_CH3_DMA_MODE
+ },
+ {
+ XPAR_PSU_ADMA_CH4_DEVICE_ID,
+ XPAR_PSU_ADMA_CH4_BASEADDR,
+ XPAR_PSU_ADMA_CH4_DMA_MODE
+ },
+ {
+ XPAR_PSU_ADMA_CH5_DEVICE_ID,
+ XPAR_PSU_ADMA_CH5_BASEADDR,
+ XPAR_PSU_ADMA_CH5_DMA_MODE
+ },
+ {
+ XPAR_PSU_ADMA_CH6_DEVICE_ID,
+ XPAR_PSU_ADMA_CH6_BASEADDR,
+ XPAR_PSU_ADMA_CH6_DMA_MODE
+ },
+ {
+ XPAR_PSU_ADMA_CH7_DEVICE_ID,
+ XPAR_PSU_ADMA_CH7_BASEADDR,
+ XPAR_PSU_ADMA_CH7_DMA_MODE
+ },
+ {
+ XPAR_PSU_GDMA_CH0_DEVICE_ID,
+ XPAR_PSU_GDMA_CH0_BASEADDR,
+ XPAR_PSU_GDMA_CH0_DMA_MODE
+ },
+ {
+ XPAR_PSU_GDMA_CH1_DEVICE_ID,
+ XPAR_PSU_GDMA_CH1_BASEADDR,
+ XPAR_PSU_GDMA_CH1_DMA_MODE
+ },
+ {
+ XPAR_PSU_GDMA_CH2_DEVICE_ID,
+ XPAR_PSU_GDMA_CH2_BASEADDR,
+ XPAR_PSU_GDMA_CH2_DMA_MODE
+ },
+ {
+ XPAR_PSU_GDMA_CH3_DEVICE_ID,
+ XPAR_PSU_GDMA_CH3_BASEADDR,
+ XPAR_PSU_GDMA_CH3_DMA_MODE
+ },
+ {
+ XPAR_PSU_GDMA_CH4_DEVICE_ID,
+ XPAR_PSU_GDMA_CH4_BASEADDR,
+ XPAR_PSU_GDMA_CH4_DMA_MODE
+ },
+ {
+ XPAR_PSU_GDMA_CH5_DEVICE_ID,
+ XPAR_PSU_GDMA_CH5_BASEADDR,
+ XPAR_PSU_GDMA_CH5_DMA_MODE
+ },
+ {
+ XPAR_PSU_GDMA_CH6_DEVICE_ID,
+ XPAR_PSU_GDMA_CH6_BASEADDR,
+ XPAR_PSU_GDMA_CH6_DMA_MODE
+ },
+ {
+ XPAR_PSU_GDMA_CH7_DEVICE_ID,
+ XPAR_PSU_GDMA_CH7_BASEADDR,
+ XPAR_PSU_GDMA_CH7_DMA_MODE
+ }
+};
diff --git a/XilinxProcessorIPLib/drivers/zdma/src/xzdma_hw.h b/XilinxProcessorIPLib/drivers/zdma/src/xzdma_hw.h
new file mode 100644
index 00000000..87b5ce1a
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/zdma/src/xzdma_hw.h
@@ -0,0 +1,380 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma_hw.h
+*
+* This header file contains identifiers and register-level driver functions (or
+* macros) that can be used to access the Xilinx ZDMA core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ------------------------------------------------------
+* 1.0 vns 2/27/15 First release
+*
+*
+******************************************************************************/
+#ifndef XZDMA_HW_H_
+#define XZDMA_HW_H_ /**< Prevent circular inclusions
+ * by using protection macros */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Registers offsets
+ * @{
+ */
+#define XZDMA_ERR_CTRL (0x000U)
+#define XZDMA_CH_ECO (0x004U)
+#define XZDMA_CH_ISR_OFFSET (0x100U)
+#define XZDMA_CH_IMR_OFFSET (0x104U)
+#define XZDMA_CH_IEN_OFFSET (0x108U)
+#define XZDMA_CH_IDS_OFFSET (0x10CU)
+#define XZDMA_CH_CTRL0_OFFSET (0x110U)
+#define XZDMA_CH_CTRL1_OFFSET (0x114U)
+#define XZDMA_CH_PERIF_OFFSET (0x118U)
+#define XZDMA_CH_STS_OFFSET (0x11CU)
+#define XZDMA_CH_DATA_ATTR_OFFSET (0x120U)
+#define XZDMA_CH_DSCR_ATTR_OFFSET (0x124U)
+#define XZDMA_CH_SRC_DSCR_WORD0_OFFSET (0x128U)
+#define XZDMA_CH_SRC_DSCR_WORD1_OFFSET (0x12CU)
+#define XZDMA_CH_SRC_DSCR_WORD2_OFFSET (0x130U)
+#define XZDMA_CH_SRC_DSCR_WORD3_OFFSET (0x134U)
+#define XZDMA_CH_DST_DSCR_WORD0_OFFSET (0x138U)
+#define XZDMA_CH_DST_DSCR_WORD1_OFFSET (0x13CU)
+#define XZDMA_CH_DST_DSCR_WORD2_OFFSET (0x140U)
+#define XZDMA_CH_DST_DSCR_WORD3_OFFSET (0x144U)
+#define XZDMA_CH_WR_ONLY_WORD0_OFFSET (0x148U)
+#define XZDMA_CH_WR_ONLY_WORD1_OFFSET (0x14CU)
+#define XZDMA_CH_WR_ONLY_WORD2_OFFSET (0x150U)
+#define XZDMA_CH_WR_ONLY_WORD3_OFFSET (0x154U)
+#define XZDMA_CH_SRC_START_LSB_OFFSET (0x158U)
+#define XZDMA_CH_SRC_START_MSB_OFFSET (0x15CU)
+#define XZDMA_CH_DST_START_LSB_OFFSET (0x160U)
+#define XZDMA_CH_DST_START_MSB_OFFSET (0x164U)
+#define XZDMA_CH_SRC_CUR_PYLD_LSB_OFFSET (0x168U)
+#define XZDMA_CH_SRC_CUR_PYLD_MSB_OFFSET (0x16CU)
+#define XZDMA_CH_DST_CUR_PYLD_LSB_OFFSET (0x170U)
+#define XZDMA_CH_DST_CUR_PYLD_MSB_OFFSET (0x174U)
+#define XZDMA_CH_SRC_CUR_DSCR_LSB_OFFSET (0x178U)
+#define XZDMA_CH_SRC_CUR_DSCR_MSB_OFFSET (0x17CU)
+#define XZDMA_CH_DST_CUR_DSCR_LSB_OFFSET (0x180U)
+#define XZDMA_CH_DST_CUR_DSCR_MSB_OFFSET (0x184U)
+#define XZDMA_CH_TOTAL_BYTE_OFFSET (0x188U)
+#define XZDMA_CH_RATE_CNTL_OFFSET (0x18CU)
+#define XZDMA_CH_IRQ_SRC_ACCT_OFFSET (0x190U)
+#define XZDMA_CH_IRQ_DST_ACCT_OFFSET (0x194U)
+#define XZDMA_CH_CTRL2_OFFSET (0x200U)
+/*@}*/
+
+/** @name Interrupt Enable/Disable/Mask/Status registers bit masks and shifts
+ * @{
+ */
+#define XZDMA_IXR_DMA_PAUSE_MASK (0x00000800U) /**< IXR pause mask */
+#define XZDMA_IXR_DMA_DONE_MASK (0x00000400U) /**< IXR done mask */
+#define XZDMA_IXR_AXI_WR_DATA_MASK (0x00000200U) /**< IXR AXI write data
+ * error mask */
+#define XZDMA_IXR_AXI_RD_DATA_MASK (0x00000100U) /**< IXR AXI read data
+ * error mask */
+#define XZDMA_IXR_AXI_RD_DST_DSCR_MASK (0x00000080U) /**< IXR AXI read
+ * descriptor error
+ * mask */
+#define XZDMA_IXR_AXI_RD_SRC_DSCR_MASK (0x00000040U) /**< IXR AXI write
+ * descriptor error
+ * mask */
+#define XZDMA_IXR_DST_ACCT_ERR_MASK (0x00000020U) /**< IXR DST interrupt
+ * count overflow
+ * mask */
+#define XZDMA_IXR_SRC_ACCT_ERR_MASK (0x00000010U) /**< IXR SRC interrupt
+ * count overflow
+ * mask */
+#define XZDMA_IXR_BYTE_CNT_OVRFL_MASK (0x00000008U) /**< IXR byte count over
+ * flow mask */
+#define XZDMA_IXR_DST_DSCR_DONE_MASK (0x00000004U) /**< IXR destination
+ * descriptor done
+ * mask */
+#define XZDMA_IXR_SRC_DSCR_DONE_MASK (0x00000002U) /**< IXR source
+ * descriptor done
+ * mask */
+#define XZDMA_IXR_INV_APB_MASK (0x00000001U) /**< IXR invalid APB
+ * access mask */
+#define XZDMA_IXR_ALL_INTR_MASK (0x00000FFFU) /**< IXR OR of all the
+ * interrupts mask */
+#define XZDMA_IXR_DONE_MASK (0x00000400U) /**< IXR All done mask */
+
+#define XZDMA_IXR_ERR_MASK (0x00000BF9U) /**< IXR all Error mask*/
+ /**< Or of XZDMA_IXR_AXI_WR_DATA_MASK,
+ * XZDMA_IXR_AXI_RD_DATA_MASK,
+ * XZDMA_IXR_AXI_RD_DST_DSCR_MASK,
+ * XZDMA_IXR_AXI_RD_SRC_DSCR_MASK,
+ * XZDMA_IXR_INV_APB_MASK,
+ * XZDMA_IXR_DMA_PAUSE_MASK,
+ * XZDMA_IXR_BYTE_CNT_OVRFL_MASK,
+ * XZDMA_IXR_SRC_ACCT_ERR_MASK,
+ * XZDMA_IXR_DST_ACCT_ERR_MASK */
+/*@}*/
+
+/** @name Channel Control0 register bit masks and shifts
+ * @{
+ */
+#define XZDMA_CTRL0_OVR_FETCH_MASK (0x00000080U) /**< Over fetch mask */
+#define XZDMA_CTRL0_POINT_TYPE_MASK (0x00000040U) /**< Pointer type mask */
+#define XZDMA_CTRL0_MODE_MASK (0x00000030U) /**< Mode mask */
+#define XZDMA_CTRL0_WRONLY_MASK (0x00000010U) /**< Write only mask */
+#define XZDMA_CTRL0_RDONLY_MASK (0x00000020U) /**< Read only mask */
+#define XZDMA_CTRL0_RATE_CNTL_MASK (0x00000008U) /**< Rate control mask */
+#define XZDMA_CTRL0_CONT_ADDR_MASK (0x00000004U) /**< Continue address
+ * specified mask */
+#define XZDMA_CTRL0_CONT_MASK (0x00000002U) /**< Continue mask */
+
+#define XZDMA_CTRL0_OVR_FETCH_SHIFT (7U) /**< Over fetch shift */
+#define XZDMA_CTRL0_POINT_TYPE_SHIFT (6U) /**< Pointer type shift */
+#define XZDMA_CTRL0_MODE_SHIFT (4U) /**< Mode type shift */
+#define XZDMA_CTRL0_RESET_VALUE (0x00000080U) /**< CTRL0 reset value */
+
+/*@}*/
+
+/** @name Channel Control1 register bit masks and shifts
+ * @{
+ */
+#define XZDMA_CTRL1_SRC_ISSUE_MASK (0x0000001FU) /**< Source issue mask */
+#define XZDMA_CTRL1_RESET_VALUE (0x000003FFU) /**< CTRL1 reset value */
+/*@}*/
+
+/** @name Channel Peripheral register bit masks and shifts
+ * @{
+ */
+#define XZDMA_PERIF_PROG_CELL_CNT_MASK (0x0000003EU) /**< Peripheral program
+ * cell count */
+#define XZDMA_PERIF_SIDE_MASK (0x00000002U) /**< Interface attached
+ * the side mask */
+#define XZDMA_PERIF_EN_MASK (0x00000001U) /**< Peripheral flow
+ * control mask */
+/*@}*/
+
+/** @name Channel Status register bit masks and shifts
+ * @{
+ */
+#define XZDMA_STS_DONE_ERR_MASK (0x00000003U) /**< Done with errors mask */
+#define XZDMA_STS_BUSY_MASK (0x00000002U) /**< ZDMA is busy in transfer
+ * mask */
+#define XZDMA_STS_PAUSE_MASK (0x00000001U) /**< ZDMA is in Pause state
+ * mask */
+#define XZDMA_STS_DONE_MASK (0x00000000U) /**< ZDMA done mask */
+#define XZDMA_STS_ALL_MASK (0x00000003U) /**< ZDMA status mask */
+
+/*@}*/
+
+/** @name Channel Data Attribute register bit masks and shifts
+ * @{
+ */
+#define XZDMA_DATA_ATTR_ARBURST_MASK (0x0C000000U) /**< Data ArBurst mask */
+#define XZDMA_DATA_ATTR_ARCACHE_MASK (0x03C00000U) /**< Data ArCache mask */
+#define XZDMA_DATA_ATTR_ARQOS_MASK (0x003C0000U) /**< Data ARQos masks */
+#define XZDMA_DATA_ATTR_ARLEN_MASK (0x0003C000U) /**< Data Arlen mask */
+#define XZDMA_DATA_ATTR_AWBURST_MASK (0x00003000U) /**< Data Awburst mask */
+#define XZDMA_DATA_ATTR_AWCACHE_MASK (0x00000F00U) /**< Data AwCache mask */
+#define XZDMA_DATA_ATTR_AWQOS_MASK (0x000000F0U) /**< Data AwQos mask */
+#define XZDMA_DATA_ATTR_AWLEN_MASK (0x0000000FU) /**< Data Awlen mask */
+
+#define XZDMA_DATA_ATTR_ARBURST_SHIFT (26U) /**< Data Arburst shift */
+#define XZDMA_DATA_ATTR_ARCACHE_SHIFT (22U) /**< Data ArCache shift */
+#define XZDMA_DATA_ATTR_ARQOS_SHIFT (18U) /**< Data ARQos shift */
+#define XZDMA_DATA_ATTR_ARLEN_SHIFT (14U) /**< Data Arlen shift */
+#define XZDMA_DATA_ATTR_AWBURST_SHIFT (12U) /**< Data Awburst shift */
+#define XZDMA_DATA_ATTR_AWCACHE_SHIFT (8U) /**< Data Awcache shift */
+#define XZDMA_DATA_ATTR_AWQOS_SHIFT (4U) /**< Data Awqos shift */
+#define XZDMA_DATA_ATTR_RESET_VALUE (0x0483D20FU) /**< Data Attributes
+ * reset value */
+
+/*@}*/
+
+/** @name Channel DSCR Attribute register bit masks and shifts
+ * @{
+ */
+#define XZDMA_DSCR_ATTR_AXCOHRNT_MASK (0x00000100U) /**< Descriptor coherent
+ * mask */
+#define XZDMA_DSCR_ATTR_AXCACHE_MASK (0x000000F0U) /**< Descriptor cache
+ * mask */
+#define XZDMA_DSCR_ATTR_AXQOS_MASK (0x0000000FU) /**< Descriptor AxQos
+ * mask */
+
+#define XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT (8U) /**< Descriptor coherent shift */
+#define XZDMA_DSCR_ATTR_AXCACHE_SHIFT (7U) /**< Descriptor cache shift */
+#define XZDMA_DSCR_ATTR_RESET_VALUE (0x00000000U) /**< Dscr Attributes
+ * reset value */
+
+/*@}*/
+
+/** @name Channel Source/Destination Word0 register bit mask
+ * @{
+ */
+#define XZDMA_WORD0_LSB_MASK (0xFFFFFFFFU) /**< LSB Address mask */
+/*@}*/
+
+/** @name Channel Source/Destination Word1 register bit mask
+ * @{
+ */
+#define XZDMA_WORD1_MSB_MASK (0x0001FFFFU) /**< MSB Address mask */
+#define XZDMA_WORD1_MSB_SHIFT (32U) /**< MSB Address shift */
+/*@}*/
+
+/** @name Channel Source/Destination Word2 register bit mask
+ * @{
+ */
+#define XZDMA_WORD2_SIZE_MASK (0x3FFFFFFFU) /**< Size mask */
+/*@}*/
+
+/** @name Channel Source/Destination Word3 register bit masks and shifts
+ * @{
+ */
+#define XZDMA_WORD3_CMD_MASK (0x00000018U) /**< Cmd mask */
+#define XZDMA_WORD3_CMD_SHIFT (3U) /**< Cmd shift */
+#define XZDMA_WORD3_CMD_NXTVALID_MASK (0x00000000U) /**< Next Dscr is valid
+ * mask */
+#define XZDMA_WORD3_CMD_PAUSE_MASK (0x00000008U) /**< Pause after this
+ * dscr mask */
+#define XZDMA_WORD3_CMD_STOP_MASK (0x00000010U) /**< Stop after this
+ ..* dscr mask */
+#define XZDMA_WORD3_INTR_MASK (0x00000004U) /**< Interrupt
+ * enable or disable
+ * mask */
+#define XZDMA_WORD3_INTR_SHIFT (2U) /**< Interrupt enable
+ * disable
+ * shift */
+#define XZDMA_WORD3_TYPE_MASK (0x00000002U) /**< Type of Descriptor
+ * mask */
+#define XZDMA_WORD3_TYPE_SHIFT (1U) /**< Type of Descriptor
+ * Shift */
+#define XZDMA_WORD3_COHRNT_MASK (0x00000001U) /**< Coherence mask */
+/*@}*/
+
+/** @name Channel Source/Destination start address or current payload
+ * MSB register bit mask
+ * @{
+ */
+#define XZDMA_START_MSB_ADDR_MASK (0x0001FFFFU) /**< Start msb address
+ * mask */
+/*@}*/
+
+/** @name Channel Rate control count register bit mask
+ * @{
+ */
+#define XZDMA_CH_RATE_CNTL_MASK (0x00000FFFU) /**< Channel rate control
+ * mask */
+/*@}*/
+
+/** @name Channel Source/Destination Interrupt account count register bit mask
+ * @{
+ */
+#define XZDMA_CH_IRQ_ACCT_MASK (0x000000FFU) /**< Interrupt count
+ * mask */
+/*@}*/
+
+/** @name Channel debug register 0/1 bit mask
+ * @{
+ */
+#define XZDMA_CH_DBG_CMN_BUF_MASK (0x000001FFU) /**< Common buffer count
+ * mask */
+/*@}*/
+
+/** @name Channel control2 register bit mask
+ * @{
+ */
+#define XZDMA_CH_CTRL2_EN_MASK (0x00000001U) /**< Channel enable
+ * mask */
+#define XZDMA_CH_CTRL2_DIS_MASK (0x00000000U) /**< Channel disable
+ * mask */
+/*@}*/
+
+/** @name Channel control2 register bit mask
+ * @{
+ */
+ #define XZDMA_WRITE_TO_CLEAR_MASK (0x00000000U) /**< Write to clear
+ * mask */
+ /*@}*/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XZDma_In32 Xil_In32 /**< Input operation */
+#define XZDma_Out32 Xil_Out32 /**< Output operation */
+
+/*****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param BaseAddress is the Xilinx base address of the ZDMA core.
+* @param RegOffset is the register offset of the register.
+*
+* @return The 32-bit value of the register.
+*
+* @note C-style signature:
+* u32 XZDma_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+******************************************************************************/
+#define XZDma_ReadReg(BaseAddress, RegOffset) \
+ XZDma_In32((BaseAddress) + (u32)(RegOffset))
+
+/*****************************************************************************/
+/**
+*
+* This macro writes the value into the given register.
+*
+* @param BaseAddress is the Xilinx base address of the ZDMA core.
+* @param RegOffset is the register offset of the register.
+* @param Data is the 32-bit value to write to the register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XZDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+******************************************************************************/
+#define XZDma_WriteReg(BaseAddress, RegOffset, Data) \
+ XZDma_Out32(((BaseAddress) + (u32)(RegOffset)), (u32)(Data))
+
+#ifdef __cplusplus
+}
+
+#endif
+
+#endif /* XZDMA_HW_H_ */
diff --git a/XilinxProcessorIPLib/drivers/zdma/src/xzdma_intr.c b/XilinxProcessorIPLib/drivers/zdma/src/xzdma_intr.c
new file mode 100644
index 00000000..3e4b5132
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/zdma/src/xzdma_intr.c
@@ -0,0 +1,202 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma_intr.c
+*
+* This file contains interrupt related functions of Xilinx ZDMA core.
+* Please see xzdma.h for more details of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ------------------------------------------------------
+* 1.0 vns 2/27/15 First release
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xzdma.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the ZDMA core.
+*
+* This handler reads the pending interrupt from Status register, determines the
+* source of the interrupts and calls the respective callbacks for the
+* interrupts that are enabled in IRQ_ENABLE register, and finally clears the
+* interrupts.
+*
+* The application is responsible for connecting this function to the interrupt
+* system. Application beyond this driver is also responsible for providing
+* callbacks to handle interrupts and installing the callbacks using
+* XZDma_SetCallBack() during initialization phase. .
+*
+* @param Instance is a pointer to the XZDma instance to be worked on.
+*
+* @return None.
+*
+* @note To generate interrupt required interrupts should be enabled.
+*
+******************************************************************************/
+void XZDma_IntrHandler(void *Instance)
+{
+ u32 PendingIntr;
+ u32 ErrorStatus;
+ XZDma *InstancePtr = NULL;
+ InstancePtr = (XZDma *)((void *)Instance);
+
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /* Get pending interrupts */
+ PendingIntr = (u32)(XZDma_IntrGetStatus(InstancePtr));
+ PendingIntr &= (~XZDma_GetIntrMask(InstancePtr));
+
+ /* ZDMA transfer has completed */
+ ErrorStatus = (PendingIntr) & (XZDMA_IXR_DMA_DONE_MASK);
+ if ((ErrorStatus) != 0U) {
+ XZDma_DisableIntr(InstancePtr, XZDMA_IXR_ALL_INTR_MASK);
+ InstancePtr->ChannelState = XZDMA_IDLE;
+ InstancePtr->DoneHandler(InstancePtr->DoneRef);
+ }
+
+ /* An error has been occurred */
+ ErrorStatus = PendingIntr & (XZDMA_IXR_ERR_MASK);
+ if ((ErrorStatus) != 0U) {
+ if ((ErrorStatus & XZDMA_IXR_DMA_PAUSE_MASK) ==
+ XZDMA_IXR_DMA_PAUSE_MASK) {
+ InstancePtr->ChannelState = XZDMA_PAUSE;
+ }
+ else {
+ if ((ErrorStatus & (XZDMA_IXR_AXI_WR_DATA_MASK |
+ XZDMA_IXR_AXI_RD_DATA_MASK |
+ XZDMA_IXR_AXI_RD_DST_DSCR_MASK |
+ XZDMA_IXR_AXI_RD_SRC_DSCR_MASK)) != 0x00U) {
+ InstancePtr->ChannelState = XZDMA_IDLE;
+ }
+ }
+ InstancePtr->ErrorHandler(InstancePtr->ErrorRef, ErrorStatus);
+ }
+
+ /* Clear pending interrupt(s) */
+ XZDma_IntrClear(InstancePtr, PendingIntr);
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine installs an asynchronous callback function for the given
+* HandlerType.
+*
+*
+* HandlerType Callback Function Type
+* ----------------------- --------------------------------------------------
+* XZDMA_HANDLER_DONE Done handler
+* XZDMA_HANDLER_ERROR Error handler
+*
+*
+*
+* @param InstancePtr is a pointer to the XZDma instance to be worked on.
+* @param HandlerType specifies which callback is to be attached.
+* @param CallBackFunc is the address of the callback function.
+* @param CallBackRef is a user data item that will be passed to the
+* callback function when it is invoked.
+*
+* @return
+* - XST_SUCCESS when handler is installed.
+* - XST_INVALID_PARAM when HandlerType is invalid.
+*
+* @note Invoking this function for a handler that already has been
+* installed replaces it with the new handler.
+*
+******************************************************************************/
+s32 XZDma_SetCallBack(XZDma *InstancePtr, XZDma_Handler HandlerType,
+ void *CallBackFunc, void *CallBackRef)
+{
+ s32 Status;
+
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(CallBackFunc != NULL);
+ Xil_AssertNonvoid(CallBackRef != NULL);
+ Xil_AssertNonvoid((HandlerType == XZDMA_HANDLER_DONE) ||
+ (HandlerType == XZDMA_HANDLER_ERROR));
+ Xil_AssertNonvoid(InstancePtr->IsReady ==
+ (u32)(XIL_COMPONENT_IS_READY));
+
+ /*
+ * Calls the respective callback function corresponding to
+ * the handler type
+ */
+ switch (HandlerType) {
+ case XZDMA_HANDLER_DONE:
+ InstancePtr->DoneHandler =
+ (XZDma_DoneHandler)((void *)CallBackFunc);
+ InstancePtr->DoneRef = CallBackRef;
+ Status = (XST_SUCCESS);
+ break;
+
+ case XZDMA_HANDLER_ERROR:
+ InstancePtr->ErrorHandler =
+ (XZDma_ErrorHandler)((void *)CallBackFunc);
+ InstancePtr->ErrorRef = CallBackRef;
+ Status = (XST_SUCCESS);
+ break;
+
+ default:
+ Status = (XST_INVALID_PARAM);
+ break;
+ }
+
+ return Status;
+}
diff --git a/XilinxProcessorIPLib/drivers/zdma/src/xzdma_selftest.c b/XilinxProcessorIPLib/drivers/zdma/src/xzdma_selftest.c
new file mode 100644
index 00000000..d4469031
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/zdma/src/xzdma_selftest.c
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma_selftest.c
+*
+* This file contains the self-test function for the ZDMA core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ------------------------------------------------------
+* 1.0 vns 2/27/15 First release
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xzdma.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This file contains a diagnostic self-test function for the ZDMA driver.
+* Refer to the header file xzdma.h for more detailed information.
+*
+* @param InstancePtr is a pointer to XZDma instance.
+*
+* @return
+* - XST_SUCCESS if the test is successful.
+* - XST_FAILURE if the test is failed.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XZDma_SelfTest(XZDma *InstancePtr)
+{
+
+ u32 Data;
+ s32 Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_CTRL0_OFFSET);
+
+ /* Changing DMA channel to over fetch */
+
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL0_OFFSET,
+ (Data | XZDMA_CTRL0_OVR_FETCH_MASK));
+
+ if (((u32)XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+ XZDMA_CH_CTRL0_OFFSET) & XZDMA_CTRL0_OVR_FETCH_MASK) !=
+ XZDMA_CTRL0_OVR_FETCH_MASK) {
+ Status = (s32)XST_FAILURE;
+ }
+ else {
+ Status = (s32)XST_SUCCESS;
+ }
+
+ /* Retrieving the change settings */
+ XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL0_OFFSET,
+ Data);
+
+ return Status;
+
+}
diff --git a/XilinxProcessorIPLib/drivers/zdma/src/xzdma_sinit.c b/XilinxProcessorIPLib/drivers/zdma/src/xzdma_sinit.c
new file mode 100644
index 00000000..d9c707f5
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/zdma/src/xzdma_sinit.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma_sinit.c
+*
+* This file contains static initialization methods for Xilinx ZDMA core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ------------------------------------------------------
+* 1.0 vns 2/27/15 First release
+*
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xzdma.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* XZDma_LookupConfig returns a reference to an XZDma_Config structure
+* based on the unique device id, DeviceId. The return value will refer
+* to an entry in the device configuration table defined in the xzdma_g.c
+* file.
+*
+* @param DeviceId is the unique device ID of the device for the lookup
+* operation.
+*
+* @return CfgPtr is a reference to a config record in the configuration
+* table (in xzdma_g.c) corresponding to DeviceId, or
+* NULL if no match is found.
+*
+* @note None.
+******************************************************************************/
+XZDma_Config *XZDma_LookupConfig(u16 DeviceId)
+{
+ extern XZDma_Config XZDma_ConfigTable[XPAR_XZDMA_NUM_INSTANCES];
+ XZDma_Config *CfgPtr = NULL;
+ u32 Index;
+
+ /* Checks all the instances */
+ for (Index = (u32)0x0; Index < (u32)(XPAR_XZDMA_NUM_INSTANCES);
+ Index++) {
+ if (XZDma_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XZDma_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XZDma_Config *)CfgPtr;
+}