diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_common.c b/lib/sw_apps/zynqmp_pmufw/src/pm_common.c index 3e65d031..fed0fa7f 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/pm_common.c +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_common.c @@ -97,6 +97,12 @@ const char* PmStrNode(const u32 node) return "NODE_USB_1"; case NODE_TTC_0: return "NODE_TTC_0"; + case NODE_TTC_1: + return "NODE_TTC_1"; + case NODE_TTC_2: + return "NODE_TTC_2"; + case NODE_TTC_3: + return "NODE_TTC_3"; case NODE_SATA: return "NODE_SATA"; case NODE_APLL: @@ -109,6 +115,48 @@ const char* PmStrNode(const u32 node) return "NODE_RPLL"; case NODE_IOPLL: return "NODE_IOPLL"; + case NODE_UART_0: + return "NODE_UART_0"; + case NODE_UART_1: + return "NODE_UART_1"; + case NODE_SPI_0: + return "NODE_SPI_0"; + case NODE_SPI_1: + return "NODE_SPI_1"; + case NODE_I2C_0: + return "NODE_I2C_0"; + case NODE_I2C_1: + return "NODE_I2C_1"; + case NODE_SD_0: + return "NODE_SD_0"; + case NODE_SD_1: + return "NODE_SD_1"; + case NODE_CAN_0: + return "NODE_CAN_0"; + case NODE_CAN_1: + return "NODE_CAN_1"; + case NODE_ETH_0: + return "NODE_ETH_0"; + case NODE_ETH_1: + return "NODE_ETH_1"; + case NODE_ETH_2: + return "NODE_ETH_2"; + case NODE_ETH_3: + return "NODE_ETH_3"; + case NODE_ADMA: + return "NODE_ADMA"; + case NODE_GDMA: + return "NODE_GDMA"; + case NODE_DP: + return "NODE_DP"; + case NODE_NAND: + return "NODE_NAND"; + case NODE_QSPI: + return "NODE_QSPI"; + case NODE_GPIO: + return "NODE_GPIO"; + case NODE_AFI: + return "NODE_AFI"; default: return "ERROR_NODE"; } diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_defs.h b/lib/sw_apps/zynqmp_pmufw/src/pm_defs.h index cdfe1e72..abe18d64 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/pm_defs.h +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_defs.h @@ -123,12 +123,36 @@ #define NODE_USB_0 22U #define NODE_USB_1 23U #define NODE_TTC_0 24U -#define NODE_SATA 25U -#define NODE_APLL 26U -#define NODE_VPLL 27U -#define NODE_DPLL 28U -#define NODE_RPLL 29U -#define NODE_IOPLL 30U +#define NODE_TTC_1 25U +#define NODE_TTC_2 26U +#define NODE_TTC_3 27U +#define NODE_SATA 28U +#define NODE_ETH_0 29U +#define NODE_ETH_1 30U +#define NODE_ETH_2 31U +#define NODE_ETH_3 32U +#define NODE_UART_0 33U +#define NODE_UART_1 34U +#define NODE_SPI_0 35U +#define NODE_SPI_1 36U +#define NODE_I2C_0 37U +#define NODE_I2C_1 38U +#define NODE_SD_0 39U +#define NODE_SD_1 40U +#define NODE_DP 41U +#define NODE_GDMA 42U +#define NODE_ADMA 43U +#define NODE_NAND 44U +#define NODE_QSPI 45U +#define NODE_GPIO 46U +#define NODE_CAN_0 47U +#define NODE_CAN_1 48U +#define NODE_AFI 49U +#define NODE_APLL 50U +#define NODE_VPLL 51U +#define NODE_DPLL 52U +#define NODE_RPLL 53U +#define NODE_IOPLL 54U #define NODE_MIN NODE_APU #define NODE_MAX NODE_IOPLL diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_master.c b/lib/sw_apps/zynqmp_pmufw/src/pm_master.c index c9572a38..b28c4830 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/pm_master.c +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_master.c @@ -111,6 +111,30 @@ PmRequirement pmApuReq_g[PM_MASTER_APU_SLAVE_MAX] = { .currReq = 0U, .nextReq = 0U, }, + [PM_MASTER_APU_SLAVE_TTC1] = { + .slave = &pmSlaveTtc1_g.slv, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_TTC2] = { + .slave = &pmSlaveTtc2_g.slv, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_TTC3] = { + .slave = &pmSlaveTtc3_g.slv, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, [PM_MASTER_APU_SLAVE_SATA] = { .slave = &pmSlaveSata_g.slv, .requestor = &pmMasterApu_g, @@ -159,6 +183,190 @@ PmRequirement pmApuReq_g[PM_MASTER_APU_SLAVE_MAX] = { .currReq = 0U, .nextReq = 0U, }, + [PM_MASTER_APU_SLAVE_GPUPP0] = { + .slave = &pmSlaveGpuPP0_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_GPUPP1] = { + .slave = &pmSlaveGpuPP1_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_UART0] = { + .slave = &pmSlaveUart0_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_UART1] = { + .slave = &pmSlaveUart1_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_SPI0] = { + .slave = &pmSlaveSpi0_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_SPI1] = { + .slave = &pmSlaveSpi1_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_I2C0] = { + .slave = &pmSlaveI2C0_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_I2C1] = { + .slave = &pmSlaveI2C1_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_SD0] = { + .slave = &pmSlaveSD0_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_SD1] = { + .slave = &pmSlaveSD1_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_CAN0] = { + .slave = &pmSlaveCan0_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_CAN1] = { + .slave = &pmSlaveCan1_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_ETH0] = { + .slave = &pmSlaveEth0_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_ETH1] = { + .slave = &pmSlaveEth1_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_ETH2] = { + .slave = &pmSlaveEth2_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_ETH3] = { + .slave = &pmSlaveEth3_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_ADMA] = { + .slave = &pmSlaveAdma_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_GDMA] = { + .slave = &pmSlaveGdma_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_DP] = { + .slave = &pmSlaveDP_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_NAND] = { + .slave = &pmSlaveNand_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_QSPI] = { + .slave = &pmSlaveQSpi_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_GPIO] = { + .slave = &pmSlaveGpio_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_AFI] = { + .slave = &pmSlaveAFI_g, + .requestor = &pmMasterApu_g, + .info = 0U, + .defaultReq = 0U, + .currReq = 0U, + .nextReq = 0U, + }, }; /* Requirement of RPU_0 master */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_master.h b/lib/sw_apps/zynqmp_pmufw/src/pm_master.h index 7e37e0b1..a3fa1e34 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/pm_master.h +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_master.h @@ -63,14 +63,40 @@ typedef struct PmMaster PmMaster; #define PM_MASTER_APU_SLAVE_USB0 5U #define PM_MASTER_APU_SLAVE_USB1 6U #define PM_MASTER_APU_SLAVE_TTC0 7U -#define PM_MASTER_APU_SLAVE_SATA 8U -#define PM_MASTER_APU_SLAVE_APLL 9U -#define PM_MASTER_APU_SLAVE_VPLL 10U -#define PM_MASTER_APU_SLAVE_DPLL 11U -#define PM_MASTER_APU_SLAVE_RPLL 12U -#define PM_MASTER_APU_SLAVE_IOPLL 13U +#define PM_MASTER_APU_SLAVE_TTC1 8U +#define PM_MASTER_APU_SLAVE_TTC2 9U +#define PM_MASTER_APU_SLAVE_TTC3 10U +#define PM_MASTER_APU_SLAVE_SATA 11U +#define PM_MASTER_APU_SLAVE_APLL 12U +#define PM_MASTER_APU_SLAVE_VPLL 13U +#define PM_MASTER_APU_SLAVE_DPLL 14U +#define PM_MASTER_APU_SLAVE_RPLL 15U +#define PM_MASTER_APU_SLAVE_IOPLL 16U +#define PM_MASTER_APU_SLAVE_GPUPP0 17U +#define PM_MASTER_APU_SLAVE_GPUPP1 18U +#define PM_MASTER_APU_SLAVE_UART0 19U +#define PM_MASTER_APU_SLAVE_UART1 20U +#define PM_MASTER_APU_SLAVE_SPI0 21U +#define PM_MASTER_APU_SLAVE_SPI1 22U +#define PM_MASTER_APU_SLAVE_I2C0 23U +#define PM_MASTER_APU_SLAVE_I2C1 24U +#define PM_MASTER_APU_SLAVE_SD0 25U +#define PM_MASTER_APU_SLAVE_SD1 26U +#define PM_MASTER_APU_SLAVE_CAN0 27U +#define PM_MASTER_APU_SLAVE_CAN1 28U +#define PM_MASTER_APU_SLAVE_ETH0 29U +#define PM_MASTER_APU_SLAVE_ETH1 30U +#define PM_MASTER_APU_SLAVE_ETH2 31U +#define PM_MASTER_APU_SLAVE_ETH3 32U +#define PM_MASTER_APU_SLAVE_ADMA 33U +#define PM_MASTER_APU_SLAVE_GDMA 34U +#define PM_MASTER_APU_SLAVE_DP 35U +#define PM_MASTER_APU_SLAVE_NAND 36U +#define PM_MASTER_APU_SLAVE_QSPI 37U +#define PM_MASTER_APU_SLAVE_GPIO 38U +#define PM_MASTER_APU_SLAVE_AFI 39U -#define PM_MASTER_APU_SLAVE_MAX 14U +#define PM_MASTER_APU_SLAVE_MAX 40U /* Rpu0 slaves */ #define PM_MASTER_RPU_0_SLAVE_TCM0A 0U diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_node.c b/lib/sw_apps/zynqmp_pmufw/src/pm_node.c index f4c3b67f..62e229e3 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/pm_node.c +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_node.c @@ -63,12 +63,38 @@ static PmNode* const pmNodes[NODE_MAX] = { &pmSlaveUsb0_g.slv.node, &pmSlaveUsb1_g.slv.node, &pmSlaveTtc0_g.slv.node, + &pmSlaveTtc1_g.slv.node, + &pmSlaveTtc2_g.slv.node, + &pmSlaveTtc3_g.slv.node, &pmSlaveSata_g.slv.node, &pmSlaveApll_g.slv.node, &pmSlaveVpll_g.slv.node, &pmSlaveDpll_g.slv.node, &pmSlaveRpll_g.slv.node, &pmSlaveIOpll_g.slv.node, + &pmSlaveGpuPP0_g.node, + &pmSlaveGpuPP1_g.node, + &pmSlaveUart0_g.node, + &pmSlaveUart1_g.node, + &pmSlaveSpi0_g.node, + &pmSlaveSpi1_g.node, + &pmSlaveI2C0_g.node, + &pmSlaveI2C1_g.node, + &pmSlaveSD0_g.node, + &pmSlaveSD1_g.node, + &pmSlaveCan0_g.node, + &pmSlaveCan1_g.node, + &pmSlaveEth0_g.node, + &pmSlaveEth1_g.node, + &pmSlaveEth2_g.node, + &pmSlaveEth3_g.node, + &pmSlaveAdma_g.node, + &pmSlaveGdma_g.node, + &pmSlaveDP_g.node, + &pmSlaveNand_g.node, + &pmSlaveQSpi_g.node, + &pmSlaveGpio_g.node, + &pmSlaveAFI_g.node, }; /** diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_periph.c b/lib/sw_apps/zynqmp_pmufw/src/pm_periph.c index 809d729e..036c289c 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/pm_periph.c +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_periph.c @@ -77,6 +77,511 @@ PmSlaveTtc pmSlaveTtc0_g = { }, }; +static PmWakeProperties pmTtc1Wake = { + .proxyIrqMask = FPD_GICP_TTC1_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP1], +}; + +static PmRequirement* const pmTtc1Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_TTC1], +}; + +PmSlaveTtc pmSlaveTtc1_g = { + .slv = { + .node = { + .derived = &pmSlaveTtc1_g, + .nodeId = NODE_TTC_1, + .typeId = PM_TYPE_TTC, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmTtc1Reqs, + .reqsCnt = ARRAY_SIZE(pmTtc1Reqs), + .wake = &pmTtc1Wake, + .slvFsm = &slaveAonFsm, + }, +}; + +static PmWakeProperties pmTtc2Wake = { + .proxyIrqMask = FPD_GICP_TTC2_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP1], +}; + +static PmRequirement* const pmTtc2Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_TTC2], +}; + +PmSlaveTtc pmSlaveTtc2_g = { + .slv = { + .node = { + .derived = &pmSlaveTtc2_g, + .nodeId = NODE_TTC_2, + .typeId = PM_TYPE_TTC, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmTtc2Reqs, + .reqsCnt = ARRAY_SIZE(pmTtc2Reqs), + .wake = &pmTtc2Wake, + .slvFsm = &slaveAonFsm, + }, +}; + +static PmWakeProperties pmTtc3Wake = { + .proxyIrqMask = FPD_GICP_TTC3_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP1], +}; + +static PmRequirement* const pmTtc3Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_TTC3], +}; + +PmSlaveTtc pmSlaveTtc3_g = { + .slv = { + .node = { + .derived = &pmSlaveTtc3_g, + .nodeId = NODE_TTC_3, + .typeId = PM_TYPE_TTC, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmTtc3Reqs, + .reqsCnt = ARRAY_SIZE(pmTtc3Reqs), + .wake = &pmTtc3Wake, + .slvFsm = &slaveAonFsm, + }, +}; + +static PmWakeProperties pmUart0Wake = { + .proxyIrqMask = FPD_GICP_UART0_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP0], +}; + +static PmRequirement* const pmUart0Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_UART0], +}; + +PmSlave pmSlaveUart0_g = { + .node = { + .derived = &pmSlaveUart0_g, + .nodeId = NODE_UART_0, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmUart0Reqs, + .reqsCnt = ARRAY_SIZE(pmUart0Reqs), + .wake = &pmUart0Wake, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmUart1Wake = { + .proxyIrqMask = FPD_GICP_UART1_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP0], +}; + +static PmRequirement* const pmUart1Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_UART1], +}; + +PmSlave pmSlaveUart1_g = { + .node = { + .derived = &pmSlaveUart1_g, + .nodeId = NODE_UART_1, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmUart1Reqs, + .reqsCnt = ARRAY_SIZE(pmUart1Reqs), + .wake = &pmUart1Wake, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmSpi0Wake = { + .proxyIrqMask = FPD_GICP_SPI0_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP0], +}; + +static PmRequirement* const pmSpi0Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_SPI0], +}; + +PmSlave pmSlaveSpi0_g = { + .node = { + .derived = &pmSlaveSpi0_g, + .nodeId = NODE_SPI_0, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmSpi0Reqs, + .reqsCnt = ARRAY_SIZE(pmSpi0Reqs), + .wake = &pmSpi0Wake, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmSpi1Wake = { + .proxyIrqMask = FPD_GICP_SPI1_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP0], +}; + +static PmRequirement* const pmSpi1Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_SPI1], +}; + +PmSlave pmSlaveSpi1_g = { + .node = { + .derived = &pmSlaveSpi1_g, + .nodeId = NODE_SPI_1, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmSpi1Reqs, + .reqsCnt = ARRAY_SIZE(pmSpi1Reqs), + .wake = &pmSpi1Wake, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmI2C0Wake = { + .proxyIrqMask = FPD_GICP_I2C0_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP0], +}; + +static PmRequirement* const pmI2C0Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_I2C0], +}; + +PmSlave pmSlaveI2C0_g = { + .node = { + .derived = &pmSlaveI2C0_g, + .nodeId = NODE_I2C_0, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmI2C0Reqs, + .reqsCnt = ARRAY_SIZE(pmI2C0Reqs), + .wake = &pmI2C0Wake, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmI2C1Wake = { + .proxyIrqMask = FPD_GICP_I2C1_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP0], +}; + +static PmRequirement* const pmI2C1Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_I2C1], +}; + +PmSlave pmSlaveI2C1_g = { + .node = { + .derived = &pmSlaveI2C1_g, + .nodeId = NODE_I2C_1, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmI2C1Reqs, + .reqsCnt = ARRAY_SIZE(pmI2C1Reqs), + .wake = &pmI2C1Wake, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmSD0Wake = { + .proxyIrqMask = FPD_GICP_SD0_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP1], +}; + +static PmRequirement* const pmSD0Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_SD0], +}; + +PmSlave pmSlaveSD0_g = { + .node = { + .derived = &pmSlaveSD0_g, + .nodeId = NODE_SD_0, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmSD0Reqs, + .reqsCnt = ARRAY_SIZE(pmSD0Reqs), + .wake = &pmSD0Wake, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmSD1Wake = { + .proxyIrqMask = FPD_GICP_SD1_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP1], +}; + +static PmRequirement* const pmSD1Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_SD1], +}; + +PmSlave pmSlaveSD1_g = { + .node = { + .derived = &pmSlaveSD1_g, + .nodeId = NODE_SD_1, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmSD1Reqs, + .reqsCnt = ARRAY_SIZE(pmSD1Reqs), + .wake = &pmSD1Wake, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmCan0Wake = { + .proxyIrqMask = FPD_GICP_CAN0_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP0], +}; + +static PmRequirement* const pmCan0Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_CAN0], +}; + +PmSlave pmSlaveCan0_g = { + .node = { + .derived = &pmSlaveCan0_g, + .nodeId = NODE_CAN_0, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmCan0Reqs, + .reqsCnt = ARRAY_SIZE(pmCan0Reqs), + .wake = &pmCan0Wake, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmCan1Wake = { + .proxyIrqMask = FPD_GICP_CAN1_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP0], +}; + +static PmRequirement* const pmCan1Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_CAN1], +}; + +PmSlave pmSlaveCan1_g = { + .node = { + .derived = &pmSlaveCan1_g, + .nodeId = NODE_CAN_1, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmCan1Reqs, + .reqsCnt = ARRAY_SIZE(pmCan1Reqs), + .wake = &pmCan1Wake, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmEth0Wake = { + .proxyIrqMask = FPD_GICP_ETH0_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP1], +}; + +static PmRequirement* const pmEth0Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_ETH0], +}; + +PmSlave pmSlaveEth0_g = { + .node = { + .derived = &pmSlaveEth0_g, + .nodeId = NODE_ETH_0, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmEth0Reqs, + .reqsCnt = ARRAY_SIZE(pmEth0Reqs), + .wake = &pmEth0Wake, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmEth1Wake = { + .proxyIrqMask = FPD_GICP_ETH1_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP1], +}; + +static PmRequirement* const pmEth1Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_ETH1], +}; + +PmSlave pmSlaveEth1_g = { + .node = { + .derived = &pmSlaveEth1_g, + .nodeId = NODE_ETH_1, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmEth1Reqs, + .reqsCnt = ARRAY_SIZE(pmEth1Reqs), + .wake = &pmEth1Wake, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmEth2Wake = { + .proxyIrqMask = FPD_GICP_ETH2_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP1], +}; + +static PmRequirement* const pmEth2Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_ETH2], +}; + +PmSlave pmSlaveEth2_g = { + .node = { + .derived = &pmSlaveEth2_g, + .nodeId = NODE_ETH_2, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmEth2Reqs, + .reqsCnt = ARRAY_SIZE(pmEth2Reqs), + .wake = &pmEth2Wake, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmEth3Wake = { + .proxyIrqMask = FPD_GICP_ETH3_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP1], +}; + +static PmRequirement* const pmEth3Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_ETH3], +}; + +PmSlave pmSlaveEth3_g = { + .node = { + .derived = &pmSlaveEth3_g, + .nodeId = NODE_ETH_3, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmEth3Reqs, + .reqsCnt = ARRAY_SIZE(pmEth3Reqs), + .wake = &pmEth3Wake, + .slvFsm = &slaveAonFsm, +}; + +static PmRequirement* const pmAdmaReqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_ADMA], +}; + +PmSlave pmSlaveAdma_g = { + .node = { + .derived = &pmSlaveAdma_g, + .nodeId = NODE_ADMA, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmAdmaReqs, + .reqsCnt = ARRAY_SIZE(pmAdmaReqs), + .wake = NULL, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmNandWake = { + .proxyIrqMask = FPD_GICP_NAND_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP0], +}; + +static PmRequirement* const pmNandReqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_NAND], +}; + +PmSlave pmSlaveNand_g = { + .node = { + .derived = &pmSlaveNand_g, + .nodeId = NODE_NAND, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmNandReqs, + .reqsCnt = ARRAY_SIZE(pmNandReqs), + .wake = &pmNandWake, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmQSpiWake = { + .proxyIrqMask = FPD_GICP_SPI_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP0], +}; + +static PmRequirement* const pmQSpiReqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_QSPI], +}; + +PmSlave pmSlaveQSpi_g = { + .node = { + .derived = &pmSlaveQSpi_g, + .nodeId = NODE_QSPI, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmQSpiReqs, + .reqsCnt = ARRAY_SIZE(pmQSpiReqs), + .wake = &pmQSpiWake, + .slvFsm = &slaveAonFsm, +}; + +static PmWakeProperties pmGpioWake = { + .proxyIrqMask = FPD_GICP_GPIO_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP0], +}; + +static PmRequirement* const pmGpioReqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_GPIO], +}; + +PmSlave pmSlaveGpio_g = { + .node = { + .derived = &pmSlaveGpio_g, + .nodeId = NODE_GPIO, + .typeId = PM_TYPE_SLAVE, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .reqs = pmGpioReqs, + .reqsCnt = ARRAY_SIZE(pmGpioReqs), + .wake = &pmGpioWake, + .slvFsm = &slaveAonFsm, +}; + /* * Standard slave with no private PM properties to be controlled. * It can be powered down with the power parent. @@ -132,3 +637,98 @@ PmSlaveSata pmSlaveSata_g = { .slvFsm = &slaveStdFsm, }, }; + +static PmRequirement* const pmGpuPP0Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_GPUPP0], +}; + +PmSlave pmSlaveGpuPP0_g = { + .node = { + .derived = &pmSlaveGpuPP0_g, + .nodeId = NODE_GPU_PP_0, + .typeId = PM_TYPE_SLAVE, + .parent = &pmPowerDomainFpd_g, + .currState = PM_STD_SLAVE_STATE_ON, + .ops = NULL, + }, + .reqs = pmGpuPP0Reqs, + .reqsCnt = ARRAY_SIZE(pmGpuPP0Reqs), + .wake = NULL, + .slvFsm = &slaveStdFsm, +}; + +static PmRequirement* const pmGpuPP1Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_GPUPP1], +}; + +PmSlave pmSlaveGpuPP1_g = { + .node = { + .derived = &pmSlaveGpuPP1_g, + .nodeId = NODE_GPU_PP_1, + .typeId = PM_TYPE_SLAVE, + .parent = &pmPowerDomainFpd_g, + .currState = PM_STD_SLAVE_STATE_ON, + .ops = NULL, + }, + .reqs = pmGpuPP1Reqs, + .reqsCnt = ARRAY_SIZE(pmGpuPP1Reqs), + .wake = NULL, + .slvFsm = &slaveStdFsm, +}; + +static PmRequirement* const pmGdmaReqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_GDMA], +}; + +PmSlave pmSlaveGdma_g = { + .node = { + .derived = &pmSlaveGdma_g, + .nodeId = NODE_GDMA, + .typeId = PM_TYPE_SLAVE, + .parent = &pmPowerDomainFpd_g, + .currState = PM_STD_SLAVE_STATE_ON, + .ops = NULL, + }, + .reqs = pmGdmaReqs, + .reqsCnt = ARRAY_SIZE(pmGdmaReqs), + .wake = NULL, + .slvFsm = &slaveStdFsm, +}; + +static PmRequirement* const pmDPReqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_DP], +}; + +PmSlave pmSlaveDP_g = { + .node = { + .derived = &pmSlaveDP_g, + .nodeId = NODE_DP, + .typeId = PM_TYPE_SLAVE, + .parent = &pmPowerDomainFpd_g, + .currState = PM_STD_SLAVE_STATE_ON, + .ops = NULL, + }, + .reqs = pmDPReqs, + .reqsCnt = ARRAY_SIZE(pmDPReqs), + .wake = NULL, + .slvFsm = &slaveStdFsm, +}; + +static PmRequirement* const pmAFIReqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_AFI], +}; + +PmSlave pmSlaveAFI_g = { + .node = { + .derived = &pmSlaveAFI_g, + .nodeId = NODE_AFI, + .typeId = PM_TYPE_SLAVE, + .parent = &pmPowerDomainFpd_g, + .currState = PM_STD_SLAVE_STATE_ON, + .ops = NULL, + }, + .reqs = pmAFIReqs, + .reqsCnt = ARRAY_SIZE(pmAFIReqs), + .wake = NULL, + .slvFsm = &slaveStdFsm, +}; diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_periph.h b/lib/sw_apps/zynqmp_pmufw/src/pm_periph.h index 64905392..a291f0fa 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/pm_periph.h +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_periph.h @@ -69,6 +69,32 @@ typedef struct PmSlaveSata { * Global data declarations ********************************************************************/ extern PmSlaveTtc pmSlaveTtc0_g; +extern PmSlaveTtc pmSlaveTtc1_g; +extern PmSlaveTtc pmSlaveTtc2_g; +extern PmSlaveTtc pmSlaveTtc3_g; extern PmSlaveSata pmSlaveSata_g; +extern PmSlave pmSlaveGpuPP0_g; +extern PmSlave pmSlaveGpuPP1_g; +extern PmSlave pmSlaveUart0_g; +extern PmSlave pmSlaveUart1_g; +extern PmSlave pmSlaveSpi0_g; +extern PmSlave pmSlaveSpi1_g; +extern PmSlave pmSlaveI2C0_g; +extern PmSlave pmSlaveI2C1_g; +extern PmSlave pmSlaveSD0_g; +extern PmSlave pmSlaveSD1_g; +extern PmSlave pmSlaveCan0_g; +extern PmSlave pmSlaveCan1_g; +extern PmSlave pmSlaveEth0_g; +extern PmSlave pmSlaveEth1_g; +extern PmSlave pmSlaveEth2_g; +extern PmSlave pmSlaveEth3_g; +extern PmSlave pmSlaveAdma_g; +extern PmSlave pmSlaveGdma_g; +extern PmSlave pmSlaveDP_g; +extern PmSlave pmSlaveNand_g; +extern PmSlave pmSlaveQSpi_g; +extern PmSlave pmSlaveGpio_g; +extern PmSlave pmSlaveAFI_g; #endif diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_power.c b/lib/sw_apps/zynqmp_pmufw/src/pm_power.c index b921417b..bcf75720 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/pm_power.c +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_power.c @@ -232,6 +232,11 @@ static PmNode* pmFpdChildren[] = { &pmSlaveApll_g.slv.node, &pmSlaveVpll_g.slv.node, &pmSlaveDpll_g.slv.node, + &pmSlaveGpuPP0_g.node, + &pmSlaveGpuPP1_g.node, + &pmSlaveGdma_g.node, + &pmSlaveDP_g.node, + &pmSlaveAFI_g.node, }; /* Operations for the Rpu power island */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_slave.c b/lib/sw_apps/zynqmp_pmufw/src/pm_slave.c index 6c129bec..1baf4e3d 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/pm_slave.c +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_slave.c @@ -82,12 +82,38 @@ static PmSlave* const pmSlaves[] = { &pmSlaveUsb0_g.slv, &pmSlaveUsb1_g.slv, &pmSlaveTtc0_g.slv, + &pmSlaveTtc1_g.slv, + &pmSlaveTtc2_g.slv, + &pmSlaveTtc3_g.slv, &pmSlaveSata_g.slv, &pmSlaveApll_g.slv, &pmSlaveVpll_g.slv, &pmSlaveDpll_g.slv, &pmSlaveRpll_g.slv, &pmSlaveIOpll_g.slv, + &pmSlaveGpuPP0_g, + &pmSlaveGpuPP1_g, + &pmSlaveUart0_g, + &pmSlaveUart1_g, + &pmSlaveSpi0_g, + &pmSlaveSpi1_g, + &pmSlaveI2C0_g, + &pmSlaveI2C1_g, + &pmSlaveSD0_g, + &pmSlaveSD1_g, + &pmSlaveCan0_g, + &pmSlaveCan1_g, + &pmSlaveEth0_g, + &pmSlaveEth1_g, + &pmSlaveEth2_g, + &pmSlaveEth3_g, + &pmSlaveAdma_g, + &pmSlaveGdma_g, + &pmSlaveDP_g, + &pmSlaveNand_g, + &pmSlaveQSpi_g, + &pmSlaveGpio_g, + &pmSlaveAFI_g, }; /** diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_slave.h b/lib/sw_apps/zynqmp_pmufw/src/pm_slave.h index b46fea87..83e3a2cf 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/pm_slave.h +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_slave.h @@ -82,9 +82,37 @@ typedef int (*const PmSlaveFsmHandler)(PmSlave* const slave, #define FPD_GICP_PMU_IRQ_GROUP4 0x10U /* FPD GIC Proxy irq masks */ -#define FPD_GICP_USB0_WAKE_IRQ_MASK (1 << 11) + +/* GIC Proxy group 0 */ +#define FPD_GICP_CAN1_WAKE_IRQ_MASK (1 << 24) +#define FPD_GICP_CAN0_WAKE_IRQ_MASK (1 << 23) +#define FPD_GICP_UART1_WAKE_IRQ_MASK (1 << 22) +#define FPD_GICP_UART0_WAKE_IRQ_MASK (1 << 21) +#define FPD_GICP_SPI1_WAKE_IRQ_MASK (1 << 20) +#define FPD_GICP_SPI0_WAKE_IRQ_MASK (1 << 19) +#define FPD_GICP_I2C1_WAKE_IRQ_MASK (1 << 18) +#define FPD_GICP_I2C0_WAKE_IRQ_MASK (1 << 17) +#define FPD_GICP_GPIO_WAKE_IRQ_MASK (1 << 16) +#define FPD_GICP_SPI_WAKE_IRQ_MASK (1 << 15) +#define FPD_GICP_NAND_WAKE_IRQ_MASK (1 << 14) + +/* GIC Proxy group 1 */ +#define FPD_GICP_ETH3_WAKE_IRQ_MASK (1 << 31) +#define FPD_GICP_ETH2_WAKE_IRQ_MASK (1 << 29) +#define FPD_GICP_ETH1_WAKE_IRQ_MASK (1 << 27) +#define FPD_GICP_ETH0_WAKE_IRQ_MASK (1 << 25) +#define FPD_GICP_SD1_WAKE_IRQ_MASK (1 << 19) +#define FPD_GICP_SD0_WAKE_IRQ_MASK (1 << 18) +#define FPD_GICP_TTC3_WAKE_IRQ_MASK (1 << 13) +#define FPD_GICP_TTC2_WAKE_IRQ_MASK (1 << 10) +#define FPD_GICP_TTC1_WAKE_IRQ_MASK (1 << 7) +#define FPD_GICP_TTC0_WAKE_IRQ_MASK (1 << 4) + +/* GIC Proxy group 2 */ #define FPD_GICP_USB1_WAKE_IRQ_MASK (1 << 12) -#define FPD_GICP_TTC0_WAKE_IRQ_MASK (1 << 4) +#define FPD_GICP_USB0_WAKE_IRQ_MASK (1 << 11) + +/* GIC Proxy group 4 */ #define FPD_GICP_SATA_WAKE_IRQ_MASK (1 << 5) /********************************************************************* diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_version.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_version.h index f4f02d54..10be77ee 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/xpfw_version.h +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_version.h @@ -1,4 +1,4 @@ #ifndef ZYNQMP_XPFW_VERSION__H_ #define ZYNQMP_XPFW_VERSION__H_ - #define ZYNQMP_XPFW_VERSION "2015.1-swbeta2-43-g4d76a0be427c" + #define ZYNQMP_XPFW_VERSION "2015.1-swbeta2-44-gae07580d347d" #endif