From 0afca23bffee8c81c671b9725e6b926feb6138b4 Mon Sep 17 00:00:00 2001 From: Andrei-Liviu Simion Date: Wed, 30 Jul 2014 00:17:46 -0700 Subject: [PATCH] dptx: Updated Doxygen documentation. Signed-off-by: Andrei-Liviu Simion --- .../dptx/doc/html/{ => api}/annotated.html | 10 +- .../dptx/doc/html/{ => api}/doxygen.png | Bin .../doc/html/{ => api}/driver_api_doxygen.css | 0 .../dptx/doc/html/{ => api}/files.html | 7 +- .../dptx/doc/html/{ => api}/functions.html | 81 +- .../doc/html/{ => api}/functions_vars.html | 79 +- .../drivers/dptx/doc/html/api/globals.html | 49 + .../dptx/doc/html/api/globals_0x78.html | 737 ++ .../dptx/doc/html/api/globals_defs.html | 601 ++ .../dptx/doc/html/{ => api}/globals_enum.html | 11 +- .../dptx/doc/html/api/globals_eval.html | 140 + .../dptx/doc/html/api/globals_func.html | 80 + .../dptx/doc/html/{ => api}/globals_type.html | 7 +- .../dptx/doc/html/{ => api}/globals_vars.html | 14 +- .../drivers/dptx/doc/html/api/index.html | 61 + .../html/{ => api}/struct_x_dptx-members.html | 2 +- .../doc/html/{ => api}/struct_x_dptx.html | 64 +- ...ruct_x_dptx___aux_transaction-members.html | 4 + .../api/struct_x_dptx___aux_transaction.html | 102 + .../struct_x_dptx___config-members.html | 0 .../{ => api}/struct_x_dptx___config.html | 14 +- .../struct_x_dptx___dmt_mode-members.html | 0 .../{ => api}/struct_x_dptx___dmt_mode.html | 24 +- .../struct_x_dptx___link_config-members.html | 0 .../struct_x_dptx___link_config.html | 22 +- ...dptx___main_stream_attributes-members.html | 50 + ...truct_x_dptx___main_stream_attributes.html | 461 + .../struct_x_dptx___sink_config-members.html | 5 +- .../struct_x_dptx___sink_config.html | 34 +- .../drivers/dptx/doc/html/{ => api}/tab_b.gif | Bin .../drivers/dptx/doc/html/{ => api}/tab_l.gif | Bin .../drivers/dptx/doc/html/{ => api}/tab_r.gif | Bin .../drivers/dptx/doc/html/{ => api}/tabs.css | 0 .../dptx/doc/html/{ => api}/xdptx_8c.html | 255 +- .../dptx/doc/html/{ => api}/xdptx_8h.html | 532 +- .../dptx/doc/html/api/xdptx__hw_8h.html | 9474 +++++++++++++++++ .../doc/html/{ => api}/xdptx__intr_8c.html | 27 +- .../dptx/doc/html/api/xdptx__selftest_8c.html | 132 + .../doc/html/{ => api}/xdptx__sinit_8c.html | 10 +- .../doc/html/{ => api}/xdptx__spm_8c.html | 48 +- .../{ => api}/xdptx__vidmodetable_8c.html | 9 +- .../drivers/dptx/doc/html/globals.html | 365 - .../drivers/dptx/doc/html/globals_defs.html | 328 - .../drivers/dptx/doc/html/globals_func.html | 78 - .../drivers/dptx/doc/html/index.html | 28 - .../html/struct_x_dptx___aux_transaction.html | 32 - ...dptx___main_stream_attributes-members.html | 25 - ...truct_x_dptx___main_stream_attributes.html | 34 - .../drivers/dptx/doc/html/xdptx__hw_8h.html | 4916 --------- .../dptx/doc/html/xdptx__selftest_8c.html | 71 - 50 files changed, 12783 insertions(+), 6240 deletions(-) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/annotated.html (81%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/doxygen.png (100%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/driver_api_doxygen.css (100%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/files.html (83%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/functions.html (53%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/functions_vars.html (53%) create mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals.html create mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_0x78.html create mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_defs.html rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/globals_enum.html (72%) create mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_eval.html create mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_func.html rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/globals_type.html (86%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/globals_vars.html (64%) create mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/api/index.html rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/struct_x_dptx-members.html (96%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/struct_x_dptx.html (78%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/struct_x_dptx___aux_transaction-members.html (51%) create mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___aux_transaction.html rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/struct_x_dptx___config-members.html (100%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/struct_x_dptx___config.html (94%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/struct_x_dptx___dmt_mode-members.html (100%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/struct_x_dptx___dmt_mode.html (90%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/struct_x_dptx___link_config-members.html (100%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/struct_x_dptx___link_config.html (95%) create mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes-members.html create mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes.html rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/struct_x_dptx___sink_config-members.html (78%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/struct_x_dptx___sink_config.html (55%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/tab_b.gif (100%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/tab_l.gif (100%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/tab_r.gif (100%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/tabs.css (100%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/xdptx_8c.html (76%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/xdptx_8h.html (58%) create mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__hw_8h.html rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/xdptx__intr_8c.html (83%) create mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__selftest_8c.html rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/xdptx__sinit_8c.html (91%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/xdptx__spm_8c.html (81%) rename XilinxProcessorIPLib/drivers/dptx/doc/html/{ => api}/xdptx__vidmodetable_8c.html (71%) delete mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/globals.html delete mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/globals_defs.html delete mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/globals_func.html delete mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/index.html delete mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___aux_transaction.html delete mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___main_stream_attributes-members.html delete mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___main_stream_attributes.html delete mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__hw_8h.html delete mode 100644 XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__selftest_8c.html diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/annotated.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/annotated.html similarity index 81% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/annotated.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/annotated.html index 53d0c8d7..fd999aa4 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/annotated.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/annotated.html @@ -2,7 +2,7 @@ - Data Structures + Class List @@ -13,15 +13,15 @@
-

Data Structures

Here are the data structures with brief descriptions: +

Class List

Here are the classes, structs, unions and interfaces with brief descriptions:
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/doxygen.png b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/doxygen.png similarity index 100% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/doxygen.png rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/doxygen.png diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/driver_api_doxygen.css b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/driver_api_doxygen.css similarity index 100% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/driver_api_doxygen.css rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/driver_api_doxygen.css diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/files.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/files.html similarity index 83% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/files.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/files.html index 0a45029a..e1583d6a 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/files.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/files.html @@ -13,16 +13,17 @@
-

File List

Here is a list of all documented files with brief descriptions:
XDptx
XDptx_AuxTransaction
XDptx_Config
+

File List

Here is a list of all files with brief descriptions:
+ diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/functions.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html similarity index 53% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/functions.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html index 83759396..1f9a8d71 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/functions.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html @@ -2,7 +2,7 @@ - Data Fields + Class Members @@ -13,13 +13,13 @@
    @@ -29,6 +29,7 @@
    +
  • a
  • b
  • c
  • d
    • @@ -37,6 +38,7 @@
  • i
  • l
  • m
    • +
  • n
  • p
  • q
  • r
    • @@ -49,40 +51,53 @@

-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +Here is a list of all class members with links to the classes they belong to:

+

- a -

- b -

+: XDptx_Config
  • BitsPerColor +: XDptx_MainStreamAttributes

    - c -

    +
  • CmdCode +: XDptx_AuxTransaction
  • ComponentFormat +: XDptx_LinkConfig
  • Config +: XDptx

    - d -

    - e -

    - h -

    +: XDptx_MainStreamAttributes, XDptx_DmtMode
  • HStart +: XDptx_MainStreamAttributes
  • HSyncPolarity +: XDptx_MainStreamAttributes, XDptx_DmtMode
  • HSyncPulseWidth +: XDptx_MainStreamAttributes, XDptx_DmtMode

    - i -

    - l -

    +: XDptx_LinkConfig, XDptx_Config
  • Misc0 +: XDptx_MainStreamAttributes
  • Misc1 +: XDptx_MainStreamAttributes
  • MsaConfig +: XDptx
  • MVid +: XDptx_MainStreamAttributes +

    - n -

    - p -

    - t -

    +: XDptx
  • TransferUnitSize +: XDptx_MainStreamAttributes

    - u -

    - v -

    +: XDptx_MainStreamAttributes, XDptx_DmtMode
  • VsLevel +: XDptx_LinkConfig
  • VStart +: XDptx_MainStreamAttributes
  • VSyncPolarity +: XDptx_MainStreamAttributes, XDptx_DmtMode
  • VSyncPulseWidth +: XDptx_MainStreamAttributes, XDptx_DmtMode

    - y -

    - d -

    - e -

    - h -

    +: XDptx_MainStreamAttributes, XDptx_DmtMode
  • HStart +: XDptx_MainStreamAttributes
  • HSyncPolarity +: XDptx_MainStreamAttributes, XDptx_DmtMode
  • HSyncPulseWidth +: XDptx_MainStreamAttributes, XDptx_DmtMode

    - i -

    - l -

    +: XDptx_LinkConfig, XDptx_Config
  • Misc0 +: XDptx_MainStreamAttributes
  • Misc1 +: XDptx_MainStreamAttributes
  • MsaConfig +: XDptx
  • MVid +: XDptx_MainStreamAttributes +

    - n -

    - p -

    - t -

    +: XDptx
  • TransferUnitSize +: XDptx_MainStreamAttributes

    - u -

    - v -

    +: XDptx_MainStreamAttributes, XDptx_DmtMode
  • VsLevel +: XDptx_LinkConfig
  • VStart +: XDptx_MainStreamAttributes
  • VSyncPolarity +: XDptx_MainStreamAttributes, XDptx_DmtMode
  • VSyncPulseWidth +: XDptx_MainStreamAttributes, XDptx_DmtMode

    - y -

    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_eval.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_eval.html new file mode 100644 index 00000000..7ea55eb3 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_eval.html @@ -0,0 +1,140 @@ + + + + + Class Members + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + +
    +
    +
    +
    +
    + +
    +
    +
      +
    • x
      • +
    +
    + +

    +  +

    +

    - x -

    +Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_func.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_func.html new file mode 100644 index 00000000..c54e8f77 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_func.html @@ -0,0 +1,80 @@ + + + + + Class Members + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + +
    +
    +
    +
    +
    + +
    +
    +
      +
    • x
      • +
    +
    + +

    +  +

    +

    - x -

    +Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_type.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_type.html similarity index 86% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/globals_type.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_type.html index 02022fc0..76b81fbb 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_type.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_type.html @@ -2,7 +2,7 @@ - Data Fields + Class Members @@ -13,13 +13,13 @@
    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_vars.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_vars.html similarity index 64% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/globals_vars.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_vars.html index c341087b..87d2917c 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_vars.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/globals_vars.html @@ -2,7 +2,7 @@ - Data Fields + Class Members @@ -13,27 +13,31 @@
     

    +: xdptx_vidmodetable.c, xdptx.h Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/index.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/index.html new file mode 100644 index 00000000..02c4c4c0 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/index.html @@ -0,0 +1,61 @@ + + + + + dptx v1_0 + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + +
    +
    +

    dptx v1_0

    +

    +The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the Xilinx DisplayPort soft IP core in source (TX) mode. This driver follows the DisplayPort 1.2a specification.

    +The Xilinx DisplayPort soft IP supports the following features:

      +
    • 1, 2, or 4 lanes.
    • A link rate of 1.62, 2.70, or 5.40Gbps per lane.
    • 1, 2, or 4 pixel-wide video interfaces.
    • RGB and YCbCr color space.
    • Up to 16 bits per component.
    • Up to 4Kx2K monitor resolution.
    • Auto lane rate and width negotiation.
    • I2C over a 1Mb/s AUX channel.
    • Secondary channel audio support (2 channels).
    • 4 independent video multi-streams.
    +

    +The Xilinx DisplayPort soft IP does not support the following features:

      +
    • The automated test feature.
    • Audio (3-8 channel).
    • FAUX.
    • Bridging function.
    • MST audio.
    • eDP optional features.
    • iDP.
    • GTC.
    +

    +DisplayPort overview

    +A DisplayPort link consists of:

      +
    • A unidirectional main link which is used to transport isochronous data streams such as video and audio. The main link may use 1, 2, or 4 lanes at a link rate of 1.62, 2.70, or 5.40Gbps per lane. The link needs to be trained prior to sending streams.
    • An auxiliary (AUX) channel is a 1MBps bidirectional channel used for link training, link management, and device control.
    • A hot-plug-detect (HPD) signal line is used to determine whether a DisplayPort connection exists between the DisplayPort TX connector and an RX device. It is serves as an interrupt request by the RX device.
    +

    +Driver description

    +The device driver enables higher-level software (e.g., an application) to configure and control a DisplayPort TX soft IP, communicate and control an RX device/sink monitor over the AUX channel, and to initialize and transmit data streams over the main link.

    +This driver implements link layer functionality: a Link Policy Maker (LPM) and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification.

      +
    • The LPM manages the main link and is responsible for keeping the link synchronized. It will establish a link with a downstream RX device by undergoing a link training sequence which consists of:
        +
      • Clock recovery: The clock needs to be recovered and PLLs need to be locked for all lanes.
      • Channel equalization: All lanes need to achieve channel equalization and and symbol lock, as well as for interlane alignment to take place.
      +
    • The SPM manages transportation of an isochronous stream. That is, it will initialize and maintain a video stream, establish a virtual channel to a sink monitor, and transmit the stream.
    +

    +Using AUX transactions to read/write from/to the sink's DisplayPort Configuration Data (DPCD) address space, the LPM obtains the link capabilities, obtains link configuration and link and sink status, and configures and controls the link and sink. The main link is trained this way.

    +I2C-over-AUX transactions are used to obtain the sink's Extended Display Identification Data (EDID) which give information on the display capabilities of the monitor. The SPM may use this information to determine what available screen resolutions and video timing are possible.

    +Device configuration

    +The device can be configured in various ways during the FPGA implementation process. Configuration parameters are stored in the xdptx_g.c file which is generated when compiling the board support package (BSP). A table is defined where each entry contains configuration information for the DisplayPort instances present in the system. This information includes parameters that are defined in the driver's data/dptx.tcl file such as the base address of the memory-mapped device and the maximum number of lanes, maximum link rate, and video interface that the DisplayPort instance supports, among others.

    +Interrupt processing

    +DisplayPort interrupts occur on the HPD signal line when the DisplayPort cable is connected/disconnected or when the RX device sends a pulse. The user hardware design must contain an interrupt controller which the DisplayPort TX instance's interrupt signal is connected to. The user application must enable interrupts in the system and set up the interrupt controller such that the XDptx_HpdInterruptHandler handler will service DisplayPort interrupts. When the XDptx_HpdInterruptHandler function is invoked, the handler will identify what type of DisplayPort interrupt has occurred, and will call either the HPD event handler function or the HPD pulse handler function, depending on whether a an HPD event on an HPD pulse event occurred.

    +The DisplayPort Tx's XDPTX_INTERRUPT_STATUS register indicates the type of interrupt that has occured, and the XDptx_HpdInterruptHandler will use this information to decide which handler to call. An HPD event is identified if bit XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is identified from the XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit.

    +The HPD event handler may be set up by using the XDptx_SetHpdEventHandler function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler function.

    +Audio

    +The driver does not handle audio. For an example as to how to configure and transmit audio, dptx/examples/xdptx_audio_example.c illustrates the required sequence. The user will need to configure the audio source connected to the Displayport TX instance and set up the audio info frame as per user requirements.

    +Asserts

    +Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.

    +Limitations

    +

      +
    • The driver currently supports single-stream transport (SST) functionality.
    • The driver does not handle audio. See the audio example in the driver examples directory for the required sequence for enabling audio.
    +

    +

    Note:
    For a 5.4Gbps link rate, a high performance 7 series FPGA is required with a speed grade of -2 or -3.
    +
    + MODIFICATION HISTORY:

    +

     Ver   Who  Date     Changes
+ ----- ---- -------- -----------------------------------------------
+ 1.00a als  05/17/14 Initial release.
+
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx-members.html similarity index 96% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx-members.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx-members.html index 4e36e4c9..8561abb9 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx-members.html @@ -22,6 +22,7 @@
  • Class Members

    • XDptx Member List

    This is the complete list of members for XDptx, including all inherited members.

    xdptx.c
    xdptx.h
    xdptx_hw.h
    xdptx_intr.c
    xdptx_selftest.c
    + @@ -32,7 +33,6 @@ -
    ConfigXDptx
    HasRedriverInPathXDptx
    HpdEventCallbackRefXDptx
    HpdEventHandlerXDptx
    MsaConfigXDptx
    RxConfigXDptx
    TrainAdaptiveXDptx
    TxConfigXDptx
    UserTimerPtrXDptx
    UserTimerWaitUsXDptx
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx.html similarity index 78% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx.html index cda60e73..b4473a98 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx.html @@ -13,29 +13,29 @@

    XDptx Struct Reference

    #include <xdptx.h>

    -

    Detailed Description

    +List of all members.

    Detailed Description

    The XDptx driver instance data. The user is required to allocate a variable of this type for every XDptx device in the system. A pointer to a variable of this type is then passed to the driver API functions.

    - + - + @@ -43,20 +43,35 @@ The XDptx driver instance data. The - + - + - +

    Data Fields


    Public Attributes

    u32 IsReady
    u8 TrainAdaptive
    u8 HasRedriverInPath
    XDptx_Config TxConfig
    XDptx_Config Config
    XDptx_SinkConfig RxConfig
    XDptx_MainStreamAttributes MsaConfig
    XDptx_TimerHandler UserTimerWaitUs
    XDptx_TimerHandler UserTimerWaitUs
    void * UserTimerPtr
    XDptx_HpdEventHandler HpdEventHandler
    XDptx_HpdEventHandler HpdEventHandler
    void * HpdEventCallbackRef
    XDptx_HpdPulseHandler HpdPulseHandler
    XDptx_HpdPulseHandler HpdPulseHandler
    void * HpdPulseCallbackRef
    -

    Field Documentation

    +

    Member Data Documentation

    + +
    +
    + + + + +
    XDptx_Config XDptx::Config
    +
    +
    + +

    +Configuration structure for the DisplayPort TX core. +

    +

    @@ -92,14 +107,14 @@ A pointer to the user data passed to the HPD event callback function.
    - +
    XDptx_HpdEventHandler XDptx::HpdEventHandler XDptx_HpdEventHandler XDptx::HpdEventHandler

    -Callback function for hot- plug-detect event interrupts. +Callback function for Hot- Plug-Detect (HPD) event interrupts.

    @@ -122,14 +137,14 @@ A pointer to the user data passed to the HPD pulse callback function.

    - +
    XDptx_HpdPulseHandler XDptx::HpdPulseHandler XDptx_HpdPulseHandler XDptx::HpdPulseHandler

    -Callback function for hot- plug-detect pulse interrupts. +Callback function for Hot- Plug-Detect (HPD) pulse interrupts.

    @@ -189,7 +204,7 @@ Configuration structure for the main stream attributes.

    -Configuration structure for the sink. +Configuration structure for the RX device.

    @@ -207,21 +222,6 @@ Configuration structure for the sink. Downshift lane count and link rate if necessary during training.

    - -

    -
    - - - - -
    XDptx_Config XDptx::TxConfig
    -
    -
    - -

    -Configuration structure for the core. -

    -

    @@ -242,7 +242,7 @@ Pointer to a timer instance used by the custom user delay/sleep function.
    - +
    XDptx_TimerHandler XDptx::UserTimerWaitUs XDptx_TimerHandler XDptx::UserTimerWaitUs
    @@ -253,5 +253,5 @@ Custom user function for delay/sleep.

    The documentation for this struct was generated from the following file: +
  • xdptx.h Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___aux_transaction-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___aux_transaction-members.html similarity index 51% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___aux_transaction-members.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___aux_transaction-members.html index fe1a190e..ea452700 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___aux_transaction-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___aux_transaction-members.html @@ -22,4 +22,8 @@
  • Class Members

    • XDptx_AuxTransaction Member List

    This is the complete list of members for XDptx_AuxTransaction, including all inherited members.

    + + + +
    AddressXDptx_AuxTransaction
    CmdCodeXDptx_AuxTransaction
    DataXDptx_AuxTransaction
    NumBytesXDptx_AuxTransaction
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___aux_transaction.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___aux_transaction.html new file mode 100644 index 00000000..49053a19 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___aux_transaction.html @@ -0,0 +1,102 @@ + + + + + XDptx_AuxTransaction Struct Reference + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + +
    +
    +
    +
    +

    XDptx_AuxTransaction Struct Reference

    List of all members.

    Detailed Description

    +This typedef describes an AUX transaction. +

    + + + + + + + + + + + +

    Public Attributes

    u16 CmdCode
    u8 NumBytes
    u32 Address
    u8 * Data
    +

    Member Data Documentation

    + +
    +
    + + + + +
    u32 XDptx_AuxTransaction::Address
    +
    +
    + +

    +The AUX or I2C start address that the AUX transaction will perform work on. +

    +

    + +

    +
    + + + + +
    u16 XDptx_AuxTransaction::CmdCode
    +
    +
    + +

    +The AUX command code that specifies what type of AUX transaction is taking place. +

    +

    + +

    +
    + + + + +
    u8* XDptx_AuxTransaction::Data
    +
    +
    + +

    +The data buffer that will store the data read from AUX read transactions or the data to write for AUX write transactions. +

    +

    + +

    +
    + + + + +
    u8 XDptx_AuxTransaction::NumBytes
    +
    +
    + +

    +The number of bytes that the AUX transaction will perform work on. +

    +

    +

    The documentation for this struct was generated from the following file: +Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___config-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config-members.html similarity index 100% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___config-members.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config-members.html diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___config.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config.html similarity index 94% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___config.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config.html index 4ffe0721..3b01100b 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___config.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config.html @@ -13,22 +13,22 @@

    XDptx_Config Struct Reference

    #include <xdptx.h>

    -

    Detailed Description

    +List of all members.

    Detailed Description

    This typedef contains configuration information for the DisplayPort TX core.

    - + @@ -50,7 +50,7 @@ This typedef contains configuration information for the DisplayPort TX core.

    Data Fields


    Public Attributes

    u16 DeviceId
    u32 BaseAddr
    u8 YCrCbEn
    -

    Field Documentation

    +

    Member Data Documentation

    @@ -202,5 +202,5 @@ YOnly format support by this core's instance.

    The documentation for this struct was generated from the following file: +
  • xdptx.h Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___dmt_mode-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___dmt_mode-members.html similarity index 100% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___dmt_mode-members.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___dmt_mode-members.html diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___dmt_mode.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___dmt_mode.html similarity index 90% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___dmt_mode.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___dmt_mode.html index be7bfb71..4bf6452c 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___dmt_mode.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___dmt_mode.html @@ -13,23 +13,23 @@

    XDptx_DmtMode Struct Reference

    #include <xdptx.h>

    -

    Detailed Description

    +List of all members.

    Detailed Description

    This typedef contains the display monitor timing attributes for a video mode.

    - - + + @@ -58,7 +58,7 @@ This typedef contains the display monitor timing attributes for a video mode.

    Data Fields

    XDptx_VideoMode VideoMode

    Public Attributes

    XDptx_VideoMode VideoMode
    u8 DmtId
    u32 VBackPorch
    -

    Field Documentation

    +

    Member Data Documentation

    @@ -71,7 +71,7 @@ This typedef contains the display monitor timing attributes for a video mode.

    -Standard DMT ID number. +Standard Display Monitor Timing (DMT) ID number.

    @@ -131,7 +131,7 @@ Horizontal resolution.

    -Horizontal polarity. +Horizontal synchronization polarity.

    @@ -214,7 +214,7 @@ Vertical front porch.

    - +
    XDptx_VideoMode XDptx_DmtMode::VideoMode XDptx_VideoMode XDptx_DmtMode::VideoMode
    @@ -251,7 +251,7 @@ Vertical resolution.

    -Vertical polarity. +Vertical synchronization polarity.

    @@ -270,5 +270,5 @@ Vertical synchronization pulse width.

    The documentation for this struct was generated from the following file:
      -
    • xdptx.h
    +
  • xdptx.h Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___link_config-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___link_config-members.html similarity index 100% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___link_config-members.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___link_config-members.html diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___link_config.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___link_config.html similarity index 95% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___link_config.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___link_config.html index 59f4d1d8..93769315 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___link_config.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___link_config.html @@ -13,22 +13,22 @@

    XDptx_LinkConfig Struct Reference

    #include <xdptx.h>

    -

    Detailed Description

    +List of all members.

    Detailed Description

    This typedef contains configuration information about the main link settings.

    - + @@ -62,7 +62,7 @@ This typedef contains configuration information about the main link settings.

    Data Fields


    Public Attributes

    u8 LaneCount
    u8 LinkRate
    u8 Pattern
    -

    Field Documentation

    +

    Member Data Documentation

    @@ -165,7 +165,7 @@ The current link rate of the main link.

    -The maximum lane count of the source-sink main link. +The maximum lane count of the main link.

    @@ -180,7 +180,7 @@ The maximum lane count of the source-sink main link.

    -The maximum link rate of the source-sink main link. +The maximum link rate of the main link.

    @@ -240,7 +240,7 @@ Symbol scrambling is currently in use over the main link.

    -Downspread control is supported by the receiver. +Downspread control is supported by the RX device.

    @@ -255,7 +255,7 @@ Downspread control is supported by the receiver.

    -Enhanced frame mode is supported by the receiver. +Enhanced frame mode is supported by the RX device.

    @@ -304,5 +304,5 @@ The YCbCr colorimetry currently in use over the main link.

    The documentation for this struct was generated from the following file:
      -
    • xdptx.h
    +
  • xdptx.h Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes-members.html new file mode 100644 index 00000000..08c15b64 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes-members.html @@ -0,0 +1,50 @@ + + + + + Member List + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + +
    +
    +
    +
    +

    XDptx_MainStreamAttributes Member List

    This is the complete list of members for XDptx_MainStreamAttributes, including all inherited members.

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    AvgBytesPerTUXDptx_MainStreamAttributes
    BitsPerColorXDptx_MainStreamAttributes
    DataPerLaneXDptx_MainStreamAttributes
    HBackPorchXDptx_MainStreamAttributes
    HClkTotalXDptx_MainStreamAttributes
    HFrontPorchXDptx_MainStreamAttributes
    HResolutionXDptx_MainStreamAttributes
    HStartXDptx_MainStreamAttributes
    HSyncPolarityXDptx_MainStreamAttributes
    HSyncPulseWidthXDptx_MainStreamAttributes
    InitWaitXDptx_MainStreamAttributes
    InterlacedXDptx_MainStreamAttributes
    Misc0XDptx_MainStreamAttributes
    Misc1XDptx_MainStreamAttributes
    MVidXDptx_MainStreamAttributes
    NVidXDptx_MainStreamAttributes
    TransferUnitSizeXDptx_MainStreamAttributes
    UserPixelWidthXDptx_MainStreamAttributes
    VBackPorchXDptx_MainStreamAttributes
    VClkTotalXDptx_MainStreamAttributes
    VFrontPorchXDptx_MainStreamAttributes
    VResolutionXDptx_MainStreamAttributes
    VStartXDptx_MainStreamAttributes
    VSyncPolarityXDptx_MainStreamAttributes
    VSyncPulseWidthXDptx_MainStreamAttributes
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes.html new file mode 100644 index 00000000..a2093af0 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes.html @@ -0,0 +1,461 @@ + + + + + XDptx_MainStreamAttributes Struct Reference + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + +
    +
    +
    +
    +

    XDptx_MainStreamAttributes Struct Reference

    #include <xdptx.h> +

    +List of all members.

    Detailed Description

    +This typedef contains the main stream attributes which determine how the video will be displayed. +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    Public Attributes

    u32 HClkTotal
    u32 VClkTotal
    u32 HSyncPulseWidth
    u32 VSyncPulseWidth
    u32 HResolution
    u32 VResolution
    u32 HSyncPolarity
    u32 VSyncPolarity
    u32 HStart
    u32 VStart
    u32 VBackPorch
    u32 VFrontPorch
    u32 HBackPorch
    u32 HFrontPorch
    u32 Misc0
    u32 Misc1
    u32 MVid
    u32 NVid
    u32 TransferUnitSize
    u32 UserPixelWidth
    u32 DataPerLane
    u32 AvgBytesPerTU
    u32 InitWait
    u32 Interlaced
    u32 BitsPerColor
    +

    Member Data Documentation

    + +
    +
    + + + + +
    u32 XDptx_MainStreamAttributes::AvgBytesPerTU
    +
    +
    + +

    +Average number of bytes per transfer unit, scaled up by a factor of 1000. +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::BitsPerColor
    +
    +
    + +

    +Number of bits per color component. +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::DataPerLane
    +
    +
    + +

    +Used to translate the number of pixels per line to the native internal 16-bit datapath. +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::HBackPorch
    +
    +
    + +

    +Horizontal back porch (in pixels). +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::HClkTotal
    +
    +
    + +

    +Horizontal total time (in pixels). +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::HFrontPorch
    +
    +
    + +

    +Horizontal front porch (in pixels). +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::HResolution
    +
    +
    + +

    +Horizontal resolution (in pixels). +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::HStart
    +
    +
    + +

    +Horizontal blank start (in pixels). +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::HSyncPolarity
    +
    +
    + +

    +Horizontal synchronization polarity (0=positive/1=negative). +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::HSyncPulseWidth
    +
    +
    + +

    +Horizontal synchronization time (in pixels). +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::InitWait
    +
    +
    + +

    +Number of initial wait cycles at the start of a new line by the framing logic. +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::Interlaced
    +
    +
    + +

    +Input stream is interlaced. +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::Misc0
    +
    +
    + +

    +Miscellaneous stream attributes 0 as specified by the DisplayPort 1.2 specification. +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::Misc1
    +
    +
    + +

    +Miscellaneous stream attributes 1 as specified by the DisplayPort 1.2 specification. +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::MVid
    +
    +
    + +

    +M value for the video stream. This value is equal to the pixel clock in KHz. +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::NVid
    +
    +
    + +

    +N value for the video stream. +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::TransferUnitSize
    +
    +
    + +

    +Size of the transfer unit in the framing logic. +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::UserPixelWidth
    +
    +
    + +

    +The width of the user data input port. +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::VBackPorch
    +
    +
    + +

    +Vertical back porch (in lines). +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::VClkTotal
    +
    +
    + +

    +Vertical total time (in pixels). +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::VFrontPorch
    +
    +
    + +

    +Vertical front porch (in lines). +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::VResolution
    +
    +
    + +

    +Vertical resolution (in lines). +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::VStart
    +
    +
    + +

    +Vertical blank start (in lines). +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::VSyncPolarity
    +
    +
    + +

    +Vertical synchronization polarity (0=positive/1=negative). +

    +

    + +

    +
    + + + + +
    u32 XDptx_MainStreamAttributes::VSyncPulseWidth
    +
    +
    + +

    +Vertical synchronization time (in lines +

    +

    +

    The documentation for this struct was generated from the following file: +Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___sink_config-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sink_config-members.html similarity index 78% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___sink_config-members.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sink_config-members.html index 7741d4b9..e55281c0 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___sink_config-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sink_config-members.html @@ -22,6 +22,7 @@
  • Class Members

    • XDptx_SinkConfig Member List

    This is the complete list of members for XDptx_SinkConfig, including all inherited members.

    - - + + +
    DpcdRxCapsFieldXDptx_SinkConfig
    EdidXDptx_SinkConfig
    DpcdRxCapsFieldXDptx_SinkConfig
    EdidXDptx_SinkConfig
    LaneStatusAdjReqsXDptx_SinkConfig
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___sink_config.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sink_config.html similarity index 55% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___sink_config.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sink_config.html index 293121e8..3091b5e4 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___sink_config.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___sink_config.html @@ -13,58 +13,58 @@

    XDptx_SinkConfig Struct Reference

    #include <xdptx.h>

    -

    Detailed Description

    -This typedef contains configuration information about the sink. +List of all members.

    Detailed Description

    +This typedef contains configuration information about the RX device.

    - - + + - +

    Data Fields

    u8 DpcdRxCapsField [256]

    Public Attributes

    u8 DpcdRxCapsField [XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE]
    u8 Edid [128]
    u8 Edid [XDPTX_EDID_SIZE]
    u8 LaneStatusAdjReqs [6]
    -

    Field Documentation

    - +

    Member Data Documentation

    +
    - +
    u8 XDptx_SinkConfig::DpcdRxCapsField[256] u8 XDptx_SinkConfig::DpcdRxCapsField[XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE]

    -The raw capabilities field of the sink's DPCD. +The raw capabilities field of the RX device's DisplayPort Configuration Data (DPCD).

    - +

    - +
    u8 XDptx_SinkConfig::Edid[128] u8 XDptx_SinkConfig::Edid[XDPTX_EDID_SIZE]

    -The sink's raw EDID. +The RX device's raw Extended Display Identification Data (EDID).

    @@ -79,9 +79,9 @@ The sink's raw EDID.

    -This is a raw read of the receiver DPCD's status registers. The first 4 bytes correspond to the lane status from the receiver's DPCD associated with clock recovery, channel equalization, symbol lock, and interlane alignment. The 2 remaining bytes represent the adjustments requested by the DPCD. +This is a raw read of the RX device's status registers. The first 4 bytes correspond to the lane status associated with clock recovery, channel equalization, symbol lock, and interlane alignment. The remaining 2 bytes represent the pre-emphasis and voltage swing level adjustments requested by the RX device.

    The documentation for this struct was generated from the following file: +
  • xdptx.h Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/tab_b.gif b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/tab_b.gif similarity index 100% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/tab_b.gif rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/tab_b.gif diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/tab_l.gif b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/tab_l.gif similarity index 100% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/tab_l.gif rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/tab_l.gif diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/tab_r.gif b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/tab_r.gif similarity index 100% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/tab_r.gif rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/tab_r.gif diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/tabs.css b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/tabs.css similarity index 100% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/tabs.css rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/tabs.css diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8c.html similarity index 76% rename from XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx_8c.html rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8c.html index 3031b35e..b04f01bd 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx_8c.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8c.html @@ -13,16 +13,17 @@

    xdptx.c File Reference

    Detailed Description

    -Contains a minimal wset of functions for the XDptx driver that allow access to all the DisplayPort transmitter's functionality. See xdptx.h for a detailed description of the driver.

    +Contains a minimal set of functions for the XDptx driver that allow access to all of the DisplayPort TX core's functionality. See xdptx.h for a detailed description of the driver.

    +

    Note:
    None.
      MODIFICATION HISTORY:

     Ver   Who  Date     Changes
@@ -30,23 +31,41 @@ Contains a minimal wset of functions for the xdptx.h"
    
 #include "xstatus.h"
    
 #include "xenv.h"
    
 
-
+
 
+
+
+
+
+
+
+
+
+
 
-
+
 
-
+
 
@@ -64,9 +83,9 @@ Contains a minimal wset of functions for the u32 
 
-
+
 
-
+
 
@@ -84,11 +103,72 @@ Contains a minimal wset of functions for the void 
 
-
+
    
 

    Data Structures

    Classes
    
 
    struct  XDptx_AuxTransaction

    Defines
    #define XDPTX_MAXIMUM_VS_LEVEL   3
    #define XDPTX_MAXIMUM_PE_LEVEL   3
    #define XDPTX_AUX_MAX_DEFER_COUNT   50
    #define XDPTX_AUX_MAX_TIMEOUT_COUNT   50

    Enumerations
    enum  XDptx_TrainingState 
    enum  XDptx_TrainingState { 
    
+  XDPTX_TS_CLOCK_RECOVERY, 
+XDPTX_TS_CHANNEL_EQUALIZATION, 
+XDPTX_TS_ADJUST_LINK_RATE, 
+XDPTX_TS_ADJUST_LANE_COUNT, 
+
    
+  XDPTX_TS_FAILURE, 
+XDPTX_TS_SUCCESS
+
    
+ }
    
 
 

    Functions
    
 
    u32 XDptx_InitializeTx (XDptx *InstancePtr)
    
 
 
    void XDptx_CfgInitialize (XDptx *InstancePtr, XDptx_Config *ConfigPtr, u32 EffectiveAddr)
    u32 XDptx_GetSinkCapabilities (XDptx *InstancePtr)
    u32 XDptx_GetRxCapabilities (XDptx *InstancePtr)
    
 
 
    u32 XDptx_GetEdid (XDptx *InstancePtr)
    XDptx_AuxWrite (XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data)
    u32 XDptx_IicWrite (XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, u8 NumBytes, u8 *DataBuffer)
    u32 XDptx_IicRead (XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, u8 NumBytes, void *Data)
    u32 XDptx_IicRead (XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, u8 NumBytes, u8 *DataBuffer)
    u32 XDptx_IicWrite (XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, u8 NumBytes, void *Data)
    
 
 
    u32 XDptx_SetDownspread (XDptx *InstancePtr, u8 Enable)
    XDptx_ResetPhy (XDptx *InstancePtr, u32 Reset)
    void XDptx_SetUserTimerHandler (XDptx *InstancePtr, XDptx_TimerHandler CallbackFunc, void *CallbackRef)
    void XDptx_SetUserTimerHandler (XDptx *InstancePtr, XDptx_TimerHandler CallbackFunc, void *CallbackRef)
    
 
 
    void XDptx_WaitUs (XDptx *InstancePtr, u32 MicroSeconds)
    
 
 
    
+
    Define Documentation
    
+    
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_MAX_DEFER_COUNT   50          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_MAX_TIMEOUT_COUNT   50          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAXIMUM_PE_LEVEL   3          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAXIMUM_VS_LEVEL   3          
    
+
    
+
    
+
+
    
+
+
    
+
    
 
    Enumeration Type Documentation
    
 
 
    
@@ -102,7 +182,23 @@ Contains a minimal wset of functions for the 
 
 
    
-This typedef enumerates the list of training states used in the state machine during the link training process. 
+This typedef enumerates the list of training states used in the state machine during the link training process. 
    Enumerator: 
    
+
+
+
+
+
+
+
+
    XDPTX_TS_CLOCK_RECOVERY 
+
    XDPTX_TS_CHANNEL_EQUALIZATION 
+
    XDPTX_TS_ADJUST_LINK_RATE 
+
    XDPTX_TS_ADJUST_LANE_COUNT 
+
    XDPTX_TS_FAILURE 
+
    XDPTX_TS_SUCCESS 
+
    
+
    
+
 
    
 
    
 
    Function Documentation
    
@@ -148,14 +244,15 @@ This function issues a read request over the AUX channel.
    
 
    Parameters:
    
   
-    
-    
+    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    Address is the starting address to read from the receiver. 
    NumBytes is the number of bytes to read from the receiver. 
    Address is the starting address to read from the RX device. 
    NumBytes is the number of bytes to read from the RX device. 
    
     
    Data is a pointer to the data buffer that will be filled with read data.
    
   
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if the AUX read request was successfully acknowledged.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_NO_DATA if no data was provided.
    • XST_ERROR_COUNT_MAX if the AUX request timed out.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if the AUX read request was successfully acknowledged.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
 
    
@@ -201,14 +298,15 @@ This function issues a write request over the AUX channel.
    
 
    Parameters:
    
   
-    
-    
-    
+    
+    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    Address is the starting address to write to the receiver. 
    NumBytes is the number of bytes to write to the receiver. 
    Data is a pointer to the data buffer that contains the data to be written to the receiver.
    Address is the starting address to write to the RX device. 
    NumBytes is the number of bytes to write to the RX device. 
    Data is a pointer to the data buffer that contains the data to be written to the RX device.
    
   
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if AUX write request was successfully acknowledged.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_NO_DATA if no data was provided.
    • XST_ERROR_COUNT_MAX if the AUX request timed out.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if AUX write request was successfully acknowledged.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
 
    
@@ -244,7 +342,7 @@ This function issues a write request over the AUX channel.
    
 
    
 
 
    
-This function retrieves the configuration for this DisplayPort TX instance and fills in the InstancePtr->TxConfig structure.
    
+This function retrieves the configuration for this DisplayPort TX instance and fills in the InstancePtr->Config structure.
    
 
    Parameters:
    
   
@@ -252,6 +350,7 @@ This function retrieves the configuration for this DisplayPort TX instance and f
     
    
     
    InstancePtr is a pointer to the XDptx instance. 
    EffectiveAddr is the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed.
    
   
    
 
    
+
    Returns:
    None.
    
 
    Note:
    Unexpected errors may occur if the address mapping is changed after this function is invoked. 
    
 
 
    
@@ -273,15 +372,16 @@ This function retrieves the configuration for this DisplayPort TX instance and f
 
    
 
 
    
-This function determines the common capabilities between the DisplayPort TX core and the receiver.
    
+This function determines the common capabilities between the DisplayPort TX core and the RX device.
    
 
    Parameters:
    
   
    
     
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if main link settings were successfully set.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_INVALID_PARAM if the specified link configuration specifies a link rate or lane count that isn't valid.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if main link settings were successfully set.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -311,7 +411,7 @@ This function determines the common capabilities between the DisplayPort TX core
 
    
 
 
    
-This function checks if the reciever's DPCD indicates the reciever has achieved and maintained clock recovery, channel equalization, symbol lock, and interlane alignment for all lanes currently in use.
    
+This function checks if the reciever's DisplayPort Configuration Data (DPCD) indicates the reciever has achieved and maintained clock recovery, channel equalization, symbol lock, and interlane alignment for all lanes currently in use.
    
 
    Parameters:
    
   
@@ -319,8 +419,9 @@ This function checks if the reciever's DPCD indicates the reciever has achieved
   
    
     
    InstancePtr is a pointer to the XDptx instance. 
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if the receiver has maintained clock recovery, channel equalization, symbol lock, and interlane alignment.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_INVALID_PARAM if the number of lanes to check does not match 1, 2, or 4 lanes.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if the RX device has maintained clock recovery, channel equalization, symbol lock, and interlane alignment.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -344,9 +445,11 @@ This function checks if the reciever's DPCD indicates the reciever has achieved
 This function disables the main link.
    
 
    Parameters:
    
   
-    
+    
    InstancePtr is a pointer to the XDptx instance. 
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
    
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -370,9 +473,11 @@ This function disables the main link.
    
 This function enables the main link.
    
 
    Parameters:
    
   
-    
+    
    InstancePtr is a pointer to the XDptx instance. 
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
    
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -406,9 +511,11 @@ This function enables or disables downshifting during the training process.
    
 
    Parameters:
    
   
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    Enable controls the downshift feature in the training process. 
    Enable controls the downshift feature in the training process.
    
   
    
 
    
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -429,15 +536,16 @@ This function enables or disables downshifting during the training process.
    
 
    
 
 
    
-This function determines the common capabilities between the DisplayPort TX core and the receiver.
    
+This function checks if the link needs training and runs the training sequence if training is required.
    
 
    Parameters:
    
   
    
     
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS was either already trained, or has been trained successfully.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_INVALID_PARAM if the current link rate or lane count isn't valid.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS was either already trained, or has been trained successfully.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -458,21 +566,25 @@ This function determines the common capabilities between the DisplayPort TX core
 
    
 
 
    
-This function retrieves the receiver's EDID.
    
+This function retrieves the RX device's Extended Display Identification Data (EDID).
    
 
    Parameters:
    
   
-    
+    
    InstancePtr is a pointer to the XDptx instance. 
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
    
+
    Returns:
      
+
    • XST_SUCCESS if the I2C transactions to read the EDID were successful.
    • XST_ERROR_COUNT_MAX if the EDID read request timed out.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
    • XST_FAILURE otherwise.
    
+
    
+
    Note:
    None. 
    
 
 
    
 
    
-
+
 
    
 
    
       
-          
+          
@@ -484,19 +596,20 @@ This function retrieves the receiver's EDID.
    
 
    
 
 
    
-This function retrieves sink device capabilities from the receiver's DPCD.
    
+This function retrieves the RX device's capabilities from the RX device's DisplayPort Configuration Data (DPCD).
    
 
    Parameters:
    
   
    
         
    u32 XDptx_GetSinkCapabilities           u32 XDptx_GetRxCapabilities           
           (
           XDptx * 
            InstancePtr          
    
     
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
 
    Returns:
      
-
    • XST_SUCCESS if the DPCD was read successfully.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if the DisplayPort Configuration Data was read successfully.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
-
+
 
    
 
    
       
@@ -527,8 +640,8 @@ This function retrieves sink device capabilities from the receiver's DPCD.
    
         
    
-          
-          
+          
+          
@@ -547,16 +660,17 @@ This function performs an I2C read over the AUX channel.
    
     
    
-    
+    
    
           
           u8 *  DataBuffer void *  Data 
         
    
         
    
           
    IicAddress is the address on the I2C bus of the target device. 
    
     
    RegStartAddress is the subaddress of the targeted I2C device that the read will start from. 
    
     
    NumBytes is the number of bytes to read. 
    DataBuffer is a pointer to a buffer that will be filled with the I2C read data.
    Data is a pointer to a buffer that will be filled with the I2C read data.
    
   
    
 
 
    Returns:
      
-
    • XST_SUCCESS if the I2C read has successfully completed with no errors.
    • XST_ERROR_COUNT_MAX if the AUX request timed out.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if the I2C read has successfully completed with no errors.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
-
+
 
    
 
    
       
@@ -587,8 +701,8 @@ This function performs an I2C read over the AUX channel.
    
         
    
-          
-          
+          
+          
@@ -607,12 +721,13 @@ This function performs an I2C write over the AUX channel.
    
     
    
-    
+    
    
           
           u8 *  DataBuffer void *  Data 
         
    
         
    
           
    IicAddress is the address on the I2C bus of the target device. 
    
     
    RegStartAddress is the sub-address of the targeted I2C device that the write will start at. 
    
     
    NumBytes is the number of bytes to write. 
    DataBuffer is a pointer to a buffer which will be used as the data source for the write.
    Data is a pointer to a buffer which will be used as the data source for the write.
    
   
    
 
 
    Returns:
      
-
    • XST_SUCCESS if the I2C write has successfully completed with no errors.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_ERROR_COUNT_MAX if the AUX request timed out.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if the I2C write has successfully completed with no errors.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -640,8 +755,9 @@ This function prepares the DisplayPort TX core for use.
    
   
 
 
    Returns:
      
-
    • XST_SUCCESS if the DisplayPort TX core was successfully initialized.
    • XST_INVALID_PARAM if the supplied link rate does not correspond to either 1.62, 2.70, or 5.40 Gbps.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if the DisplayPort TX core was successfully initialized.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
 
    
@@ -674,10 +790,12 @@ This function prepares the DisplayPort TX core for use.
    
 This function does a PHY reset.
    
 
    Parameters:
    
   
-    
-    
+    
+    
    InstancePtr is a pointer to the XDptx instance. &
    Reset is the type of reset to assert. 
    InstancePtr is a pointer to the XDptx instance. 
    Reset is the type of reset to assert.
    
   
    
 
    
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -707,16 +825,17 @@ This function does a PHY reset.
    
 
    
 
 
    
-This function enables or disables 0.5% spreading of the clock for both the DisplayPort and the sink device.
    
+This function enables or disables 0.5% spreading of the clock for both the DisplayPort and the RX device.
    
 
    Parameters:
    
   
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    Enable will enable or disable down-spread control.
    Enable will downspread the main link signal if set to 1 and disable downspreading if set to 0.
    
   
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if setting the downspread control enable was successful.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if setting the downspread control enable was successful.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -746,16 +865,17 @@ This function enables or disables 0.5% spreading of the clock for both the Displ
 
    
 
 
    
-This function enables or disables the enhanced framing symbol sequence for both the DisplayPort TX core and the sink device.
    
+This function enables or disables the enhanced framing symbol sequence for both the DisplayPort TX core and the RX device.
    
 
    Parameters:
    
   
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    Enable will enable or disable enhanced frame mode.
    Enable will enable enhanced frame mode if set to 1 and disable it if set to 0.
    
   
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if setting the enhanced frame mode enable was successful.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if setting the enhanced frame mode enable was successful.
  • XST_DEVICE_NOT_FOUND if no RX is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -789,9 +909,11 @@ This function sets a software switch that signifies whether or not a redriver ex
 
    Parameters:
    
   
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    Set establishes that a redriver exists in the DisplayPort output path. 
    Set establishes that a redriver exists in the DisplayPort output path.
    
   
    
 
    
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -821,7 +943,7 @@ This function sets a software switch that signifies whether or not a redriver ex
 
    
 
 
    
-This function sets the number of lanes to be used by the main link for both the DisplayPort TX core and the sink device.
    
+This function sets the number of lanes to be used by the main link for both the DisplayPort TX core and the RX device.
    
 
    Parameters:
    
   
@@ -829,8 +951,9 @@ This function sets the number of lanes to be used by the main link for both the
   
    
     
    InstancePtr is a pointer to the XDptx instance. 
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if setting the new lane count was successful.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_INVALID_PARAM if the supplied lane count is not either 1, 2, or 4 lanes.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if setting the new lane count was successful.
  • XST_DEVICE_NOT_FOUND if no RX is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -860,7 +983,7 @@ This function sets the number of lanes to be used by the main link for both the
 
    
 
 
    
-This function sets the data rate to be used by the main link for both the DisplayPort TX core and the sink device.
    
+This function sets the data rate to be used by the main link for both the DisplayPort TX core and the RX device.
    
 
    Parameters:
    
   
@@ -870,8 +993,9 @@ This function sets the data rate to be used by the main link for both the Displa
   
    
     
    InstancePtr is a pointer to the XDptx instance. 
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if setting the new link rate was successful.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_INVALID_PARAM if the supplied link rate does not correspond to either 1.62, 2.70, or 5.40 Gbps.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if setting the new link rate was successful.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -901,7 +1025,7 @@ This function sets the data rate to be used by the main link for both the Displa
 
    
 
 
    
-This function enables or disables scrambling of symbols for both the DisplayPort and the sink device.
    
+This function enables or disables scrambling of symbols for both the DisplayPort and the RX device.
    
 
    Parameters:
    
   
@@ -909,8 +1033,9 @@ This function enables or disables scrambling of symbols for both the DisplayPort
   
    
     
    InstancePtr is a pointer to the XDptx instance. 
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if setting the scrambling enable was successful.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if setting the scrambling enable was successful.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -927,7 +1052,7 @@ This function enables or disables scrambling of symbols for both the DisplayPort
         
           
           
-          XDptx_TimerHandler 
+          XDptx_TimerHandler 
            CallbackFunc, 
         
         
@@ -951,9 +1076,11 @@ This function installs a custom delay/sleep function to be used by the XDdptx dr
   
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    
     
    CallbackFunc is the address to the callback function. 
    CallbackRef is the user data item (microseconds to delay) that will be passed to the custom sleep/delay function when it is invoked. 
    CallbackRef is the user data item (microseconds to delay) that will be passed to the custom sleep/delay function when it is invoked.
    
   
    
 
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -987,9 +1114,11 @@ This function is the delay/sleep function for the 
     InstancePtr is a pointer to the XDptx instance. 
-    MicroSeconds is the number of microseconds to delay/sleep for. 
+    MicroSeconds is the number of microseconds to delay/sleep for.
   
 
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx_8h.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8h.html
similarity index 58%
rename from XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx_8h.html
rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8h.html
index f012d52d..c4924a02 100644
--- a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx_8h.html
+++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8h.html
@@ -13,30 +13,22 @@
 
    
   
    
 
    
   
    
-
    xdptx.h File Reference
    Detailed Description
    
-The Xilinx DisplayPort transmitter (TX) driver.
    
-The driver currently supports single-stream transport (SST) functionality.
    
-
    - MODIFICATION HISTORY:
    
-
     Ver   Who  Date     Changes
- ----- ---- -------- -----------------------------------------------
- 1.00a als  05/17/14 Initial release.
- 
     
+
    xdptx.h File Reference
    
 
    
 #include "xdptx_hw.h"
    
 #include "xil_assert.h"
    
 #include "xil_types.h"
    
 
-
+
@@ -60,14 +52,125 @@ The driver currently supports single-stream transport (SST) functionality.
    
 
    
-
+
 
-
+
 
@@ -85,9 +188,9 @@ The driver currently supports single-stream transport (SST) functionality.
    
 
 
    
 
-
+
 
-
+
 
@@ -111,13 +214,13 @@ The driver currently supports single-stream transport (SST) functionality.
    
 
 
    
 
-
+
 
-
+
 
@@ -153,9 +256,9 @@ The driver currently supports single-stream transport (SST) functionality.
    
 
    
 
 
    
-Value:
    (XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, \
-        XDPTX_INTERRUPT_SIG_STATE) & 0x1)
-
    This macro checks if there is a connected sink.
    
+Value:
    (XDptx_ReadReg(InstancePtr->Config.BaseAddr, \
+        XDPTX_INTERRUPT_SIG_STATE) & XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK)
+
    This macro checks if there is a connected RX device.
    
 
    Parameters:
    
   
    
 

    Data Structures

    Classes
    
 
    struct  XDptx_DmtMode
    
 
 
    struct  XDptx_Config
    typedef void(*) XDptx_HpdPulseHandler (void *InstancePtr)
    
 
 

    Enumerations
    enum  XDptx_VideoMode 
    enum  XDptx_VideoMode { 
    
+  XDPTX_VM_640x480_60_P, 
+XDPTX_VM_800x600_60_P, 
+XDPTX_VM_848x480_60_P, 
+XDPTX_VM_1024x768_60_P, 
+
    
+  XDPTX_VM_1280x768_60_P_RB, 
+XDPTX_VM_1280x768_60_P, 
+XDPTX_VM_1280x800_60_P_RB, 
+XDPTX_VM_1280x800_60_P, 
+
    
+  XDPTX_VM_1280x960_60_P, 
+XDPTX_VM_1280x1024_60_P, 
+XDPTX_VM_1360x768_60_P, 
+XDPTX_VM_1400x1050_60_P_RB, 
+
    
+  XDPTX_VM_1400x1050_60_P, 
+XDPTX_VM_1440x900_60_P_RB, 
+XDPTX_VM_1440x900_60_P, 
+XDPTX_VM_1600x1200_60_P, 
+
    
+  XDPTX_VM_1680x1050_60_P_RB, 
+XDPTX_VM_1680x1050_60_P, 
+XDPTX_VM_1792x1344_60_P, 
+XDPTX_VM_1856x1392_60_P, 
+
    
+  XDPTX_VM_1920x1200_60_P_RB, 
+XDPTX_VM_1920x1200_60_P, 
+XDPTX_VM_1920x1440_60_P, 
+XDPTX_VM_2560x1600_60_P_RB, 
+
    
+  XDPTX_VM_2560x1600_60_P, 
+XDPTX_VM_800x600_56_P, 
+XDPTX_VM_1600x1200_65_P, 
+XDPTX_VM_1600x1200_70_P, 
+
    
+  XDPTX_VM_1024x768_70_P, 
+XDPTX_VM_640x480_72_P, 
+XDPTX_VM_800x600_72_P, 
+XDPTX_VM_640x480_75_P, 
+
    
+  XDPTX_VM_800x600_75_P, 
+XDPTX_VM_1024x768_75_P, 
+XDPTX_VM_1152x864_75_P, 
+XDPTX_VM_1280x768_75_P, 
+
    
+  XDPTX_VM_1280x800_75_P, 
+XDPTX_VM_1280x1024_75_P, 
+XDPTX_VM_1400x1050_75_P, 
+XDPTX_VM_1440x900_75_P, 
+
    
+  XDPTX_VM_1600x1200_75_P, 
+XDPTX_VM_1680x1050_75_P, 
+XDPTX_VM_1792x1344_75_P, 
+XDPTX_VM_1856x1392_75_P, 
+
    
+  XDPTX_VM_1920x1200_75_P, 
+XDPTX_VM_1920x1440_75_P, 
+XDPTX_VM_2560x1600_75_P, 
+XDPTX_VM_640x350_85_P, 
+
    
+  XDPTX_VM_640x400_85_P, 
+XDPTX_VM_720x400_85_P, 
+XDPTX_VM_640x480_85_P, 
+XDPTX_VM_800x600_85_P, 
+
    
+  XDPTX_VM_1024x768_85_P, 
+XDPTX_VM_1280x768_85_P, 
+XDPTX_VM_1280x800_85_P, 
+XDPTX_VM_1280x960_85_P, 
+
    
+  XDPTX_VM_1280x1024_85_P, 
+XDPTX_VM_1400x1050_85_P, 
+XDPTX_VM_1440x900_85_P, 
+XDPTX_VM_1600x1200_85_P, 
+
    
+  XDPTX_VM_1680x1050_85_P, 
+XDPTX_VM_1920x1200_85_P, 
+XDPTX_VM_2560x1600_85_P, 
+XDPTX_VM_800x600_120_P_RB, 
+
    
+  XDPTX_VM_1024x768_120_P_RB, 
+XDPTX_VM_1280x768_120_P_RB, 
+XDPTX_VM_1280x800_120_P_RB, 
+XDPTX_VM_1280x960_120_P_RB, 
+
    
+  XDPTX_VM_1280x1024_120_P_RB, 
+XDPTX_VM_1360x768_120_P_RB, 
+XDPTX_VM_1400x1050_120_P_RB, 
+XDPTX_VM_1440x900_120_P_RB, 
+
    
+  XDPTX_VM_1600x1200_120_P_RB, 
+XDPTX_VM_1680x1050_120_P_RB, 
+XDPTX_VM_1792x1344_120_P_RB, 
+XDPTX_VM_1856x1392_120_P_RB, 
+
    
+  XDPTX_VM_1920x1200_120_P_RB, 
+XDPTX_VM_1920x1440_120_P_RB, 
+XDPTX_VM_2560x1600_120_P_RB, 
+XDPTX_VM_1366x768_60_P, 
+
    
+  XDPTX_VM_1920x1080_60_P, 
+XDPTX_VM_UHD_30_P, 
+XDPTX_VM_720_60_P, 
+XDPTX_VM_480_60_P, 
+
    
+  XDPTX_VM_UHD2_60_P, 
+XDPTX_VM_UHD_60, 
+XDPTX_VM_USE_EDID_PREFERRED, 
+XDPTX_VM_LAST =  XDPTX_VM_USE_EDID_PREFERRED
+
    
+ }
    
 
 

    Functions
    
 
    u32 XDptx_InitializeTx (XDptx *InstancePtr)
    
 
 
    void XDptx_CfgInitialize (XDptx *InstancePtr, XDptx_Config *ConfigPtr, u32 EffectiveAddr)
    u32 XDptx_GetSinkCapabilities (XDptx *InstancePtr)
    u32 XDptx_GetRxCapabilities (XDptx *InstancePtr)
    
 
 
    u32 XDptx_GetEdid (XDptx *InstancePtr)
    u32 XDptx_AuxWrite (XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data)
    u32 XDptx_IicWrite (XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, u8 NumBytes, u8 *DataBuffer)
    u32 XDptx_IicRead (XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, u8 NumBytes, void *Data)
    u32 XDptx_IicRead (XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, u8 NumBytes, u8 *DataBuffer)
    u32 XDptx_IicWrite (XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress, u8 NumBytes, void *Data)
    
 
 
    u32 XDptx_SetDownspread (XDptx *InstancePtr, u8 Enable)
    void XDptx_CfgMsaRecalculate (XDptx *InstancePtr)
    u32 XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, XDptx_VideoMode VideoMode)
    void XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, XDptx_VideoMode VideoMode)
    
 
 
    void XDptx_CfgMsaUseEdidPreferredTiming (XDptx *InstancePtr)
    
 
 
    void XDptx_CfgMsaUseCustom (XDptx *InstancePtr, XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate)
    u32 XDptx_CfgMsaSetBpc (XDptx *InstancePtr, u8 BitsPerColor)
    void XDptx_CfgMsaSetBpc (XDptx *InstancePtr, u8 BitsPerColor)
    
 
 
    void XDptx_SetVideoMode (XDptx *InstancePtr)
    
@@ -181,12 +284,13 @@ The driver currently supports single-stream transport (SST) functionality.
    
 
    
 
 
    
-Callback type which represents the handler for a hot-plug-detect event interrupt.
    
+Callback type which represents the handler for a Hot-Plug-Detect (HPD) event interrupt.
    
 
    Parameters:
    
   
    
     
    InstancePtr is a pointer to the XDptx instance.
    
-    
+    
    InstancePtr is a pointer to the XDptx instance. 
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
+
    Note:
    None. 
    
 
 
 
    
@@ -202,12 +306,13 @@ Callback type which represents the handler for a hot-plug-detect event interrupt
 
    
 
 
    
-Callback type which represents the handler for a hot-plug-detect pulse interrupt.
    
+Callback type which represents the handler for a Hot-Plug-Detect (HPD) pulse interrupt.
    
 
    Parameters:
    
   
-    
+    
    InstancePtr is a pointer to the XDptx instance. 
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -227,9 +332,10 @@ Callback type which represents a custom timer wait handler. This is only used fo
 
    Parameters:
    
   
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    MicroSeconds is the number of microseconds to be passed to the timer function. 
    MicroSeconds is the number of microseconds to be passed to the timer function.
    
   
    
 
    
+
    Note:
    None. 
    
 
 
 
    
@@ -248,7 +354,187 @@ Callback type which represents a custom timer wait handler. This is only used fo
 
    
 This typedef enumerates the list of available standard display monitor timings as specified in the mode_table.c file. The naming format is:
    
 XDPTX_VM_<RESOLUTION>_<REFRESH RATE (HZ)>_<P|RB>
    
-Where RB stands for reduced blanking. 
+Where RB stands for reduced blanking. 
    Enumerator: 
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    XDPTX_VM_640x480_60_P 
+
    XDPTX_VM_800x600_60_P 
+
    XDPTX_VM_848x480_60_P 
+
    XDPTX_VM_1024x768_60_P 
+
    XDPTX_VM_1280x768_60_P_RB 
+
    XDPTX_VM_1280x768_60_P 
+
    XDPTX_VM_1280x800_60_P_RB 
+
    XDPTX_VM_1280x800_60_P 
+
    XDPTX_VM_1280x960_60_P 
+
    XDPTX_VM_1280x1024_60_P 
+
    XDPTX_VM_1360x768_60_P 
+
    XDPTX_VM_1400x1050_60_P_RB 
+
    XDPTX_VM_1400x1050_60_P 
+
    XDPTX_VM_1440x900_60_P_RB 
+
    XDPTX_VM_1440x900_60_P 
+
    XDPTX_VM_1600x1200_60_P 
+
    XDPTX_VM_1680x1050_60_P_RB 
+
    XDPTX_VM_1680x1050_60_P 
+
    XDPTX_VM_1792x1344_60_P 
+
    XDPTX_VM_1856x1392_60_P 
+
    XDPTX_VM_1920x1200_60_P_RB 
+
    XDPTX_VM_1920x1200_60_P 
+
    XDPTX_VM_1920x1440_60_P 
+
    XDPTX_VM_2560x1600_60_P_RB 
+
    XDPTX_VM_2560x1600_60_P 
+
    XDPTX_VM_800x600_56_P 
+
    XDPTX_VM_1600x1200_65_P 
+
    XDPTX_VM_1600x1200_70_P 
+
    XDPTX_VM_1024x768_70_P 
+
    XDPTX_VM_640x480_72_P 
+
    XDPTX_VM_800x600_72_P 
+
    XDPTX_VM_640x480_75_P 
+
    XDPTX_VM_800x600_75_P 
+
    XDPTX_VM_1024x768_75_P 
+
    XDPTX_VM_1152x864_75_P 
+
    XDPTX_VM_1280x768_75_P 
+
    XDPTX_VM_1280x800_75_P 
+
    XDPTX_VM_1280x1024_75_P 
+
    XDPTX_VM_1400x1050_75_P 
+
    XDPTX_VM_1440x900_75_P 
+
    XDPTX_VM_1600x1200_75_P 
+
    XDPTX_VM_1680x1050_75_P 
+
    XDPTX_VM_1792x1344_75_P 
+
    XDPTX_VM_1856x1392_75_P 
+
    XDPTX_VM_1920x1200_75_P 
+
    XDPTX_VM_1920x1440_75_P 
+
    XDPTX_VM_2560x1600_75_P 
+
    XDPTX_VM_640x350_85_P 
+
    XDPTX_VM_640x400_85_P 
+
    XDPTX_VM_720x400_85_P 
+
    XDPTX_VM_640x480_85_P 
+
    XDPTX_VM_800x600_85_P 
+
    XDPTX_VM_1024x768_85_P 
+
    XDPTX_VM_1280x768_85_P 
+
    XDPTX_VM_1280x800_85_P 
+
    XDPTX_VM_1280x960_85_P 
+
    XDPTX_VM_1280x1024_85_P 
+
    XDPTX_VM_1400x1050_85_P 
+
    XDPTX_VM_1440x900_85_P 
+
    XDPTX_VM_1600x1200_85_P 
+
    XDPTX_VM_1680x1050_85_P 
+
    XDPTX_VM_1920x1200_85_P 
+
    XDPTX_VM_2560x1600_85_P 
+
    XDPTX_VM_800x600_120_P_RB 
+
    XDPTX_VM_1024x768_120_P_RB 
+
    XDPTX_VM_1280x768_120_P_RB 
+
    XDPTX_VM_1280x800_120_P_RB 
+
    XDPTX_VM_1280x960_120_P_RB 
+
    XDPTX_VM_1280x1024_120_P_RB 
+
    XDPTX_VM_1360x768_120_P_RB 
+
    XDPTX_VM_1400x1050_120_P_RB 
+
    XDPTX_VM_1440x900_120_P_RB 
+
    XDPTX_VM_1600x1200_120_P_RB 
+
    XDPTX_VM_1680x1050_120_P_RB 
+
    XDPTX_VM_1792x1344_120_P_RB 
+
    XDPTX_VM_1856x1392_120_P_RB 
+
    XDPTX_VM_1920x1200_120_P_RB 
+
    XDPTX_VM_1920x1440_120_P_RB 
+
    XDPTX_VM_2560x1600_120_P_RB 
+
    XDPTX_VM_1366x768_60_P 
+
    XDPTX_VM_1920x1080_60_P 
+
    XDPTX_VM_UHD_30_P 
+
    XDPTX_VM_720_60_P 
+
    XDPTX_VM_480_60_P 
+
    XDPTX_VM_UHD2_60_P 
+
    XDPTX_VM_UHD_60 
+
    XDPTX_VM_USE_EDID_PREFERRED 
+
    XDPTX_VM_LAST 
+
    
+
    
+
 
 
    
 
    Function Documentation
    
@@ -294,14 +580,15 @@ This function issues a read request over the AUX channel.
    
 
    Parameters:
    
   
-    
-    
+    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    Address is the starting address to read from the receiver. 
    NumBytes is the number of bytes to read from the receiver. 
    Address is the starting address to read from the RX device. 
    NumBytes is the number of bytes to read from the RX device. 
    
     
    Data is a pointer to the data buffer that will be filled with read data.
    
   
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if the AUX read request was successfully acknowledged.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_NO_DATA if no data was provided.
    • XST_ERROR_COUNT_MAX if the AUX request timed out.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if the AUX read request was successfully acknowledged.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
 
    
@@ -347,14 +634,15 @@ This function issues a write request over the AUX channel.
    
 
    Parameters:
    
   
-    
-    
-    
+    
+    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    Address is the starting address to write to the receiver. 
    NumBytes is the number of bytes to write to the receiver. 
    Data is a pointer to the data buffer that contains the data to be written to the receiver.
    Address is the starting address to write to the RX device. 
    NumBytes is the number of bytes to write to the RX device. 
    Data is a pointer to the data buffer that contains the data to be written to the RX device.
    
   
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if AUX write request was successfully acknowledged.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_NO_DATA if no data was provided.
    • XST_ERROR_COUNT_MAX if the AUX request timed out.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if AUX write request was successfully acknowledged.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
 
    
@@ -390,7 +678,7 @@ This function issues a write request over the AUX channel.
    
 
    
 
 
    
-This function retrieves the configuration for this DisplayPort TX instance and fills in the InstancePtr->TxConfig structure.
    
+This function retrieves the configuration for this DisplayPort TX instance and fills in the InstancePtr->Config structure.
    
 
    Parameters:
    
   
@@ -398,6 +686,7 @@ This function retrieves the configuration for this DisplayPort TX instance and f
     
    
     
    InstancePtr is a pointer to the XDptx instance. 
    EffectiveAddr is the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed.
    
   
    
 
    
+
    Returns:
    None.
    
 
    Note:
    Unexpected errors may occur if the address mapping is changed after this function is invoked. 
    
 
 
    
@@ -419,15 +708,16 @@ This function retrieves the configuration for this DisplayPort TX instance and f
 
    
 
 
    
-This function determines the common capabilities between the DisplayPort TX core and the receiver.
    
+This function determines the common capabilities between the DisplayPort TX core and the RX device.
    
 
    Parameters:
    
   
    
     
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if main link settings were successfully set.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_INVALID_PARAM if the specified link configuration specifies a link rate or lane count that isn't valid.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if main link settings were successfully set.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -448,7 +738,7 @@ This function determines the common capabilities between the DisplayPort TX core
 
    
 
 
    
-This function calculates the following main stream attributes:
      
+This function calculates the following Main Stream Attributes (MSA):
        
 
      • Transfer unit size
      • User pixel width
      • NVid
      • Horizontal start
      • Vertical start
      • Horizontal total clock
      • Vertical total clock
      • Misc0
      • Misc1
      • Data per lane
      • Average number of bytes per transfer unit
      • Number of initial wait cycles These values are derived from:
      • Bits per color
      • MVid
      • Horizontal sync polarity
      • Vertical sync polarity
      • Horizontal sync pulse width
      • Vertical sync pulse width
      • Horizontal resolution
      • Vertical resolution
      • Vertical back porch
      • Vertical front porch
      • Horizontal back porch
      • Horizontal front porch
      
 
      
 
      Parameters:
      
@@ -456,16 +746,17 @@ This function calculates the following main stream attributes:
        
     InstancePtr is a pointer to the XDptx instance.
   
 
      
+
      Returns:
      None.
      
 
      Note:
      The MsaConfig structure is modified with the new, calculated values. The main stream attributes that were used to derive the calculated values are untouched in the MsaConfig structure. 
      
 
 
    
 
    
-
+
 
    
 
    
       
-          
+          
@@ -493,10 +784,8 @@ This function sets the bits per color value of the video stream.
    
     
    
         
    u32 XDptx_CfgMsaSetBpc           void XDptx_CfgMsaSetBpc           
           (
           XDptx * 
            InstancePtr, 
    BitsPerColor is the new number of bits per color to use.
    
   
    
 
-
    Note:
    The InstancePtr->MsaConfig structure is modified to reflect the new main stream attributes associated with a new bits per color value.
    
-
    Returns:
      
-
    • XST_INVALID_PARAM if the supplied bits per color value is not either 6, 8, 10, 12, or 16.
    • XST_SUCCESS otherwise. 
    
-
    
+
    Returns:
    None.
    
+
    Note:
    The InstancePtr->MsaConfig structure is modified to reflect the new main stream attributes associated with a new bits per color value. 
    
 
 
    
 
    
@@ -542,6 +831,7 @@ This function takes a the main stream attributes from MsaConfigCustom and copies
     Recalculate is a boolean enable that determines whether or not the main stream attributes should be recalculated.
   
 
+
    Returns:
    None.
    
 
    Note:
    The InstancePtr-> MsaConfig structure is modified with the new values. 
    
 
 
@@ -563,22 +853,23 @@ This function takes a the main stream attributes from MsaConfigCustom and copies
 
    
 
 
    
-This function sets the main stream attribute values in the configuration structure to match the preferred timing of the sink monitor. This preferred timing information is stored in the sink's extended display identification data (EDID).
    
+This function sets the main stream attribute values in the configuration structure to match the preferred timing of the sink monitor. This Preferred Timing Mode (PTM) information is stored in the sink's Extended Display Identification Data (EDID).
    
 
    Parameters:
    
   
    
     
    InstancePtr is a pointer to the XDptx instance
    
   
    
 
    
+
    Returns:
    None.
    
 
    Note:
    The InstancePtr->MsaConfig structure is modified to reflect the main stream attribute values associated to the preferred timing of the sink monitor. 
    
 
 
    
 
    
-
+
 
    
 
    
       
-          
+          
@@ -599,17 +890,15 @@ This function sets the main stream attribute values in the configuration structu
 
    
 
 
    
-This function sets the main stream attribute values in the configuration structure to match one of the standard display mode timings from the XDptx_DmtModes[] table. THe XDptx_VideoMode enumeration in xdptx.h lists the available video modes.
    
+This function sets the Main Stream Attribute (MSA) values in the configuration structure to match one of the standard display mode timings from the XDptx_DmtModes[] standard Display Monitor Timing (DMT) table. The XDptx_VideoMode enumeration in xdptx.h lists the available video modes.
    
 
    Parameters:
    
   
    
         
    u32 XDptx_CfgMsaUseStandardVideoMode           void XDptx_CfgMsaUseStandardVideoMode           
           (
           XDptx * 
            InstancePtr, 
    
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    VideoMode is one of the enumerated standard video modes that is used to determine the main stream attributes to be used.
    VideoMode is one of the enumerated standard video modes that is used to determine the MSA values to be used.
    
   
    
 
-
    Returns:
      
-
    • XST_INVALID_PARAM if the supplied video mode isn't in the DMT table.
    • XST_SUCCESS otherwise.
    
-
    
-
    Note:
    The InstancePtr->MsaConfig structure is modified to reflect the main stream attribute values associated to the specified video mode. 
    
+
    Returns:
    None.
    
+
    Note:
    The InstancePtr->MsaConfig structure is modified to reflect the MSA values associated to the specified video mode. 
    
 
 
    
 
    
@@ -639,7 +928,7 @@ This function sets the main stream attribute values in the configuration structu
 
    
 
 
    
-This function checks if the reciever's DPCD indicates the reciever has achieved and maintained clock recovery, channel equalization, symbol lock, and interlane alignment for all lanes currently in use.
    
+This function checks if the reciever's DisplayPort Configuration Data (DPCD) indicates the reciever has achieved and maintained clock recovery, channel equalization, symbol lock, and interlane alignment for all lanes currently in use.
    
 
    Parameters:
    
   
@@ -647,8 +936,9 @@ This function checks if the reciever's DPCD indicates the reciever has achieved
   
    
     
    InstancePtr is a pointer to the XDptx instance. 
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if the receiver has maintained clock recovery, channel equalization, symbol lock, and interlane alignment.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_INVALID_PARAM if the number of lanes to check does not match 1, 2, or 4 lanes.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if the RX device has maintained clock recovery, channel equalization, symbol lock, and interlane alignment.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -672,9 +962,11 @@ This function checks if the reciever's DPCD indicates the reciever has achieved
 This function disables the main link.
    
 
    Parameters:
    
   
-    
+    
    InstancePtr is a pointer to the XDptx instance. 
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
    
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -698,9 +990,11 @@ This function disables the main link.
    
 This function enables the main link.
    
 
    Parameters:
    
   
-    
+    
    InstancePtr is a pointer to the XDptx instance. 
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
    
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -734,9 +1028,11 @@ This function enables or disables downshifting during the training process.
    
 
    Parameters:
    
   
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    Enable controls the downshift feature in the training process. 
    Enable controls the downshift feature in the training process.
    
   
    
 
    
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -757,15 +1053,16 @@ This function enables or disables downshifting during the training process.
    
 
    
 
 
    
-This function determines the common capabilities between the DisplayPort TX core and the receiver.
    
+This function checks if the link needs training and runs the training sequence if training is required.
    
 
    Parameters:
    
   
    
     
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS was either already trained, or has been trained successfully.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_INVALID_PARAM if the current link rate or lane count isn't valid.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS was either already trained, or has been trained successfully.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -786,21 +1083,25 @@ This function determines the common capabilities between the DisplayPort TX core
 
    
 
 
    
-This function retrieves the receiver's EDID.
    
+This function retrieves the RX device's Extended Display Identification Data (EDID).
    
 
    Parameters:
    
   
-    
+    
    InstancePtr is a pointer to the XDptx instance. 
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
    
+
    Returns:
      
+
    • XST_SUCCESS if the I2C transactions to read the EDID were successful.
    • XST_ERROR_COUNT_MAX if the EDID read request timed out.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
    • XST_FAILURE otherwise.
    
+
    
+
    Note:
    None. 
    
 
 
    
 
    
-
+
 
    
 
    
       
-          
+          
@@ -812,15 +1113,16 @@ This function retrieves the receiver's EDID.
    
 
    
 
 
    
-This function retrieves sink device capabilities from the receiver's DPCD.
    
+This function retrieves the RX device's capabilities from the RX device's DisplayPort Configuration Data (DPCD).
    
 
    Parameters:
    
   
    
         
    u32 XDptx_GetSinkCapabilities           u32 XDptx_GetRxCapabilities           
           (
           XDptx * 
            InstancePtr          
    
     
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
 
    Returns:
      
-
    • XST_SUCCESS if the DPCD was read successfully.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if the DisplayPort Configuration Data was read successfully.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -845,13 +1147,15 @@ This function is the interrupt handler for the 
-    InstancePtr is a pointer to the XDptx instance. 
+    InstancePtr is a pointer to the XDptx instance.
   
 
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
-
+
 
    
 
    
       
@@ -882,8 +1186,8 @@ When an interrupt happens, it first detects what kind of interrupt happened, the
         
-          
-          
+          
+          
@@ -902,16 +1206,17 @@ This function performs an I2C read over the AUX channel.
    
     
    
-    
+    
    
           
           u8 *  DataBuffer void *  Data 
         
    
         
    
           
    IicAddress is the address on the I2C bus of the target device. 
    
     
    RegStartAddress is the subaddress of the targeted I2C device that the read will start from. 
    
     
    NumBytes is the number of bytes to read. 
    DataBuffer is a pointer to a buffer that will be filled with the I2C read data.
    Data is a pointer to a buffer that will be filled with the I2C read data.
    
   
    
 
 
    Returns:
      
-
    • XST_SUCCESS if the I2C read has successfully completed with no errors.
    • XST_ERROR_COUNT_MAX if the AUX request timed out.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if the I2C read has successfully completed with no errors.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
-
+
 
    
 
    
       
@@ -942,8 +1247,8 @@ This function performs an I2C read over the AUX channel.
    
         
    
-          
-          
+          
+          
@@ -962,12 +1267,13 @@ This function performs an I2C write over the AUX channel.
    
     
    
-    
+    
    
           
           u8 *  DataBuffer void *  Data 
         
    
         
    
           
    IicAddress is the address on the I2C bus of the target device. 
    
     
    RegStartAddress is the sub-address of the targeted I2C device that the write will start at. 
    
     
    NumBytes is the number of bytes to write. 
    DataBuffer is a pointer to a buffer which will be used as the data source for the write.
    Data is a pointer to a buffer which will be used as the data source for the write.
    
   
    
 
 
    Returns:
      
-
    • XST_SUCCESS if the I2C write has successfully completed with no errors.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_ERROR_COUNT_MAX if the AUX request timed out.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if the I2C write has successfully completed with no errors.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -995,8 +1301,9 @@ This function prepares the DisplayPort TX core for use.
    
   
 
 
    Returns:
      
-
    • XST_SUCCESS if the DisplayPort TX core was successfully initialized.
    • XST_INVALID_PARAM if the supplied link rate does not correspond to either 1.62, 2.70, or 5.40 Gbps.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if the DisplayPort TX core was successfully initialized.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
 
    
@@ -1023,7 +1330,8 @@ This function looks for the device configuration based on the unique device ID.
     DeviceId is the unique device ID of the device being looked up.
   
 
-
    Returns:
    A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found. 
    
+
    Returns:
    A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -1056,10 +1364,12 @@ This function looks for the device configuration based on the unique device ID.
 This function does a PHY reset.
    
 
    Parameters:
    
   
-    
-    
+    
+    
    InstancePtr is a pointer to the XDptx instance. &
    Reset is the type of reset to assert. 
    InstancePtr is a pointer to the XDptx instance. 
    Reset is the type of reset to assert.
    
   
    
 
    
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -1080,15 +1390,16 @@ This function does a PHY reset.
    
 
    
 
 
    
-This function runs a self-test on the XDptx driver/device. The test attempts to intialize the DisplayPort TX core, train the main link at the highest common capabilities between the core and the sink, and checks the status of the link after training.
    
+This function runs a self-test on the XDptx driver/device. The sanity test checks whether or not all tested registers hold their default reset values.
    
 
    Parameters:
    
   
    
     
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if the self-test passed. The main link has been trained and established successfully.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if the self-test passed - all tested registers hold their default reset values.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -1118,16 +1429,17 @@ This function runs a self-test on the XD
 
    
 
 
    
-This function enables or disables 0.5% spreading of the clock for both the DisplayPort and the sink device.
    
+This function enables or disables 0.5% spreading of the clock for both the DisplayPort and the RX device.
    
 
    Parameters:
    
   
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    Enable will enable or disable down-spread control.
    Enable will downspread the main link signal if set to 1 and disable downspreading if set to 0.
    
   
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if setting the downspread control enable was successful.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if setting the downspread control enable was successful.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -1157,16 +1469,17 @@ This function enables or disables 0.5% spreading of the clock for both the Displ
 
    
 
 
    
-This function enables or disables the enhanced framing symbol sequence for both the DisplayPort TX core and the sink device.
    
+This function enables or disables the enhanced framing symbol sequence for both the DisplayPort TX core and the RX device.
    
 
    Parameters:
    
   
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    Enable will enable or disable enhanced frame mode.
    Enable will enable enhanced frame mode if set to 1 and disable it if set to 0.
    
   
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if setting the enhanced frame mode enable was successful.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if setting the enhanced frame mode enable was successful.
  • XST_DEVICE_NOT_FOUND if no RX is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -1200,9 +1513,11 @@ This function sets a software switch that signifies whether or not a redriver ex
 
    Parameters:
    
   
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    Set establishes that a redriver exists in the DisplayPort output path. 
    Set establishes that a redriver exists in the DisplayPort output path.
    
   
    
 
    
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -1243,9 +1558,11 @@ This function installs a callback function for when a hot-plug-detect event inte
   
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    
     
    CallbackFunc is the address to the callback function. 
    CallbackRef is the user data item that will be passed to the callback function when it is invoked. 
    CallbackRef is the user data item that will be passed to the callback function when it is invoked.
    
   
    
 
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -1286,9 +1603,11 @@ This function installs a callback function for when a hot-plug-detect pulse inte
   
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    
     
    CallbackFunc is the address to the callback function. 
    CallbackRef is the user data item that will be passed to the callback function when it is invoked. 
    CallbackRef is the user data item that will be passed to the callback function when it is invoked.
    
   
    
 
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -1318,7 +1637,7 @@ This function installs a callback function for when a hot-plug-detect pulse inte
 
    
 
 
    
-This function sets the number of lanes to be used by the main link for both the DisplayPort TX core and the sink device.
    
+This function sets the number of lanes to be used by the main link for both the DisplayPort TX core and the RX device.
    
 
    Parameters:
    
   
@@ -1326,8 +1645,9 @@ This function sets the number of lanes to be used by the main link for both the
   
    
     
    InstancePtr is a pointer to the XDptx instance. 
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if setting the new lane count was successful.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_INVALID_PARAM if the supplied lane count is not either 1, 2, or 4 lanes.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if setting the new lane count was successful.
  • XST_DEVICE_NOT_FOUND if no RX is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -1357,7 +1677,7 @@ This function sets the number of lanes to be used by the main link for both the
 
    
 
 
    
-This function sets the data rate to be used by the main link for both the DisplayPort TX core and the sink device.
    
+This function sets the data rate to be used by the main link for both the DisplayPort TX core and the RX device.
    
 
    Parameters:
    
   
@@ -1367,8 +1687,9 @@ This function sets the data rate to be used by the main link for both the Displa
   
    
     
    InstancePtr is a pointer to the XDptx instance. 
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if setting the new link rate was successful.
    • XST_DEVICE_NOT_FOUND if no receiver is connected.
    • XST_INVALID_PARAM if the supplied link rate does not correspond to either 1.62, 2.70, or 5.40 Gbps.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if setting the new link rate was successful.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -1398,7 +1719,7 @@ This function sets the data rate to be used by the main link for both the Displa
 
    
 
 
    
-This function enables or disables scrambling of symbols for both the DisplayPort and the sink device.
    
+This function enables or disables scrambling of symbols for both the DisplayPort and the RX device.
    
 
    Parameters:
    
   
@@ -1406,8 +1727,9 @@ This function enables or disables scrambling of symbols for both the DisplayPort
   
    
     
    InstancePtr is a pointer to the XDptx instance. 
    
 
    
 
    Returns:
      
-
    • XST_SUCCESS if setting the scrambling enable was successful.
    • XST_FAILURE otherwise. 
    
+
  • XST_SUCCESS if setting the scrambling enable was successful.
  • XST_FAILURE otherwise.
    • 
 
    
+
    Note:
    None. 
    
 
 
    
 
    
@@ -1448,9 +1770,11 @@ This function installs a custom delay/sleep function to be used by the XDdptx dr
   
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    
     
    CallbackFunc is the address to the callback function. 
    CallbackRef is the user data item (microseconds to delay) that will be passed to the custom sleep/delay function when it is invoked. 
    CallbackRef is the user data item (microseconds to delay) that will be passed to the custom sleep/delay function when it is invoked.
    
   
    
 
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -1474,9 +1798,11 @@ This function installs a custom delay/sleep function to be used by the XDdptx dr
 This function clears the main stream attributes registers of the DisplayPort TX core and sets them to the values specified in the main stream attributes configuration structure.
    
 
    Parameters:
    
   
-    
+    
    InstancePtr is a pointer to the XDptx instance 
    InstancePtr is a pointer to the XDptx instance
    
   
    
 
    
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -1510,9 +1836,11 @@ This function is the delay/sleep function for the 
     InstancePtr is a pointer to the XDptx instance. 
-    MicroSeconds is the number of microseconds to delay/sleep for. 
+    MicroSeconds is the number of microseconds to delay/sleep for.
   
 
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -1529,7 +1857,7 @@ This function is the delay/sleep function for the 
 
 
    
-This table contains the main stream attributes for various standard resolutions. 
+This table contains the main stream attributes for various standard resolutions. Each entry is of the format: 1) XDPTX_VM_<HRES>x<VRES>_<REFRESH (HZ)>_P(_RB = Reduced Blanking) 2) Display Monitor Timing (DMT) ID 3) Horizontal resolution (pixels) 4) Vertical resolution (lines) 5) Pixel clock (KHz) 6) Scan (0=non-interlaced|1=interlaced) 7) Horizontal sync polarity (0=positive|1=negative) 8) Vertical sync polarity (0=positive|1=negative) 9) Horizontal front porch (pixels) 10) Horizontal sync time (pixels) 11) Horizontal back porch (pixels) 12) Vertical front porch (lines) 13) Vertical sync time (lines) 14) Vertical back porch (lines) 
 
 
    
 Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__hw_8h.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__hw_8h.html
new file mode 100644
index 00000000..ce4b580e
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__hw_8h.html
@@ -0,0 +1,9474 @@
+
+
+   
+
+   xdptx_hw.h File Reference
+
+
+
+
    Xilinx Processor IP Library
    
+Software Drivers
+
    
+
+
    
+  
    
+
    
+  
    
+
    xdptx_hw.h File Reference
    Detailed Description
    
+This header file contains the identifiers and low-level driver functions (or macros) that can be used to access the device. High-level driver functions are defined in xdptx.h.
    
+
    Note:
    None.
    
+
    + MODIFICATION HISTORY:
    
+
     Ver   Who  Date     Changes
+ ----- ---- -------- -----------------------------------------------
+ 1.00a als  05/17/14 Initial release.
+ 
     
+
    
+#include "xil_io.h"
    
+#include "xil_types.h"
    
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    DPTX core registers: Link configuration field.
    #define XDPTX_LINK_BW_SET   0x0000
    #define XDPTX_LANE_COUNT_SET   0x0004
    #define XDPTX_ENHANCED_FRAME_EN   0x0008
    #define XDPTX_TRAINING_PATTERN_SET   0x000C
    #define XDPTX_LINK_QUAL_PATTERN_SET   0x0010
    #define XDPTX_SCRAMBLING_DISABLE   0x0014
    #define XDPTX_DOWNSPREAD_CTRL   0x0018
    #define XDPTX_SOFT_RESET   0x001C

    DPTX core registers: Core enables.
    #define XDPTX_ENABLE   0x0080
    #define XDPTX_ENABLE_MAIN_STREAM   0x0084
    #define XDPTX_ENABLE_SEC_STREAM   0x0088
    #define XDPTX_FORCE_SCRAMBLER_RESET   0x00C0
    #define XDPTX_TX_MST_CONFIG   0x00D0

    DPTX core registers: Core ID.
    #define XDPTX_VERSION   0x00F8
    #define XDPTX_CORE_ID   0x00FC

    DPTX core registers: AUX channel interface.
    #define XDPTX_AUX_CMD   0x0100
    #define XDPTX_AUX_WRITE_FIFO   0x0104
    #define XDPTX_AUX_ADDRESS   0x0108
    #define XDPTX_AUX_CLK_DIVIDER   0x010C
    #define XDPTX_TX_USER_FIFO_OVERFLOW   0x0110
    #define XDPTX_INTERRUPT_SIG_STATE   0x0130
    #define XDPTX_AUX_REPLY_DATA   0x0134
    #define XDPTX_AUX_REPLY_CODE   0x0138
    #define XDPTX_AUX_REPLY_COUNT   0x013C
    #define XDPTX_INTERRUPT_STATUS   0x0140
    #define XDPTX_INTERRUPT_MASK   0x0144
    #define XDPTX_REPLY_DATA_COUNT   0x0148
    #define XDPTX_REPLY_STATUS   0x014C
    #define XDPTX_HPD_DURATION   0x0150

    DPTX core registers: Main stream attributes for SST / MST STREAM1.
    #define XDPTX_STREAM1_MSA_START   0x0180
    #define XDPTX_MAIN_STREAM_HTOTAL   0x0180
    #define XDPTX_MAIN_STREAM_VTOTAL   0x0184
    #define XDPTX_MAIN_STREAM_POLARITY   0x0188
    #define XDPTX_MAIN_STREAM_HSWIDTH   0x018C
    #define XDPTX_MAIN_STREAM_VSWIDTH   0x0190
    #define XDPTX_MAIN_STREAM_HRES   0x0194
    #define XDPTX_MAIN_STREAM_VRES   0x0198
    #define XDPTX_MAIN_STREAM_HSTART   0x019C
    #define XDPTX_MAIN_STREAM_VSTART   0x01A0
    #define XDPTX_MAIN_STREAM_MISC0   0x01A4
    #define XDPTX_MAIN_STREAM_MISC1   0x01A8
    #define XDPTX_M_VID   0x01AC
    #define XDPTX_TU_SIZE   0x01B0
    #define XDPTX_N_VID   0x01B4
    #define XDPTX_USER_PIXEL_WIDTH   0x01B8
    #define XDPTX_USER_DATA_COUNT_PER_LANE   0x01BC
    #define XDPTX_MAIN_STREAM_INTERLACED   0x01C0
    #define XDPTX_MIN_BYTES_PER_TU   0x01C4
    #define XDPTX_FRAC_BYTES_PER_TU   0x01C8
    #define XDPTX_INIT_WAIT   0x01CC
    #define XDPTX_STREAM0   0x01D0
    #define XDPTX_STREAM1   0x01D4
    #define XDPTX_STREAM2   0x01D8
    #define XDPTX_STREAM3   0x01DC

    DPTX core registers: PHY configuration status.
    #define XDPTX_PHY_CONFIG   0x0200
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_0   0x0220
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_1   0x0224
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_2   0x0228
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_3   0x022C
    #define XDPTX_PHY_TRANSMIT_PRBS7   0x0230
    #define XDPTX_PHY_CLOCK_SELECT   0x0234
    #define XDPTX_TX_PHY_POWER_DOWN   0x0238
    #define XDPTX_PHY_PRECURSOR_LANE_0   0x023C
    #define XDPTX_PHY_PRECURSOR_LANE_1   0x0240
    #define XDPTX_PHY_PRECURSOR_LANE_2   0x0244
    #define XDPTX_PHY_PRECURSOR_LANE_3   0x0248
    #define XDPTX_PHY_POSTCURSOR_LANE_0   0x024C
    #define XDPTX_PHY_POSTCURSOR_LANE_1   0x0250
    #define XDPTX_PHY_POSTCURSOR_LANE_2   0x0254
    #define XDPTX_PHY_POSTCURSOR_LANE_3   0x0258
    #define XDPTX_PHY_STATUS   0x0280
    #define XDPTX_GT_DRP_COMMAND   0x02A0
    #define XDPTX_GT_DRP_READ_DATA   0x02A4
    #define XDPTX_GT_DRP_CHANNEL_STATUS   0x02A8

    DPTX core registers: DisplayPort audio.
    #define XDPTX_TX_AUDIO_CONTROL   0x0300
    #define XDPTX_TX_AUDIO_CHANNELS   0x0304
    #define XDPTX_TX_AUDIO_INFO_DATA   0x0308
    #define XDPTX_TX_AUDIO_MAUD   0x0328
    #define XDPTX_TX_AUDIO_NAUD   0x032C
    #define XDPTX_TX_AUDIO_EXT_DATA   0x0330

    DPTX core registers: Main stream attributes for MST STREAM2, 3, and 4.
    #define XDPTX_STREAM2_MSA_START   0x0500
    #define XDPTX_STREAM2_MSA_START_OFFSET
    #define XDPTX_STREAM3_MSA_START   0x0550
    #define XDPTX_STREAM3_MSA_START_OFFSET
    #define XDPTX_STREAM4_MSA_START   0x05A0
    #define XDPTX_STREAM4_MSA_START_OFFSET

    DPTX core masks, shifts, and register values.
    #define XDPTX_LINK_BW_SET_162GBPS   0x06
    #define XDPTX_LINK_BW_SET_270GBPS   0x0A
    #define XDPTX_LINK_BW_SET_540GBPS   0x14
    #define XDPTX_LANE_COUNT_SET_1   0x01
    #define XDPTX_LANE_COUNT_SET_2   0x02
    #define XDPTX_LANE_COUNT_SET_4   0x04
    #define XDPTX_TRAINING_PATTERN_SET_OFF   0x0
    #define XDPTX_TRAINING_PATTERN_SET_TP1   0x1
    #define XDPTX_TRAINING_PATTERN_SET_TP2   0x2
    #define XDPTX_TRAINING_PATTERN_SET_TP3   0x3
    #define XDPTX_LINK_QUAL_PATTERN_SET_OFF   0x0
    #define XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST   0x1
    #define XDPTX_LINK_QUAL_PATTERN_SET_SER_MES   0x2
    #define XDPTX_LINK_QUAL_PATTERN_SET_PRBS7   0x3
    #define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK   0x00000001
    #define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK   0x00000002
    #define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK   0x00000004
    #define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK   0x00000008
    #define XDPTX_SOFT_RESET_AUX_MASK   0x00000080
    #define XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK   0x0000000F
    #define XDPTX_TX_MST_CONFIG_MST_EN_MASK   0x00000001
    #define XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK   0x00000002
    #define XDPTX_VERSION_INTER_REV_MASK   0x0000000F
    #define XDPTX_VERSION_CORE_PATCH_MASK   0x00000030
    #define XDPTX_VERSION_CORE_PATCH_SHIFT   8
    #define XDPTX_VERSION_CORE_VER_REV_MASK   0x000000C0
    #define XDPTX_VERSION_CORE_VER_REV_SHIFT   12
    #define XDPTX_VERSION_CORE_VER_MNR_MASK   0x00000F00
    #define XDPTX_VERSION_CORE_VER_MNR_SHIFT   16
    #define XDPTX_VERSION_CORE_VER_MJR_MASK   0x0000F000
    #define XDPTX_VERSION_CORE_VER_MJR_SHIFT   24
    #define XDPTX_CORE_ID_TYPE_MASK   0x0000000F
    #define XDPTX_CORE_ID_TYPE_TX   0x0
    #define XDPTX_CORE_ID_TYPE_RX   0x1
    #define XDPTX_CORE_ID_DP_REV_MASK   0x000000F0
    #define XDPTX_CORE_ID_DP_REV_SHIFT   8
    #define XDPTX_CORE_ID_DP_MNR_VER_MASK   0x00000F00
    #define XDPTX_CORE_ID_DP_MNR_VER_SHIFT   16
    #define XDPTX_CORE_ID_DP_MJR_VER_MASK   0x0000F000
    #define XDPTX_CORE_ID_DP_MJR_VER_SHIFT   24
    #define XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK   0x0000000F
    #define XDPTX_AUX_CMD_MASK   0x00000F00
    #define XDPTX_AUX_CMD_SHIFT   8
    #define XDPTX_AUX_CMD_I2C_WRITE   0x0
    #define XDPTX_AUX_CMD_I2C_READ   0x1
    #define XDPTX_AUX_CMD_I2C_WRITE_STATUS   0x2
    #define XDPTX_AUX_CMD_I2C_WRITE_MOT   0x4
    #define XDPTX_AUX_CMD_I2C_READ_MOT   0x5
    #define XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT   0x6
    #define XDPTX_AUX_CMD_WRITE   0x8
    #define XDPTX_AUX_CMD_READ   0x9
    #define XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN   0x00001000
    #define XDPTX_AUX_CLK_DIVIDER_VAL_MASK   0x0000000F
    #define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK   0x00000F00
    #define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT   8
    #define XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK   0x00000001
    #define XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK   0x00000002
    #define XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK   0x00000004
    #define XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK   0x00000008
    #define XDPTX_AUX_REPLY_CODE_ACK   0x0
    #define XDPTX_AUX_REPLY_CODE_I2C_ACK   0x0
    #define XDPTX_AUX_REPLY_CODE_NACK   0x1
    #define XDPTX_AUX_REPLY_CODE_DEFER   0x2
    #define XDPTX_AUX_REPLY_CODE_I2C_NACK   0x4
    #define XDPTX_AUX_REPLY_CODE_I2C_DEFER   0x8
    #define XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK   0x00000001
    #define XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK   0x00000002
    #define XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK   0x00000004
    #define XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK   0x00000008
    #define XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK   0x00000010
    #define XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK   0x00000020
    #define XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK   0x00000001
    #define XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK   0x00000002
    #define XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK   0x00000004
    #define XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK   0x00000008
    #define XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK   0x00000010
    #define XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK   0x00000020
    #define XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK   0x00000001
    #define XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK   0x00000002
    #define XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK   0x00000004
    #define XDPTX_REPLY_STATUS_REPLY_ERROR_MASK   0x00000008
    #define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK   0x00000FF0
    #define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT   4
    #define XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK   0x00000001
    #define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK   0x00000002
    #define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT   1
    #define XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK   0x00000001
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK   0x00000006
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT   1
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB   0x0
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422   0x1
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444   0x2
    #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK   0x00000008
    #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT   3
    #define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK   0x00000010
    #define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT   4
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_MASK   0x000000E0
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT   5
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC   0x0
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC   0x1
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC   0x2
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC   0x3
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC   0x4
    #define XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK   0x00000001
    #define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK   0x00000006
    #define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT   1
    #define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK   0x0010000
    #define XDPTX_PHY_CONFIG_PHY_RESET_MASK   0x0010001
    #define XDPTX_PHY_CONFIG_GTTX_RESET_MASK   0x0010002
    #define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK   0x0010100
    #define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK   0x0010200
    #define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK   0x0010400
    #define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK   0x0011000
    #define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK   0x001E000
    #define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK   0x0010003
    #define XDPTX_PHY_CLOCK_SELECT_162GBPS   0x1
    #define XDPTX_PHY_CLOCK_SELECT_270GBPS   0x3
    #define XDPTX_PHY_CLOCK_SELECT_540GBPS   0x5
    #define XDPTX_VS_LEVEL_0   0x2
    #define XDPTX_VS_LEVEL_1   0x5
    #define XDPTX_VS_LEVEL_2   0x8
    #define XDPTX_VS_LEVEL_3   0xF
    #define XDPTX_VS_LEVEL_OFFSET   0x4
    #define XDPTX_PE_LEVEL_0   0x00
    #define XDPTX_PE_LEVEL_1   0x0E
    #define XDPTX_PE_LEVEL_2   0x14
    #define XDPTX_PE_LEVEL_3   0x1B
    #define XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK   0x00000003
    #define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK   0x0000000C
    #define XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK   0x00000010
    #define XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK   0x00000020
    #define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK   0x00000020
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK   0x00030000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT   16
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK   0x000C0000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT   18
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK   0x00300000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT   20
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK   0x00C00000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT   22
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK   0x03000000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT   24
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK   0x0C000000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT   26
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK   0x30000000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT   28
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK   0xC0000000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT   30
    #define XDPTX_PHY_STATUS_ALL_LANES_READY_MASK   0x0000003F
    #define XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK   0x000F
    #define XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK   0x0080
    #define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK   0xFF00
    #define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT   16

    DisplayPort Configuration Data: Receiver capability field.
    #define XDPTX_DPCD_REV   0x00000
    #define XDPTX_DPCD_MAX_LINK_RATE   0x00001
    #define XDPTX_DPCD_MAX_LANE_COUNT   0x00002
    #define XDPTX_DPCD_MAX_DOWNSPREAD   0x00003
    #define XDPTX_DPCD_NORP_PWR_V_CAP   0x00004
    #define XDPTX_DPCD_DOWNSP_PRESENT   0x00005
    #define XDPTX_DPCD_ML_CH_CODING_CAP   0x00006
    #define XDPTX_DPCD_DOWNSP_COUNT_MSA_OUI   0x00007
    #define XDPTX_DPCD_RX_PORT0_CAP_0   0x00008
    #define XDPTX_DPCD_RX_PORT0_CAP_1   0x00009
    #define XDPTX_DPCD_RX_PORT1_CAP_0   0x0000A
    #define XDPTX_DPCD_RX_PORT1_CAP_1   0x0000B
    #define XDPTX_DPCD_I2C_SPEED_CTL_CAP   0x0000C
    #define XDPTX_DPCD_EDP_CFG_CAP   0x0000D
    #define XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL   0x0000E
    #define XDPTX_DPCD_ADAPTER_CAP   0x0000F
    #define XDPTX_DPCD_FAUX_CAP   0x00020
    #define XDPTX_DPCD_MSTM_CAP   0x00021
    #define XDPTX_DPCD_NUM_AUDIO_EPS   0x00022
    #define XDPTX_DPCD_AV_GRANULARITY   0x00023
    #define XDPTX_DPCD_AUD_DEC_LAT_7_0   0x00024
    #define XDPTX_DPCD_AUD_DEC_LAT_15_8   0x00025
    #define XDPTX_DPCD_AUD_PP_LAT_7_0   0x00026
    #define XDPTX_DPCD_AUD_PP_LAT_15_8   0x00027
    #define XDPTX_DPCD_VID_INTER_LAT   0x00028
    #define XDPTX_DPCD_VID_PROG_LAT   0x00029
    #define XDPTX_DPCD_REP_LAT   0x0002A
    #define XDPTX_DPCD_AUD_DEL_INS_7_0   0x0002B
    #define XDPTX_DPCD_AUD_DEL_INS_15_8   0x0002C
    #define XDPTX_DPCD_AUD_DEL_INS_23_16   0x0002D
    #define XDPTX_DPCD_GUID   0x00030
    #define XDPTX_DPCD_RX_GTC_VALUE_7_0   0x00054
    #define XDPTX_DPCD_RX_GTC_VALUE_15_8   0x00055
    #define XDPTX_DPCD_RX_GTC_VALUE_23_16   0x00056
    #define XDPTX_DPCD_RX_GTC_VALUE_31_24   0x00057
    #define XDPTX_DPCD_RX_GTC_MSTR_REQ   0x00058
    #define XDPTX_DPCD_RX_GTC_FREQ_LOCK_DONE   0x00059
    #define XDPTX_DPCD_DOWNSP_0_CAP   0x00080
    #define XDPTX_DPCD_DOWNSP_1_CAP   0x00081
    #define XDPTX_DPCD_DOWNSP_2_CAP   0x00082
    #define XDPTX_DPCD_DOWNSP_3_CAP   0x00083
    #define XDPTX_DPCD_DOWNSP_0_DET_CAP   0x00080
    #define XDPTX_DPCD_DOWNSP_1_DET_CAP   0x00084
    #define XDPTX_DPCD_DOWNSP_2_DET_CAP   0x00088
    #define XDPTX_DPCD_DOWNSP_3_DET_CAP   0x0008C

    DisplayPort Configuration Data: Link configuration field.
    #define XDPTX_DPCD_LINK_BW_SET   0x00100
    #define XDPTX_DPCD_LANE_COUNT_SET   0x00101
    #define XDPTX_DPCD_TP_SET   0x00102
    #define XDPTX_DPCD_TRAINING_LANE0_SET   0x00103
    #define XDPTX_DPCD_TRAINING_LANE1_SET   0x00104
    #define XDPTX_DPCD_TRAINING_LANE2_SET   0x00105
    #define XDPTX_DPCD_TRAINING_LANE3_SET   0x00106
    #define XDPTX_DPCD_DOWNSPREAD_CTRL   0x00107
    #define XDPTX_DPCD_ML_CH_CODING_SET   0x00108
    #define XDPTX_DPCD_I2C_SPEED_CTL_SET   0x00109
    #define XDPTX_DPCD_EDP_CFG_SET   0x0010A
    #define XDPTX_DPCD_LINK_QUAL_LANE0_SET   0x0010B
    #define XDPTX_DPCD_LINK_QUAL_LANE1_SET   0x0010C
    #define XDPTX_DPCD_LINK_QUAL_LANE2_SET   0x0010D
    #define XDPTX_DPCD_LINK_QUAL_LANE3_SET   0x0010E
    #define XDPTX_DPCD_TRAINING_LANE0_1_SET2   0x0010F
    #define XDPTX_DPCD_TRAINING_LANE2_3_SET2   0x00110
    #define XDPTX_DPCD_MSTM_CTRL   0x00111
    #define XDPTX_DPCD_AUDIO_DELAY_7_0   0x00112
    #define XDPTX_DPCD_AUDIO_DELAY_15_8   0x00113
    #define XDPTX_DPCD_AUDIO_DELAY_23_6   0x00114
    #define XDPTX_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED   0x00118
    #define XDPTX_DPCD_FAUX_MODE_CTRL   0x00120
    #define XDPTX_DPCD_FAUX_FORWARD_CH_DRIVE_SET   0x00121
    #define XDPTX_DPCD_BACK_CH_STATUS   0x00122
    #define XDPTX_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT   0x00123
    #define XDPTX_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME   0x00125
    #define XDPTX_DPCD_TX_GTC_VALUE_7_0   0x00154
    #define XDPTX_DPCD_TX_GTC_VALUE_15_8   0x00155
    #define XDPTX_DPCD_TX_GTC_VALUE_23_16   0x00156
    #define XDPTX_DPCD_TX_GTC_VALUE_31_24   0x00157
    #define XDPTX_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN   0x00158
    #define XDPTX_DPCD_TX_GTC_FREQ_LOCK_DONE   0x00159
    #define XDPTX_DPCD_ADAPTER_CTRL   0x001A0
    #define XDPTX_DPCD_BRANCH_DEVICE_CTRL   0x001A1
    #define XDPTX_DPCD_PAYLOAD_ALLOCATE_SET   0x001C0
    #define XDPTX_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT   0x001C1
    #define XDPTX_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT   0x001C2

    DisplayPort Configuration Data: Link/sink status field.
    #define XDPTX_DPCD_SINK_COUNT   0x00200
    #define XDPTX_DPCD_DEVICE_SERVICE_IRQ   0x00201
    #define XDPTX_DPCD_STATUS_LANE_0_1   0x00202
    #define XDPTX_DPCD_STATUS_LANE_2_3   0x00203
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED   0x00204
    #define XDPTX_DPCD_SINK_STATUS   0x00205
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_1   0x00206
    #define XDPTX_DPCD_ADJ_REQ_LANE_2_3   0x00207
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_0   0x00208
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_1   0x00209
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_2   0x0020A
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_3   0x0020B
    #define XDPTX_DPCD_ADJ_REQ_PC2   0x0020C
    #define XDPTX_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT   0x0020D
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_0   0x00210
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_1   0x00212
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_2   0x00214
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_3   0x00216

    DisplayPort Configuration Data: Automated testing sub-field.
    #define XDPTX_DPCD_FAUX_FORWARD_CH_STATUS   0x00280
    #define XDPTX_DPCD_FAUX_BACK_CH_DRIVE_SET   0x00281
    #define XDPTX_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL   0x00282
    #define XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS   0x002C0
    #define XDPTX_DPCD_VC_PAYLOAD_ID_SLOT(SlotNum)   (XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum)

    DisplayPort Configuration Data: Sink control field.
    #define XDPTX_DPCD_SET_POWER_DP_PWR_VOLTAGE   0x00600

    DisplayPort Configuration Data: Sideband message buffers.
    #define XDPTX_DPCD_DOWN_REQ   0x01000
    #define XDPTX_DPCD_UP_REP   0x01200
    #define XDPTX_DPCD_DOWN_REP   0x01400
    #define XDPTX_DPCD_UP_REQ   0x01600

    DisplayPort Configuration Data: Event status indicator field.
    #define XDPTX_DPCD_SINK_COUNT_ESI   0x02002
    #define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x02003
    #define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x02004
    #define XDPTX_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0   0x02005
    #define XDPTX_DPCD_SINK_LANE0_1_STATUS   0x0200C
    #define XDPTX_DPCD_SINK_LANE2_3_STATUS   0x0200D
    #define XDPTX_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI   0x0200E
    #define XDPTX_DPCD_SINK_STATUS_ESI   0x0200F

    DisplayPort Configuration Data: Field addresses and sizes.
    #define XDPTX_DPCD_RECEIVER_CAP_FIELD_START   XDPTX_DPCD_REV
    #define XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE   0x100
    #define XDPTX_DPCD_LINK_CFG_FIELD_START   XDPTX_DPCD_LINK_BW_SET
    #define XDPTX_DPCD_LINK_CFG_FIELD_SIZE   0x100
    #define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_START   XDPTX_DPCD_SINK_COUNT
    #define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_SIZE   0x17

    DisplayPort Configuration Data: Receiver capability field masks,
    shifts, and register values. 

    #define XDPTX_DPCD_REV_MNR_MASK   0x0F
    #define XDPTX_DPCD_REV_MJR_MASK   0xF0
    #define XDPTX_DPCD_REV_MJR_SHIFT   4
    #define XDPTX_DPCD_MAX_LINK_RATE_162GBPS   0x06
    #define XDPTX_DPCD_MAX_LINK_RATE_270GBPS   0x0A
    #define XDPTX_DPCD_MAX_LINK_RATE_540GBPS   0x14
    #define XDPTX_DPCD_MAX_LANE_COUNT_MASK   0x1F
    #define XDPTX_DPCD_MAX_LANE_COUNT_1   0x01
    #define XDPTX_DPCD_MAX_LANE_COUNT_2   0x02
    #define XDPTX_DPCD_MAX_LANE_COUNT_4   0x04
    #define XDPTX_DPCD_TPS3_SUPPORT_MASK   0x40
    #define XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK   0x80
    #define XDPTX_DPCD_MAX_DOWNSPREAD_MASK   0x01
    #define XDPTX_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK   0x40
    #define XDPTX_DPCD_DOWNSP_PRESENT_MASK   0x01
    #define XDPTX_DPCD_DOWNSP_TYPE_MASK   0x06
    #define XDPTX_DPCD_DOWNSP_TYPE_SHIFT   1
    #define XDPTX_DPCD_DOWNSP_TYPE_DP   0x0
    #define XDPTX_DPCD_DOWNSP_TYPE_AVGA_ADVII   0x1
    #define XDPTX_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP   0x2
    #define XDPTX_DPCD_DOWNSP_TYPE_OTHERS   0x3
    #define XDPTX_DPCD_DOWNSP_FORMAT_CONV_MASK   0x08
    #define XDPTX_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK   0x10
    #define XDPTX_DPCD_ML_CH_CODING_MASK   0x01
    #define XDPTX_DPCD_DOWNSP_COUNT_MASK   0x0F
    #define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_MASK   0x40
    #define XDPTX_DPCD_OUI_SUPPORT_MASK   0x80
    #define XDPTX_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK   0x02
    #define XDPTX_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK   0x04
    #define XDPTX_DPCD_I2C_SPEED_CTL_NONE   0x00
    #define XDPTX_DPCD_I2C_SPEED_CTL_1KBIPS   0x01
    #define XDPTX_DPCD_I2C_SPEED_CTL_5KBIPS   0x02
    #define XDPTX_DPCD_I2C_SPEED_CTL_10KBIPS   0x04
    #define XDPTX_DPCD_I2C_SPEED_CTL_100KBIPS   0x08
    #define XDPTX_DPCD_I2C_SPEED_CTL_400KBIPS   0x10
    #define XDPTX_DPCD_I2C_SPEED_CTL_1MBIPS   0x20
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_100_400US   0x00
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_4MS   0x01
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_8MS   0x02
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_12MS   0x03
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_16MS   0x04
    #define XDPTX_DPCD_FAUX_CAP_MASK   0x01
    #define XDPTX_DPCD_MST_CAP_MASK   0x01
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_MASK   0x07
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DP   0x0
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_AVGA   0x1
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DVI   0x2
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_HDMI   0x3
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_OTHERS   0x4
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DPPP   0x5
    #define XDPTX_DPCD_DOWNSP_X_CAP_HPD_MASK   0x80
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK   0xF0
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT   4
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60   0x1
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50   0x2
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60   0x3
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50   0x4
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60   0x5
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50   0x7
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK   0x03
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_8   0x0
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_10   0x1
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_12   0x2
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_16   0x3
    #define XDPTX_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK   0x01
    #define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK   0x02
    #define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK   0x04

    DisplayPort Configuration Data: Link configuration field masks,
    shifts, and register values. 

    #define XDPTX_DPCD_LINK_BW_SET_162GBPS   0x06
    #define XDPTX_DPCD_LINK_BW_SET_270GBPS   0x0A
    #define XDPTX_DPCD_LINK_BW_SET_540GBPS   0x14
    #define XDPTX_DPCD_LANE_COUNT_SET_MASK   0x1F
    #define XDPTX_DPCD_LANE_COUNT_SET_1   0x01
    #define XDPTX_DPCD_LANE_COUNT_SET_2   0x02
    #define XDPTX_DPCD_LANE_COUNT_SET_4   0x04
    #define XDPTX_DPCD_ENHANCED_FRAME_EN_MASK   0x80
    #define XDPTX_DPCD_TP_SEL_MASK   0x03
    #define XDPTX_DPCD_TP_SEL_OFF   0x0
    #define XDPTX_DPCD_TP_SEL_TP1   0x1
    #define XDPTX_DPCD_TP_SEL_TP2   0x2
    #define XDPTX_DPCD_TP_SEL_TP3   0x3
    #define XDPTX_DPCD_TP_SET_LQP_MASK   0x06
    #define XDPTX_DPCD_TP_SET_LQP_SHIFT   2
    #define XDPTX_DPCD_TP_SET_LQP_OFF   0x0
    #define XDPTX_DPCD_TP_SET_LQP_D102_TEST   0x1
    #define XDPTX_DPCD_TP_SET_LQP_SER_MES   0x2
    #define XDPTX_DPCD_TP_SET_LQP_PRBS7   0x3
    #define XDPTX_DPCD_TP_SET_REC_CLK_OUT_EN_MASK   0x10
    #define XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK   0x20
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_MASK   0xC0
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_SHIFT   6
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE   0x0
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE   0x1
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_ISE   0x2
    #define XDPTX_DPCD_TRAINING_LANEX_SET_VS_MASK   0x03
    #define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK   0x04
    #define XDPTX_DPCD_TRAINING_LANEX_SET_PE_MASK   0x18
    #define XDPTX_DPCD_TRAINING_LANEX_SET_PE_SHIFT   3
    #define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK   0x20
    #define XDPTX_DPCD_SPREAD_AMP_MASK   0x10
    #define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK   0x80
    #define XDPTX_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK   0x03
    #define XDPTX_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK   0x04
    #define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK   0x30
    #define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT   4
    #define XDPTX_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK   0x40
    #define XDPTX_DPCD_MST_EN_MASK   0x01
    #define XDPTX_DPCD_UP_REQ_EN_MASK   0x02
    #define XDPTX_DPCD_UP_IS_SRC_MASK   0x03

    DisplayPort Configuration Data: Link/sink status field masks, shifts,
    and register values. 

    #define XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK   0x01
    #define XDPTX_DPCD_STATUS_LANE_0_CE_DONE_MASK   0x02
    #define XDPTX_DPCD_STATUS_LANE_0_SL_DONE_MASK   0x04
    #define XDPTX_DPCD_STATUS_LANE_1_CR_DONE_MASK   0x10
    #define XDPTX_DPCD_STATUS_LANE_1_CE_DONE_MASK   0x20
    #define XDPTX_DPCD_STATUS_LANE_1_SL_DONE_MASK   0x40
    #define XDPTX_DPCD_STATUS_LANE_2_CR_DONE_MASK   0x01
    #define XDPTX_DPCD_STATUS_LANE_2_CE_DONE_MASK   0x02
    #define XDPTX_DPCD_STATUS_LANE_2_SL_DONE_MASK   0x04
    #define XDPTX_DPCD_STATUS_LANE_3_CR_DONE_MASK   0x10
    #define XDPTX_DPCD_STATUS_LANE_3_CE_DONE_MASK   0x20
    #define XDPTX_DPCD_STATUS_LANE_3_SL_DONE_MASK   0x40
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK   0x01
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK   0x40
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK   0x80
    #define XDPTX_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK   0x01
    #define XDPTX_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK   0x02
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK   0x03
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK   0x0C
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT   2
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK   0x30
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT   4
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK   0xC0
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT   6
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_0_MASK   0x03
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_MASK   0x0C
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT   2
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_MASK   0x30
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT   4
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_MASK   0xC0
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT   6

    Extended Display Identification Data: Field addresses and sizes.
    #define XDPTX_EDID_ADDR   0x50
    #define XDPTX_EDID_SIZE   128
    #define XDPTX_EDID_DTD_DD(Num)   (0x36 + (18 * Num))
    #define XDPTX_EDID_PTM   XDPTX_EDID_DTD_DD(0)

    Extended Display Identification Data: Register offsets for the
    Detailed Timing Descriptor (DTD). 

    #define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB   0x00
    #define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB   0x01
    #define XDPTX_EDID_DTD_HRES_LSB   0x02
    #define XDPTX_EDID_DTD_HBLANK_LSB   0x03
    #define XDPTX_EDID_DTD_HRES_HBLANK_U4   0x04
    #define XDPTX_EDID_DTD_VRES_LSB   0x05
    #define XDPTX_EDID_DTD_VBLANK_LSB   0x06
    #define XDPTX_EDID_DTD_VRES_VBLANK_U4   0x07
    #define XDPTX_EDID_DTD_HFPORCH_LSB   0x08
    #define XDPTX_EDID_DTD_HSPW_LSB   0x09
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4   0x0A
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2   0x0B
    #define XDPTX_EDID_DTD_HIMGSIZE_MM_LSB   0x0C
    #define XDPTX_EDID_DTD_VIMGSIZE_MM_LSB   0x0D
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4   0x0E
    #define XDPTX_EDID_DTD_HBORDER   0x0F
    #define XDPTX_EDID_DTD_VBORDER   0x10
    #define XDPTX_EDID_DTD_SIGNAL   0x11

    Extended Display Identification Data: Masks, shifts, and register
    values. 

    #define XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK   0x0F
    #define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK   0xF0
    #define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT   4
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK   0x0F
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK   0xF0
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT   4
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK   0xC0
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK   0x30
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK   0x0C
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK   0x03
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT   6
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT   4
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT   2
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK   0x0F
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK   0xF0
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT   4
    #define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_MASK   0x02
    #define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_MASK   0x04
    #define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_SHIFT   1
    #define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_SHIFT   2

    Register access macro definitions.
    #define XDptx_In32   Xil_In32
    #define XDptx_Out32   Xil_Out32

    Defines
    #define XDPTX_VC_PAYLOAD_BUFFER_ADDR   0x0800
    #define XDptx_ReadReg(BaseAddress, RegOffset)   XDptx_In32((BaseAddress) + (RegOffset))
    #define XDptx_WriteReg(BaseAddress, RegOffset, Data)   XDptx_Out32((BaseAddress) + (RegOffset), (Data))
    
+
    Define Documentation
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_ADDRESS   0x0108          
    
+
    
+
    
+
+
    
+Specifies the address of current AUX command. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CLK_DIVIDER   0x010C          
    
+
    
+
    
+
+
    
+Clock divider value for generating the internal 1MHz clock. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK   0x00000F00          
    
+
    
+
    
+
+
    
+AUX (noise) signal width filter. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT   8          
    
+
    
+
    
+
+
    
+Shift bits for AUX signal width filter. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CLK_DIVIDER_VAL_MASK   0x0000000F          
    
+
    
+
    
+
+
    
+Clock divider value. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CMD   0x0100          
    
+
    
+
    
+
+
    
+Initiates AUX commands. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN   0x00001000          
    
+
    
+
    
+
+
    
+Address only transfer enable (STOP will be sent after command). 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CMD_I2C_READ   0x1          
    
+
    
+
    
+
+
    
+I2C-over-AUX read command. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CMD_I2C_READ_MOT   0x5          
    
+
    
+
    
+
+
    
+I2C-over-AUX read MOT (middle-of-transaction) command. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CMD_I2C_WRITE   0x0          
    
+
    
+
    
+
+
    
+I2C-over-AUX write command. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CMD_I2C_WRITE_MOT   0x4          
    
+
    
+
    
+
+
    
+I2C-over-AUX write MOT (middle-of-transaction) command. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CMD_I2C_WRITE_STATUS   0x2          
    
+
    
+
    
+
+
    
+I2C-over-AUX write status command. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT   0x6          
    
+
    
+
    
+
+
    
+I2C-over-AUX write status MOT (middle-of- transaction) command. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CMD_MASK   0x00000F00          
    
+
    
+
    
+
+
    
+AUX command. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK   0x0000000F          
    
+
    
+
    
+
+
    
+Number of bytes to transfer with the current AUX command. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CMD_READ   0x9          
    
+
    
+
    
+
+
    
+AUX read command. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CMD_SHIFT   8          
    
+
    
+
    
+
+
    
+Shift bits for command. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_CMD_WRITE   0x8          
    
+
    
+
    
+
+
    
+AUX write command. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_REPLY_CODE   0x0138          
    
+
    
+
    
+
+
    
+Reply code received from the most recent AUX command. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_REPLY_CODE_ACK   0x0          
    
+
    
+
    
+
+
    
+AUX command ACKed. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_REPLY_CODE_DEFER   0x2          
    
+
    
+
    
+
+
    
+AUX command deferred. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_REPLY_CODE_I2C_ACK   0x0          
    
+
    
+
    
+
+
    
+I2C-over-AUX command not ACKed. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_REPLY_CODE_I2C_DEFER   0x8          
    
+
    
+
    
+
+
    
+I2C-over-AUX command deferred. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_REPLY_CODE_I2C_NACK   0x4          
    
+
    
+
    
+
+
    
+I2C-over-AUX command not ACKed. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_REPLY_CODE_NACK   0x1          
    
+
    
+
    
+
+
    
+AUX command not ACKed. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_REPLY_COUNT   0x013C          
    
+
    
+
    
+
+
    
+Number of reply transactions receieved over AUX. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_REPLY_DATA   0x0134          
    
+
    
+
    
+
+
    
+Reply data received during the AUX reply. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_AUX_WRITE_FIFO   0x0104          
    
+
    
+
    
+
+
    
+Write data for the current AUX command. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_CORE_ID   0x00FC          
    
+
    
+
    
+
+
    
+DisplayPort revision. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_CORE_ID_DP_MJR_VER_MASK   0x0000F000          
    
+
    
+
    
+
+
    
+DisplayPort protocol major version. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_CORE_ID_DP_MJR_VER_SHIFT   24          
    
+
    
+
    
+
+
    
+Shift bits for DisplayPort protocol major version. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_CORE_ID_DP_MNR_VER_MASK   0x00000F00          
    
+
    
+
    
+
+
    
+DisplayPort protocol minor version. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_CORE_ID_DP_MNR_VER_SHIFT   16          
    
+
    
+
    
+
+
    
+Shift bits for DisplayPort protocol major version. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_CORE_ID_DP_REV_MASK   0x000000F0          
    
+
    
+
    
+
+
    
+DisplayPort protocol revision. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_CORE_ID_DP_REV_SHIFT   8          
    
+
    
+
    
+
+
    
+Shift bits for DisplayPort protocol revision. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_CORE_ID_TYPE_MASK   0x0000000F          
    
+
    
+
    
+
+
    
+Core type. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_CORE_ID_TYPE_RX   0x1          
    
+
    
+
    
+
+
    
+Core is a receiver. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_CORE_ID_TYPE_TX   0x0          
    
+
    
+
    
+
+
    
+Core is a transmitter. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DOWNSPREAD_CTRL   0x0018          
    
+
    
+
    
+
+
    
+Enable a 0.5% spreading of the clock. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADAPTER_CAP   0x0000F          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADAPTER_CTRL   0x001A0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_1   0x00206          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK   0x0C          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT   2          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK   0x03          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK   0xC0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT   6          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK   0x30          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT   4          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_LANE_2_3   0x00207          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_PC2   0x0020C          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_0_MASK   0x03          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_MASK   0x0C          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT   2          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_MASK   0x30          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT   4          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_MASK   0xC0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT   6          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_AUD_DEC_LAT_15_8   0x00025          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_AUD_DEC_LAT_7_0   0x00024          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_AUD_DEL_INS_15_8   0x0002C          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_AUD_DEL_INS_23_16   0x0002D          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_AUD_DEL_INS_7_0   0x0002B          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_AUD_PP_LAT_15_8   0x00027          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_AUD_PP_LAT_7_0   0x00026          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_AUDIO_DELAY_15_8   0x00113          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_AUDIO_DELAY_23_6   0x00114          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_AUDIO_DELAY_7_0   0x00112          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_AV_GRANULARITY   0x00023          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_BACK_CH_STATUS   0x00122          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_BRANCH_DEVICE_CTRL   0x001A1          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DEVICE_SERVICE_IRQ   0x00201          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWN_REP   0x01400          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWN_REQ   0x01000          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_0_CAP   0x00080          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_0_DET_CAP   0x00080          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_1_CAP   0x00081          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_1_DET_CAP   0x00084          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_2_CAP   0x00082          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_2_DET_CAP   0x00088          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_3_CAP   0x00083          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_3_DET_CAP   0x0008C          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_COUNT_MASK   0x0F          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_COUNT_MSA_OUI   0x00007          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK   0x10          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_FORMAT_CONV_MASK   0x08          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_PRESENT   0x00005          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_PRESENT_MASK   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_TYPE_AVGA_ADVII   0x1          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_TYPE_DP   0x0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP   0x2          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_TYPE_MASK   0x06          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_TYPE_OTHERS   0x3          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_TYPE_SHIFT   1          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_HPD_MASK   0x80          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50   0x7          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60   0x5          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50   0x4          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60   0x3          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50   0x2          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60   0x1          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK   0xF0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT   4          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_AVGA   0x1          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DP   0x0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DPPP   0x5          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DVI   0x2          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_HDMI   0x3          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_MASK   0x07          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_OTHERS   0x4          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK   0x02          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK   0x04          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_10   0x1          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_12   0x2          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_16   0x3          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_8   0x0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK   0x03          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_DOWNSPREAD_CTRL   0x00107          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_EDP_CFG_CAP   0x0000D          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_EDP_CFG_SET   0x0010A          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ENHANCED_FRAME_EN_MASK   0x80          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK   0x80          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_FAUX_BACK_CH_DRIVE_SET   0x00281          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL   0x00282          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT   0x00123          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME   0x00125          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_FAUX_CAP   0x00020          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_FAUX_CAP_MASK   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_FAUX_FORWARD_CH_DRIVE_SET   0x00121          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_FAUX_FORWARD_CH_STATUS   0x00280          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT   0x0020D          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_FAUX_MODE_CTRL   0x00120          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_GUID   0x00030          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_I2C_SPEED_CTL_100KBIPS   0x08          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_I2C_SPEED_CTL_10KBIPS   0x04          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_I2C_SPEED_CTL_1KBIPS   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_I2C_SPEED_CTL_1MBIPS   0x20          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_I2C_SPEED_CTL_400KBIPS   0x10          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_I2C_SPEED_CTL_5KBIPS   0x02          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_I2C_SPEED_CTL_CAP   0x0000C          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_I2C_SPEED_CTL_NONE   0x00          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_I2C_SPEED_CTL_SET   0x00109          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED   0x00204          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK   0x40          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK   0x80          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LANE_COUNT_SET   0x00101          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LANE_COUNT_SET_1   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LANE_COUNT_SET_2   0x02          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LANE_COUNT_SET_4   0x04          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LANE_COUNT_SET_MASK   0x1F          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LINK_BW_SET   0x00100          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LINK_BW_SET_162GBPS   0x06          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LINK_BW_SET_270GBPS   0x0A          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LINK_BW_SET_540GBPS   0x14          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LINK_CFG_FIELD_SIZE   0x100          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LINK_CFG_FIELD_START   XDPTX_DPCD_LINK_BW_SET          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LINK_QUAL_LANE0_SET   0x0010B          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LINK_QUAL_LANE1_SET   0x0010C          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LINK_QUAL_LANE2_SET   0x0010D          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LINK_QUAL_LANE3_SET   0x0010E          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_SIZE   0x17          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_START   XDPTX_DPCD_SINK_COUNT          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MAX_DOWNSPREAD   0x00003          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MAX_DOWNSPREAD_MASK   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MAX_LANE_COUNT   0x00002          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MAX_LANE_COUNT_1   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MAX_LANE_COUNT_2   0x02          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MAX_LANE_COUNT_4   0x04          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MAX_LANE_COUNT_MASK   0x1F          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MAX_LINK_RATE   0x00001          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MAX_LINK_RATE_162GBPS   0x06          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MAX_LINK_RATE_270GBPS   0x0A          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MAX_LINK_RATE_540GBPS   0x14          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ML_CH_CODING_CAP   0x00006          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ML_CH_CODING_MASK   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_ML_CH_CODING_SET   0x00108          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK   0x80          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_MASK   0x40          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MST_CAP_MASK   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MST_EN_MASK   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MSTM_CAP   0x00021          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_MSTM_CTRL   0x00111          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK   0x40          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_NORP_PWR_V_CAP   0x00004          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_NUM_AUDIO_EPS   0x00022          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_OUI_SUPPORT_MASK   0x80          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_PAYLOAD_ALLOCATE_SET   0x001C0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT   0x001C1          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT   0x001C2          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS   0x002C0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE   0x100          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_RECEIVER_CAP_FIELD_START   XDPTX_DPCD_REV          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_REP_LAT   0x0002A          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_REV   0x00000          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_REV_MJR_MASK   0xF0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_REV_MJR_SHIFT   4          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_REV_MNR_MASK   0x0F          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_RX_GTC_FREQ_LOCK_DONE   0x00059          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_RX_GTC_MSTR_REQ   0x00058          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_RX_GTC_VALUE_15_8   0x00055          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_RX_GTC_VALUE_23_16   0x00056          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_RX_GTC_VALUE_31_24   0x00057          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_RX_GTC_VALUE_7_0   0x00054          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN   0x00158          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_RX_PORT0_CAP_0   0x00008          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_RX_PORT0_CAP_1   0x00009          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_RX_PORT1_CAP_0   0x0000A          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_RX_PORT1_CAP_1   0x0000B          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK   0x04          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK   0x02          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SET_POWER_DP_PWR_VOLTAGE   0x00600          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI   0x0200E          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SINK_COUNT   0x00200          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SINK_COUNT_ESI   0x02002          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x02003          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x02004          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SINK_LANE0_1_STATUS   0x0200C          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SINK_LANE2_3_STATUS   0x0200D          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0   0x02005          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SINK_STATUS   0x00205          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SINK_STATUS_ESI   0x0200F          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK   0x02          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SPREAD_AMP_MASK   0x10          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_STATUS_LANE_0_1   0x00202          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_STATUS_LANE_0_CE_DONE_MASK   0x02          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_STATUS_LANE_0_SL_DONE_MASK   0x04          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_STATUS_LANE_1_CE_DONE_MASK   0x20          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_STATUS_LANE_1_CR_DONE_MASK   0x10          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_STATUS_LANE_1_SL_DONE_MASK   0x40          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_STATUS_LANE_2_3   0x00203          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_STATUS_LANE_2_CE_DONE_MASK   0x02          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_STATUS_LANE_2_CR_DONE_MASK   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_STATUS_LANE_2_SL_DONE_MASK   0x04          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_STATUS_LANE_3_CE_DONE_MASK   0x20          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_STATUS_LANE_3_CR_DONE_MASK   0x10          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_STATUS_LANE_3_SL_DONE_MASK   0x40          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_0   0x00210          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_1   0x00212          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_2   0x00214          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_3   0x00216          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SEL_MASK   0x03          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SEL_OFF   0x0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SEL_TP1   0x1          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SEL_TP2   0x2          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SEL_TP3   0x3          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SET   0x00102          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SET_LQP_D102_TEST   0x1          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SET_LQP_MASK   0x06          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SET_LQP_OFF   0x0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SET_LQP_PRBS7   0x3          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SET_LQP_SER_MES   0x2          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SET_LQP_SHIFT   2          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SET_REC_CLK_OUT_EN_MASK   0x10          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK   0x20          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE   0x1          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE   0x0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_ISE   0x2          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_MASK   0xC0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_SHIFT   6          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TPS3_SUPPORT_MASK   0x40          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_100_400US   0x00          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_12MS   0x03          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_16MS   0x04          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_4MS   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAIN_AUX_RD_INT_8MS   0x02          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL   0x0000E          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANE0_1_SET2   0x0010F          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANE0_SET   0x00103          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANE1_SET   0x00104          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANE2_3_SET2   0x00110          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANE2_SET   0x00105          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANE3_SET   0x00106          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK   0x04          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK   0x03          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK   0x40          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK   0x30          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT   4          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK   0x20          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK   0x04          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANEX_SET_PE_MASK   0x18          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANEX_SET_PE_SHIFT   3          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_LANEX_SET_VS_MASK   0x03          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_0   0x00208          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_1   0x00209          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_2   0x0020A          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TRAINING_SCORE_LANE_3   0x0020B          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TX_GTC_FREQ_LOCK_DONE   0x00159          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TX_GTC_VALUE_15_8   0x00155          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TX_GTC_VALUE_23_16   0x00156          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TX_GTC_VALUE_31_24   0x00157          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_TX_GTC_VALUE_7_0   0x00154          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_UP_IS_SRC_MASK   0x03          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_UP_REP   0x01200          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_UP_REQ   0x01600          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_UP_REQ_EN_MASK   0x02          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED   0x00118          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    #define XDPTX_DPCD_VC_PAYLOAD_ID_SLOT          (SlotNum            )    (XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum)
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_VID_INTER_LAT   0x00028          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_DPCD_VID_PROG_LAT   0x00029          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_ADDR   0x50          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    #define XDPTX_EDID_DTD_DD          (Num            )    (0x36 + (18 * Num))
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_HBLANK_LSB   0x03          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_HBORDER   0x0F          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_HFPORCH_LSB   0x08          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_HIMGSIZE_MM_LSB   0x0C          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_HRES_HBLANK_U4   0x04          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_HRES_LSB   0x02          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_HSPW_LSB   0x09          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB   0x00          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB   0x01          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_SIGNAL   0x11          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_MASK   0x02          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_SHIFT   1          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_MASK   0x04          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_SHIFT   2          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_VBLANK_LSB   0x06          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_VBORDER   0x10          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4   0x0A          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK   0xF0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT   4          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK   0x0F          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_VIMGSIZE_MM_LSB   0x0D          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_VRES_LSB   0x05          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_VRES_VBLANK_U4   0x07          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2   0x0B          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK   0xC0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT   6          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK   0x30          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT   4          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK   0x0C          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT   2          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK   0x03          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4   0x0E          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK   0xF0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT   4          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK   0x0F          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK   0x0F          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK   0xF0          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT   4          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_PTM   XDPTX_EDID_DTD_DD(0)          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_EDID_SIZE   128          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_ENABLE   0x0080          
    
+
    
+
    
+
+
    
+Enable the basic operations of the DisplayPort TX core or output stuffing symbols if disabled. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_ENABLE_MAIN_STREAM   0x0084          
    
+
    
+
    
+
+
    
+Enable transmission of main link video info. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_ENABLE_SEC_STREAM   0x0088          
    
+
    
+
    
+
+
    
+Enable the transmission of secondary link info. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_ENHANCED_FRAME_EN   0x0008          
    
+
    
+
    
+
+
    
+Enable enhanced framing symbol sequence. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_FORCE_SCRAMBLER_RESET   0x00C0          
    
+
    
+
    
+
+
    
+Force a scrambler reset. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_FRAC_BYTES_PER_TU   0x01C8          
    
+
    
+
    
+
+
    
+The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_GT_DRP_CHANNEL_STATUS   0x02A8          
    
+
    
+
    
+
+
    
+Provides access to GT DRP channel status. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_GT_DRP_COMMAND   0x02A0          
    
+
    
+
    
+
+
    
+Provides acces to the GT DRP ports. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK   0x000F          
    
+
    
+
    
+
+
    
+DRP address. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK   0x0080          
    
+
    
+
    
+
+
    
+DRP read/write command (Read=0, Write=1). 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK   0xFF00          
    
+
    
+
    
+
+
    
+DRP write data. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT   16          
    
+
    
+
    
+
+
    
+Shift bits for DRP write data. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_GT_DRP_READ_DATA   0x02A4          
    
+
    
+
    
+
+
    
+Provides access to GT DRP read data. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_HPD_DURATION   0x0150          
    
+
    
+
    
+
+
    
+Duration of the HPD pulse in microseconds. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDptx_In32   Xil_In32          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INIT_WAIT   0x01CC          
    
+
    
+
    
+
+
    
+Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_MASK   0x0144          
    
+
    
+
    
+
+
    
+Masks the specified interrupt sources. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK   0x00000020          
    
+
    
+
    
+
+
    
+Mask extended packet transmit interrupt. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK   0x00000002          
    
+
    
+
    
+
+
    
+Mask HPD event interrupt. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK   0x00000001          
    
+
    
+
    
+
+
    
+Mask HPD IRQ interrupt. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK   0x00000010          
    
+
    
+
    
+
+
    
+Mask HPD pulse detected interrupt. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK   0x00000004          
    
+
    
+
    
+
+
    
+Mask reply received interrupt. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK   0x00000008          
    
+
    
+
    
+
+
    
+Mask reply received interrupt. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_SIG_STATE   0x0130          
    
+
    
+
    
+
+
    
+The raw signal values for interupt events. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK   0x00000001          
    
+
    
+
    
+
+
    
+Raw state of the HPD pin on the DP connector. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK   0x00000004          
    
+
    
+
    
+
+
    
+A reply is currently being received. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK   0x00000008          
    
+
    
+
    
+
+
    
+A reply timeout has occurred. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK   0x00000002          
    
+
    
+
    
+
+
    
+A request is currently being sent. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_STATUS   0x0140          
    
+
    
+
    
+
+
    
+Status for interrupt events. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK   0x00000020          
    
+
    
+
    
+
+
    
+Extended packet has been transmitted and the core is ready to accept a new packet. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK   0x00000002          
    
+
    
+
    
+
+
    
+Detected the presence of the HPD signal. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK   0x00000001          
    
+
    
+
    
+
+
    
+Detected an IRQ framed with the proper timing on the HPD signal. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK   0x00000010          
    
+
    
+
    
+
+
    
+A pulse on the HPD line was detected. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK   0x00000004          
    
+
    
+
    
+
+
    
+An AUX reply transaction has been detected. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK   0x00000008          
    
+
    
+
    
+
+
    
+A reply timeout has occurred. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_LANE_COUNT_SET   0x0004          
    
+
    
+
    
+
+
    
+Set lane count setting. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_LANE_COUNT_SET_1   0x01          
    
+
    
+
    
+
+
    
+Lane count of 1. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_LANE_COUNT_SET_2   0x02          
    
+
    
+
    
+
+
    
+Lane count of 2. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_LANE_COUNT_SET_4   0x04          
    
+
    
+
    
+
+
    
+Lane count of 4. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_LINK_BW_SET   0x0000          
    
+
    
+
    
+
+
    
+Set main link bandwidth setting. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_LINK_BW_SET_162GBPS   0x06          
    
+
    
+
    
+
+
    
+1.62 Gbps link rate. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_LINK_BW_SET_270GBPS   0x0A          
    
+
    
+
    
+
+
    
+2.70 Gbps link rate. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_LINK_BW_SET_540GBPS   0x14          
    
+
    
+
    
+
+
    
+5.40 Gbps link rate. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_LINK_QUAL_PATTERN_SET   0x0010          
    
+
    
+
    
+
+
    
+Transmit the link quality pattern. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST   0x1          
    
+
    
+
    
+
+
    
+D10.2 unscrambled test pattern transmitted. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_LINK_QUAL_PATTERN_SET_OFF   0x0          
    
+
    
+
    
+
+
    
+Link quality test pattern not transmitted. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_LINK_QUAL_PATTERN_SET_PRBS7   0x3          
    
+
    
+
    
+
+
    
+Pseudo random bit sequence 7 transmitted. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_LINK_QUAL_PATTERN_SET_SER_MES   0x2          
    
+
    
+
    
+
+
    
+Symbol error rate measurement pattern transmitted. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_M_VID   0x01AC          
    
+
    
+
    
+
+
    
+M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAM_HRES   0x0194          
    
+
    
+
    
+
+
    
+Number of active pixels per line (the horizontal resolution). 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAM_HSTART   0x019C          
    
+
    
+
    
+
+
    
+Number of clocks between the leading edge of the horizontal sync and the start of active data. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAM_HSWIDTH   0x018C          
    
+
    
+
    
+
+
    
+Width of the horizontal sync pulse. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAM_HTOTAL   0x0180          
    
+
    
+
    
+
+
    
+Total number of clocks in the horizontal framing period. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAM_INTERLACED   0x01C0          
    
+
    
+
    
+
+
    
+Video is interlaced. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAM_MISC0   0x01A4          
    
+
    
+
    
+
+
    
+Miscellaneous stream attributes. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAM_MISC1   0x01A8          
    
+
    
+
    
+
+
    
+Miscellaneous stream attributes. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAM_POLARITY   0x0188          
    
+
    
+
    
+
+
    
+Polarity for the video sync signals. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAM_VRES   0x0198          
    
+
    
+
    
+
+
    
+Number of active lines (the vertical resolution). 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAM_VSTART   0x01A0          
    
+
    
+
    
+
+
    
+Number of lines between the leading edge of the vertical sync and the first line of active data. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAM_VSWIDTH   0x0190          
    
+
    
+
    
+
+
    
+Width of the vertical sync pulse. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAM_VTOTAL   0x0184          
    
+
    
+
    
+
+
    
+Total number of lines in the video frame. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC   0x2          
    
+
    
+
    
+
+
    
+10 bits per component. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC   0x3          
    
+
    
+
    
+
+
    
+12 bits per component. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC   0x4          
    
+
    
+
    
+
+
    
+16 bits per component. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC   0x0          
    
+
    
+
    
+
+
    
+6 bits per component. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC   0x1          
    
+
    
+
    
+
+
    
+8 bits per component. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_MASK   0x000000E0          
    
+
    
+
    
+
+
    
+Bit depth per color component (BDC). 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT   5          
    
+
    
+
    
+
+
    
+Shift bits for BDC. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK   0x00000006          
    
+
    
+
    
+
+
    
+Component format. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB   0x0          
    
+
    
+
    
+
+
    
+Stream's component format is RGB. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT   1          
    
+
    
+
    
+
+
    
+Shift bits for component format. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422   0x1          
    
+
    
+
    
+
+
    
+Stream's component format is YcbCr 4:2:2. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444   0x2          
    
+
    
+
    
+
+
    
+Stream's component format is YcbCr 4:4:4. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK   0x00000008          
    
+
    
+
    
+
+
    
+Dynamic range. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT   3          
    
+
    
+
    
+
+
    
+Shift bits for dynamic range. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK   0x00000001          
    
+
    
+
    
+
+
    
+Synchronous clock. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK   0x00000010          
    
+
    
+
    
+
+
    
+YCbCr colorimetry. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT   4          
    
+
    
+
    
+
+
    
+Shift bits for YCbCr colorimetry. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK   0x00000001          
    
+
    
+
    
+
+
    
+Interlaced vertical total even. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK   0x00000006          
    
+
    
+
    
+
+
    
+Stereo video attribute. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT   1          
    
+
    
+
    
+
+
    
+Shift bits for stereo video attribute. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK   0x00000001          
    
+
    
+
    
+
+
    
+Polarity of the horizontal sync pulse. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK   0x00000002          
    
+
    
+
    
+
+
    
+Polarity of the vertical sync pulse. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT   1          
    
+
    
+
    
+
+
    
+Shift bits for polarity of the vertical sync pulse. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_MIN_BYTES_PER_TU   0x01C4          
    
+
    
+
    
+
+
    
+The minimum number of bytes per transfer unit. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_N_VID   0x01B4          
    
+
    
+
    
+
+
    
+N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDptx_Out32   Xil_Out32          
    
+
    
+
    
+
+
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PE_LEVEL_0   0x00          
    
+
    
+
    
+
+
    
+Pre-emphasis level 0. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PE_LEVEL_1   0x0E          
    
+
    
+
    
+
+
    
+Pre-emphasis level 1. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PE_LEVEL_2   0x14          
    
+
    
+
    
+
+
    
+Pre-emphasis level 2. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PE_LEVEL_3   0x1B          
    
+
    
+
    
+
+
    
+Pre-emphasis level 3. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_CLOCK_SELECT   0x0234          
    
+
    
+
    
+
+
    
+Instructs the PHY PLL to generate the proper clock frequency for the required link rate. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_CLOCK_SELECT_162GBPS   0x1          
    
+
    
+
    
+
+
    
+1.62 Gbps link. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_CLOCK_SELECT_270GBPS   0x3          
    
+
    
+
    
+
+
    
+2.70 Gbps link. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_CLOCK_SELECT_540GBPS   0x5          
    
+
    
+
    
+
+
    
+5.40 Gbps link. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_CONFIG   0x0200          
    
+
    
+
    
+
+
    
+Transceiver PHY reset and configuration. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK   0x0010003          
    
+
    
+
    
+
+
    
+Rest GT and PHY. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_CONFIG_GTTX_RESET_MASK   0x0010002          
    
+
    
+
    
+
+
    
+Hold GTTXRESET in reset. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK   0x0010000          
    
+
    
+
    
+
+
    
+Release reset. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_CONFIG_PHY_RESET_MASK   0x0010001          
    
+
    
+
    
+
+
    
+Hold the PHY in reset. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK   0x001E000          
    
+
    
+
    
+
+
    
+Set TX_PHY_LOOPBACK. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK   0x0010200          
    
+
    
+
    
+
+
    
+HOLD TX_PHY_PCS reset. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK   0x0010100          
    
+
    
+
    
+
+
    
+Hold TX_PHY_PMA reset. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK   0x0010400          
    
+
    
+
    
+
+
    
+Set TX_PHY_POLARITY. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK   0x0011000          
    
+
    
+
    
+
+
    
+Set TX_PHY_PRBSFORCEERR. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_POSTCURSOR_LANE_0   0x024C          
    
+
    
+
    
+
+
    
+Controls the post-cursor level. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_POSTCURSOR_LANE_1   0x0250          
    
+
    
+
    
+
+
    
+Controls the post-cursor level. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_POSTCURSOR_LANE_2   0x0254          
    
+
    
+
    
+
+
    
+Controls the post-cursor level. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_POSTCURSOR_LANE_3   0x0258          
    
+
    
+
    
+
+
    
+Controls the post-cursor level. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_PRECURSOR_LANE_0   0x023C          
    
+
    
+
    
+
+
    
+Controls the pre-cursor level. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_PRECURSOR_LANE_1   0x0240          
    
+
    
+
    
+
+
    
+Controls the pre-cursor level. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_PRECURSOR_LANE_2   0x0244          
    
+
    
+
    
+
+
    
+Controls the pre-cursor level. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_PRECURSOR_LANE_3   0x0248          
    
+
    
+
    
+
+
    
+Controls the pre-cursor level. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS   0x0280          
    
+
    
+
    
+
+
    
+Current PHY status. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_ALL_LANES_READY_MASK   0x0000003F          
    
+
    
+
    
+
+
    
+All lanes are ready. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK   0x00000020          
    
+
    
+
    
+
+
    
+FPGA fabric clock PLL locked. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK   0x00000010          
    
+
    
+
    
+
+
    
+PLL locked for lanes 0 and 1. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK   0x00000020          
    
+
    
+
    
+
+
    
+PLL locked for lanes 2 and 3. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK   0x00000003          
    
+
    
+
    
+
+
    
+Reset done for lanes 0 and 1. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK   0x0000000C          
    
+
    
+
    
+
+
    
+Reset done for lanes 2 and 3. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK   0x00030000          
    
+
    
+
    
+
+
    
+TX buffer status lane 0. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT   16          
    
+
    
+
    
+
+
    
+Shift bits for TX buffer status lane 0. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK   0x00300000          
    
+
    
+
    
+
+
    
+TX buffer status lane 1. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT   20          
    
+
    
+
    
+
+
    
+Shift bits for TX buffer status lane 1. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK   0x03000000          
    
+
    
+
    
+
+
    
+TX buffer status lane 2. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT   24          
    
+
    
+
    
+
+
    
+Shift bits for TX buffer status lane 2. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK   0x30000000          
    
+
    
+
    
+
+
    
+TX buffer status lane 3. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT   28          
    
+
    
+
    
+
+
    
+Shift bits for TX buffer status lane 3. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK   0x000C0000          
    
+
    
+
    
+
+
    
+TX error on lane 0. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT   18          
    
+
    
+
    
+
+
    
+Shift bits for TX error on lane 0. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK   0x00C00000          
    
+
    
+
    
+
+
    
+TX error on lane 1. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT   22          
    
+
    
+
    
+
+
    
+Shift bits for TX error on lane 1. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK   0x0C000000          
    
+
    
+
    
+
+
    
+TX error on lane 2. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT   26          
    
+
    
+
    
+
+
    
+Shift bits for TX error on lane 2. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK   0xC0000000          
    
+
    
+
    
+
+
    
+TX error on lane 3. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT   30          
    
+
    
+
    
+
+
    
+Shift bits for TX error on lane 3. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_TRANSMIT_PRBS7   0x0230          
    
+
    
+
    
+
+
    
+Enable pseudo random bit sequence 7 pattern transmission for link quality assessment. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_0   0x0220          
    
+
    
+
    
+
+
    
+Controls the differential voltage swing. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_1   0x0224          
    
+
    
+
    
+
+
    
+Controls the differential voltage swing. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_2   0x0228          
    
+
    
+
    
+
+
    
+Controls the differential voltage swing. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_3   0x022C          
    
+
    
+
    
+
+
    
+Controls the differential voltage swing. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+      
    #define XDptx_ReadReg          (BaseAddress,         
    RegOffset            )    XDptx_In32((BaseAddress) + (RegOffset))
    
+
    
+
    
+
+
    
+This is a low-level function that reads from the specified register.
    
+
    Parameters:
    
+  
+    
+    
+  
    BaseAddress is the base address of the device. 
    RegOffset is the register offset to be read from.
    
+
    
+
    Returns:
    The 32-bit value of the specified register.
    
+
    Note:
    C-style signature: u32 XDptx_ReadReg(u32 BaseAddress, u32 RegOffset) 
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_REPLY_DATA_COUNT   0x0148          
    
+
    
+
    
+
+
    
+Total number of data bytes actually received during a transaction. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_REPLY_STATUS   0x014C          
    
+
    
+
    
+
+
    
+Reply status of most recent AUX transaction. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_REPLY_STATUS_REPLY_ERROR_MASK   0x00000008          
    
+
    
+
    
+
+
    
+Detected an error in the AUX reply of the most recent transaction. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK   0x00000002          
    
+
    
+
    
+
+
    
+AUX reply is currently being received. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK   0x00000001          
    
+
    
+
    
+
+
    
+AUX transaction is complete and a valid reply transaction received. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK   0x00000FF0          
    
+
    
+
    
+
+
    
+Internal AUX reply state machine status bits. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT   4          
    
+
    
+
    
+
+
    
+Shift bits for the internal AUX reply state machine status. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK   0x00000004          
    
+
    
+
    
+
+
    
+AUX request is currently being transmitted. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_SCRAMBLING_DISABLE   0x0014          
    
+
    
+
    
+
+
    
+Disable scrambler and transmit all symbols. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_SOFT_RESET   0x001C          
    
+
    
+
    
+
+
    
+Software reset. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_SOFT_RESET_AUX_MASK   0x00000080          
    
+
    
+
    
+
+
    
+Reset AUX logic. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK   0x00000001          
    
+
    
+
    
+
+
    
+Reset video logic. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK   0x00000002          
    
+
    
+
    
+
+
    
+Reset video logic. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK   0x00000004          
    
+
    
+
    
+
+
    
+Reset video logic. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK   0x00000008          
    
+
    
+
    
+
+
    
+Reset video logic. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK   0x0000000F          
    
+
    
+
    
+
+
    
+Reset video logic for all streams. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_STREAM0   0x01D0          
    
+
    
+
    
+
+
    
+Average stream symbol timeslots per MTP config. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_STREAM1   0x01D4          
    
+
    
+
    
+
+
    
+Average stream symbol timeslots per MTP config. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_STREAM1_MSA_START   0x0180          
    
+
    
+
    
+
+
    
+Start of the MSA registers for stream 1. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_STREAM2   0x01D8          
    
+
    
+
    
+
+
    
+Average stream symbol timeslots per MTP config. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_STREAM2_MSA_START   0x0500          
    
+
    
+
    
+
+
    
+Start of the MSA registers for stream 2. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_STREAM2_MSA_START_OFFSET          
    
+
    
+
    
+
+
    
+Value:
    (XDPTX_STREAM2_MSA_START - \
+                XDPTX_STREAM1_MSA_START)
+
    The MSA registers for stream 2 are at an offset from the corresponding registers of stream 1. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_STREAM3   0x01DC          
    
+
    
+
    
+
+
    
+Average stream symbol timeslots per MTP config. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_STREAM3_MSA_START   0x0550          
    
+
    
+
    
+
+
    
+Start of the MSA registers for stream 3. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_STREAM3_MSA_START_OFFSET          
    
+
    
+
    
+
+
    
+Value:
    (XDPTX_STREAM3_MSA_START - \
+                XDPTX_STREAM1_MSA_START)
+
    The MSA registers for stream 3 are at an offset from the corresponding registers of stream 1. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_STREAM4_MSA_START   0x05A0          
    
+
    
+
    
+
+
    
+Start of the MSA registers for stream 4. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_STREAM4_MSA_START_OFFSET          
    
+
    
+
    
+
+
    
+Value:
    (XDPTX_STREAM4_MSA_START - \
+                XDPTX_STREAM1_MSA_START)
+
    The MSA registers for stream 4 are at an offset from the corresponding registers of stream 1. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TRAINING_PATTERN_SET   0x000C          
    
+
    
+
    
+
+
    
+Set the link training pattern. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TRAINING_PATTERN_SET_OFF   0x0          
    
+
    
+
    
+
+
    
+Training off. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TRAINING_PATTERN_SET_TP1   0x1          
    
+
    
+
    
+
+
    
+Training pattern 1 used for clock recovery. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TRAINING_PATTERN_SET_TP2   0x2          
    
+
    
+
    
+
+
    
+Training pattern 2 used for channel equalization. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TRAINING_PATTERN_SET_TP3   0x3          
    
+
    
+
    
+
+
    
+Training pattern 3 used for channel equalization for cores with DP v1.2. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TU_SIZE   0x01B0          
    
+
    
+
    
+
+
    
+Size of a transfer unit in the framing logic. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TX_AUDIO_CHANNELS   0x0304          
    
+
    
+
    
+
+
    
+Used to input active channel count. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TX_AUDIO_CONTROL   0x0300          
    
+
    
+
    
+
+
    
+Enables audio stream packets in main link and buffer control. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TX_AUDIO_EXT_DATA   0x0330          
    
+
    
+
    
+
+
    
+Word formatted as per extension packet. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TX_AUDIO_INFO_DATA   0x0308          
    
+
    
+
    
+
+
    
+Word formatted as per CEA 861-C info frame. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TX_AUDIO_MAUD   0x0328          
    
+
    
+
    
+
+
    
+M value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TX_AUDIO_NAUD   0x032C          
    
+
    
+
    
+
+
    
+N value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TX_MST_CONFIG   0x00D0          
    
+
    
+
    
+
+
    
+Enable MST. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TX_MST_CONFIG_MST_EN_MASK   0x00000001          
    
+
    
+
    
+
+
    
+Enable MST. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK   0x00000002          
    
+
    
+
    
+
+
    
+The VC payload has been updated in the sink. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TX_PHY_POWER_DOWN   0x0238          
    
+
    
+
    
+
+
    
+Controls PHY power down. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_TX_USER_FIFO_OVERFLOW   0x0110          
    
+
    
+
    
+
+
    
+Indicates an overflow in user FIFO. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_USER_DATA_COUNT_PER_LANE   0x01BC          
    
+
    
+
    
+
+
    
+Used to translate the number of pixels per line to the native internal 16-bit datapath. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_USER_PIXEL_WIDTH   0x01B8          
    
+
    
+
    
+
+
    
+Selects the width of the user data input port. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VC_PAYLOAD_BUFFER_ADDR   0x0800          
    
+
    
+
    
+
+
    
+Virtual channel payload table (0xFF bytes). 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VERSION   0x00F8          
    
+
    
+
    
+
+
    
+Core version. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VERSION_CORE_PATCH_MASK   0x00000030          
    
+
    
+
    
+
+
    
+Core patch details. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VERSION_CORE_PATCH_SHIFT   8          
    
+
    
+
    
+
+
    
+Shift bits for core patch details. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VERSION_CORE_VER_MJR_MASK   0x0000F000          
    
+
    
+
    
+
+
    
+Core major version. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VERSION_CORE_VER_MJR_SHIFT   24          
    
+
    
+
    
+
+
    
+Shift bits for core major version. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VERSION_CORE_VER_MNR_MASK   0x00000F00          
    
+
    
+
    
+
+
    
+Core minor version. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VERSION_CORE_VER_MNR_SHIFT   16          
    
+
    
+
    
+
+
    
+Shift bits for core minor version. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VERSION_CORE_VER_REV_MASK   0x000000C0          
    
+
    
+
    
+
+
    
+Core version revision. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VERSION_CORE_VER_REV_SHIFT   12          
    
+
    
+
    
+
+
    
+Shift bits for core version revision. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VERSION_INTER_REV_MASK   0x0000000F          
    
+
    
+
    
+
+
    
+Internal revision. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VS_LEVEL_0   0x2          
    
+
    
+
    
+
+
    
+Voltage swing level 0. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VS_LEVEL_1   0x5          
    
+
    
+
    
+
+
    
+Voltage swing level 1. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VS_LEVEL_2   0x8          
    
+
    
+
    
+
+
    
+Voltage swing level 2. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VS_LEVEL_3   0xF          
    
+
    
+
    
+
+
    
+Voltage swing level 3. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XDPTX_VS_LEVEL_OFFSET   0x4          
    
+
    
+
    
+
+
    
+Voltage swing compensation offset used when there's no redriver in display path. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+      
    #define XDptx_WriteReg          (BaseAddress,         
    RegOffset,         
    Data            )    XDptx_Out32((BaseAddress) + (RegOffset), (Data))
    
+
    
+
    
+
+
    
+This is a low-level function that writes to the specified register.
    
+
    Parameters:
    
+  
+    
+    
+    
+  
    BaseAddress is the base address of the device. 
    RegOffset is the register offset to write to. 
    Data is the 32-bit data to write to the specified register.
    
+
    
+
    Returns:
    None.
    
+
    Note:
    C-style signature: void XDptx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) 
    
+
+
    
+
    
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__intr_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__intr_8c.html
similarity index 83%
rename from XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__intr_8c.html
rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__intr_8c.html
index 0b2b49e0..ea02bc5b 100644
--- a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__intr_8c.html
+++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__intr_8c.html
@@ -13,16 +13,17 @@
 
    
   
    
 
    
   
    
 
    xdptx_intr.c File Reference
    Detailed Description
    
 This file contains functions related to XDptx interrupt handling.
    
+
    Note:
    None.
    
 
      MODIFICATION HISTORY:
    
 
     Ver   Who  Date     Changes
@@ -30,13 +31,13 @@ This file contains functions related to 
  1.00a als  05/17/14 Initial release.
  
     
 
    
-#include "xdptx.h"
    
+#include "    xdptx.h"
    
 
-
+
 
-
+
 
@@ -63,9 +64,11 @@ This function is the interrupt handler for the 
-    
+    
    
 
    
 

    Functions
    void XDptx_SetHpdEventHandler (XDptx *InstancePtr, XDptx_HpdEventHandler CallbackFunc, void *CallbackRef)
    void XDptx_SetHpdEventHandler (XDptx *InstancePtr, XDptx_HpdEventHandler CallbackFunc, void *CallbackRef)
    void XDptx_SetHpdPulseHandler (XDptx *InstancePtr, XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef)
    void XDptx_SetHpdPulseHandler (XDptx *InstancePtr, XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef)
    
 
 
    void XDptx_HpdInterruptHandler (XDptx *InstancePtr)
    InstancePtr is a pointer to the XDptx instance. 
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -82,7 +85,7 @@ When an interrupt happens, it first detects what kind of interrupt happened, the
         
           
           
-          XDptx_HpdEventHandler 
+          XDptx_HpdEventHandler 
            CallbackFunc, 
         
         
@@ -106,9 +109,11 @@ This function installs a callback function for when a hot-plug-detect event inte
   
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    
     
    CallbackFunc is the address to the callback function. 
    CallbackRef is the user data item that will be passed to the callback function when it is invoked. 
    CallbackRef is the user data item that will be passed to the callback function when it is invoked.
    
   
    
 
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
@@ -125,7 +130,7 @@ This function installs a callback function for when a hot-plug-detect event inte
         
           
           
-          XDptx_HpdPulseHandler 
+          XDptx_HpdPulseHandler 
            CallbackFunc, 
         
         
@@ -149,9 +154,11 @@ This function installs a callback function for when a hot-plug-detect pulse inte
   
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    
     
    CallbackFunc is the address to the callback function. 
    CallbackRef is the user data item that will be passed to the callback function when it is invoked. 
    CallbackRef is the user data item that will be passed to the callback function when it is invoked.
    
   
    
 
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__selftest_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__selftest_8c.html
new file mode 100644
index 00000000..3a2b6542
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__selftest_8c.html
@@ -0,0 +1,132 @@
+
+
+   
+
+   xdptx_selftest.c File Reference
+
+
+
+
    Xilinx Processor IP Library
    
+Software Drivers
+
    
+
+
    
+  
    
+
    
+  
    
+
    xdptx_selftest.c File Reference
    Detailed Description
    
+This file contains a diagnostic self-test function for the XDptx driver. It will check many of the DisplayPort TX's register values against the default reset values as a sanity-check that the core is ready to be used.
    
+
    Note:
    None.
    
+
    + MODIFICATION HISTORY:
    
+
     Ver   Who  Date     Changes
+ ----- ---- -------- -----------------------------------------------
+ 1.00a als  05/17/14 Initial release.
+ 
     
+
    
+#include "xdptx.h"
    
+#include "xstatus.h"
    
+
+
+
+
+
+
+
+
+
+
+

    Functions
    u32 XDptx_SelfTest (XDptx *InstancePtr)

    Variables
    u32 ResetValues [53][2]
    u32 ResetValuesMsa [20][2]
    
+
    Function Documentation
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    u32 XDptx_SelfTest           (XDptx *  InstancePtr           ) 
    
+
    
+
    
+
+
    
+This function runs a self-test on the XDptx driver/device. The sanity test checks whether or not all tested registers hold their default reset values.
    
+
    Parameters:
    
+  
+    
+  
    InstancePtr is a pointer to the XDptx instance.
    
+
    
+
    Returns:
      
+
    • XST_SUCCESS if the self-test passed - all tested registers hold their default reset values.
    • XST_FAILURE otherwise.
    
+
    
+
    Note:
    None. 
    
+
+
    
+
    
+
    Variable Documentation
    
+
+
    
+
    
+      
+        
+          
+        
+      
    u32 ResetValues[53][2]          
    
+
    
+
    
+
+
    
+This table contains the default values for the DisplayPort TX core's general usage registers. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    u32 ResetValuesMsa[20][2]          
    
+
    
+
    
+
+
    
+Initial value:
    +{
+        {XDPTX_MAIN_STREAM_HTOTAL, 0},
+        {XDPTX_MAIN_STREAM_VTOTAL, 0},
+        {XDPTX_MAIN_STREAM_POLARITY, 0},
+        {XDPTX_MAIN_STREAM_HSWIDTH, 0},
+        {XDPTX_MAIN_STREAM_VSWIDTH, 0},
+        {XDPTX_MAIN_STREAM_HRES, 0},
+        {XDPTX_MAIN_STREAM_VRES, 0},
+        {XDPTX_MAIN_STREAM_HSTART, 0},
+        {XDPTX_MAIN_STREAM_VSTART, 0},
+        {XDPTX_MAIN_STREAM_MISC0, 0},
+        {XDPTX_MAIN_STREAM_MISC1, 0},
+        {XDPTX_M_VID, 0},
+        {XDPTX_TU_SIZE, 0},
+        {XDPTX_N_VID, 0},
+        {XDPTX_USER_PIXEL_WIDTH, 0},
+        {XDPTX_USER_DATA_COUNT_PER_LANE, 0},
+        {XDPTX_MAIN_STREAM_INTERLACED, 0},
+        {XDPTX_MIN_BYTES_PER_TU, 0},
+        {XDPTX_FRAC_BYTES_PER_TU, 0},
+        {XDPTX_INIT_WAIT, 32}
+}
+
    This table contains the default values for the DisplayPort TX core's main stream attribute (MSA) registers. 
+
    
+
    
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__sinit_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__sinit_8c.html
similarity index 91%
rename from XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__sinit_8c.html
rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__sinit_8c.html
index 18a0ffc1..3bf52424 100644
--- a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__sinit_8c.html
+++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__sinit_8c.html
@@ -13,16 +13,17 @@
 
    
   
    
 
    
   
    
 
    xdptx_sinit.c File Reference
    Detailed Description
    
 This file contains static initialization methods for the XDptx driver.
    
+
    Note:
    None.
    
 
      MODIFICATION HISTORY:
    
 
     Ver   Who  Date     Changes
@@ -30,7 +31,7 @@ This file contains static initialization methods for the xdptx.h"
    
 #include "xparameters.h"
    
 
@@ -65,7 +66,8 @@ This function looks for the device configuration based on the unique device ID.
     
    
 
    DeviceId is the unique device ID of the device being looked up.
    
   
    
 
-
    Returns:
    A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found. 
    
+
    Returns:
    A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found.
    
+
    Note:
    None. 
    
 
 
 
    
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__spm_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html
similarity index 81%
rename from XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__spm_8c.html
rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html
index 90e392a4..a9ef1253 100644
--- a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__spm_8c.html
+++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html
@@ -13,16 +13,17 @@
 
    
   
    
 
    
   
    
 
    xdptx_spm.c File Reference
    Detailed Description
    
 This file contains the stream policy maker functions for the XDptx driver. These functions set up the DisplayPort TX core's main stream attributes that determine how a video stream will be displayed.
    
+
    Note:
    None.
    
 
      MODIFICATION HISTORY:
    
 
     Ver   Who  Date     Changes
@@ -30,7 +31,7 @@ This file contains the stream policy maker functions for the  
 
    
-#include "xdptx.h"
    
+#include "    xdptx.h"
    
 #include "xdptx_hw.h"
    
 #include "xstatus.h"
    
 
@@ -38,13 +39,13 @@ This file contains the stream policy maker functions for the 
 
-
+
 
-
+
 
@@ -67,7 +68,7 @@ This file contains the stream policy maker functions for the 
 
 
    
-This function calculates the following main stream attributes:
      
+This function calculates the following Main Stream Attributes (MSA):
        
 
      • Transfer unit size
      • User pixel width
      • NVid
      • Horizontal start
      • Vertical start
      • Horizontal total clock
      • Vertical total clock
      • Misc0
      • Misc1
      • Data per lane
      • Average number of bytes per transfer unit
      • Number of initial wait cycles These values are derived from:
      • Bits per color
      • MVid
      • Horizontal sync polarity
      • Vertical sync polarity
      • Horizontal sync pulse width
      • Vertical sync pulse width
      • Horizontal resolution
      • Vertical resolution
      • Vertical back porch
      • Vertical front porch
      • Horizontal back porch
      • Horizontal front porch
      
 
      
 
      Parameters:
      
@@ -75,16 +76,17 @@ This function calculates the following main stream attributes:
        
     

    Functions
    
 
    void XDptx_CfgMsaRecalculate (XDptx *InstancePtr)
    u32 XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, XDptx_VideoMode VideoMode)
    void XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, XDptx_VideoMode VideoMode)
    
 
 
    void XDptx_CfgMsaUseEdidPreferredTiming (XDptx *InstancePtr)
    
 
 
    void XDptx_CfgMsaUseCustom (XDptx *InstancePtr, XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate)
    u32 XDptx_CfgMsaSetBpc (XDptx *InstancePtr, u8 BitsPerColor)
    void XDptx_CfgMsaSetBpc (XDptx *InstancePtr, u8 BitsPerColor)
    
 
 
    void XDptx_SetVideoMode (XDptx *InstancePtr)
    InstancePtr is a pointer to the XDptx instance.
    
   
    
 
+
    Returns:
    None.
    
 
    Note:
    The MsaConfig structure is modified with the new, calculated values. The main stream attributes that were used to derive the calculated values are untouched in the MsaConfig structure. 
    
 
 
 
    
-
+
 
    
 
    
       
-          
+          
@@ -112,10 +114,8 @@ This function sets the bits per color value of the video stream.
    
     
    
         
    u32 XDptx_CfgMsaSetBpc           void XDptx_CfgMsaSetBpc           
           (
           XDptx * 
            InstancePtr, 
    BitsPerColor is the new number of bits per color to use.
    
   
    
 
-
    Note:
    The InstancePtr->MsaConfig structure is modified to reflect the new main stream attributes associated with a new bits per color value.
    
-
    Returns:
      
-
    • XST_INVALID_PARAM if the supplied bits per color value is not either 6, 8, 10, 12, or 16.
    • XST_SUCCESS otherwise. 
    
-
    
+
    Returns:
    None.
    
+
    Note:
    The InstancePtr->MsaConfig structure is modified to reflect the new main stream attributes associated with a new bits per color value. 
    
 
 
    
 
    
@@ -161,6 +161,7 @@ This function takes a the main stream attributes from MsaConfigCustom and copies
     Recalculate is a boolean enable that determines whether or not the main stream attributes should be recalculated.
   
 
+
    Returns:
    None.
    
 
    Note:
    The InstancePtr-> MsaConfig structure is modified with the new values. 
    
 
 
@@ -182,22 +183,23 @@ This function takes a the main stream attributes from MsaConfigCustom and copies
 
    
 
 
    
-This function sets the main stream attribute values in the configuration structure to match the preferred timing of the sink monitor. This preferred timing information is stored in the sink's extended display identification data (EDID).
    
+This function sets the main stream attribute values in the configuration structure to match the preferred timing of the sink monitor. This Preferred Timing Mode (PTM) information is stored in the sink's Extended Display Identification Data (EDID).
    
 
    Parameters:
    
   
    
     
    InstancePtr is a pointer to the XDptx instance
    
   
    
 
    
+
    Returns:
    None.
    
 
    Note:
    The InstancePtr->MsaConfig structure is modified to reflect the main stream attribute values associated to the preferred timing of the sink monitor. 
    
 
 
    
 
    
-
+
 
    
 
    
       
-          
+          
@@ -205,7 +207,7 @@ This function sets the main stream attribute values in the configuration structu
         
-          
+          
@@ -218,17 +220,15 @@ This function sets the main stream attribute values in the configuration structu
 
    
 
 
    
-This function sets the main stream attribute values in the configuration structure to match one of the standard display mode timings from the XDptx_DmtModes[] table. THe XDptx_VideoMode enumeration in xdptx.h lists the available video modes.
    
+This function sets the Main Stream Attribute (MSA) values in the configuration structure to match one of the standard display mode timings from the XDptx_DmtModes[] standard Display Monitor Timing (DMT) table. The XDptx_VideoMode enumeration in xdptx.h lists the available video modes.
    
 
    Parameters:
    
   
    
         
    u32 XDptx_CfgMsaUseStandardVideoMode           void XDptx_CfgMsaUseStandardVideoMode           
           (
           XDptx * 
            InstancePtr, 
    
           
           XDptx_VideoMode XDptx_VideoMode 
            VideoMode 
         
    
         
    
-    
+    
    
     
    InstancePtr is a pointer to the XDptx instance. 
    VideoMode is one of the enumerated standard video modes that is used to determine the main stream attributes to be used.
    VideoMode is one of the enumerated standard video modes that is used to determine the MSA values to be used.
    
   
    
 
-
    Returns:
      
-
    • XST_INVALID_PARAM if the supplied video mode isn't in the DMT table.
    • XST_SUCCESS otherwise.
    
-
    
-
    Note:
    The InstancePtr->MsaConfig structure is modified to reflect the main stream attribute values associated to the specified video mode. 
    
+
    Returns:
    None.
    
+
    Note:
    The InstancePtr->MsaConfig structure is modified to reflect the MSA values associated to the specified video mode. 
    
 
 
    
 
    
@@ -252,9 +252,11 @@ This function sets the main stream attribute values in the configuration structu
 This function clears the main stream attributes registers of the DisplayPort TX core and sets them to the values specified in the main stream attributes configuration structure.
    
 
    Parameters:
    
   
-    
+    
    InstancePtr is a pointer to the XDptx instance 
    InstancePtr is a pointer to the XDptx instance
    
   
    
 
    
+
    Returns:
    None.
    
+
    Note:
    None. 
    
 
 
 
    
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__vidmodetable_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__vidmodetable_8c.html
similarity index 71%
rename from XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__vidmodetable_8c.html
rename to XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__vidmodetable_8c.html
index 11ac61c7..b1686a81 100644
--- a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__vidmodetable_8c.html
+++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__vidmodetable_8c.html
@@ -13,16 +13,17 @@
 
    
   
    
 
    
   
    
 
    xdptx_vidmodetable.c File Reference
    Detailed Description
    
 Contains display monitor timing (DMT) modes for various standard resolutions.
    
+
    Note:
    None.
    
 
      MODIFICATION HISTORY:
    
 
     Ver   Who  Date     Changes
@@ -31,7 +32,7 @@ Contains display monitor timing (DMT) modes for various standard resolutions.
    
  
     
 
    
 #include "xil_types.h"
    
-#include "xdptx.h"
    
+#include "xdptx.h"
    
 
@@ -51,7 +52,7 @@ Contains display monitor timing (DMT) modes for various standard resolutions.
    
 
    
 
 
    
-This table contains the main stream attributes for various standard resolutions. 
+This table contains the main stream attributes for various standard resolutions. Each entry is of the format: 1) XDPTX_VM_<HRES>x<VRES>_<REFRESH (HZ)>_P(_RB = Reduced Blanking) 2) Display Monitor Timing (DMT) ID 3) Horizontal resolution (pixels) 4) Vertical resolution (lines) 5) Pixel clock (KHz) 6) Scan (0=non-interlaced|1=interlaced) 7) Horizontal sync polarity (0=positive|1=negative) 8) Vertical sync polarity (0=positive|1=negative) 9) Horizontal front porch (pixels) 10) Horizontal sync time (pixels) 11) Horizontal back porch (pixels) 12) Vertical front porch (lines) 13) Vertical sync time (lines) 14) Vertical back porch (lines) 
 
    
 Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/globals.html
deleted file mode 100644
index 2d05ec67..00000000
--- a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals.html
+++ /dev/null
@@ -1,365 +0,0 @@
-
-
-   
-
-   Data Fields
-
-
-
-
    Xilinx Processor IP Library
    
-Software Drivers
-
    
-
-
    
-  
    
-
    
-  
    
-
    
-  
-
    
-
    
-  
      
-    
    • x
      • 
-  
    
-
    
-
-
    
-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
-
    
-
    - x -
    
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_defs.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_defs.html
deleted file mode 100644
index d5866ed2..00000000
--- a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_defs.html
+++ /dev/null
@@ -1,328 +0,0 @@
-
-
-   
-
-   Data Fields
-
-
-
-
    Xilinx Processor IP Library
    
-Software Drivers
-
    
-
-
    
-  
    
-
    
-  
    
-
    
-  
-
    
-
    
-  
      
-    
    • x
      • 
-  
    
-
    
-
-
    
- 
-
    
-
    - x -
    
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_func.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_func.html
deleted file mode 100644
index 10c83545..00000000
--- a/XilinxProcessorIPLib/drivers/dptx/doc/html/globals_func.html
+++ /dev/null
@@ -1,78 +0,0 @@
-
-
-   
-
-   Data Fields
-
-
-
-
    Xilinx Processor IP Library
    
-Software Drivers
-
    
-
-
    
-  
    
-
    
-  
    
-
    
-  
-
    
-
    
-  
      
-    
    • x
      • 
-  
    
-
    
-
-
    
- 
-
    
-
    - x -
    
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/index.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/index.html
deleted file mode 100644
index 0a2875e7..00000000
--- a/XilinxProcessorIPLib/drivers/dptx/doc/html/index.html
+++ /dev/null
@@ -1,28 +0,0 @@
-
-
-   
-
-   Main Page
-
-
-
-
    Xilinx Processor IP Library
    
-Software Drivers
-
    
-
-
    
-  
    
-
    
-
    
-The Xilinx DisplayPort transmitter (TX) driver.
    
-The driver currently supports single-stream transport (SST) functionality.
    
-
    - MODIFICATION HISTORY:
    
-
     Ver   Who  Date     Changes
- ----- ---- -------- -----------------------------------------------
- 1.00a als  05/17/14 Initial release.
- 
     Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___aux_transaction.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___aux_transaction.html
deleted file mode 100644
index 5471bf32..00000000
--- a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___aux_transaction.html
+++ /dev/null
@@ -1,32 +0,0 @@
-
-
-   
-
-   XDptx_AuxTransaction Struct Reference
-
-
-
-
    Xilinx Processor IP Library
    
-Software Drivers
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    XDptx_AuxTransaction Struct Reference
    Detailed Description
    
-This typedef describes an AUX transaction. 
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    Variables
    
 
    
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    The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___main_stream_attributes-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___main_stream_attributes-members.html
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    XDptx_MainStreamAttributes Member List
    This is the complete list of members for XDptx_MainStreamAttributes, including all inherited members.
    
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    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___main_stream_attributes.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/struct_x_dptx___main_stream_attributes.html
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    XDptx_MainStreamAttributes Struct Reference
    #include <xdptx.h>
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    Detailed Description
    
-This typedef contains the main stream attributes which determine how the video will be displayed. 
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    The documentation for this struct was generated from the following file:
      
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    • xdptx.h
    
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__hw_8h.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__hw_8h.html
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    xdptx_hw.h File Reference
    Detailed Description
    
-This header file contains the identifiers and low-level driver functions (or macros) that can be used to access the device. High-level driver functions are defined in xdptx.h.
    
-
    - MODIFICATION HISTORY:
    
-
     Ver   Who  Date     Changes
- ----- ---- -------- -----------------------------------------------
- 1.00a als  05/17/14 Initial release.
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    DPTX core registers: Link configuration field.
    #define XDPTX_LINK_BW_SET   0x0000
    #define XDPTX_LANE_COUNT_SET   0x0004
    #define XDPTX_ENHANCED_FRAME_EN   0x0008
    #define XDPTX_TRAINING_PATTERN_SET   0x000C
    #define XDPTX_LINK_QUAL_PATTERN_SET   0x0010
    #define XDPTX_SCRAMBLING_DISABLE   0x0014
    #define XDPTX_DOWNSPREAD_CTRL   0x0018
    #define XDPTX_SOFT_RESET   0x001C

    DPTX core registers: Core enables.
    #define XDPTX_ENABLE   0x0080
    #define XDPTX_ENABLE_MAIN_STREAM   0x0084
    #define XDPTX_ENABLE_SEC_STREAM   0x0088
    #define XDPTX_FORCE_SCRAMBLER_RESET   0x00C0
    #define XDPTX_TX_MST_CONFIG   0x00D0

    DPTX core registers: Core ID.
    #define XDPTX_VERSION   0x00F8
    #define XDPTX_CORE_ID   0x00FC

    DPTX core registers: AUX channel interface.
    #define XDPTX_AUX_CMD   0x0100
    #define XDPTX_AUX_WRITE_FIFO   0x0104
    #define XDPTX_AUX_ADDRESS   0x0108
    #define XDPTX_AUX_CLK_DIVIDER   0x010C
    #define XDPTX_TX_USER_FIFO_OVERFLOW   0x0110
    #define XDPTX_INTERRUPT_SIG_STATE   0x0130
    #define XDPTX_AUX_REPLY_DATA   0x0134
    #define XDPTX_AUX_REPLY_CODE   0x0138
    #define XDPTX_AUX_REPLY_COUNT   0x013C
    #define XDPTX_INTERRUPT_STATUS   0x0140
    #define XDPTX_INTERRUPT_MASK   0x0144
    #define XDPTX_REPLY_DATA_COUNT   0x0148
    #define XDPTX_REPLY_STATUS   0x014C
    #define XDPTX_HPD_DURATION   0x0150

    DPTX core registers: Main stream attributes for SST / MST STREAM1.
    #define XDPTX_MAIN_STREAM_HTOTAL   0x0180
    #define XDPTX_MAIN_STREAM_VTOTAL   0x0184
    #define XDPTX_MAIN_STREAM_POLARITY   0x0188
    #define XDPTX_MAIN_STREAM_HSWIDTH   0x018C
    #define XDPTX_MAIN_STREAM_VSWIDTH   0x0190
    #define XDPTX_MAIN_STREAM_HRES   0x0194
    #define XDPTX_MAIN_STREAM_VRES   0x0198
    #define XDPTX_MAIN_STREAM_HSTART   0x019C
    #define XDPTX_MAIN_STREAM_VSTART   0x01A0
    #define XDPTX_MAIN_STREAM_MISC0   0x01A4
    #define XDPTX_MAIN_STREAM_MISC1   0x01A8
    #define XDPTX_M_VID   0x01AC
    #define XDPTX_TU_SIZE   0x01B0
    #define XDPTX_N_VID   0x01B4
    #define XDPTX_USER_PIXEL_WIDTH   0x01B8
    #define XDPTX_USER_DATA_COUNT_PER_LANE   0x01BC
    #define XDPTX_MAIN_STREAM_INTERLACED   0x01C0
    #define XDPTX_MIN_BYTES_PER_TU   0x01C4
    #define XDPTX_FRAC_BYTES_PER_TU   0x01C8
    #define XDPTX_INIT_WAIT   0x01CC
    #define XDPTX_STREAM0   0x01D0
    #define XDPTX_STREAM1   0x01D4
    #define XDPTX_STREAM2   0x01D8
    #define XDPTX_STREAM3   0x01DC

    DPTX core registers: PHY configuration status.
    #define XDPTX_PHY_CONFIG   0x0200
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_0   0x0220
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_1   0x0224
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_2   0x0228
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_3   0x022C
    #define XDPTX_PHY_TRANSMIT_PRBS7   0x0230
    #define XDPTX_PHY_CLOCK_SELECT   0x0234
    #define XDPTX_TX_PHY_POWER_DOWN   0x0238
    #define XDPTX_PHY_PRECURSOR_LANE_0   0x023C
    #define XDPTX_PHY_PRECURSOR_LANE_1   0x0240
    #define XDPTX_PHY_PRECURSOR_LANE_2   0x0244
    #define XDPTX_PHY_PRECURSOR_LANE_3   0x0248
    #define XDPTX_PHY_POSTCURSOR_LANE_0   0x024C
    #define XDPTX_PHY_POSTCURSOR_LANE_1   0x0250
    #define XDPTX_PHY_POSTCURSOR_LANE_2   0x0254
    #define XDPTX_PHY_POSTCURSOR_LANE_3   0x0258
    #define XDPTX_PHY_STATUS   0x0280
    #define XDPTX_GT_DRP_COMMAND   0x02A0
    #define XDPTX_GT_DRP_READ_DATA   0x02A4
    #define XDPTX_GT_DRP_CHANNEL_STATUS   0x02A8

    DPTX core registers: DisplayPort audio.
    #define XDPTX_TX_AUDIO_CONTROL   0x0300
    #define XDPTX_TX_AUDIO_CHANNELS   0x0304
    #define XDPTX_TX_AUDIO_INFO_DATA   0x0308
    #define XDPTX_TX_AUDIO_MAUD   0x0328
    #define XDPTX_TX_AUDIO_NAUD   0x032C
    #define XDPTX_TX_AUDIO_EXT_DATA   0x0330

    DPTX core registers: Main stream attributes for MST STREAM2.
    #define XDPTX_MAIN_STREAM2_HTOTAL   0x0500
    #define XDPTX_MAIN_STREAM2_VTOTAL   0x0504
    #define XDPTX_MAIN_STREAM2_POLARITY   0x0508
    #define XDPTX_MAIN_STREAM2_HSWIDTH   0x050C
    #define XDPTX_MAIN_STREAM2_VSWIDTH   0x0510
    #define XDPTX_MAIN_STREAM2_HRES   0x0514
    #define XDPTX_MAIN_STREAM2_VRES   0x0518
    #define XDPTX_MAIN_STREAM2_HSTART   0x051C
    #define XDPTX_MAIN_STREAM2_VSTART   0x0520
    #define XDPTX_MAIN_STREAM2_MISC0   0x0524
    #define XDPTX_MAIN_STREAM2_MISC1   0x0528
    #define XDPTX_M_VID_STREAM2   0x052C
    #define XDPTX_TU_SIZE_STREAM2   0x0530
    #define XDPTX_N_VID_STREAM2   0x0534
    #define XDPTX_USER_PIXEL_WIDTH_STREAM2   0x0538
    #define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM2   0x053C
    #define XDPTX_MAIN_STREAM2_INTERLACED   0x0540
    #define XDPTX_MIN_BYTES_PER_TU_STREAM2   0x0544
    #define XDPTX_FRAC_BYTES_PER_TU_STREAM2   0x0548
    #define XDPTX_INIT_WAIT_STREAM2   0x054C

    DPTX core registers: Main stream attributes for MST STREAM3.
    #define XDPTX_MAIN_STREAM3_HTOTAL   0x0550
    #define XDPTX_MAIN_STREAM3_VTOTAL   0x0554
    #define XDPTX_MAIN_STREAM3_POLARITY   0x0558
    #define XDPTX_MAIN_STREAM3_HSWIDTH   0x055C
    #define XDPTX_MAIN_STREAM3_VSWIDTH   0x0560
    #define XDPTX_MAIN_STREAM3_HRES   0x0564
    #define XDPTX_MAIN_STREAM3_VRES   0x0568
    #define XDPTX_MAIN_STREAM3_HSTART   0x056C
    #define XDPTX_MAIN_STREAM3_VSTART   0x0570
    #define XDPTX_MAIN_STREAM3_MISC0   0x0574
    #define XDPTX_MAIN_STREAM3_MISC1   0x0578
    #define XDPTX_M_VID_STREAM3   0x057C
    #define XDPTX_TU_SIZE_STREAM3   0x0580
    #define XDPTX_N_VID_STREAM3   0x0584
    #define XDPTX_USER_PIXEL_WIDTH_STREAM3   0x0588
    #define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM3   0x058C
    #define XDPTX_MAIN_STREAM3_INTERLACED   0x0590
    #define XDPTX_MIN_BYTES_PER_TU_STREAM3   0x0594
    #define XDPTX_FRAC_BYTES_PER_TU_STREAM3   0x0598
    #define XDPTX_INIT_WAIT_STREAM3   0x059C

    DPTX core registers: Main stream attributes for MST STREAM4.
    #define XDPTX_MAIN_STREAM4_HTOTAL   0x05A0
    #define XDPTX_MAIN_STREAM4_VTOTAL   0x05A4
    #define XDPTX_MAIN_STREAM4_POLARITY   0x05A8
    #define XDPTX_MAIN_STREAM4_HSWIDTH   0x05AC
    #define XDPTX_MAIN_STREAM4_VSWIDTH   0x05B0
    #define XDPTX_MAIN_STREAM4_HRES   0x05B4
    #define XDPTX_MAIN_STREAM4_VRES   0x05B8
    #define XDPTX_MAIN_STREAM4_HSTART   0x05BC
    #define XDPTX_MAIN_STREAM4_VSTART   0x05C0
    #define XDPTX_MAIN_STREAM4_MISC0   0x05C4
    #define XDPTX_MAIN_STREAM4_MISC1   0x05C8
    #define XDPTX_M_VID_STREAM4   0x05CC
    #define XDPTX_TU_SIZE_STREAM4   0x05D0
    #define XDPTX_N_VID_STREAM4   0x05D4
    #define XDPTX_USER_PIXEL_WIDTH_STREAM4   0x05D8
    #define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM4   0x05DC
    #define XDPTX_MAIN_STREAM4_INTERLACED   0x05E0
    #define XDPTX_MIN_BYTES_PER_TU_STREAM4   0x05E4
    #define XDPTX_FRAC_BYTES_PER_TU_STREAM4   0x05E8
    #define XDPTX_INIT_WAIT_STREAM4   0x05EC

    DPTX core masks, shifts, and register values.
    #define XDPTX_LINK_BW_SET_162GBPS   0x06
    #define XDPTX_LINK_BW_SET_270GBPS   0x0A
    #define XDPTX_LINK_BW_SET_540GBPS   0x14
    #define XDPTX_TRAINING_PATTERN_SET_OFF   0x0
    #define XDPTX_TRAINING_PATTERN_SET_TP1   0x1
    #define XDPTX_TRAINING_PATTERN_SET_TP2   0x2
    #define XDPTX_TRAINING_PATTERN_SET_TP3   0x3
    #define XDPTX_LINK_QUAL_PATTERN_SET_OFF   0x0
    #define XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST   0x1
    #define XDPTX_LINK_QUAL_PATTERN_SET_SER_MES   0x2
    #define XDPTX_LINK_QUAL_PATTERN_SET_PRBS7   0x3
    #define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK   0x00000001
    #define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK   0x00000002
    #define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK   0x00000004
    #define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK   0x00000008
    #define XDPTX_SOFT_RESET_AUX_MASK   0x00000080
    #define XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK   0x0000000F
    #define XDPTX_TX_MST_CONFIG_MST_EN_MASK   0x00000001
    #define XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK   0x00000002
    #define XDPTX_VERSION_INTER_REV_MASK   0x0000000F
    #define XDPTX_VERSION_CORE_PATCH_MASK   0x00000030
    #define XDPTX_VERSION_CORE_PATCH_SHIFT   8
    #define XDPTX_VERSION_CORE_VER_REV_MASK   0x000000C0
    #define XDPTX_VERSION_CORE_VER_REV_SHIFT   12
    #define XDPTX_VERSION_CORE_VER_MNR_MASK   0x00000F00
    #define XDPTX_VERSION_CORE_VER_MNR_SHIFT   16
    #define XDPTX_VERSION_CORE_VER_MJR_MASK   0x0000F000
    #define XDPTX_VERSION_CORE_VER_MJR_SHIFT   24
    #define XDPTX_CORE_ID_TYPE_MASK   0x0000000F
    #define XDPTX_CORE_ID_TYPE_TX   0x0
    #define XDPTX_CORE_ID_TYPE_RX   0x1
    #define XDPTX_CORE_ID_DP_REV_MASK   0x000000F0
    #define XDPTX_CORE_ID_DP_REV_SHIFT   8
    #define XDPTX_CORE_ID_DP_MNR_VER_MASK   0x00000F00
    #define XDPTX_CORE_ID_DP_MNR_VER_SHIFT   16
    #define XDPTX_CORE_ID_DP_MJR_VER_MASK   0x0000F000
    #define XDPTX_CORE_ID_DP_MJR_VER_SHIFT   24
    #define XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK   0x0000000F
    #define XDPTX_AUX_CMD_MASK   0x00000F00
    #define XDPTX_AUX_CMD_SHIFT   8
    #define XDPTX_AUX_CMD_I2C_WRITE   0x0
    #define XDPTX_AUX_CMD_I2C_READ   0x1
    #define XDPTX_AUX_CMD_I2C_WRITE_STATUS   0x2
    #define XDPTX_AUX_CMD_I2C_WRITE_MOT   0x4
    #define XDPTX_AUX_CMD_I2C_READ_MOT   0x5
    #define XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT   0x6
    #define XDPTX_AUX_CMD_WRITE   0x8
    #define XDPTX_AUX_CMD_READ   0x9
    #define XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN   0x00001000
    #define XDPTX_AUX_CLK_DIVIDER_VAL_MASK   0x0000000F
    #define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK   0x00000F00
    #define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT   8
    #define XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK   0x00000001
    #define XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK   0x00000002
    #define XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK   0x00000004
    #define XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK   0x00000008
    #define XDPTX_AUX_REPLY_CODE_ACK   0x0
    #define XDPTX_AUX_REPLY_CODE_I2C_ACK   0x0
    #define XDPTX_AUX_REPLY_CODE_NACK   0x1
    #define XDPTX_AUX_REPLY_CODE_DEFER   0x2
    #define XDPTX_AUX_REPLY_CODE_I2C_NACK   0x4
    #define XDPTX_AUX_REPLY_CODE_I2C_DEFER   0x8
    #define XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK   0x00000001
    #define XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK   0x00000002
    #define XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK   0x00000004
    #define XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK   0x00000008
    #define XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK   0x00000010
    #define XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK   0x00000020
    #define XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK   0x00000001
    #define XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK   0x00000002
    #define XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK   0x00000004
    #define XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK   0x00000008
    #define XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK   0x00000010
    #define XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK   0x00000020
    #define XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK   0x00000001
    #define XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK   0x00000002
    #define XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK   0x00000004
    #define XDPTX_REPLY_STATUS_REPLY_ERROR_MASK   0x00000008
    #define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK   0x00000FF0
    #define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT   4
    #define XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK   0x00000001
    #define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK   0x00000002
    #define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT   1
    #define XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK   0x00000001
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK   0x00000006
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT   1
    #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK   0x00000008
    #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT   3
    #define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK   0x00000010
    #define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT   4
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_MASK   0x000000E0
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT   5
    #define XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK   0x00000001
    #define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK   0x00000006
    #define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT   1
    #define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK   0x0010000
    #define XDPTX_PHY_CONFIG_PHY_RESET_MASK   0x0010001
    #define XDPTX_PHY_CONFIG_GTTX_RESET_MASK   0x0010002
    #define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK   0x0010100
    #define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK   0x0010200
    #define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK   0x0010400
    #define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK   0x0011000
    #define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK   0x001E000
    #define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK   0x0010003
    #define XDPTX_PHY_CLOCK_SELECT_162GBPS   0x1
    #define XDPTX_PHY_CLOCK_SELECT_270GBPS   0x3
    #define XDPTX_PHY_CLOCK_SELECT_540GBPS   0x5
    #define XDPTX_VS_LEVEL_0   0x2
    #define XDPTX_VS_LEVEL_1   0x5
    #define XDPTX_VS_LEVEL_2   0x8
    #define XDPTX_VS_LEVEL_3   0xF
    #define XDPTX_VS_LEVEL_OFFSET   0x4
    #define XDPTX_PE_LEVEL_0   0x00
    #define XDPTX_PE_LEVEL_1   0x0E
    #define XDPTX_PE_LEVEL_2   0x14
    #define XDPTX_PE_LEVEL_3   0x1B
    #define XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK   0x00000003
    #define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK   0x0000000C
    #define XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK   0x00000010
    #define XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK   0x00000020
    #define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK   0x00000020
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK   0x00030000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT   16
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK   0x000C0000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT   18
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK   0x00300000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT   20
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK   0x00C00000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT   22
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK   0x03000000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT   24
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK   0x0C000000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT   26
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK   0x30000000
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT   28
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK   0xC0000000
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT   30
    #define XDPTX_PHY_STATUS_ALL_LANES_READY_MASK   0x0000003F
    #define XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK   0x000F
    #define XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK   0x0080
    #define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK   0xFF00
    #define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT   16

    Defines
    #define XDPTX_VC_PAYLOAD_BUFFER_ADDR   0x0800
    #define XDptx_ReadReg(BaseAddress, RegOffset)   XDptx_In32((BaseAddress) + (RegOffset))
    #define XDptx_WriteReg(BaseAddress, RegOffset, Data)   XDptx_Out32((BaseAddress) + (RegOffset), (Data))
    
-
    Define Documentation
    
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    #define XDPTX_AUX_ADDRESS   0x0108          
    
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-Specifies the address of current AUX command. 
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    #define XDPTX_AUX_CLK_DIVIDER   0x010C          
    
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-Clock divider value for generating the internal 1MHz clock. 
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    #define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK   0x00000F00          
    
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-AUX (noise) signal width filter. 
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    #define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT   8          
    
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-Shift bits for AUX signal width filter. 
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    #define XDPTX_AUX_CLK_DIVIDER_VAL_MASK   0x0000000F          
    
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-Clock divider value. 
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    #define XDPTX_AUX_CMD   0x0100          
    
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-Initiates AUX commands. 
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    #define XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN   0x00001000          
    
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-Address only transfer enable (STOP will be sent after command). 
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    #define XDPTX_AUX_CMD_I2C_READ   0x1          
    
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-I2C-over-AUX read command. 
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    #define XDPTX_AUX_CMD_I2C_READ_MOT   0x5          
    
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-I2C-over-AUX read MOT (middle-of-transaction) command. 
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    #define XDPTX_AUX_CMD_I2C_WRITE   0x0          
    
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-I2C-over-AUX write command. 
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    #define XDPTX_AUX_CMD_I2C_WRITE_MOT   0x4          
    
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-I2C-over-AUX write MOT (middle-of-transaction) command. 
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    #define XDPTX_AUX_CMD_I2C_WRITE_STATUS   0x2          
    
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-I2C-over-AUX write status command. 
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    #define XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT   0x6          
    
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-I2C-over-AUX write status MOT (middle-of- transaction) command. 
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    #define XDPTX_AUX_CMD_MASK   0x00000F00          
    
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-AUX command. 
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    #define XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK   0x0000000F          
    
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-Number of bytes to transfer with the current AUX command. 
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    #define XDPTX_AUX_CMD_READ   0x9          
    
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-AUX read command. 
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    #define XDPTX_AUX_CMD_SHIFT   8          
    
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-Shift bits for command. 
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    #define XDPTX_AUX_CMD_WRITE   0x8          
    
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-AUX write command. 
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    #define XDPTX_AUX_REPLY_CODE   0x0138          
    
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-Reply code received from the most recent AUX command. 
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    #define XDPTX_AUX_REPLY_CODE_ACK   0x0          
    
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-AUX command ACKed. 
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    #define XDPTX_AUX_REPLY_CODE_DEFER   0x2          
    
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-AUX command deferred. 
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    #define XDPTX_AUX_REPLY_CODE_I2C_ACK   0x0          
    
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-I2C-over-AUX command not ACKed. 
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    #define XDPTX_AUX_REPLY_CODE_I2C_DEFER   0x8          
    
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-I2C-over-AUX command deferred. 
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    #define XDPTX_AUX_REPLY_CODE_I2C_NACK   0x4          
    
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-I2C-over-AUX command not ACKed. 
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    #define XDPTX_AUX_REPLY_CODE_NACK   0x1          
    
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-AUX command not ACKed. 
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    #define XDPTX_AUX_REPLY_COUNT   0x013C          
    
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-Number of reply transactions receieved over AUX. 
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    #define XDPTX_AUX_REPLY_DATA   0x0134          
    
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-Reply data received during the AUX reply. 
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    #define XDPTX_AUX_WRITE_FIFO   0x0104          
    
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-Write data for the current AUX command. 
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    #define XDPTX_CORE_ID   0x00FC          
    
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-DisplayPort revision. 
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    #define XDPTX_CORE_ID_DP_MJR_VER_MASK   0x0000F000          
    
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-DisplayPort protocol major version. 
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    #define XDPTX_CORE_ID_DP_MJR_VER_SHIFT   24          
    
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-Shift bits for DisplayPort protocol major version. 
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    #define XDPTX_CORE_ID_DP_MNR_VER_MASK   0x00000F00          
    
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-DisplayPort protocol minor version. 
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    #define XDPTX_CORE_ID_DP_MNR_VER_SHIFT   16          
    
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-Shift bits for DisplayPort protocol major version. 
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    #define XDPTX_CORE_ID_DP_REV_MASK   0x000000F0          
    
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-DisplayPort protocol revision. 
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    #define XDPTX_CORE_ID_DP_REV_SHIFT   8          
    
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-Shift bits for DisplayPort protocol revision. 
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    #define XDPTX_CORE_ID_TYPE_MASK   0x0000000F          
    
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-Core type. 
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    #define XDPTX_CORE_ID_TYPE_RX   0x1          
    
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-Core is a receiver. 
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    #define XDPTX_CORE_ID_TYPE_TX   0x0          
    
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-Core is a transmitter. 
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    #define XDPTX_DOWNSPREAD_CTRL   0x0018          
    
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-Enable a 0.5% spreading of the clock. 
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    #define XDPTX_ENABLE   0x0080          
    
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-Enable the basic operations of the transmitter or output stuffing symbols if disabled. 
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    #define XDPTX_ENABLE_MAIN_STREAM   0x0084          
    
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-Enable transmission of main link video info. 
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    #define XDPTX_ENABLE_SEC_STREAM   0x0088          
    
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-Enable the transmission of secondary link info. 
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    #define XDPTX_ENHANCED_FRAME_EN   0x0008          
    
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-Enable enhanced framing symbol sequence. 
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    #define XDPTX_FORCE_SCRAMBLER_RESET   0x00C0          
    
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-Force a scrambler reset. 
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    #define XDPTX_FRAC_BYTES_PER_TU   0x01C8          
    
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-The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value. 
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    #define XDPTX_FRAC_BYTES_PER_TU_STREAM2   0x0548          
    
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-The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value. 
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    #define XDPTX_FRAC_BYTES_PER_TU_STREAM3   0x0598          
    
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-The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value. 
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    #define XDPTX_FRAC_BYTES_PER_TU_STREAM4   0x05E8          
    
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-The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value. 
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    #define XDPTX_GT_DRP_CHANNEL_STATUS   0x02A8          
    
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-Provides access to GT DRP channel status. 
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    #define XDPTX_GT_DRP_COMMAND   0x02A0          
    
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-Provides acces to the GT DRP ports. 
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    #define XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK   0x000F          
    
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-DRP address. 
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    #define XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK   0x0080          
    
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-DRP read/write command (Read=0, Write=1). 
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    #define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK   0xFF00          
    
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-DRP write data. 
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    #define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT   16          
    
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-Shift bits for DRP write data. 
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    #define XDPTX_GT_DRP_READ_DATA   0x02A4          
    
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-Provides access to GT DRP read data. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_HPD_DURATION   0x0150          
    
-
    
-
    
-
-
    
-Duration of the HPD pulse in microseconds. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INIT_WAIT   0x01CC          
    
-
    
-
    
-
-
    
-Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INIT_WAIT_STREAM2   0x054C          
    
-
    
-
    
-
-
    
-Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INIT_WAIT_STREAM3   0x059C          
    
-
    
-
    
-
-
    
-Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INIT_WAIT_STREAM4   0x05EC          
    
-
    
-
    
-
-
    
-Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_MASK   0x0144          
    
-
    
-
    
-
-
    
-Masks the specified interrupt sources. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK   0x00000020          
    
-
    
-
    
-
-
    
-Mask extended packet transmit interrupt. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK   0x00000002          
    
-
    
-
    
-
-
    
-Mask HPD event interrupt. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK   0x00000001          
    
-
    
-
    
-
-
    
-Mask HPD IRQ interrupt. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK   0x00000010          
    
-
    
-
    
-
-
    
-Mask HPD pulse detected interrupt. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK   0x00000004          
    
-
    
-
    
-
-
    
-Mask reply received interrupt. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK   0x00000008          
    
-
    
-
    
-
-
    
-Mask reply received interrupt. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_SIG_STATE   0x0130          
    
-
    
-
    
-
-
    
-The raw signal values for interupt events. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK   0x00000001          
    
-
    
-
    
-
-
    
-Raw state of the HPD pin on the DP connector. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK   0x00000004          
    
-
    
-
    
-
-
    
-A reply is currently being received. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK   0x00000008          
    
-
    
-
    
-
-
    
-A reply timeout has occurred. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK   0x00000002          
    
-
    
-
    
-
-
    
-A request is currently being sent. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_STATUS   0x0140          
    
-
    
-
    
-
-
    
-Status for interrupt events. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK   0x00000020          
    
-
    
-
    
-
-
    
-Extended packet has been transmitted and the core is ready to accept a new packet. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK   0x00000002          
    
-
    
-
    
-
-
    
-Detected the presence of the HPD signal. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK   0x00000001          
    
-
    
-
    
-
-
    
-Detected an IRQ framed with the proper timing on the HPD signal. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK   0x00000010          
    
-
    
-
    
-
-
    
-A pulse on the HPD line was detected. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK   0x00000004          
    
-
    
-
    
-
-
    
-An AUX reply transaction has been detected. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK   0x00000008          
    
-
    
-
    
-
-
    
-A reply timeout has occurred. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_LANE_COUNT_SET   0x0004          
    
-
    
-
    
-
-
    
-Set lane count setting. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_LINK_BW_SET   0x0000          
    
-
    
-
    
-
-
    
-Set main link bandwidth setting. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_LINK_BW_SET_162GBPS   0x06          
    
-
    
-
    
-
-
    
-1.62 Gbps link rate. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_LINK_BW_SET_270GBPS   0x0A          
    
-
    
-
    
-
-
    
-2.70 Gbps link rate. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_LINK_BW_SET_540GBPS   0x14          
    
-
    
-
    
-
-
    
-5.40 Gbps link rate. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_LINK_QUAL_PATTERN_SET   0x0010          
    
-
    
-
    
-
-
    
-Transmit the link quality pattern. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST   0x1          
    
-
    
-
    
-
-
    
-D10.2 unscrambled test pattern transmitted. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_LINK_QUAL_PATTERN_SET_OFF   0x0          
    
-
    
-
    
-
-
    
-Link quality test pattern not transmitted. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_LINK_QUAL_PATTERN_SET_PRBS7   0x3          
    
-
    
-
    
-
-
    
-Pseudo random bit sequence 7 transmitted. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_LINK_QUAL_PATTERN_SET_SER_MES   0x2          
    
-
    
-
    
-
-
    
-Symbol error rate measurement pattern transmitted. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_M_VID   0x01AC          
    
-
    
-
    
-
-
    
-M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_M_VID_STREAM2   0x052C          
    
-
    
-
    
-
-
    
-M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_M_VID_STREAM3   0x057C          
    
-
    
-
    
-
-
    
-M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_M_VID_STREAM4   0x05CC          
    
-
    
-
    
-
-
    
-M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM2_HRES   0x0514          
    
-
    
-
    
-
-
    
-Number of active pixels per line (the horizontal resolution). 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM2_HSTART   0x051C          
    
-
    
-
    
-
-
    
-Number of clocks between the leading edge of the horizontal sync and the start of active data. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM2_HSWIDTH   0x050C          
    
-
    
-
    
-
-
    
-Width of the horizontal sync pulse. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM2_HTOTAL   0x0500          
    
-
    
-
    
-
-
    
-Total number of clocks in the horizontal framing period. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM2_INTERLACED   0x0540          
    
-
    
-
    
-
-
    
-Video is interlaced. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM2_MISC0   0x0524          
    
-
    
-
    
-
-
    
-Miscellaneous stream attributes. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM2_MISC1   0x0528          
    
-
    
-
    
-
-
    
-Miscellaneous stream attributes. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM2_POLARITY   0x0508          
    
-
    
-
    
-
-
    
-Polarity for the video sync signals. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM2_VRES   0x0518          
    
-
    
-
    
-
-
    
-Number of active lines (the vertical resolution). 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM2_VSTART   0x0520          
    
-
    
-
    
-
-
    
-Number of lines between the leading edge of the vertical sync and the first line of active data. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM2_VSWIDTH   0x0510          
    
-
    
-
    
-
-
    
-Width of the vertical sync pulse. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM2_VTOTAL   0x0504          
    
-
    
-
    
-
-
    
-Total number of lines in the video frame. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM3_HRES   0x0564          
    
-
    
-
    
-
-
    
-Number of active pixels per line (the horizontal resolution). 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM3_HSTART   0x056C          
    
-
    
-
    
-
-
    
-Number of clocks between the leading edge of the horizontal sync and the start of active data. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM3_HSWIDTH   0x055C          
    
-
    
-
    
-
-
    
-Width of the horizontal sync pulse. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM3_HTOTAL   0x0550          
    
-
    
-
    
-
-
    
-Total number of clocks in the horizontal framing period. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM3_INTERLACED   0x0590          
    
-
    
-
    
-
-
    
-Video is interlaced. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM3_MISC0   0x0574          
    
-
    
-
    
-
-
    
-Miscellaneous stream attributes. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM3_MISC1   0x0578          
    
-
    
-
    
-
-
    
-Miscellaneous stream attributes. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM3_POLARITY   0x0558          
    
-
    
-
    
-
-
    
-Polarity for the video sync signals. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM3_VRES   0x0568          
    
-
    
-
    
-
-
    
-Number of active lines (the vertical resolution). 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM3_VSTART   0x0570          
    
-
    
-
    
-
-
    
-Number of lines between the leading edge of the vertical sync and the first line of active data. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM3_VSWIDTH   0x0560          
    
-
    
-
    
-
-
    
-Width of the vertical sync pulse. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM3_VTOTAL   0x0554          
    
-
    
-
    
-
-
    
-Total number of lines in the video frame. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM4_HRES   0x05B4          
    
-
    
-
    
-
-
    
-Number of active pixels per line (the horizontal resolution). 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM4_HSTART   0x05BC          
    
-
    
-
    
-
-
    
-Number of clocks between the leading edge of the horizontal sync and the start of active data. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM4_HSWIDTH   0x05AC          
    
-
    
-
    
-
-
    
-Width of the horizontal sync pulse. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM4_HTOTAL   0x05A0          
    
-
    
-
    
-
-
    
-Total number of clocks in the horizontal framing period. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM4_INTERLACED   0x05E0          
    
-
    
-
    
-
-
    
-Video is interlaced. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM4_MISC0   0x05C4          
    
-
    
-
    
-
-
    
-Miscellaneous stream attributes. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM4_MISC1   0x05C8          
    
-
    
-
    
-
-
    
-Miscellaneous stream attributes. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM4_POLARITY   0x05A8          
    
-
    
-
    
-
-
    
-Polarity for the video sync signals. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM4_VRES   0x05B8          
    
-
    
-
    
-
-
    
-Number of active lines (the vertical resolution). 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM4_VSTART   0x05C0          
    
-
    
-
    
-
-
    
-Number of lines between the leading edge of the vertical sync and the first line of active data. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM4_VSWIDTH   0x05B0          
    
-
    
-
    
-
-
    
-Width of the vertical sync pulse. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM4_VTOTAL   0x05A4          
    
-
    
-
    
-
-
    
-Total number of lines in the video frame. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM_HRES   0x0194          
    
-
    
-
    
-
-
    
-Number of active pixels per line (the horizontal resolution). 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM_HSTART   0x019C          
    
-
    
-
    
-
-
    
-Number of clocks between the leading edge of the horizontal sync and the start of active data. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM_HSWIDTH   0x018C          
    
-
    
-
    
-
-
    
-Width of the horizontal sync pulse. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM_HTOTAL   0x0180          
    
-
    
-
    
-
-
    
-Total number of clocks in the horizontal framing period. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM_INTERLACED   0x01C0          
    
-
    
-
    
-
-
    
-Video is interlaced. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM_MISC0   0x01A4          
    
-
    
-
    
-
-
    
-Miscellaneous stream attributes. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM_MISC1   0x01A8          
    
-
    
-
    
-
-
    
-Miscellaneous stream attributes. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM_POLARITY   0x0188          
    
-
    
-
    
-
-
    
-Polarity for the video sync signals. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM_VRES   0x0198          
    
-
    
-
    
-
-
    
-Number of active lines (the vertical resolution). 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM_VSTART   0x01A0          
    
-
    
-
    
-
-
    
-Number of lines between the leading edge of the vertical sync and the first line of active data. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM_VSWIDTH   0x0190          
    
-
    
-
    
-
-
    
-Width of the vertical sync pulse. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAM_VTOTAL   0x0184          
    
-
    
-
    
-
-
    
-Total number of lines in the video frame. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_MASK   0x000000E0          
    
-
    
-
    
-
-
    
-Bit depth per color component (BDC). 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT   5          
    
-
    
-
    
-
-
    
-Shift bits for BDC. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK   0x00000006          
    
-
    
-
    
-
-
    
-Component format. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT   1          
    
-
    
-
    
-
-
    
-Shift bits for component format. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK   0x00000008          
    
-
    
-
    
-
-
    
-Dynamic range. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT   3          
    
-
    
-
    
-
-
    
-Shift bits for dynamic range. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK   0x00000001          
    
-
    
-
    
-
-
    
-Synchronous clock. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK   0x00000010          
    
-
    
-
    
-
-
    
-YCbCr colorimetry. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT   4          
    
-
    
-
    
-
-
    
-Shift bits for YCbCr colorimetry. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK   0x00000001          
    
-
    
-
    
-
-
    
-Interlaced vertical total even. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK   0x00000006          
    
-
    
-
    
-
-
    
-Stereo video attribute. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT   1          
    
-
    
-
    
-
-
    
-Shift bits for stereo video attribute. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK   0x00000001          
    
-
    
-
    
-
-
    
-Polarity of the horizontal sync pulse. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK   0x00000002          
    
-
    
-
    
-
-
    
-Polarity of the vertical sync pulse. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT   1          
    
-
    
-
    
-
-
    
-Shift bits for polarity of the vertical sync pulse. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MIN_BYTES_PER_TU   0x01C4          
    
-
    
-
    
-
-
    
-The minimum number of bytes per transfer unit. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MIN_BYTES_PER_TU_STREAM2   0x0544          
    
-
    
-
    
-
-
    
-The minimum number of bytes per transfer unit. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MIN_BYTES_PER_TU_STREAM3   0x0594          
    
-
    
-
    
-
-
    
-The minimum number of bytes per transfer unit. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_MIN_BYTES_PER_TU_STREAM4   0x05E4          
    
-
    
-
    
-
-
    
-The minimum number of bytes per transfer unit. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_N_VID   0x01B4          
    
-
    
-
    
-
-
    
-N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_N_VID_STREAM2   0x0534          
    
-
    
-
    
-
-
    
-N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_N_VID_STREAM3   0x0584          
    
-
    
-
    
-
-
    
-N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_N_VID_STREAM4   0x05D4          
    
-
    
-
    
-
-
    
-N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PE_LEVEL_0   0x00          
    
-
    
-
    
-
-
    
-Pre-emphasis level 0. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PE_LEVEL_1   0x0E          
    
-
    
-
    
-
-
    
-Pre-emphasis level 1. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PE_LEVEL_2   0x14          
    
-
    
-
    
-
-
    
-Pre-emphasis level 2. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PE_LEVEL_3   0x1B          
    
-
    
-
    
-
-
    
-Pre-emphasis level 3. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_CLOCK_SELECT   0x0234          
    
-
    
-
    
-
-
    
-Instructs the PHY PLL to generate the proper clock frequency for the required link rate. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_CLOCK_SELECT_162GBPS   0x1          
    
-
    
-
    
-
-
    
-1.62 Gbps link. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_CLOCK_SELECT_270GBPS   0x3          
    
-
    
-
    
-
-
    
-2.70 Gbps link. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_CLOCK_SELECT_540GBPS   0x5          
    
-
    
-
    
-
-
    
-5.40 Gbps link. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_CONFIG   0x0200          
    
-
    
-
    
-
-
    
-Transceiver PHY reset and configuration. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK   0x0010003          
    
-
    
-
    
-
-
    
-Rest GT and PHY. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_CONFIG_GTTX_RESET_MASK   0x0010002          
    
-
    
-
    
-
-
    
-Hold GTTXRESET in reset. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK   0x0010000          
    
-
    
-
    
-
-
    
-Release reset. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_CONFIG_PHY_RESET_MASK   0x0010001          
    
-
    
-
    
-
-
    
-Hold the PHY in reset. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK   0x001E000          
    
-
    
-
    
-
-
    
-Set TX_PHY_LOOPBACK. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK   0x0010200          
    
-
    
-
    
-
-
    
-HOLD TX_PHY_PCS reset. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK   0x0010100          
    
-
    
-
    
-
-
    
-Hold TX_PHY_PMA reset. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK   0x0010400          
    
-
    
-
    
-
-
    
-Set TX_PHY_POLARITY. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK   0x0011000          
    
-
    
-
    
-
-
    
-Set TX_PHY_PRBSFORCEERR. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_POSTCURSOR_LANE_0   0x024C          
    
-
    
-
    
-
-
    
-Controls the post-cursor level. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_POSTCURSOR_LANE_1   0x0250          
    
-
    
-
    
-
-
    
-Controls the post-cursor level. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_POSTCURSOR_LANE_2   0x0254          
    
-
    
-
    
-
-
    
-Controls the post-cursor level. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_POSTCURSOR_LANE_3   0x0258          
    
-
    
-
    
-
-
    
-Controls the post-cursor level. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_PRECURSOR_LANE_0   0x023C          
    
-
    
-
    
-
-
    
-Controls the pre-cursor level. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_PRECURSOR_LANE_1   0x0240          
    
-
    
-
    
-
-
    
-Controls the pre-cursor level. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_PRECURSOR_LANE_2   0x0244          
    
-
    
-
    
-
-
    
-Controls the pre-cursor level. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_PRECURSOR_LANE_3   0x0248          
    
-
    
-
    
-
-
    
-Controls the pre-cursor level. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS   0x0280          
    
-
    
-
    
-
-
    
-Current PHY status. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_ALL_LANES_READY_MASK   0x0000003F          
    
-
    
-
    
-
-
    
-All lanes are ready. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK   0x00000020          
    
-
    
-
    
-
-
    
-FPGA fabric clock PLL locked. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK   0x00000010          
    
-
    
-
    
-
-
    
-PLL locked for lanes 0 and 1. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK   0x00000020          
    
-
    
-
    
-
-
    
-PLL locked for lanes 2 and 3. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK   0x00000003          
    
-
    
-
    
-
-
    
-Reset done for lanes 0 and 1. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK   0x0000000C          
    
-
    
-
    
-
-
    
-Reset done for lanes 2 and 3. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK   0x00030000          
    
-
    
-
    
-
-
    
-TX buffer status lane 0. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT   16          
    
-
    
-
    
-
-
    
-Shift bits for TX buffer status lane 0. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK   0x00300000          
    
-
    
-
    
-
-
    
-TX buffer status lane 1. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT   20          
    
-
    
-
    
-
-
    
-Shift bits for TX buffer status lane 1. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK   0x03000000          
    
-
    
-
    
-
-
    
-TX buffer status lane 2. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT   24          
    
-
    
-
    
-
-
    
-Shift bits for TX buffer status lane 2. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK   0x30000000          
    
-
    
-
    
-
-
    
-TX buffer status lane 3. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT   28          
    
-
    
-
    
-
-
    
-Shift bits for TX buffer status lane 3. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK   0x000C0000          
    
-
    
-
    
-
-
    
-TX error on lane 0. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT   18          
    
-
    
-
    
-
-
    
-Shift bits for TX error on lane 0. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK   0x00C00000          
    
-
    
-
    
-
-
    
-TX error on lane 1. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT   22          
    
-
    
-
    
-
-
    
-Shift bits for TX error on lane 1. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK   0x0C000000          
    
-
    
-
    
-
-
    
-TX error on lane 2. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT   26          
    
-
    
-
    
-
-
    
-Shift bits for TX error on lane 2. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK   0xC0000000          
    
-
    
-
    
-
-
    
-TX error on lane 3. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT   30          
    
-
    
-
    
-
-
    
-Shift bits for TX error on lane 3. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_TRANSMIT_PRBS7   0x0230          
    
-
    
-
    
-
-
    
-Enable pseudo random bit sequence 7 pattern transmission for link quality assessment. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_0   0x0220          
    
-
    
-
    
-
-
    
-Controls the differential voltage swing. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_1   0x0224          
    
-
    
-
    
-
-
    
-Controls the differential voltage swing. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_2   0x0228          
    
-
    
-
    
-
-
    
-Controls the differential voltage swing. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_PHY_VOLTAGE_DIFF_LANE_3   0x022C          
    
-
    
-
    
-
-
    
-Controls the differential voltage swing. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-          
-          
-          
-        
-      
    #define XDptx_ReadReg          (BaseAddress,         
    RegOffset            )    XDptx_In32((BaseAddress) + (RegOffset))
    
-
    
-
    
-
-
    
-This is a low-level function that reads from the specified register.
    
-
    Parameters:
    
-  
-    
-    
-  
    BaseAddress is the base address of the device. 
    RegOffset is the register offset to be read from.
    
-
    
-
    Returns:
    The 32-bit value of the specified register.
    
-
    Note:
    C-style signature: u32 XDptx_ReadReg(u32 BaseAddress, u32 RegOffset) 
    
-
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_REPLY_DATA_COUNT   0x0148          
    
-
    
-
    
-
-
    
-Total number of data bytes actually received during a transaction. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_REPLY_STATUS   0x014C          
    
-
    
-
    
-
-
    
-Reply status of most recent AUX transaction. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_REPLY_STATUS_REPLY_ERROR_MASK   0x00000008          
    
-
    
-
    
-
-
    
-Detected an error in the AUX reply of the most recent transaction. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK   0x00000002          
    
-
    
-
    
-
-
    
-AUX reply is currently being received. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK   0x00000001          
    
-
    
-
    
-
-
    
-AUX transaction is complete and a valid reply transaction received. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK   0x00000FF0          
    
-
    
-
    
-
-
    
-Internal AUX reply state machine status bits. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT   4          
    
-
    
-
    
-
-
    
-Shift bits for the internal AUX reply state machine status. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK   0x00000004          
    
-
    
-
    
-
-
    
-AUX request is currently being transmitted. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_SCRAMBLING_DISABLE   0x0014          
    
-
    
-
    
-
-
    
-Disable scrambler and transmit all symbols. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_SOFT_RESET   0x001C          
    
-
    
-
    
-
-
    
-Software reset. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_SOFT_RESET_AUX_MASK   0x00000080          
    
-
    
-
    
-
-
    
-Reset AUX logic. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK   0x00000001          
    
-
    
-
    
-
-
    
-Reset video logic. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK   0x00000002          
    
-
    
-
    
-
-
    
-Reset video logic. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK   0x00000004          
    
-
    
-
    
-
-
    
-Reset video logic. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK   0x00000008          
    
-
    
-
    
-
-
    
-Reset video logic. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK   0x0000000F          
    
-
    
-
    
-
-
    
-Reset video logic for all streams. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_STREAM0   0x01D0          
    
-
    
-
    
-
-
    
-Average stream symbol timeslots per MTP config. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_STREAM1   0x01D4          
    
-
    
-
    
-
-
    
-Average stream symbol timeslots per MTP config. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_STREAM2   0x01D8          
    
-
    
-
    
-
-
    
-Average stream symbol timeslots per MTP config. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_STREAM3   0x01DC          
    
-
    
-
    
-
-
    
-Average stream symbol timeslots per MTP config. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TRAINING_PATTERN_SET   0x000C          
    
-
    
-
    
-
-
    
-Set the link training pattern. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TRAINING_PATTERN_SET_OFF   0x0          
    
-
    
-
    
-
-
    
-Training off. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TRAINING_PATTERN_SET_TP1   0x1          
    
-
    
-
    
-
-
    
-Training pattern 1 used for clock recovery. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TRAINING_PATTERN_SET_TP2   0x2          
    
-
    
-
    
-
-
    
-Training pattern 2 used for channel equalization. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TRAINING_PATTERN_SET_TP3   0x3          
    
-
    
-
    
-
-
    
-Training pattern 3 used for channel equalization for cores with DP v1.2. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TU_SIZE   0x01B0          
    
-
    
-
    
-
-
    
-Size of a transfer unit in the framing logic. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TU_SIZE_STREAM2   0x0530          
    
-
    
-
    
-
-
    
-Size of a transfer unit in the framing logic. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TU_SIZE_STREAM3   0x0580          
    
-
    
-
    
-
-
    
-Size of a transfer unit in the framing logic. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TU_SIZE_STREAM4   0x05D0          
    
-
    
-
    
-
-
    
-Size of a transfer unit in the framing logic. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TX_AUDIO_CHANNELS   0x0304          
    
-
    
-
    
-
-
    
-Used to input active channel count. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TX_AUDIO_CONTROL   0x0300          
    
-
    
-
    
-
-
    
-Enables audio stream packets in main link and buffer control. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TX_AUDIO_EXT_DATA   0x0330          
    
-
    
-
    
-
-
    
-Word formatted as per extension packet. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TX_AUDIO_INFO_DATA   0x0308          
    
-
    
-
    
-
-
    
-Word formatted as per CEA 861-C info frame. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TX_AUDIO_MAUD   0x0328          
    
-
    
-
    
-
-
    
-M value of audio stream as computed by the transmitter when audio clock and link clock are synchronous. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TX_AUDIO_NAUD   0x032C          
    
-
    
-
    
-
-
    
-N value of audio stream as computed by the transmitter when audio clock and link clock are synchronous. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TX_MST_CONFIG   0x00D0          
    
-
    
-
    
-
-
    
-Enable MST. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TX_MST_CONFIG_MST_EN_MASK   0x00000001          
    
-
    
-
    
-
-
    
-Enable MST. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK   0x00000002          
    
-
    
-
    
-
-
    
-The VC payload has been updated in the sink. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TX_PHY_POWER_DOWN   0x0238          
    
-
    
-
    
-
-
    
-Controls PHY power down. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_TX_USER_FIFO_OVERFLOW   0x0110          
    
-
    
-
    
-
-
    
-Indicates an overflow in user FIFO. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_USER_DATA_COUNT_PER_LANE   0x01BC          
    
-
    
-
    
-
-
    
-Used to translate the number of pixels per line to the native internal 16-bit datapath. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM2   0x053C          
    
-
    
-
    
-
-
    
-Used to translate the number of pixels per line to the native internal 16-bit datapath. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM3   0x058C          
    
-
    
-
    
-
-
    
-Used to translate the number of pixels per line to the native internal 16-bit datapath. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM4   0x05DC          
    
-
    
-
    
-
-
    
-Used to translate the number of pixels per line to the native internal 16-bit datapath. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_USER_PIXEL_WIDTH   0x01B8          
    
-
    
-
    
-
-
    
-Selects the width of the user data input port. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_USER_PIXEL_WIDTH_STREAM2   0x0538          
    
-
    
-
    
-
-
    
-Selects the width of the user data input port. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_USER_PIXEL_WIDTH_STREAM3   0x0588          
    
-
    
-
    
-
-
    
-Selects the width of the user data input port. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_USER_PIXEL_WIDTH_STREAM4   0x05D8          
    
-
    
-
    
-
-
    
-Selects the width of the user data input port. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VC_PAYLOAD_BUFFER_ADDR   0x0800          
    
-
    
-
    
-
-
    
-Virtual channel payload table (0xFF bytes). 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VERSION   0x00F8          
    
-
    
-
    
-
-
    
-Core version. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VERSION_CORE_PATCH_MASK   0x00000030          
    
-
    
-
    
-
-
    
-Core patch details. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VERSION_CORE_PATCH_SHIFT   8          
    
-
    
-
    
-
-
    
-Shift bits for core patch details. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VERSION_CORE_VER_MJR_MASK   0x0000F000          
    
-
    
-
    
-
-
    
-Core major version. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VERSION_CORE_VER_MJR_SHIFT   24          
    
-
    
-
    
-
-
    
-Shift bits for core major version. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VERSION_CORE_VER_MNR_MASK   0x00000F00          
    
-
    
-
    
-
-
    
-Core minor version. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VERSION_CORE_VER_MNR_SHIFT   16          
    
-
    
-
    
-
-
    
-Shift bits for core minor version. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VERSION_CORE_VER_REV_MASK   0x000000C0          
    
-
    
-
    
-
-
    
-Core version revision. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VERSION_CORE_VER_REV_SHIFT   12          
    
-
    
-
    
-
-
    
-Shift bits for core version revision. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VERSION_INTER_REV_MASK   0x0000000F          
    
-
    
-
    
-
-
    
-Internal revision. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VS_LEVEL_0   0x2          
    
-
    
-
    
-
-
    
-Voltage swing level 0. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VS_LEVEL_1   0x5          
    
-
    
-
    
-
-
    
-Voltage swing level 1. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VS_LEVEL_2   0x8          
    
-
    
-
    
-
-
    
-Voltage swing level 2. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VS_LEVEL_3   0xF          
    
-
    
-
    
-
-
    
-Voltage swing level 3. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-        
-      
    #define XDPTX_VS_LEVEL_OFFSET   0x4          
    
-
    
-
    
-
-
    
-Voltage swing compensation offset used when there's no redriver in display path. 
-
    
-
    
-
-
    
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-          
-          
-          
-          
-          
-          
-        
-      
    #define XDptx_WriteReg          (BaseAddress,         
    RegOffset,         
    Data            )    XDptx_Out32((BaseAddress) + (RegOffset), (Data))
    
-
    
-
    
-
-
    
-This is a low-level function that writes to the specified register.
    
-
    Parameters:
    
-  
-    
-    
-    
-  
    BaseAddress is the base address of the device. 
    RegOffset is the register offset to write to. 
    Data is the 32-bit data to write to the specified register.
    
-
    
-
    Note:
    C-style signature: void XDptx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) 
    
-
-
    
-
    
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__selftest_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__selftest_8c.html
deleted file mode 100644
index fd79fe0a..00000000
--- a/XilinxProcessorIPLib/drivers/dptx/doc/html/xdptx__selftest_8c.html
+++ /dev/null
@@ -1,71 +0,0 @@
-
-
-   
-
-   xdptx_selftest.c File Reference
-
-
-
-
    Xilinx Processor IP Library
    
-Software Drivers
-
    
-
-
    
-  
    
-
    
-  
    
-
    xdptx_selftest.c File Reference
    Detailed Description
    
-This file contains a diagnostic self-test function for the XDptx driver.
    
-
    - MODIFICATION HISTORY:
    
-
     Ver   Who  Date     Changes
- ----- ---- -------- -----------------------------------------------
- 1.00a als  05/17/14 Initial release.
- 
     
-
    
-#include "xdptx.h"
    
-#include "xstatus.h"
    
-
-
-
-
-
-

    Functions
    u32 XDptx_SelfTest (XDptx *InstancePtr)
    
-
    Function Documentation
    
-
-
    
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-        
-      
    u32 XDptx_SelfTest           (XDptx *  InstancePtr           ) 
    
-
    
-
    
-
-
    
-This function runs a self-test on the XDptx driver/device. The test attempts to intialize the DisplayPort TX core, train the main link at the highest common capabilities between the core and the sink, and checks the status of the link after training.
    
-
    Parameters:
    
-  
-    
-  
    InstancePtr is a pointer to the XDptx instance.
    
-
    
-
    Returns:
      
-
    • XST_SUCCESS if the self-test passed. The main link has been trained and established successfully.
    • XST_FAILURE otherwise. 
    
-
    
-
-
    
-
    
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.