From 0b34da9303f94b83370389f78e72340e6089b938 Mon Sep 17 00:00:00 2001 From: Andrei-Liviu Simion Date: Fri, 6 Nov 2015 01:25:08 -0700 Subject: [PATCH] vphy: gt: Modified CDR configuration. For: - GTHE3 (DisplayPort), and - GTHE2. Signed-off-by: Andrei-Liviu Simion Acked-by: Srikanth Vemula --- .../drivers/vphy/src/xvphy_gthe2.c | 25 +++++++++---------- .../drivers/vphy/src/xvphy_gthe3.c | 11 +++----- 2 files changed, 15 insertions(+), 21 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/vphy/src/xvphy_gthe2.c b/XilinxProcessorIPLib/drivers/vphy/src/xvphy_gthe2.c index 3724e78d..325e900a 100644 --- a/XilinxProcessorIPLib/drivers/vphy/src/xvphy_gthe2.c +++ b/XilinxProcessorIPLib/drivers/vphy/src/xvphy_gthe2.c @@ -169,6 +169,7 @@ const XVphy_GtConfig Gthe2Config = { u32 XVphy_Gthe2CfgSetCdr(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId) { XVphy_Channel *ChPtr; + u32 PllClkInFreqHz; /* Set CDR values only for CPLLs. */ if ((ChId < XVPHY_CHANNEL_ID_CH1) || (ChId > XVPHY_CHANNEL_ID_CH4)) { @@ -176,22 +177,20 @@ u32 XVphy_Gthe2CfgSetCdr(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId) } ChPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(ChId)]; + PllClkInFreqHz = XVphy_GetQuadRefClkFreq(InstancePtr, QuadId, + ChPtr->CpllRefClkSel); /* Update the RXCDR_CFG2 settings. */ - ChPtr->PllParams.Cdr[0] = 0x0020; - ChPtr->PllParams.Cdr[1] = 0x07FE; - ChPtr->PllParams.Cdr[3] = (ChPtr->RxOutDiv == 1) ? 0xC208 : 0xC220; - ChPtr->PllParams.Cdr[4] = 0x0018; - - /* RxOutDiv = 1 => Cdr[2] = 0x2000 - * RxOutDiv = 2 => Cdr[2] = 0x1000 - * RxOutDiv = 4 => Cdr[2] = 0x0800 - * RxOutDiv = 8 => Cdr[2] = 0x0400 */ - u8 RxOutDiv = ChPtr->RxOutDiv; - ChPtr->PllParams.Cdr[2] = 0x2000; - while (RxOutDiv >>= 1) { - ChPtr->PllParams.Cdr[2] >>= 1; + ChPtr->PllParams.Cdr[0] = 0x0018; + if (PllClkInFreqHz == 270000000) { + ChPtr->PllParams.Cdr[1] = 0xC208; } + else { + ChPtr->PllParams.Cdr[1] = 0xC220; + } + ChPtr->PllParams.Cdr[2] = 0x1000; + ChPtr->PllParams.Cdr[3] = 0x07FE; + ChPtr->PllParams.Cdr[4] = 0x0020; return XST_SUCCESS; } diff --git a/XilinxProcessorIPLib/drivers/vphy/src/xvphy_gthe3.c b/XilinxProcessorIPLib/drivers/vphy/src/xvphy_gthe3.c index bb5a4d98..430aa87e 100644 --- a/XilinxProcessorIPLib/drivers/vphy/src/xvphy_gthe3.c +++ b/XilinxProcessorIPLib/drivers/vphy/src/xvphy_gthe3.c @@ -183,20 +183,15 @@ u32 XVphy_Gthe3CfgSetCdr(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId) if (InstancePtr->Config.RxProtocol == XVPHY_PROTOCOL_DP) { PllClkInFreqHz = XVphy_GetQuadRefClkFreq(InstancePtr, QuadId, ChPtr->CpllRefClkSel); - - if ((ChPtr->RxOutDiv == 1) && (PllClkInFreqHz == 270000000)) { + if (PllClkInFreqHz == 270000000) { ChPtr->PllParams.Cdr[2] = 0x0766; } - else if ((ChPtr->RxOutDiv == 2) && - (PllClkInFreqHz == 135000000)) { + else if (PllClkInFreqHz == 135000000) { ChPtr->PllParams.Cdr[2] = 0x0756; } /* RBR does not use DP159 forwarded clock and expects 162MHz. */ - else if (ChPtr->RxOutDiv == 2) { - ChPtr->PllParams.Cdr[2] = 0x0721; - } else { - Status = XST_FAILURE; + ChPtr->PllParams.Cdr[2] = 0x0721; } } else if (InstancePtr->Config.RxProtocol == XVPHY_PROTOCOL_HDMI) {