From 0ba5c5df85b7b27b0e6a84211193ac4794d480a9 Mon Sep 17 00:00:00 2001
From: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>
Date: Tue, 1 Jul 2014 11:32:35 +0530
Subject: [PATCH] hwicap: Add new version 10.0 and deprecate 9.0

Add new version 10.0 and deprecate 9.0

Signed-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
---
 .../drivers/hwicap/data/hwicap.mdd            |   43 +
 .../drivers/hwicap/data/hwicap.tcl            |   83 ++
 .../drivers/hwicap/data/hwicap_header.h       |   41 +
 .../drivers/hwicap/data/hwicap_tapp.tcl       |  135 ++
 .../drivers/hwicap/examples/index.html        |   23 +
 .../drivers/hwicap/examples/xhwicap_ff.c      |  255 ++++
 .../hwicap/examples/xhwicap_intr_example.c    |  434 ++++++
 .../examples/xhwicap_low_level_example.c      |  298 ++++
 .../drivers/hwicap/examples/xhwicap_lut.c     |  276 ++++
 .../hwicap/examples/xhwicap_read_config_reg.c |  353 +++++
 .../xhwicap_read_frame_polled_example.c       |  235 +++
 .../hwicap/examples/xhwicap_testapp_example.c |  178 +++
 .../drivers/hwicap/src/Makefile               |   30 +
 .../drivers/hwicap/src/xhwicap.c              | 1286 +++++++++++++++++
 .../drivers/hwicap/src/xhwicap.h              |  899 ++++++++++++
 .../drivers/hwicap/src/xhwicap_clb_ff.h       |  531 +++++++
 .../drivers/hwicap/src/xhwicap_clb_lut.h      |  909 ++++++++++++
 .../drivers/hwicap/src/xhwicap_clb_srinv.h    |  127 ++
 .../hwicap/src/xhwicap_device_read_frame.c    |  317 ++++
 .../hwicap/src/xhwicap_device_write_frame.c   |  509 +++++++
 .../drivers/hwicap/src/xhwicap_g.c            |   81 ++
 .../drivers/hwicap/src/xhwicap_i.h            |  581 ++++++++
 .../drivers/hwicap/src/xhwicap_intr.c         |  194 +++
 .../drivers/hwicap/src/xhwicap_l.h            |  413 ++++++
 .../drivers/hwicap/src/xhwicap_selftest.c     |  154 ++
 .../drivers/hwicap/src/xhwicap_sinit.c        |  101 ++
 .../drivers/hwicap/src/xhwicap_srp.c          |  328 +++++
 27 files changed, 8814 insertions(+)
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/data/hwicap.mdd
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/data/hwicap.tcl
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/data/hwicap_header.h
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/data/hwicap_tapp.tcl
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/examples/index.html
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_ff.c
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_intr_example.c
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_low_level_example.c
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_lut.c
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_read_config_reg.c
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_read_frame_polled_example.c
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_testapp_example.c
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/src/Makefile
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/src/xhwicap.c
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/src/xhwicap.h
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_clb_ff.h
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_clb_lut.h
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_clb_srinv.h
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_device_read_frame.c
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_device_write_frame.c
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_g.c
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_i.h
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_intr.c
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_l.h
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_selftest.c
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_sinit.c
 create mode 100755 XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_srp.c

diff --git a/XilinxProcessorIPLib/drivers/hwicap/data/hwicap.mdd b/XilinxProcessorIPLib/drivers/hwicap/data/hwicap.mdd
new file mode 100755
index 00000000..33ca15c7
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/data/hwicap.mdd
@@ -0,0 +1,43 @@
+###############################################################################
+#
+# Copyright (C) 2003 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+#
+##############################################################################
+OPTION psf_version = 2.1;
+
+BEGIN driver hwicap
+
+OPTION supported_peripherals = (axi_hwicap_v[2-9]_[0-9][3-9]_[a-z] axi_hwicap_v[0-9]_[0-9]); 
+OPTION driver_state = ACTIVE;
+OPTION copyfiles = all;
+OPTION VERSION = 10.0;
+OPTION NAME = hwicap;
+
+END DRIVER
diff --git a/XilinxProcessorIPLib/drivers/hwicap/data/hwicap.tcl b/XilinxProcessorIPLib/drivers/hwicap/data/hwicap.tcl
new file mode 100755
index 00000000..b6536493
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/data/hwicap.tcl
@@ -0,0 +1,83 @@
+###############################################################################
+#
+# Copyright (C) 2003 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+#
+# MODIFICATION HISTORY:
+# Ver      Who    Date     Changes
+# -------- ------ -------- ------------------------------------
+# 9.0     adk    12/10/13 Updated as per the New Tcl API's
+# 9.0     bss    02/20/14 Added kintex 8 and kintexu families
+##############################################################################
+#--------------------------------
+# Tcl procedure generate 
+#--------------------------------
+
+proc generate {drv_handle} {
+
+    # This returns the C_FAMILY parameter from the processor.
+    # MicroBlaze has C_FAMILY defined, but PowerPC does not.
+    set sw_proc_handle [get_sw_processor]
+    set prochandle [get_cells [get_property HW_INSTANCE $sw_proc_handle] ]
+    set proctype [string tolower [get_property SPECIAL $prochandle]]
+    set family [string tolower [get_property CONFIG.C_FAMILY $prochandle]]
+     
+    # Create a definition in a header file
+    set filename  "./src/xhwicap_family.h"
+    set filehandle [ open $filename a ]
+    ::hsm::utils::write_c_header $filehandle "Device family" 
+    if {[string compare $family "kintex7"] == 0} {
+    	puts $filehandle "#define XHI_FPGA_FAMILY 7\n"   	
+    } elseif {[string compare $family "virtex7"] == 0} {
+	    puts $filehandle "#define XHI_FPGA_FAMILY 8\n"
+    } elseif {[string compare $family "artix7"] == 0} {
+	    puts $filehandle "#define XHI_FPGA_FAMILY 9\n"
+    } elseif {[string compare $family "zynq"] == 0} {
+	    puts $filehandle "#define XHI_FPGA_FAMILY 10\n"
+    } elseif {[string compare $family "kintex8"] == 0} {
+    	    puts $filehandle "#define XHI_FPGA_FAMILY 11\n"
+    } elseif {[string compare $family "kintexu"] == 0} {
+    	    puts $filehandle "#define XHI_FPGA_FAMILY 11\n"
+    } else {
+            puts $filehandle "#define XHI_FPGA_FAMILY 1\n"
+    }
+    close $filehandle
+
+
+    # Generate #defines in xparameters.h
+    xdefine_include_file $drv_handle "xparameters.h" "XHwIcap" "NUM_INSTANCES" "C_BASEADDR" "C_HIGHADDR" "DEVICE_ID" "C_ICAP_DWIDTH" "C_MODE"
+       
+    # Generate the _g.c configuration file
+    xdefine_config_file $drv_handle "xhwicap_g.c" "XHwIcap"  "DEVICE_ID" "C_BASEADDR" "C_ICAP_DWIDTH" "C_MODE" 
+       
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "HwIcap" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_ICAP_DWIDTH" "C_MODE"
+
+}
+
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/data/hwicap_header.h b/XilinxProcessorIPLib/drivers/hwicap/data/hwicap_header.h
new file mode 100755
index 00000000..b9926045
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/data/hwicap_header.h
@@ -0,0 +1,41 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef HWICAP_HEADER_H		/* prevent circular inclusions */
+#define HWICAP_HEADER_H		/* by using protection macros */
+
+#include <xil_types.h>
+#include <xil_assert.h>
+#include "xstatus.h"
+
+XStatus HwIcapTestAppExample(u16 DeviceId);
+
+#endif
diff --git a/XilinxProcessorIPLib/drivers/hwicap/data/hwicap_tapp.tcl b/XilinxProcessorIPLib/drivers/hwicap/data/hwicap_tapp.tcl
new file mode 100755
index 00000000..ce338a34
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/data/hwicap_tapp.tcl
@@ -0,0 +1,135 @@
+###############################################################################
+#
+# Copyright (C) 2004 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+# MODIFICATION HISTORY:
+# Ver      Who    Date     Changes
+# -------- ------ -------- ------------------------------------
+# 9.0     adk    12/10/13 Updated as per the New Tcl API's
+##############################################################################
+
+## @BEGIN_CHANGELOG EDK_I_SP1
+##
+##  - Added support for generation of multiple applications.
+##    All TCL procedures are now required to have a software
+##    project type as its first argument
+##    
+## @END_CHANGELOG
+
+# Uses $XILINX_EDK/bin/lib/xillib_sw.tcl
+
+# -----------------------------------------------------------------
+# Software Project Types (swproj):
+#   0 : MemoryTest - Calls basic  memorytest routines from common driver dir
+#   1 : PeripheralTest - Calls any existing polled_example and/or selftest
+# -----------------------------------------------------------------
+
+# -----------------------------------------------------------------
+# TCL Procedures:
+# -----------------------------------------------------------------
+
+proc gen_include_files {swproj mhsinst} {
+  if {$swproj == 0} {
+    return ""
+  }
+  if {$swproj == 1} {
+    set inc_file_lines {xhwicap.h hwicap_header.h}
+    return $inc_file_lines
+  }
+}
+
+proc gen_src_files {swproj mhsinst} {
+  if {$swproj == 0} {
+    return ""
+  }
+  if {$swproj == 1} {
+    set inc_file_lines {examples/xhwicap_testapp_example.c data/hwicap_header.h}
+    return $inc_file_lines
+  }
+}
+
+proc gen_testfunc_def {swproj mhsinst} {
+  return ""
+}
+
+proc gen_init_code {swproj mhsinst} {
+  return ""
+}
+
+proc gen_testfunc_call {swproj mhsinst} {
+
+  if {$swproj == 0} {
+    return ""
+  }
+ 
+  set ipname [get_property NAME  $mhsinst] 
+  set deviceid [::hsm::utils::get_ip_param_name $mhsinst "DEVICE_ID"]
+  set stdout [get_property CONFIG.STDOUT [get_os]]
+  if { $stdout == "" || $stdout == "none" } {
+       set hasStdout 0
+  } else {
+       set hasStdout 1
+  }
+
+  set testfunc_call ""
+
+  if {${hasStdout} == 0} {
+
+      append testfunc_call "
+
+   {
+      XStatus status;
+                        
+      status = HwIcapTestAppExample(${deviceid});
+
+   }"
+  } else {
+
+      append testfunc_call "
+
+   {
+      XStatus status;
+            
+      
+      print(\"\\r\\n Running HwIcapTestAppExample() for ${ipname}...\\r\\n\");
+      
+      status = HwIcapTestAppExample(${deviceid});
+      
+      if (status == 0) {
+         print(\"HwIcapTestAppExample PASSED\\r\\n\");
+      }
+      else {
+         print(\"HwIcapTestAppExample FAILED\\r\\n\");
+      }
+   }"
+  }
+
+  return $testfunc_call
+}
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/examples/index.html b/XilinxProcessorIPLib/drivers/hwicap/examples/index.html
new file mode 100755
index 00000000..670be77f
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/examples/index.html
@@ -0,0 +1,23 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
+<html>
+<head>
+<meta http-equiv="Content-Language" content="en-us">
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<title>Driver example applications</title>
+<link rel="stylesheet" type="text/css" href="../help.css">
+</head>
+<body bgcolor="#FFFFFF">
+<h1> Example Applications for the driver hwicap_v9_0 </h1>
+<HR>
+<ul>
+  <li>xhwicap_low_level_example.c <a href="xhwicap_low_level_example.c">(source)</a> </li>
+  <li>xhwicap_testapp_example.c <a href="xhwicap_testapp_example.c">(source)</a> </li>
+  <li>xhwicap_ff.c <a href="xhwicap_ff.c">(source)</a> </li>
+  <li>xhwicap_intr_example.c <a href="xhwicap_intr_example.c">(source)</a> </li>
+  <li>xhwicap_read_config_reg.c <a href="xhwicap_read_config_reg.c">(source)</a> </li>
+  <li>xhwicap_lut.c <a href="xhwicap_lut.c">(source)</a> </li>
+  <li>xhwicap_read_frame_polled_example.c <a href="xhwicap_read_frame_polled_example.c">(source)</a> </li>
+</ul>
+<p><font face="Times New Roman" color="#800000">Copyright © 1995-2014 Xilinx, Inc. All rights reserved.</font></p>
+</body>
+</html>
\ No newline at end of file
diff --git a/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_ff.c b/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_ff.c
new file mode 100755
index 00000000..30e88d6f
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_ff.c
@@ -0,0 +1,255 @@
+/******************************************************************************
+*
+* Copyright (C) 2003 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xhwicap_ff.c
+*
+* This example demonstrates how to set and reset FF values. It sets and
+* resets the FFX in SLICE_X0Y0. Make sure this FF is not being used in
+* the design. This can be done by adding the following line in the UCF
+* file.
+*
+* CONFIG PROHIBIT = SLICE_X0Y0;
+*
+* This example assumes that there is a UART Device or STDIO Device in the
+* hardware system.
+*
+* @note
+*
+* This example should run on any or a Virtex4 device.
+*
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb  12/02/03 First release
+* 1.00a bjs  03/08/04 Updated for EDK6.2.1
+* 1.00a sv   07/18/05 Minor changes to comply to Doxygen and coding guidelines
+* 4.00a hvm  12/1/09  Updated with HAL phase 1 changes
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include <xparameters.h>
+#include <xstatus.h>
+#include <xhwicap.h>
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex 4 */
+#include <xhwicap_clb_ff.h>
+#include <xhwicap_clb_srinv.h>
+#endif
+#include <stdio.h>
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define HWICAP_DEVICEID		XPAR_HWICAP_0_DEVICE_ID
+
+
+/*
+ * Row and column to test
+ */
+#define HWICAP_EXAMPLE_TEST_COL		0
+#define HWICAP_EXAMPLE_TEST_ROW		0
+
+#define printf      xil_printf     /* A smaller footprint print */
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+int HwIcapBramFfExample(u16 DeviceId);
+
+/************************** Variable Definitions *****************************/
+
+static XHwIcap HwIcap;
+
+/*****************************************************************************/
+/**
+* Main function to call the HwIcap BRAM-FF example.
+*
+* @param	None
+*
+* @return	XST_SUCCESS if successful, XST_FAILURE if unsuccessful
+*
+* @note		None
+*
+******************************************************************************/
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex 4 */
+int main(void)
+{
+	int Status;
+
+	/*
+	 * Run the HwIcap BRAM-FF example, specify the Device ID generated in
+	 * xparameters.h
+	 */
+	Status = HwIcapBramFfExample(HWICAP_DEVICEID);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function does a test on the BRAM FF as an  example.
+*
+* @param	DeviceId is the XPAR_<HWICAP_INSTANCE>_DEVICE_ID value from
+*		xparameters.h
+*
+* @return	XST_SUCCESS if successful, otherwise XST_FAILURE
+*
+* @note		None
+*
+****************************************************************************/
+int HwIcapBramFfExample(u16 DeviceId)
+{
+	u32 SrMode=0;
+	int Status;
+	u32 Row;
+	u32 Col;
+	u32 Slice;
+	u32 Loop;
+	u32 Value;
+	u8 Contents[1];
+	XHwIcap_Config *CfgPtr;
+
+	/*
+	 * Initialize the HwIcap instance.
+	 */
+	CfgPtr = XHwIcap_LookupConfig(DeviceId);
+	if (CfgPtr == NULL) {
+		return XST_FAILURE;
+	}
+
+	Status = XHwIcap_CfgInitialize(&HwIcap, CfgPtr, CfgPtr->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Identify the FF to change: FFX in SLICE_X0Y0.
+	 */
+	Col = XHwIcap_SliceX2Col(HWICAP_EXAMPLE_TEST_COL);
+	Row = XHwIcap_SliceY2Row(&HwIcap, HWICAP_EXAMPLE_TEST_ROW);
+	Slice = XHwIcap_SliceXY2Slice(HWICAP_EXAMPLE_TEST_COL,
+						HWICAP_EXAMPLE_TEST_ROW);
+
+	printf("Setting the SRMODE -> SRHIGH. \r\n");
+	Status = XHwIcap_SetClbBits(&HwIcap, Row, Col,
+		XHI_CLB_FF.SRMODE[Slice][XHI_CLB_XQ], XHI_CLB_FF.SRHIGH, 1);
+	if (Status != XST_SUCCESS) {
+		printf("Failed to Set SRMODE->SRHIGH: %d \r\n", Status);
+		return XST_FAILURE;
+	}
+
+	printf("Setting the SRMODE -> SRLOW. \r\n");
+	Status = XHwIcap_SetClbBits(&HwIcap, Row, Col,
+	XHI_CLB_FF.SRMODE[Slice][XHI_CLB_XQ], XHI_CLB_FF.SRLOW, 1);
+	if (Status != XST_SUCCESS) {
+		printf("Failed to Set SRMODE->SRLOW: %d \r\n", Status);
+		return XST_FAILURE;
+	}
+
+
+	printf("Set SRINV to SR \r\n");
+	Status = XHwIcap_SetClbBits(&HwIcap, Row, Col,
+		 XHI_CLB_SRINV.RES[Slice], XHI_CLB_SRINV.SR, 1);
+	if (Status != XST_SUCCESS) {
+		printf("Failed to Set SRINV->SR: %d \r\n", Status);
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set it back
+	 */
+	printf("Set SRINV to SR_B \r\n");
+	Status = XHwIcap_SetClbBits(&HwIcap, Row, Col,
+		 XHI_CLB_SRINV.RES[Slice], XHI_CLB_SRINV.SR_B, 1);
+	if (Status != XST_SUCCESS) {
+		printf("Failed to Set SRINV->SR_B: %d \r\n", Status);
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Capture the FF states. If the CAPTURE block is instantiated in
+	 * the design then the XHwIcap_CommandCapture() is not necessary.
+	 */
+	printf("Capture the FF state. \r\n");
+	Status = XHwIcap_CommandCapture(&HwIcap);
+	if (Status != XST_SUCCESS) {
+		printf("Failed to capture FF states: %d \r\n", Status);
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Read the FF Contents
+	 */
+	Status = XHwIcap_GetClbBits(&HwIcap, Row, Col,
+					XHI_CLB_FF.CONTENTS[Slice][XHI_CLB_XQ],
+					Contents, 1);
+	if (Status != XST_SUCCESS) {
+		printf("Failed to Get FF Contents: %d \r\n", Status);
+		return XST_FAILURE;
+	}
+
+	/*
+	 * The readback value of the FF is inverted from its true value.
+	 */
+	Value = ~Contents[0] & 0x1;
+	printf("FF Contents: %d \r\n", Value);
+
+
+	printf("HwicapBramFFExample Passed Successfully ... \r\n\r\n");
+	return XST_SUCCESS;
+}
+#else
+#error Unsupported FPGA Family
+#endif
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_intr_example.c b/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_intr_example.c
new file mode 100755
index 00000000..856db305
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_intr_example.c
@@ -0,0 +1,434 @@
+/******************************************************************************
+*
+* Copyright (C) 2007 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xhwicap_intr_example.c
+*
+*
+* This file contains a design example using the HwIcap driver (XHwIcap) and
+* the HwIcap device using the interrupt mode.
+*
+* @note		None.
+*
+*
+* *****WARNING ************
+*
+* This is not an example that can be used directly. This example gives the
+* sequence of steps that need to be done for programming the FPGA with a given
+* configuration(partial) file. This configuration file differs from each system
+* and each version of the FPGA device.
+*
+*<pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 2.00a sv   09/29/07 First release
+* 4.00a hvm  12/1/09  Updated with HAL phase 1 changes
+* 5.00a hvm  2/25/10  Updated with S6 support
+*
+*</pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"	/* XPAR parameters */
+#include "xhwicap.h"		/* HwIcap device driver */
+#include "xintc.h"		/* Interrupt controller device driver */
+#include "xil_exception.h"      /* Exceptions */
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define HWICAP_DEVICE_ID		XPAR_HWICAP_0_DEVICE_ID
+#define INTC_DEVICE_ID			XPAR_INTC_0_DEVICE_ID
+#define HWICAP_IRPT_INTR		XPAR_INTC_0_HWICAP_0_VEC_ID
+
+/*
+ *  This is the size of the buffer in words which is written in this example.
+ */
+#define TEST_WRITE_BUFFER_SIZE		4096
+
+
+#error This is an example to show the usage of the device/driver in Interrupt \
+	mode. The user has to give a valid partial bitstream as in input to \
+	the example otherwise it may overwrite the existing configuration \
+	data in the device and result in unpredicatble behaviour
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+int HwIcapIntrExample(XIntc *IntcInstancePtr,
+			XHwIcap *HwIcapInstancePtr,
+			u16 HwIcapDeviceId,
+			u16 HwIcapIntrId);
+
+void HwIcapIntrHandler(void *CallBackRef, u32 StatusEvent, u32 WordCount);
+
+static int HwIcapSetupInterruptSystem(XIntc* IntcInstancePtr,
+				      XHwIcap *HwIcapPtr,
+				      u16 IntrId );
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * The instances to support the device drivers are global such that the
+ * are initialized to zero each time the program runs.
+ */
+static XIntc IntcInstance;	/* The instance of the Interrupt Controller */
+static XHwIcap  HwIcapInstance;	/* The instance of the HwIcap device */
+
+/*
+ * The following variables are shared between non-interrupt processing and
+ * interrupt processing such that they must be global.
+ */
+volatile int TransferInProgress;
+
+/*
+ * The following variable tracks any errors that occur during interrupt
+ * processing
+ */
+int Error;
+
+/*
+ * The following variables are used to read and write to the  HwIcap device, they
+ * are global to avoid having large buffers on the stack.
+ */
+u32 WriteBuffer[TEST_WRITE_BUFFER_SIZE];
+
+
+/*****************************************************************************/
+/**
+*
+* Main function to call the HwIcap interrupt example.
+*
+* @param    None
+*
+* @return   XST_SUCCESS if successful, otherwise XST_FAILURE.
+*
+* @note     None
+*
+******************************************************************************/
+int main(void)
+{
+	int Status;
+
+	/*
+	 * Run the HwIcap Interrupt example.
+	 */
+	Status = HwIcapIntrExample(&IntcInstance, &HwIcapInstance,
+			    HWICAP_DEVICE_ID,
+			    HWICAP_IRPT_INTR);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function does a minimal test on the HwIcap device and driver as a
+* design example. The purpose of this function is to illustrate how to use
+* the XHwIcap component using the interrupt mode.
+*
+* This function sends data and expects to receive the same data.
+*
+*
+* @param	IntcInstancePtr is a pointer to the instance of the INTC component.
+* @param	HwIcapInstancePtr is a pointer to the instance of HwIcap component.
+* @param	HwIcapDeviceId is the Device ID of the HwIcap Device and is the
+*		XPAR_<HWICAP_instance>_DEVICE_ID value from xparameters.h.
+* @param	HwIcapIntrId is the interrupt Id and is typically
+*		XPAR_<INTC_instance>_<HWICAP_instance>_IP2INTC_IRPT_INTR
+*		value from xparameters.h .
+*
+* @return	XST_SUCCESS if successful, otherwise XST_FAILURE.
+*
+* @note
+*
+* This function contains an infinite loop such that if interrupts are not
+* working it may never return.
+*
+******************************************************************************/
+int HwIcapIntrExample(XIntc *IntcInstancePtr, XHwIcap *HwIcapInstancePtr,
+			u16 HwIcapDeviceId, u16 HwIcapIntrId)
+{
+	int Status;
+	u32 Count;
+	u8 Test;
+	XHwIcap_Config *ConfigPtr;
+
+	/*
+	 * Initialize the HwIcap driver.
+	 */
+	ConfigPtr = XHwIcap_LookupConfig(HwIcapDeviceId);
+	if (ConfigPtr == NULL) {
+		return XST_FAILURE;
+	}
+	Status = XHwIcap_CfgInitialize(HwIcapInstancePtr,
+					ConfigPtr,
+					ConfigPtr->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Perform a self-test to ensure that the hardware was built correctly.
+	 */
+	Status = XHwIcap_SelfTest(HwIcapInstancePtr);
+
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Connect the HwIcap device to the interrupt subsystem such that
+	 * interrupts can occur. This function is application specific.
+	 */
+	Status = HwIcapSetupInterruptSystem(IntcInstancePtr,
+					HwIcapInstancePtr,
+					HwIcapIntrId);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Setup the handler for the HwIcap that will be called from the
+	 * interrupt context when an HwIcap status occurs, specify a pointer
+	 * to the HwIcap driver instance as the callback reference so the
+	 * handler is able to access the instance data.
+	 */
+	XHwIcap_SetInterruptHandler(HwIcapInstancePtr, HwIcapInstancePtr,
+			 (XHwIcap_StatusHandler)HwIcapIntrHandler);
+
+
+
+	/*
+	 * Initialize the write buffer with pattern to write.
+	 */
+	for (Count = 0; Count < TEST_WRITE_BUFFER_SIZE;) {
+
+		WriteBuffer[Count++] = XHI_DUMMY_PACKET;
+	#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+		WriteBuffer[Count++] = XHI_SYNC_PACKET1;
+		WriteBuffer[Count++] = XHI_SYNC_PACKET2;
+	#else
+		WriteBuffer[Count++] = XHI_SYNC_PACKET;
+	#endif
+		WriteBuffer[Count++] = XHwIcap_Type1Read(XHI_IDCODE) | 1;
+		WriteBuffer[Count++] = XHI_NOOP_PACKET;
+		WriteBuffer[Count++] = XHI_NOOP_PACKET;
+
+		WriteBuffer[Count++] = XHI_DUMMY_PACKET;
+	#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+		WriteBuffer[Count++] = XHI_SYNC_PACKET1;
+		WriteBuffer[Count++] = XHI_SYNC_PACKET2;
+		WriteBuffer[Count++] = XHwIcap_Type1Read(XHI_COR1) | 1;
+	#else
+		WriteBuffer[Count++] = XHI_SYNC_PACKET;
+		WriteBuffer[Count++] = XHwIcap_Type1Read(XHI_COR) | 1;
+	#endif
+		WriteBuffer[Count++] = XHI_NOOP_PACKET;
+		WriteBuffer[Count++] = XHI_NOOP_PACKET;
+	}
+
+	/*
+	 * Enable the Write FIFO Half Full Interrupt.
+	 */
+	XHwIcap_IntrEnable(HwIcapInstancePtr, XHI_IPIXR_WRP_MASK);
+
+	/*
+	 * Write the the data to the device.
+	 */
+	TransferInProgress = TRUE;
+	#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+	Status = XHwIcap_DeviceWrite(HwIcapInstancePtr,
+					(u16 *) &WriteBuffer[0],
+					TEST_WRITE_BUFFER_SIZE);
+	#else
+	Status = XHwIcap_DeviceWrite(HwIcapInstancePtr,
+					(u32 *) &WriteBuffer[0],
+					TEST_WRITE_BUFFER_SIZE);
+
+	#endif
+	if (Status != XST_SUCCESS)  {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Wait for the data to be written to the device.
+	 */
+	while (TransferInProgress);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is the handler which performs processing for the HwIcap driver.
+* It is called from an interrupt context such that the amount of processing
+* performed should be minimized. It is called when a transfer of HwIcap data
+* completes or an error occurs.
+*
+* This handler provides an example of how to handle HwIcap interrupts and
+* is application specific.
+*
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	StatusEvent is the event that just occurred.
+* @param	WordCount is the number of words (32 bit) transferred up until
+*		the event occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void HwIcapIntrHandler(void *CallBackRef, u32 StatusEvent, u32 ByteCount)
+{
+	/*
+	 * Indicate the transfer between the HwIcap to the Icap device is done
+	 * regardless of the status event.
+	 */
+	TransferInProgress = FALSE;
+
+	/*
+	 * If the event was not transfer done, then track it as an error.
+	 */
+	if (StatusEvent != XST_HWICAP_WRITE_DONE) {
+		Error++;
+	}
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets up the interrupt system so interrupts can occur for the
+* HwIcap device.  The function is application-specific since the actual
+* system may or may not have an interrupt controller. The HwIcap device
+* could be directly connected to a processor without an interrupt controller.
+* The user should modify this function to fit the application.
+*
+* @param	IntcInstancePtr is a pointer to the Interrupt Controller
+*		driver Instance
+* @param	HwIcapPtr is a pointer to the driver instance for the System
+* 		Monitor device which is going to be connected to the interrupt
+*		controller
+* @param	DeviceId is the XPAR_<HWICAP_INSTANCE>_DEVICE_ID value from
+*		xparameters.h
+*
+* @return	XST_SUCCESS if successful, or XST_FAILURE.
+*
+* @note		None.
+*
+*
+****************************************************************************/
+static int HwIcapSetupInterruptSystem(XIntc* IntcInstancePtr,
+				      XHwIcap *HwIcapPtr,
+				      u16 IntrId )
+{
+	int Status;
+
+	/*
+	 * Initialize the interrupt controller driver so that it's ready to use.
+	 */
+	Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Connect the handler that will be called when an interrupt
+	 * for the device occurs, the handler defined above performs the
+	 * specific interrupt processing for the device.
+	 */
+	Status = XIntc_Connect(IntcInstancePtr,
+		 		IntrId,
+				(XInterruptHandler) XHwIcap_IntrHandler,
+				HwIcapPtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Start the interrupt controller so interrupts are enabled for all
+	 * devices that cause interrupts. Specify real mode so that the
+	 * HwIcap device can cause interrupts through the interrupt
+	 * controller.
+	 */
+	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Enable the interrupt for the HwIcap device.
+	 */
+	XIntc_Enable(IntcInstancePtr, IntrId);
+
+	/*
+	 * Initialize the exception table.
+	 */
+	Xil_ExceptionInit();
+
+	/*
+	 * Register the interrupt controller handler with the exception table.
+	 */
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+				(Xil_ExceptionHandler) XIntc_InterruptHandler,
+				IntcInstancePtr);
+
+	/*
+	 * Enable non-critical exceptions.
+	 */
+	Xil_ExceptionEnable();
+
+	return XST_SUCCESS;
+}
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_low_level_example.c b/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_low_level_example.c
new file mode 100755
index 00000000..e147c949
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_low_level_example.c
@@ -0,0 +1,298 @@
+/******************************************************************************
+*
+* Copyright (C) 2003 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+*
+* @file xhwicap_low_level_example.c
+*
+* Contains a design example of how to use the low-level macros and functions
+* of the XHwIcap driver.
+*
+* This example reads back the value stored in the IDCODE register.
+*
+* This example assumes that there is a UART Device or STDIO Device in the
+* hardware system.
+*
+*
+* @note
+*
+* This example should run on a Virtex4 or a Virtex5 or Virtex6 or
+* a Spartan6 or a Kintex 7 device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb  11/21/03 First release
+* 1.00a sv   07/18/05 Minor changes to comply to Doxygen and coding guidelines
+* 1.01a sv   04/10/07 Changes to support V4
+* 2.00a sv   10/10/07 Changes to support V5
+* 4.00a hvm  11/20/09 Added support for V6 and updated with HAL phase 1
+*		      modifications
+* 5.00a hvm  02/08/10 Added support for S6
+* 5.00a hvm  04/28/10 Added Check for the control bit clearance in the CR
+*			register for regsiter read and write operations.
+* 5.00a hvm  05/04/10 Updated the example to read Id twice so as to igonore
+*			the first read.
+* 5.00a hvm  05/21/10 Updated the ID sequence to be consistent across V4/V5/V6
+*			devices. Added an extra NOP before Type1 Read device ID
+*			and removed  extra NOP after the device ID. This
+*			change removed the need of reading ID twice.
+*			Removed the extra read ID.
+* 5.01a hvm  07/29/10 Code to check whether read/write bit in control register
+*			is cleared after the initiation of respective transfer
+*			is added for all devices. This check was earlier done
+*			only for S6 devices
+* 6.00a hvm  08/05/11 Added support for K7 family
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include <xparameters.h>
+#include <xstatus.h>
+#include <xil_types.h>
+#include <xil_assert.h>
+#include <xhwicap_i.h>
+#include <xhwicap_l.h>
+#include <stdio.h>
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define HWICAP_BASEADDR         XPAR_HWICAP_0_BASEADDR
+
+/*
+ * Number of words to Read for getting Id code.
+ */
+#if XHI_FAMILY == XHI_DEV_FAMILY_S6
+#define HWICAP_IDCODE_SIZE		    2
+#else
+#define HWICAP_IDCODE_SIZE		    1
+#endif
+
+/*
+ * Bitstream that reads back ID Code Register
+ */
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) ||(XHI_FAMILY == XHI_DEV_FAMILY_V5) \
+|| (XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+
+#define HWICAP_EXAMPLE_BITSTREAM_LENGTH     6
+
+static u32 ReadId[HWICAP_EXAMPLE_BITSTREAM_LENGTH] =
+{
+	XHI_DUMMY_PACKET, /* Dummy Word */
+	XHI_SYNC_PACKET, /* Sync Word*/
+	XHI_NOOP_PACKET, /* Type 1 NO OP */
+	XHI_NOOP_PACKET, /* Type 1 NO OP */
+	XHI_DEVICE_ID_READ, /* Read Product ID Code Register */
+	XHI_NOOP_PACKET, /* Type 1 NO OP */
+};
+#elif XHI_FAMILY == XHI_DEV_FAMILY_S6/* Spartan 6*/
+
+#define HWICAP_EXAMPLE_BITSTREAM_LENGTH     7
+
+static u32 ReadId[HWICAP_EXAMPLE_BITSTREAM_LENGTH] =
+{
+	XHI_DUMMY_PACKET, /* Dummy Word */
+	XHI_SYNC_PACKET1, /* Sync Word*/
+	XHI_SYNC_PACKET2, /* Sync Word*/
+	XHI_NOOP_PACKET, /* Type 1 NO OP */
+	XHI_NOOP_PACKET, /* Type 1 NO OP */
+	XHI_DEVICE_ID_READ, /* Read Product ID Code Register */
+	XHI_NOOP_PACKET, /* Type 1 NO OP */
+ };
+#else
+
+#error Unsupported Family of FPGAs
+
+#endif
+
+#define printf  xil_printf           /* A smaller footprint printf */
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+u32 HwIcapLowLevelExample(u32 BaseAddress, u32 *IdCode);
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+* Main function to call the HWICAP Low Level example.
+*
+* @param    None
+*
+* @return   XST_SUCCESS if successful, otherwise XST_FAILURE
+*
+* @note     None
+*
+******************************************************************************/
+int main(void)
+{
+	int Status;
+	u32 IdCode;
+
+	/*
+	 * Run the HwIcap Low Level example, specify the Base Address
+	 * generated in xparameters.h.
+	 */
+	Status = HwIcapLowLevelExample(HWICAP_BASEADDR, &IdCode);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	printf("The IDCODE is %x \r\n", IdCode);
+	printf("\r\nHwIcapLowLevelExample Passed Successfully. \r\n\r\n");
+
+	return XST_SUCCESS;
+
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function returns the IDCODE of the target device.
+*
+* @param	BaseAddress is the base address of the HwIcap instance.
+* @param	IdCode is the IDCODE of the part this code is running on.
+*
+* @return	XST_SUCCESS if successful, otherwise XST_FAILURE
+*
+* @note		None
+*
+******************************************************************************/
+u32 HwIcapLowLevelExample(u32 BaseAddress, u32 *IdCode)
+{
+
+	u32 Index;
+	u32 Retries;
+
+	/*
+	 * Write command sequence to the FIFO
+	 */
+	for (Index = 0; Index < HWICAP_EXAMPLE_BITSTREAM_LENGTH; Index++) {
+		XHwIcap_WriteReg(BaseAddress, XHI_WF_OFFSET, ReadId[Index]);
+	}
+
+	/*
+	 * Start the transfer of the data from the FIFO to the ICAP device.
+	 */
+	XHwIcap_WriteReg(BaseAddress, XHI_CR_OFFSET, XHI_CR_WRITE_MASK);
+
+	/*
+	 * Poll for done, which indicates end of transfer
+	 */
+	Retries = 0;
+	while ((XHwIcap_ReadReg(BaseAddress, XHI_SR_OFFSET) &
+			XHI_SR_DONE_MASK) != XHI_SR_DONE_MASK) {
+		Retries++;
+		if (Retries > XHI_MAX_RETRIES) {
+
+			/*
+			 * Waited to long. Exit with error.
+			 */
+			printf("\r\nHwIcapLowLevelExample failed- retries  \
+			failure. \r\n\r\n");
+
+			return XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Wait till the Write bit is cleared in the CR register.
+	 */
+	while ((XHwIcap_ReadReg(BaseAddress, XHI_CR_OFFSET)) &
+					XHI_CR_WRITE_MASK);
+	/*
+	 * Write to the SIZE register. We want to readback one word.
+	 */
+	XHwIcap_WriteReg(BaseAddress, XHI_SZ_OFFSET, HWICAP_IDCODE_SIZE);
+
+
+	/*
+	 * Start the transfer of the data from ICAP to the FIFO.
+	 */
+	XHwIcap_WriteReg(BaseAddress, XHI_CR_OFFSET, XHI_CR_READ_MASK);
+
+	/*
+	 * Poll for done, which indicates end of transfer
+	 */
+	Retries = 0;
+	while ((XHwIcap_ReadReg(BaseAddress, XHI_SR_OFFSET) &
+			XHI_SR_DONE_MASK) != XHI_SR_DONE_MASK) {
+		Retries++;
+		if (Retries > XHI_MAX_RETRIES) {
+
+			/*
+			 * Waited to long. Exit with error.
+			 */
+
+			return XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Wait till the Read bit is cleared in the CR register.
+	 */
+	while ((XHwIcap_ReadReg(BaseAddress, XHI_CR_OFFSET)) &
+					XHI_CR_READ_MASK);
+	/*
+	 * Return the IDCODE value
+	 */
+	*IdCode =  XHwIcap_ReadReg(BaseAddress, XHI_RF_OFFSET);
+
+#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+
+	*IdCode =  (*IdCode << 16 | (XHwIcap_ReadReg(BaseAddress,
+					XHI_RF_OFFSET)));
+#endif
+
+	return XST_SUCCESS;
+}
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_lut.c b/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_lut.c
new file mode 100755
index 00000000..8c427de6
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_lut.c
@@ -0,0 +1,276 @@
+/******************************************************************************
+*
+* Copyright (C) 2003 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xhwicap_lut.c
+*
+* This example tests some of the values in a LUT. This example requires the
+* use of a LUT not in use. One can reserve a LUT in the UCF file with the
+* constraint: CONFIG PROHIBIT = SLICE_X0Y0
+*
+*
+* @note
+*
+* This example should run on any Virtex4 or a Virtex5 or a Virtex6 device.
+*
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ------------------------------------------------------
+* 1.00a bjb  10/30/03 Original version
+* 1.00a bjs  01/01/04 First release
+* 1.00a bjs  03/08/04 Updated for EDK 6.2.1
+* 1.00a sv   07/18/05 Minor changes to comply to Doxygen and coding guidelines
+* 2.00a ecm  10/04/07 Changes to support FIFO mode and V5
+* 4.00a hvm  11/30/09 Added support for V6
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include <xparameters.h>
+#include <xhwicap.h>
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5 ) ||\
+	(XHI_FAMILY == XHI_DEV_FAMILY_V6))
+#include <xhwicap_clb_lut.h>
+#endif
+#include <stdio.h>
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define HWICAP_DEVICEID		XPAR_HWICAP_0_DEVICE_ID
+
+
+/*
+ * This is the LUT that is  tested . This LUT must not be used by the design.
+ * This can be done in the system.ucf file by putting the following statements:
+ *
+ * CONFIG PROHIBIT = SLICE_X[COL]Y[ROW];
+ *
+ * If you wish to reserve the entire column then put the following statement in
+ * the ucf file:
+ *
+ * CONFIG PROHIBIT = SLICE_X[COL]Y*;
+ *
+ */
+#define TEST_COL	0	/* Test Column for LUT */
+#define TEST_ROW	0	/* Test Row for LUT    */
+
+
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4
+#define TEST_LUT	XHI_CLB_LUT_F	/* Test LUT */
+#define LUT_SIZE	16	/* The number of bits in a LUT */
+#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6))
+#define TEST_LUT	XHI_CLB_LUT_A	/* Test LUT */
+#define LUT_SIZE	64	/* The number of bits in a LUT */
+#endif
+
+
+
+
+#define MAX_TEST_COUNT	0xFF
+
+#define printf		xil_printf      /* A smaller footprint printf */
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+int HwIcapLutExample(u16 DeviceId);
+
+
+/************************** Variable Definitions *****************************/
+
+static XHwIcap HwIcap;
+
+u8 LutWriteBuffer[LUT_SIZE];	/* Value written to the LUT     */
+u8 LutReadBuffer[LUT_SIZE];	/* Value read back from the LUT */
+
+
+/*****************************************************************************/
+/**
+*
+* Main function to call the HwIcap LUT example.
+*
+* @param    None
+*
+* @return   XST_SUCCESS if successful, otherwise XST_FAILURE.
+*
+* @note     None
+*
+******************************************************************************/
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5 ) ||\
+	(XHI_FAMILY == XHI_DEV_FAMILY_V6))
+int main(void)
+{
+	int Status;
+
+	/*
+	 * Run the HwIcap LUT example, specify the Device ID generated in
+	 * xparameters.h
+	 */
+	Status = HwIcapLutExample(HWICAP_DEVICEID);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function does a test on the LUT as an  example.
+*
+* @param	DeviceId is the XPAR_<HWICAP_INSTANCE>_DEVICE_ID value from
+*		xparameters.h
+*
+*
+* @return	XST_SUCCESS if successful, otherwise XST_FAILURE
+*
+* @note		None.
+*
+******************************************************************************/
+int HwIcapLutExample(u16 DeviceId)
+{
+	XHwIcap_Config *CfgPtr; /* Pointer to HwIcap Config */
+	u32 Count;		/* Current value to test */
+	int Status;		/* Return value          */
+	u32 Index;		/* Counter               */
+	u32 RowNum;		/* CLB Row location      */
+	u32 ColNum;		/* CLB Column location   */
+	u32 Slice;		/* CLB Slice location    */
+
+	printf("\r\n Starting HwIcapLutExample. \r\n");
+	/*
+	 * Initialize the HwIcap instance.
+	 */
+	CfgPtr = XHwIcap_LookupConfig(DeviceId);
+	if (CfgPtr == NULL) {
+		return XST_FAILURE;
+	}
+
+	Status = XHwIcap_CfgInitialize(&HwIcap, CfgPtr, CfgPtr->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Perform a self-test to ensure that the hardware was built correctly.
+	 */
+	Status = XHwIcap_SelfTest(&HwIcap);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Identify the LUT to change: LUT in SLICE_X0Y0.
+	 */
+	ColNum = XHwIcap_SliceX2Col(TEST_COL);
+	RowNum = XHwIcap_SliceY2Row(&HwIcap, TEST_ROW);
+	Slice  = XHwIcap_SliceXY2Slice(TEST_COL, TEST_ROW);
+
+	/*
+	 * Loop through all possible LUT Values
+	 */
+	for (Count = 0; Count < MAX_TEST_COUNT; Count++) {
+
+		/*
+		 * Set the LUT array to be assigned
+		 */
+		for (Index = 0; Index < LUT_SIZE; Index++) {
+			LutWriteBuffer[Index] = (Count >> Index) & 0x01;
+			LutReadBuffer[Index] = 0;
+		}
+
+		/*
+		 * Set LUT
+		 */
+		Status = XHwIcap_SetClbBits(&HwIcap, RowNum, ColNum,
+			 		XHI_CLB_LUT.CONTENTS[Slice][TEST_LUT],
+			 		LutWriteBuffer, LUT_SIZE);
+		if (Status != XST_SUCCESS) {
+			return XST_FAILURE;
+		}
+
+		/*
+		 * Read back LUT value
+		 */
+		Status = XHwIcap_GetClbBits(&HwIcap, RowNum, ColNum,
+					XHI_CLB_LUT.CONTENTS[Slice][TEST_LUT],
+					LutReadBuffer, LUT_SIZE);
+		if (Status != XST_SUCCESS) {
+			return XST_FAILURE;
+		}
+
+		/*
+		 * Compare the written and read values
+		 */
+		for (Index = 0; Index < LUT_SIZE; Index++) {
+			if (LutWriteBuffer[Index] != LutReadBuffer[Index]) {
+			printf("\r\n HwIcapLutExample Failed. Cnt = %d , Index = %d WrBuf = %d RdBuf= %d\
+					\r\n", Count, Index, LutWriteBuffer[Index], LutReadBuffer[Index] );
+			return XST_FAILURE;
+			}
+		}
+
+
+	}
+
+	printf("\r\n HwIcapLutExample Passed Successfully.\r\n");
+	return XST_SUCCESS;
+}
+#else
+#error Unsupported FPGA Family
+#endif
+
+
+
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_read_config_reg.c b/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_read_config_reg.c
new file mode 100755
index 00000000..0dc41e64
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_read_config_reg.c
@@ -0,0 +1,353 @@
+/******************************************************************************
+*
+* Copyright (C) 2003 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xhwicap_read_config_reg.c
+*
+* This file contains a design example using the HwIcap driver and hardware
+* device.
+*
+* This example prints out the values of all the configuration registers in the
+* FPGA.
+*
+* This example assumes that there is a UART Device or STDIO Device in the
+* hardware system.
+*
+* @note
+*
+* This example can been run on any Virtex4 or Virtex5 or Virtex6 or a
+* Spartan6 or a 7 series device or a Zynq device.
+*
+* In a Zynq device the ICAP needs to be selected using the
+* XDcfg_SelectIcapInterface API of the DevCfg driver (clear the PCAP_PR bit of
+* Control register in the Device Config Interface)  before it can be
+* accessed using the HwIcap.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a bjb  11/21/03 First release
+* 1.00a sv   07/18/05 Minor changes to comply to Doxygen and coding guidelines
+* 1.01a sv   04/10/07 Changes to support V4
+* 4.00a hvm  11/30/09 Added support for V6 and updated with HAL phase 1
+*		      modifications
+* 5.00a hvm  04/28/10 Added support for S6 support.
+* 6.00a hvm  08/05/11 Added support for K7 family
+* 8.01a bss  05/14/12 Replaced the define XHI_C0R_1 with XHI_COR_1 for CR718042
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include <xparameters.h>
+#include <xil_types.h>
+#include <xil_assert.h>
+#include <xhwicap.h>
+#include <stdio.h>
+
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define HWICAP_DEVICEID         XPAR_HWICAP_0_DEVICE_ID
+
+
+#define printf   xil_printf          /* A smaller footprint printf */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+int HwIcapReadConfigRegExample(u16 DeviceId);
+
+/************************** Variable Definitions *****************************/
+
+static XHwIcap HwIcap;
+
+/*****************************************************************************/
+/**
+*
+* Main function to call the HWICAP example.
+*
+* @param	None
+*
+* @return	XST_SUCCESS if successful, XST_FAILURE if unsuccessful
+*
+* @note		None
+*
+******************************************************************************/
+int main(void)
+{
+	int Status;
+
+	/*
+	 * Run the HwIcap example, specify the Device Id generated in
+	 * xparameters.h.
+	 */
+	Status = HwIcapReadConfigRegExample(HWICAP_DEVICEID);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function reads the configuration  registers inside the FPGA.
+*
+* @param	DeviceId is the XPAR_<HWICAP_INSTANCE>_DEVICE_ID value from
+*		xparameters.h.
+*
+* @return	XST_SUCCESS if successful, otherwise XST_FAILURE.
+*
+* @note		None.
+*
+******************************************************************************/
+int HwIcapReadConfigRegExample(u16 DeviceId)
+{
+	int Status;
+	XHwIcap_Config *CfgPtr;
+	u32 ConfigRegData;
+
+	/*
+	 * Initialize the HwIcap instance.
+	 */
+	CfgPtr = XHwIcap_LookupConfig(DeviceId);
+	if (CfgPtr == NULL) {
+		return XST_FAILURE;
+	}
+
+	Status = XHwIcap_CfgInitialize(&HwIcap, CfgPtr, CfgPtr->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Run the Self test.
+	 */
+	Status = XHwIcap_SelfTest(&HwIcap);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	printf("Value of the Configuration Registers. \r\n\r\n");
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_CRC, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" CRC -> \t %x \t\r\n", ConfigRegData);
+	}
+
+#if (XHI_FAMILY != XHI_DEV_FAMILY_S6)
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_FAR, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" FAR -> \t %x \t\r\n", ConfigRegData);
+	}
+#else
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_FAR_MIN, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" FAR_MIN -> \t %x \t\r\n", ConfigRegData);
+	}
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_FAR_MAJ, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" FAR_MAJ -> \t %x \t\r\n", ConfigRegData);
+	}
+#endif
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_FDRI, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" FDRI -> \t %x \t\r\n", ConfigRegData);
+	}
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_FDRO, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" FDRO -> \t %x \t\r\n", ConfigRegData);
+	}
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_CMD, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" CMD -> \t %x \t\r\n", ConfigRegData);
+	}
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_CTL, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" CTL -> \t %x \t\r\n", ConfigRegData);
+	}
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_MASK, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" MASK -> \t %x \t\r\n", ConfigRegData);
+	}
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_STAT, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" STAT -> \t %x \t\r\n", ConfigRegData);
+	}
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_LOUT, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" LOUT -> \t %x \t\r\n", ConfigRegData);
+	}
+
+#if (XHI_FAMILY != XHI_DEV_FAMILY_S6)
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_COR, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" COR -> \t %x \t\r\n", ConfigRegData);
+	}
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_MFWR, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" MFWR -> \t %x \t\r\n", ConfigRegData);
+	}
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_CBC, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" CBC -> \t %x \t\r\n", ConfigRegData);
+	}
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_AXSS, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" AXSS -> \t %x \t\r\n", ConfigRegData);
+	}
+
+#else
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_COR1, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" COR1 -> \t %x \t\r\n", ConfigRegData);
+	}
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_COR2, &ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" COR2 -> \t %x \t\r\n", ConfigRegData);
+	}
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_PWRDN_REG,
+		(u32 *)&ConfigRegData) == XST_SUCCESS) {
+		printf(" PWRDN_REG -> \t %x \t\r\n", ConfigRegData);
+	}
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_FLR, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" FLR -> \t %x \t\r\n", ConfigRegData);
+	}
+
+#endif
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_IDCODE, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" IDCODE -> \t %x \t\r\n", ConfigRegData);
+	}
+
+
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) \
+	|| (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_COR_1, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" COR_1 -> \t %x \t\r\n", ConfigRegData);
+	}
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_CSOB, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" CSOB -> \t %x \t\r\n", ConfigRegData);
+	}
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_WBSTAR, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" WBSTAR -> \t %x \t\r\n", ConfigRegData);
+	}
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_TIMER, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" TIMER -> \t %x \t\r\n", ConfigRegData);
+	}
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_BOOTSTS, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" BOOTSTS -> \t %x \t\r\n", ConfigRegData);
+	}
+
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_CTL_1, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" CTL_1 -> \t %x \t\r\n", ConfigRegData);
+	}
+
+#endif
+#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_CWDT, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" CWDT -> \t %x \t\r\n", ConfigRegData);
+	}
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_HC_OPT_REG,
+		(u32 *)&ConfigRegData) == XST_SUCCESS) {
+		printf(" HC_OPT_REG -> \t %x \t\r\n", ConfigRegData);
+	}
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_MODE_REG,
+		(u32 *)&ConfigRegData) == XST_SUCCESS) {
+		printf(" MODE_REG -> \t %x \t\r\n", ConfigRegData);
+	}
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_SEU_OPT, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" SEU_OPT -> \t %x \t\r\n", ConfigRegData);
+	}
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_EXP_SIGN,
+		(u32 *)&ConfigRegData) == XST_SUCCESS) {
+		printf(" EXP_SIGN -> \t %x \t\r\n", ConfigRegData);
+	}
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_RDBK_SIGN,
+		(u32 *)&ConfigRegData) == XST_SUCCESS) {
+		printf(" RDBK_SIGN -> \t %x \t\r\n", ConfigRegData);
+	}
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_BOOTSTS, (u32 *)&ConfigRegData) ==
+		XST_SUCCESS) {
+		printf(" BOOTSTS -> \t %x \t\r\n", ConfigRegData);
+	}
+	if (XHwIcap_GetConfigReg(&HwIcap, XHI_EYE_MASK,
+		(u32 *)&ConfigRegData) == XST_SUCCESS) {
+		printf(" EYE_MASK -> \t %x \t\r\n", ConfigRegData);
+	}
+
+#endif
+
+	printf("\r\n HwIcapReadConfigRegExample Passed Successfully.\r\n\r\n");
+
+	return XST_SUCCESS;
+}
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_read_frame_polled_example.c b/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_read_frame_polled_example.c
new file mode 100755
index 00000000..c5071d88
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_read_frame_polled_example.c
@@ -0,0 +1,235 @@
+/******************************************************************************
+*
+* Copyright (C) 2003 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xhwicap_read_frame_polled_example.c
+*
+* The is example shows how to use the XHwIcap_DeviceReadFrame() to read a
+* frame of data. This example simply reads one frame from the device using
+* the polled mode.
+*
+* This example assumes that there is a UART Device or STDIO Device in the
+* hardware system.
+*
+* @note
+*
+* This example should run on any Virtex4 or Virtex5 or Virtex6 or
+* Spartan6 or Kintex 7 device.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb  11/21/03 First release
+* 1.00a sv   07/18/05 Minor changes to comply to Doxygen and coding guidelines
+* 1.01a sv   04/10/07 Changes to support V4
+* 2.00a sv   10/04/07 Changes to support FIFO mode
+* 4.00a hvm  11/20/09 Updated to support V6
+* 5.00a hvm  2/20/10  Updated to support S6.
+* 6.00a hvm  08/05/11 Added support for K7 family
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include <xparameters.h>
+#include <xil_types.h>
+#include <xil_assert.h>
+#include <xhwicap.h>
+#include <stdio.h>
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define HWICAP_DEVICEID		XPAR_HWICAP_0_DEVICE_ID
+
+#define HWICAP_EXAMPLE_BLOCK		0
+
+/*
+ * These are the parameters for reading a frame of data in
+ * the slice SLICE_X0Y0
+ */
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5 ) ||\
+	(XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+#define HWICAP_EXAMPLE_TOP		0
+#define HWICAP_EXAMPLE_HCLK		5
+#define HWICAP_EXAMPLE_MAJOR		5
+#define HWICAP_EXAMPLE_MINOR		10
+
+#elif (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+
+#define HWICAP_EXAMPLE_ROW		5
+#define HWICAP_EXAMPLE_MAJOR		2
+#define HWICAP_EXAMPLE_MINOR		20
+
+#endif
+
+#define printf  xil_printf	/* A smaller footprint printf */
+
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+int HwIcapReadFramePolledExample(u16 DeviceId);
+
+/************************** Variable Definitions *****************************/
+
+static XHwIcap HwIcap;
+
+/*****************************************************************************/
+/**
+*
+* Main function to call the HwIcap Frame example.
+*
+* @param	None
+*
+* @return	XST_SUCCESS if successful, XST_FAILURE if unsuccessful
+*
+* @note		None
+*
+******************************************************************************/
+int main(void)
+{
+	int Status;
+
+	/*
+	 * Run the HwIcap example, specify the Device ID generated in
+	 * xparameters.h
+	 */
+	Status = HwIcapReadFramePolledExample(HWICAP_DEVICEID);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function reads a frame from the device as an example using polled mode.
+*
+* @param	DeviceId is the XPAR_<HWICAP_INSTANCE>_DEVICE_ID value from
+*		xparameters.h
+*
+* @return	XST_SUCCESS if successful, otherwise XST_FAILURE
+*
+* @note		None
+*
+****************************************************************************/
+int HwIcapReadFramePolledExample(u16 DeviceId)
+{
+	int Status;
+	u32 Index;
+	XHwIcap_Config *CfgPtr;
+#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+	u16  FrameData[XHI_NUM_WORDS_FRAME_INCL_NULL_FRAME];
+#else
+	u32  FrameData[XHI_NUM_WORDS_FRAME_INCL_NULL_FRAME];
+#endif
+	/*
+	 * Initialize the HwIcap instance.
+	 */
+	CfgPtr = XHwIcap_LookupConfig(DeviceId);
+	if (CfgPtr == NULL) {
+		return XST_FAILURE;
+	}
+
+	Status = XHwIcap_CfgInitialize(&HwIcap, CfgPtr, CfgPtr->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Perform a self-test to ensure that the hardware was built correctly.
+	 */
+	Status = XHwIcap_SelfTest(&HwIcap);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5 ) ||\
+	(XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+	/*
+	 * Read the Frame
+	 */
+	Status = XHwIcap_DeviceReadFrame(&HwIcap,
+					 HWICAP_EXAMPLE_TOP,
+					 HWICAP_EXAMPLE_BLOCK,
+					 HWICAP_EXAMPLE_HCLK,
+					 HWICAP_EXAMPLE_MAJOR,
+					 HWICAP_EXAMPLE_MINOR,
+					 (u32 *) &FrameData[0]);
+
+#elif (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+	Status = XHwIcap_DeviceReadFrame(&HwIcap,
+					 HWICAP_EXAMPLE_BLOCK,
+					 HWICAP_EXAMPLE_ROW,
+					 HWICAP_EXAMPLE_MAJOR,
+					 HWICAP_EXAMPLE_MINOR,
+					 (u16 *) &FrameData[0]);
+
+#endif
+
+	if (Status != XST_SUCCESS) {
+		printf("Failed to Read Frame: %d \r\n", Status);
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Print Frame contents
+	 */
+	for (Index = XHI_NUM_FRAME_WORDS;
+		Index < (XHI_NUM_FRAME_WORDS << 1) ; Index++) {
+
+		printf("Frame Word %d -> \t %x \r\n",
+			(Index - XHI_NUM_FRAME_WORDS) , FrameData[Index]);
+	}
+
+	printf("\r\nHwIcapReadFramePolledExample Passed Successfully.\r\n\r\n");
+	return  XST_SUCCESS;
+}
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_testapp_example.c b/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_testapp_example.c
new file mode 100755
index 00000000..1cea971d
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/examples/xhwicap_testapp_example.c
@@ -0,0 +1,178 @@
+/******************************************************************************
+*
+* Copyright (C) 2007 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xhwicap_testapp_example.c
+*
+* This file contains a design example using the HwIcap device driver and
+* hardware device.
+*
+* @note
+*
+* This example should run on a Virtex4 or a Virtex5 or a Virtex6 or a
+* Spartan6 or a 7 series device or a Zynq device.
+*
+* In a Zynq device the ICAP needs to be selected using the
+* XDcfg_SelectIcapInterface API of the DevCfg driver (clear the PCAP_PR bit of
+* Control register in the Device Config Interface)  before it can be
+* accessed using the HwIcap.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 2.00a sv   10/04/07 Initial release.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"	/* XPAR parameters */
+#include "xhwicap.h"		/* HWICAP device driver */
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are defined here such that a user can easily
+ * change all the needed parameters in one place. This definition is not
+ * included if the example is generated from the TestAppGen test tool.
+ */
+#ifndef TESTAPP_GEN
+#define HWICAP_DEVICE_ID		XPAR_HWICAP_0_DEVICE_ID
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+int HwIcapTestAppExample(u16 DeviceId);
+
+
+/************************** Variable Definitions *****************************/
+
+static XHwIcap  HwIcap;	/* The instance of the HWICAP device */
+
+/*****************************************************************************/
+/**
+*
+* Main function to call the HwIcap example. This function is not included if the
+* example is generated from the TestAppGen test tool.
+*
+* @param	None.
+*
+* @return	XST_SUCCESS to indicate success, otherwise XST_FAILURE.
+*
+* @note		None.
+*
+****************************************************************************/
+#ifndef TESTAPP_GEN
+int main(void)
+{
+	int Status;
+
+	/*
+	 * Run the HwIcap Example, specify the Device ID generated in
+	 * xparameters.h
+	 */
+	Status = HwIcapTestAppExample(HWICAP_DEVICE_ID);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+#endif
+
+/****************************************************************************/
+/**
+*
+* The purpose of this function is to illustrate the usage of the HwIcap driver.
+*
+* @param	HwIcapDeviceId is device ID of the XHwIcap Device, typically
+*		XPAR_<HWICAP_instance>_DEVICE_ID value from xparameters.h
+*
+* @return	XST_SUCCESS to indicate success, otherwise XST_FAILURE.
+*
+* @note		None.
+*
+****************************************************************************/
+int HwIcapTestAppExample(u16 HwIcapDeviceId)
+{
+	int Status;
+
+	XHwIcap_Config *ConfigPtr;
+	u32 ConfigRegData;
+
+	/*
+	 * Initialize the HwIcap driver.
+	 */
+	ConfigPtr = XHwIcap_LookupConfig(HwIcapDeviceId);
+	if (ConfigPtr == NULL) {
+		return XST_FAILURE;
+	}
+
+	Status = XHwIcap_CfgInitialize(&HwIcap, ConfigPtr,
+				ConfigPtr->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Perform a self-test to ensure that the hardware was built correctly.
+	 */
+	Status = XHwIcap_SelfTest(&HwIcap);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * Read the ID Code register inside the FPGA.
+	 */
+	Status = XHwIcap_GetConfigReg(&HwIcap, XHI_IDCODE, &ConfigRegData);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	return XST_SUCCESS;
+}
diff --git a/XilinxProcessorIPLib/drivers/hwicap/src/Makefile b/XilinxProcessorIPLib/drivers/hwicap/src/Makefile
new file mode 100755
index 00000000..c0e541b6
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/src/Makefile
@@ -0,0 +1,30 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+# LIB=libxil.a
+LIB=libxil.a
+LEVEL=0
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES=*.c
+INCLUDEFILES=*.h
+
+libs:
+	echo "Compiling hwicap"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+#	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf $(OUTS)
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap.c b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap.c
new file mode 100755
index 00000000..81878378
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap.c
@@ -0,0 +1,1286 @@
+/******************************************************************************
+*
+* Copyright (C) 2007 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap.c
+*
+* This file contains the functions of the XHwIcap driver. See xhwicap.h for a
+* detailed description of the driver.
+*
+* @note
+*
+* Virtex4, Virtex5, Virtex6, Spartan6, 7 series and Zynq devices are supported.
+*
+* In a Zynq device the ICAP needs to be selected using the
+* XDcfg_SelectIcapInterface API of the DevCfg driver (clear the PCAP_PR bit of
+* Control register in the Device Config Interface)  before it can be
+* accessed using the HwIcap.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date      Changes
+* ----- ---- -------- -------------------------------------------------------
+* 2.00a sv   09/11/07  Initial version.
+* 2.01a ecm  04/08/08  Updated data structures to include the V5FXT parts.
+* 3.00a sv   11/28/08  Added the API for initiating Abort while reading/writing
+*		       from the ICAP.
+* 4.00a hvm  12/1/09   Added support for V6 and updated with HAL phase 1
+*		       modifications
+* 5.00a hvm  04/02/10  Added support for S6 device.
+* 5.01a hvm  07/06/10  In XHwIcap_DeviceRead function, a read bit mask
+*		       verification is added after all the data bytes are read
+*		       from READ FIFO.The Verification of the read bit mask
+*		       at the begining of reading of bytes is removed.
+* 5.03a hvm  15/4/11   Updated with V6 CXT device definitions.
+* 6.00a hvm  08/01/11  Added support for K7 devices.
+* 7.00a bss  03/14/12  Added support for 8/16/32 ICAP Data Widths - CR 620085
+*		       Added support for Lite Mode(no Write FIFO) - CR 601748
+*		       Added Virtex 7, Artix 7 and Zynq Idcodes in Device look
+*		        up table - CR 647140, CR 643295
+* 8.01a bss  04/18/13  Updated to fix compiler warnings. CR#704814
+* 9.0   bss  02/20/14  Updated to support Kintex8, kintexu and virtex72000T
+*	 		family devices.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include <xil_types.h>
+#include <xil_assert.h>
+#include "xhwicap.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * This is a list of arrays that contain information about columns interspersed
+ * into the CLB columns.  These are DSP, IOB, DCM, and clock tiles.  When these
+ * are crossed, the frame address must be incremeneted by an additional count
+ * from the CLB column index.  The center tile is skipped twice because it
+ * contains both a DCM and a GCLK tile that must be skipped.
+ * CXT SKIP column definitions are removed for the V6 devices as the existig
+ * V6 Lx definitions are valid for CXT devices also.
+ */
+u16 XHI_EMPTY_SKIP_COLS[] = {0xFFFF};
+
+u16 XHI_XC4VLX15_SKIP_COLS[] = {8, 12, 12, 0xFFFF};
+u16 XHI_XC4VLX25_SKIP_COLS[] = {8, 14, 14, 0xFFFF};
+u16 XHI_XC4VLX40_SKIP_COLS[] = {8, 18, 18, 0xFFFF};
+u16 XHI_XC4VLX60_SKIP_COLS[] = {12, 26, 26, 0xFFFF};
+u16 XHI_XC4VLX80_SKIP_COLS[] = {12, 28, 28, 0xFFFF};
+u16 XHI_XC4VLX100_SKIP_COLS[] = {12, 32, 32, 0xFFFF};
+u16 XHI_XC4VLX160_SKIP_COLS[] = {12, 44, 44, 0xFFFF};
+u16 XHI_XC4VLX200_SKIP_COLS[] = {12, 58, 58, 0xFFFF};
+u16 XHI_XC4VSX25_SKIP_COLS[] = {6, 14, 20, 20, 26, 34, 0xFFFF};
+u16 XHI_XC4VSX35_SKIP_COLS[] = {6, 14, 20, 20, 26, 34, 0xFFFF};
+u16 XHI_XC4VSX55_SKIP_COLS[] = {6, 10, 14, 18, 24, 24, 30, 34, 38,
+                                  42, 0xFFFF};
+u16 XHI_XC4VFX12_SKIP_COLS[] = {12, 12, 16, 0xFFFF};
+u16 XHI_XC4VFX20_SKIP_COLS[] = {6, 18, 18, 22, 30, 0xFFFF};
+u16 XHI_XC4VFX40_SKIP_COLS[] = {6, 26, 26, 38, 46, 0xFFFF};
+u16 XHI_XC4VFX60_SKIP_COLS[] = {6, 18, 26, 26, 34, 46, 0xFFFF};
+u16 XHI_XC4VFX100_SKIP_COLS[] = {6, 22, 34, 34, 46, 62, 0xFFFF};
+u16 XHI_XC4VFX140_SKIP_COLS[] = {6, 22, 42, 42, 62, 78, 0xFFFF};
+
+
+u16 XHI_XC5VLX30_SKIP_COLS[] = {4, 6, 14, 14, 22, 26, 0xFFFF};
+u16 XHI_XC5VLX50_SKIP_COLS[] = {4, 6, 14, 14, 22, 26, 0xFFFF};
+u16 XHI_XC5VLX85_SKIP_COLS[] = {4, 14, 16, 24, 24, 36, 46, 50, 0xFFFF};
+u16 XHI_XC5VLX110_SKIP_COLS[] = {4, 14, 16, 24, 24, 36, 46, 50, 0xFFFF};
+u16 XHI_XC5VLX220_SKIP_COLS[] = {4, 26, 28, 30, 32, 52, 52, 72, 78, 100,
+				104, 0xFFFF};
+u16 XHI_XC5VLX330_SKIP_COLS[] = {4, 26, 28, 30, 32, 52, 52, 72, 78, 100,
+				104, 0xFFFF};
+u16 XHI_XC5VLX30T_SKIP_COLS[] = {4, 6, 14, 14, 22, 26, 0xFFFF};
+u16 XHI_XC5VLX50T_SKIP_COLS[] = {4, 6, 14, 14, 22, 26, 0xFFFF};
+u16 XHI_XC5VLX85T_SKIP_COLS[] = {4, 14, 16, 24, 24, 36, 46, 50, 0xFFFF};
+u16 XHI_XC5VLX110T_SKIP_COLS[] = {4, 14, 16, 24, 24, 36, 46, 50, 0xFFFF};
+u16 XHI_XC5VLX220T_SKIP_COLS[] = {4, 26, 28, 30, 32, 52, 52, 72, 78, 100,
+				104, 0xFFFF};
+u16 XHI_XC5VLX330T_SKIP_COLS[] = {4, 26, 28, 30, 32, 52, 52, 72, 78, 100,
+				104, 0xFFFF};
+u16 XHI_XC5VSX35T_SKIP_COLS[] = {4, 6, 8, 10, 12, 14, 16, 18, 18, 20, 22,
+				24, 26, 30, 0xFFFF};
+u16 XHI_XC5VSX50T_SKIP_COLS[] = {4, 6, 8, 10, 12, 14, 16, 18, 18, 20, 22,
+				24, 26, 30, 0xFFFF};
+u16 XHI_XC5VSX95T_SKIP_COLS[] = {4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24,
+				24, 26, 28, 30, 32, 34, 36, 38, 42, 0xFFFF};
+u16 XHI_XC5VFX30T_SKIP_COLS[] = {4, 10, 16, 20, 20, 24, 26, 28, 30, 34, 0xFFFF};
+u16 XHI_XC5VFX70T_SKIP_COLS[] = {4, 10, 16, 20, 20, 24, 26, 28, 30, 34, 0xFFFF};
+u16 XHI_XC5VFX100T_SKIP_COLS[] = {4, 10, 16, 22, 24, 26, 28, 32, 32, 36,
+				38, 40, 42, 48, 52, 0xFFFF};
+u16 XHI_XC5VFX130T_SKIP_COLS[] = {4, 10, 16, 22, 24, 26, 28, 32, 32, 36,
+				38, 40, 42, 48, 52, 0xFFFF};
+u16 XHI_XC5VFX200T_SKIP_COLS[] = {4, 10, 16, 22, 28, 30, 32, 34, 38, 38, 42, 44,
+				46, 48, 54, 60, 64, 0xFFFF};
+
+/* V6 devices Skip column information */
+u16 XHI_XC6VHX250T_SKIP_COLS[] = {5, 10, 13, 18, 27, 30, 35, 38, 43, 54, 59,
+				64, 67, 72, 75, 84, 89, 92, 97, 105, 106,
+				0xFFFF};
+
+u16 XHI_XC6VHX255T_SKIP_COLS[] = {5, 10, 13, 18, 27, 30, 35, 38, 43, 54, 59,
+				64, 67, 72, 75, 84, 89, 92, 97, 105, 106,
+				0xFFFF};
+
+u16 XHI_XC6VHX380T_SKIP_COLS[] = {5, 10, 13, 18, 27, 30, 35, 38, 43, 54, 59,
+				64, 67, 72, 75, 84, 89, 92, 97, 105, 106,
+				0xFFFF};
+
+u16 XHI_XC6VHX565T_SKIP_COLS[] = {5, 10, 13, 22, 39, 48, 51, 56, 59, 64, 75,
+				80, 85, 88, 93, 96, 105, 122, 131, 134,
+				139, 147, 148, 0xFFFF};
+
+u16 XHI_XC6VLX75T_SKIP_COLS[] = {5, 8, 13, 16, 19, 22, 25, 36, 41, 44, 47,
+				50, 53, 58, 61, 69, 70, 0xFFFF};
+
+u16 XHI_XC6VLX130T_SKIP_COLS[] = {5, 8, 13, 16, 19, 22, 25, 36, 41, 44, 47,
+				50, 53, 58, 61, 69, 70, 0xFFFF};
+
+u16 XHI_XC6VLX195T_SKIP_COLS[] = {5, 8, 13, 16, 25, 28, 33, 36, 41, 52, 57,
+				62, 65, 70, 73, 82, 85, 90, 93, 101, 102,
+				0xFFFF};
+
+u16 XHI_XC6VLX240T_SKIP_COLS[] = {5, 8, 13, 16, 25, 28, 33, 36, 41, 52, 57,
+				62, 65, 70, 73, 82, 85, 90, 93, 101, 102,
+				0xFFFF};
+
+u16 XHI_XC6VLX365T_SKIP_COLS[] = {5, 8, 21, 24, 33, 50, 53, 58, 69, 74, 79,
+				82, 99, 108, 111, 124, 127, 132, 140, 141,
+				0xFFFF};
+
+u16 XHI_XC6VLX550T_SKIP_COLS[] = {5, 8, 21, 24, 33, 50, 53, 58, 69, 74, 79,
+				82, 99, 108, 111, 124, 127, 132, 140, 141,
+				0xFFFF};
+
+u16 XHI_XC6VLX760_SKIP_COLS[] = {5, 8, 33, 36, 45, 70, 77, 80, 85, 96, 101,
+				106, 109, 116, 141, 150, 153, 178, 181, 186,
+				0xFFFF};
+
+u16 XHI_XC6VSX315T_SKIP_COLS[] = {5, 8, 13, 16, 21, 24, 29, 32, 37, 40, 45,
+				48, 51, 54, 59, 70, 75, 80, 83, 86, 89, 94,
+				97, 102,105, 110, 113, 118, 121, 126, 129,
+				137, 138, 0xFFFF};
+
+u16 XHI_XC6VSX475T_SKIP_COLS[] = {5, 8, 13, 16, 21, 24, 29, 32, 37, 40, 45,
+				48, 51, 54, 59, 70, 75, 80, 83, 86, 89, 94,
+				97, 102,105, 110, 113, 118, 121, 126, 129,
+				137, 138, 0xFFFF};
+
+
+u16 XHI_XC6SLX4_SKIP_COLS[] = {3, 6, 9, 0xFFFF};
+
+u16 XHI_XC6SLX9_SKIP_COLS[] = {3, 6, 9, 14, 0xFFFF};
+
+u16 XHI_XC6SLX16_SKIP_COLS[] = {3, 6, 12, 19, 22, 0xFFFF};
+
+u16 XHI_XC6SLX25_SKIP_COLS[] = {3, 6, 12, 19, 28, 31, 0xFFFF};
+
+u16 XHI_XC6SLX45_SKIP_COLS[] = {3, 6, 12, 19, 26, 32, 35, 0xFFFF};
+
+u16 XHI_XC6SLX45T_SKIP_COLS[] = {3, 6, 12, 19, 26, 32, 35, 0xFFFF};
+
+u16 XHI_XC6SLX75_SKIP_COLS[] = {3, 8, 14, 21, 27, 33, 36, 39, 0xFFFF};
+
+u16 XHI_XC6SLX100_SKIP_COLS[] = {3, 6, 11, 15, 21, 28, 35, 41, 46, 51, 54,
+				 0xFFFF};
+
+u16 XHI_XC6SLX150_SKIP_COLS[] = {3, 6, 17, 21, 27, 40, 51, 57, 61, 70, 73,
+				 0xFFFF};
+
+/* Device details look up table  */
+
+const DeviceDetails DeviceDetaillkup[] = {
+
+	/* Virtex4 devices */
+
+	{ XHI_XC4VLX15, 24, 64, 3, 1, 3, 0, 4, XHI_XC4VLX15_SKIP_COLS },
+
+	{ XHI_XC4VLX25, 28, 96, 3, 1, 3, 0, 6, XHI_XC4VLX25_SKIP_COLS },
+
+	{ XHI_XC4VLX40,	36, 128, 3, 1, 3, 0, 8, XHI_XC4VLX40_SKIP_COLS },
+
+	{ XHI_XC4VLX60, 52, 128, 5, 1, 3, 0, 8, XHI_XC4VLX60_SKIP_COLS },
+
+	{ XHI_XC4VLX80, 56, 160, 5, 1, 3, 0, 10, XHI_XC4VLX80_SKIP_COLS },
+
+	{ XHI_XC4VLX100,64, 192, 5, 1, 3, 0, 12, XHI_XC4VLX100_SKIP_COLS },
+
+	{ XHI_XC4VLX160, 88, 192, 6, 1, 3, 0, 12, XHI_XC4VLX160_SKIP_COLS },
+
+	{ XHI_XC4VLX200, 116, 192, 7, 1, 3, 0, 12, XHI_XC4VLX200_SKIP_COLS },
+
+	{ XHI_XC4VSX25,  40, 64, 8, 4, 3, 0, 4, XHI_XC4VSX25_SKIP_COLS },
+
+	{ XHI_XC4VSX35,  40, 96, 8, 4, 3, 0, 6, XHI_XC4VSX35_SKIP_COLS },
+
+	{ XHI_XC4VSX55, 48, 128, 10, 8, 3, 0, 8, XHI_XC4VSX55_SKIP_COLS },
+
+	{ XHI_XC4VFX12, 24, 64, 3, 1, 3, 0, 4, XHI_XC4VFX12_SKIP_COLS },
+
+	{ XHI_XC4VFX20, 36, 64, 5, 1, 3, 2, 4, XHI_XC4VFX20_SKIP_COLS },
+
+	{ XHI_XC4VFX40, 52, 96, 7, 1, 3, 2, 6, XHI_XC4VFX40_SKIP_COLS },
+
+	{ XHI_XC4VFX60, 52, 128, 8, 2, 3, 2, 8, XHI_XC4VFX60_SKIP_COLS },
+
+	{ XHI_XC4VFX100, 68, 160, 10, 2, 3, 2, 10, XHI_XC4VFX100_SKIP_COLS },
+
+	{ XHI_XC4VFX140, 84, 192, 12, 2, 3, 2, 12, XHI_XC4VFX140_SKIP_COLS },
+
+	/* Virtex5 devices.  Array index is 17 for the first V5 device*/
+
+	{ XHI_XC5VLX30, 30, 80, 2, 1, 2, 0, 4, XHI_XC5VLX30_SKIP_COLS },
+
+	{ XHI_XC5VLX50, 30, 120, 2, 1, 2, 0, 6, XHI_XC5VLX50_SKIP_COLS },
+
+	{ XHI_XC5VLX85, 54, 120, 4, 1, 2, 0, 6, XHI_XC5VLX85_SKIP_COLS },
+
+	{ XHI_XC5VLX110, 54, 160, 4, 1, 2, 0, 8, XHI_XC5VLX110_SKIP_COLS },
+
+	{ XHI_XC5VLX220, 108, 160, 6, 2, 2, 0, 8, XHI_XC5VLX220_SKIP_COLS },
+
+	{ XHI_XC5VLX330, 108, 240, 6, 2, 2, 0, 12, XHI_XC5VLX330_SKIP_COLS },
+
+	{ XHI_XC5VLX30T, 30, 80, 3, 1, 2, 1, 4, XHI_XC5VLX30T_SKIP_COLS },
+
+	{ XHI_XC5VLX50T, 30, 120, 3, 1, 2, 1, 6, XHI_XC5VLX50T_SKIP_COLS },
+
+	{ XHI_XC5VLX85T, 54, 120, 5, 1, 2, 1, 6, XHI_XC5VLX85T_SKIP_COLS },
+
+	{ XHI_XC5VLX110T, 54, 160, 5, 1, 2, 1, 8, XHI_XC5VLX110T_SKIP_COLS },
+
+	{ XHI_XC5VLX220T, 108, 160, 7, 2, 2, 1, 8, XHI_XC5VLX220T_SKIP_COLS },
+
+	{ XHI_XC5VLX330T, 108, 240, 7, 2, 2, 1, 12, XHI_XC5VLX330T_SKIP_COLS },
+
+	{ XHI_XC5VSX35T, 34, 80, 6, 6, 2, 1, 4, XHI_XC5VSX35T_SKIP_COLS },
+
+	{ XHI_XC5VSX50T, 34, 120, 6, 6, 2, 1, 6, XHI_XC5VSX50T_SKIP_COLS },
+
+	{ XHI_XC5VSX95T, 46, 160, 7, 10, 2, 1, 8, XHI_XC5VSX95T_SKIP_COLS },
+
+	{ XHI_XC5VFX30T, 38, 80, 5, 2, 2, 1, 4, XHI_XC5VFX30T_SKIP_COLS },
+
+	{ XHI_XC5VFX70T, 38, 160, 5, 2, 2, 1, 8, XHI_XC5VFX70T_SKIP_COLS },
+
+	{ XHI_XC5VFX100T, 56, 160, 8, 4, 2, 1, 8, XHI_XC5VFX100T_SKIP_COLS },
+
+	{ XHI_XC5VFX130T, 56, 200, 8, 4, 3, 1, 10, XHI_XC5VFX130T_SKIP_COLS },
+
+	{ XHI_XC5VFX200T, 68, 240, 10, 4, 3, 1, 12, XHI_XC5VFX200T_SKIP_COLS },
+
+	/* Virtex6 devices. Array index is 37 for the first V6 device */
+
+	{ XHI_XC6VHX250T, 85, 240, 11, 6, 2, 2, 6, XHI_XC6VHX250T_SKIP_COLS },
+
+	{ XHI_XC6VHX255T, 85, 240, 11, 6, 2, 2, 6, XHI_XC6VHX255T_SKIP_COLS },
+
+	{ XHI_XC6VHX380T, 85, 360, 11, 6, 2, 2, 9, XHI_XC6VHX380T_SKIP_COLS },
+
+	{ XHI_XC6VHX565T, 125, 360, 13, 6, 2, 2, 9, XHI_XC6VHX565T_SKIP_COLS },
+
+	{ XHI_XC6VLX75T, 53, 120, 7, 5, 3, 1, 3, XHI_XC6VLX75T_SKIP_COLS },
+
+	{ XHI_XC6VLX130T, 53, 200, 7, 6, 3, 1, 3, XHI_XC6VLX130T_SKIP_COLS },
+
+	{ XHI_XC6VLX195T, 81, 200, 9, 8, 3, 1, 5, XHI_XC6VLX195T_SKIP_COLS },
+
+	{ XHI_XC6VLX240T, 81, 240, 9, 8, 3, 1, 6, XHI_XC6VLX240T_SKIP_COLS },
+
+	{ XHI_XC6VLX365T, 121, 240, 9, 6, 4, 1, 6, XHI_XC6VLX365T_SKIP_COLS },
+
+	{ XHI_XC6VLX550T, 121, 360, 9, 6, 4, 1, 9, XHI_XC6VLX550T_SKIP_COLS },
+
+	{ XHI_XC6VLX760, 121, 360, 10, 6, 4, 0, 9, XHI_XC6VLX760_SKIP_COLS },
+
+	{ XHI_XC6VSX315T, 105, 240, 15, 14, 3, 1, 6, XHI_XC6VSX315T_SKIP_COLS},
+
+	{ XHI_XC6VSX475T, 105, 360, 15, 14, 3, 1, 9, XHI_XC6VSX475T_SKIP_COLS},
+
+	{ XHI_XC6VCX75T, 53, 120, 7, 5, 3, 1, 3, XHI_XC6VLX75T_SKIP_COLS },
+
+	{ XHI_XC6VCX130T, 53, 200, 7, 6, 3, 1, 3, XHI_XC6VLX130T_SKIP_COLS },
+
+	{ XHI_XC6VCX195T, 81, 200, 9, 8, 3, 1, 5, XHI_XC6VLX195T_SKIP_COLS },
+
+	{ XHI_XC6VCX240T, 81, 240, 9, 8, 3, 1, 6, XHI_XC6VLX240T_SKIP_COLS },
+
+	/* Spartan6 devices. Array index is 54 for the first S6 device */
+
+	{ XHI_XC6SLX4, 5, 64, 1, 1, 0, 1, 0, XHI_XC6SLX4_SKIP_COLS },
+
+	{ XHI_XC6SLX9, 12, 64, 2, 1, 0, 1, 0, XHI_XC6SLX9_SKIP_COLS },
+
+	{ XHI_XC6SLX16, 19, 64, 2, 2, 0, 1, 0, XHI_XC6SLX16_SKIP_COLS },
+
+	{ XHI_XC6SLX25, 27, 80, 3, 2, 0, 1, 0, XHI_XC6SLX25_SKIP_COLS },
+
+	{ XHI_XC6SLX25T, 27, 80, 3, 2, 0, 1, 0, XHI_XC6SLX25_SKIP_COLS },
+
+	{ XHI_XC6SLX45, 30, 128, 4, 2, 0, 1, 0, XHI_XC6SLX45_SKIP_COLS },
+
+	{ XHI_XC6SLX45T, 30, 128, 4, 2, 0, 1, 0, XHI_XC6SLX45_SKIP_COLS },
+
+	{ XHI_XC6SLX75, 34, 192, 4, 3, 0, 1, 0, XHI_XC6SLX75_SKIP_COLS },
+
+	{ XHI_XC6SLX75T, 34, 192, 4, 3, 0, 1, 0, XHI_XC6SLX75_SKIP_COLS },
+
+	{ XHI_XC6SLX100, 45, 192, 6, 4, 0, 1, 0, XHI_XC6SLX100_SKIP_COLS },
+
+	{ XHI_XC6SLX100T, 45, 192, 6, 4, 0, 1, 0, XHI_XC6SLX100_SKIP_COLS },
+
+	{ XHI_XC6SLX150, 64, 192, 6, 4, 0, 1, 0, XHI_XC6SLX150_SKIP_COLS },
+
+	{ XHI_XC6SLX150T, 64, 192, 6, 4, 0, 1, 0, XHI_XC6SLX150_SKIP_COLS },
+
+	/*
+	 * Kintex7 devices. Array index is 67 for the first K7 device
+	 * The details of the rows, cloumns etc. are not filled  as
+	 * the related support is not added in the driver. The data
+	 * will be populated whenever the support for writing into a CLB
+	 * is implemented.
+	 */
+	{ XHI_XC7K30T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	{ XHI_XC7K70T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	{ XHI_XC7K160T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	{ XHI_XC7K325T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	{ XHI_XC7K410T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	{ XHI_XC7K235T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	{ XHI_XC7K125T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	{ XHI_XC7K290T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	{ XHI_XC7K355T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	{ XHI_XC7K420T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	{ XHI_XC7K480T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+
+	/*
+	 * Virtex7 devices. Array index is 78 for the first V7 device
+	 * The details of the rows, cloumns etc. are not filled  as
+	 * the related support is not added in the driver. The data
+	 * will be populated whenever the support for writing into a CLB
+	 * is implemented.
+	 */
+
+	 { XHI_XC7VX80T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7VX82T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7VX330T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7VX415T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7V450T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7VX485T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7VX550T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7V585T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7VX690T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7VX980T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7VX2000T_SLR0, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7VX2000T_SLR1, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7VX2000T_SLR2, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7VX2000T_SLR3, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	/*
+	 * Artix7 devices. Array index is 88 for the first V7 device
+	 * The details of the rows, cloumns etc. are not filled  as
+	 * the related support is not added in the driver. The data
+	 * will be populated whenever the support for writing into a CLB
+	 * is implemented.
+	 */
+
+	 { XHI_XC7A15, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7A30T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7A50T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7A100T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7A200T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 { XHI_XC7A350T, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	 /*
+	  * Zynq devices. Array index is 94 for the first V7 device
+	  * The details of the rows, cloumns etc. are not filled  as
+	  * the related support is not added in the driver. The data
+	  * will be populated whenever the support for writing into a CLB
+	  * is implemented.
+	  */
+
+	  { XHI_XC7Z010, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	  { XHI_XC7Z020, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	  { XHI_XC7Z030, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+   	  { XHI_XC7Z045, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+	/*
+	 * Kintex8 devices. Array index is 98 for the first K8 device
+	 * The details of the rows, cloumns etc. are not filled  as
+	 * the related support is not added in the driver. The data
+	 * will be populated whenever the support for writing into a CLB
+	 * is implemented.
+	 */
+
+   	 { XHI_XCKU040T, 0, 0, 0, 0, 0, 0, 0, 0 }
+};
+
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+				u32 ByteCount);
+
+/****************************************************************************/
+/**
+*
+* This function initializes a specific XHwIcap instance.
+* The IDCODE is read from the FPGA and based on the IDCODE the information
+* about the resources in the FPGA is filled in the instance structure.
+*
+* The HwIcap device will be in put in a reset state before exiting this
+* function.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+* @param	ConfigPtr points to the XHwIcap device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address is passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+int XHwIcap_CfgInitialize(XHwIcap *InstancePtr, XHwIcap_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	int Status;
+	u32 DeviceIdCode;
+	u32 TempDevId;
+	u8 DeviceIdIndex;
+	u8 NumDevices;
+	u8 IndexCount;
+	int DeviceFound = FALSE;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values.
+	 */
+	InstancePtr->IsReady = FALSE;
+	InstancePtr->IsTransferInProgress = FALSE;
+	InstancePtr->IsPolled = TRUE; /* Polled Mode */
+
+	/*
+	 * Set the device base address and stub handler.
+	 */
+	InstancePtr->HwIcapConfig.BaseAddress = EffectiveAddr;
+	InstancePtr->StatusHandler = (XHwIcap_StatusHandler) StubStatusHandler;
+
+	/** Set IcapWidth **/
+
+	InstancePtr->HwIcapConfig.IcapWidth = ConfigPtr->IcapWidth;
+
+	/** Set IsLiteMode **/
+	InstancePtr->HwIcapConfig.IsLiteMode = ConfigPtr->IsLiteMode;
+
+	/*
+	 * Read the IDCODE from ICAP.
+	 */
+
+	/*
+	 * Setting the IsReady of the driver temporarily so that
+	 * we can read the IdCode of the device.
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Dummy Read of the IDCODE as the first data read from the
+	 * ICAP has to be discarded (Due to the way the HW is designed).
+	 */
+	Status = XHwIcap_GetConfigReg(InstancePtr, XHI_IDCODE, &TempDevId);
+	if (Status != XST_SUCCESS) {
+		InstancePtr->IsReady = 0;
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Read the IDCODE and mask out the version section of the DeviceIdCode.
+	 */
+	Status = XHwIcap_GetConfigReg(InstancePtr, XHI_IDCODE, &DeviceIdCode);
+	if (Status != XST_SUCCESS) {
+		InstancePtr->IsReady = 0;
+		return XST_FAILURE;
+	}
+
+	DeviceIdCode = DeviceIdCode & XHI_DEVICE_ID_CODE_MASK;
+
+#if (XHI_FAMILY != XHI_DEV_FAMILY_S6)
+	Status = XHwIcap_CommandDesync(InstancePtr);
+	InstancePtr->IsReady = 0;
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+#endif
+
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
+
+	DeviceIdIndex = 0;
+	NumDevices = XHI_V4_NUM_DEVICES;
+
+#elif XHI_FAMILY == XHI_DEV_FAMILY_V5 /* Virtex5 */
+
+	DeviceIdIndex = XHI_V4_NUM_DEVICES;
+	NumDevices = XHI_V5_NUM_DEVICES;
+
+#elif XHI_FAMILY == XHI_DEV_FAMILY_V6 /* Virtex6 */
+
+	DeviceIdIndex = XHI_V4_NUM_DEVICES +  XHI_V5_NUM_DEVICES;
+	NumDevices = XHI_V6_NUM_DEVICES;
+
+#elif XHI_FAMILY == XHI_DEV_FAMILY_S6 /* Spartan6 */
+
+	DeviceIdIndex = XHI_V4_NUM_DEVICES +  XHI_V5_NUM_DEVICES +
+			XHI_V6_NUM_DEVICES;
+	NumDevices = XHI_S6_NUM_DEVICES;
+
+#elif XHI_FAMILY == XHI_DEV_FAMILY_7SERIES /* 7Series */
+
+	DeviceIdIndex = XHI_V4_NUM_DEVICES +  XHI_V5_NUM_DEVICES +
+			XHI_V6_NUM_DEVICES +  XHI_S6_NUM_DEVICES;
+	NumDevices = XHI_K7_NUM_DEVICES + XHI_V7_NUM_DEVICES +
+			XHI_A7_NUM_DEVICES + XHI_ZYNQ_NUM_DEVICES +
+			XHI_K8_NUM_DEVICES;
+#endif
+	/*
+	 * Find the device index
+	 */
+	for (IndexCount = 0; IndexCount < NumDevices; IndexCount++) {
+
+		if (DeviceIdCode == DeviceDetaillkup[DeviceIdIndex +
+					IndexCount]. DeviceIdCode) {
+			DeviceIdIndex += IndexCount;
+			DeviceFound = TRUE;
+			break;
+		}
+	}
+
+	if (DeviceFound != TRUE) {
+
+		return XST_FAILURE;
+
+	}
+	InstancePtr->DeviceIdCode = DeviceDetaillkup[DeviceIdIndex].
+					DeviceIdCode;
+
+	InstancePtr->Rows = DeviceDetaillkup[DeviceIdIndex].Rows;
+	InstancePtr->Cols = DeviceDetaillkup[DeviceIdIndex].Cols;
+	InstancePtr->BramCols = DeviceDetaillkup[DeviceIdIndex].BramCols;
+
+	InstancePtr->DSPCols = DeviceDetaillkup[DeviceIdIndex].DSPCols;
+	InstancePtr->IOCols = DeviceDetaillkup[DeviceIdIndex].IOCols;
+	InstancePtr->MGTCols = DeviceDetaillkup[DeviceIdIndex].MGTCols;
+
+	InstancePtr->HClkRows = DeviceDetaillkup[DeviceIdIndex].HClkRows;
+	InstancePtr->SkipCols = DeviceDetaillkup[DeviceIdIndex].SkipCols;
+
+	InstancePtr->BytesPerFrame = XHI_NUM_FRAME_BYTES;
+
+#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+	/*
+	 * In Spartan6 devices the word is defined as 16 bit
+	 */
+	InstancePtr->WordsPerFrame = (InstancePtr->BytesPerFrame/2);
+#else
+	InstancePtr->WordsPerFrame = (InstancePtr->BytesPerFrame/4);
+#endif
+	InstancePtr->ClbBlockFrames = (4 +22*2 + 4*2 + 22*InstancePtr->Cols);
+	InstancePtr->BramBlockFrames = (64*InstancePtr->BramCols);
+	InstancePtr->BramIntBlockFrames = (22*InstancePtr->BramCols);
+
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Reset the device.
+	 */
+	XHwIcap_Reset(InstancePtr);
+
+	return XST_SUCCESS;
+} /* end XHwIcap_CfgInitialize() */
+
+
+/****************************************************************************/
+/**
+*
+* This function writes the given user data to the Write FIFO in both the
+* polled mode and the interrupt mode and starts the transfer of the data to
+* the ICAP device.
+*
+* In the polled mode, this function will write the specified number of words
+* into the FIFO before returning.
+*
+* In the interrupt mode, this function will write the words upto the size
+* of the Write FIFO and starts the transfer, then subsequent transfer of the
+* data is performed by the interrupt service routine until the entire buffer
+* has been transferred. The status callback function is called when the entire
+* buffer has been sent.
+* In order to use interrupts, it is necessary for the user to connect the driver
+* interrupt handler, XHwIcap_IntrHandler(), to the interrupt system of
+* the application and enable the interrupts associated with the Write FIFO.
+* The user has to enable the interrupts each time this function is called
+* using the XHwIcap_IntrEnable macro.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+* @param	FrameBuffer is a pointer to the data to be written to the
+*			ICAP device.
+* @param	NumWords is the number of words (16 bit for S6 and 32 bit
+*		for all other devices)to write to the ICAP device.
+*
+* @return	XST_SUCCESS or XST_FAILURE
+*
+* @note		This function is a blocking for the polled mode of operation
+*		and is non-blocking for the interrupt mode of operation.
+*		Use the function XHwIcap_DeviceWriteFrame for writing a frame
+*		of data to the ICAP device.
+*
+*****************************************************************************/
+#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+int XHwIcap_DeviceWrite(XHwIcap *InstancePtr, u16 *FrameBuffer, u32 NumWords)
+#else
+int XHwIcap_DeviceWrite(XHwIcap *InstancePtr, u32 *FrameBuffer, u32 NumWords)
+#endif
+{
+
+#if (XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)
+	u32 Index; /* Array Index */
+#if XPAR_HWICAP_0_ICAP_DWIDTH == 8
+	u8 Fifo[NumWords*4];
+#elif XPAR_HWICAP_0_ICAP_DWIDTH == 16
+	u16 Fifo[NumWords*2];
+#else
+	u32 Fifo[4]; /** Icap Width of 32 does not use Fifo but declared
+			 to overcome compilation error. Size of 4 is used
+			 to overcome compiler warnings */
+#endif
+
+#endif
+
+#if (XPAR_HWICAP_0_MODE == 0)
+	u32 WrFifoVacancy;
+	u32 IntrStatus;
+#endif
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(FrameBuffer != NULL);
+	Xil_AssertNonvoid(NumWords > 0);
+
+	/*
+	 * Make sure that the last Read/Write by the driver is complete.
+	 */
+	if (XHwIcap_IsTransferDone(InstancePtr) == FALSE) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Check if the ICAP device is Busy with the last Read/Write
+	 */
+	if (XHwIcap_IsDeviceBusy(InstancePtr) == TRUE) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set the flag, which will be cleared when the transfer
+	 * is entirely done from the FIFO to the ICAP.
+	 */
+	InstancePtr->IsTransferInProgress = TRUE;
+
+	/*
+	 * Disable the Global Interrupt.
+	 */
+	XHwIcap_IntrGlobalDisable(InstancePtr);
+
+
+#if (XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)
+
+	/* 16 bit */
+	if(InstancePtr->HwIcapConfig.IcapWidth == 16)
+	{
+
+		for(Index = 0;Index < (NumWords*2);Index = Index + 2)
+		{
+			Fifo[Index + 1] = *FrameBuffer;
+			Fifo[Index]	= *FrameBuffer >> 16;
+			FrameBuffer++;
+		}
+
+		InstancePtr->RequestedWords = NumWords * 2;
+		InstancePtr->RemainingWords = NumWords * 2;
+		InstancePtr->SendBufferPtr = &Fifo[0];
+	}
+
+	/* 8 bit */
+	else if(InstancePtr->HwIcapConfig.IcapWidth == 8)
+	{
+		for(Index = 0;Index < (NumWords*4);Index = Index + 4)
+		{
+			Fifo[Index + 3] = *FrameBuffer;
+			Fifo[Index + 2] = *FrameBuffer >> 8;
+			Fifo[Index + 1] = *FrameBuffer >> 16;
+			Fifo[Index]	= *FrameBuffer >> 24;
+			FrameBuffer++;
+		}
+		InstancePtr->RequestedWords = NumWords * 4;
+		InstancePtr->RemainingWords = NumWords * 4;
+		InstancePtr->SendBufferPtr = &Fifo[0];
+
+	}
+
+#endif
+
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_S6) || (XPAR_HWICAP_0_ICAP_DWIDTH == 32)\
+|| (XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5))
+
+	/*
+	 * Set up the buffer pointer and the words to be transferred.
+	 */
+	InstancePtr->SendBufferPtr = FrameBuffer;
+	InstancePtr->RequestedWords = NumWords;
+	InstancePtr->RemainingWords = NumWords;
+
+#endif
+
+	/*
+	 * Fill the FIFO with as many words as it will take (or as many as we
+	 * have to send.
+	 */
+
+
+#if (XPAR_HWICAP_0_MODE == 1)
+	 /* If Lite Mode then write one by one word in WriteFIFO register */
+	while (InstancePtr->RemainingWords > 0) {
+
+		XHwIcap_FifoWrite(InstancePtr, *InstancePtr->SendBufferPtr);
+
+		XHwIcap_StartConfig(InstancePtr);
+
+		while ((XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
+					XHI_CR_OFFSET)) & XHI_CR_WRITE_MASK);
+
+		InstancePtr->RemainingWords--;
+
+		InstancePtr->SendBufferPtr++;
+	}
+
+	/*
+	 * Clear the flag to indicate the write has been done
+	 */
+	InstancePtr->IsTransferInProgress = FALSE;
+	InstancePtr->RequestedWords = 0x0;
+
+#else
+	/* If FIFOs are enabled, fill the FIFO and initiate transfer */
+
+	WrFifoVacancy = XHwIcap_GetWrFifoVacancy(InstancePtr);
+	while ((WrFifoVacancy != 0) &&
+			(InstancePtr->RemainingWords > 0)) {
+
+		XHwIcap_FifoWrite(InstancePtr, *InstancePtr->SendBufferPtr);
+		InstancePtr->RemainingWords--;
+		WrFifoVacancy--;
+		InstancePtr->SendBufferPtr++;
+	}
+
+
+	/*
+	 * Start the transfer of the data from the FIFO to the ICAP device.
+	 */
+	XHwIcap_StartConfig(InstancePtr);
+
+	while ((XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
+				XHI_CR_OFFSET)) & XHI_CR_WRITE_MASK);
+
+	/*
+	 * Check if there is more data to be written to the ICAP
+	 */
+	if (InstancePtr->RemainingWords != NULL){
+
+		/*
+		 * Check whether it is polled or interrupt mode of operation.
+		 */
+		if (InstancePtr->IsPolled == FALSE) { /* Interrupt Mode */
+
+			/*
+			 * If it is interrupt mode of operation then the
+			 * transfer of the remaining data will be done in the
+			 * interrupt handler.
+			 */
+
+			/*
+			 * Clear the interrupt status of the earlier interrupts
+			 */
+			IntrStatus  = XHwIcap_IntrGetStatus(InstancePtr);
+			XHwIcap_IntrClear(InstancePtr, IntrStatus);
+
+
+			/*
+			 * Enable the interrupts by enabling the
+			 * Global Interrupt.
+			 */
+			XHwIcap_IntrGlobalEnable(InstancePtr);
+
+		}
+
+		else { /* Polled Mode */
+
+			while (InstancePtr->RemainingWords > 0) {
+
+				WrFifoVacancy =
+					XHwIcap_GetWrFifoVacancy(InstancePtr);
+				while ((WrFifoVacancy != 0) &&
+			       		(InstancePtr->RemainingWords > 0)) {
+					XHwIcap_FifoWrite(InstancePtr,
+						*InstancePtr->SendBufferPtr);
+					InstancePtr->RemainingWords--;
+					WrFifoVacancy--;
+					InstancePtr->SendBufferPtr++;
+				}
+
+				XHwIcap_StartConfig(InstancePtr);
+				while ((XHwIcap_ReadReg(InstancePtr->
+					HwIcapConfig.BaseAddress,
+					XHI_CR_OFFSET)) & XHI_CR_WRITE_MASK);
+				}
+
+				/*
+		 		 * Clear the flag to indicate the write has
+		 		 * been done
+		 		 */
+				InstancePtr->IsTransferInProgress = FALSE;
+				InstancePtr->RequestedWords = 0x0;
+			}
+
+		}
+
+	else {
+
+		/*
+		 * Clear the flag to indicate the write has been done
+		 */
+		InstancePtr->IsTransferInProgress = FALSE;
+		InstancePtr->RequestedWords = 0x0;
+
+	}
+
+#endif
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the specified number of words from the ICAP device in
+* the polled mode. Interrupt mode is not supported in reading data from the
+* ICAP device.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+* @param	FrameBuffer is a pointer to the memory where the frame read
+*		from the ICAP device is stored.
+* @param	NumWords is the number of words (16 bit for S6 and 32 bit for
+* 			all other devices) to write to the ICAP device.
+*
+* @return
+*		- XST_SUCCESS if the specified number of words have been read
+*		from the ICAP device
+*		- XST_FAILURE if the device is busy with the last Read/Write or
+*		if the requested number of words have not been read from the
+*		ICAP device, or there is a timeout.
+*
+* @note		This is a blocking function.
+*
+*****************************************************************************/
+#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+int XHwIcap_DeviceRead(XHwIcap *InstancePtr, u16 *FrameBuffer, u32 NumWords)
+#else
+int XHwIcap_DeviceRead(XHwIcap *InstancePtr, u32 *FrameBuffer, u32 NumWords)
+#endif
+{
+
+	u32 Retries = 0;
+#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+	u16 *Data = FrameBuffer;
+#elif (XHI_FAMILY == XHI_DEV_FAMILY_V6) ||\
+(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)
+	u32 Index = 0; /* Array Index */
+#if XPAR_HWICAP_0_ICAP_DWIDTH == 8
+	u8 Data[NumWords*4];
+#elif XPAR_HWICAP_0_ICAP_DWIDTH == 16
+	u16 Data[NumWords*2];
+#else
+	u32 *Data = FrameBuffer;
+#endif
+
+#else
+	u32 *Data = FrameBuffer;
+#endif
+	u32 RdFifoOccupancy = 0;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(FrameBuffer != NULL);
+	Xil_AssertNonvoid(NumWords > 0);
+
+	/*
+	 * Make sure that the last Read/Write by the driver is complete.
+	 */
+	if (XHwIcap_IsTransferDone(InstancePtr) == FALSE) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Check if the ICAP device is Busy with the last Write/Read
+	 */
+	if (XHwIcap_IsDeviceBusy(InstancePtr) == TRUE) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set the flag, which will be cleared by the driver
+	 * when the transfer is entirely done.
+	 */
+	InstancePtr->IsTransferInProgress = TRUE;
+
+#if (XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)
+
+	/* 8 bit */
+	if(InstancePtr->HwIcapConfig.IcapWidth == 8)
+	{
+		InstancePtr->RequestedWords = NumWords * 4;
+		InstancePtr->RemainingWords = NumWords * 4;
+		XHwIcap_SetSizeReg(InstancePtr, NumWords*4);
+	}
+	/* 16 bit */
+	else if(InstancePtr->HwIcapConfig.IcapWidth == 16)
+	{
+		InstancePtr->RequestedWords = NumWords * 2;
+		InstancePtr->RemainingWords = NumWords * 2;
+		XHwIcap_SetSizeReg(InstancePtr, NumWords*2);
+	}
+
+	/* 32 bit */
+	else {
+
+		InstancePtr->RequestedWords = NumWords;
+		InstancePtr->RemainingWords = NumWords;
+		XHwIcap_SetSizeReg(InstancePtr, NumWords);
+	}
+
+
+#else
+
+	InstancePtr->RequestedWords = NumWords;
+	InstancePtr->RemainingWords = NumWords;
+	XHwIcap_SetSizeReg(InstancePtr, NumWords);
+
+#endif
+
+	XHwIcap_StartReadBack(InstancePtr);
+
+	/*
+	 * Read the data from the Read FIFO into the buffer provided by
+	 * the user.
+	 */
+	/* As long as there is still data to read... */
+	while (InstancePtr->RemainingWords > 0) {
+		/* Wait until we have some data in the fifo. */
+
+			while(RdFifoOccupancy == 0) {
+			RdFifoOccupancy =
+			XHwIcap_GetRdFifoOccupancy(InstancePtr);
+
+			Retries++;
+			if (Retries > XHI_MAX_RETRIES) {
+				break;
+			}
+		}
+
+		/* Read the data from the Read FIFO. */
+
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_S6) || (XPAR_HWICAP_0_ICAP_DWIDTH == 32)\
+|| (XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5))
+		while((RdFifoOccupancy != 0) &&
+				(InstancePtr->RemainingWords > 0)) {
+			*Data++ = XHwIcap_FifoRead(InstancePtr);
+			InstancePtr->RemainingWords--;
+			RdFifoOccupancy--;
+		}
+
+#elif (XHI_FAMILY == XHI_DEV_FAMILY_V6) ||\
+(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)
+	/* 8/16 bit */
+	if((InstancePtr->HwIcapConfig.IcapWidth == 8) ||
+				(InstancePtr->HwIcapConfig.IcapWidth == 16)) {
+
+		while((RdFifoOccupancy != 0) &&
+			(InstancePtr->RemainingWords > 0)) {
+			Data[Index] = XHwIcap_FifoRead(InstancePtr);
+			InstancePtr->RemainingWords--;
+			RdFifoOccupancy--;
+			Index++;
+		}
+	}
+
+#endif
+
+}
+
+while ((XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
+					XHI_CR_OFFSET)) &
+					XHI_CR_READ_MASK);
+
+#if (XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)
+
+	/* 8 bit */
+	if(InstancePtr->HwIcapConfig.IcapWidth == 8)
+	{
+		for(Index = 0 ; Index < (NumWords * 4) ; Index = Index + 4) {
+			*FrameBuffer = Data[Index] << 24;
+			*FrameBuffer = *FrameBuffer | Data[Index + 1] << 16;
+			*FrameBuffer = *FrameBuffer | Data[Index + 2] << 8;
+			*FrameBuffer = *FrameBuffer | Data[Index + 3];
+			FrameBuffer++;
+		}
+
+	}
+
+	/* 16 bit */
+	else if(InstancePtr->HwIcapConfig.IcapWidth == 16)
+	{
+		for(Index = 0 ; Index < (NumWords * 2) ; Index = Index + 2) {
+			*FrameBuffer = Data[Index] << 16;
+			*FrameBuffer = *FrameBuffer | Data[Index + 1];
+			FrameBuffer++;
+		}
+	}
+#endif
+
+	/*
+	 * If the requested number of words have not been read from
+	 * the device then indicate failure.
+	 */
+	if (InstancePtr->RemainingWords != 0){
+		return XST_FAILURE;
+	}
+
+
+	InstancePtr->IsTransferInProgress = FALSE;
+	InstancePtr->RequestedWords = 0x0;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function forces the software reset of the complete HWICAP device.
+* All the registers will return to the default value and the FIFO is also
+* flushed as a part of this software reset.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XHwIcap_Reset(XHwIcap *InstancePtr)
+{
+	u32 RegData;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Reset the device by setting/clearing the RESET bit in the
+	 * Control Register.
+	 */
+	RegData = XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
+				XHI_CR_OFFSET);
+
+	XHwIcap_WriteReg(InstancePtr->HwIcapConfig.BaseAddress, XHI_CR_OFFSET,
+				RegData | XHI_CR_SW_RESET_MASK);
+
+	XHwIcap_WriteReg(InstancePtr->HwIcapConfig.BaseAddress, XHI_CR_OFFSET,
+				RegData & (~ XHI_CR_SW_RESET_MASK));
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function flushes the FIFOs in the device.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XHwIcap_FlushFifo(XHwIcap *InstancePtr)
+{
+	u32 RegData;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Flush the FIFO by setting/clearing the FIFO Clear bit in the
+	 * Control Register.
+	 */
+	RegData = XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
+				XHI_CR_OFFSET);
+
+	XHwIcap_WriteReg(InstancePtr->HwIcapConfig.BaseAddress, XHI_CR_OFFSET,
+				RegData | XHI_CR_FIFO_CLR_MASK);
+
+	XHwIcap_WriteReg(InstancePtr->HwIcapConfig.BaseAddress, XHI_CR_OFFSET,
+				RegData & (~ XHI_CR_FIFO_CLR_MASK));
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function initiates the Abort Sequence by setting the Abort bit in the
+* control register.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XHwIcap_Abort(XHwIcap *InstancePtr)
+{
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Initiate the Abort sequence in the ICAP by setting the Abort bit in
+	 * the Control Register.
+	 */
+	RegData = XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
+				XHI_CR_OFFSET);
+
+	XHwIcap_WriteReg(InstancePtr->HwIcapConfig.BaseAddress, XHI_CR_OFFSET,
+				RegData | XHI_CR_SW_ABORT_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+* @param	StatusEvent is the event that just occurred.
+* @param	WordCount is the number of words (32 bit) transferred up until
+*		the event occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent, u32 ByteCount)
+{
+	(void) CallBackRef;
+	(void) StatusEvent;
+	(void) ByteCount;
+
+	Xil_AssertVoidAlways();
+}
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap.h b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap.h
new file mode 100755
index 00000000..9bb7918a
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap.h
@@ -0,0 +1,899 @@
+/******************************************************************************
+*
+* Copyright (C) 2007 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap.h
+*
+* The Xilinx XHwIcap driver supports the Xilinx Hardware Internal Configuration
+* Access Port (HWICAP) device.
+*
+* The HWICAP device is used for reconfiguration of select FPGA resources
+* as well as loading partial bitstreams from the system memory through the
+* Internal Configuration Access Port (ICAP).
+*
+* The source code for the XHwIcap_SetClbBits and XHwIcap_GetClbBits
+* functions  are not included. These functions are delivered as .o
+* files. These files have been compiled using gcc version 4.1.1.
+* Libgen uses the appropriate .o files for the target processor.
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the HWICAP device.
+*
+* XHwIcap_CfgInitialize() API is used to initialize the HWICAP device.
+* The user needs to first call the XHwIcap_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to the
+* XHwIcap_CfgInitialize() API.
+*
+* <b> Interrupts </b>
+*
+* The driver provides an interrupt handler XHwIcap_IntrHandler for handling
+* the interrupt from the HWICAP device. The users of this driver have to
+* register this handler with the interrupt system and provide the callback
+* functions. The callback functions are invoked by the interrupt handler based
+* on the interrupt source.
+*
+* The driver supports interrupt mode only for writing to the ICAP device and
+* is NOT supported for reading from the ICAP device.
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XHwIcap driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+* @note
+*
+* There are a few items to be aware of when using this driver:
+* 1) Only Virtex4, Virtex5, Virtex6,  Spartan6, 7 series and Zynq devices are
+*    supported.
+* 2) The ICAP port is disabled when the configuration mode, via the MODE pins,
+* is set to Boundary Scan/JTAG. The ICAP is enabled in all other configuration
+* modes and it is possible to configure the device via JTAG in all
+* configuration modes.
+* 3) Reading or writing to columns containing SRL16's or LUT RAM's can cause
+* corruption of data in those elements. Avoid reading or writing to columns
+* containing SRL16's or LUT RAM's.
+* 4) Only the LUT and SRL are accesible, all other features of the slice are
+* not available through this interface.
+* 5) The Spartan6 devices access is 16-bit access and is 32 bit for all
+* other devices.
+* 6) In a Zynq device the ICAP needs to be selected using the
+*    XDcfg_SelectIcapInterface API of the DevCfg driver (clear the PCAP_PR bit
+*    of Control register in the Device Config Interface)  before it can be
+*    accessed using the HwIcap.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb  11/17/03 First release
+* 1.01a bjb  04/10/06 V4 Support
+* 2.00a sv   09/28/07 First release for the FIFO mode
+* 2.01a ecm  04/08/08 Updated data structures to include the V5FXT parts.
+* 3.00a sv   11/28/08 Added the API for initiating Abort while reading/writing
+*		      from the ICAP.
+* 3.01a sv   10/21/09 Corrected the IDCODE definitions for some of the
+*                     V5 FX parts in xhwicap_l.h. Corrected the V5 BOOTSTS and
+*                     CTL_1 Register definitions in xhwicap_i.h file as they
+*                     were wrongly defined.
+* 4.00a hvm  12/1/09  Added support for V6 and updated with HAL phase 1
+*		      modifications
+* 5.00a hvm  04/02/10 Added S6 device support
+* 5.01a hvm  07/06/10 In XHwIcap_DeviceRead function, a read bit mask
+*		      verification is added after all the data bytes are read
+*		      from READ FIFO.The Verification of the read bit mask
+*		      at the begining of reading of bytes is removed.
+*		      Removed the code that adds wrong data byte before the
+*		      CRC bytes in the XHwIcap_DeviceWriteFrame function for S6
+*		      (CR560534).
+* 5.02a hvm  10/06/10 Updated to support AXI HWICAP
+* 5.03a hvm  15/4/11 Updated with V6 CXT device definitions.
+*
+* 6.00a hvm  08/01/11 Added support for K7 devices.
+* 7.00a bss  03/14/12 Added support for 8/16/32 ICAP Data Widths - CR 620085
+*		      Added support for Lite Mode(no Write FIFO) - CR 601748
+*		      Added Virtex7,Artix7 and Zynq Idcodes-CR647140,CR643295
+*		      ReadId API is added to desync after lock up during
+*			configuration CR 637538
+* 8.00a bss  06/20/12 Deleted ReadId API in xhwicap_srp.c and Hang mask
+*			definition in xhwicap_l.h as per CR 656162
+* 8.01a bss  04/18/13  Updated xhwicap.c to fix compiler warnings. CR#704814
+* 		       Added the define XHI_COR_1 for CR718042
+* 9.0   adk  19/12/13 Updated as per the New Tcl API's
+* 9.0   bss  02/20/14 Modified xhwicap.c, xhwicap_l.h, xhwicap_i.h and tcl
+*		      to support Kintex8, kintexu and virtex72000T family
+*		      devices.
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XHWICAP_H_ /* prevent circular inclusions */
+#define XHWICAP_H_ /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xhwicap_i.h"
+#include "xhwicap_l.h"
+#include <xstatus.h>
+#include "xparameters.h"
+
+/************************** Constant Definitions ****************************/
+
+/************************** Type Definitions ********************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing of the HwIcap driver. The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode. The handler executes in an interrupt context such
+ * that minimal processing should be performed.
+ *
+ * @param 	CallBackRef is a callback reference passed in by the
+ *		application layer when setting the callback functions, and
+ *		passed back to the upper layer when the callback is invoked.
+ *		Its type is unimportant to the driver component, so it is a
+ *		void pointer.
+ * @param 	StatusEvent indicates one or more status events that occurred.
+ *		See the XHwIcap_SetInterruptHandler for details on the status
+ *		events that can be passed in the callback.
+ * @param	WordCount indicates how many words of data were successfully
+ *		transferred.  This may be less than the number of words
+ *		requested if there was an error.
+ */
+typedef void (*XHwIcap_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+					u32 WordCount);
+
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Device ID  of device */
+	u32 BaseAddress;	/**< Register base address */
+	int IcapWidth;		/**< Width of ICAP */
+	int IsLiteMode;		/**< IsLiteMode, 0 not
+					present, 1 present */
+
+} XHwIcap_Config;
+
+typedef struct  {
+
+	u32 DeviceIdCode;	     /**< IDCODE of targeted device */
+	u32 Cols;		     /**< Number of CLB cols */
+	u32 Rows;		     /**< Number of CLB rows */
+	u32 BramCols;		     /**< Number of BRAM cols */
+	u8  DSPCols;		     /**< Number of DSP cols for V4/V5/V6 */
+	u8  IOCols;		     /**< Number of IO cols for V4/V5/V6 */
+	u8  MGTCols;		     /**< Number of MGT cols for V4/V5/V6 */
+	u8  HClkRows;		     /**< Number of HClk cols for V4/V5/V6 */
+	u16 *SkipCols;		     /**< Columns to skip for CLB Col */
+
+} DeviceDetails;
+
+ /**
+  * The XHwIcap driver instance data. The user is required to allocate a
+  * variable of this type for every HwIcap device in the system. A pointer
+  * to a variable of this type is then passed to the driver API functions.
+  */
+typedef struct {
+	XHwIcap_Config HwIcapConfig; /**< Instance of the config struct. */
+	u32 IsReady;		     /**< Device is initialized and ready */
+	int IsPolled;		     /**< Device is in polled mode */
+	u32 DeviceIdCode;	     /**< IDCODE of targeted device */
+	u32 Rows;		     	/**< Number of CLB rows */
+	u32 Cols;		     		/**< Number of CLB cols */
+	u32 BramCols;		     /**< Number of BRAM cols */
+	u32 BytesPerFrame;	     /**< Number of Bytes per minor Frame */
+	u32 WordsPerFrame;	     /**< Number of Words per minor Frame */
+	u32 ClbBlockFrames; 	     /**< Number of CLB type minor Frames */
+	u32 BramBlockFrames;	     /**< Number of Bram type minor Frames */
+	u32 BramIntBlockFrames;	     /**< Number of BramInt type minor
+						Frames */
+	u8  HClkRows;		     /**< Number of HClk cols for V4/V5 */
+	u8  DSPCols;		     /**< Number of DSP cols for V4/V5 */
+	u8  IOCols;		     	/**< Number of IO cols for V4/V5 */
+	u8  MGTCols;		     /**< Number of MGT cols for V4/V5 */
+	u16 *SkipCols;		     /**< Columns to skip for CLB Col
+				      			**  calculations */
+
+#if XHI_FAMILY == XHI_DEV_FAMILY_S6 /* If Spartan6 device */
+	u16 *SendBufferPtr;	     /**< Buffer to write to the ICAP device */
+
+
+#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V6) ||\
+(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+				      /**< If V6 or 7Series declare buffer
+					  ** pointer depending on ICAP width */
+#if XPAR_HWICAP_0_ICAP_DWIDTH == 8
+	u8 *SendBufferPtr;
+#elif XPAR_HWICAP_0_ICAP_DWIDTH == 16
+	u16 *SendBufferPtr;
+#else
+	u32 *SendBufferPtr;
+#endif
+
+#else
+	u32 *SendBufferPtr;
+
+#endif
+	u32 RequestedWords;	     /**< Number of Words to transfer  */
+	u32 RemainingWords; 	     /**< Number of Words left to transfer  */
+	int IsTransferInProgress;    /**< A transfer is in progress */
+	XHwIcap_StatusHandler StatusHandler; /**< Interrupt handler callback */
+	void *StatusRef;	     /**< Callback ref. for the interrupt
+						* handler */
+
+} XHwIcap;
+
+/***************** Macro (Inline Functions) Definitions *********************/
+
+
+/****************************************************************************/
+/**
+*
+* Write data to the Write FIFO.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+* @param	Data is the 32-bit value to be written to the FIFO.
+*
+* @return	None.
+*
+* @note		C-style Signature:
+* 		void XHwIcap_FifoWrite(XHwIcap *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XHwIcap_FifoWrite(InstancePtr, Data) 				\
+	(XHwIcap_WriteReg(((InstancePtr)->HwIcapConfig.BaseAddress),	\
+		XHI_WF_OFFSET, (Data)))
+
+/****************************************************************************/
+/**
+*
+* Read data from the Read FIFO.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+*
+* @return	The 32-bit Data read from the FIFO.
+*
+* @note		C-style Signature:
+* 		u32 XHwIcap_FifoRead(XHwIcap *InstancePtr);
+*
+*****************************************************************************/
+#define XHwIcap_FifoRead(InstancePtr) 					\
+(XHwIcap_ReadReg(((InstancePtr)->HwIcapConfig.BaseAddress), XHI_RF_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* Set the number of words to be read from the Icap in the Size register.
+*
+* The Size Register holds the number of 32 bit words to transfer from the
+* the Icap to the Read FIFO of the HwIcap device.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+* @param	Data is the size in words.
+*
+* @return	None.
+*
+* @note		C-style Signature:
+*		void XHwIcap_SetSizeReg(XHwIcap *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XHwIcap_SetSizeReg(InstancePtr, Data) \
+	(XHwIcap_WriteReg(((InstancePtr)->HwIcapConfig.BaseAddress), \
+		XHI_SZ_OFFSET, (Data)))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the Control register.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+*
+* @return	A 32-bit value representing the contents of the Control
+*		register.
+*
+* @note		u32 XHwIcap_GetControlReg(XHwIcap *InstancePtr);
+*
+*****************************************************************************/
+#define XHwIcap_GetControlReg(InstancePtr) \
+ (XHwIcap_ReadReg(((InstancePtr)->HwIcapConfig.BaseAddress), XHI_CR_OFFSET))
+
+
+/****************************************************************************/
+/**
+*
+* Set the Control Register to initiate a configuration (write) to the device.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+*
+* @return	None.
+*
+* @note		C-style Signature:
+*		void XHwIcap_StartConfig(XHwIcap *InstancePtr);
+*
+*****************************************************************************/
+#define XHwIcap_StartConfig(InstancePtr) \
+ (XHwIcap_WriteReg(((InstancePtr)->HwIcapConfig.BaseAddress), XHI_CR_OFFSET, \
+ 	(XHwIcap_GetControlReg(InstancePtr) & 				      \
+ 	(~ XHI_CR_READ_MASK)) | XHI_CR_WRITE_MASK))
+
+
+/****************************************************************************/
+/**
+*
+* Set the Control Register to initiate a ReadBack from the device.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+*
+* @return	None.
+*
+* @note		C-style Signature:
+*		void XHwIcap_StartReadBack(XHwIcap *InstancePtr);
+*
+*****************************************************************************/
+#define XHwIcap_StartReadBack(InstancePtr) \
+ (XHwIcap_WriteReg(((InstancePtr)->HwIcapConfig.BaseAddress) , XHI_CR_OFFSET, \
+ 	(XHwIcap_GetControlReg(InstancePtr) & 				      \
+ 	(~ XHI_CR_WRITE_MASK)) | XHI_CR_READ_MASK))
+
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the status register.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+*
+* @return	A 32-bit value representing the contents of the status register.
+*
+* @note		u32 XHwIcap_GetStatusReg(XHwIcap *InstancePtr);
+*
+*****************************************************************************/
+#define XHwIcap_GetStatusReg(InstancePtr) \
+(XHwIcap_ReadReg(((InstancePtr)->HwIcapConfig.BaseAddress), XHI_SR_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the last Read/Write of the data to the Read/Write FIFO
+* of the HwIcap device is completed.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+*
+* @return
+*		- TRUE if the Read/Write to the FIFO's is completed.
+*		- FALSE if the Read/Write to the FIFO's is NOT completed..
+*
+* @note		C-Style signature:
+*		int XHwIcap_IsTransferDone(XHwIcap *InstancePtr);
+*
+*****************************************************************************/
+#define XHwIcap_IsTransferDone(InstancePtr)			\
+	((InstancePtr->IsTransferInProgress) ? FALSE : TRUE)
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the last Read/Write to the ICAP device in the FPGA
+* is completed.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+*
+* @return
+*		- TRUE if the last Read/Write(Config) to the ICAP is NOT
+*		completed.
+*		- FALSE if the Read/Write(Config) to the ICAP is completed..
+*
+* @note		C-Style signature:
+*		int XHwIcap_IsDeviceBusy(XHwIcap *InstancePtr);
+*
+*****************************************************************************/
+#define XHwIcap_IsDeviceBusy(InstancePtr)			\
+	((XHwIcap_GetStatusReg(InstancePtr) & XHI_SR_DONE_MASK) ? \
+				FALSE : TRUE)
+
+/*****************************************************************************/
+/**
+*
+* This macro enables the global interrupt in the Global Interrupt Enable
+* Register (GIER) so that the interrupt output from the HwIcap device is
+* enabled. Interrupts enabled using XHwIcap_IntrEnable() will not occur until
+* the global interrupt enable bit is set by using this macro.
+*
+* @param	InstancePtr is a pointer to the HwIcap instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XHwIcap_IntrGlobalEnable(InstancePtr)
+*
+******************************************************************************/
+#define XHwIcap_IntrGlobalEnable(InstancePtr)				\
+	XHwIcap_WriteReg((InstancePtr)->HwIcapConfig.BaseAddress,	\
+				XHI_GIER_OFFSET, XHI_GIER_GIE_MASK)
+
+/*****************************************************************************/
+/**
+*
+* This macro disables the global interrupt in the Global Interrupt Enable
+* Register (GIER) so that the interrupt output from the HwIcap device is
+* disabled.
+*
+* @param	InstancePtr is a pointer to the HwIcap instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XHwIcap_IntrGlobalDisable(InstancePtr)
+*
+******************************************************************************/
+#define XHwIcap_IntrGlobalDisable(InstancePtr)				\
+	XHwIcap_WriteReg((InstancePtr)->HwIcapConfig.BaseAddress,	\
+				XHI_GIER_OFFSET, 0x0)
+
+/*****************************************************************************/
+/**
+*
+* This macro returns the interrupt status read from Interrupt Status
+* Register(IPISR). Use the XHI_IPIXR_* constants defined in xhwicap_l.h
+* to interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the HwIcap instance.
+*
+* @return	The contents read from the Interrupt Status Register.
+*
+* @note		C-Style signature:
+*		u32 XHwIcap_IntrGetStatus(InstancePtr)
+*
+******************************************************************************/
+#define XHwIcap_IntrGetStatus(InstancePtr)				\
+	XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, 	\
+				XHI_IPISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This macro disables the specified interrupts in the Interrupt Enable
+* Register. It is non-destructive in that the register is read and only the
+* interrupts specified is changed.
+*
+* @param	InstancePtr is a pointer to the HwIcap instance.
+* @param	IntrMask is the bit-mask of the interrupts to be disabled.
+*		Bit positions of 1 will be disabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XHI_IPIXR_*_MASK bits defined in xhwicap_l.h.
+*
+* @return	None.
+*
+* @note		Signature:
+*		void XHwIcap_IntrDisable(XHwIcap *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XHwIcap_IntrDisable(InstancePtr, IntrMask)           \
+XHwIcap_WriteReg((InstancePtr)->HwIcapConfig.BaseAddress, 	\
+			XHI_IPIER_OFFSET, \
+	XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, \
+		XHI_IPIER_OFFSET) & (~ (IntrMask & XHI_IPIXR_ALL_MASK)));\
+		(InstancePtr)->IsPolled = TRUE;
+
+/*****************************************************************************/
+/**
+*
+* This macro enables the specified interrupts in the Interrupt Enable
+* Register. It is non-destructive in that the register is read and only the
+* interrupts specified is changed.
+*
+* @param	InstancePtr is a pointer to the HwIcap instance.
+* @param	IntrMask is the bit-mask of the interrupts to be enabled.
+*		Bit positions of 1 will be enabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XHI_IPIXR_*_MASK bits defined in xhwicap_l.h.
+*
+* @return	None.
+*
+* @note		Signature:
+*		void XHwIcap_IntrEnable(XHwIcap *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XHwIcap_IntrEnable(InstancePtr, IntrMask) \
+	XHwIcap_WriteReg((InstancePtr)->HwIcapConfig.BaseAddress, 	\
+			XHI_IPIER_OFFSET, \
+	(XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, \
+		XHI_IPIER_OFFSET) | ((IntrMask) & XHI_IPIXR_ALL_MASK))); \
+		(InstancePtr)->IsPolled = FALSE;
+
+/*****************************************************************************/
+/**
+*
+* This macro returns the interrupt status read from Interrupt Enable
+* Register(IIER). Use the XHI_IPIXR_* constants defined in xhwicap_l.h
+* to interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the HwIcap instance.
+*
+* @return	The contents read from the Interrupt Enable Register.
+*
+* @note		C-Style signature:
+*		u32 XHwIcap_IntrGetEnabled(InstancePtr)
+*
+******************************************************************************/
+#define XHwIcap_IntrGetEnabled(InstancePtr)				\
+	XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, 	\
+			XHI_IPIER_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This macro clears the specified interrupts in the Interrupt Status
+* Register (IPISR).
+*
+* @param	InstancePtr is a pointer to the HwIcap instance.
+* @param	IntrMask contains the interrupts to be cleared.
+*
+* @return	None.
+*
+* @note		Signature:
+*		void XHwIcap_DisableIntr(XHwIcap *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XHwIcap_IntrClear(InstancePtr, IntrMask)           \
+	XHwIcap_WriteReg((InstancePtr)->HwIcapConfig.BaseAddress, 	\
+			XHI_IPISR_OFFSET, \
+		XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, \
+		XHI_IPISR_OFFSET) | ((IntrMask) & XHI_IPIXR_ALL_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This macro returns the vacancy of the Write FIFO. This indicates the
+* number of words that can be written to the Write FIFO before it becomes
+* full.
+*
+* @param	InstancePtr is a pointer to the HwIcap instance.
+*
+* @return	The contents read from the Write FIFO Vacancy Register.
+*
+* @note		C-Style signature:
+*		u32 XHwIcap_GetWrFifoVacancy(InstancePtr)
+*
+******************************************************************************/
+#define XHwIcap_GetWrFifoVacancy(InstancePtr)				\
+ XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, XHI_WFV_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This macro returns the occupancy  of the Read FIFO.
+*
+* @param	InstancePtr is a pointer to the HwIcap instance.
+*
+* @return	The contents read from the Read FIFO Occupancy Register.
+*
+* @note		C-Style signature:
+*		u32 XHwIcap_GetRdFifoOccupancy(InstancePtr)
+*
+******************************************************************************/
+#define XHwIcap_GetRdFifoOccupancy(InstancePtr)		\
+ XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, XHI_RFO_OFFSET)
+
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* If Virtex4 device */
+
+/****************************************************************************/
+/**
+*
+* Converts a CLB SliceX coordinate to a column coordinate used by the
+* XHwIcap_GetClbBits and XHwIcap_SetClbBits functions.
+*
+* @param	SliceX - the SliceX coordinate to be converted
+*
+* @return	Column
+*
+* @note		C-style Signature:
+*		u32 XHwIcap_SliceX2Col(u32 SliceX);
+*
+*****************************************************************************/
+#define XHwIcap_SliceX2Col(SliceX) \
+	( (SliceX >> 1) + 1)
+
+/****************************************************************************/
+/**
+*
+* Converts a CLB SliceY coordinate to a row coordinate used by the
+* XHwIcap_GetClbBits and XHwIcap_SetClbBits functions.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+* @param	SliceY - the SliceY coordinate to be converted
+* @return	Row
+*
+* @note		C-style Signature:
+*		u32 XHwIcap_SliceY2Row(XHwIcap *InstancePtr, u32 SliceY);
+*
+*****************************************************************************/
+#define XHwIcap_SliceY2Row(InstancePtr, SliceY) \
+	( (InstancePtr)->Rows - (SliceY >> 1) )
+
+/****************************************************************************/
+/**
+*
+* Figures out which slice in a CLB is targeted by a given
+* (SliceX,SliceY) pair.  This slice value is used for indexing in
+* resource arrays.
+*
+* @param	SliceX - the SliceX coordinate to be converted
+* @param	SliceY - the SliceY coordinate to be converted
+*
+* @return	Slice index
+*
+* @note		C-style Signature:
+*		u32 XHwIcap_SliceXY2Slice(u32 SliceX, u32 SliceY);
+*
+*****************************************************************************/
+#define XHwIcap_SliceXY2Slice(SliceX,SliceY) \
+	( ((SliceX % 2) << 1) + (SliceY % 2) )
+
+#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6)\
+|| (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+/****************************************************************************/
+/**
+*
+* Converts a CLB SliceX coordinate to a column coordinate used by the
+* XHwIcap_GetClbBits and XHwIcap_SetClbBits functions.
+*
+* @param	SliceX - the SliceX coordinate to be converted
+*
+* @return	Column
+*
+* @note		C-style Signature:
+*		u32 XHwIcap_SliceX2Col(u32 SliceX);
+*
+*****************************************************************************/
+#define XHwIcap_SliceX2Col(SliceX) \
+	( ((SliceX) >> 1) + 1)
+
+/****************************************************************************/
+/**
+*
+* Converts a CLB SliceY coordinate to a row coordinate used by the
+* XHwIcap_GetClbBits and XHwIcap_SetClbBits functions.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+* @param	SliceY - the SliceY coordinate to be converted
+* @return	Row
+*
+* @note		C-style Signature:
+*		u32 XHwIcap_SliceY2Row(XHwIcap *InstancePtr, u32 SliceY);
+*
+*****************************************************************************/
+#define XHwIcap_SliceY2Row(InstancePtr, SliceY) \
+	((InstancePtr)->Rows - (SliceY))
+
+/****************************************************************************/
+/**
+*
+* Figures out which slice in a CLB is targeted by a given
+* (SliceX,SliceY) pair.  This slice value is used for indexing in
+* resource arrays.
+*
+* @param	SliceX - the SliceX coordinate to be converted
+* @param	SliceY - the SliceY coordinate to be converted
+*
+* @return	Slice index
+*
+* @note		C-style Signature:
+*		u32 XHwIcap_SliceXY2Slice(u32 SliceX, u32 SliceY);
+*
+*****************************************************************************/
+#define XHwIcap_SliceXY2Slice(SliceX,SliceY) \
+	((SliceX) % 2)
+
+#endif
+/************************** Function Prototypes *****************************/
+
+/*
+ * Functions in the xhwicap.c
+ */
+int XHwIcap_CfgInitialize(XHwIcap *InstancePtr, XHwIcap_Config *ConfigPtr,
+				u32 EffectiveAddr);
+
+#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+int XHwIcap_DeviceWrite(XHwIcap *InstancePtr, u16 *FrameBuffer, u32 NumWords);
+int XHwIcap_DeviceRead(XHwIcap *InstancePtr, u16 *FrameBuffer, u32 NumWords);
+#else
+int XHwIcap_DeviceWrite(XHwIcap *InstancePtr, u32 *FrameBuffer, u32 NumWords);
+int XHwIcap_DeviceRead(XHwIcap *InstancePtr, u32 *FrameBuffer, u32 NumWords);
+#endif
+void XHwIcap_Reset(XHwIcap *InstancePtr);
+void XHwIcap_FlushFifo(XHwIcap *InstancePtr);
+void XHwIcap_Abort(XHwIcap *InstancePtr);
+
+/*
+ * Functions in xhwicap_sinit.c.
+ */
+XHwIcap_Config *XHwIcap_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions in the xhwicap_srp.c
+ */
+int XHwIcap_CommandDesync(XHwIcap *InstancePtr);
+int XHwIcap_CommandCapture(XHwIcap *InstancePtr);
+u32 XHwIcap_GetConfigReg(XHwIcap *InstancePtr, u32 ConfigReg, u32 *RegData);
+
+/*
+ *  Function in xhwicap_selftest.c
+ */
+ int XHwIcap_SelfTest(XHwIcap *InstancePtr);
+
+/*
+ *  Function in xhwicap_intr.c
+ */
+void XHwIcap_IntrHandler(void *InstancePtr);
+void XHwIcap_SetInterruptHandler(XHwIcap * InstancePtr, void *CallBackRef,
+			   XHwIcap_StatusHandler FuncPtr);
+
+/*
+ * Functions in the xhwicap_device_read_frame.c
+ */
+#if (XHI_FAMILY != XHI_DEV_FAMILY_S6)
+int XHwIcap_DeviceReadFrame(XHwIcap *InstancePtr, long Top,
+				long Block, long HClkRow,
+				long MajorFrame, long MinorFrame,
+				u32 *FrameBuffer);
+
+/*
+ * Functions in the xhwicap_device_write_frame.c
+ */
+int XHwIcap_DeviceWriteFrame(XHwIcap *InstancePtr, long Top,
+				long Block, long HClkRow,
+				long MajorFrame, long MinorFrame,
+				u32 *FrameData);
+
+#else
+int XHwIcap_DeviceReadFrame(XHwIcap *InstancePtr, long Block, long Row,
+				long MajorFrame, long MinorFrame,
+				u16 *FrameBuffer);
+/*
+ * Functions in the xhwicap_device_write_frame.c
+ */
+int XHwIcap_DeviceWriteFrame(XHwIcap *InstancePtr, long Block, long Row,
+				long MajorFrame, long MinorFrame,
+				u16 *FrameData);
+
+#endif
+
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* If Virtex4 device */
+#define XHwIcap_SetClbBits XHwIcap_SetClbBitsV4
+#define XHwIcap_GetClbBits XHwIcap_GetClbBitsV4
+
+#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6))
+		/* If Virtex5 or Virtex6 device */
+#define XHwIcap_SetClbBits XHwIcap_SetClbBitsV5
+#define XHwIcap_GetClbBits XHwIcap_GetClbBitsV5
+#endif
+
+
+/****************************************************************************/
+/**
+*
+* Sets bits contained in a Center tile specified by the CLB row and col
+* coordinates.  The coordinate system lables the upper left CLB as
+* (1,1).
+*
+* @param	InstancePtr is a pointer to XHwIcap instance to be worked on
+* @param	Row is the CLB row. (1,1) is the upper left CLB.
+* @param	Col is the CLB col. (1,1) is the upper left CLB.
+* @param	Resource is the Target bits (first dimension length will be
+*		the number of bits to set and must match the numBits parameter)
+*		(second dimension contains two value -- one for
+*		 minor row and one for col information from within
+*		the Center tile targetted by the above row and
+*		col coords).
+* @param	Value is the values to set each of the targets bits to.
+*		The size of this array must be euqal to NumBits.
+* @param	NumBits is the number of Bits to change in this method.
+*
+* @return	XST_SUCCESS, XST_BUFFER_TOO_SMALL or XST_INVALID_PARAM.
+*
+* @note		The source code for this function is not included. This
+*		function is delivered as .o file. Libgen uses the appropriate
+*		.o file for the target processor.
+*
+*****************************************************************************/
+int XHwIcap_SetClbBits(XHwIcap *InstancePtr, long Row, long Col,
+		const u8 Resource[][2], const u8 Value[], long NumBits);
+
+/****************************************************************************/
+/**
+*
+* Gets bits contained in a Center tile specified by the CLB row and col
+* coordinates.  The coordinate system lables the upper left CLB as
+* (1,1).
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+* @param	Row is the CLB row. (1,1) is the upper left CLB.
+* @param	Col is the CLB col. (1,1) is the upper left CLB.
+* @param	Resource is the Target bits (first dimension length will be
+*		the number of bits to set and must match the numBits parameter)
+*		(second dimension contains two value -- one for
+*		 minor row and one for col information from within
+*		the Center tile targetted by the above row and
+*		col coords).
+* @param	Value is the values to set each of the targets bits to.
+*		The size of this array must be euqal to NumBits.
+* @param	NumBits is the number of Bits to change in this method.
+*
+* @return	XST_SUCCESS, XST_BUFFER_TOO_SMALL or XST_INVALID_PARAM.
+*
+* @note		The source code for this function is not included. This
+*		function is delivered as .o file.  Libgen uses the appropriate
+*		.o file for the target processor.
+*
+*****************************************************************************/
+int XHwIcap_GetClbBits(XHwIcap *InstancePtr, long Row, long Col,
+      const u8 Resource[][2], u8 Value[], long NumBits);
+
+
+/************************** Variable Declarations ***************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_clb_ff.h b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_clb_ff.h
new file mode 100755
index 00000000..b7df2aba
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_clb_ff.h
@@ -0,0 +1,531 @@
+/******************************************************************************
+*
+* Copyright (C) 2007 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_clb_ff.h
+*
+* This header file contains bit information about the CLB FF resource.
+* This header file can be used with the XHwIcap_GetClbBits() and
+* XHwIcap_SetClbBits() functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb  11/14/03 First release
+* 1.01a bjb  04/10/06 V4 Support
+* 2.00a ecm  10/20/07 V5 Support
+* </pre>
+*
+*****************************************************************************/
+#ifndef XHWICAP_CLB_FF_H_  /* prevent circular inclusions */
+#define XHWICAP_CLB_FF_H_  /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
+/************************** Constant Definitions ****************************/
+
+/**
+ * Index into the CONTENTS and SRMODE for XQ Register.
+ */
+#define XHI_CLB_XQ 0
+
+/**
+ * Index into the CONTENTS and SRMODE for YQ Register.
+ */
+#define XHI_CLB_YQ 1
+
+/**************************** Type Definitions ******************************/
+
+typedef struct  {
+
+	/**
+	 * MODE values.
+	 */
+	const u8 LATCH[1];  /**< Value to put register into LATCH mode */
+	const u8 FF[1];     /**< Value to put register into FF mode */
+
+	/**
+	 * CONTENTS values.
+	 */
+	const u8 INIT0[1];  /**< Value to initialize register CONTENTS to 0 */
+	const u8 INIT1[1];  /**< Value to initialize register CONTENTS to 1 */
+	const u8 ZERO[1];   /**< Same as INIT0 */
+	const u8 ONE[1];    /**< Same as INIT1 */
+
+	/**
+	 * SRMODE values.
+	 */
+	const u8 SRLOW[1];  /**< When SR is asserted register goes to 0-Reset */
+	const u8 SRHIGH[1]; /**< When SR is asserted register goes to 1-Set */
+
+	/**
+	 * SYNCMODE values.
+	 */
+	const u8 SYNC[1];  /**< Puts XQ and YQ in synchronous set/reset mode */
+	const u8 ASYNC[1]; /**< Puts XQ and YQ in asynchronous set/reset mode */
+
+	/**
+	 * LATCH or FF mode.  Indexed by slice (0-3) only.
+	 * It affects both XQ and YQ registers.
+	 */
+	const u8 MODE[4][1][2];
+
+	/**
+	 * SYNC or ASYNC mode.  Indexed by slice (0-3) only.
+	 * It affects both  XQ and YQ registers.
+	 */
+	const u8 SYNCMODE[4][1][2];
+
+	/**
+	 * INIT0, INIT1, ONE, or ZERO.  Indexed by the slice basis (0-3).
+	 * And then indexed by the element (XHI_CLB_XQ or XHI_CLB_YQ).
+	 * INIT0 and ZERO are equivalent as well as INIT1 and ONE.  There
+	 * are two values there only as to not confuse the values given in
+	 * FPGA_EDITOR which are INIT0 and INIT1.  They both can either
+	 * initialize or directly set the Register contents (assuming a
+	 * GRESTORE packet command is used after doing a configuration on a
+	 * device).
+	 */
+	const u8 CONTENTS[4][2][1][2];
+
+	/**
+	 * SRHIGH or SRLOW.  Indexed by the slice (0-3).
+	 * And then indexed by the element (XHI_CLB_XQ or XHI_CLB_YQ)
+	 */
+	const u8 SRMODE[4][2][1][2];
+
+} XHwIcap_ClbFf;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/************************** Variable Definitions ****************************/
+
+/***************************************************************************/
+
+/**
+ *  This structure defines the bits associated with a Flip Flop in a CLB
+ *  tile. Note that there are 8 FFs, the XQ and YQ Registers in
+ *  Slice 0, 1, 2 and 3.
+ */
+const XHwIcap_ClbFf XHI_CLB_FF =
+{
+	{1}, 	/* LATCH*/
+	{0}, 	/* FF*/
+	{1}, 	/* INIT0*/
+	{0},	/* INIT1*/
+	{1}, 	/* ZERO*/
+	{0}, 	/* ONE*/
+	{1}, 	/* SRLOW*/
+	{0},	/* SRHIGH*/
+	{1},	/* SYNC*/
+	{0},	/* ASYNC*/
+	/* MODE*/
+	{
+		/* Slice 0. */
+		{
+			{10, 20}
+		},
+		/* Slice 1. */
+		{
+			{50, 20}
+		},
+		/* Slice 2. */
+		{
+			{22, 20}
+		},
+		/* Slice 3. */
+		{
+			{62, 20}
+		}
+	},
+	/* SYNCMODE*/
+	{
+		/* Slice 0. */
+		{
+			 {26, 20}
+		},
+		/* Slice 1. */
+		{
+			 {66, 20}
+		},
+		/* Slice 2. */
+		{
+			 {25, 20}
+		},
+		/* Slice 3. */
+		{
+			 {65, 20}
+		}
+	},
+	/* CONTENTS*/
+	{
+		/* Slice 0. */
+		{
+			/* LE 0. */
+			{
+				{6, 20}
+			},
+			/* LE 1. */
+			{
+				{34, 20}
+			}
+		},
+		/* Slice 1. */
+		{
+			/* LE 0. */
+			{
+				{46, 20}
+			},
+			/* LE 1. */
+			{
+				{74, 20}
+			}
+		},
+		/* Slice 2. */
+		{
+			/* LE 0. */
+			{
+				{5, 20}
+			},
+			/* LE 1. */
+			{
+				{33, 20}
+			}
+		},
+		/* Slice 3. */
+		{
+			/* LE 0. */
+			 {
+			    {45, 20}
+			 },
+			 /* LE 1. */
+			 {
+			    {73, 20}
+			 }
+		}
+	},
+	/* SRMODE*/
+	{
+		/* Slice 0. */
+		{
+			/* LE 0. */
+			{
+				{0, 20}
+			},
+			/* LE 1. */
+			{
+				{30, 20}
+			}
+		},
+		/* Slice 1. */
+		{
+			/* LE 0. */
+			{
+				{42, 20}
+			},
+			/* LE 1. */
+			{
+				{70, 20}
+			}
+		},
+		/* Slice 2. */
+		{
+			/* LE 0. */
+			{
+				{1, 20}
+			},
+			/* LE 1. */
+			{
+				{29, 20}
+			}
+		},
+		/* Slice 3. */
+		{
+			/* LE 0. */
+			{
+				{41, 20}
+			},
+			/* LE 1. */
+			{
+				{69, 20}
+			}
+		}
+	},
+
+};
+#elif XHI_FAMILY == XHI_DEV_FAMILY_V5 /* Virtex5 */
+
+/************************** Constant Definitions ****************************/
+
+/**
+ * Index into the CONTENTS and SRMODE for {A...D}Q Register.
+ */
+#define XHI_CLB_AQ 0
+#define XHI_CLB_BQ 1
+#define XHI_CLB_CQ 2
+#define XHI_CLB_DQ 3
+
+
+/**************************** Type Definitions ******************************/
+
+typedef struct  {
+
+	/**
+	 * MODE values.
+	 */
+	const u8 LATCH[1];  /**< Value to put register into LATCH mode */
+	const u8 FF[1];     /**< Value to put register into FF mode */
+
+	/**
+	 * CONTENTS values.
+	 */
+	const u8 INIT0[1];  /**< Value to initialize register CONTENTS to 0 */
+	const u8 INIT1[1];  /**< Value to initialize register CONTENTS to 1 */
+	const u8 ZERO[1];   /**< Same as INIT0 */
+	const u8 ONE[1];    /**< Same as INIT1 */
+
+	/**
+	 * SRMODE values.
+	 */
+	const u8 SRLOW[1];  /**< When SR is asserted register goes to 0-Reset */
+	const u8 SRHIGH[1]; /**< When SR is asserted register goes to 1-Set */
+
+	/**
+	 * SYNCMODE values.
+	 */
+	const u8 SYNC[1];  /**< Puts XQ and YQ in synchronous set/reset mode */
+	const u8 ASYNC[1]; /**< Puts XQ and YQ in asynchronous set/reset mode */
+
+	/**
+	 * LATCH or FF mode.  Indexed by slice (0-1) only.
+	 * It affects both XQ and YQ registers.
+	 */
+	const u8 MODE[2][4][2];
+
+	/**
+	 * SYNC or ASYNC mode.  Indexed by slice (0-1) only.
+	 * It affects both  XQ and YQ registers.
+	 */
+	const u8 SYNCMODE[2][4][2];
+
+	/**
+	 * [type slice, L/M][num LUTS,4][num configs, 4]
+	 * INIT0, INIT1, ONE, or ZERO.  Indexed by the slice basis (0-1).
+	 * And then indexed by the element (XHI_CLB_AQ .. XHI_CLB_DQ).
+	 * INIT0 and ZERO are equivalent as well as INIT1 and ONE.  There
+	 * are two values there only as to not confuse the values given in
+	 * FPGA_EDITOR which are INIT0 and INIT1.  They both can either
+	 * initialize or directly set the Register contents (assuming a
+	 * GRESTORE packet command is used after doing a configuration on a
+	 * device).
+	 */
+	const u8 CONTENTS[2][4][1][2];
+
+	/**
+	 * [type slice, L/M][num LUTs 4][mode]
+	 * SRHIGH or SRLOW.  Indexed by the slice (0-3).
+	 * And then indexed by the element (XHI_CLB_AQ ... XHI_CLB_DQ)
+	 */
+	const u8 SRMODE[2][4][1][2];
+
+} XHwIcap_ClbFf;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/************************** Variable Definitions ****************************/
+
+/***************************************************************************/
+
+/**
+ *  This structure defines the bits associated with a Flip Flop in a CLB
+ *  tile. Note that there are 8 FFs, the XQ and YQ Registers in
+ *  Slice 0, 1, 2 and 3.
+ */
+
+const XHwIcap_ClbFf XHI_CLB_FF =
+{
+	{1}, 	/* LATCH*/
+	{0}, 	/* FF*/
+	{1}, 	/* INIT0*/
+	{0},	/* INIT1*/
+	{1}, 	/* ZERO*/
+	{0}, 	/* ONE*/
+	{1}, 	/* SRLOW*/
+	{0},	/* SRHIGH*/
+	{1},	/* SYNC*/
+	{0},	/* ASYNC*/
+	/* MODE*/
+	{
+		/* Slice 0. */
+		{
+			{0, 0},
+			{0, 0},
+			{0, 0},
+			{0, 0}
+		},
+		/* Slice 1. */
+		{
+			{0, 0},
+			{0, 0},
+			{0, 0},
+			{0, 0}
+
+		}
+	},
+	/* SYNCMODE*/
+	{
+		/* Slice 0. */
+		{
+			 {6, 0},
+			 {6, 0},
+			 {6, 0},
+			 {6, 0}
+		},
+		/* Slice 1. */
+		{
+			 {6, 0},
+			 {6, 0},
+			 {6, 0},
+			 {6, 0}
+		}
+	},
+	/* CONTENTS*/
+	{
+		/* Slice 0. */
+		{
+			/* LE 0. */
+			{
+				{6, 20}
+			},
+			/* LE 1. */
+			{
+				{6, 20}
+			},
+			/* LE 2. */
+			{
+				{6, 20}
+			},
+			/* LE 3. */
+			{
+				{6, 20}
+			}
+		},
+		/* Slice 1. */
+		{
+			/* LE 0. */
+			{
+				{6, 20}
+			},
+			/* LE 1. */
+			{
+				{6, 20}
+			},
+			/* LE 2. */
+			{
+				{6, 20}
+			},
+			/* LE 3. */
+			{
+				{4, 20}
+			}
+		}
+	},
+	/* SRMODE*/
+	{
+		/* Slice 0. */
+		{
+			/* LE 0. */
+			{
+				{0, 20}
+			},
+			/* LE 1. */
+			{
+				{0, 20}
+			},
+			/* LE 2. */
+			{
+				{0, 20}
+			},
+			/* LE 3. */
+			{
+				{0, 20}
+			}
+		},
+		/* Slice 1. */
+		{
+			/* LE 0. */
+			{
+				{2, 20}
+			},
+			/* LE 1. */
+			{
+				{2, 20}
+			},
+			/* LE 2. */
+			{
+				{2, 20}
+			},
+			/* LE 3. */
+			{
+				{0, 20}
+			}
+		}
+	},
+
+};
+
+#else
+
+#error Unsupported FPGA Family
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_clb_lut.h b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_clb_lut.h
new file mode 100755
index 00000000..14774709
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_clb_lut.h
@@ -0,0 +1,909 @@
+/******************************************************************************
+*
+* Copyright (C) 2003 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_clb_lut.h
+*
+* This header file contains bit information about the CLB LUT resource.
+* This header file can be used with the XHwIcap_GetClbBits() and
+* XHwIcap_SetClbBits() functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb  11/14/03 First release
+* 1.01a bjb  04/10/06 V4 Support
+* 2.00a ecm  10/20/07 V5 Support
+* 4.00a hvm  11/13/09 V6 Support
+* </pre>
+*
+*****************************************************************************/
+#ifndef XHWICAP_CLB_LUT_H_  /* prevent circular inclusions */
+#define XHWICAP_CLB_LUT_H_  /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
+
+/************************** Constant Definitions ****************************/
+
+/**
+ * Index into SLICE and MODE for F LUT.
+ */
+#define XHI_CLB_LUT_F 0
+
+/**
+ * Index into SLICE and MODE for G LUT.
+ */
+#define XHI_CLB_LUT_G 1
+
+/**************************** Type Definitions ******************************/
+
+
+typedef struct {
+	/**
+	 * MODE resource values.
+	 */
+	const u8 LUT_MODE[1];	/**< Set MODE to LUT mode */
+	const u8 ROM_MODE[1];	/**< Set MODE to ROM mode.
+					  * (Same as LUT mode) */
+	const u8 RAM_MODE[1];	/**< Set MODE to RAM mode. */
+
+	/**
+	 * CONFIG resource values.
+	 */
+	const u8 SHIFT_CONFIG[2];	/**< Set CONFIG to shfiter. */
+	const u8 RAM_CONFIG[2];	/**< Set CONFIG to ram. */
+	const u8 LUT_CONFIG[2];	/**< Set CONFIG to LUT. */
+
+	/**
+	 * RAM_MODE, ROM_MODE, or LUT_MODE.  Indexed by the slice (0-3).  If
+	 * only one LUT is in RAM or SHIFT mode, it MUST be the G LUT.
+	 */
+	const u8 MODE[4][1][2];
+
+	/**
+	 * SHIFT_CONFIG, RAM_CONFIG, or LUT_CONFIG.  Indexed by the slice
+	 * (0-3).  And then indexed by the logic element (LUT.F or LUT.G).
+	 * Note that if the F LUT is in any sort of ram or shifter modes,
+	 * the G LUT must also be in ram or shifter mode.  Also, be sure to
+	 * set the MODE bit appropriately.
+	 */
+	const u8 CONFIG[4][2][2][2];
+
+	/**
+	 * LUT memory contents. Indexed by slice first (0-3) and by
+	 * XHI_CLB_LUT_F or XHI_CLB_LUT_G second.
+	 */
+	const u8 CONTENTS[4][2][16][2];
+
+} XHwIcap_ClbLut;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*  This structure defines the Look Up Tables, or <em>LUTs</em>.
+*  in the Virtex4 CLB.  Note that there are 8 16-bit
+*  LUTs, the F and G LUTs in Slice 0, 1, 2 and 3.  These
+*  LUTs can take any arbitrary bit pattern.
+*
+*  <p>
+*
+*  Note, that DUAL_PORT mode cannot be configured here.  Thats because
+*  it is essentially always in effect. But, it can only be used in the top
+*  two slices (2 and 3) using the address lines from the bottom
+*  two slices (0 and 1) for the write address. Although you can technically
+*  put the bottom two slice LUTs in dual port mode in the fpga_editor,
+*  the read and write addresses will always be the same.  This is
+*  different from the Virtex where the two LUTs in a slice were
+*  combined to make a dual port RAM.  In Virtex4, every LUT is
+*  dual ported, but only the top two have different read/write
+*  addresses.
+*
+***************************************************************************/
+const XHwIcap_ClbLut XHI_CLB_LUT =
+{
+
+	{0},    /* LUT_MODE*/
+	{0},    /* ROM_MODE*/
+	{1},    /* RAM_MODE*/
+	{0,1},  /* SHIFT_CONFIG*/
+	{1,0}, 	/* RAM_CONFIG*/
+	{0,0}, 	/* LUT_CONFIG*/
+	/* MODE*/
+	{
+		/* Slice 0. */
+		{
+			{38, 20}
+		},
+		/* Slice 1. */
+		{
+			{79, 20}
+		},
+		/* Slice 2. */
+		{
+			/* No MODE for SLICE_L's, LUT only. */
+		},
+		/* Slice 3. */
+		{
+			/* No MODE for SLICE_L's, LUT only. */
+		}
+	},
+	/* CONFIG*/
+	{
+		/* Slice 0. */
+		{
+		 	/* LE 0. */
+		 	{
+		 		{8, 20}, {37, 20}
+		 	},
+		 	/* LE 1. */
+		 	{
+				{7, 20}, {36, 20}
+		 	}
+		},
+		/* Slice 1. */
+		{
+			 /* LE 0. */
+			{
+				{48, 20}, {78, 20}
+	 		},
+			 /* LE 1. */
+			{
+				{40, 20}, {78, 20}
+			}
+		},
+		/* Slice 2. */
+		{
+		 	/* LE 0. */
+		 	{
+		 	 /* No CONFIG for SLICE_L's, LUT only. */
+		 	},
+		 	/* LE 1. */
+		 	{
+		 	 /* No CONFIG for SLICE_L's, LUT only. */
+		 	}
+		},
+		/* Slice 3. */
+		{
+		 	/* LE 0. */
+		 	{
+		 	 /* No CONFIG for SLICE_L's, LUT only. */
+		 	},
+		 	/* LE 1. */
+		 	{
+		 	 /* No CONFIG for SLICE_L's, LUT only. */
+		 	}
+		}
+	},
+	/* CONTENTS*/
+	{
+		/* Slice 0. */
+		{
+		 	/* LE 0. */
+			{
+				{15, 21}, {14, 21}, {13, 21}, {12, 21},
+				{11, 21}, {10, 21}, {9, 21}, {8, 21},
+				{7, 21}, {6, 21}, {5, 21}, {4, 21},
+				{3, 21}, {2, 21}, {1, 21}, {0, 21}
+			},
+			/* LE 1. */
+			{
+				{38, 21}, {37, 21}, {36, 21}, {35, 21},
+				{34, 21}, {33, 21}, {32, 21}, {31, 21},
+				{30, 21}, {29, 21}, {28, 21}, {27, 21},
+				{26, 21}, {25, 21}, {24, 21}, {23, 21}
+			}
+		},
+		/* Slice 1. */
+		{
+			 /* LE 0. */
+			 {
+				{55, 21}, {54, 21}, {53, 21}, {52, 21},
+				{51, 21}, {50, 21}, {49, 21}, {48, 21},
+				{47, 21}, {46, 21}, {45, 21}, {44, 21},
+				{43, 21}, {42, 21}, {41, 21}, {40, 21}
+			 },
+			/* LE 1. */
+			{
+				{78, 21}, {77, 21}, {76, 21}, {75, 21},
+				{74, 21}, {73, 21}, {72, 21}, {71, 21},
+				{70, 21}, {69, 21}, {68, 21}, {67, 21},
+				{66, 21}, {65, 21}, {64, 21}, {63, 21}
+			}
+		},
+		/* Slice 2. */
+		{
+			 /* LE 0. */
+			 {
+				{15, 19}, {14, 19}, {13, 19}, {12, 19},
+				{11, 19}, {10, 19}, {9, 19}, {8, 19},
+				{7, 19}, {6, 19}, {5, 19}, {4, 19},
+				{3, 19}, {2, 19}, {1, 19}, {0, 19}
+			 },
+			 /* LE 1. */
+			 {
+				{38, 19}, {37, 19}, {36, 19}, {35, 19},
+				{34, 19}, {33, 19}, {32, 19}, {31, 19},
+				{30, 19}, {29, 19}, {28, 19}, {27, 19},
+				{26, 19}, {25, 19}, {24, 19}, {23, 19}
+			 }
+		},
+		/* Slice 3. */
+		{
+			/* LE 0. */
+			{
+				{55, 19}, {54, 19}, {53, 19}, {52, 19},
+				{51, 19}, {50, 19}, {49, 19}, {48, 19},
+				{47, 19}, {46, 19}, {45, 19}, {44, 19},
+				{43, 19}, {42, 19}, {41, 19}, {40, 19}
+			},
+		 	/* LE 1. */
+		 	{
+				{78, 19}, {77, 19}, {76, 19}, {75, 19},
+				{74, 19}, {73, 19}, {72, 19}, {71, 19},
+				{70, 19}, {69, 19}, {68, 19}, {67, 19},
+				{66, 19}, {65, 19}, {64, 19}, {63, 19}
+		 	}
+		}
+	},
+
+};
+
+#elif XHI_FAMILY == XHI_DEV_FAMILY_V5 /* Virtex5 */
+
+/************************** Constant Definitions ****************************/
+
+/**
+ * Index into SLICE and MODE for TYPE, L or M.
+ */
+#define XHI_CLB_TYPE_L 0
+#define XHI_CLB_TYPE_M 1
+
+
+/**
+ * Index into SLICE and MODE for LUT A...D.
+ */
+#define XHI_CLB_LUT_A 0
+#define XHI_CLB_LUT_B 1
+#define XHI_CLB_LUT_C 2
+#define XHI_CLB_LUT_D 3
+
+
+/**************************** Type Definitions ******************************/
+
+typedef struct {
+	/**
+	 * MODE resource values.
+	 */
+	const u8 LUT_MODE[1];	/**< Set MODE to LUT mode */
+	const u8 ROM_MODE[1];	/**< Set MODE to ROM mode.
+					  * (Same as LUT mode) */
+	const u8 RAM_MODE[1];	/**< Set MODE to RAM mode. */
+
+	/**
+	 * CONFIG resource values.
+	 */
+	const u8 SHIFT_CONFIG16[2];	/**< Set CONFIG to shifter SRL16 */
+	const u8 SHIFT_CONFIG32[2];	/**< Set CONFIG to shifter SRL32 */
+	const u8 RAM_CONFIG_SP[2];	/**< Set CONFIG to ram, single port,
+						64/32. */
+	const u8 RAM_CONFIG_DP[2];	/**< Set CONFIG to ram. dual port,
+						64/32.*/
+	const u8 LUT_CONFIG[2];		/**< Set CONFIG to LUT. */
+
+	/**
+	 * [num slice, 0/1{L/M}][num LUTS,4][(lut/ram)/srl]
+	 * RAM_MODE, ROM_MODE, or LUT_MODE.  Indexed by the slice (0,1).
+	 */
+	const u8 MODE[2][4][2][2];
+
+	/**
+	 * [type slice, L/M][num LUTS,4][num configs, 4]
+	 * SHIFT_CONFIG, RAM_CONFIG, or LUT_CONFIG.  Indexed by the slice
+	 * (0-1).  And then indexed by the LUT number (A=0 ... D=3).
+	 */
+	const u8 CONFIG[2][4][4][2];
+
+	/**
+	 * [type slice, L/M][num LUTs 4][contents]
+	 * LUT memory contents. Indexed by slice first (0-1) and by
+	 * LUT number {A=0...D=3}.
+	 */
+	const u8 CONTENTS[2][4][64][2];
+
+} XHwIcap_ClbLut;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*  This structure defines the Look Up Tables, or <em>LUTs</em>.
+*  in the Virtex5 CLB.  Note that there are 8 16-bit
+*  LUTs, the L and M LUTs in Slice 0, and 1.  These
+*  LUTs can take any arbitrary bit pattern.
+*
+*
+*
+***************************************************************************/
+
+const XHwIcap_ClbLut XHI_CLB_LUT =
+{
+   /* LUT_MODE*/
+   {0},
+   /* ROM_MODE*/
+   {0},
+   /* RAM_MODE*/
+   {1},
+   /* SHIFT_CONFIG 16 */
+   {4, 1},
+   /* SHIFT_CONFIG 32 */
+   {4,  1},
+   /* RAM_CONFIG SP */
+   {4,  1},
+   /* RAM_CONFIG DP */
+   {4,  1},
+   /* LUT_CONFIG*/
+   {4,  1},
+   /* MODE*/
+   {
+      /* Type 0, Slice  L.*/
+      {
+         /* LE 0. LUTA, LUT/RAM mode, SRL mode */
+         {
+            {4,  1}, {5, 1}
+         },
+         /* LE 1. LUTB LUT/RAM mode, SRL mode */
+         {
+            {4,  15}, {5, 13}
+         },
+         /* LE 2. LUTC LUT/RAM mode, SRL mode */
+         {
+            {4,  31}, {5, 32}
+         },
+         /* LE 3. LUTD LUT/RAM mode, SRL mode */
+         {
+            {4 , 38}, {5, 37}
+         }
+      },
+      /* Type 1, Slice M */
+      {
+         /* LE 0. LUTA, LUT/RAM mode, SRL mode */
+         {
+            {4,  1}, {5, 1}
+         },
+         /* LE 1. LUTB LUT/RAM mode, SRL mode */
+         {
+            {4,  15}, {5, 13}
+         },
+         /* LE 2. LUTC LUT/RAM mode, SRL mode */
+         {
+            {4,  31}, {5, 32}
+         },
+         /* LE 3. LUTD LUT/RAM mode, SRL mode */
+         {
+            {4,  38}, {5, 37}
+         }
+	  }
+   },
+   /* CONFIG*/
+   {
+      /* Type 0, Slice L. */
+      {
+         /* LE 0. LUTA*/
+         {
+            {8, 20}, {37, 20}, {8, 20}, {37, 20}
+         },
+         /* LE 1. LUTB*/
+         {
+            {8, 20}, {37, 20}, {8, 20}, {37, 20}
+         },
+         /* LE 2. LUTC*/
+         {
+            {8, 20}, {37, 20}, {8, 20}, {37, 20}
+         },
+         /* LE 3. LUTD*/
+         {
+            {7, 20}, {36, 20}, {8, 20}, {37, 20}
+         }
+      },
+      /* Type 1, Slice M. */
+      {
+         /* LE 0. LUTA*/
+         {
+            {48, 20}, {78, 20}, {48, 20}, {78, 20}
+         },
+         /* LE 1. LUTB*/
+         {
+            {48, 20}, {78, 20}, {48, 20}, {78, 20}
+         },
+         /* LE 2. LUTC*/
+         {
+            {48, 20}, {78, 20}, {48, 20}, {78, 20}
+         },
+         /* LE 3. LUTD*/
+         {
+            {40, 20}, {78, 20}, {48, 20}, {78, 20}
+         }
+      }
+   },
+   /* CONTENTS*/
+   {
+      /* Type 0, Slice L. */
+      {
+         /* LE 0. LUTA*/
+         {
+			/* Icle_ll.ISL.LUTA */
+
+			/* LSb to MSb, offset, minor */
+			{15,3},{14,2},{13,3},{12,2},{11,3},{10,2},{9,3}, {8,2},
+			{7,3}, {6,2}, {5,3}, {4,2}, {3,3}, {2,2}, {1,3}, {0,2},
+			{15,2},{14,3},{13,2},{12,3},{11,2},{10,3},{9,2}, {8,3},
+			{7,2}, {6,3}, {5,2}, {4,3}, {3,2}, {2,3}, {1,2}, {0,3},
+			{15,0},{14,1},{13,0},{12,1},{11,0},{10,1},{9,0}, {8,1},
+			{7,0}, {6,1}, {5,0}, {4,1}, {3,0}, {2,1}, {1,0}, {0,1},
+			{15,1},{14,0},{13,1},{12,0},{11,1},{10,0},{9,1}, {8,0},
+			{7,1}, {6,0}, {5,1}, {4,0}, {3,1}, {2,0}, {1,1}, {0,0}
+
+
+  	 },
+         /* LE 1. LUTB*/
+         {
+			/* Icle_ll.ISL.LUTB */
+
+			/* LSb to MSb, offset, minor */
+		{31, 3},{30, 2},{29, 3},{28, 2},{27, 3},{26, 2},{25, 3},{24, 2},
+		{23, 3},{22, 2},{21, 3},{20, 2},{19, 3},{18, 2},{17, 3},{16, 2},
+		{31, 2},{30, 3},{29, 2},{28, 3},{27, 2},{26, 3},{25, 2},{24, 3},
+		{23, 2},{22, 3},{21, 2},{20, 3},{19, 2},{18, 3},{17, 2},{16, 3},
+		{31, 0},{30, 1},{29, 0},{28, 1},{27, 0},{26, 1},{25, 0},{24, 1},
+		{23, 0},{22, 1},{21, 0},{20, 1},{19, 0},{18, 1},{17, 0},{16, 1},
+		{31, 1},{30, 0},{29, 1},{28, 0},{27, 1},{26, 0},{25, 1},{24, 0},
+		{23, 1},{22, 0},{21, 1},{20, 0},{19, 1},{18, 0},{17, 1},{16, 0}
+
+         },
+         /* LE 2. LUTC*/
+         {
+			/* Icle_ll.ISL.LUTC */
+
+			/* LSb to MSb, offset, minor */
+		{47, 3},{46, 2},{45, 3},{44, 2},{43, 3},{42, 2},{41, 3},{40, 2},
+		{39, 3},{38, 2},{37, 3},{36, 2},{35, 3},{34, 2},{33, 3},{32, 2},
+		{47, 2},{46, 3},{45, 2},{44, 3},{43, 2},{42, 3},{41, 2},{40, 3},
+		{39, 2},{38, 3},{37, 2},{36, 3},{35, 2},{34, 3},{33, 2},{32, 3},
+		{47, 0},{46, 1},{45, 0},{44, 1},{43, 0},{42, 1},{41, 0},{40, 1},
+		{39, 0},{38, 1},{37, 0},{36, 1},{35, 0},{34, 1},{33, 0},{32, 1},
+		{47, 1},{46, 0},{45, 1},{44, 0},{43, 1},{42, 0},{41, 1},{40, 0},
+		{39, 1},{38, 0},{37, 1},{36, 0},{35, 1},{34, 0},{33, 1},{32, 0}
+         },
+         /* LE 3. LUTD*/
+         {
+			/* Icle_ll.ISL.LUTD */
+
+			/* LSb to MSb, offset, minor */
+		{63, 3},{62, 2},{61, 3},{60, 2},{59, 3},{58, 2},{57, 3},{56, 2},
+		{55, 3},{54, 2},{53, 3},{52, 2},{51, 3},{50, 2},{49, 3},{48, 2},
+		{63, 2},{62, 3},{61, 2},{60, 3},{59, 2},{58, 3},{57, 2},{56, 3},
+		{55, 2},{54, 3},{53, 2},{52, 3},{51, 2},{50, 3},{49, 2},{48, 3},
+		{63, 0},{62, 1},{61, 0},{60, 1},{59, 0},{58, 1},{57, 0},{56, 1},
+		{55, 0},{54, 1},{53, 0},{52, 1},{51, 0},{50, 1},{49, 0},{48, 1},
+		{63, 1},{62, 0},{61, 1},{60, 0},{59, 1},{58, 0},{57, 1},{56, 0},
+		{55, 1},{54, 0},{53, 1},{52, 0},{51, 1},{50, 0},{49, 1},{48, 0}
+
+         }
+      },
+      /* Type 1. Slice M */
+      {
+         /* LE 0. LUTA*/
+         {
+			/* Icle_lm.ISL.LUTA */
+
+
+			/* LSb to MSb, offset, minor */
+			{15,3},{14,2},{13,3},{12,2},{11,3},{10,2},{9,3}, {8,2},
+			{7,3}, {6,2}, {5,3}, {4,2}, {3,3}, {2,2}, {1,3}, {0,2},
+			{15,2},{14,3},{13,2},{12,3},{11,2},{10,3},{9,2}, {8,3},
+			{7,2}, {6,3}, {5,2}, {4,3}, {3,2}, {2,3}, {1,2}, {0,3},
+			{15,0},{14,1},{13,0},{12,1},{11,0},{10,1},{9,0}, {8,1},
+			{7,0}, {6,1}, {5,0}, {4,1}, {3,0}, {2,1}, {1,0}, {0,1},
+			{15,1},{14,0},{13,1},{12,0},{11,1},{10,0},{9,1}, {8,0},
+			{7,1}, {6,0}, {5,1}, {4,0}, {3,1}, {2,0}, {1,1}, {0,0}
+		},
+         /* LE 1. LUTB*/
+         {
+			/* Icle_lm.ISL.LUTB */
+
+			/* LSb to MSb, offset, minor */
+		{31, 3},{30, 2},{29, 3},{28, 2},{27, 3},{26, 2},{25, 3},{24, 2},
+		{23, 3},{22, 2},{21, 3},{20, 2},{19, 3},{18, 2},{17, 3},{16, 2},
+		{31, 2},{30, 3},{29, 2},{28, 3},{27, 2},{26, 3},{25, 2},{24, 3},
+		{23, 2},{22, 3},{21, 2},{20, 3},{19, 2},{18, 3},{17, 2},{16, 3},
+		{31, 0},{30, 1},{29, 0},{28, 1},{27, 0},{26, 1},{25, 0},{24, 1},
+		{23, 0},{22, 1},{21, 0},{20, 1},{19, 0},{18, 1},{17, 0},{16, 1},
+		{31, 1},{30, 0},{29, 1},{28, 0},{27, 1},{26, 0},{25, 1},{24, 0},
+		{23, 1},{22, 0},{21, 1},{20, 0},{19, 1},{18, 0},{17, 1},{16, 0}
+         },
+         /* LE 2. LUTC*/
+         {
+			/* Icle_lm.ISL.LUTC */
+
+			/* LSb to MSb, offset, minor */
+		{47, 3},{46, 2},{45, 3},{44, 2},{43, 3},{42, 2},{41, 3},{40, 2},
+		{39, 3},{38, 2},{37, 3},{36, 2},{35, 3},{34, 2},{33, 3},{32, 2},
+		{47, 2},{46, 3},{45, 2},{44, 3},{43, 2},{42, 3},{41, 2},{40, 3},
+		{39, 2},{38, 3},{37, 2},{36, 3},{35, 2},{34, 3},{33, 2},{32, 3},
+		{47, 0},{46, 1},{45, 0},{44, 1},{43, 0},{42, 1},{41, 0},{40, 1},
+		{39, 0},{38, 1},{37, 0},{36, 1},{35, 0},{34, 1},{33, 0},{32, 1},
+		{47, 1},{46, 0},{45, 1},{44, 0},{43, 1},{42, 0},{41, 1},{40, 0},
+		{39, 1},{38, 0},{37, 1},{36, 0},{35, 1},{34, 0},{33, 1},{32, 0}
+
+         },
+         /* LE 3. LUTD*/
+         {
+			/* Icle_lm.ISL.LUTD */
+
+			/* LSb to MSb, offset, minor */
+		{63, 3},{62, 2},{61, 3},{60, 2},{59, 3},{58, 2},{57, 3},{56, 2},
+		{55, 3},{54, 2},{53, 3},{52, 2},{51, 3},{50, 2},{49, 3},{48, 2},
+		{63, 2},{62, 3},{61, 2},{60, 3},{59, 2},{58, 3},{57, 2},{56, 3},
+		{55, 2},{54, 3},{53, 2},{52, 3},{51, 2},{50, 3},{49, 2},{48, 3},
+		{63, 0},{62, 1},{61, 0},{60, 1},{59, 0},{58, 1},{57, 0},{56, 1},
+		{55, 0},{54, 1},{53, 0},{52, 1},{51, 0},{50, 1},{49, 0},{48, 1},
+		{63, 1},{62, 0},{61, 1},{60, 0},{59, 1},{58, 0},{57, 1},{56, 0},
+		{55, 1},{54, 0},{53, 1},{52, 0},{51, 1},{50, 0},{49, 1},{48, 0}
+
+         }
+      }
+   },
+
+};
+
+#elif XHI_FAMILY == XHI_DEV_FAMILY_V6 /* Virtex6 */
+
+/************************** Constant Definitions ****************************/
+
+/**
+ * Index into SLICE and MODE for TYPE, L or M.
+ */
+#define XHI_CLB_TYPE_L 0
+#define XHI_CLB_TYPE_M 1
+
+
+/**
+ * Index into SLICE and MODE for LUT A...D.
+ */
+#define XHI_CLB_LUT_A 0
+#define XHI_CLB_LUT_B 1
+#define XHI_CLB_LUT_C 2
+#define XHI_CLB_LUT_D 3
+
+
+/**************************** Type Definitions ******************************/
+
+typedef struct {
+	/**
+	 * MODE resource values.
+	 */
+	const u8 LUT_MODE[1];	/**< Set MODE to LUT mode */
+	const u8 ROM_MODE[1];	/**< Set MODE to ROM mode.
+					  * (Same as LUT mode) */
+	const u8 RAM_MODE[1];	/**< Set MODE to RAM mode. */
+
+	/**
+	 * CONFIG resource values.
+	 */
+	const u8 SHIFT_CONFIG16[2];	/**< Set CONFIG to shifter SRL16 */
+	const u8 SHIFT_CONFIG32[2];	/**< Set CONFIG to shifter SRL32 */
+	const u8 RAM_CONFIG_SP[2];	/**< Set CONFIG to ram, single port,
+						64/32. */
+	const u8 RAM_CONFIG_DP[2];	/**< Set CONFIG to ram. dual port,
+						64/32.*/
+	const u8 LUT_CONFIG[2];		/**< Set CONFIG to LUT. */
+
+	/**
+	 * [num slice, 0/1{L/M}][num LUTS,4][(lut/ram)/srl]
+	 * RAM_MODE, ROM_MODE, or LUT_MODE.  Indexed by the slice (0,1).
+	 */
+	const u8 MODE[2][4][2][2];
+
+	/**
+	 * [type slice, L/M][num LUTS,4][num configs, 4]
+	 * SHIFT_CONFIG, RAM_CONFIG, or LUT_CONFIG.  Indexed by the slice
+	 * (0-1).  And then indexed by the LUT number (A=0 ... D=3).
+	 */
+	const u8 CONFIG[2][4][4][2];
+
+	/**
+	 * [type slice, L/M][num LUTs 4][contents]
+	 * LUT memory contents. Indexed by slice first (0-1) and by
+	 * LUT number {A=0...D=3}.
+	 */
+	const u8 CONTENTS[2][4][64][2];
+
+} XHwIcap_ClbLut;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*  This structure defines the Look Up Tables, or <em>LUTs</em>.
+*  in the Virtex6 CLB.  Note that there are 8 16-bit
+*  LUTs, the L and M LUTs in Slice 0, and 1.  These
+*  LUTs can take any arbitrary bit pattern.
+*
+*
+*
+***************************************************************************/
+
+const XHwIcap_ClbLut XHI_CLB_LUT =
+{
+   /* LUT_MODE*/
+   {0},
+   /* ROM_MODE*/
+   {0},
+   /* RAM_MODE*/
+   {1},
+   /* SHIFT_CONFIG 16 */
+   {4, 1},
+   /* SHIFT_CONFIG 32 */
+   {4,  1},
+   /* RAM_CONFIG SP */
+   {4,  1},
+   /* RAM_CONFIG DP */
+   {4,  1},
+   /* LUT_CONFIG*/
+   {4,  1},
+   /* MODE*/
+   {
+      /* Type 0, Slice  L.*/
+      {
+         /* LE 0. LUTA, LUT/RAM mode, SRL mode */
+         {
+            {4,  1}, {5, 1}
+         },
+         /* LE 1. LUTB LUT/RAM mode, SRL mode */
+         {
+            {4,  15}, {5, 13}
+         },
+         /* LE 2. LUTC LUT/RAM mode, SRL mode */
+         {
+            {4,  31}, {5, 32}
+         },
+         /* LE 3. LUTD LUT/RAM mode, SRL mode */
+         {
+            {4 , 38}, {5, 37}
+         }
+      },
+      /* Type 1, Slice M */
+      {
+         /* LE 0. LUTA, LUT/RAM mode, SRL mode */
+         {
+            {4,  1}, {5, 1}
+         },
+         /* LE 1. LUTB LUT/RAM mode, SRL mode */
+         {
+            {4,  15}, {5, 13}
+         },
+         /* LE 2. LUTC LUT/RAM mode, SRL mode */
+         {
+            {4,  31}, {5, 32}
+         },
+         /* LE 3. LUTD LUT/RAM mode, SRL mode */
+         {
+            {4,  38}, {5, 37}
+         }
+	  }
+   },
+   /* CONFIG*/
+   {
+      /* Type 0, Slice L. */
+      {
+         /* LE 0. LUTA*/
+         {
+            {8, 20}, {37, 20}, {8, 20}, {37, 20}
+         },
+         /* LE 1. LUTB*/
+         {
+            {8, 20}, {37, 20}, {8, 20}, {37, 20}
+         },
+         /* LE 2. LUTC*/
+         {
+            {8, 20}, {37, 20}, {8, 20}, {37, 20}
+         },
+         /* LE 3. LUTD*/
+         {
+            {7, 20}, {36, 20}, {8, 20}, {37, 20}
+         }
+      },
+      /* Type 1, Slice M. */
+      {
+         /* LE 0. LUTA*/
+         {
+            {48, 20}, {78, 20}, {48, 20}, {78, 20}
+         },
+         /* LE 1. LUTB*/
+         {
+            {48, 20}, {78, 20}, {48, 20}, {78, 20}
+         },
+         /* LE 2. LUTC*/
+         {
+            {48, 20}, {78, 20}, {48, 20}, {78, 20}
+         },
+         /* LE 3. LUTD*/
+         {
+            {40, 20}, {78, 20}, {48, 20}, {78, 20}
+         }
+      }
+   },
+   /* CONTENTS*/
+   {
+      /* Type 0, Slice L. */
+      {
+         /* LE 0. LUTA*/
+         {
+			/* Icle_ll.ISL.LUTA */
+	{15,1}, {13,1}, {15, 3},  {13,3},  {11,1},  {9,1},   {11,3}, {9,3},
+	{7, 1}, {5, 1}, {7,  3},  {5,3},   {3,1},   {1,1},   {3,3},  {1,3},
+	{15,0}, {13,0}, {15,2},   {13,2},  {11,0},  {9,0},   {11,2},  {9,2},
+	{7,0},  {5,0},  {7,2},    {5,2},   {3,0},   {1,0},   {3,2},   {1,2},
+	{14, 1},{12, 1},{14, 3},  {12,3},  {10,1},  {8,1},   {10,3},  {8,3},
+	{6,1},  {4,1},  {6,3},    {4,3},   {2,1},    {0,1},   {2,3},   {0,3},
+ 	{14,0}, {12,0}, {14,2},   {12,2},  {10,0},  {8,0},   {10,2},  {8,2},
+	{6,0},  {4,0},  {6,2},    {4,2},   {2,0},   {0,0},   {2,2},   {0,2}
+         },
+         /* LE 1. LUTB*/
+         {
+			/* Icle_ll.ISL.LUTB */
+	{31, 1}, {29, 1}, {31, 3}, {29, 3}, {27, 1}, {25, 1}, {27, 3}, {25, 3},
+	{23, 1}, {21, 1}, {23, 3}, {21, 3}, {19, 1}, {17, 1}, {19, 3}, {17, 3},
+	{31, 0}, {29, 0}, {31, 2}, {29, 2}, {27, 0}, {25, 0}, {27, 2}, {25, 2},
+	{23, 0}, {21, 0}, {23, 2}, {21, 2}, {19, 0}, {17, 0}, {19, 2}, {17, 2},
+	{30, 1}, {28, 1}, {30, 3}, {28, 3}, {26, 1}, {24, 1}, {26, 3}, {24, 3},
+	{22, 1}, {20, 1}, {22, 3}, {20, 3}, {18, 1}, {16, 1}, {18, 3}, {16, 3},
+	{30, 0}, {28, 0}, {30, 2}, {28, 2}, {26, 0}, {24, 0}, {26, 2}, {24, 2},
+	{22, 0}, {20, 0}, {22, 2}, {20, 2}, {18, 0}, {16, 0}, {18, 2}, {16, 2}
+	 },
+         /* LE 2. LUTC*/
+         {
+			/* Icle_ll.ISL.LUTC */
+	{47, 1}, {45, 1}, {47, 3}, {45, 3}, {43, 1}, {41, 1}, {43, 3}, {41, 3},
+	{39, 1}, {37, 1}, {39, 3}, {37, 3}, {35, 1}, {33, 1}, {35, 3}, {33, 3},
+	{47, 0}, {45, 0}, {47, 2}, {45, 2}, {43, 0}, {41, 0}, {43, 2}, {41, 2},
+	{39, 0}, {37, 0}, {39, 2}, {37, 2}, {35, 0}, {33, 0}, {35, 2}, {33, 2},
+	{46, 1}, {44, 1}, {46, 3}, {44, 3}, {42, 1}, {40, 1}, {42, 3}, {40, 3},
+	{38, 1}, {36, 1}, {38, 3}, {36, 3}, {34, 1}, {32, 1}, {34, 3}, {32, 3},
+	{46, 0}, {44, 0}, {46, 2}, {44, 2}, {42, 0}, {40, 0}, {42, 2}, {40, 2},
+	{38, 0}, {36, 0}, {38, 2}, {36, 2}, {34, 0}, {32, 0}, {34, 2}, {32, 2}
+         },
+         /* LE 3. LUTD*/
+         {
+			/* Icle_ll.ISL.LUTD */
+	{63, 1}, {61, 1}, {63, 3}, {61, 3}, {59, 1}, {57, 1}, {59, 3}, {57, 3},
+	{55, 1}, {53, 1}, {55, 3}, {53, 3}, {51, 1}, {49, 1}, {51, 3}, {49, 3},
+	{63, 0}, {61, 0}, {63, 2}, {61, 2}, {59, 0}, {57, 0}, {59, 2}, {57, 2},
+	{55, 0}, {53, 0}, {55, 2}, {53, 2}, {51, 0}, {49, 0}, {51, 2}, {49, 2},
+	{62, 1}, {60, 1}, {62, 3}, {60, 3}, {58, 1}, {56, 1}, {58, 3}, {56, 3},
+	{54, 1}, {52, 1}, {54, 3}, {52, 3}, {50, 1}, {48, 1}, {50, 3}, {48, 3},
+	{62, 0}, {60, 0}, {62, 2}, {60, 2}, {58, 0}, {56, 0}, {58, 2}, {56, 2},
+	{54, 0}, {52, 0}, {54, 2}, {52, 2}, {50, 0}, {48, 0}, {50, 2}, {48, 2}
+         }
+      },
+      /* Type 1. Slice M */
+      {
+         /* LE 0. LUTA*/
+         {
+			/* Icle_lm.ISL.LUTA */
+	{15, 9}, {13, 9}, {15, 6}, {13, 6}, {11, 9}, {9, 9}, {11, 6}, {9, 6},
+	{7, 9},  {5, 9},  {7, 6},  {5, 6},  {3, 9},  {1, 9}, {3, 6},  {1, 6},
+	{15, 8}, {13, 8}, {15, 7}, {13, 7}, {11, 8}, {9, 8}, {11, 7}, {9, 7},
+	{7, 8},  {5, 8},  {7, 7},  {5, 7},  {3, 8},  {1, 8}, {3, 7},  {1, 7},
+	{14, 9}, {12,6},  {14,6},  {12, 6}, {10, 9}, {8, 9}, {10, 6}, {8, 6},
+	{6, 9},  {4, 9},  {6, 6},  {4, 6},  {2, 9},  {0, 9}, {2, 6},  {0, 6},
+	{14, 8}, {12, 8}, {14, 7}, {12, 7}, {10, 8}, {8, 8}, {10, 7}, {8, 7},
+	{6, 8},  {4, 8},  {6, 7},  {4, 7},  {2, 8},  {0, 8}, {2, 7},  {0, 7},         },
+         /* LE 1. LUTB*/
+         {
+			/* Icle_lm.ISL.LUTB */
+	{31, 8}, {29, 9}, {31, 6}, {29, 6}, {27, 9}, {25, 9}, {27, 6}, {25, 6},
+	{23, 9}, {21, 9}, {23, 6}, {21, 6}, {19, 9}, {17, 9}, {19, 6}, {17, 6},
+	{31, 8}, {29, 8}, {31, 7}, {29, 7}, {27, 8}, {25, 8}, {27, 7}, {25, 7},
+	{23, 8}, {21, 8}, {23, 7}, {21, 7}, {19, 8}, {17, 8}, {19, 7}, {17, 7},
+	{30, 9}, {28, 9}, {30, 6}, {28, 6}, {26, 9}, {24, 9}, {26, 6}, {24, 6},
+	{22, 9}, {20, 9}, {22, 6}, {20, 6}, {18, 9}, {16, 9}, {18, 6}, {16, 6},
+	{30, 8}, {28, 8}, {30, 7}, {28, 7}, {26, 8}, {24, 8}, {26, 7}, {24, 7},
+	{22, 8}, {20, 8}, {22, 7}, {20, 7}, {18, 8}, {16, 8}, {18, 7}, {16, 7}
+         },
+         /* LE 2. LUTC*/
+         {
+			/* Icle_lm.ISL.LUTC */
+	{47, 9}, {45, 9}, {47, 6}, {44, 6}, {43, 9}, {41, 9}, {43, 6}, {41, 6},
+	{39, 9}, {37, 9}, {39, 6}, {37, 6}, {35, 9}, {33, 9}, {35, 6}, {33, 6},
+	{47, 8}, {45, 8}, {47, 7}, {45, 7}, {43, 8}, {41, 8}, {43, 7}, {41, 7},
+	{39, 8}, {37, 8}, {39, 7}, {37, 7}, {35, 8}, {33, 8}, {35, 7}, {33, 7},
+	{46, 9}, {44, 9}, {46, 6}, {44, 6}, {42, 9}, {40, 9}, {42, 6}, {40, 6},
+	{38, 9}, {36, 9}, {38, 6}, {36, 6}, {34, 9}, {32, 9}, {34, 6}, {32, 6},
+	{46, 8}, {44, 8}, {46, 7}, {44, 7}, {42, 8}, {40, 8}, {42, 7}, {40, 7},
+	{38, 8}, {36, 8}, {38, 7}, {36, 7}, {34, 8}, {32, 8}, {34, 7}, {32, 7}
+         },
+         /* LE 3. LUTD*/
+         {
+			/* Icle_lm.ISL.LUTD */
+	{63, 9}, {61, 9}, {63, 6}, {61, 6}, {59, 9}, {57, 9}, {59, 6}, {57, 6},
+	{55, 9}, {53, 9}, {55, 6}, {53, 6}, {51, 9}, {49, 9}, {51, 6}, {49, 6},
+	{63, 8}, {61, 8}, {63, 7}, {61, 7}, {59, 8}, {57, 8}, {59, 7}, {57, 7},
+	{55, 8}, {53, 8}, {55, 7}, {53, 7}, {51, 8}, {49, 8}, {51, 7}, {49, 7},
+	{62, 9}, {60, 9}, {62, 6}, {60, 6}, {58, 9}, {56, 9}, {58, 6}, {56, 6},
+	{54, 9}, {52, 9}, {54, 6}, {52, 6}, {50, 9}, {48, 9}, {50, 6}, {48, 6},
+	{62, 8}, {60, 8}, {62, 7}, {60, 7}, {58, 8}, {56, 8}, {58, 7}, {56, 7},
+	{54, 8}, {52, 8}, {54, 7}, {52, 7}, {50, 8}, {48, 8}, {50, 7}, {48, 7}
+         }
+      }
+   },
+
+};
+
+#else
+
+#error Unsupported FPGA Family
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_clb_srinv.h b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_clb_srinv.h
new file mode 100755
index 00000000..ce1299b6
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_clb_srinv.h
@@ -0,0 +1,127 @@
+/******************************************************************************
+*
+* Copyright (C) 2007 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_clb_srinv.h
+*
+* This header file contains bit information about the CLB SRINV resource.
+* This header file can be used with the XHwIcap_GetClbBits() and
+* XHwIcap_SetClbBits() functions. This is only for Virtex4 devices.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb  11/14/03 First release
+* 1.01a bjb  04/10/06 V4 Support
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XHWICAP_CLB_SRINV_H_  /* prevent circular inclusions */
+#define XHWICAP_CLB_SRINV_H_  /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
+typedef struct {
+	/**
+	 * SRINV Resource values.
+	 */
+	const u8 SR_B[1];  /* Invert SR Line. */
+	const u8 SR[1];    /* Do not Invert SR line. */
+
+	/**
+	 * Configure the SRINV mux (SR_B or SR).  This array indexed by
+	 * slice  (0-3).
+	 */
+	const u8 RES[4][1][2];
+} XHwIcap_ClbSrinv;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/************************** Variable Definitions ****************************/
+
+/**
+ * This structure defines the SRINV mux
+ */
+const XHwIcap_ClbSrinv XHI_CLB_SRINV =
+{
+	/* SR_B*/
+	{0},
+	/* SR*/
+	{1},
+	/* RES*/
+	{
+		/* Slice 0. */
+		{
+			{24, 18}
+		},
+		/* Slice 1. */
+		{
+			{23, 18}
+		},
+		/* Slice 2. */
+		{
+			{26, 18}
+		},
+		/* Slice 3. */
+		{
+			{25, 18}
+		}
+	},
+
+};
+
+#else
+#error Unsupported FPGA Family
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_device_read_frame.c b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_device_read_frame.c
new file mode 100755
index 00000000..c5ff405b
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_device_read_frame.c
@@ -0,0 +1,317 @@
+/******************************************************************************
+*
+* Copyright (C) 2003 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_device_read_frame.c
+*
+* This file contains the function that reads a specified frame from the
+* device (ICAP) and stores it in the memory specified by the user.
+*
+* @note none.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb  11/20/03 First release
+* 1.01a nps  04/10/06 V4 Support
+* 2.00a ecm  10/20/07 V5 Support
+* 4.00a hvm  11/30/09 Added support for V6 and updated with HAL phase 1
+*					  modifications
+* 5.00a hvm  2/25/10  Added support for S6
+* 6.00a hvm  08/01/11 Added support for K7
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xhwicap_i.h"
+#include "xhwicap.h"
+#include <xil_types.h>
+#include <xil_assert.h>
+
+/************************** Constant Definitions ****************************/
+
+#define READ_FRAME_SIZE 20
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5 ) ||\
+	(XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES ))
+/****************************************************************************/
+/**
+*
+* Reads one frame from the device and puts it in memory specified by the user.
+*
+* @param	InstancePtr - a pointer to the XHwIcap instance to be worked on.
+* @param	Top - top (0) or bottom (1) half of device
+* @param	Block - Block Address (XHI_FAR_CLB_BLOCK,
+*		XHI_FAR_BRAM_BLOCK, XHI_FAR_BRAM_INT_BLOCK)
+* @param	HClkRow - selects the HClk Row
+* @param	MajorFrame - selects the column
+* @param	MinorFrame - selects frame inside column
+* @param	FrameBuffer is a pointer to the memory where the frame read
+*		from the device is stored
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		This is a blocking call.
+*
+*****************************************************************************/
+int XHwIcap_DeviceReadFrame(XHwIcap *InstancePtr, long Top, long Block,
+				long HClkRow, long MajorFrame, long MinorFrame,
+				u32 *FrameBuffer)
+{
+
+	u32 Packet;
+	u32 Data;
+	u32 TotalWords;
+	int Status;
+	u32 WriteBuffer[READ_FRAME_SIZE];
+	u32 Index = 0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(FrameBuffer != NULL);
+
+	/*
+	 * DUMMY and SYNC
+	 */
+	WriteBuffer[Index++] = XHI_DUMMY_PACKET;
+	WriteBuffer[Index++] = XHI_SYNC_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+
+	/*
+	 * Reset CRC
+	 */
+	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = XHI_CMD_RCRC;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+
+	/*
+	 * Setup CMD register to read configuration
+	 */
+	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = XHI_CMD_RCFG;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+
+	/*
+	 * Setup FAR register.
+	 */
+	Packet = XHwIcap_Type1Write(XHI_FAR) | 1;
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
+	Data = XHwIcap_SetupFarV4(Top, Block, HClkRow,  MajorFrame, MinorFrame);
+#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) || \
+	(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+	Data = XHwIcap_SetupFarV5(Top, Block, HClkRow,  MajorFrame, MinorFrame);
+#endif
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = Data;
+
+	/*
+	 * Setup read data packet header.
+	 * The frame will be preceeded by a dummy frame, and we need to read one
+	 * extra word for V4 and V5 devices.
+	 */
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5))
+	TotalWords = (InstancePtr->WordsPerFrame << 1) + 1;
+#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+	TotalWords = (InstancePtr->WordsPerFrame << 1);
+#endif
+	/*
+	 * Create Type one packet
+	 */
+	Packet = XHwIcap_Type1Read(XHI_FDRO) | TotalWords;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+
+	/*
+	 * Write the data to the FIFO and initiate the transfer of data
+	 * present in the FIFO to the ICAP device
+	 */
+	Status = XHwIcap_DeviceWrite(InstancePtr, (u32 *)&WriteBuffer[0],
+			Index);
+	if (Status != XST_SUCCESS)  {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Wait till the write is done.
+	 */
+	while (XHwIcap_IsDeviceBusy(InstancePtr) != FALSE);
+
+
+	/*
+	 * Read the frame of the data including the NULL frame.
+	 */
+	Status = XHwIcap_DeviceRead(InstancePtr, FrameBuffer, TotalWords);
+	if (Status != XST_SUCCESS)  {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Send DESYNC command
+	 */
+	Status = XHwIcap_CommandDesync(InstancePtr);
+	if (Status != XST_SUCCESS)  {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+};
+#elif (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+/****************************************************************************/
+/**
+*
+* Reads one frame from the device and puts it in memory specified by the user.
+*
+* @param	InstancePtr - a pointer to the XHwIcap instance to be worked on.
+* @param	Block - Block Address (XHI_FAR_CLB_BLOCK,
+*		XHI_FAR_BRAM_BLOCK, XHI_FAR_BRAM_INT_BLOCK)
+* @param	MajorFrame - selects the column
+* @param	MinorFrame - selects frame inside column
+* @param	FrameBuffer is a pointer to the memory where the frame read
+*		from the device is stored
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		This is a blocking call.
+*
+*****************************************************************************/
+int XHwIcap_DeviceReadFrame(XHwIcap *InstancePtr, long Block, long Row,
+				long MajorFrame, long MinorFrame,
+				u16 *FrameBuffer)
+{
+	int Status;
+	u16 Packet;
+	u16 TotalWords;
+	u16 WriteBuffer[READ_FRAME_SIZE];
+	u16 Index = 0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(FrameBuffer != NULL);
+
+	/*
+	 * DUMMY and SYNC
+	 */
+	WriteBuffer[Index++] = XHI_DUMMY_PACKET;
+	WriteBuffer[Index++] = XHI_SYNC_PACKET1;
+	WriteBuffer[Index++] = XHI_SYNC_PACKET2;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+
+	/*
+	 * Setup FAR register.
+	 */
+	Packet = XHwIcap_Type1Write(XHI_FAR_MAJ) | 1;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = (Block << XHI_BLOCK_SHIFT) |
+				(Row << XHI_ROW_SHIFT) | MajorFrame;
+	Packet = XHwIcap_Type1Write(XHI_FAR_MIN) | 1;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = MinorFrame;
+
+	/*
+	 * Setup CMD register to read configuration
+	 */
+	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = XHI_CMD_RCFG;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+
+	TotalWords = (InstancePtr->WordsPerFrame << 1) + 1;
+	/*
+	 * Create Type two packet for FDRO
+	 */
+	WriteBuffer[Index++] = XHwIcap_Type2Read(XHI_FDRO);
+	WriteBuffer[Index++] = 0x0000;
+	WriteBuffer[Index++] = TotalWords;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+
+	/*
+	 * Write the data to the FIFO and initiate the transfer of data
+	 * present in the FIFO to the ICAP device
+	 */
+	Status = XHwIcap_DeviceWrite(InstancePtr, (u16 *)&WriteBuffer[0],
+					Index);
+	if (Status != XST_SUCCESS)  {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Wait till the write is done.
+	 */
+	while ((XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
+					XHI_CR_OFFSET)) &
+					XHI_CR_WRITE_MASK);
+
+	/*
+	 * Read the frame of the data including the NULL frame.
+	 */
+	Status = XHwIcap_DeviceRead(InstancePtr, &FrameBuffer[0],
+				TotalWords);
+
+	if (Status != XST_SUCCESS)  {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Send DESYNC command
+	 */
+	Status = XHwIcap_CommandDesync(InstancePtr);
+	if (Status != XST_SUCCESS)  {
+		return XST_FAILURE;
+	}
+
+	return Status;
+}
+#endif
diff --git a/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_device_write_frame.c b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_device_write_frame.c
new file mode 100755
index 00000000..2062265e
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_device_write_frame.c
@@ -0,0 +1,509 @@
+/******************************************************************************
+*
+* Copyright (C) 2003 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_device_write_frame.c
+*
+* This file contains the function that writes the frame stored in the
+* memory to the device (ICAP).
+*
+* @note none.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb  11/20/03 First release
+* 1.01a bjb  04/10/06 V4 Support
+* 4.00a hvm  11/30/09 Added support for V6 and updated with HAL phase 1
+*		      modifications
+* 5.00a hvm  2/25/10  Added support for S6
+* 5.01a hvm  07/06/10 Removed the code that adds wrong data byte before the
+*		      CRC bytes in the XHwIcap_DeviceWriteFrame function for S6
+*		      (CR560534)
+* 6.00a hvm  08/01/11   Added support for K7
+*
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xhwicap.h"
+#include <xil_types.h>
+#include <xil_assert.h>
+
+/************************** Constant Definitions ****************************/
+
+#define READ_FRAME_SIZE 30
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5 ) ||\
+(XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+/****************************************************************************/
+/**
+*
+* Writes one frame from the specified buffer and puts it in the device
+* (ICAP).
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+* @param	Top - top (0) or bottom (1) half of device
+* @param	Block - Block Address (XHI_FAR_CLB_BLOCK,
+* 		XHI_FAR_BRAM_BLOCK, XHI_FAR_BRAM_INT_BLOCK)
+* @param	HClkRow - selects the HClk Row
+* @param	MajorFrame - selects the column
+* @param	MinorFrame - selects frame inside column
+* @param	FrameData is a pointer to the frame that is to be written
+*		to the device.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		This is a blocking function.
+*		This function is used in conjunction with the function
+*		XHwIcap_DeviceReadFrame. This function is used to write back
+*		the frame of data read using the XHwIcap_DeviceReadFrame.
+*
+*****************************************************************************/
+int XHwIcap_DeviceWriteFrame(XHwIcap *InstancePtr, long Top, long Block,
+				long HClkRow, long MajorFrame, long MinorFrame,
+				u32 *FrameData)
+{
+
+	u32 Packet;
+	u32 Data;
+	u32 TotalWords;
+	int Status;
+	u32 WriteBuffer[READ_FRAME_SIZE];
+	u32 Index =0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(FrameData != NULL);
+
+
+	/*
+	 * DUMMY and SYNC
+	 */
+	WriteBuffer[Index++] = XHI_DUMMY_PACKET;
+	WriteBuffer[Index++] = XHI_SYNC_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+
+	/*
+	 * Reset CRC
+	 */
+	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
+	Data = XHI_CMD_RCRC;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = Data;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+
+
+
+	/*
+	 * Bypass CRC
+	 */
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5))
+	Packet = XHwIcap_Type1Write(XHI_COR) | 1;
+	Data = 0x10042FDD;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = Data;
+#endif
+	/*
+	 * ID register
+	 */
+	Packet = XHwIcap_Type1Write(XHI_IDCODE) | 1;
+	Data = InstancePtr->DeviceIdCode;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = Data;
+
+
+	/*
+	 * Setup FAR
+	 */
+	Packet = XHwIcap_Type1Write(XHI_FAR) | 1;
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex 4 */
+	Data = XHwIcap_SetupFarV4(Top, Block, HClkRow,  MajorFrame, MinorFrame);
+#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) || \
+	(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+	Data = XHwIcap_SetupFarV5(Top, Block, HClkRow,  MajorFrame, MinorFrame);
+#endif
+
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = Data;
+
+	/*
+	 * Setup CMD register - write configuration
+	 */
+	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
+	Data = XHI_CMD_WCFG;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = Data;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+
+	/*
+	 * Setup Packet header.
+	 */
+	TotalWords = InstancePtr->WordsPerFrame << 1;
+	if (TotalWords < XHI_TYPE_1_PACKET_MAX_WORDS)  {
+		/*
+		 * Create Type 1 Packet.
+		 */
+		Packet = XHwIcap_Type1Write(XHI_FDRI) | TotalWords;
+		WriteBuffer[Index++] = Packet;
+	}
+	else {
+
+		/*
+		 * Create Type 2 Packet.
+		 */
+		Packet = XHwIcap_Type1Write(XHI_FDRI);
+		WriteBuffer[Index++] = Packet;
+
+		Packet = XHI_TYPE_2_WRITE | TotalWords;
+		WriteBuffer[Index++] = Packet;
+	}
+
+
+	/*
+	 * Write the Header data into the FIFO and intiate the transfer of
+	 * data present in the FIFO to the ICAP device
+	 */
+	Status = XHwIcap_DeviceWrite(InstancePtr, (u32 *)&WriteBuffer[0], Index);
+	if (Status != XST_SUCCESS)  {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Write the modified frame data.
+	 */
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5))
+	Status = XHwIcap_DeviceWrite(InstancePtr,
+				(u32 *) &FrameData[InstancePtr->WordsPerFrame + 1],
+				InstancePtr->WordsPerFrame);
+#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)) /* Virtex 6 */
+	Status = XHwIcap_DeviceWrite(InstancePtr,
+				(u32 *) &FrameData[InstancePtr->WordsPerFrame],
+				InstancePtr->WordsPerFrame);
+#endif
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Write out the pad frame. The pad frame was read from the device
+	 * before the data frame.
+	 */
+
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5))
+	Status = XHwIcap_DeviceWrite(InstancePtr, (u32 *) &FrameData[1],
+				    InstancePtr->WordsPerFrame);
+#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)) /* Virtex6 */
+	Status = XHwIcap_DeviceWrite(InstancePtr, (u32 *) &FrameData[0],
+				    InstancePtr->WordsPerFrame);
+#endif
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/* Add CRC */
+	Index = 0;
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5))
+	Packet = XHwIcap_Type1Write(XHI_CRC) | 1;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = XHI_DISABLED_AUTO_CRC;
+#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)) /* Virtex6 */
+	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
+	Data = XHI_CMD_RCRC;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = Data;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+#endif
+
+	/* Park the FAR */
+	Packet = XHwIcap_Type1Write(XHI_FAR) | 1;
+
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
+	Data = XHwIcap_SetupFarV4(0, 0, 3, 33, 0);
+#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) || \
+	(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+	Data = XHwIcap_SetupFarV5(0, 0, 3, 33, 0);
+#endif
+
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] =  Data;
+
+	/* Add CRC */
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5))
+	Packet = XHwIcap_Type1Write(XHI_CRC) | 1;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = XHI_DISABLED_AUTO_CRC;
+#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)) /* Virtex6 */
+	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
+	Data = XHI_CMD_RCRC;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = Data;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+#endif
+
+	/*
+	 * Intiate the transfer of data present in the FIFO to
+	 * the ICAP device
+	 */
+	Status = XHwIcap_DeviceWrite(InstancePtr, &WriteBuffer[0], Index);
+	if (Status != XST_SUCCESS)  {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Send DESYNC command
+	 */
+	Status = XHwIcap_CommandDesync(InstancePtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+};
+
+#elif (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+/****************************************************************************/
+/**
+*
+* Writes one frame from the specified buffer and puts it in the device
+* (ICAP).
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+* @param	Top - top (0) or bottom (1) half of device
+* @param	Block - Block Address (XHI_FAR_CLB_BLOCK,
+* 		XHI_FAR_BRAM_BLOCK, XHI_FAR_BRAM_INT_BLOCK)
+* @param	HClkRow - selects the HClk Row
+* @param	MajorFrame - selects the column
+* @param	MinorFrame - selects frame inside column
+* @param	FrameData is a pointer to the frame that is to be written
+*		to the device.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		This is a blocking function.
+*		This function is used in conjunction with the function
+*		XHwIcap_DeviceReadFrame. This function is used to write back
+*		the frame of data read using the XHwIcap_DeviceReadFrame.
+*
+*****************************************************************************/
+int XHwIcap_DeviceWriteFrame(XHwIcap *InstancePtr, long Block, long Row,
+				long MajorFrame, long MinorFrame,
+				u16 *FrameData)
+{
+	u16 Packet;
+	u16 TotalWords;
+	int Status;
+	u16 WriteBuffer[READ_FRAME_SIZE];
+	u16 Data;
+	u16 Index =0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(FrameData != NULL);
+
+	/*
+	 * DUMMY and SYNC
+	 */
+	WriteBuffer[Index++] = XHI_DUMMY_PACKET;
+	WriteBuffer[Index++] = XHI_SYNC_PACKET1;
+	WriteBuffer[Index++] = XHI_SYNC_PACKET2;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+
+	/*
+	 * Reset CRC
+	 */
+	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
+	Data = XHI_CMD_RCRC;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = Data;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+
+
+	/*
+	 * Write the FLR
+	 */
+	Packet = XHwIcap_Type1Write(XHI_FLR) | 1;
+	WriteBuffer[Index++] =  Packet ;
+	WriteBuffer[Index++] =  0x430;
+
+	/*
+	 * ID register
+	 */
+	Packet = XHwIcap_Type1Write(XHI_IDCODE) | 2;
+	WriteBuffer[Index++] = Packet;
+
+	/*
+	 * It is written wrongly in the document that only lower 16 bits are
+	 * needed.The document will be updated. We need the complete 32 bit.
+	 */
+	Data = (u16)(InstancePtr->DeviceIdCode >> 16);
+	WriteBuffer[Index++] = Data;
+	Data = (u16)InstancePtr->DeviceIdCode;
+	WriteBuffer[Index++] = Data;
+
+	/*
+	 * Bypass CRC
+	 */
+	Packet = XHwIcap_Type1Write(XHI_COR1) | 1;
+	Data = XHI_COR1_DEFAULT;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = Data;
+
+
+	Packet = XHwIcap_Type1Write(XHI_COR2) | 1;
+	Data = XHI_COR2_DEFAULT;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = Data;
+
+	/*
+	 * Write the FAR MAJ and MIN address values
+	 */
+	Packet = XHwIcap_Type1Write(XHI_FAR_MAJ) | 1;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = (Block << XHI_BLOCK_SHIFT) |
+				(Row << XHI_ROW_SHIFT) | MajorFrame;
+	Packet = XHwIcap_Type1Write(XHI_FAR_MIN) | 1;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = MinorFrame;
+
+	/*
+	 * Setup CMD register - write configuration
+	 */
+	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
+	Data = XHI_CMD_WCFG;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = Data;
+
+	/*
+	 * Setup Packet header.
+	 */
+	TotalWords = InstancePtr->WordsPerFrame << 1;
+	/*
+	 * Create Type 2 Packet.
+	 */
+	Packet = XHwIcap_Type2Write(XHI_FDRI);
+
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = 0;
+	WriteBuffer[Index++] = TotalWords;
+
+	/*
+	 * Write the Header data into the FIFO and intiate the transfer of
+	 * data present in the FIFO to the ICAP device
+	 */
+	Status = XHwIcap_DeviceWrite(InstancePtr, (u16 *)&WriteBuffer[0],
+					Index);
+	if (Status != XST_SUCCESS)  {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Write the modified frame data.
+	 */
+	Status = XHwIcap_DeviceWrite(InstancePtr,
+				(u16 *) &FrameData[InstancePtr->WordsPerFrame],
+				InstancePtr->WordsPerFrame);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Write out the pad frame. The pad frame was read from the device
+	 * before the data frame.
+	 */
+	Status = XHwIcap_DeviceWrite(InstancePtr, (u16 *) &FrameData[0],
+				    InstancePtr->WordsPerFrame);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+
+	/* Disable CRC */
+	Index = 0;
+	WriteBuffer[Index++] = XHI_DISABLED_AUTO_CRC_ONE;
+	WriteBuffer[Index++] = XHI_DISABLED_AUTO_CRC_TWO;
+
+	/*
+	 * Setup CMD register - write configuration
+	 */
+	Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
+	Data = XHI_CMD_LFRM;
+	WriteBuffer[Index++] = Packet;
+	WriteBuffer[Index++] = Data;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+	WriteBuffer[Index++] = XHI_NOOP_PACKET;
+
+	/*
+	 * Intiate the transfer of data present in the FIFO to
+	 * the ICAP device
+	 */
+	Status = XHwIcap_DeviceWrite(InstancePtr, &WriteBuffer[0], Index);
+	if (Status != XST_SUCCESS)  {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Send DESYNC command
+	 */
+	Status = XHwIcap_CommandDesync(InstancePtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+
+}
+#endif
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_g.c b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_g.c
new file mode 100755
index 00000000..b0905a1d
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_g.c
@@ -0,0 +1,81 @@
+/******************************************************************************
+*
+* Copyright (C) 2003 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_g.c
+*
+* This file contains a configuration table that specifies the configuration of
+* Hwicap devices in the system. Each device in the system should have an
+* entry in the table.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a bjb  12/08/03 First release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xhwicap.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Prototypes ******************************/
+
+/**
+ * The configuration table for opb_hwicap devices
+ */
+XHwIcap_Config XHwIcap_ConfigTable[XPAR_XHWICAP_NUM_INSTANCES] =
+{
+    {
+        XPAR_HWICAP_0_DEVICE_ID,    /* Unique ID of device */
+        XPAR_HWICAP_0_BASEADDR,     /* Device base address */
+    },
+};
+
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_i.h b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_i.h
new file mode 100755
index 00000000..5728eedf
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_i.h
@@ -0,0 +1,581 @@
+/******************************************************************************
+*
+* Copyright (C) 2003 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_i.h
+*
+* This head file contains internal identifiers, which are those shared
+* between the files of the driver.  It is intended for internal use
+* only.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb  11/14/03 First release
+* 1.00b nps  02/09/05 V4 changes
+* 1.01a tjb  10/14/05 V4 Updates
+* 2.00a sv   10/14/07 V5 Updates
+* 3.01a sv   10/19/09 Corrected the V5 BOOTSTS and CTL_1 Register definitions
+*                     as they were wrongly defined
+* 4.00a hvm  11/13/09 Updated with V6 changes
+* 5.00a hvm  2/25/10  Added changes to support S6
+* 6.00a hvm  08/01/11 Added support for K7
+* 7.00a bss  03/14/12 Added Virtex 7, Artix 7 and Zynq Device families
+* 8.01a bss  05/14/12 Added the define XHI_COR_1 for CR718042
+* 9.0   bss  02/20/14 Added XHI_DEV_FAMILY_K8 for Kintex 8 devices. #CR764668
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XHWICAP_I_H_ /* prevent circular inclusions */
+#define XHWICAP_I_H_ /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xhwicap_family.h"
+
+/************************** Constant Definitions ****************************/
+
+#define XHI_DEV_FAMILY_V4		2	/* Virtex4 */
+#define XHI_DEV_FAMILY_V5		3	/* Virtex5 */
+#define XHI_DEV_FAMILY_V6		4	/* Virtex6 */
+#define XHI_DEV_FAMILY_S6		5	/* Spartan6 */
+#define XHI_DEV_FAMILY_K7		7	/* Kintex7 */
+#define XHI_DEV_FAMILY_V7		8	/* Virtex7 */
+#define XHI_DEV_FAMILY_A7		9	/* Artix7 */
+#define XHI_DEV_FAMILY_ZYNQ		10	/* Zynq */
+#define XHI_DEV_FAMILY_K8		11	/* Zynq */
+
+
+#if ((XHI_FPGA_FAMILY == XHI_DEV_FAMILY_K7) ||\
+(XHI_FPGA_FAMILY == XHI_DEV_FAMILY_A7) ||\
+(XHI_FPGA_FAMILY == XHI_DEV_FAMILY_V7) ||\
+(XHI_FPGA_FAMILY == XHI_DEV_FAMILY_K8) ||\
+(XHI_FPGA_FAMILY == XHI_DEV_FAMILY_ZYNQ))
+
+#define XHI_DEV_FAMILY_7SERIES	6	/* 7 SERIES */
+
+#define XHI_FAMILY XHI_DEV_FAMILY_7SERIES
+
+#else
+
+#define XHI_FAMILY XHI_FPGA_FAMILY
+
+
+#endif
+
+
+
+/**
+ * @name Configuration Type1/Type2 packet headers masks
+ * @{
+ */
+#define XHI_TYPE_MASK			0x7
+#define XHI_REGISTER_MASK		0x1F
+#define XHI_OP_MASK				0x3
+
+#if XHI_FAMILY == XHI_DEV_FAMILY_S6
+
+#define XHI_WORD_COUNT_MASK_TYPE_1	0x1F
+
+#define XHI_TYPE_SHIFT			13
+#define XHI_REGISTER_SHIFT		5
+#define XHI_OP_SHIFT			11
+
+#else
+
+#define XHI_WORD_COUNT_MASK_TYPE_1	0x7FF
+#define XHI_WORD_COUNT_MASK_TYPE_2	0x07FFFFFF
+
+#define XHI_TYPE_SHIFT			29
+#define XHI_REGISTER_SHIFT		13
+#define XHI_OP_SHIFT			27
+
+#endif
+
+#define XHI_TYPE_1			1
+#define XHI_TYPE_2			2
+#define XHI_OP_WRITE			2
+#define XHI_OP_READ			1
+
+/* @} */
+
+#if XHI_FAMILY == XHI_DEV_FAMILY_S6
+/*
+ * Addresses of the Configuration Registers
+ */
+
+#define XHI_CRC				0
+#define XHI_FAR_MAJ			1
+#define XHI_FAR_MIN			2
+#define XHI_FDRI			3
+#define XHI_FDRO			4
+#define XHI_CMD				5
+#define XHI_CTL				6
+#define XHI_MASK			7
+#define XHI_STAT			8
+#define XHI_LOUT			9
+#define XHI_COR1			10
+#define XHI_COR2			11
+#define XHI_PWRDN_REG			12
+#define XHI_FLR				13
+#define XHI_IDCODE			14
+#define XHI_CWDT			15
+#define XHI_HC_OPT_REG			16
+
+#define XHI_CSBO			18
+#define XHI_GENERAL1			19
+#define XHI_GENERAL2			20
+#define XHI_GENERAL3			21
+#define XHI_GENERAL4			22
+#define XHI_GENERAL5			23
+#define XHI_MODE_REG			24
+#define XHI_PU_GWE			25
+#define XHI_PU_GTS			26
+#define XHI_MFWR			27
+#define XHI_CCLK_FREQ			28
+#define XHI_SEU_OPT			29
+#define XHI_EXP_SIGN			30
+#define XHI_RDBK_SIGN			31
+#define XHI_BOOTSTS			32
+#define XHI_EYE_MASK			33
+#define CBC_REG				34
+
+#define XHI_NUM_REGISTERS		35 /* Note that there is skip at
+					    * number 17. There is no register
+					    * at with this number */
+
+#else
+/*
+ * Addresses of the Configuration Registers
+ */
+#define XHI_CRC				0
+#define XHI_FAR				1
+#define XHI_FDRI			2
+#define XHI_FDRO			3
+#define XHI_CMD				4
+#define XHI_CTL				5
+#define XHI_MASK			6
+#define XHI_STAT			7
+#define XHI_LOUT			8
+#define XHI_COR				9
+#define XHI_MFWR			10
+#define XHI_CBC				11
+#define XHI_IDCODE			12
+#define XHI_AXSS			13
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
+#define XHI_NUM_REGISTERS           14
+#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) || \
+	(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+	/* Virtex5 or Virtex6 or Kintex 7*/
+#define XHI_C0R_1			14
+#define XHI_CSOB			15
+#define XHI_WBSTAR			16
+#define XHI_TIMER			17
+#define XHI_BOOTSTS			22
+#define XHI_CTL_1			24
+#define XHI_NUM_REGISTERS		25 /* Note that the register numbering
+					    * is not sequential in V5/V6 and
+					    *there are gaps */
+#define XHI_COR_1			14
+#endif
+#endif
+/**
+ * @name Frame Address Register mask(s)
+ * @{
+ */
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
+#define XHI_FAR_BOTTOM_MASK		0x1
+#define XHI_FAR_BLOCK_MASK		0x7
+#define XHI_FAR_MAJOR_FRAME_MASK	0xFF
+#define XHI_FAR_HCLKROW_MASK		0x1F
+#define XHI_FAR_MINOR_FRAME_MASK	0xFF
+#define XHI_FAR_COLUMN_MASK		0xFF
+#define XHI_FAR_MINOR_MASK		0x3F
+#define XHI_FAR_BOTTOM_SHIFT		22
+#define XHI_FAR_BLOCK_SHIFT		19
+#define XHI_FAR_MAJOR_FRAME_SHIFT	17
+#define XHI_FAR_HCLKROW_SHIFT		14
+#define XHI_FAR_MINOR_FRAME_SHIFT	9
+#define XHI_FAR_COLUMN_SHIFT		6
+#define XHI_FAR_MINOR_SHIFT		0
+
+/*
+ * Address Block Types in the  Frame Address Register
+ */
+#define XHI_FAR_CLB_BLOCK		0 /**< CLB/IO/CLK Block */
+#define XHI_FAR_BRAM_BLOCK		1 /**< Block RAM interconnect */
+#define XHI_FAR_BRAM_INT_BLOCK		2 /**< Block RAM content */
+
+#elif ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) || \
+	(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+	/* Virtex5 or Virtex6 */
+#define XHI_FAR_BLOCK_MASK		0x7
+#define XHI_FAR_TOP_BOTTOM_MASK		0x1
+#define XHI_FAR_MAJOR_FRAME_MASK	0xFF
+#define XHI_FAR_ROW_ADDR_MASK		0x1F
+#define XHI_FAR_MINOR_FRAME_MASK	0xFF
+#define XHI_FAR_COLUMN_ADDR_MASK	0xFF
+#define XHI_FAR_MINOR_ADDR_MASK		0x7F
+#define XHI_FAR_BLOCK_SHIFT		21
+#define XHI_FAR_TOP_BOTTOM_SHIFT	20
+#define XHI_FAR_MAJOR_FRAME_SHIFT	17
+#define XHI_FAR_ROW_ADDR_SHIFT		15
+#define XHI_FAR_MINOR_FRAME_SHIFT	9
+#define XHI_FAR_COLUMN_ADDR_SHIFT	7
+#define XHI_FAR_MINOR_ADDR_SHIFT	0
+
+/*
+ * Address Block Types in the  Frame Address Register
+ */
+#define XHI_FAR_CLB_BLOCK		0 /**< CLB/IO/CLK Block */
+#define XHI_FAR_BRAM_BLOCK		1 /**< Block RAM interconnect */
+
+#endif
+/* @} */
+
+/*
+ * Configuration Commands
+ */
+#define XHI_CMD_NULL			0
+#define XHI_CMD_WCFG			1
+#define XHI_CMD_MFW			2
+#if XHI_FAMILY == XHI_DEV_FAMILY_S6
+#define XHI_CMD_LFRM			3
+#else
+#define XHI_CMD_DGHIGH			3
+#endif
+#define XHI_CMD_RCFG			4
+#define XHI_CMD_START			5
+#define XHI_CMD_RCAP			6
+#define XHI_CMD_RCRC			7
+#define XHI_CMD_AGHIGH			8
+#define XHI_CMD_SWITCH			9
+#define XHI_CMD_GRESTORE		10
+#define XHI_CMD_SHUTDOWN		11
+#if (XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5) || \
+	(XHI_FAMILY == XHI_DEV_FAMILY_V6)  || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)
+#define XHI_CMD_GCAPTURE		12
+#endif
+#define XHI_CMD_DESYNCH			13
+
+#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+#define XHI_CMD_IPROG			14
+#endif
+
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) || \
+	(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+	/* Virtex5 or Virtex6 */
+#define XHI_CMD_IPROG			15
+#define XHI_CMD_CRCC			16
+#define XHI_CMD_LTIMER			17
+#endif
+#define XHI_TYPE_2_READ 		((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
+					(XHI_OP_READ << XHI_OP_SHIFT))
+
+#define XHI_TYPE_2_WRITE 		( (XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
+					(XHI_OP_WRITE << XHI_OP_SHIFT) )
+
+#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+
+#define XHI_SYNC_PACKET1		0xAA99
+#define XHI_SYNC_PACKET2		0x5566
+#define XHI_DUMMY_PACKET		0xFFFF
+#define XHI_NOOP_PACKET			0x2000
+#define XHI_TYPE1_WRITE			(XHI_TYPE_1 << XHI_TYPE_SHIFT) | \
+					((XHI_OP_WRITE << XHI_OP_SHIFT))
+
+#define XHI_TYPE2_CNT_MASK		0x07FFFFFF
+
+#define XHI_TYPE_1_PACKET_MAX_WORDS 	32
+
+#define XHI_DEVICE_ID_READ		0x29C2
+#define XHI_BLOCK_SHIFT			12
+#define XHI_ROW_SHIFT			8
+#define XHI_COR1_DEFAULT		0x3d10
+#define XHI_COR2_DEFAULT		0x9EE
+#else
+/*
+ * Packet constants
+ */
+#define XHI_SYNC_PACKET			0xAA995566
+#define XHI_DUMMY_PACKET		0xFFFFFFFF
+#define XHI_DEVICE_ID_READ		0x28018001
+#define XHI_NOOP_PACKET			(XHI_TYPE_1 << XHI_TYPE_SHIFT)
+
+#define XHI_TYPE_1_PACKET_MAX_WORDS 	2047
+#define XHI_TYPE_1_HEADER_BYTES		4
+#define XHI_TYPE_2_HEADER_BYTES		8
+
+
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V4) || (XHI_FAMILY == XHI_DEV_FAMILY_V5))
+#define XHI_NUM_FRAME_BYTES		164  /* Number of bytes in a frame */
+#define XHI_NUM_FRAME_WORDS		41   /* Number of Words in a frame */
+#define XHI_NUM_WORDS_FRAME_INCL_NULL_FRAME  83 /* Num of Words in a frame read
+						 * from the device including
+						 * the NULL frame and an extra
+						 * 32 bit word
+						 */
+#endif
+#endif
+
+/* Virtex6 or 7 SERIES */
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V6) || (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+#define XHI_NUM_FRAME_BYTES		324  /* Number of bytes in a frame */
+#define XHI_NUM_FRAME_WORDS		81   /* Number of Words in a frame */
+#define XHI_NUM_WORDS_FRAME_INCL_NULL_FRAME  162 /* Num of Words in a frame read
+						 * from the device including
+						 * the NULL frame
+						 */
+#endif
+
+
+#if XHI_FAMILY == XHI_DEV_FAMILY_S6 /* Spartan6 */
+#define XHI_NUM_FRAME_BYTES		130  /* Number of bytes in a frame */
+#define XHI_NUM_FRAME_WORDS		65   /* Number of Words in a frame */
+#define XHI_NUM_WORDS_FRAME_INCL_NULL_FRAME  131 /* Num of Words in a frame read
+						 * from the device including
+						 * the NULL frame
+						 */
+#endif
+
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
+
+#define XHI_GCLK_FRAMES             	3
+#define XHI_IOB_FRAMES              	30
+#define XHI_DSP_FRAMES              	21
+#define XHI_CLB_FRAMES              	22
+#define XHI_BRAM_FRAMES             	64
+#define XHI_BRAM_INT_FRAMES         	20
+
+#elif XHI_FAMILY == XHI_DEV_FAMILY_V5 /* Virtex5  */
+
+#define XHI_GCLK_FRAMES             	4
+#define XHI_IOB_FRAMES              	54
+#define XHI_DSP_FRAMES              	28
+#define XHI_CLB_FRAMES              	36
+#define XHI_BRAM_FRAMES             	64
+#define XHI_BRAM_INT_FRAMES         	30
+
+#endif
+
+
+/* Device Resources */
+#define CLB				0
+#define DSP				1
+#define BRAM				2
+#define BRAM_INT			3
+#define IOB				4
+#define IOI				5
+#define CLK				6
+#define MGT				7
+
+/*
+ * The number of words reserved for the header
+ */
+#define XHI_HEADER_BUFFER_WORDS		20
+#define XHI_HEADER_BUFFER_BYTES		(XHI_HEADER_BUFFER_WORDS << 2)
+
+/*
+ * CLB major frames start at 3 for the first column (since we are using
+ * column numbers that start at 1, when the column is added to this offset,
+ * that first one will be 3 as required.
+ */
+#define XHI_CLB_MAJOR_FRAME_OFFSET	2
+
+/*
+ * Constant to use for CRC check when CRC has been disabled
+ */
+#define XHI_DISABLED_AUTO_CRC		0x0000DEFC
+#define XHI_DISABLED_AUTO_CRC_ONE	0x9876
+#define XHI_DISABLED_AUTO_CRC_TWO	0xDEFC
+
+/*
+ * Major Row Offset
+ */
+#define XHI_CLB_MAJOR_ROW_OFFSET 	96+(32*XHI_HEADER_BUFFER_WORDS)-1
+
+/*
+ * Number of times to poll the Status Register
+ */
+#define XHI_MAX_RETRIES			1000
+
+/*
+ * Mask for the Device ID read from the ID code Register
+ */
+#define XHI_DEVICE_ID_CODE_MASK		0x0FFFFFFF
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Generates a Type 1 packet header that reads back the requested Configuration
+* register.
+*
+* @param	Register is the address of the register to be read back.
+*
+* @return	Type 1 packet header to read the specified register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XHwIcap_Type1Read(Register) \
+	( (XHI_TYPE_1 << XHI_TYPE_SHIFT) | (Register << XHI_REGISTER_SHIFT) | \
+	(XHI_OP_READ << XHI_OP_SHIFT) )
+
+/****************************************************************************/
+/**
+*
+* Generates a Type 2 packet header that reads back the requested Configuration
+* register.
+*
+* @param	Register is the address of the register to be read back.
+*
+* @return	Type 1 packet header to read the specified register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XHwIcap_Type2Read(Register) \
+	( XHI_TYPE_2_READ | (Register << XHI_REGISTER_SHIFT))
+
+/****************************************************************************/
+/**
+*
+* Generates a Type 1 packet header that writes to the requested Configuration
+* register.
+*
+* @param	Register is the address of the register to be written to.
+*
+* @return	Type 1 packet header to write the specified register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XHwIcap_Type1Write(Register) \
+	( (XHI_TYPE_1 << XHI_TYPE_SHIFT) | (Register << XHI_REGISTER_SHIFT) | \
+	(XHI_OP_WRITE << XHI_OP_SHIFT) )
+
+/****************************************************************************/
+/**
+*
+* Generates a Type 2 packet header that writes to the requested Configuration
+* register.
+*
+* @param	Register is the address of the register to be written to.
+*
+* @return	Type 1 packet header to write the specified register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XHwIcap_Type2Write(Register) \
+	( (XHI_TYPE_2 << XHI_TYPE_SHIFT) | (Register << XHI_REGISTER_SHIFT) | \
+	(XHI_OP_WRITE << XHI_OP_SHIFT) )
+
+#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
+/****************************************************************************/
+/**
+*
+* Generates a Type 1 packet header that is written to the Frame Address
+* Register (FAR) for a Virtex4 device.
+*
+* @param	Top - top (0) or bottom (1) half of device
+* @param	Block - Address Block Type (CLB or BRAM address space)
+* @param	HClkRow - H Clock row
+* @param	MajorAddress - CLB or BRAM column
+* @param	MinorAdderss - Frame within column
+*
+* @return	Type 1 packet header to write the FAR
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XHwIcap_SetupFarV4(Top, Block, HClkRow, MajorAddress, MinorAddress)  \
+	((Top << XHI_FAR_BOTTOM_SHIFT) | \
+	(Block << XHI_FAR_BLOCK_SHIFT) | \
+	(HClkRow << XHI_FAR_HCLKROW_SHIFT) | \
+	(MajorAddress << XHI_FAR_COLUMN_SHIFT) | \
+	(MinorAddress << XHI_FAR_MINOR_SHIFT))
+#endif
+
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) || \
+	(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES))
+/****************************************************************************/
+/**
+*
+* Generates a Type 1 packet header that is written to the Frame Address
+* Register (FAR) for a Virtex5 device.
+*
+* @param	Block - Address Block Type (CLB or BRAM address space)
+* @param	Top - top (0) or bottom (1) half of device
+* @param	Row - Row Address
+* @param	ColumnAddress - CLB or BRAM column
+* @param	MinorAddress - Frame within a column
+*
+* @return	Type 1 packet header to write the FAR
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XHwIcap_SetupFarV5(Top, Block, Row, ColumnAddress, MinorAddress)  \
+	(Block << XHI_FAR_BLOCK_SHIFT) | \
+	((Top << XHI_FAR_TOP_BOTTOM_SHIFT) | \
+	(Row << XHI_FAR_ROW_ADDR_SHIFT) | \
+	(ColumnAddress << XHI_FAR_COLUMN_ADDR_SHIFT) | \
+	(MinorAddress << XHI_FAR_MINOR_ADDR_SHIFT))
+#endif
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions ****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_intr.c b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_intr.c
new file mode 100755
index 00000000..ba341067
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_intr.c
@@ -0,0 +1,194 @@
+/******************************************************************************
+*
+* Copyright (C) 2007 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xhwicap_intr.c
+*
+* This file contains interrupt handling API functions of the HwIcap device.
+*
+* Refer to xhwicap.h header file and device specification for more information.
+*
+* @note
+*
+* Calling the interrupt functions without including the interrupt component will
+* result in asserts if asserts are enabled, and will result in a unpredictable
+* behavior if the asserts are not enabled.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 2.00a  sv    09/22/07 First release
+* 4.00a  hvm   12/1/09  Updated with HAL phase 1 changes
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xhwicap.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Sets the status callback function, the status handler, which the driver calls
+* when it encounters conditions that should be reported to the higher layer
+* software. The handler executes in an interrupt context, so it must minimize
+* the amount of processing performed such as transferring data to a thread
+* context. One of the following status events is passed to the status handler.
+* <pre>
+*
+* </pre>
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPtr is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should do its work
+* quickly and queue potentially time-consuming work to a task-level thread.
+*
+******************************************************************************/
+void XHwIcap_SetInterruptHandler(XHwIcap * InstancePtr, void *CallBackRef,
+			   		XHwIcap_StatusHandler FuncPtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = FuncPtr;
+	InstancePtr->StatusRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* The interrupt handler for HwIcap interrupts. This function must be connected
+* by the user to an interrupt source.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+*
+* @return	None.
+*
+* @note		The interrupts are being used only while writing data to the
+*		ICAP device. The reading of the data from the ICAP device is
+*		done in polled mode.
+*		In a worst case scenario the interrupt handler can
+*		be busy writing large amount of data to the Write FIFO.
+*
+******************************************************************************/
+void XHwIcap_IntrHandler(void *InstancePtr)
+{
+	XHwIcap *HwIcapPtr = (XHwIcap *) InstancePtr;
+	u32 IntrStatus;
+	u32 WrFifoVacancy;
+
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+
+	/*
+	 * Get the Interrupt status.
+	 */
+	IntrStatus = XHwIcap_IntrGetStatus(HwIcapPtr);
+
+	if (IntrStatus & XHI_IPIXR_WRP_MASK) {
+
+		/*
+		 * A transmit has just completed. Check for more data
+		 * to transmit.
+		 */
+		if (HwIcapPtr->RemainingWords > 0) {
+
+			/*
+			 * Fill the FIFO with as many words as it will take (or
+			 * as many as we have to write). We can use the Write
+			 * FIFO vacancy to know if the device can take more data.
+			 */
+			WrFifoVacancy = XHwIcap_GetWrFifoVacancy(HwIcapPtr);
+			while ((WrFifoVacancy != 0) &&
+			       (HwIcapPtr->RemainingWords > 0)) {
+				XHwIcap_FifoWrite(HwIcapPtr,
+						*HwIcapPtr->SendBufferPtr);
+
+				HwIcapPtr->RemainingWords--;
+				WrFifoVacancy--;
+				HwIcapPtr->SendBufferPtr++;
+			}
+
+			XHwIcap_StartConfig(HwIcapPtr);
+		}
+		else {
+
+			if (HwIcapPtr->RequestedWords != 0) {
+
+				/*
+				 * No more data to send. Disable the interrupts
+				 * by disabling the Global Interrupts.
+				 * Inform the upper layer software that the
+				 * transfer is done.
+				 */
+				XHwIcap_IntrGlobalDisable(HwIcapPtr);
+				HwIcapPtr->IsTransferInProgress = FALSE;
+				HwIcapPtr->StatusHandler(HwIcapPtr->StatusRef,
+						    XST_HWICAP_WRITE_DONE,
+						    HwIcapPtr->RequestedWords);
+			}
+		}
+	}
+
+
+	/*
+	 * Clear the Interrupt status.
+	 */
+	XHwIcap_IntrClear(HwIcapPtr, IntrStatus);
+
+}
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_l.h b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_l.h
new file mode 100755
index 00000000..11c3b0d5
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_l.h
@@ -0,0 +1,413 @@
+/******************************************************************************
+*
+* Copyright (C) 2007 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_l.h
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xhwicap.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 2.00a sv   09/28/07 First release for the FIFO mode
+* 3.00a sv   11/28/08 Added Abort bit definition in the Control Register
+*		      Removed XHI_WFO_MAX_VACANCY and XHI_RFO_MAX_OCCUPANCY
+*		      definitions.
+* 3.01a sv   10/21/09 Corrected the IDCODE definitions for some of the
+*                     V5 FX parts.
+* 4.00a hvm  11/30/09 Added support for V6 and updated with HAL phase 1
+*		      modifications
+* 5.00a hvm  02/04/10 Added S6 Support
+* 5.03a hvm  15/4/11  Updated with V6 CXT device definitions.
+* 6.00a hvm  08/01/11 Updated with K7 device Ids.
+* 7.00a bss  03/14/12 Added EOS mask and Hang mask CR CR 637538
+*		      Added Virtex 7 and Zynq Idcodes - CR 647140, CR 643295
+*
+* 8.00a bss  06/20/12 Deleted Hang mask definition as per CR 656162
+* 9.0   bss  02/20/14 Added Kintex 8 and Virtex72000T device Idcodes.
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XHWICAP_L_H_ /* prevent circular inclusions */
+#define XHWICAP_L_H_ /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include <xil_types.h>
+#include <xil_assert.h>
+#include "xil_io.h"
+#include "xhwicap_family.h"
+/************************** Constant Definitions ****************************/
+
+/******************************************************************/
+/** @name Register Map
+ *
+ * Register offsets for the XHwIcap device.
+ * @{
+ */
+#define XHI_GIER_OFFSET		0x1C  /**< Device Global Interrupt Enable Reg */
+#define XHI_IPISR_OFFSET	0x20  /**< Interrupt Status Register */
+#define XHI_IPIER_OFFSET	0x28  /**< Interrupt Enable Register */
+#define XHI_WF_OFFSET		0x100 /**< Write FIFO */
+#define XHI_RF_OFFSET		0x104 /**< Read FIFO */
+#define XHI_SZ_OFFSET		0x108 /**< Size Register */
+#define XHI_CR_OFFSET		0x10C /**< Control Register */
+#define XHI_SR_OFFSET		0x110 /**< Status Register */
+#define XHI_WFV_OFFSET		0x114 /**< Write FIFO Vacancy Register */
+#define XHI_RFO_OFFSET		0x118 /**< Read FIFO Occupancy Register */
+
+/* @} */
+
+
+/** @name Device Global Interrupt Enable Register (GIER) bit definitions
+ *
+ * @{
+ */
+#define XHI_GIER_GIE_MASK      0x80000000 /**< Global Interrupt enable Mask */
+
+/* @} */
+
+/** @name HwIcap Device Interrupt Status/Enable Registers
+ *
+ * <b> Interrupt Status Register (IPISR) </b>
+ *
+ * This register holds the interrupt status flags for the device. These
+ * bits are toggle on write.
+ *
+ * <b> Interrupt Enable Register (IPIER) </b>
+ *
+ * This register is used to enable interrupt sources for the device.
+ * Writing a '1' to a bit in this register enables the corresponding Interrupt.
+ * Writing a '0' to a bit in this register disables the corresponding Interrupt.
+ *
+ * IPISR/IPIER registers have the same bit definitions and are only defined
+ * once.
+ * @{
+ */
+#define XHI_IPIXR_RFULL_MASK	0x00000008 /**< Read FIFO Full */
+#define XHI_IPIXR_WEMPTY_MASK	0x00000004 /**< Write FIFO Empty */
+#define XHI_IPIXR_RDP_MASK	0x00000002 /**< Read FIFO half full */
+#define XHI_IPIXR_WRP_MASK	0x00000001 /**< Write FIFO half full */
+#define XHI_IPIXR_ALL_MASK	0x0000000F /**< Mask of all interrupts */
+
+/* @} */
+
+/** @name Control Register (CR)
+ *
+ * @{
+ */
+#define XHI_CR_SW_ABORT_MASK	0x00000010 /**< Abort current ICAP Read/Write */
+#define XHI_CR_SW_RESET_MASK	0x00000008 /**< SW Reset Mask */
+#define XHI_CR_FIFO_CLR_MASK	0x00000004 /**< FIFO Clear Mask */
+#define XHI_CR_READ_MASK	0x00000002 /**< Read from ICAP to FIFO */
+#define XHI_CR_WRITE_MASK	0x00000001 /**< Write from FIFO to ICAP */
+
+/* @} */
+
+
+/** @name Status Register (SR)
+ *
+ * @{
+ */
+#define XHI_SR_CFGERR_N_MASK	0x00000100 /**< Config Error Mask */
+#define XHI_SR_DALIGN_MASK	0x00000080 /**< Data Alignment Mask */
+#define XHI_SR_RIP_MASK		0x00000040 /**< Read back Mask */
+#define XHI_SR_IN_ABORT_N_MASK	0x00000020 /**< Select Map Abort Mask */
+#define XHI_SR_DONE_MASK	0x00000001 /**< Done bit Mask */
+#define XHI_SR_EOS_MASK 	0x00000004 /**< EOS bit Mask */
+
+/* @} */
+
+/** @name IDCODE's for the Virtex4 Devices.
+ *
+ * @{
+ */
+#define XHI_XC4VLX15	0x01658093
+#define XHI_XC4VLX25	0x0167C093
+#define XHI_XC4VLX40	0x016A4093
+#define XHI_XC4VLX60	0x016B4093
+#define XHI_XC4VLX80	0x016D8093
+#define XHI_XC4VLX100	0x01700093
+#define XHI_XC4VLX160	0x01718093
+#define XHI_XC4VLX200	0x01734093
+
+#define XHI_XC4VSX25	0x02068093
+#define XHI_XC4VSX35	0x02088093
+#define XHI_XC4VSX55	0x020B0093
+
+#define XHI_XC4VFX12	0x01E58093
+#define XHI_XC4VFX20	0x01E64093
+#define XHI_XC4VFX40	0x01E8C093
+#define XHI_XC4VFX60	0x01EB4093
+#define XHI_XC4VFX100	0x01EE4093
+#define XHI_XC4VFX140	0x01F14093
+
+#define XHI_V4_NUM_DEVICES	17
+
+/* @} */
+
+/** @name IDCODE's for the Virtex5 Devices.
+ *
+ * @{
+ */
+#define XHI_XC5VLX30	0x0286E093
+#define XHI_XC5VLX50	0x02896093
+#define XHI_XC5VLX85	0x028AE093
+#define XHI_XC5VLX110	0x028D6093
+#define XHI_XC5VLX220	0x0290C093
+#define XHI_XC5VLX330	0x0295C093
+
+#define XHI_XC5VLX30T	0x02A6E093
+#define XHI_XC5VLX50T	0x02A96093
+#define XHI_XC5VLX85T	0x02AAE093
+#define XHI_XC5VLX110T	0x02AD6093
+#define XHI_XC5VLX220T	0x02B0C093
+#define XHI_XC5VLX330T	0x02B5C093
+
+#define XHI_XC5VSX35T	0x02E72093
+#define XHI_XC5VSX50T	0x02E9A093
+#define XHI_XC5VSX95T	0x02ECE093
+
+#define XHI_XC5VFX30T	0x03276093
+#define XHI_XC5VFX70T	0x032C6093
+#define XHI_XC5VFX100T	0x032D8093
+#define XHI_XC5VFX130T	0x03300093
+#define XHI_XC5VFX200T	0x03334093
+
+#define XHI_V5_NUM_DEVICES	20
+/* @} */
+
+/** @name IDCODE's for the Virtex6 Devices.
+ *
+ * @{
+ */
+
+#define XHI_XC6VHX250T	0x042A2093
+#define XHI_XC6VHX255T	0x042A4093
+#define XHI_XC6VHX380T	0x042A8093
+#define XHI_XC6VHX565T	0x042AC093
+
+#define XHI_XC6VLX75T	0x04244093
+#define XHI_XC6VLX130T	0x0424A093
+#define XHI_XC6VLX195T	0x0424C093
+#define XHI_XC6VLX240T 	0x04250093
+#define XHI_XC6VLX365T	0x04252093
+#define XHI_XC6VLX550T	0x04256093
+#define XHI_XC6VLX760	0x0423A093
+#define XHI_XC6VSX315T	0x04286093
+#define XHI_XC6VSX475T	0x04288093
+#define XHI_XC6VCX75T	0x042C4093
+#define XHI_XC6VCX130T	0x042CA093
+#define XHI_XC6VCX195T	0x042CC093
+#define XHI_XC6VCX240T 	0x042D0093
+
+#define XHI_V6_NUM_DEVICES 	17
+
+/* @} */
+
+/** @name IDCODE's for the Spartan6 Devices.
+ *
+ * @{
+ */
+
+#define XHI_XC6SLX4	0x04000093
+#define XHI_XC6SLX9	0x04001093
+#define XHI_XC6SLX16	0x04002093
+#define XHI_XC6SLX25	0x04004093
+#define XHI_XC6SLX25T	0x04024093
+#define XHI_XC6SLX45	0x04008093
+#define XHI_XC6SLX45T	0x04028093
+#define XHI_XC6SLX75	0x0400E093
+#define XHI_XC6SLX75T	0x0402E093
+#define XHI_XC6SLX100	0x04011093
+#define XHI_XC6SLX100T	0x04031093
+#define XHI_XC6SLX150	0x0401D093
+#define XHI_XC6SLX150T	0x0403D093
+
+#define XHI_S6_NUM_DEVICES	13
+
+/* @} */
+
+/** @name IDCODE's for the Kintex7 Devices.
+ *
+ * @{
+ */
+
+#define XHI_XC7K30T	0x03642093
+#define XHI_XC7K70T	0x03647093
+#define XHI_XC7K160T	0x0364C093
+#define XHI_XC7K325T	0x03651093
+#define XHI_XC7K410T	0x03656093
+#define XHI_XC7K235T	0x0365B093
+#define XHI_XC7K125T	0x0365C093
+#define XHI_XC7K290T	0x0365D093
+#define XHI_XC7K355T	0x03747093
+#define XHI_XC7K420T	0x0374C093
+#define XHI_XC7K480T	0x03751093
+
+#define XHI_K7_NUM_DEVICES      11
+
+/* @} */
+
+
+/** @name IDCODE's for the Virtex7 Devices.
+ *
+ * @{
+ */
+
+#define XHI_XC7VX80T		0x03680093
+#define XHI_XC7VX82T		0x03681093
+#define XHI_XC7VX330T		0x03667093
+#define XHI_XC7VX415T		0x03682093
+#define XHI_XC7V450T		0x0366C093
+#define XHI_XC7VX485T		0x03687093
+#define XHI_XC7VX550T		0x03692093
+#define XHI_XC7V585T		0x03671093
+#define XHI_XC7VX690T		0x03691093
+#define XHI_XC7VX980T		0x03696093
+#define XHI_XC7VX2000T_SLR0	0x036B3093
+#define XHI_XC7VX2000T_SLR1	0x036A2093
+#define XHI_XC7VX2000T_SLR2	0x036A4093
+#define XHI_XC7VX2000T_SLR3	0x036A6093
+
+
+#define XHI_V7_NUM_DEVICES      14
+
+/* @} */
+
+/** @name IDCODE's for the Artix7 Devices.
+ *
+ * @{
+ */
+
+#define XHI_XC7A15		0x03627093
+#define XHI_XC7A30T		0x0362D093
+#define XHI_XC7A50T		0x0362C093
+#define XHI_XC7A100T		0x03631093
+#define XHI_XC7A200T		0x03636093
+#define XHI_XC7A350T		0x0363B093
+
+#define XHI_A7_NUM_DEVICES      6
+
+/* @} */
+
+/** @name IDCODE's for the Zynq Devices.
+ *
+ * @{
+ */
+
+#define XHI_XC7Z010		0x03722093
+#define XHI_XC7Z020		0x03727093
+#define XHI_XC7Z030		0x0372C093
+#define XHI_XC7Z045		0x03731093
+
+#define XHI_ZYNQ_NUM_DEVICES      4
+
+/* @} */
+
+/** @name IDCODE's for the Kintex8 Devices.
+ *
+ * @{
+ */
+#define XHI_XCKU040T	0x03822093
+
+#define XHI_K8_NUM_DEVICES      1
+
+/* @} */
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+#define XHwIcap_In32 Xil_In32
+
+#define XHwIcap_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+*
+* Read from the specified HwIcap device register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XHwIcap_ReadReg(u32 BaseAddress, u32 RegOffset);
+*
+******************************************************************************/
+#define XHwIcap_ReadReg(BaseAddress, RegOffset) \
+	XHwIcap_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+*
+* Write to the specified HwIcap device register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XHwIcap_WriteReg(u32 BaseAddress, u32 RegOffset,
+*					u32 RegisterValue);
+******************************************************************************/
+#define XHwIcap_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XHwIcap_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif         /* end of protection macro */
+
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_selftest.c b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_selftest.c
new file mode 100755
index 00000000..d19a293d
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_selftest.c
@@ -0,0 +1,154 @@
+/******************************************************************************
+*
+* Copyright (C) 2007 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xhwicap_selftest.c
+*
+* This file contains a diagnostic self test function for the XHwIcap driver.
+* The self test functions writes to the Interrupt Enable Register and reads it
+* back for comparison.
+*
+* See xhwicap.h for more information.
+*
+* @note	None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a sv     09/17/07 First release
+* 4.00a hvm    12/1/09  Updated with HAL phase 1 modifications
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xhwicap.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. The test
+*	- Writes to the Interrupt Enable Register and reads it back
+*	for comparison.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+*
+* @return
+*		- XST_SUCCESS if the value read from the register
+*		is the same as the value written.
+*		- XST_FAILURE otherwise
+*
+* @note		None.
+*
+******************************************************************************/
+int XHwIcap_SelfTest(XHwIcap *InstancePtr)
+{
+	int Status = XST_SUCCESS;
+	u32 IeRegister;
+	u32 DgieRegister;
+
+
+	/*
+	 * Assert the argument
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * Save a copy of the Global Interrupt Enable Register and Interrupt
+	 * Enable Register before writing them so that they can be restored.
+	 */
+	DgieRegister = XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
+						XHI_GIER_OFFSET);
+	IeRegister = XHwIcap_IntrGetEnabled(InstancePtr);
+
+	/*
+	 * Disable the Global Interrupt
+	 */
+	XHwIcap_IntrGlobalDisable(InstancePtr);
+
+
+	/*
+	 * Disable/Enable the interrupts and then verify that the register
+	 * is read back correct.
+	 */
+	XHwIcap_IntrDisable(InstancePtr, XHI_IPIXR_ALL_MASK);
+	if (XHwIcap_IntrGetEnabled(InstancePtr) != 0x0) {
+		Status = XST_FAILURE;
+	}
+
+	XHwIcap_IntrEnable(InstancePtr, (XHI_IPIXR_WEMPTY_MASK |
+					XHI_IPIXR_RDP_MASK));
+	if (XHwIcap_IntrGetEnabled(InstancePtr) !=
+			(XHI_IPIXR_WEMPTY_MASK | XHI_IPIXR_RDP_MASK)) {
+		Status |= XST_FAILURE;
+	}
+
+	/*
+	 * Restore the Interrupt Enable Register to the value before the
+	 * test.
+	 */
+	XHwIcap_IntrDisable(InstancePtr, XHI_IPIXR_ALL_MASK);
+	if (IeRegister != 0) {
+		XHwIcap_IntrEnable(InstancePtr, IeRegister);
+	}
+
+
+	/*
+	 * Restore the Global Interrupt Enable Register to the value
+	 * before the test.
+	 */
+	XHwIcap_WriteReg(InstancePtr->HwIcapConfig.BaseAddress,
+				XHI_GIER_OFFSET, DgieRegister);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
diff --git a/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_sinit.c b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_sinit.c
new file mode 100755
index 00000000..42f47d75
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_sinit.c
@@ -0,0 +1,101 @@
+/******************************************************************************
+*
+* Copyright (C) 2007 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xhwicap_sinit.c
+*
+* This file contains the implementation of the XHwicap driver's static
+* initialization functionality.
+*
+* @note		None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 2.00a  sv  09/28/07 First release
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xhwicap.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XHwIcap_Config XHwIcap_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device for which the
+*		device configuration pointer is to be returned.
+*
+* @return
+*		- A pointer to the configuration found.
+*		- NULL if the specified device ID was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+XHwIcap_Config *XHwIcap_LookupConfig(u16 DeviceId)
+{
+
+	XHwIcap_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index=0; Index < XPAR_XHWICAP_NUM_INSTANCES; Index++) {
+		if (XHwIcap_ConfigTable[Index].DeviceId == DeviceId) {
+		CfgPtr = &XHwIcap_ConfigTable[Index];
+		break;
+		}
+	}
+
+	return CfgPtr;
+}
+
diff --git a/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_srp.c b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_srp.c
new file mode 100755
index 00000000..4867dee7
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_srp.c
@@ -0,0 +1,328 @@
+/******************************************************************************
+*
+* Copyright (C) 2003 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_srp.c
+*
+* This file contains the functions of the XHwIcap driver used to access the
+* configuration memory of the Xilinx FPGAs through the ICAP port.
+*
+* These APIs provide methods for reading and writing data, frames, and partial
+* bitstreams to the ICAP port. See xhwicap.h for a detailed description of the
+* driver.
+*
+* @note
+*
+* Only Virtex4, Virtex5, Virtex6, Spartan6 and kintex 7 devices are supported.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb  11/17/03 First release
+* 1.01a sv   03/03/07 V4 Updates.
+* 2.00a ecm  10/20/07 V5 Support
+* 4.00a hvm  11/30/09 Added support for V6 and updated with HAL phase 1
+*		      modifications
+* 5.00a hvm  2/25/10  Added support for S6
+* 5.00a hvm  5/21/10  Modified XHwIcap_GetConfigReg function for V4/V5/V6/S6
+*			command sequence. Added one extra NOP before the
+*			Type 1 read config register command and removed an
+*			extra NOP after the config register command.
+* 6.00a hvm  8/12/11  Added support for K7
+* 7.00a bss  03/14/12 ReadId API is added to desync after lock up during
+*			configuration CR 637538
+*
+* 8.00a bss  06/20/12 Deleted ReadId API as per CR 656162
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include <xil_types.h>
+#include <xil_assert.h>
+#include "xhwicap.h"
+
+/************************** Constant Definitions *****************************/
+
+#define DESYNC_COMMAND_SIZE	7 /* Number of words in the Desync command */
+#define CAPTURE_COMMAND_SIZE	7 /* Number of words in the Capture command */
+#if XHI_FAMILY == XHI_DEV_FAMILY_S6
+#define READ_CFG_REG_COMMAND_SIZE 8 /* Num of words in Read Config command */
+#else
+#define READ_CFG_REG_COMMAND_SIZE 7 /* Num of words in Read Config command */
+#endif
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Sends a DESYNC command to the ICAP port.
+*
+* @param	InstancePtr - a pointer to the XHwIcap instance to be worked on
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+******************************************************************************/
+int XHwIcap_CommandDesync(XHwIcap *InstancePtr)
+{
+	int Status;
+#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+	u16 FrameBuffer[DESYNC_COMMAND_SIZE];
+#else
+	u32 FrameBuffer[DESYNC_COMMAND_SIZE];
+#endif
+	u32 Index =0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Create the data to be written to the ICAP.
+	 */
+	FrameBuffer[Index++] = (XHwIcap_Type1Write(XHI_CMD) | 1);
+	FrameBuffer[Index++] = XHI_CMD_DESYNCH;
+	FrameBuffer[Index++] = XHI_DUMMY_PACKET;
+	FrameBuffer[Index++] = XHI_DUMMY_PACKET;
+
+
+	/*
+	 * Write the data to the FIFO and intiate the transfer of data present
+	 * in the FIFO to the ICAP device.
+	 */
+	Status = XHwIcap_DeviceWrite(InstancePtr, &FrameBuffer[0], Index);
+	if (Status != XST_SUCCESS)  {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+#if (XHI_FAMILY != XHI_DEV_FAMILY_S6)
+/****************************************************************************/
+/**
+*
+* Sends a CAPTURE command to the ICAP port.  This command captures all
+* of the flip flop states so they will be available during readback.
+* One can use this command instead of enabling the CAPTURE block in the
+* design.
+*
+* @param	InstancePtr is a pointer to the XHwIcap instance.
+*
+* @return	XST_SUCCESS or XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+int XHwIcap_CommandCapture(XHwIcap *InstancePtr)
+{
+	int Status;
+	u32 FrameBuffer[CAPTURE_COMMAND_SIZE];
+	u32 Index =0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Create the data to be written to the ICAP.
+	 */
+	FrameBuffer[Index++] = XHI_DUMMY_PACKET;
+	FrameBuffer[Index++] = XHI_SYNC_PACKET;
+#if ((XHI_FAMILY == XHI_DEV_FAMILY_V5) || (XHI_FAMILY == XHI_DEV_FAMILY_V6) \
+	|| (XHI_FAMILY == XHI_DEV_FAMILY_7SERIES ))
+	FrameBuffer[Index++] = XHI_NOOP_PACKET;
+#endif
+	FrameBuffer[Index++] = (XHwIcap_Type1Write(XHI_CMD) | 1);
+	FrameBuffer[Index++] = XHI_CMD_GCAPTURE;
+	FrameBuffer[Index++] =  XHI_DUMMY_PACKET;
+	FrameBuffer[Index++] =  XHI_DUMMY_PACKET;
+
+	/*
+	 * Write the data to the FIFO and intiate the transfer of data present
+	 * in the FIFO to the ICAP device.
+	 */
+	Status = XHwIcap_DeviceWrite(InstancePtr, &FrameBuffer[0], Index);
+	if (Status != XST_SUCCESS)  {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+#endif
+/****************************************************************************/
+/**
+ *
+ * This function returns the value of the specified configuration register.
+ *
+ * @param	InstancePtr is a pointer to the XHwIcap instance.
+ * @param	ConfigReg  is a constant which represents the configuration
+ *		register value to be returned. Constants specified in
+ *		xhwicap_i.h.
+ * 		Examples:  XHI_IDCODE, XHI_FLR.
+ * @param	RegData is the value of the specified configuration
+ *		register.
+ *
+ * @return	XST_SUCCESS or XST_FAILURE
+ *
+ * @note	This is a blocking call.
+ *
+ *****************************************************************************/
+u32 XHwIcap_GetConfigReg(XHwIcap *InstancePtr, u32 ConfigReg, u32 *RegData)
+{
+	int Status;
+	int EosRetries =0; /* Counter for checking EOS to become high */
+
+#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+	u16 FrameBuffer[READ_CFG_REG_COMMAND_SIZE];
+	u32 Retries =0;
+#else
+	u32 FrameBuffer[READ_CFG_REG_COMMAND_SIZE];
+#endif
+	u32 Index =0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Create the data to be written to the ICAP.
+	 */
+	FrameBuffer[Index++] = XHI_DUMMY_PACKET;
+
+#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+	FrameBuffer[Index++] = XHI_SYNC_PACKET1;
+	FrameBuffer[Index++] = XHI_SYNC_PACKET2;
+#else
+	FrameBuffer[Index++] = XHI_SYNC_PACKET;
+#endif
+	FrameBuffer[Index++] = XHI_NOOP_PACKET;
+	FrameBuffer[Index++] = XHI_NOOP_PACKET;
+
+#if (XHI_FAMILY == XHI_DEV_FAMILY_S6)
+	if (ConfigReg == XHI_IDCODE) {
+		FrameBuffer[Index++] = XHwIcap_Type1Read(ConfigReg) | 0x2;
+	}else {
+		FrameBuffer[Index++] = XHwIcap_Type1Read(ConfigReg) | 0x1;
+	}
+#else
+	FrameBuffer[Index++] = XHwIcap_Type1Read(ConfigReg) | 0x1;
+#endif
+
+	FrameBuffer[Index++] = XHI_NOOP_PACKET;
+	FrameBuffer[Index++] = XHI_NOOP_PACKET;
+
+	/*
+	 * Check for EOS bit of Status Register. EOS bit becomes high after
+	 * ICAP completes Start up sequence. Access to ICAP should start
+	 * only after EOS bit becomes high.
+	 */
+
+	while((!(XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
+			XHI_SR_OFFSET)& XHI_SR_EOS_MASK))) {
+
+		if(EosRetries < XHI_MAX_RETRIES) {
+			EosRetries++;
+		}
+		else {
+	   		return XST_FAILURE;
+		}
+
+	}
+
+	/*
+	 * Write the data to the FIFO and intiate the transfer of data present
+	 * in the FIFO to the ICAP device.
+	 */
+	Status = XHwIcap_DeviceWrite(InstancePtr, &FrameBuffer[0], Index);
+	if (Status != XST_SUCCESS)  {
+		return XST_FAILURE;
+	}
+
+	while (XHwIcap_IsDeviceBusy(InstancePtr) != FALSE);
+	while ((XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
+			XHI_CR_OFFSET)) & XHI_CR_WRITE_MASK);
+
+#if (XHI_FAMILY == XHI_DEV_FAMILY_V6) ||\
+(XHI_FAMILY == XHI_DEV_FAMILY_7SERIES)
+
+	/*
+	 * Read the Config Register using DeviceRead since
+	 * DeviceRead reads depending on ICAP Width for V6
+	 * and 7 series devices
+  	 */
+	XHwIcap_DeviceRead(InstancePtr, RegData, 1);
+
+#else
+
+	XHwIcap_SetSizeReg(InstancePtr, 1);
+
+	if (ConfigReg == XHI_IDCODE) {
+		XHwIcap_SetSizeReg(InstancePtr, 2);
+	}
+
+	XHwIcap_StartReadBack(InstancePtr);
+	while (XHwIcap_IsDeviceBusy(InstancePtr) != FALSE) {
+		Retries++;
+		if (Retries > XHI_MAX_RETRIES) {
+			return XST_FAILURE;
+		}
+	}
+	while ((XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
+						XHI_CR_OFFSET)) &
+						XHI_CR_READ_MASK);
+
+	/*
+	 * Return the Register value
+	 */
+	*RegData = XHwIcap_FifoRead(InstancePtr);
+
+	if (ConfigReg == XHI_IDCODE) {
+
+		*RegData = ((*RegData << 16) |
+						(XHwIcap_FifoRead(InstancePtr)));
+	}
+
+#endif
+	return XST_SUCCESS;
+}
+