From 0ede20560da27defe75ea596a4f8ffa17aea8222 Mon Sep 17 00:00:00 2001 From: Shubhrajyoti Datta Date: Wed, 19 Aug 2015 20:39:51 +0530 Subject: [PATCH] tft: Add 64-bit support Add support for 64 bit support Signed-off-by: Shubhrajyoti Datta Reviewed-by: Kedareswara rao Appana --- XilinxProcessorIPLib/drivers/tft/data/tft.mdd | 2 +- XilinxProcessorIPLib/drivers/tft/data/tft.tcl | 6 ++-- XilinxProcessorIPLib/drivers/tft/src/xtft.c | 30 ++++++++++++++----- XilinxProcessorIPLib/drivers/tft/src/xtft.h | 25 ++++++++++++---- XilinxProcessorIPLib/drivers/tft/src/xtft_g.c | 3 +- .../drivers/tft/src/xtft_hw.h | 8 +++++ 6 files changed, 56 insertions(+), 18 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/tft/data/tft.mdd b/XilinxProcessorIPLib/drivers/tft/data/tft.mdd index 6d665397..1ffd3867 100755 --- a/XilinxProcessorIPLib/drivers/tft/data/tft.mdd +++ b/XilinxProcessorIPLib/drivers/tft/data/tft.mdd @@ -37,7 +37,7 @@ BEGIN driver tft OPTION supported_peripherals = (axi_tft); OPTION driver_state = ACTIVE; OPTION copyfiles = all; - OPTION VERSION = 5.0; + OPTION VERSION = 6.0; OPTION NAME = tft; END driver diff --git a/XilinxProcessorIPLib/drivers/tft/data/tft.tcl b/XilinxProcessorIPLib/drivers/tft/data/tft.tcl index c67194d2..8b08b3a1 100755 --- a/XilinxProcessorIPLib/drivers/tft/data/tft.tcl +++ b/XilinxProcessorIPLib/drivers/tft/data/tft.tcl @@ -50,9 +50,9 @@ proc generate {drv_handle} { - ::hsi::utils::define_include_file $drv_handle "xparameters.h" "XTft" "NUM_INSTANCES" "C_BASEADDR" "C_HIGHADDR" "DEVICE_ID" "C_DEFAULT_TFT_BASE_ADDR" - ::hsi::utils::define_config_file $drv_handle "xtft_g.c" "XTft" "DEVICE_ID" "C_BASEADDR" "C_DEFAULT_TFT_BASE_ADDR" - xdefine_canonical_xpars $drv_handle "xparameters.h" "Tft" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_DEFAULT_TFT_BASE_ADDR" + ::hsi::utils::define_include_file $drv_handle "xparameters.h" "XTft" "NUM_INSTANCES" "C_BASEADDR" "C_HIGHADDR" "DEVICE_ID" "C_DEFAULT_TFT_BASE_ADDR" "C_M_AXI_ADDR_WIDTH" + ::hsi::utils::define_config_file $drv_handle "xtft_g.c" "XTft" "DEVICE_ID" "C_BASEADDR" "C_DEFAULT_TFT_BASE_ADDR" "C_M_AXI_ADDR_WIDTH" + xdefine_canonical_xpars $drv_handle "xparameters.h" "Tft" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_DEFAULT_TFT_BASE_ADDR" "C_M_AXI_ADDR_WIDTH" } # diff --git a/XilinxProcessorIPLib/drivers/tft/src/xtft.c b/XilinxProcessorIPLib/drivers/tft/src/xtft.c index 6fb30ed8..62c98850 100644 --- a/XilinxProcessorIPLib/drivers/tft/src/xtft.c +++ b/XilinxProcessorIPLib/drivers/tft/src/xtft.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -59,6 +59,12 @@ * 4.00a bss 01/25/13 Added support for AXI TFT controller, * XTft_WriteReg and XTft_ReadReg functions are updated * Removed all functionality associated with DCR access +* 6.0 sd 07/13/15 Modified the XTft_SetFrameBaseAddr API to +* void XTft_SetFrameBaseAddr(XTft *InstancePtr, +* UINTPR NewFrameBaseAddr) so that it can be used +* in systems with memory greater than 4 GB +* Updated XTft_CfgInitialize API so that input +* argument EffectiveAddr is a UINTPTR type * * ****************************************************************************/ @@ -107,7 +113,7 @@ static void XTft_WriteChar(XTft* InstancePtr, u8 CharValue, * ****************************************************************************/ int XTft_CfgInitialize(XTft *InstancePtr, XTft_Config *ConfigPtr, - u32 EffectiveAddr) + UINTPTR EffectiveAddr) { /* * Assert validates the input arguments. @@ -754,7 +760,7 @@ void XTft_ScanNormal(XTft* InstancePtr) * screen can be written. * ****************************************************************************/ -void XTft_SetFrameBaseAddr(XTft* InstancePtr, u32 NewFrameBaseAddr) +void XTft_SetFrameBaseAddr(XTft *InstancePtr, UINTPTR NewFrameBaseAddr) { /* * Assert validates the input arguments. @@ -763,10 +769,20 @@ void XTft_SetFrameBaseAddr(XTft* InstancePtr, u32 NewFrameBaseAddr) Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid((NewFrameBaseAddr & 0x1FFFFF) == 0x0); - /* - * Write to the Control Register. - */ - XTft_WriteReg(InstancePtr, XTFT_AR_OFFSET, NewFrameBaseAddr); + if (InstancePtr->TftConfig.AddrWidth > 32 ) { + + /* Write to the Address (Video memory) MSB Register */ + XTft_WriteReg(InstancePtr, XTFT_AR_MSB_OFFSET, + UPPER_32_BITS(NewFrameBaseAddr)); + + /* Write to the Address (Video memory) LSB Register */ + XTft_WriteReg(InstancePtr, XTFT_AR_LSB_OFFSET, + (u32)(NewFrameBaseAddr & 0xFFFFFFFF)); + } else { + + /* Write to the Address (Video memory) LSB Register */ + XTft_WriteReg(InstancePtr, XTFT_AR_OFFSET, NewFrameBaseAddr); + } /* * Update the Instance structure member. diff --git a/XilinxProcessorIPLib/drivers/tft/src/xtft.h b/XilinxProcessorIPLib/drivers/tft/src/xtft.h index 5f85c565..ed298f71 100644 --- a/XilinxProcessorIPLib/drivers/tft/src/xtft.h +++ b/XilinxProcessorIPLib/drivers/tft/src/xtft.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -114,6 +114,16 @@ * 4.01a bss 11/01/13 Modified driver tcl to retrieve C_BASEADDR/C_HIGHADDR * CR#757359. * 5.0 adk 19/12/13 Updated as per the New Tcl API's +* 6.0 sd 19/08/15 Updated the BaseAddress and VideoMemBaseAddr +* variables in XTft_Config to be UINTPTR to support +* 64 bit addresses. Added AddrWidth to the +* XTft_Config structure which reflects the value of +* C_M_AXI_ADDR_WIDTH. +* Updated to tcl add the C_M_AXI_ADDR_WIDTH parameter. +* Added XTFT_AR_LSB_OFFSET and XTFT_AR_MSB_OFFSET +* definitions to the xtft_hw.h file, these offsets +* are valid only when the Address Width is greater +* than 32 bits. * * ****************************************************************************/ @@ -152,14 +162,17 @@ extern "C" { /**************************** Type Definitions *****************************/ /** + * @struct XTft_Config + * * This structure holds the Device base address, video memory base address * and Unique identifier of the device. */ typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Base address of device */ - u32 VideoMemBaseAddr; /**< Video Memory Base address */ + u16 DeviceId; /**< Unique ID of device */ + UINTPTR BaseAddress; /**< Base address of device */ + UINTPTR VideoMemBaseAddr; /**< Video Memory Base address */ + u32 AddrWidth; /**< Address Width */ } XTft_Config; @@ -193,7 +206,7 @@ XTft_Config *XTft_LookupConfig(u16 DeviceId); * Functions for basic driver operations in xtft.c. */ int XTft_CfgInitialize(XTft *InstancePtr, XTft_Config *ConfigPtr, - u32 EffectiveAddr); + UINTPTR EffectiveAddr); void XTft_SetPos(XTft *InstancePtr, u32 ColVal, u32 RowVal); void XTft_SetPosChar(XTft *InstancePtr, u32 ColVal, u32 RowVal); @@ -213,7 +226,7 @@ void XTft_EnableDisplay(XTft *InstancePtr); void XTft_DisableDisplay(XTft *InstancePtr); void XTft_ScanReverse(XTft* InstancePtr); void XTft_ScanNormal(XTft* InstancePtr); -void XTft_SetFrameBaseAddr(XTft *InstancePtr, u32 NewFrameBaseAddr); +void XTft_SetFrameBaseAddr(XTft *InstancePtr, UINTPTR NewFrameBaseAddr); void XTft_WriteReg(XTft* InstancePtr, u32 RegOffset, u32 Data); u32 XTft_ReadReg(XTft* InstancePtr, u32 RegOffset); void XTft_IntrEnable(XTft* InstancePtr); diff --git a/XilinxProcessorIPLib/drivers/tft/src/xtft_g.c b/XilinxProcessorIPLib/drivers/tft/src/xtft_g.c index 2dadde0f..e0776711 100644 --- a/XilinxProcessorIPLib/drivers/tft/src/xtft_g.c +++ b/XilinxProcessorIPLib/drivers/tft/src/xtft_g.c @@ -74,7 +74,8 @@ XTft_Config XTft_ConfigTable[] = { XPAR_TFT_0_DEVICE_ID, XPAR_TFT_0_BASEADDR, - XPAR_TFT_0_DEFAULT_TFT_BASE_ADDR + XPAR_TFT_0_DEFAULT_TFT_BASE_ADDR, + XPAR_TFT_0_ADDR_WIDTH } }; diff --git a/XilinxProcessorIPLib/drivers/tft/src/xtft_hw.h b/XilinxProcessorIPLib/drivers/tft/src/xtft_hw.h index 4ef0f97a..1a880755 100644 --- a/XilinxProcessorIPLib/drivers/tft/src/xtft_hw.h +++ b/XilinxProcessorIPLib/drivers/tft/src/xtft_hw.h @@ -35,6 +35,7 @@ * @file xtft_hw.h * @addtogroup tft_v5_0 * @{ +* @details * * This file defines the macros and definitions for the Xilinx TFT Controller * device. @@ -49,6 +50,10 @@ * bit masks. * 3.00a ktn 10/22/09 Updated driver to use the HAL APIs/macros. * Removed the macros XTft_mSetPixel and XTft_mGetPixel. +* 6.0 sd 07/09/15 Added XTFT_AR_LSB_OFFSET and XTFT_AR_MSB_OFFSET +* definitions to the xtft_hw.h file, these offsets +* are valid only when the Address Width is greater +* than 32 bits. * * ****************************************************************************/ @@ -77,6 +82,9 @@ extern "C" { #define XTFT_CR_OFFSET 4 /**< Control Register Offset */ #define XTFT_IESR_OFFSET 8 /**< Interrupt Enable and Status Reg Offset */ +#define XTFT_AR_LSB_OFFSET 0x10 /**< Address Reg LSB (Video memory) Offset */ +#define XTFT_AR_MSB_OFFSET 0x14 /**< Address Reg MSB (Video memory) Offset */ + /*@}*/ /**