diff --git a/XilinxProcessorIPLib/drivers/v_hdmitx/data/v_hdmitx.tcl b/XilinxProcessorIPLib/drivers/v_hdmitx/data/v_hdmitx.tcl index 9eec443c..13760506 100755 --- a/XilinxProcessorIPLib/drivers/v_hdmitx/data/v_hdmitx.tcl +++ b/XilinxProcessorIPLib/drivers/v_hdmitx/data/v_hdmitx.tcl @@ -32,18 +32,18 @@ proc generate {drv_handle} { xdefine_include_file $drv_handle "xparameters.h" "XV_HdmiTx" \ - "NUM_INSTANCES" \ - "DEVICE_ID" \ - "C_BASEADDR" \ - "C_HIGHADDR" + "NUM_INSTANCES" \ + "DEVICE_ID" \ + "C_BASEADDR" \ + "C_HIGHADDR" xdefine_config_file $drv_handle "xv_hdmitx_g.c" "XV_HdmiTx" \ - "DEVICE_ID" \ - "C_BASEADDR" + "DEVICE_ID" \ + "C_BASEADDR" xdefine_canonical_xpars $drv_handle "xparameters.h" "XV_HdmiTx" \ - "NUM_INSTANCES" \ - "DEVICE_ID" \ - "C_BASEADDR" \ - "C_HIGHADDR" -} \ No newline at end of file + "NUM_INSTANCES" \ + "DEVICE_ID" \ + "C_BASEADDR" \ + "C_HIGHADDR" +} diff --git a/XilinxProcessorIPLib/drivers/v_hdmitx/src/Makefile b/XilinxProcessorIPLib/drivers/v_hdmitx/src/Makefile old mode 100755 new mode 100644 index c20c6fc4..4ba2be8e --- a/XilinxProcessorIPLib/drivers/v_hdmitx/src/Makefile +++ b/XilinxProcessorIPLib/drivers/v_hdmitx/src/Makefile @@ -16,13 +16,13 @@ OUTS = *.o libs: - echo "Compiling v_hdmitx" - $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS) - make clean + echo "Compiling v_hdmitx" + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS) + make clean include: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} clean: - rm -rf ${OUTS} + rm -rf ${OUTS} diff --git a/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx.c b/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx.c old mode 100755 new mode 100644 index b91162db..e012c91e --- a/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx.c +++ b/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx.c @@ -69,74 +69,74 @@ * 2) Video Identification Code. */ static const XV_HdmiTx_VicTable VicTable[34] = { - {XVIDC_VM_640x480_60_P, 1}, /**< Vic 1 */ - {XVIDC_VM_720x480_60_P, 2}, /**< Vic 2 */ - {XVIDC_VM_1280x720_60_P, 4}, /**< Vic 4 */ - {XVIDC_VM_1920x1080_60_I, 5}, /**< Vic 5 */ - {XVIDC_VM_1440x480_60_I, 6}, /**< Vic 6 */ - {XVIDC_VM_720x576_50_P, 17}, /**< Vic 17 */ - {XVIDC_VM_1280x720_50_P, 19}, /**< Vic 19 */ - {XVIDC_VM_1920x1080_50_I, 20}, /**< Vic 20 */ - {XVIDC_VM_1440x576_50_I, 21}, /**< Vic 21 */ + {XVIDC_VM_640x480_60_P, 1}, /**< Vic 1 */ + {XVIDC_VM_720x480_60_P, 2}, /**< Vic 2 */ + {XVIDC_VM_1280x720_60_P, 4}, /**< Vic 4 */ + {XVIDC_VM_1920x1080_60_I, 5}, /**< Vic 5 */ + {XVIDC_VM_1440x480_60_I, 6}, /**< Vic 6 */ + {XVIDC_VM_720x576_50_P, 17}, /**< Vic 17 */ + {XVIDC_VM_1280x720_50_P, 19}, /**< Vic 19 */ + {XVIDC_VM_1920x1080_50_I, 20}, /**< Vic 20 */ + {XVIDC_VM_1440x576_50_I, 21}, /**< Vic 21 */ - /**< 1680 x 720 */ - {XVIDC_VM_1680x720_50_P, 82}, /**< Vic 82 */ - {XVIDC_VM_1680x720_60_P, 83}, /**< Vic 83 */ - {XVIDC_VM_1680x720_100_P, 84}, /**< Vic 84 */ - {XVIDC_VM_1680x720_120_P, 85}, /**< Vic 85 */ + /**< 1680 x 720 */ + {XVIDC_VM_1680x720_50_P, 82}, /**< Vic 82 */ + {XVIDC_VM_1680x720_60_P, 83}, /**< Vic 83 */ + {XVIDC_VM_1680x720_100_P, 84}, /**< Vic 84 */ + {XVIDC_VM_1680x720_120_P, 85}, /**< Vic 85 */ - /**< 1920 x 1080 */ - {XVIDC_VM_1920x1080_24_P, 32}, /**< Vic 32 */ - {XVIDC_VM_1920x1080_25_P, 33}, /**< Vic 33 */ - {XVIDC_VM_1920x1080_30_P, 34}, /**< Vic 34 */ - {XVIDC_VM_1920x1080_50_P, 31}, /**< Vic 31 */ - {XVIDC_VM_1920x1080_60_P, 16}, /**< Vic 16 */ - {XVIDC_VM_1920x1080_100_P, 64}, /**< Vic 64 */ - {XVIDC_VM_1920x1080_120_P, 63}, /**< Vic 63 */ + /**< 1920 x 1080 */ + {XVIDC_VM_1920x1080_24_P, 32}, /**< Vic 32 */ + {XVIDC_VM_1920x1080_25_P, 33}, /**< Vic 33 */ + {XVIDC_VM_1920x1080_30_P, 34}, /**< Vic 34 */ + {XVIDC_VM_1920x1080_50_P, 31}, /**< Vic 31 */ + {XVIDC_VM_1920x1080_60_P, 16}, /**< Vic 16 */ + {XVIDC_VM_1920x1080_100_P, 64}, /**< Vic 64 */ + {XVIDC_VM_1920x1080_120_P, 63}, /**< Vic 63 */ - /**< 2560 x 1080 */ - {XVIDC_VM_2560x1080_50_P, 89}, /**< Vic 89 */ - {XVIDC_VM_2560x1080_60_P, 90}, /**< Vic 89 */ - {XVIDC_VM_2560x1080_100_P, 91}, /**< Vic 91 */ - {XVIDC_VM_2560x1080_120_P, 92}, /**< Vic 92 */ + /**< 2560 x 1080 */ + {XVIDC_VM_2560x1080_50_P, 89}, /**< Vic 89 */ + {XVIDC_VM_2560x1080_60_P, 90}, /**< Vic 89 */ + {XVIDC_VM_2560x1080_100_P, 91}, /**< Vic 91 */ + {XVIDC_VM_2560x1080_120_P, 92}, /**< Vic 92 */ - /**< 3840 x 2160 */ - {XVIDC_VM_3840x2160_24_P, 93}, /**< Vic 93 */ - {XVIDC_VM_3840x2160_25_P, 94}, /**< Vic 94 */ - {XVIDC_VM_3840x2160_30_P, 95}, /**< Vic 95 */ - {XVIDC_VM_3840x2160_50_P, 96}, /**< Vic 96 */ - {XVIDC_VM_3840x2160_60_P, 97}, /**< Vic 97 */ + /**< 3840 x 2160 */ + {XVIDC_VM_3840x2160_24_P, 93}, /**< Vic 93 */ + {XVIDC_VM_3840x2160_25_P, 94}, /**< Vic 94 */ + {XVIDC_VM_3840x2160_30_P, 95}, /**< Vic 95 */ + {XVIDC_VM_3840x2160_50_P, 96}, /**< Vic 96 */ + {XVIDC_VM_3840x2160_60_P, 97}, /**< Vic 97 */ - /**< 4096 x 2160 */ - {XVIDC_VM_4096x2160_24_P, 98}, /**< Vic 98 */ - {XVIDC_VM_4096x2160_25_P, 99}, /**< Vic 99 */ - {XVIDC_VM_4096x2160_30_P, 100}, /**< Vic 100 */ - {XVIDC_VM_4096x2160_50_P, 101}, /**< Vic 101 */ - {XVIDC_VM_4096x2160_60_P, 102} /**< Vic 102 */ + /**< 4096 x 2160 */ + {XVIDC_VM_4096x2160_24_P, 98}, /**< Vic 98 */ + {XVIDC_VM_4096x2160_25_P, 99}, /**< Vic 99 */ + {XVIDC_VM_4096x2160_30_P, 100}, /**< Vic 100 */ + {XVIDC_VM_4096x2160_50_P, 101}, /**< Vic 101 */ + {XVIDC_VM_4096x2160_60_P, 102} /**< Vic 102 */ }; const XV_HdmiTx_ReducedBlankingTable ReducedBlankingTable[4] = { - // 720p50 @ 12 bpc - { XVIDC_VM_1280x720_50_P, - {1280, 90, 30, 100, 1500, 1, - 720, 5, 5, 5, 725, 0, 0, 0, 0, 1} }, + // 720p50 @ 12 bpc + { XVIDC_VM_1280x720_50_P, + {1280, 90, 30, 100, 1500, 1, + 720, 5, 5, 5, 725, 0, 0, 0, 0, 1} }, - // 720p60 @ 12 bpc - { XVIDC_VM_1280x720_60_P, - {1280, 90, 30, 100, 1500, 1, - 720, 5, 5, 5, 725, 0, 0, 0, 0, 1} }, + // 720p60 @ 12 bpc + { XVIDC_VM_1280x720_60_P, + {1280, 90, 30, 100, 1500, 1, + 720, 5, 5, 5, 725, 0, 0, 0, 0, 1} }, - // 1080p50 @ 12 bpc - { XVIDC_VM_1920x1080_50_P, - {1920, 56, 44, 100, 2000, 1, - 1080, 4, 5, 9, 1100, 0, 0, 0, 0, 1} }, + // 1080p50 @ 12 bpc + { XVIDC_VM_1920x1080_50_P, + {1920, 56, 44, 100, 2000, 1, + 1080, 4, 5, 9, 1100, 0, 0, 0, 0, 1} }, - // 1080p60 @ 12 bpc - { XVIDC_VM_1920x1080_60_P, - {1920, 56, 44, 100, 2000, 1, - 1080, 4, 5, 9, 1100, 0, 0, 0, 0, 1} } + // 1080p60 @ 12 bpc + { XVIDC_VM_1920x1080_60_P, + {1920, 56, 44, 100, 2000, 1, + 1080, 4, 5, 9, 1100, 0, 0, 0, 0, 1} } }; /************************** Function Prototypes ******************************/ @@ -157,123 +157,123 @@ static int HdmiTx_DdcExec(XV_HdmiTx *InstancePtr); * setting up the instance data and ensuring the hardware is in a quiescent * state. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. -* @param CfgPtr points to the configuration structure associated with -* the HDMI TX core. -* @param EffectiveAddr is the base address of the device. If address -* translation is being used, then this parameter must reflect the -* virtual base address. Otherwise, the physical address should be -* used. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param CfgPtr points to the configuration structure associated with +* the HDMI TX core. +* @param EffectiveAddr is the base address of the device. If address +* translation is being used, then this parameter must reflect the +* virtual base address. Otherwise, the physical address should be +* used. * * @return -* - XST_SUCCESS if XV_HdmiTx_CfgInitialize was successful. -* - XST_FAILURE if HDMI TX PIO ID mismatched. +* - XST_SUCCESS if XV_HdmiTx_CfgInitialize was successful. +* - XST_FAILURE if HDMI TX PIO ID mismatched. * -* @note None. +* @note None. * ******************************************************************************/ int XV_HdmiTx_CfgInitialize(XV_HdmiTx *InstancePtr, XV_HdmiTx_Config *CfgPtr, - u32 EffectiveAddr) + u32 EffectiveAddr) { - u32 RegValue; + u32 RegValue; - /* Verify arguments. */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(CfgPtr != NULL); - Xil_AssertNonvoid(EffectiveAddr != (u32)0x0); + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(CfgPtr != NULL); + Xil_AssertNonvoid(EffectiveAddr != (u32)0x0); - /* Setup the instance */ - (void)memset((void *)InstancePtr, 0, sizeof(XV_HdmiTx)); - (void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr, - sizeof(XV_HdmiTx_Config)); - InstancePtr->Config.BaseAddress = EffectiveAddr; + /* Setup the instance */ + (void)memset((void *)InstancePtr, 0, sizeof(XV_HdmiTx)); + (void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr, + sizeof(XV_HdmiTx_Config)); + InstancePtr->Config.BaseAddress = EffectiveAddr; #if defined(__MICROBLAZE__) - InstancePtr->CpuClkFreq = XPAR_CPU_CORE_CLOCK_FREQ_HZ; + InstancePtr->CpuClkFreq = XPAR_CPU_CORE_CLOCK_FREQ_HZ; #elif defined(__arm__) - InstancePtr->CpuClkFreq = XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ; + InstancePtr->CpuClkFreq = XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ; #endif - /* Set all handlers to stub values, let user configure this data later */ - InstancePtr->ConnectCallback = (XV_HdmiTx_Callback)((void *)StubCallback); - InstancePtr->IsConnectCallbackSet = (FALSE); + /* Set all handlers to stub values, let user configure this data later */ + InstancePtr->ConnectCallback = (XV_HdmiTx_Callback)((void *)StubCallback); + InstancePtr->IsConnectCallbackSet = (FALSE); - InstancePtr->VsCallback = (XV_HdmiTx_Callback)((void *)StubCallback); - InstancePtr->IsVsCallbackSet = (FALSE); + InstancePtr->VsCallback = (XV_HdmiTx_Callback)((void *)StubCallback); + InstancePtr->IsVsCallbackSet = (FALSE); - InstancePtr->StreamDownCallback =(XV_HdmiTx_Callback)((void *)StubCallback); - InstancePtr->IsStreamDownCallbackSet = (FALSE); + InstancePtr->StreamDownCallback =(XV_HdmiTx_Callback)((void *)StubCallback); + InstancePtr->IsStreamDownCallbackSet = (FALSE); - InstancePtr->StreamUpCallback = (XV_HdmiTx_Callback)((void *)StubCallback); - InstancePtr->IsStreamUpCallbackSet = (FALSE); + InstancePtr->StreamUpCallback = (XV_HdmiTx_Callback)((void *)StubCallback); + InstancePtr->IsStreamUpCallbackSet = (FALSE); - /* Clear HDMI variables */ - XV_HdmiTx_Clear(InstancePtr); + /* Clear HDMI variables */ + XV_HdmiTx_Clear(InstancePtr); - // Set stream status - InstancePtr->Stream.State = XV_HDMITX_STATE_STREAM_DOWN; - // The stream is down + // Set stream status + InstancePtr->Stream.State = XV_HDMITX_STATE_STREAM_DOWN; + // The stream is down - // Clear connected flag - InstancePtr->Stream.IsConnected = (FALSE); + // Clear connected flag + InstancePtr->Stream.IsConnected = (FALSE); - /* Reset all peripherals */ - XV_HdmiTx_PioDisable(InstancePtr); - XV_HdmiTx_DdcDisable(InstancePtr); - XV_HdmiTx_AudioDisable(InstancePtr); - XV_HdmiTx_AuxDisable(InstancePtr); + /* Reset all peripherals */ + XV_HdmiTx_PioDisable(InstancePtr); + XV_HdmiTx_DdcDisable(InstancePtr); + XV_HdmiTx_AudioDisable(InstancePtr); + XV_HdmiTx_AuxDisable(InstancePtr); - XV_HdmiTx_PioIntrClear(InstancePtr); - XV_HdmiTx_DdcIntrClear(InstancePtr); + XV_HdmiTx_PioIntrClear(InstancePtr); + XV_HdmiTx_DdcIntrClear(InstancePtr); - /* Read PIO peripheral Identification register */ - RegValue = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_PIO_ID_OFFSET)); - RegValue = ((RegValue) >> (XV_HDMITX_SHIFT_16)) & - (XV_HDMITX_MASK_16); - if (RegValue != (XV_HDMITX_PIO_ID)) { - return (XST_FAILURE); - } + /* Read PIO peripheral Identification register */ + RegValue = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_PIO_ID_OFFSET)); + RegValue = ((RegValue) >> (XV_HDMITX_SHIFT_16)) & + (XV_HDMITX_MASK_16); + if (RegValue != (XV_HDMITX_PIO_ID)) { + return (XST_FAILURE); + } - /* PIO: Set event rising edge masks */ - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_PIO_IN_EVT_RE_OFFSET), - (XV_HDMITX_PIO_IN_HPD_MASK) | - (XV_HDMITX_PIO_IN_VS_MASK) | - (XV_HDMITX_PIO_IN_LNK_RDY_MASK) - ); + /* PIO: Set event rising edge masks */ + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_PIO_IN_EVT_RE_OFFSET), + (XV_HDMITX_PIO_IN_HPD_MASK) | + (XV_HDMITX_PIO_IN_VS_MASK) | + (XV_HDMITX_PIO_IN_LNK_RDY_MASK) + ); - /* PIO: Set event falling edge masks */ - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_PIO_IN_EVT_FE_OFFSET), - (XV_HDMITX_PIO_IN_HPD_MASK) | - (XV_HDMITX_PIO_IN_LNK_RDY_MASK) - ); + /* PIO: Set event falling edge masks */ + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_PIO_IN_EVT_FE_OFFSET), + (XV_HDMITX_PIO_IN_HPD_MASK) | + (XV_HDMITX_PIO_IN_LNK_RDY_MASK) + ); - /* Enable the PIO peripheral interrupt */ - XV_HdmiTx_PioIntrEnable(InstancePtr); + /* Enable the PIO peripheral interrupt */ + XV_HdmiTx_PioIntrEnable(InstancePtr); - /* Enable the PIO peripheral */ - XV_HdmiTx_PioEnable(InstancePtr); + /* Enable the PIO peripheral */ + XV_HdmiTx_PioEnable(InstancePtr); - /* Set HDMI mode */ - XV_HdmiTx_SetMode(InstancePtr); + /* Set HDMI mode */ + XV_HdmiTx_SetMode(InstancePtr); - /* Enable the AUX peripheral */ - /* The aux peripheral is enabled at stream up */ - //XV_HdmiTx_AuxEnable(InstancePtr); + /* Enable the AUX peripheral */ + /* The aux peripheral is enabled at stream up */ + //XV_HdmiTx_AuxEnable(InstancePtr); - /* Enable audio */ - /* The audio peripheral is enabled at stream up */ - //XV_HdmiTx_AudioEnable(InstancePtr); + /* Enable audio */ + /* The audio peripheral is enabled at stream up */ + //XV_HdmiTx_AudioEnable(InstancePtr); - /* Initialize DDC */ - XV_HdmiTx_DdcInit(InstancePtr, InstancePtr->CpuClkFreq); + /* Initialize DDC */ + XV_HdmiTx_DdcInit(InstancePtr, InstancePtr->CpuClkFreq); - /* Reset the hardware and set the flag to indicate the driver is ready */ - InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY); + /* Reset the hardware and set the flag to indicate the driver is ready */ + InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY); - return (XST_SUCCESS); + return (XST_SUCCESS); } /*****************************************************************************/ @@ -281,19 +281,19 @@ int XV_HdmiTx_CfgInitialize(XV_HdmiTx *InstancePtr, XV_HdmiTx_Config *CfgPtr, * * This function clear the HDMI TX variables and sets it to the defaults. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * * @return * * -* @note This is required after a reset or init. +* @note This is required after a reset or init. * ******************************************************************************/ void XV_HdmiTx_Clear(XV_HdmiTx *InstancePtr) { - /* Verify argument. */ - Xil_AssertVoid(InstancePtr != NULL); + /* Verify argument. */ + Xil_AssertVoid(InstancePtr != NULL); } /*****************************************************************************/ @@ -301,11 +301,11 @@ void XV_HdmiTx_Clear(XV_HdmiTx *InstancePtr) * * This function provides video identification code of video mode. * -* @param VideoMode specifies resolution identifier. +* @param VideoMode specifies resolution identifier. * -* @return Video identification code defined in the VIC table. +* @return Video identification code defined in the VIC table. * -* @note None. +* @note None. * ******************************************************************************/ u8 XV_HdmiTx_LookupVic(XVidC_VideoMode VideoMode) @@ -317,7 +317,7 @@ u8 XV_HdmiTx_LookupVic(XVidC_VideoMode VideoMode) // Xil_AssertNonvoid(VideoMode < (XVIDC_VM_NUM_SUPPORTED)); for (Index = 0; Index < sizeof(VicTable)/sizeof(XV_HdmiTx_VicTable); - Index++) { + Index++) { Entry = &VicTable[Index]; if (Entry->VmId == VideoMode) return (Entry->Vic); @@ -330,11 +330,11 @@ u8 XV_HdmiTx_LookupVic(XVidC_VideoMode VideoMode) * * This function provides video identification code of video mode. * -* @param VideoMode specifies resolution identifier. +* @param VideoMode specifies resolution identifier. * -* @return Video identification code defined in the VIC table. +* @return Video identification code defined in the VIC table. * -* @note None. +* @note None. * ******************************************************************************/ const XVidC_VideoTiming *XV_HdmiTx_GetReducedBlankingTimingInfo(XVidC_VideoMode VideoMode) @@ -343,7 +343,7 @@ const XVidC_VideoTiming *XV_HdmiTx_GetReducedBlankingTimingInfo(XVidC_VideoMode u8 Index; for (Index = 0; Index < sizeof(ReducedBlankingTable)/sizeof( - XV_HdmiTx_ReducedBlankingTable); Index++) { + XV_HdmiTx_ReducedBlankingTable); Index++) { Entry = &ReducedBlankingTable[Index]; if (Entry->VmId == VideoMode) return (&ReducedBlankingTable[Index].Timing); @@ -358,78 +358,78 @@ const XVidC_VideoTiming *XV_HdmiTx_GetReducedBlankingTimingInfo(XVidC_VideoMode * This function controls the scrambler * * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * * @return -* - XST_SUCCESS if HDMI 2.0 -* - XST_FAILURE if HDMI 1.4 +* - XST_SUCCESS if HDMI 2.0 +* - XST_FAILURE if HDMI 1.4 * -* @note None. +* @note None. * ******************************************************************************/ int XV_HdmiTx_Scrambler(XV_HdmiTx *InstancePtr) { - u8 DdcBuf[2]; - u32 Status; + u8 DdcBuf[2]; + u32 Status; - /* Verify argument. */ - Xil_AssertNonvoid(InstancePtr != NULL); + /* Verify argument. */ + Xil_AssertNonvoid(InstancePtr != NULL); - // Check scrambler flag - if (InstancePtr->Stream.IsScrambled) { + // Check scrambler flag + if (InstancePtr->Stream.IsScrambled) { - // Check if the sink is HDMI 2.0 - if (InstancePtr->Stream.IsHdmi20) { - XV_HdmiTx_SetScrambler(InstancePtr, (TRUE)); - } - else { - XV_HdmiTx_SetScrambler(InstancePtr, (FALSE)); - } - } + // Check if the sink is HDMI 2.0 + if (InstancePtr->Stream.IsHdmi20) { + XV_HdmiTx_SetScrambler(InstancePtr, (TRUE)); + } + else { + XV_HdmiTx_SetScrambler(InstancePtr, (FALSE)); + } + } - // Clear - else - XV_HdmiTx_SetScrambler(InstancePtr, (FALSE)); + // Clear + else + XV_HdmiTx_SetScrambler(InstancePtr, (FALSE)); - // Update TMDS configuration - // Only when it is a HDMI 2.0 sink device - if (InstancePtr->Stream.IsHdmi20) { + // Update TMDS configuration + // Only when it is a HDMI 2.0 sink device + if (InstancePtr->Stream.IsHdmi20) { - DdcBuf[0] = 0x20; // Offset scrambler status - Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 1, - (u8*)&DdcBuf, (FALSE)); + DdcBuf[0] = 0x20; // Offset scrambler status + Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 1, + (u8*)&DdcBuf, (FALSE)); - // Check if write was successful - if (Status == (XST_SUCCESS)) { + // Check if write was successful + if (Status == (XST_SUCCESS)) { - // Read TMDS configuration - Status = XV_HdmiTx_DdcRead(InstancePtr, 0x54, 1, - (u8*)&DdcBuf, (TRUE)); + // Read TMDS configuration + Status = XV_HdmiTx_DdcRead(InstancePtr, 0x54, 1, + (u8*)&DdcBuf, (TRUE)); - // The result is in ddc_buf[0] - // Clear scrambling enable bit - DdcBuf[0] &= 0xfe; + // The result is in ddc_buf[0] + // Clear scrambling enable bit + DdcBuf[0] &= 0xfe; - // Set scrambler bit if scrambler is enabled - if (InstancePtr->Stream.IsScrambled) - DdcBuf[0] |= 0x01; + // Set scrambler bit if scrambler is enabled + if (InstancePtr->Stream.IsScrambled) + DdcBuf[0] |= 0x01; - // Copy buf[0] to buf[1] - DdcBuf[1] = DdcBuf[0]; + // Copy buf[0] to buf[1] + DdcBuf[1] = DdcBuf[0]; - // Offset - DdcBuf[0] = 0x20; // Offset scrambler status + // Offset + DdcBuf[0] = 0x20; // Offset scrambler status - // Write back TMDS configuration - Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 2, - (u8*)&DdcBuf, (TRUE)); - } + // Write back TMDS configuration + Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 2, + (u8*)&DdcBuf, (TRUE)); + } - // Write failed - else { - return XST_FAILURE; - } - } - return XST_SUCCESS; + // Write failed + else { + return XST_FAILURE; + } + } + return XST_SUCCESS; } /*****************************************************************************/ @@ -438,58 +438,58 @@ int XV_HdmiTx_Scrambler(XV_HdmiTx *InstancePtr) { * This function controls the TMDS clock ratio * * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * * @return -* - XST_SUCCESS if HDMI 2.0 -* - XST_FAILURE if HDMI 1.4 +* - XST_SUCCESS if HDMI 2.0 +* - XST_FAILURE if HDMI 1.4 * -* @note None. +* @note None. * ******************************************************************************/ int XV_HdmiTx_ClockRatio(XV_HdmiTx *InstancePtr) { - u8 DdcBuf[2]; - u32 Status; + u8 DdcBuf[2]; + u32 Status; - /* Verify argument. */ - Xil_AssertNonvoid(InstancePtr != NULL); + /* Verify argument. */ + Xil_AssertNonvoid(InstancePtr != NULL); - // Update TMDS configuration - // Only when it is a HDMI 2.0 sink device - if (InstancePtr->Stream.IsHdmi20) { + // Update TMDS configuration + // Only when it is a HDMI 2.0 sink device + if (InstancePtr->Stream.IsHdmi20) { - DdcBuf[0] = 0x20; // Offset scrambler status - Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (FALSE)); + DdcBuf[0] = 0x20; // Offset scrambler status + Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (FALSE)); - // Check if write was successful - if (Status == (XST_SUCCESS)) { + // Check if write was successful + if (Status == (XST_SUCCESS)) { - // Read TMDS configuration - Status = XV_HdmiTx_DdcRead(InstancePtr, 0x54, 1, - (u8*)&DdcBuf, (TRUE)); + // Read TMDS configuration + Status = XV_HdmiTx_DdcRead(InstancePtr, 0x54, 1, + (u8*)&DdcBuf, (TRUE)); - // The result is in ddc_buf[0] - // Clear TMDS clock ration bit (1) - DdcBuf[0] &= 0xfd; + // The result is in ddc_buf[0] + // Clear TMDS clock ration bit (1) + DdcBuf[0] &= 0xfd; - /* Set the TMDS clock ratio bit if the bandwidth is - higher than 3.4 Gbps */ - if (InstancePtr->Stream.TMDSClockRatio) { - DdcBuf[0] |= 0x02; - } + /* Set the TMDS clock ratio bit if the bandwidth is + higher than 3.4 Gbps */ + if (InstancePtr->Stream.TMDSClockRatio) { + DdcBuf[0] |= 0x02; + } - // Copy buf[0] to buf[1] - DdcBuf[1] = DdcBuf[0]; + // Copy buf[0] to buf[1] + DdcBuf[1] = DdcBuf[0]; - // Offset - DdcBuf[0] = 0x20; // Offset scrambler status + // Offset + DdcBuf[0] = 0x20; // Offset scrambler status - // Write back TMDS configuration - Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 2, - (u8*)&DdcBuf, (TRUE)); - } - return XST_SUCCESS; - } + // Write back TMDS configuration + Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 2, + (u8*)&DdcBuf, (TRUE)); + } + return XST_SUCCESS; + } } /*****************************************************************************/ @@ -498,43 +498,43 @@ int XV_HdmiTx_ClockRatio(XV_HdmiTx *InstancePtr) { * This function detects connected sink is a HDMI 2.0/HDMI 1.4 sink device * and sets appropriate flag in the TX stream. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * * @return -* - XST_SUCCESS if HDMI 2.0 -* - XST_FAILURE if HDMI 1.4 +* - XST_SUCCESS if HDMI 2.0 +* - XST_FAILURE if HDMI 1.4 * -* @note None. +* @note None. * ******************************************************************************/ int XV_HdmiTx_DetectHdmi20(XV_HdmiTx *InstancePtr) { - u8 DdcBuf[2]; - u32 Status; + u8 DdcBuf[2]; + u32 Status; - /* Verify argument. */ - Xil_AssertNonvoid(InstancePtr != NULL); + /* Verify argument. */ + Xil_AssertNonvoid(InstancePtr != NULL); - /* Write source version. Offset (Source version) */ - DdcBuf[0] = 0x02; + /* Write source version. Offset (Source version) */ + DdcBuf[0] = 0x02; - /* Version 1 */ - DdcBuf[1] = 0x01; - Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 2, (u8*)&DdcBuf, (TRUE)); + /* Version 1 */ + DdcBuf[1] = 0x01; + Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 2, (u8*)&DdcBuf, (TRUE)); - /* If the write was successful, then the sink is HDMI 2.0 */ - if (Status == (XST_SUCCESS)) { - InstancePtr->Stream.IsHdmi20 = (TRUE); - Status = (XST_SUCCESS); - } + /* If the write was successful, then the sink is HDMI 2.0 */ + if (Status == (XST_SUCCESS)) { + InstancePtr->Stream.IsHdmi20 = (TRUE); + Status = (XST_SUCCESS); + } - /* Else it is a HDMI 1.4 device */ - else { - InstancePtr->Stream.IsHdmi20 = (FALSE); - Status = (XST_FAILURE); - } + /* Else it is a HDMI 1.4 device */ + else { + InstancePtr->Stream.IsHdmi20 = (FALSE); + Status = (XST_FAILURE); + } - return Status; + return Status; } /*****************************************************************************/ @@ -542,60 +542,60 @@ int XV_HdmiTx_DetectHdmi20(XV_HdmiTx *InstancePtr) * * This function shows the sinks SCDC registers. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note None. +* @note None. * ******************************************************************************/ void XV_HdmiTx_ShowSCDC(XV_HdmiTx *InstancePtr) { - u8 DdcBuf[2]; - u32 Status; + u8 DdcBuf[2]; + u32 Status; - /* Verify argument. */ - Xil_AssertVoid(InstancePtr != NULL); + /* Verify argument. */ + Xil_AssertVoid(InstancePtr != NULL); - /* Sink version. Offset Scrambler status */ - DdcBuf[0] = 0x01; - Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (FALSE)); + /* Sink version. Offset Scrambler status */ + DdcBuf[0] = 0x01; + Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (FALSE)); - /* Check if write was successful */ - if (Status == (XST_SUCCESS)) { - Status = XV_HdmiTx_DdcRead(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (TRUE)); - xil_printf("HDMI TX: SCDC 0x01 : %0x\r\n", DdcBuf[0]); - } + /* Check if write was successful */ + if (Status == (XST_SUCCESS)) { + Status = XV_HdmiTx_DdcRead(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (TRUE)); + xil_printf("HDMI TX: SCDC 0x01 : %0x\r\n", DdcBuf[0]); + } - /* TMDS configuration. Offset Scrambler status */ - DdcBuf[0] = 0x20; - Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (FALSE)); + /* TMDS configuration. Offset Scrambler status */ + DdcBuf[0] = 0x20; + Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (FALSE)); - /* Check if write was successful */ - if (Status == (XST_SUCCESS)) { - Status = XV_HdmiTx_DdcRead(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (TRUE)); - xil_printf("HDMI TX: SCDC 0x20 : %0x\r\n", DdcBuf[0]); - } + /* Check if write was successful */ + if (Status == (XST_SUCCESS)) { + Status = XV_HdmiTx_DdcRead(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (TRUE)); + xil_printf("HDMI TX: SCDC 0x20 : %0x\r\n", DdcBuf[0]); + } - /* Scrambler status. Offset Scrambler status */ - DdcBuf[0] = 0x21; - Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (FALSE)); + /* Scrambler status. Offset Scrambler status */ + DdcBuf[0] = 0x21; + Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (FALSE)); - /* Check if write was successful */ - if (Status == (XST_SUCCESS)) { - Status = XV_HdmiTx_DdcRead(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (TRUE)); - xil_printf("HDMI TX: SCDC 0x21 : %0x\r\n", DdcBuf[0]); - } + /* Check if write was successful */ + if (Status == (XST_SUCCESS)) { + Status = XV_HdmiTx_DdcRead(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (TRUE)); + xil_printf("HDMI TX: SCDC 0x21 : %0x\r\n", DdcBuf[0]); + } - /* Status flags. Offset Scrambler status */ - DdcBuf[0] = 0x40; - Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (FALSE)); + /* Status flags. Offset Scrambler status */ + DdcBuf[0] = 0x40; + Status = XV_HdmiTx_DdcWrite(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (FALSE)); - /* Check if write was successful */ - if (Status == (XST_SUCCESS)) { - Status = XV_HdmiTx_DdcRead(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (TRUE)); - xil_printf("HDMI TX: SCDC 0x40 : %0x\r\n", DdcBuf[0]); - } + /* Check if write was successful */ + if (Status == (XST_SUCCESS)) { + Status = XV_HdmiTx_DdcRead(InstancePtr, 0x54, 1, (u8*)&DdcBuf, (TRUE)); + xil_printf("HDMI TX: SCDC 0x40 : %0x\r\n", DdcBuf[0]); + } } /*****************************************************************************/ @@ -603,155 +603,152 @@ void XV_HdmiTx_ShowSCDC(XV_HdmiTx *InstancePtr) * * This function sets the HDMI TX stream parameters. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. -* @param VideoMode specifies resolution identifier. -* @param ColorFormat specifies the type of color format. -* - 0 = XVIDC_CSF_RGB -* - 1 = XVIDC_CSF_YCRCB_444 -* - 2 = XVIDC_CSF_YCRCB_422 -* - 3 = XVIDC_CSF_YCRCB_420 -* @param Bpc specifies the color depth/bits per color component. -* - 6 = XVIDC_BPC_6 -* - 8 = XVIDC_BPC_8 -* - 10 = XVIDC_BPC_10 -* - 12 = XVIDC_BPC_12 -* - 16 = XVIDC_BPC_16 -* @param Ppc specifies the pixel per clock. -* - 1 = XVIDC_PPC_1 -* - 2 = XVIDC_PPC_2 -* - 4 = XVIDC_PPC_4 +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param VideoMode specifies resolution identifier. +* @param ColorFormat specifies the type of color format. +* - 0 = XVIDC_CSF_RGB +* - 1 = XVIDC_CSF_YCRCB_444 +* - 2 = XVIDC_CSF_YCRCB_422 +* - 3 = XVIDC_CSF_YCRCB_420 +* @param Bpc specifies the color depth/bits per color component. +* - 6 = XVIDC_BPC_6 +* - 8 = XVIDC_BPC_8 +* - 10 = XVIDC_BPC_10 +* - 12 = XVIDC_BPC_12 +* - 16 = XVIDC_BPC_16 +* @param Ppc specifies the pixel per clock. +* - 1 = XVIDC_PPC_1 +* - 2 = XVIDC_PPC_2 +* - 4 = XVIDC_PPC_4 * -* @return TmdsClock, reference clock calculated based on the input -* parameters. +* @return TmdsClock, reference clock calculated based on the input +* parameters. * -* @note None. +* @note None. * ******************************************************************************/ u32 XV_HdmiTx_SetStream(XV_HdmiTx *InstancePtr, XVidC_VideoMode VideoMode, XVidC_ColorFormat ColorFormat, XVidC_ColorDepth Bpc, XVidC_PixelsPerClock Ppc) { - u32 TmdsClock; - u32 Status; + u32 TmdsClock; + u32 Status; - /* Verify arguments. */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(VideoMode < (XVIDC_VM_NUM_SUPPORTED)); - Xil_AssertNonvoid((ColorFormat == (XVIDC_CSF_RGB)) || - (ColorFormat == (XVIDC_CSF_YCRCB_444)) || - (ColorFormat == (XVIDC_CSF_YCRCB_422)) || - (ColorFormat == (XVIDC_CSF_YCRCB_420))); - Xil_AssertNonvoid((Bpc == (XVIDC_BPC_8)) || - (Bpc == (XVIDC_BPC_10)) || - (Bpc == (XVIDC_BPC_12)) || - (Bpc == (XVIDC_BPC_16))); - Xil_AssertNonvoid((Ppc == (XVIDC_PPC_2)) || (Ppc == (XVIDC_PPC_4))); + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(VideoMode < (XVIDC_VM_NUM_SUPPORTED)); + Xil_AssertNonvoid((ColorFormat == (XVIDC_CSF_RGB)) || + (ColorFormat == (XVIDC_CSF_YCRCB_444)) || + (ColorFormat == (XVIDC_CSF_YCRCB_422)) || + (ColorFormat == (XVIDC_CSF_YCRCB_420))); + Xil_AssertNonvoid((Bpc == (XVIDC_BPC_8)) || + (Bpc == (XVIDC_BPC_10)) || + (Bpc == (XVIDC_BPC_12)) || + (Bpc == (XVIDC_BPC_16))); + Xil_AssertNonvoid((Ppc == (XVIDC_PPC_1)) || (Ppc == (XVIDC_PPC_2)) || (Ppc == (XVIDC_PPC_4))); - /* Check HDMI sink version */ - XV_HdmiTx_DetectHdmi20(InstancePtr); + InstancePtr->Stream.Video.VmId = VideoMode; + InstancePtr->Stream.Video.ColorFormatId = ColorFormat; - InstancePtr->Stream.Video.VmId = VideoMode; - InstancePtr->Stream.Video.ColorFormatId = ColorFormat; + /** In HDMI the colordepth in YUV422 is always 12 bits, + * although on the link itself it is being transmitted as 8-bits. + * Therefore if the colorspace is YUV422, then force the colordepth + * to 12 bits. */ + if (ColorFormat == XVIDC_CSF_YCRCB_422) { + InstancePtr->Stream.Video.ColorDepth = XVIDC_BPC_12; + } - /** In HDMI the colordepth in YUV422 is always 12 bits, - * although on the link itself it is being transmitted as 8-bits. - * Therefore if the colorspace is YUV422, then force the colordepth - * to 12 bits. */ - if (ColorFormat == XVIDC_CSF_YCRCB_422) { - InstancePtr->Stream.Video.ColorDepth = XVIDC_BPC_12; - } + // Other colorspaces + else { + InstancePtr->Stream.Video.ColorDepth = Bpc; + } - // Other colorspaces - else { - InstancePtr->Stream.Video.ColorDepth = Bpc; - } - - InstancePtr->Stream.Video.PixPerClk = Ppc; + InstancePtr->Stream.Video.PixPerClk = Ppc; InstancePtr->Stream.Video.Timing = *XVidC_GetTimingInfo( - InstancePtr->Stream.Video.VmId); + InstancePtr->Stream.Video.VmId); InstancePtr->Stream.Video.FrameRate = XVidC_GetFrameRate( - InstancePtr->Stream.Video.VmId); + InstancePtr->Stream.Video.VmId); InstancePtr->Stream.Vic = XV_HdmiTx_LookupVic( - InstancePtr->Stream.Video.VmId); + InstancePtr->Stream.Video.VmId); InstancePtr->Stream.Video.IsInterlaced = XVidC_GetVideoFormat( - InstancePtr->Stream.Video.VmId); + InstancePtr->Stream.Video.VmId); - // Set TX pixel rate - XV_HdmiTx_SetPixelRate(InstancePtr); + // Set TX pixel rate + XV_HdmiTx_SetPixelRate(InstancePtr); - // Set TX color space - XV_HdmiTx_SetColorFormat(InstancePtr); + // Set TX color space + XV_HdmiTx_SetColorFormat(InstancePtr); - // Set TX color depth - XV_HdmiTx_SetColorDepth(InstancePtr); + // Set TX color depth + XV_HdmiTx_SetColorDepth(InstancePtr); - /* Calculate reference clock. First calculate the pixel clock */ - TmdsClock = XVidC_GetPixelClockHzByVmId(InstancePtr->Stream.Video.VmId); + /* Calculate reference clock. First calculate the pixel clock */ + TmdsClock = XVidC_GetPixelClockHzByVmId(InstancePtr->Stream.Video.VmId); - /* Store the pixel clock in the structure */ - InstancePtr->Stream.PixelClk = TmdsClock; + /* Store the pixel clock in the structure */ + InstancePtr->Stream.PixelClk = TmdsClock; - /* YUV420 */ - if (ColorFormat == (XVIDC_CSF_YCRCB_420)) { - /* In YUV420 the tmds clock is divided by two*/ - TmdsClock = TmdsClock / 2; - } + /* YUV420 */ + if (ColorFormat == (XVIDC_CSF_YCRCB_420)) { + /* In YUV420 the tmds clock is divided by two*/ + TmdsClock = TmdsClock / 2; + } - /* RGB, YUV444 and YUV420 */ - if ( ColorFormat != XVIDC_CSF_YCRCB_422 ) { + /* RGB, YUV444 and YUV420 */ + if ( ColorFormat != XVIDC_CSF_YCRCB_422 ) { - switch (Bpc) { + switch (Bpc) { - // 10-bits - case XVIDC_BPC_10 : - TmdsClock = TmdsClock * 5 / 4; - break; + // 10-bits + case XVIDC_BPC_10 : + TmdsClock = TmdsClock * 5 / 4; + break; - // 12-bits - case XVIDC_BPC_12 : - TmdsClock = TmdsClock * 3 / 2; - break; + // 12-bits + case XVIDC_BPC_12 : + TmdsClock = TmdsClock * 3 / 2; + break; - // 16-bits - case XVIDC_BPC_16 : - TmdsClock = TmdsClock * 2; - break; + // 16-bits + case XVIDC_BPC_16 : + TmdsClock = TmdsClock * 2; + break; - // 8-bits - default: - TmdsClock = TmdsClock; - break; - } - } + // 8-bits + default: + TmdsClock = TmdsClock; + break; + } + } - /* Store TMDS clock for future reference */ - InstancePtr->Stream.TMDSClock = TmdsClock; + /* Store TMDS clock for future reference */ + InstancePtr->Stream.TMDSClock = TmdsClock; - /* HDMI 2.0 */ - if (InstancePtr->Stream.IsHdmi20) { - if (TmdsClock > 340000000) { - InstancePtr->Stream.IsScrambled = (TRUE); - InstancePtr->Stream.TMDSClockRatio = 1; - } - else { - InstancePtr->Stream.IsScrambled = (FALSE); - InstancePtr->Stream.TMDSClockRatio = 0; - } - } + /* HDMI 2.0 */ + if (InstancePtr->Stream.IsHdmi20) { + if (TmdsClock > 340000000) { + InstancePtr->Stream.IsScrambled = (TRUE); + InstancePtr->Stream.TMDSClockRatio = 1; + } + else { + InstancePtr->Stream.IsScrambled = (FALSE); + InstancePtr->Stream.TMDSClockRatio = 0; + } + } - /* HDMI 1.4 */ - else { - InstancePtr->Stream.IsScrambled = (FALSE); - InstancePtr->Stream.TMDSClockRatio = 0; - } + /* HDMI 1.4 */ + else { + InstancePtr->Stream.IsScrambled = (FALSE); + InstancePtr->Stream.TMDSClockRatio = 0; + } - XV_HdmiTx_Scrambler(InstancePtr); - XV_HdmiTx_ClockRatio(InstancePtr); + XV_HdmiTx_Scrambler(InstancePtr); + XV_HdmiTx_ClockRatio(InstancePtr); - if ((InstancePtr->Stream.IsHdmi20 == (FALSE)) && (TmdsClock > 340000000)) { - TmdsClock = 0; - } + if ((InstancePtr->Stream.IsHdmi20 == (FALSE)) && (TmdsClock > 340000000)) { + TmdsClock = 0; + } - return TmdsClock; + return TmdsClock; } /*****************************************************************************/ @@ -760,74 +757,74 @@ XVidC_ColorFormat ColorFormat, XVidC_ColorDepth Bpc, XVidC_PixelsPerClock Ppc) * This function sets the HDMI TX stream parameters with reduced blanking. * Reduced blanking is applied when the original video line rate can't be * selected due to QPLL line rate holes -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. -* @param VideoMode specifies resolution identifier. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param VideoMode specifies resolution identifier. * -* @return TmdsClock, reference clock calculated based on the input -* parameters. +* @return TmdsClock, reference clock calculated based on the input +* parameters. * -* @note None. +* @note None. * ******************************************************************************/ u32 XV_HdmiTx_SetStreamReducedBlanking(XV_HdmiTx *InstancePtr) { - XVidC_VideoTiming *Timing; - u32 TmdsClock = 0; + XVidC_VideoTiming *Timing; + u32 TmdsClock = 0; - /* Verify arguments. */ - Xil_AssertNonvoid(InstancePtr != NULL); + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); Timing = (XVidC_VideoTiming *)XV_HdmiTx_GetReducedBlankingTimingInfo( - InstancePtr->Stream.Video.VmId); + InstancePtr->Stream.Video.VmId); // Check if the reduced timing was found if (Timing) { - InstancePtr->Stream.Video.Timing = *Timing; + InstancePtr->Stream.Video.Timing = *Timing; - /* Calculate reference clock. First calculate the pixel clock */ - TmdsClock = XVidC_GetPixelClockHzByHVFr( - InstancePtr->Stream.Video.Timing.HTotal, - InstancePtr->Stream.Video.Timing.F0PVTotal, - InstancePtr->Stream.Video.FrameRate); + /* Calculate reference clock. First calculate the pixel clock */ + TmdsClock = XVidC_GetPixelClockHzByHVFr( + InstancePtr->Stream.Video.Timing.HTotal, + InstancePtr->Stream.Video.Timing.F0PVTotal, + InstancePtr->Stream.Video.FrameRate); - /* Store the pixel clock in the structure */ - InstancePtr->Stream.PixelClk = TmdsClock; + /* Store the pixel clock in the structure */ + InstancePtr->Stream.PixelClk = TmdsClock; - /* YUV420 */ - if (InstancePtr->Stream.Video.ColorFormatId == (XVIDC_CSF_YCRCB_420)) { - /* In YUV420 the*/ - TmdsClock = TmdsClock / 2; - } + /* YUV420 */ + if (InstancePtr->Stream.Video.ColorFormatId == (XVIDC_CSF_YCRCB_420)) { + /* In YUV420 the*/ + TmdsClock = TmdsClock / 2; + } - /* RGB and YUV444 */ - else if ((InstancePtr->Stream.Video.ColorFormatId == (XVIDC_CSF_RGB)) || - (InstancePtr->Stream.Video.ColorFormatId == (XVIDC_CSF_YCRCB_444))) { + /* RGB and YUV444 */ + else if ((InstancePtr->Stream.Video.ColorFormatId == (XVIDC_CSF_RGB)) || + (InstancePtr->Stream.Video.ColorFormatId == (XVIDC_CSF_YCRCB_444))) { - switch (InstancePtr->Stream.Video.ColorDepth) { + switch (InstancePtr->Stream.Video.ColorDepth) { - // 10-bits - case XVIDC_BPC_10 : - TmdsClock = TmdsClock * 5 / 4; - break; + // 10-bits + case XVIDC_BPC_10 : + TmdsClock = TmdsClock * 5 / 4; + break; - // 12-bits - case XVIDC_BPC_12 : - TmdsClock = TmdsClock * 3 / 2; - break; + // 12-bits + case XVIDC_BPC_12 : + TmdsClock = TmdsClock * 3 / 2; + break; - // 16-bits - case XVIDC_BPC_16 : - TmdsClock = TmdsClock * 2; - break; - } - } + // 16-bits + case XVIDC_BPC_16 : + TmdsClock = TmdsClock * 2; + break; + } + } - if ((InstancePtr->Stream.IsHdmi20 == (FALSE)) && - (TmdsClock > 340000000)) { - TmdsClock = 0; - } - } - return TmdsClock; + if ((InstancePtr->Stream.IsHdmi20 == (FALSE)) && + (TmdsClock > 340000000)) { + TmdsClock = 0; + } + } + return TmdsClock; } /*****************************************************************************/ @@ -835,45 +832,45 @@ u32 XV_HdmiTx_SetStreamReducedBlanking(XV_HdmiTx *InstancePtr) * * This function sets the pixel rate at output. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note None. +* @note None. * ******************************************************************************/ void XV_HdmiTx_SetPixelRate(XV_HdmiTx *InstancePtr) { - u32 RegValue; + u32 RegValue; - /* Verify argument. */ - Xil_AssertVoid(InstancePtr != NULL); + /* Verify argument. */ + Xil_AssertVoid(InstancePtr != NULL); - /* Mask PIO Out Mask register */ - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_PIO_OUT_MSK_OFFSET), - (XV_HDMITX_PIO_OUT_PIXEL_RATE_MASK)); + /* Mask PIO Out Mask register */ + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_PIO_OUT_MSK_OFFSET), + (XV_HDMITX_PIO_OUT_PIXEL_RATE_MASK)); - /* Check for pixel width */ - switch (InstancePtr->Stream.Video.PixPerClk) { + /* Check for pixel width */ + switch (InstancePtr->Stream.Video.PixPerClk) { - case (XVIDC_PPC_2): - RegValue = 1; - break; + case (XVIDC_PPC_2): + RegValue = 1; + break; - case (XVIDC_PPC_4): - RegValue = 2; - break; + case (XVIDC_PPC_4): + RegValue = 2; + break; - default: - RegValue = 0; - break; - } + default: + RegValue = 0; + break; + } - /* Write pixel rate into PIO Out register */ - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_PIO_OUT_OFFSET), - (RegValue << (XV_HDMITX_PIO_OUT_PIXEL_RATE_SHIFT))); + /* Write pixel rate into PIO Out register */ + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_PIO_OUT_OFFSET), + (RegValue << (XV_HDMITX_PIO_OUT_PIXEL_RATE_SHIFT))); } /*****************************************************************************/ @@ -881,55 +878,55 @@ void XV_HdmiTx_SetPixelRate(XV_HdmiTx *InstancePtr) * * This function sets the sample rate at output. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. -* @param SampleRate specifies the value that needs to be set. -* - 3 samples per clock. -* - 5 samples per clock. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param SampleRate specifies the value that needs to be set. +* - 3 samples per clock. +* - 5 samples per clock. * -* @return None. +* @return None. * -* @note None. +* @note None. * ******************************************************************************/ void XV_HdmiTx_SetSampleRate(XV_HdmiTx *InstancePtr, u8 SampleRate) { - u32 RegValue; + u32 RegValue; - /* Verify argument. */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(SampleRate < 0xFF); + /* Verify argument. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(SampleRate < 0xFF); - // Store sample rate in structure - InstancePtr->Stream.SampleRate = SampleRate; + // Store sample rate in structure + InstancePtr->Stream.SampleRate = SampleRate; - // Mask PIO Out Mask register - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_PIO_OUT_MSK_OFFSET), - (XV_HDMITX_PIO_OUT_SAMPLE_RATE_MASK)); + // Mask PIO Out Mask register + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_PIO_OUT_MSK_OFFSET), + (XV_HDMITX_PIO_OUT_SAMPLE_RATE_MASK)); - // Check for sample rate - switch (SampleRate) { - case 3: - RegValue = 1; - break; + // Check for sample rate + switch (SampleRate) { + case 3: + RegValue = 1; + break; - case 4: - RegValue = 2; - break; + case 4: + RegValue = 2; + break; - case 5: - RegValue = 3; - break; + case 5: + RegValue = 3; + break; - default: - RegValue = 0; - break; - } + default: + RegValue = 0; + break; + } - // Write sample rate into PIO Out register - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_PIO_OUT_OFFSET), - (RegValue << (XV_HDMITX_PIO_OUT_SAMPLE_RATE_SHIFT))); + // Write sample rate into PIO Out register + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_PIO_OUT_OFFSET), + (RegValue << (XV_HDMITX_PIO_OUT_SAMPLE_RATE_SHIFT))); } /*****************************************************************************/ @@ -937,48 +934,48 @@ void XV_HdmiTx_SetSampleRate(XV_HdmiTx *InstancePtr, u8 SampleRate) * * This function sets the color format * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note None. +* @note None. * ******************************************************************************/ void XV_HdmiTx_SetColorFormat(XV_HdmiTx *InstancePtr) { - u32 RegValue; + u32 RegValue; - /* Verify argument. */ - Xil_AssertVoid(InstancePtr != NULL); + /* Verify argument. */ + Xil_AssertVoid(InstancePtr != NULL); - /* Mask PIO Out Mask register */ - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_PIO_OUT_MSK_OFFSET), - (XV_HDMITX_PIO_OUT_COLOR_SPACE_MASK)); + /* Mask PIO Out Mask register */ + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_PIO_OUT_MSK_OFFSET), + (XV_HDMITX_PIO_OUT_COLOR_SPACE_MASK)); - /* Check for color format */ - switch (InstancePtr->Stream.Video.ColorFormatId) { - case (XVIDC_CSF_YCRCB_444): - RegValue = 1; - break; + /* Check for color format */ + switch (InstancePtr->Stream.Video.ColorFormatId) { + case (XVIDC_CSF_YCRCB_444): + RegValue = 1; + break; - case (XVIDC_CSF_YCRCB_422): - RegValue = 2; - break; + case (XVIDC_CSF_YCRCB_422): + RegValue = 2; + break; - case (XVIDC_CSF_YCRCB_420): - RegValue = 3; - break; + case (XVIDC_CSF_YCRCB_420): + RegValue = 3; + break; - default: - RegValue = 0; - break; - } + default: + RegValue = 0; + break; + } - /* Write color space into PIO Out register */ - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_PIO_OUT_OFFSET), - (RegValue << (XV_HDMITX_PIO_OUT_COLOR_SPACE_SHIFT))); + /* Write color space into PIO Out register */ + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_PIO_OUT_OFFSET), + (RegValue << (XV_HDMITX_PIO_OUT_COLOR_SPACE_SHIFT))); } /*****************************************************************************/ @@ -986,51 +983,51 @@ void XV_HdmiTx_SetColorFormat(XV_HdmiTx *InstancePtr) * * This function sets the color depth * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note None. +* @note None. * ******************************************************************************/ void XV_HdmiTx_SetColorDepth(XV_HdmiTx *InstancePtr) { - u32 RegValue; + u32 RegValue; - /* Verify argument. */ - Xil_AssertVoid(InstancePtr != NULL); + /* Verify argument. */ + Xil_AssertVoid(InstancePtr != NULL); - /* Mask PIO Out Mask register */ - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_PIO_OUT_MSK_OFFSET), (XV_HDMITX_PIO_OUT_COLOR_DEPTH_MASK)); + /* Mask PIO Out Mask register */ + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_PIO_OUT_MSK_OFFSET), (XV_HDMITX_PIO_OUT_COLOR_DEPTH_MASK)); - // Color depth - switch (InstancePtr->Stream.Video.ColorDepth) { - // 10 bits - case (XVIDC_BPC_10): - RegValue = 1; - break; + // Color depth + switch (InstancePtr->Stream.Video.ColorDepth) { + // 10 bits + case (XVIDC_BPC_10): + RegValue = 1; + break; - // 12 bits - case (XVIDC_BPC_12): - RegValue = 2; - break; + // 12 bits + case (XVIDC_BPC_12): + RegValue = 2; + break; - // 16 bits - case (XVIDC_BPC_16): - RegValue = 3; - break; + // 16 bits + case (XVIDC_BPC_16): + RegValue = 3; + break; - // 8 bits - default: - RegValue = 0; - break; - } + // 8 bits + default: + RegValue = 0; + break; + } - /* Write color depth into PIO Out register */ - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_PIO_OUT_OFFSET), - (RegValue << (XV_HDMITX_PIO_OUT_COLOR_DEPTH_SHIFT))); + /* Write color depth into PIO Out register */ + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_PIO_OUT_OFFSET), + (RegValue << (XV_HDMITX_PIO_OUT_COLOR_DEPTH_SHIFT))); } /*****************************************************************************/ @@ -1038,29 +1035,29 @@ void XV_HdmiTx_SetColorDepth(XV_HdmiTx *InstancePtr) * * This function prepares TX DDC peripheral to use. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. -* @param Frequency specifies the value that needs to be set. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param Frequency specifies the value that needs to be set. * -* @return None. +* @return None. * -* @note None. +* @note None. * ******************************************************************************/ void XV_HdmiTx_DdcInit(XV_HdmiTx *InstancePtr, u32 Frequency) { - u32 RegValue; + u32 RegValue; - /* Verify arguments. */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(Frequency > 0x0); + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(Frequency > 0x0); - RegValue = (Frequency / 100000) / 2; - RegValue = ((RegValue) << (XV_HDMITX_DDC_CTRL_CLK_DIV_SHIFT)) & - ((XV_HDMITX_DDC_CTRL_CLK_DIV_MASK) << (XV_HDMITX_DDC_CTRL_CLK_DIV_SHIFT)); + RegValue = (Frequency / 100000) / 2; + RegValue = ((RegValue) << (XV_HDMITX_DDC_CTRL_CLK_DIV_SHIFT)) & + ((XV_HDMITX_DDC_CTRL_CLK_DIV_MASK) << (XV_HDMITX_DDC_CTRL_CLK_DIV_SHIFT)); - /* Update DDC Control register */ - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_DDC_CTRL_OFFSET), RegValue); + /* Update DDC Control register */ + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_DDC_CTRL_OFFSET), RegValue); } /*****************************************************************************/ @@ -1068,19 +1065,19 @@ void XV_HdmiTx_DdcInit(XV_HdmiTx *InstancePtr, u32 Frequency) * * This function gets the acknowledge flag * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @note None. +* @note None. * ******************************************************************************/ int XV_HdmiTx_DdcGetAck(XV_HdmiTx *InstancePtr) { - u32 Status; + u32 Status; - // Read status register - Status = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_DDC_STA_OFFSET)); - return (Status & XV_HDMITX_DDC_STA_ACK_MASK); + // Read status register + Status = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_DDC_STA_OFFSET)); + return (Status & XV_HDMITX_DDC_STA_ACK_MASK); } /*****************************************************************************/ @@ -1088,48 +1085,48 @@ int XV_HdmiTx_DdcGetAck(XV_HdmiTx *InstancePtr) * * This function waits for the done flag to be set * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @note None. +* @note None. * ******************************************************************************/ int XV_HdmiTx_DdcWaitForDone(XV_HdmiTx *InstancePtr) { - u32 Data; - u32 Status; - u32 Exit; + u32 Data; + u32 Status; + u32 Exit; - Exit = (FALSE); + Exit = (FALSE); - // Default status, assume failure - Status = XST_FAILURE; + // Default status, assume failure + Status = XST_FAILURE; - do { - // Read status register - Data = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_DDC_STA_OFFSET)); + do { + // Read status register + Data = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_DDC_STA_OFFSET)); - // Done - if (Data & (XV_HDMITX_DDC_STA_DONE_MASK)) { - // Clear done flag - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_DDC_STA_OFFSET), (XV_HDMITX_DDC_STA_DONE_MASK)); - Exit = (TRUE); - Status = XST_SUCCESS; - } + // Done + if (Data & (XV_HDMITX_DDC_STA_DONE_MASK)) { + // Clear done flag + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_DDC_STA_OFFSET), (XV_HDMITX_DDC_STA_DONE_MASK)); + Exit = (TRUE); + Status = XST_SUCCESS; + } - // Time out - else if (Data & (XV_HDMITX_DDC_STA_TIMEOUT_MASK)) { - // Clear time out flag - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_DDC_STA_OFFSET), (XV_HDMITX_DDC_STA_TIMEOUT_MASK)); - Exit = (TRUE); - Status = XST_FAILURE; - } + // Time out + else if (Data & (XV_HDMITX_DDC_STA_TIMEOUT_MASK)) { + // Clear time out flag + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_DDC_STA_OFFSET), (XV_HDMITX_DDC_STA_TIMEOUT_MASK)); + Exit = (TRUE); + Status = XST_FAILURE; + } - } while (!Exit); + } while (!Exit); - return Status; + return Status; } /*****************************************************************************/ @@ -1137,33 +1134,33 @@ int XV_HdmiTx_DdcWaitForDone(XV_HdmiTx *InstancePtr) * * This function writes data into the command fifo. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @note None. +* @note None. * ******************************************************************************/ void XV_HdmiTx_DdcWriteCommand(XV_HdmiTx *InstancePtr, u32 Cmd) { - u32 Status; - u32 Exit; + u32 Status; + u32 Exit; - Exit = (FALSE); + Exit = (FALSE); - do { - // Read status register - Status = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_DDC_STA_OFFSET)); + do { + // Read status register + Status = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_DDC_STA_OFFSET)); - // Mask command fifo full flag - Status &= XV_HDMITX_DDC_STA_CMD_FULL; + // Mask command fifo full flag + Status &= XV_HDMITX_DDC_STA_CMD_FULL; - // Check if the command fifo isn't full - if (!Status) { - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_DDC_CMD_OFFSET), (Cmd)); - Exit = (TRUE); - } - } while (!Exit); + // Check if the command fifo isn't full + if (!Status) { + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_DDC_CMD_OFFSET), (Cmd)); + Exit = (TRUE); + } + } while (!Exit); } /*****************************************************************************/ @@ -1171,36 +1168,36 @@ void XV_HdmiTx_DdcWriteCommand(XV_HdmiTx *InstancePtr, u32 Cmd) * * This function reads data from the data fifo. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @note None. +* @note None. * ******************************************************************************/ u8 XV_HdmiTx_DdcReadData(XV_HdmiTx *InstancePtr) { - u32 Status; - u32 Exit; - u32 Data; + u32 Status; + u32 Exit; + u32 Data; - Exit = (FALSE); + Exit = (FALSE); - do { - // Read status register - Status = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_DDC_STA_OFFSET)); + do { + // Read status register + Status = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_DDC_STA_OFFSET)); - // Mask data fifo empty flag - Status &= XV_HDMITX_DDC_STA_DAT_EMPTY; + // Mask data fifo empty flag + Status &= XV_HDMITX_DDC_STA_DAT_EMPTY; - // Check if the data fifo has data - if (!Status) { - Data = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_DDC_DAT_OFFSET)); - Exit = (TRUE); - } - } while (!Exit); + // Check if the data fifo has data + if (!Status) { + Data = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_DDC_DAT_OFFSET)); + Exit = (TRUE); + } + } while (!Exit); - return (Data); + return (Data); } /*****************************************************************************/ @@ -1208,120 +1205,120 @@ u8 XV_HdmiTx_DdcReadData(XV_HdmiTx *InstancePtr) * * This function writes data from DDC peripheral from given slave address. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. -* @param Slave specifies the slave address from where data needs to be -* read. -* @param Length specifies number of bytes to be read. -* @param Buffer specifies a pointer to u8 variable that will be -* filled with data. -* @param Stop specifies the stop flag which is either TRUE/FALSE. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param Slave specifies the slave address from where data needs to be +* read. +* @param Length specifies number of bytes to be read. +* @param Buffer specifies a pointer to u8 variable that will be +* filled with data. +* @param Stop specifies the stop flag which is either TRUE/FALSE. * * @return -* - XST_SUCCESS if an acknowledgement received and timeout. -* - XST_FAILURE if no acknowledgement received. +* - XST_SUCCESS if an acknowledgement received and timeout. +* - XST_FAILURE if no acknowledgement received. * -* @note None. +* @note None. * ******************************************************************************/ int XV_HdmiTx_DdcWrite(XV_HdmiTx *InstancePtr, u8 Slave, - u16 Length, u8 *Buffer, u8 Stop) + u16 Length, u8 *Buffer, u8 Stop) { - u32 Status; - u32 Data; - u32 Index; + u32 Status; + u32 Data; + u32 Index; - /* Verify arguments. */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(Slave > 0x0); - Xil_AssertNonvoid(Length > 0x0); - Xil_AssertNonvoid(Buffer != NULL); - Xil_AssertNonvoid((Stop == (TRUE)) || (Stop == (FALSE))); + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(Slave > 0x0); + Xil_AssertNonvoid(Length > 0x0); + Xil_AssertNonvoid(Buffer != NULL); + Xil_AssertNonvoid((Stop == (TRUE)) || (Stop == (FALSE))); - // Status default, assume failure - Status = XST_FAILURE; + // Status default, assume failure + Status = XST_FAILURE; - // Enable DDC peripheral - XV_HdmiTx_DdcEnable(InstancePtr); + // Enable DDC peripheral + XV_HdmiTx_DdcEnable(InstancePtr); - // Disable interrupt in DDC peripheral - // Polling is used - XV_HdmiTx_DdcIntrDisable(InstancePtr); + // Disable interrupt in DDC peripheral + // Polling is used + XV_HdmiTx_DdcIntrDisable(InstancePtr); - // Write start token - XV_HdmiTx_DdcWriteCommand(InstancePtr, (XV_HDMITX_DDC_CMD_STR_TOKEN)); + // Write start token + XV_HdmiTx_DdcWriteCommand(InstancePtr, (XV_HDMITX_DDC_CMD_STR_TOKEN)); - // First check if the slave can be addressed - // Write write token - XV_HdmiTx_DdcWriteCommand(InstancePtr, (XV_HDMITX_DDC_CMD_WR_TOKEN)); + // First check if the slave can be addressed + // Write write token + XV_HdmiTx_DdcWriteCommand(InstancePtr, (XV_HDMITX_DDC_CMD_WR_TOKEN)); - // Write length (high) - XV_HdmiTx_DdcWriteCommand(InstancePtr, 0); + // Write length (high) + XV_HdmiTx_DdcWriteCommand(InstancePtr, 0); - // Write length (low) - XV_HdmiTx_DdcWriteCommand(InstancePtr, 1); + // Write length (low) + XV_HdmiTx_DdcWriteCommand(InstancePtr, 1); - // Slave address - Data = Slave << 1; + // Slave address + Data = Slave << 1; - // Set write bit (low) - Data &= 0xFE; + // Set write bit (low) + Data &= 0xFE; - // Write slave address - XV_HdmiTx_DdcWriteCommand(InstancePtr, (Data)); + // Write slave address + XV_HdmiTx_DdcWriteCommand(InstancePtr, (Data)); - // Wait for done flag - if (XV_HdmiTx_DdcWaitForDone(InstancePtr) == XST_SUCCESS) { + // Wait for done flag + if (XV_HdmiTx_DdcWaitForDone(InstancePtr) == XST_SUCCESS) { - // Check acknowledge - if (XV_HdmiTx_DdcGetAck(InstancePtr)) { + // Check acknowledge + if (XV_HdmiTx_DdcGetAck(InstancePtr)) { - // Now write the data - // Write write token - XV_HdmiTx_DdcWriteCommand(InstancePtr, - (XV_HDMITX_DDC_CMD_WR_TOKEN)); + // Now write the data + // Write write token + XV_HdmiTx_DdcWriteCommand(InstancePtr, + (XV_HDMITX_DDC_CMD_WR_TOKEN)); - // Write length (high) - Data = ((Length >> 8) & 0xFF); - XV_HdmiTx_DdcWriteCommand(InstancePtr, Data); + // Write length (high) + Data = ((Length >> 8) & 0xFF); + XV_HdmiTx_DdcWriteCommand(InstancePtr, Data); - // Write length (low) - Data = (Length & 0xFF); - XV_HdmiTx_DdcWriteCommand(InstancePtr, Data); + // Write length (low) + Data = (Length & 0xFF); + XV_HdmiTx_DdcWriteCommand(InstancePtr, Data); - // Write Data - for (Index = 0; Index < Length; Index++) { - XV_HdmiTx_DdcWriteCommand(InstancePtr, *Buffer++); - } + // Write Data + for (Index = 0; Index < Length; Index++) { + XV_HdmiTx_DdcWriteCommand(InstancePtr, *Buffer++); + } - // Wait for done flag - if (XV_HdmiTx_DdcWaitForDone(InstancePtr) == XST_SUCCESS) { + // Wait for done flag + if (XV_HdmiTx_DdcWaitForDone(InstancePtr) == XST_SUCCESS) { - // Check acknowledge - // ACK - if (XV_HdmiTx_DdcGetAck(InstancePtr)) { + // Check acknowledge + // ACK + if (XV_HdmiTx_DdcGetAck(InstancePtr)) { - // Stop condition - if (Stop) { - // Write stop token - XV_HdmiTx_DdcWriteCommand(InstancePtr, - (XV_HDMITX_DDC_CMD_STP_TOKEN)); + // Stop condition + if (Stop) { + // Write stop token + XV_HdmiTx_DdcWriteCommand(InstancePtr, + (XV_HDMITX_DDC_CMD_STP_TOKEN)); - // Wait for done flag - XV_HdmiTx_DdcWaitForDone(InstancePtr); + // Wait for done flag + XV_HdmiTx_DdcWaitForDone(InstancePtr); - } + } - // Update status flag - Status = XST_SUCCESS; - } - } - } - } + // Update status flag + Status = XST_SUCCESS; + } + } + } + } - // Disable DDC peripheral - XV_HdmiTx_DdcDisable(InstancePtr); + // Disable DDC peripheral + XV_HdmiTx_DdcDisable(InstancePtr); - return Status; + return Status; } /*****************************************************************************/ @@ -1329,114 +1326,114 @@ int XV_HdmiTx_DdcWrite(XV_HdmiTx *InstancePtr, u8 Slave, * * This function reads data from DDC peripheral from given slave address. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. -* @param Slave specifies the slave address from where data needs to be -* read. -* @param Length specifies number of bytes to be read. -* @param Buffer specifies a pointer to u8 variable that will be -* filled with data. -* @param Stop specifies the stop flag which is either TRUE/FALSE. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param Slave specifies the slave address from where data needs to be +* read. +* @param Length specifies number of bytes to be read. +* @param Buffer specifies a pointer to u8 variable that will be +* filled with data. +* @param Stop specifies the stop flag which is either TRUE/FALSE. * * @return -* - XST_SUCCESS if an acknowledgement received and timeout. -* - XST_FAILURE if no acknowledgement received. +* - XST_SUCCESS if an acknowledgement received and timeout. +* - XST_FAILURE if no acknowledgement received. * -* @note None. +* @note None. * ******************************************************************************/ int XV_HdmiTx_DdcRead(XV_HdmiTx *InstancePtr, u8 Slave, u16 Length, - u8 *Buffer, u8 Stop) + u8 *Buffer, u8 Stop) { - u32 Status; - u32 Data; - u32 Index; + u32 Status; + u32 Data; + u32 Index; - /* Verify arguments. */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(Slave > 0x0); - Xil_AssertNonvoid(Length > 0x0); - Xil_AssertNonvoid(Buffer != NULL); - Xil_AssertNonvoid((Stop == (TRUE)) || (Stop == (FALSE))); + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(Slave > 0x0); + Xil_AssertNonvoid(Length > 0x0); + Xil_AssertNonvoid(Buffer != NULL); + Xil_AssertNonvoid((Stop == (TRUE)) || (Stop == (FALSE))); - // Status default, assume failure - Status = XST_FAILURE; + // Status default, assume failure + Status = XST_FAILURE; - // Enable DDC peripheral - XV_HdmiTx_DdcEnable(InstancePtr); + // Enable DDC peripheral + XV_HdmiTx_DdcEnable(InstancePtr); - // Disable interrupt in DDC peripheral - // Polling is used - XV_HdmiTx_DdcIntrDisable(InstancePtr); + // Disable interrupt in DDC peripheral + // Polling is used + XV_HdmiTx_DdcIntrDisable(InstancePtr); - // Write start token - XV_HdmiTx_DdcWriteCommand(InstancePtr, (XV_HDMITX_DDC_CMD_STR_TOKEN)); + // Write start token + XV_HdmiTx_DdcWriteCommand(InstancePtr, (XV_HDMITX_DDC_CMD_STR_TOKEN)); - // First check if the slave can be addressed - // Write write token - XV_HdmiTx_DdcWriteCommand(InstancePtr, (XV_HDMITX_DDC_CMD_WR_TOKEN)); + // First check if the slave can be addressed + // Write write token + XV_HdmiTx_DdcWriteCommand(InstancePtr, (XV_HDMITX_DDC_CMD_WR_TOKEN)); - // Write length (high) - XV_HdmiTx_DdcWriteCommand(InstancePtr, 0); + // Write length (high) + XV_HdmiTx_DdcWriteCommand(InstancePtr, 0); - // Write length (low) - XV_HdmiTx_DdcWriteCommand(InstancePtr, 1); + // Write length (low) + XV_HdmiTx_DdcWriteCommand(InstancePtr, 1); - // Slave address - Data = Slave << 1; + // Slave address + Data = Slave << 1; - // Set read bit (high) - Data |= 0x01; + // Set read bit (high) + Data |= 0x01; - // Write slave address - XV_HdmiTx_DdcWriteCommand(InstancePtr, (Data)); + // Write slave address + XV_HdmiTx_DdcWriteCommand(InstancePtr, (Data)); - // Wait for done flag - if (XV_HdmiTx_DdcWaitForDone(InstancePtr) == XST_SUCCESS) { + // Wait for done flag + if (XV_HdmiTx_DdcWaitForDone(InstancePtr) == XST_SUCCESS) { - // Check acknowledge - if (XV_HdmiTx_DdcGetAck(InstancePtr)) { + // Check acknowledge + if (XV_HdmiTx_DdcGetAck(InstancePtr)) { - // Write read token - XV_HdmiTx_DdcWriteCommand(InstancePtr, - (XV_HDMITX_DDC_CMD_RD_TOKEN)); + // Write read token + XV_HdmiTx_DdcWriteCommand(InstancePtr, + (XV_HDMITX_DDC_CMD_RD_TOKEN)); - // Write read length (high) - Data = (Length >> 8) & 0xFF; - XV_HdmiTx_DdcWriteCommand(InstancePtr, (Data)); + // Write read length (high) + Data = (Length >> 8) & 0xFF; + XV_HdmiTx_DdcWriteCommand(InstancePtr, (Data)); - // Write read length (low) - Data = Length & 0xFF; - XV_HdmiTx_DdcWriteCommand(InstancePtr, (Data)); + // Write read length (low) + Data = Length & 0xFF; + XV_HdmiTx_DdcWriteCommand(InstancePtr, (Data)); - // Read Data - for (Index = 0; Index < Length; Index++) { - *Buffer++ = XV_HdmiTx_DdcReadData(InstancePtr); - } + // Read Data + for (Index = 0; Index < Length; Index++) { + *Buffer++ = XV_HdmiTx_DdcReadData(InstancePtr); + } - // Wait for done flag - if (XV_HdmiTx_DdcWaitForDone(InstancePtr) == XST_SUCCESS) { + // Wait for done flag + if (XV_HdmiTx_DdcWaitForDone(InstancePtr) == XST_SUCCESS) { - // Stop condition - if (Stop) { - // Write stop token - XV_HdmiTx_DdcWriteCommand(InstancePtr, - (XV_HDMITX_DDC_CMD_STP_TOKEN)); + // Stop condition + if (Stop) { + // Write stop token + XV_HdmiTx_DdcWriteCommand(InstancePtr, + (XV_HDMITX_DDC_CMD_STP_TOKEN)); - // Wait for done flag - XV_HdmiTx_DdcWaitForDone(InstancePtr); + // Wait for done flag + XV_HdmiTx_DdcWaitForDone(InstancePtr); - } + } - // Update status - Status = XST_SUCCESS; - } - } - } + // Update status + Status = XST_SUCCESS; + } + } + } - // Disable DDC peripheral - XV_HdmiTx_DdcDisable(InstancePtr); + // Disable DDC peripheral + XV_HdmiTx_DdcDisable(InstancePtr); - return Status; + return Status; } /*****************************************************************************/ @@ -1444,47 +1441,47 @@ int XV_HdmiTx_DdcRead(XV_HdmiTx *InstancePtr, u8 Slave, u16 Length, * * This function transmits the infoframes generated by the processor. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * * @return -* - XST_SUCCESS if infoframes transmitted successfully. -* - XST_FAILURE if AUX FIFO is full. +* - XST_SUCCESS if infoframes transmitted successfully. +* - XST_FAILURE if AUX FIFO is full. * -* @note None. +* @note None. * ******************************************************************************/ int XV_HdmiTx_AuxSend(XV_HdmiTx *InstancePtr) { - u32 Index; - u32 Status; - u32 RegValue; + u32 Index; + u32 Status; + u32 RegValue; - /* Verify argument. */ - Xil_AssertNonvoid(InstancePtr != NULL); + /* Verify argument. */ + Xil_AssertNonvoid(InstancePtr != NULL); - /* Check if AUX FIFO has room */ - RegValue = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_AUX_STA_OFFSET)) & (XV_HDMITX_AUX_STA_FIFO_FUL_MASK); + /* Check if AUX FIFO has room */ + RegValue = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_AUX_STA_OFFSET)) & (XV_HDMITX_AUX_STA_FIFO_FUL_MASK); - if (RegValue) { - xdbg_printf((XDBG_DEBUG_GENERAL), "HDMI TX AUX FIFO full\r\n"); - Status = (XST_FAILURE); - } - else { - /* Update AUX with header data */ - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_AUX_DAT_OFFSET), InstancePtr->Aux.Header.Data); + if (RegValue) { + xdbg_printf((XDBG_DEBUG_GENERAL), "HDMI TX AUX FIFO full\r\n"); + Status = (XST_FAILURE); + } + else { + /* Update AUX with header data */ + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_AUX_DAT_OFFSET), InstancePtr->Aux.Header.Data); - /* Update AUX with actual data */ - for (Index = 0x0; Index < 8; Index++) { - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_AUX_DAT_OFFSET), InstancePtr->Aux.Data.Data[Index]); - } + /* Update AUX with actual data */ + for (Index = 0x0; Index < 8; Index++) { + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_AUX_DAT_OFFSET), InstancePtr->Aux.Data.Data[Index]); + } - Status = (XST_SUCCESS); - } + Status = (XST_SUCCESS); + } - return Status; + return Status; } /******************************************************************************/ @@ -1492,26 +1489,26 @@ int XV_HdmiTx_AuxSend(XV_HdmiTx *InstancePtr) * * This function prints stream and timing information on STDIO/Uart console. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note None. +* @note None. * ******************************************************************************/ void XV_HdmiTx_DebugInfo(XV_HdmiTx *InstancePtr) { - u32 Reset; + u32 Reset; - /* Verify argument. */ - Xil_AssertVoid(InstancePtr != NULL); + /* Verify argument. */ + Xil_AssertVoid(InstancePtr != NULL); - /* Print stream information */ - XVidC_ReportStreamInfo(&InstancePtr->Stream.Video); + /* Print stream information */ + XVidC_ReportStreamInfo(&InstancePtr->Stream.Video); - /* Print timing information */ - XVidC_ReportTiming(&InstancePtr->Stream.Video.Timing, - InstancePtr->Stream.Video.IsInterlaced); + /* Print timing information */ + XVidC_ReportTiming(&InstancePtr->Stream.Video.Timing, + InstancePtr->Stream.Video.IsInterlaced); } /*****************************************************************************/ @@ -1519,22 +1516,22 @@ void XV_HdmiTx_DebugInfo(XV_HdmiTx *InstancePtr) * * This function provides status of the stream * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * * @return -* - TRUE = Scrambled. -* - FALSE = Not scrambled. +* - TRUE = Scrambled. +* - FALSE = Not scrambled. * -* @note None. +* @note None. * ******************************************************************************/ int XV_HdmiTx_IsStreamScrambled(XV_HdmiTx *InstancePtr) { - /* Verify argument. */ - Xil_AssertNonvoid(InstancePtr != NULL); + /* Verify argument. */ + Xil_AssertNonvoid(InstancePtr != NULL); - return (InstancePtr->Stream.IsScrambled); + return (InstancePtr->Stream.IsScrambled); } /*****************************************************************************/ @@ -1542,22 +1539,22 @@ int XV_HdmiTx_IsStreamScrambled(XV_HdmiTx *InstancePtr) * * This function provides the stream connected status * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * * @return -* - TRUE = Stream is connected. -* - FALSE = Stream is connected. +* - TRUE = Stream is connected. +* - FALSE = Stream is connected. * -* @note None. +* @note None. * ******************************************************************************/ int XV_HdmiTx_IsStreamConnected(XV_HdmiTx *InstancePtr) { - /* Verify argument. */ - Xil_AssertNonvoid(InstancePtr != NULL); + /* Verify argument. */ + Xil_AssertNonvoid(InstancePtr != NULL); - return (InstancePtr->Stream.IsConnected); + return (InstancePtr->Stream.IsConnected); } /*****************************************************************************/ @@ -1565,69 +1562,69 @@ int XV_HdmiTx_IsStreamConnected(XV_HdmiTx *InstancePtr) * * This function sets the active audio channels * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * * @return -* - XST_SUCCESS if active channels were set. -* - XST_FAILURE if no active channles were set. +* - XST_SUCCESS if active channels were set. +* - XST_FAILURE if no active channles were set. * -* @note None. +* @note None. * ******************************************************************************/ int XV_HdmiTx_SetAudioChannels(XV_HdmiTx *InstancePtr, u8 Value) { - u32 Data; - u32 Status; + u32 Data; + u32 Status; - // Stop peripheral - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, - (XV_HDMITX_AUD_CTRL_CLR_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK)); + // Stop peripheral + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, + (XV_HDMITX_AUD_CTRL_CLR_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK)); - switch (Value) { + switch (Value) { - // 8 Channels - case 8: - Data = 3 << XV_HDMITX_AUD_CTRL_CH_SHIFT; - Status = (XST_SUCCESS); - break; + // 8 Channels + case 8: + Data = 3 << XV_HDMITX_AUD_CTRL_CH_SHIFT; + Status = (XST_SUCCESS); + break; - // 6 Channels - case 6: - Data = 2 << XV_HDMITX_AUD_CTRL_CH_SHIFT; - Status = (XST_SUCCESS); - break; + // 6 Channels + case 6: + Data = 2 << XV_HDMITX_AUD_CTRL_CH_SHIFT; + Status = (XST_SUCCESS); + break; - // 4 Channels - case 4: - Data = 1 << XV_HDMITX_AUD_CTRL_CH_SHIFT; - Status = (XST_SUCCESS); - break; + // 4 Channels + case 4: + Data = 1 << XV_HDMITX_AUD_CTRL_CH_SHIFT; + Status = (XST_SUCCESS); + break; - // 2 Channels - case 2: - Data = 0 << XV_HDMITX_AUD_CTRL_CH_SHIFT; - Status = (XST_SUCCESS); - break; + // 2 Channels + case 2: + Data = 0 << XV_HDMITX_AUD_CTRL_CH_SHIFT; + Status = (XST_SUCCESS); + break; - default : - Status = (XST_FAILURE); - break; - } + default : + Status = (XST_FAILURE); + break; + } - if (Status == (XST_SUCCESS)) { - // Set active channels - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, - (XV_HDMITX_AUD_CTRL_OFFSET), (Data)); + if (Status == (XST_SUCCESS)) { + // Set active channels + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, + (XV_HDMITX_AUD_CTRL_OFFSET), (Data)); - // Store active channel in structure - (InstancePtr)->Stream.Audio.Channels = Value; + // Store active channel in structure + (InstancePtr)->Stream.Audio.Channels = Value; - // Start peripheral - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, - (XV_HDMITX_AUD_CTRL_SET_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK)); - } + // Start peripheral + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, + (XV_HDMITX_AUD_CTRL_SET_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK)); + } - return Status; + return Status; } /*****************************************************************************/ @@ -1638,17 +1635,17 @@ int XV_HdmiTx_SetAudioChannels(XV_HdmiTx *InstancePtr, u8 Value) * handlers are set to this callback. It is considered an error for this * handler to be invoked. * -* @param CallbackRef is a callback reference passed in by the upper -* layer when setting the callback functions, and passed back to -* the upper layer when the callback is invoked. +* @param CallbackRef is a callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. * -* @return None. +* @return None. * -* @note None. +* @note None. * ******************************************************************************/ static void StubCallback(void *Callback) { - Xil_AssertVoid(Callback != NULL); - Xil_AssertVoidAlways(); + Xil_AssertVoid(Callback != NULL); + Xil_AssertVoidAlways(); } diff --git a/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx.h b/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx.h old mode 100755 new mode 100644 index 98979fc7..55050f8c --- a/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx.h +++ b/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx.h @@ -126,8 +126,8 @@ * ******************************************************************************/ #ifndef XV_HDMITX_H_ -#define XV_HDMITX_H_ /**< Prevent circular inclusions - * by using protection macros */ +#define XV_HDMITX_H_ /**< Prevent circular inclusions + * by using protection macros */ #ifdef __cplusplus extern "C" { @@ -154,10 +154,10 @@ extern "C" { * interrupt requests from peripheral. */ typedef enum { - XV_HDMITX_HANDLER_CONNECT = 1, // Handler for connect - XV_HDMITX_HANDLER_VS, // Handler for vsync - XV_HDMITX_HANDLER_STREAM_DOWN, // Handler for stream down - XV_HDMITX_HANDLER_STREAM_UP // Handler for stream up + XV_HDMITX_HANDLER_CONNECT = 1, // Handler for connect + XV_HDMITX_HANDLER_VS, // Handler for vsync + XV_HDMITX_HANDLER_STREAM_DOWN, // Handler for stream down + XV_HDMITX_HANDLER_STREAM_UP // Handler for stream up } XV_HdmiTx_HandlerType; /*@}*/ @@ -165,8 +165,8 @@ typedef enum { * @{ */ typedef enum { - XV_HDMITX_STATE_STREAM_DOWN, // Stream down - XV_HDMITX_STATE_STREAM_UP // Stream up + XV_HDMITX_STATE_STREAM_DOWN, // Stream down + XV_HDMITX_STATE_STREAM_UP // Stream up } XV_HdmiTx_State; /** @@ -174,91 +174,91 @@ typedef enum { * Each HDMI TX device should have a configuration structure associated. */ typedef struct { - u16 DeviceId; /**< DeviceId is the unique ID of the HDMI TX core */ - u32 BaseAddress; /**< BaseAddress is the physical - * base address of the core's registers */ + u16 DeviceId; /**< DeviceId is the unique ID of the HDMI TX core */ + u32 BaseAddress; /**< BaseAddress is the physical + * base address of the core's registers */ } XV_HdmiTx_Config; /** * This typedef contains Video identification information in tabular form. */ typedef struct { - XVidC_VideoMode VmId; /**< Video mode/Resolution ID */ - u8 Vic; /**< Video Identification code */ + XVidC_VideoMode VmId; /**< Video mode/Resolution ID */ + u8 Vic; /**< Video Identification code */ } XV_HdmiTx_VicTable; /** * This typedef contains Video identification information in tabular form. */ typedef struct { - XVidC_VideoMode VmId; /**< Video mode/Resolution ID */ - XVidC_VideoTiming Timing; /**< Video Timing*/ + XVidC_VideoMode VmId; /**< Video mode/Resolution ID */ + XVidC_VideoTiming Timing; /**< Video Timing*/ } XV_HdmiTx_ReducedBlankingTable; /** * This typedef contains audio stream specific data structure */ typedef struct { - u8 Channels; //< Video Identification code */ + u8 Channels; //< Video Identification code */ } XV_HdmiTx_AudioStream; /** * This typedef contains HDMI TX stream specific data structure. */ typedef struct { - XVidC_VideoStream Video; /**< Video stream for HDMI TX */ - XV_HdmiTx_AudioStream Audio; /**< Audio stream for HDMI TX */ - u8 Vic; /**< Video Identification code - flag */ - u8 IsHdmi; /**< HDMI flag. 1 - HDMI Stream, - 0 - DVI Stream */ - u8 IsHdmi20; /**< HDMI 2.0 flag */ - u8 IsScrambled; /**< Scrambler flag - 1 - scrambled data , 0 - non scrambled data */ - u32 TMDSClock; /**< TMDS clock */ - u8 TMDSClockRatio; /**< TMDS clock ration - 0 - 1/10, 1 - 1/40 */ - u32 PixelClk; /**< Pixel Clock */ - XV_HdmiTx_State State; /**< State */ - u8 IsConnected; /**< Connected flag. - This flag is set when the cable is connected */ - u8 SampleRate; /**< Sample rate */ + XVidC_VideoStream Video; /**< Video stream for HDMI TX */ + XV_HdmiTx_AudioStream Audio; /**< Audio stream for HDMI TX */ + u8 Vic; /**< Video Identification code + flag */ + u8 IsHdmi; /**< HDMI flag. 1 - HDMI Stream, + 0 - DVI Stream */ + u8 IsHdmi20; /**< HDMI 2.0 flag */ + u8 IsScrambled; /**< Scrambler flag + 1 - scrambled data , 0 - non scrambled data */ + u32 TMDSClock; /**< TMDS clock */ + u8 TMDSClockRatio; /**< TMDS clock ration + 0 - 1/10, 1 - 1/40 */ + u32 PixelClk; /**< Pixel Clock */ + XV_HdmiTx_State State; /**< State */ + u8 IsConnected; /**< Connected flag. + This flag is set when the cable is connected */ + u8 SampleRate; /**< Sample rate */ } XV_HdmiTx_Stream; /** * This typedef contains Auxiliary header information for infoframe. */ typedef union { - u32 Data; /**< AUX header data field */ - u8 Byte[4]; /**< AUX header byte field */ + u32 Data; /**< AUX header data field */ + u8 Byte[4]; /**< AUX header byte field */ } XV_HdmiTx_AuxHeader; /** * This typedef contains Auxiliary data information for infoframe. */ typedef union { - u32 Data[8]; /**< AUX data field */ - u8 Byte[32]; /**< AUX data byte field */ + u32 Data[8]; /**< AUX data field */ + u8 Byte[32]; /**< AUX data byte field */ } XV_HdmiTx_AuxData; /** * This typedef holds HDMI TX's Auxiliary peripheral specific data structure. */ typedef struct { - XV_HdmiTx_AuxHeader Header; /**< AUX header field */ - XV_HdmiTx_AuxData Data; /**< AUX data field */ + XV_HdmiTx_AuxHeader Header; /**< AUX header field */ + XV_HdmiTx_AuxData Data; /**< AUX data field */ } XV_HdmiTx_Aux; /** * Callback type for Vsync event interrupt. * -* @param CallbackRef is a callback reference passed in by the upper -* layer when setting the callback functions, and passed back to -* the upper layer when the callback is invoked. +* @param CallbackRef is a callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. * -* @return None. +* @return None. * -* @note None. +* @note None. * */ typedef void (*XV_HdmiTx_Callback)(void *CallbackRef); @@ -268,44 +268,44 @@ typedef void (*XV_HdmiTx_Callback)(void *CallbackRef); * HDMI TX core in use. */ typedef struct { - XV_HdmiTx_Config Config; /**< Hardware Configuration */ - u32 IsReady; /**< Core and the driver instance are initialized */ + XV_HdmiTx_Config Config; /**< Hardware Configuration */ + u32 IsReady; /**< Core and the driver instance are initialized */ - /* Callbacks */ - XV_HdmiTx_Callback ConnectCallback; /**< Callback for connect event - interrupt */ - void *ConnectRef; /**< To be passed to the connect - interrupt callback */ - u32 IsConnectCallbackSet; /**< Set flag. This flag is set - to true when the callback has been registered */ + /* Callbacks */ + XV_HdmiTx_Callback ConnectCallback; /**< Callback for connect event + interrupt */ + void *ConnectRef; /**< To be passed to the connect + interrupt callback */ + u32 IsConnectCallbackSet; /**< Set flag. This flag is set + to true when the callback has been registered */ - XV_HdmiTx_Callback VsCallback; /**< Callback for Vsync event - interrupt */ - void *VsRef; /**< To be passed to the Vsync - interrupt callback */ - u32 IsVsCallbackSet; /**< Set flag. This flag is set to - true when the callback has been registered */ + XV_HdmiTx_Callback VsCallback; /**< Callback for Vsync event + interrupt */ + void *VsRef; /**< To be passed to the Vsync + interrupt callback */ + u32 IsVsCallbackSet; /**< Set flag. This flag is set to + true when the callback has been registered */ - XV_HdmiTx_Callback StreamDownCallback; /**< Callback for stream down - callback */ - void *StreamDownRef; /**< To be passed to the stream - down callback */ - u32 IsStreamDownCallbackSet; /**< Set flag. This flag is set to - true when the callback has been registered */ + XV_HdmiTx_Callback StreamDownCallback; /**< Callback for stream down + callback */ + void *StreamDownRef; /**< To be passed to the stream + down callback */ + u32 IsStreamDownCallbackSet; /**< Set flag. This flag is set to + true when the callback has been registered */ - XV_HdmiTx_Callback StreamUpCallback; /**< Callback for stream up - callback */ - void *StreamUpRef; /**< To be passed to the stream up - callback */ - u32 IsStreamUpCallbackSet; /**< Set flag. This flag is set to - true when the callback has been registered */ + XV_HdmiTx_Callback StreamUpCallback; /**< Callback for stream up + callback */ + void *StreamUpRef; /**< To be passed to the stream up + callback */ + u32 IsStreamUpCallbackSet; /**< Set flag. This flag is set to + true when the callback has been registered */ - /* Aux peripheral specific */ - volatile XV_HdmiTx_Aux Aux; /**< AUX peripheral information */ + /* Aux peripheral specific */ + volatile XV_HdmiTx_Aux Aux; /**< AUX peripheral information */ - /* HDMI TX stream */ - XV_HdmiTx_Stream Stream; /**< HDMI TX stream information */ - u32 CpuClkFreq; /**< CPU Clock frequency */ + /* HDMI TX stream */ + XV_HdmiTx_Stream Stream; /**< HDMI TX stream information */ + u32 CpuClkFreq; /* CPU Clock frequency */ } XV_HdmiTx; @@ -331,30 +331,30 @@ typedef struct { * * This macro asserts or releases the HDMI TX reset. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. -* @param Reset specifies TRUE/FALSE value to either assert or -* release HDMI TX reset. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param Reset specifies TRUE/FALSE value to either assert or +* release HDMI TX reset. * -* @return None. +* @return None. * -* @note The reset output of the PIO is inverted. When the system is -* in reset, the PIO output is cleared and this will reset the -* HDMI RX. Therefore, clearing the PIO reset output will assert -* the HDMI link and video reset. -* C-style signature: -* void XV_HdmiTx_Reset(XV_HdmiTx *InstancePtr, u8 Reset) +* @note The reset output of the PIO is inverted. When the system is +* in reset, the PIO output is cleared and this will reset the +* HDMI RX. Therefore, clearing the PIO reset output will assert +* the HDMI link and video reset. +* C-style signature: +* void XV_HdmiTx_Reset(XV_HdmiTx *InstancePtr, u8 Reset) * ******************************************************************************/ #define XV_HdmiTx_Reset(InstancePtr, Reset) \ { \ - if (Reset) { \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_PIO_OUT_CLR_OFFSET), (XV_HDMITX_PIO_OUT_RST_MASK)); \ - } \ - else { \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_PIO_OUT_SET_OFFSET), (XV_HDMITX_PIO_OUT_RST_MASK)); \ - } \ + if (Reset) { \ + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_PIO_OUT_CLR_OFFSET), (XV_HDMITX_PIO_OUT_RST_MASK)); \ + } \ + else { \ + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_PIO_OUT_SET_OFFSET), (XV_HDMITX_PIO_OUT_RST_MASK)); \ + } \ } /*****************************************************************************/ @@ -362,28 +362,28 @@ typedef struct { * * This macro controls the HDMI TX Scrambler. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. -* @param SetClr specifies TRUE/FALSE value to either set ON or clear -* Scrambler. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param SetClr specifies TRUE/FALSE value to either set ON or clear +* Scrambler. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_SetScrambler(XV_HdmiTx *InstancePtr, u8 SetClr) +* @note C-style signature: +* void XV_HdmiTx_SetScrambler(XV_HdmiTx *InstancePtr, u8 SetClr) * ******************************************************************************/ #define XV_HdmiTx_SetScrambler(InstancePtr, SetClr) \ { \ - if (SetClr) { \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_PIO_OUT_SET_OFFSET), (XV_HDMITX_PIO_OUT_SCRM_MASK)); \ - (InstancePtr)->Stream.IsScrambled = (TRUE); \ - } \ - else { \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_PIO_OUT_CLR_OFFSET), (XV_HDMITX_PIO_OUT_SCRM_MASK)); \ - (InstancePtr)->Stream.IsScrambled = (FALSE); \ - } \ + if (SetClr) { \ + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_PIO_OUT_SET_OFFSET), (XV_HDMITX_PIO_OUT_SCRM_MASK)); \ + (InstancePtr)->Stream.IsScrambled = (TRUE); \ + } \ + else { \ + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_PIO_OUT_CLR_OFFSET), (XV_HDMITX_PIO_OUT_SCRM_MASK)); \ + (InstancePtr)->Stream.IsScrambled = (FALSE); \ + } \ } /*****************************************************************************/ @@ -391,388 +391,388 @@ typedef struct { * * This macro enables the HDMI TX PIO peripheral. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_PioEnable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_PioEnable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_PioEnable(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_PIO_CTRL_SET_OFFSET), (XV_HDMITX_PIO_CTRL_RUN_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_PIO_CTRL_SET_OFFSET), (XV_HDMITX_PIO_CTRL_RUN_MASK)) /*****************************************************************************/ /** * * This macro disables the HDMI TX PIO peripheral. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_PioDisable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_PioDisable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_PioDisable(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_PIO_CTRL_CLR_OFFSET), (XV_HDMITX_PIO_CTRL_RUN_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_PIO_CTRL_CLR_OFFSET), (XV_HDMITX_PIO_CTRL_RUN_MASK)) /*****************************************************************************/ /** * * This macro enables interrupt in the HDMI TX PIO peripheral. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_PioIntrEnable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_PioIntrEnable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_PioIntrEnable(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_PIO_CTRL_SET_OFFSET), (XV_HDMITX_PIO_CTRL_IE_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_PIO_CTRL_SET_OFFSET), (XV_HDMITX_PIO_CTRL_IE_MASK)) /*****************************************************************************/ /** * * This macro disables interrupt in the HDMI TX PIO peripheral. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_PioIntrDisable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_PioIntrDisable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_PioIntrDisable(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_PIO_CTRL_CLR_OFFSET), (XV_HDMITX_PIO_CTRL_IE_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_PIO_CTRL_CLR_OFFSET), (XV_HDMITX_PIO_CTRL_IE_MASK)) /*****************************************************************************/ /** * * This macro clears HDMI TX PIO interrupt. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_PioIntrClear(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_PioIntrClear(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_PioIntrClear(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_PIO_STA_OFFSET), (XV_HDMITX_PIO_STA_IRQ_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_PIO_STA_OFFSET), (XV_HDMITX_PIO_STA_IRQ_MASK)) /*****************************************************************************/ /** * * This macro enables the HDMI TX Display Data Channel (DDC) peripheral. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_DdcEnable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_DdcEnable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_DdcEnable(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_DDC_CTRL_SET_OFFSET), (XV_HDMITX_DDC_CTRL_RUN_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_DDC_CTRL_SET_OFFSET), (XV_HDMITX_DDC_CTRL_RUN_MASK)) /*****************************************************************************/ /** * * This macro disables the HDMI TX Display Data Channel (DDC) peripheral. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_DdcDisable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_DdcDisable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_DdcDisable(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_DDC_CTRL_CLR_OFFSET), (XV_HDMITX_DDC_CTRL_RUN_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_DDC_CTRL_CLR_OFFSET), (XV_HDMITX_DDC_CTRL_RUN_MASK)) /*****************************************************************************/ /** * * This macro enables interrupt in the HDMI TX DDC peripheral. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_DdcIntrEnable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_DdcIntrEnable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_DdcIntrEnable(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_DDC_CTRL_SET_OFFSET), (XV_HDMITX_DDC_CTRL_IE_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_DDC_CTRL_SET_OFFSET), (XV_HDMITX_DDC_CTRL_IE_MASK)) /*****************************************************************************/ /** * * This macro disables interrupt in the HDMI TX DDC peripheral. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_DdcIntrDisable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_DdcIntrDisable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_DdcIntrDisable(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_DDC_CTRL_CLR_OFFSET), (XV_HDMITX_DDC_CTRL_IE_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_DDC_CTRL_CLR_OFFSET), (XV_HDMITX_DDC_CTRL_IE_MASK)) /*****************************************************************************/ /** * * This macro clears HDMI TX DDC interrupt. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_DdcIntrClear(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_DdcIntrClear(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_DdcIntrClear(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_DDC_STA_OFFSET), (XV_HDMITX_DDC_STA_IRQ_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_DDC_STA_OFFSET), (XV_HDMITX_DDC_STA_IRQ_MASK)) /*****************************************************************************/ /** * * This macro enables the HDMI TX Auxiliary (AUX) peripheral. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_AuxEnable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_AuxEnable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_AuxEnable(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_AUX_CTRL_SET_OFFSET), (XV_HDMITX_AUX_CTRL_RUN_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_AUX_CTRL_SET_OFFSET), (XV_HDMITX_AUX_CTRL_RUN_MASK)) /*****************************************************************************/ /** * * This macro disables the HDMI TX Auxiliary (AUX) peripheral. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_AuxDisable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_AuxDisable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_AuxDisable(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_AUX_CTRL_CLR_OFFSET), (XV_HDMITX_AUX_CTRL_RUN_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_AUX_CTRL_CLR_OFFSET), (XV_HDMITX_AUX_CTRL_RUN_MASK)) /*****************************************************************************/ /** * * This macro enables interrupt in the HDMI TX AUX peripheral. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_AuxIntrEnable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_AuxIntrEnable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_AuxIntrEnable(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_AUX_CTRL_SET_OFFSET), (XV_HDMITX_AUX_CTRL_IE_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_AUX_CTRL_SET_OFFSET), (XV_HDMITX_AUX_CTRL_IE_MASK)) /*****************************************************************************/ /** * * This macro disables interrupt in the HDMI TX AUX peripheral. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_AuxIntrDisable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_AuxIntrDisable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_AuxIntrDisable(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_AUX_CTRL_CLR_OFFSET), (XV_HDMITX_AUX_CTRL_IE_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_AUX_CTRL_CLR_OFFSET), (XV_HDMITX_AUX_CTRL_IE_MASK)) /*****************************************************************************/ /** * * This macro enables audio in HDMI TX core. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_AudioEnable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_AudioEnable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_AudioEnable(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_AUD_CTRL_SET_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_AUD_CTRL_SET_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK)) /*****************************************************************************/ /** * * This macro disables audio in HDMI TX core. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_AudioDisable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_AudioDisable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_AudioDisable(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_AUD_CTRL_CLR_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_AUD_CTRL_CLR_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK)) /*****************************************************************************/ /** * * This macro unmutes audio in HDMI TX core. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_AudioEnable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_AudioEnable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_AudioUnmute(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_AUD_CTRL_SET_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_AUD_CTRL_SET_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK)) /*****************************************************************************/ /** * * This macro mutes audio in HDMI TX core. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_AudioDisable(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_AudioDisable(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_AudioMute(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_AUD_CTRL_CLR_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_AUD_CTRL_CLR_OFFSET), (XV_HDMITX_AUD_CTRL_RUN_MASK)) /*****************************************************************************/ /** * * This macro sets the mode to operate in. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_SetMode(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* void XV_HdmiTx_SetMode(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_SetMode(InstancePtr) \ - XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_PIO_OUT_SET_OFFSET), (XV_HDMITX_PIO_OUT_MODE_MASK)) + XV_HdmiTx_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_PIO_OUT_SET_OFFSET), (XV_HDMITX_PIO_OUT_MODE_MASK)) /*****************************************************************************/ /** * * This macro provides the current mode. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return Current mode. -* 0 = DVI -* 1 = HDMI +* @return Current mode. +* 0 = DVI +* 1 = HDMI * -* @note C-style signature: -* u8 XV_HdmiTx_GetMode(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* u8 XV_HdmiTx_GetMode(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_GetMode(InstancePtr) \ - XV_HdmiTx_ReadReg((InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_PIO_OUT_OFFSET)) & (XV_HDMITX_PIO_OUT_MODE_MASK) + XV_HdmiTx_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_PIO_OUT_OFFSET)) & (XV_HDMITX_PIO_OUT_MODE_MASK) /*****************************************************************************/ /** * * This macro provides the current sample rate. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return Sample rate +* @return Sample rate * -* @note C-style signature: -* u8 XV_HdmiTx_GetMode(XV_HdmiTx *InstancePtr) +* @note C-style signature: +* u8 XV_HdmiTx_GetMode(XV_HdmiTx *InstancePtr) * ******************************************************************************/ #define XV_HdmiTx_GetSampleRate(InstancePtr) \ - (InstancePtr)->Stream.SampleRate + (InstancePtr)->Stream.SampleRate /*****************************************************************************/ /** * * This macro provides the active audio channels. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return Audio channels +* @return Audio channels * * ******************************************************************************/ #define XV_HdmiTx_GetAudioChannels(InstancePtr) \ - (InstancePtr)->Stream.Audio.Channels + (InstancePtr)->Stream.Audio.Channels /*****************************************************************************/ /** * * This macro provides the current pixel packing phase. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * -* @return Pixel packing phase. +* @return Pixel packing phase. * * ******************************************************************************/ #define XV_HdmiTx_GetPixelPackingPhase(InstancePtr) \ - ( ( (XV_HdmiTx_ReadReg( (InstancePtr)->Config.BaseAddress, \ - (XV_HDMITX_PIO_IN_OFFSET) ) ) >> (XV_HDMITX_PIO_IN_PPP_SHIFT)) \ - & (XV_HDMITX_PIO_IN_PPP_MASK)) + ( ( (XV_HdmiTx_ReadReg( (InstancePtr)->Config.BaseAddress, \ + (XV_HDMITX_PIO_IN_OFFSET) ) ) >> (XV_HDMITX_PIO_IN_PPP_SHIFT)) \ + & (XV_HDMITX_PIO_IN_PPP_MASK)) /************************** Function Prototypes ******************************/ @@ -781,16 +781,16 @@ XV_HdmiTx_Config *XV_HdmiTx_LookupConfig(u16 DeviceId); /* Initialization and control functions in xv_hdmitx.c */ int XV_HdmiTx_CfgInitialize(XV_HdmiTx *InstancePtr, - XV_HdmiTx_Config *CfgPtr, - u32 EffectiveAddr); + XV_HdmiTx_Config *CfgPtr, + u32 EffectiveAddr); void XV_HdmiTx_Clear(XV_HdmiTx *InstancePtr); u8 XV_HdmiTx_GetVic(XVidC_VideoMode VideoMode); XVidC_VideoMode XV_HdmiTx_GetVideoModeFromVic(u8 Vic); u32 XV_HdmiTx_SetStream(XV_HdmiTx *InstancePtr, - XVidC_VideoMode VideoMode, - XVidC_ColorFormat ColorFormat, - XVidC_ColorDepth Bpc, - XVidC_PixelsPerClock Ppc); + XVidC_VideoMode VideoMode, + XVidC_ColorFormat ColorFormat, + XVidC_ColorDepth Bpc, + XVidC_PixelsPerClock Ppc); u32 XV_HdmiTx_SetStreamReducedBlanking(XV_HdmiTx *InstancePtr); void XV_HdmiTx_SetPixelRate(XV_HdmiTx *InstancePtr); void XV_HdmiTx_SetSampleRate(XV_HdmiTx *InstancePtr, u8 SampleRate); @@ -800,9 +800,9 @@ int XV_HdmiTx_IsStreamScrambled(XV_HdmiTx *InstancePtr); int XV_HdmiTx_IsStreamConnected(XV_HdmiTx *InstancePtr); void XV_HdmiTx_DdcInit(XV_HdmiTx *InstancePtr, u32 Frequency); int XV_HdmiTx_DdcWrite(XV_HdmiTx *InstancePtr, u8 Slave, u16 Length, - u8 *Buffer, u8 Stop); + u8 *Buffer, u8 Stop); int XV_HdmiTx_DdcRead(XV_HdmiTx *InstancePtr, u8 Slave, u16 Length, - u8 *Buffer, u8 Stop); + u8 *Buffer, u8 Stop); int XV_HdmiTx_AuxSend(XV_HdmiTx *InstancePtr); int XV_HdmiTx_Scrambler(XV_HdmiTx *InstancePtr); int XV_HdmiTx_ClockRatio(XV_HdmiTx *InstancePtr); @@ -817,7 +817,7 @@ int XV_HdmiTx_SelfTest(XV_HdmiTx *InstancePtr); /* Interrupt related functions in xv_hdmitx_intr.c */ void XV_HdmiTx_IntrHandler(void *InstancePtr); int XV_HdmiTx_SetCallback(XV_HdmiTx *InstancePtr, u32 HandlerType, - void *CallbackFunc, void *CallbackRef); + void *CallbackFunc, void *CallbackRef); /************************** Variable Declarations ****************************/ diff --git a/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_g.c b/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_g.c old mode 100755 new mode 100644 index ce4b05be..bcc1dac3 --- a/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_g.c +++ b/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_g.c @@ -46,8 +46,9 @@ XV_HdmiTx_Config XV_HdmiTx_ConfigTable[] = { - { - XPAR_V_HDMI_TX_SS_0_V_HDMI_TX_DEVICE_ID, - XPAR_V_HDMI_TX_SS_0_V_HDMI_TX_BASEADDR - } + { + XPAR_V_HDMI_TX_SS_0_V_HDMI_TX_DEVICE_ID, + XPAR_V_HDMI_TX_SS_0_V_HDMI_TX_BASEADDR, + XPAR_V_HDMI_TX_SS_0_V_HDMI_TX_S_AXI_FREQUENCY + } }; diff --git a/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_hw.h b/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_hw.h old mode 100755 new mode 100644 index 2e5ec09a..ea3e17b8 --- a/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_hw.h +++ b/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_hw.h @@ -51,8 +51,8 @@ * ******************************************************************************/ #ifndef XV_HDMITX_HW_H_ -#define XV_HDMITX_HW_H_ /**< Prevent circular inclusions - * by using protection macros */ +#define XV_HDMITX_HW_H_ /**< Prevent circular inclusions + * by using protection macros */ #ifdef __cplusplus extern "C" { @@ -66,202 +66,202 @@ extern "C" { /**< VER (Version Interface) peripheral register offsets */ /**< The VER is the first peripheral on the local bus */ -#define XV_HDMITX_VER_BASE (0*64) -#define XV_HDMITX_VER_ID_OFFSET ((XV_HDMITX_VER_BASE)+(0*4))/**< - * VER Identification * Register offset */ -#define XV_HDMITX_VER_VERSION_OFFSET ((XV_HDMITX_VER_BASE)+(1*4))/**< - * VER Version Register * offset */ +#define XV_HDMITX_VER_BASE (0*64) +#define XV_HDMITX_VER_ID_OFFSET ((XV_HDMITX_VER_BASE)+(0*4))/**< + * VER Identification * Register offset */ +#define XV_HDMITX_VER_VERSION_OFFSET ((XV_HDMITX_VER_BASE)+(1*4))/**< + * VER Version Register * offset */ /**< PIO (Parallel Interface) peripheral register offsets */ /**< The PIO is the first peripheral on the local bus */ -#define XV_HDMITX_PIO_BASE (1*64) -#define XV_HDMITX_PIO_ID_OFFSET ((XV_HDMITX_PIO_BASE)+(0*4))/**< PIO - * Identification * Register offset */ -#define XV_HDMITX_PIO_CTRL_OFFSET ((XV_HDMITX_PIO_BASE)+(1*4))/**< PIO - * Control Register * offset */ -#define XV_HDMITX_PIO_CTRL_SET_OFFSET ((XV_HDMITX_PIO_BASE)+(2*4))/**< PIO - * Control Register Set * offset */ -#define XV_HDMITX_PIO_CTRL_CLR_OFFSET ((XV_HDMITX_PIO_BASE)+(3*4))/**< PIO - * Control Register Clear * offset */ -#define XV_HDMITX_PIO_STA_OFFSET ((XV_HDMITX_PIO_BASE)+(4*4))/**< PIO - * Status Register * offset */ -#define XV_HDMITX_PIO_OUT_OFFSET ((XV_HDMITX_PIO_BASE)+(5*4))/**< PIO - * Out Register offset */ -#define XV_HDMITX_PIO_OUT_SET_OFFSET ((XV_HDMITX_PIO_BASE)+(6*4))/**< PIO - * Out Register Set * offset */ -#define XV_HDMITX_PIO_OUT_CLR_OFFSET ((XV_HDMITX_PIO_BASE)+(7*4))/**< PIO - * Out Register Clear * offset */ -#define XV_HDMITX_PIO_OUT_MSK_OFFSET ((XV_HDMITX_PIO_BASE)+(8*4))/**< PIO - * Out Mask Register * offset */ -#define XV_HDMITX_PIO_IN_OFFSET ((XV_HDMITX_PIO_BASE)+(9*4))/**< PIO - * In Register offset */ -#define XV_HDMITX_PIO_IN_EVT_OFFSET ((XV_HDMITX_PIO_BASE)+(10*4))/**< PIO - * In Event Register * offset */ -#define XV_HDMITX_PIO_IN_EVT_RE_OFFSET ((XV_HDMITX_PIO_BASE)+(11*4))/**< PIO - * In Event Rising Edge * Register offset */ -#define XV_HDMITX_PIO_IN_EVT_FE_OFFSET ((XV_HDMITX_PIO_BASE)+(12*4))/**< PIO - * In Event Falling Edge * Register offset */ +#define XV_HDMITX_PIO_BASE (1*64) +#define XV_HDMITX_PIO_ID_OFFSET ((XV_HDMITX_PIO_BASE)+(0*4))/**< PIO + * Identification * Register offset */ +#define XV_HDMITX_PIO_CTRL_OFFSET ((XV_HDMITX_PIO_BASE)+(1*4))/**< PIO + * Control Register * offset */ +#define XV_HDMITX_PIO_CTRL_SET_OFFSET ((XV_HDMITX_PIO_BASE)+(2*4))/**< PIO + * Control Register Set * offset */ +#define XV_HDMITX_PIO_CTRL_CLR_OFFSET ((XV_HDMITX_PIO_BASE)+(3*4))/**< PIO + * Control Register Clear * offset */ +#define XV_HDMITX_PIO_STA_OFFSET ((XV_HDMITX_PIO_BASE)+(4*4))/**< PIO + * Status Register * offset */ +#define XV_HDMITX_PIO_OUT_OFFSET ((XV_HDMITX_PIO_BASE)+(5*4))/**< PIO + * Out Register offset */ +#define XV_HDMITX_PIO_OUT_SET_OFFSET ((XV_HDMITX_PIO_BASE)+(6*4))/**< PIO + * Out Register Set * offset */ +#define XV_HDMITX_PIO_OUT_CLR_OFFSET ((XV_HDMITX_PIO_BASE)+(7*4))/**< PIO + * Out Register Clear * offset */ +#define XV_HDMITX_PIO_OUT_MSK_OFFSET ((XV_HDMITX_PIO_BASE)+(8*4))/**< PIO + * Out Mask Register * offset */ +#define XV_HDMITX_PIO_IN_OFFSET ((XV_HDMITX_PIO_BASE)+(9*4))/**< PIO + * In Register offset */ +#define XV_HDMITX_PIO_IN_EVT_OFFSET ((XV_HDMITX_PIO_BASE)+(10*4))/**< PIO + * In Event Register * offset */ +#define XV_HDMITX_PIO_IN_EVT_RE_OFFSET ((XV_HDMITX_PIO_BASE)+(11*4))/**< PIO + * In Event Rising Edge * Register offset */ +#define XV_HDMITX_PIO_IN_EVT_FE_OFFSET ((XV_HDMITX_PIO_BASE)+(12*4))/**< PIO + * In Event Falling Edge * Register offset */ // PIO peripheral Control register masks -#define XV_HDMITX_PIO_CTRL_RUN_MASK (1<<0) /**< PIO Control Run mask */ -#define XV_HDMITX_PIO_CTRL_IE_MASK (1<<1) /**< PIO Control Interrupt - * Enable mask */ +#define XV_HDMITX_PIO_CTRL_RUN_MASK (1<<0) /**< PIO Control Run mask */ +#define XV_HDMITX_PIO_CTRL_IE_MASK (1<<1) /**< PIO Control Interrupt + * Enable mask */ // PIO peripheral Status register masks -#define XV_HDMITX_PIO_STA_IRQ_MASK (1<<0) /**< PIO Status Interrupt mask */ -#define XV_HDMITX_PIO_STA_EVT_MASK (1<<1) /**< PIO Status Event mask */ +#define XV_HDMITX_PIO_STA_IRQ_MASK (1<<0) /**< PIO Status Interrupt mask */ +#define XV_HDMITX_PIO_STA_EVT_MASK (1<<1) /**< PIO Status Event mask */ // PIO peripheral PIO Out register masks and shifts -#define XV_HDMITX_PIO_OUT_RST_MASK (1<<0) /**< PIO Out Reset mask */ -#define XV_HDMITX_PIO_OUT_MODE_MASK (1<<3) /**< PIO Out Mode mask */ -#define XV_HDMITX_PIO_OUT_COLOR_DEPTH_MASK 0x30 /**< PIO Out Color Depth - * mask */ -#define XV_HDMITX_PIO_OUT_PIXEL_RATE_MASK 0xC0 /**< PIO Out Pixel Rate - * mask */ -#define XV_HDMITX_PIO_OUT_SAMPLE_RATE_MASK 0x300 /**< PIO Out Sample Rate - * mask */ -#define XV_HDMITX_PIO_OUT_COLOR_SPACE_MASK 0xC00 /**< PIO Out Color Space - * mask */ -#define XV_HDMITX_PIO_OUT_SCRM_MASK (1<<12) /**< PIO Out Scrambler - * mask */ -#define XV_HDMITX_PIO_OUT_COLOR_DEPTH_SHIFT 4 /**< PIO Out Color Depth - * shift */ -#define XV_HDMITX_PIO_OUT_PIXEL_RATE_SHIFT 6 /**< PIO Out Pixel Rate - * shift */ -#define XV_HDMITX_PIO_OUT_SAMPLE_RATE_SHIFT 8 /**< PIO Out Sample Rate - * shift */ -#define XV_HDMITX_PIO_OUT_COLOR_SPACE_SHIFT 10 /**< PIO Out Color Space - * shift */ +#define XV_HDMITX_PIO_OUT_RST_MASK (1<<0) /**< PIO Out Reset mask */ +#define XV_HDMITX_PIO_OUT_MODE_MASK (1<<3) /**< PIO Out Mode mask */ +#define XV_HDMITX_PIO_OUT_COLOR_DEPTH_MASK 0x30 /**< PIO Out Color Depth + * mask */ +#define XV_HDMITX_PIO_OUT_PIXEL_RATE_MASK 0xC0 /**< PIO Out Pixel Rate + * mask */ +#define XV_HDMITX_PIO_OUT_SAMPLE_RATE_MASK 0x300 /**< PIO Out Sample Rate + * mask */ +#define XV_HDMITX_PIO_OUT_COLOR_SPACE_MASK 0xC00 /**< PIO Out Color Space + * mask */ +#define XV_HDMITX_PIO_OUT_SCRM_MASK (1<<12) /**< PIO Out Scrambler + * mask */ +#define XV_HDMITX_PIO_OUT_COLOR_DEPTH_SHIFT 4 /**< PIO Out Color Depth + * shift */ +#define XV_HDMITX_PIO_OUT_PIXEL_RATE_SHIFT 6 /**< PIO Out Pixel Rate + * shift */ +#define XV_HDMITX_PIO_OUT_SAMPLE_RATE_SHIFT 8 /**< PIO Out Sample Rate + * shift */ +#define XV_HDMITX_PIO_OUT_COLOR_SPACE_SHIFT 10 /**< PIO Out Color Space + * shift */ // PIO peripheral PIO In register masks -#define XV_HDMITX_PIO_IN_LNK_RDY_MASK (1<<0) /**< PIO In link ready - * mask */ -#define XV_HDMITX_PIO_IN_VID_RDY_MASK (1<<1) /**< PIO In video ready - * mask */ -#define XV_HDMITX_PIO_IN_HPD_MASK (1<<2) /**< PIO In HPD mask */ -#define XV_HDMITX_PIO_IN_VS_MASK (1<<3) /**< PIO In Vsync mask */ -#define XV_HDMITX_PIO_IN_PPP_MASK 0x07 /**< PIO In Pixel packing - * phase mask */ -#define XV_HDMITX_PIO_IN_PPP_SHIFT 5 /**< PIO In Pixel packing - * phase shift */ +#define XV_HDMITX_PIO_IN_LNK_RDY_MASK (1<<0) /**< PIO In link ready + * mask */ +#define XV_HDMITX_PIO_IN_VID_RDY_MASK (1<<1) /**< PIO In video ready + * mask */ +#define XV_HDMITX_PIO_IN_HPD_MASK (1<<2) /**< PIO In HPD mask */ +#define XV_HDMITX_PIO_IN_VS_MASK (1<<3) /**< PIO In Vsync mask */ +#define XV_HDMITX_PIO_IN_PPP_MASK 0x07 /**< PIO In Pixel packing + * phase mask */ +#define XV_HDMITX_PIO_IN_PPP_SHIFT 5 /**< PIO In Pixel packing + * phase shift */ /**< DDC (Display Data Channel) peripheral register offsets */ /**< The DDC is the second peripheral on the local bus */ -#define XV_HDMITX_DDC_BASE (2*64) -#define XV_HDMITX_DDC_ID_OFFSET ((XV_HDMITX_DDC_BASE)+(0*4))/**< DDC - * Identification * Register offset */ -#define XV_HDMITX_DDC_CTRL_OFFSET ((XV_HDMITX_DDC_BASE)+(1*4))/**< DDC - * Control Register * offset */ -#define XV_HDMITX_DDC_CTRL_SET_OFFSET ((XV_HDMITX_DDC_BASE)+(2*4))/**< DDC - * Control Register Set * offset */ -#define XV_HDMITX_DDC_CTRL_CLR_OFFSET ((XV_HDMITX_DDC_BASE)+(3*4))/**< DDC - * Control Register Clear * offset */ -#define XV_HDMITX_DDC_STA_OFFSET ((XV_HDMITX_DDC_BASE)+(4*4))/**< DDC - * Status Register * offset */ -#define XV_HDMITX_DDC_CMD_OFFSET ((XV_HDMITX_DDC_BASE)+(5*4))/**< DDC - * Command Register * offset */ -#define XV_HDMITX_DDC_DAT_OFFSET ((XV_HDMITX_DDC_BASE)+(6*4))/**< DDC - * Data Register * offset */ +#define XV_HDMITX_DDC_BASE (2*64) +#define XV_HDMITX_DDC_ID_OFFSET ((XV_HDMITX_DDC_BASE)+(0*4))/**< DDC + * Identification * Register offset */ +#define XV_HDMITX_DDC_CTRL_OFFSET ((XV_HDMITX_DDC_BASE)+(1*4))/**< DDC + * Control Register * offset */ +#define XV_HDMITX_DDC_CTRL_SET_OFFSET ((XV_HDMITX_DDC_BASE)+(2*4))/**< DDC + * Control Register Set * offset */ +#define XV_HDMITX_DDC_CTRL_CLR_OFFSET ((XV_HDMITX_DDC_BASE)+(3*4))/**< DDC + * Control Register Clear * offset */ +#define XV_HDMITX_DDC_STA_OFFSET ((XV_HDMITX_DDC_BASE)+(4*4))/**< DDC + * Status Register * offset */ +#define XV_HDMITX_DDC_CMD_OFFSET ((XV_HDMITX_DDC_BASE)+(5*4))/**< DDC + * Command Register * offset */ +#define XV_HDMITX_DDC_DAT_OFFSET ((XV_HDMITX_DDC_BASE)+(6*4))/**< DDC + * Data Register * offset */ // DDC peripheral Control register masks and shift -#define XV_HDMITX_DDC_CTRL_RUN_MASK (1<<0) /**< DDC Control Run mask */ -#define XV_HDMITX_DDC_CTRL_IE_MASK (1<<1) /**< DDC Control Interrupt - * Enable mask */ -#define XV_HDMITX_DDC_CTRL_CLK_DIV_MASK 0xFFFF /**< DDC Control Clock - * Divider mask */ -#define XV_HDMITX_DDC_CTRL_CLK_DIV_SHIFT 16 /**< DDC Control Clock - *Divider shift */ /*@}*/ +#define XV_HDMITX_DDC_CTRL_RUN_MASK (1<<0) /**< DDC Control Run mask */ +#define XV_HDMITX_DDC_CTRL_IE_MASK (1<<1) /**< DDC Control Interrupt + * Enable mask */ +#define XV_HDMITX_DDC_CTRL_CLK_DIV_MASK 0xFFFF /**< DDC Control Clock + * Divider mask */ +#define XV_HDMITX_DDC_CTRL_CLK_DIV_SHIFT 16 /**< DDC Control Clock + *Divider shift */ /*@}*/ // DDC peripheral Status register masks -#define XV_HDMITX_DDC_STA_IRQ_MASK (1<<0) /**< DDC Status IRQ mask */ -#define XV_HDMITX_DDC_STA_EVT_MASK (1<<1) /**< DDC Status Event mask */ -#define XV_HDMITX_DDC_STA_BUSY_MASK (1<<2) /**< DDC Status Busy mask */ -#define XV_HDMITX_DDC_STA_DONE_MASK (1<<3) /**< DDC Status Busy mask */ -#define XV_HDMITX_DDC_STA_TIMEOUT_MASK (1<<4) /**< DDC Status Timeout mask */ -#define XV_HDMITX_DDC_STA_ACK_MASK (1<<5) /**< DDC Status ACK mask */ -#define XV_HDMITX_DDC_STA_SCL_MASK (1<<6) /**< DDC State of SCL Input - * mask */ -#define XV_HDMITX_DDC_STA_SDA_MASK (1<<7) /**< DDC State of SDA Input - * mask */ -#define XV_HDMITX_DDC_STA_CMD_FULL (1<<8) /**< Command fifo full */ -#define XV_HDMITX_DDC_STA_DAT_EMPTY (1<<9) /**< Data fifo empty */ -#define XV_HDMITX_DDC_STA_CMD_WRDS_MASK 0xFF /**< Command fifo words mask*/ -#define XV_HDMITX_DDC_STA_CMD_WRDS_SHIFT 16 /**< Command fifo words shift */ -#define XV_HDMITX_DDC_STA_DAT_WRDS_MASK 0xFF /**< Data fifo words mask */ -#define XV_HDMITX_DDC_STA_DAT_WRDS_SHIFT 24 /**< Data fifo words shift */ +#define XV_HDMITX_DDC_STA_IRQ_MASK (1<<0) /**< DDC Status IRQ mask */ +#define XV_HDMITX_DDC_STA_EVT_MASK (1<<1) /**< DDC Status Event mask */ +#define XV_HDMITX_DDC_STA_BUSY_MASK (1<<2) /**< DDC Status Busy mask */ +#define XV_HDMITX_DDC_STA_DONE_MASK (1<<3) /**< DDC Status Busy mask */ +#define XV_HDMITX_DDC_STA_TIMEOUT_MASK (1<<4) /**< DDC Status Timeout mask */ +#define XV_HDMITX_DDC_STA_ACK_MASK (1<<5) /**< DDC Status ACK mask */ +#define XV_HDMITX_DDC_STA_SCL_MASK (1<<6) /**< DDC State of SCL Input + * mask */ +#define XV_HDMITX_DDC_STA_SDA_MASK (1<<7) /**< DDC State of SDA Input + * mask */ +#define XV_HDMITX_DDC_STA_CMD_FULL (1<<8) /**< Command fifo full */ +#define XV_HDMITX_DDC_STA_DAT_EMPTY (1<<9) /**< Data fifo empty */ +#define XV_HDMITX_DDC_STA_CMD_WRDS_MASK 0xFF /**< Command fifo words mask*/ +#define XV_HDMITX_DDC_STA_CMD_WRDS_SHIFT 16 /**< Command fifo words shift */ +#define XV_HDMITX_DDC_STA_DAT_WRDS_MASK 0xFF /**< Data fifo words mask */ +#define XV_HDMITX_DDC_STA_DAT_WRDS_SHIFT 24 /**< Data fifo words shift */ // DDC peripheral token -#define XV_HDMITX_DDC_CMD_STR_TOKEN (0x100) /**< Start token */ -#define XV_HDMITX_DDC_CMD_STP_TOKEN (0x101) /**< Stop token */ -#define XV_HDMITX_DDC_CMD_RD_TOKEN (0x102) /**< Read token */ -#define XV_HDMITX_DDC_CMD_WR_TOKEN (0x103) /**< Write token */ +#define XV_HDMITX_DDC_CMD_STR_TOKEN (0x100) /**< Start token */ +#define XV_HDMITX_DDC_CMD_STP_TOKEN (0x101) /**< Stop token */ +#define XV_HDMITX_DDC_CMD_RD_TOKEN (0x102) /**< Read token */ +#define XV_HDMITX_DDC_CMD_WR_TOKEN (0x103) /**< Write token */ // Auxiliary (AUX) peripheral register offsets // The AUX is the third peripheral on the local bus -#define XV_HDMITX_AUX_BASE (3*64) -#define XV_HDMITX_AUX_ID_OFFSET ((XV_HDMITX_AUX_BASE)+(0*4)) /**< AUX - * Identification * Register offset */ -#define XV_HDMITX_AUX_CTRL_OFFSET ((XV_HDMITX_AUX_BASE)+(1*4)) /**< AUX - * Control Register * offset */ -#define XV_HDMITX_AUX_CTRL_SET_OFFSET ((XV_HDMITX_AUX_BASE)+(2*4)) /**< AUX - * Control Register Set * offset */ -#define XV_HDMITX_AUX_CTRL_CLR_OFFSET ((XV_HDMITX_AUX_BASE)+(3*4)) /**< AUX - * Control Register Clear * offset */ -#define XV_HDMITX_AUX_STA_OFFSET ((XV_HDMITX_AUX_BASE)+(4*4)) /**< AUX - * Status Register * offset */ -#define XV_HDMITX_AUX_DAT_OFFSET ((XV_HDMITX_AUX_BASE)+(5*4)) /**< AUX - * Data Register * offset */ +#define XV_HDMITX_AUX_BASE (3*64) +#define XV_HDMITX_AUX_ID_OFFSET ((XV_HDMITX_AUX_BASE)+(0*4)) /**< AUX + * Identification * Register offset */ +#define XV_HDMITX_AUX_CTRL_OFFSET ((XV_HDMITX_AUX_BASE)+(1*4)) /**< AUX + * Control Register * offset */ +#define XV_HDMITX_AUX_CTRL_SET_OFFSET ((XV_HDMITX_AUX_BASE)+(2*4)) /**< AUX + * Control Register Set * offset */ +#define XV_HDMITX_AUX_CTRL_CLR_OFFSET ((XV_HDMITX_AUX_BASE)+(3*4)) /**< AUX + * Control Register Clear * offset */ +#define XV_HDMITX_AUX_STA_OFFSET ((XV_HDMITX_AUX_BASE)+(4*4)) /**< AUX + * Status Register * offset */ +#define XV_HDMITX_AUX_DAT_OFFSET ((XV_HDMITX_AUX_BASE)+(5*4)) /**< AUX + * Data Register * offset */ // Auxiliary peripheral Control register masks -#define XV_HDMITX_AUX_CTRL_RUN_MASK (1<<0) /**< AUX Control Run mask */ -#define XV_HDMITX_AUX_CTRL_IE_MASK (1<<1) /**< AUX Control Interrupt - * Enable mask */ +#define XV_HDMITX_AUX_CTRL_RUN_MASK (1<<0) /**< AUX Control Run mask */ +#define XV_HDMITX_AUX_CTRL_IE_MASK (1<<1) /**< AUX Control Interrupt + * Enable mask */ // Auxiliary peripheral Status register masks and shift -#define XV_HDMITX_AUX_STA_IRQ_MASK (1<<0) /**< AUX Status Interrupt - * mask */ -#define XV_HDMITX_AUX_STA_FIFO_EMT_MASK (1<<1) /**< AUX Status FIFO Empty - * mask */ -#define XV_HDMITX_AUX_STA_FIFO_FUL_MASK (1<<2) /**< AUX Status FIFO Full - * mask */ -#define XV_HDMITX_AUX_STA_FREE_PKTS_MASK 0x0F /**< AUX Status Free Packets - * mask */ -#define XV_HDMITX_AUX_STA_FREE_PKTS_SHIFT 15 /**< AUX Status Free - * Packets shift */ +#define XV_HDMITX_AUX_STA_IRQ_MASK (1<<0) /**< AUX Status Interrupt + * mask */ +#define XV_HDMITX_AUX_STA_FIFO_EMT_MASK (1<<1) /**< AUX Status FIFO Empty + * mask */ +#define XV_HDMITX_AUX_STA_FIFO_FUL_MASK (1<<2) /**< AUX Status FIFO Full + * mask */ +#define XV_HDMITX_AUX_STA_FREE_PKTS_MASK 0x0F /**< AUX Status Free Packets + * mask */ +#define XV_HDMITX_AUX_STA_FREE_PKTS_SHIFT 15 /**< AUX Status Free + * Packets shift */ // Audio (AUD) peripheral register offsets // The AUD is the forth peripheral on the local bus -#define XV_HDMITX_AUD_BASE (4*64) -#define XV_HDMITX_AUD_ID_OFFSET ((XV_HDMITX_AUD_BASE)+(0*4)) /**< AUD - * Identification * Register offset */ -#define XV_HDMITX_AUD_CTRL_OFFSET ((XV_HDMITX_AUD_BASE)+(1*4)) /**< AUD - * Control Register * offset */ -#define XV_HDMITX_AUD_CTRL_SET_OFFSET ((XV_HDMITX_AUD_BASE)+(2*4)) /**< AUD - * Control Register Set * offset */ -#define XV_HDMITX_AUD_CTRL_CLR_OFFSET ((XV_HDMITX_AUD_BASE)+(3*4)) /**< AUD - * Control Register Clear * offset */ -#define XV_HDMITX_AUD_STA_OFFSET ((XV_HDMITX_AUD_BASE)+(4*4)) /**< AUD - * Status Register * offset */ -#define XV_HDMITX_AUD_ACR_CTS_OFFSET ((XV_HDMITX_AUD_BASE)+(5*4)) /**< AUD - * Clock Regeneration CTS * Register offset */ -#define XV_HDMITX_AUD_ACR_N_OFFSET ((XV_HDMITX_AUD_BASE)+(6*4)) /**< AUD - * Clock Regeneration N * Register offset */ +#define XV_HDMITX_AUD_BASE (4*64) +#define XV_HDMITX_AUD_ID_OFFSET ((XV_HDMITX_AUD_BASE)+(0*4)) /**< AUD + * Identification * Register offset */ +#define XV_HDMITX_AUD_CTRL_OFFSET ((XV_HDMITX_AUD_BASE)+(1*4)) /**< AUD + * Control Register * offset */ +#define XV_HDMITX_AUD_CTRL_SET_OFFSET ((XV_HDMITX_AUD_BASE)+(2*4)) /**< AUD + * Control Register Set * offset */ +#define XV_HDMITX_AUD_CTRL_CLR_OFFSET ((XV_HDMITX_AUD_BASE)+(3*4)) /**< AUD + * Control Register Clear * offset */ +#define XV_HDMITX_AUD_STA_OFFSET ((XV_HDMITX_AUD_BASE)+(4*4)) /**< AUD + * Status Register * offset */ +#define XV_HDMITX_AUD_ACR_CTS_OFFSET ((XV_HDMITX_AUD_BASE)+(5*4)) /**< AUD + * Clock Regeneration CTS * Register offset */ +#define XV_HDMITX_AUD_ACR_N_OFFSET ((XV_HDMITX_AUD_BASE)+(6*4)) /**< AUD + * Clock Regeneration N * Register offset */ // Audio peripheral Control register masks -#define XV_HDMITX_AUD_CTRL_RUN_MASK (1<<0) /**< AUD Control Run mask */ -#define XV_HDMITX_AUD_CTRL_IE_MASK (1<<1) /**< AUD Control Interrupt - * Enable mask */ -#define XV_HDMITX_AUD_CTRL_CH_MASK 0x03 /**< AUD Control channels mask */ -#define XV_HDMITX_AUD_CTRL_CH_SHIFT 2 /**< AUD Control channels mask */ +#define XV_HDMITX_AUD_CTRL_RUN_MASK (1<<0) /**< AUD Control Run mask */ +#define XV_HDMITX_AUD_CTRL_IE_MASK (1<<1) /**< AUD Control Interrupt + * Enable mask */ +#define XV_HDMITX_AUD_CTRL_CH_MASK 0x03 /**< AUD Control channels mask */ +#define XV_HDMITX_AUD_CTRL_CH_SHIFT 2 /**< AUD Control channels mask */ // Audio peripheral Status register masks -#define XV_HDMITX_AUD_STA_IRQ_MASK (1<<0) /**< AUD Status Interrupt mask */ +#define XV_HDMITX_AUD_STA_IRQ_MASK (1<<0) /**< AUD Status Interrupt mask */ // Peripheral ID and General shift values. -#define XV_HDMITX_SHIFT_16 16 /**< 16 shift value */ -#define XV_HDMITX_MASK_16 0xFFFF /**< 16 bit mask value */ -#define XV_HDMITX_PIO_ID 0x2200 /**< TX's PIO ID */ +#define XV_HDMITX_SHIFT_16 16 /**< 16 shift value */ +#define XV_HDMITX_MASK_16 0xFFFF /**< 16 bit mask value */ +#define XV_HDMITX_PIO_ID 0x2200 /**< TX's PIO ID */ /**************************** Type Definitions *******************************/ @@ -269,8 +269,8 @@ extern "C" { /***************** Macros (Inline Functions) Definitions *********************/ // Register access macro definition -#define XV_HdmiTx_In32 Xil_In32 /**< Input Operations */ -#define XV_HdmiTx_Out32 Xil_Out32 /**< Output Operations */ +#define XV_HdmiTx_In32 Xil_In32 /**< Input Operations */ +#define XV_HdmiTx_Out32 Xil_Out32 /**< Output Operations */ /*****************************************************************************/ /** @@ -280,18 +280,18 @@ extern "C" { * significant data is read from the register. The most significant data * will be read as 0. * -* @param BaseAddress is the base address of the HDMI TX core instance. -* @param RegOffset is the register offset of the register (defined at -* the top of this file). +* @param BaseAddress is the base address of the HDMI TX core instance. +* @param RegOffset is the register offset of the register (defined at +* the top of this file). * -* @return The 32-bit value of the register. +* @return The 32-bit value of the register. * -* @note C-style signature: -* u32 XV_HdmiTx_ReadReg(u32 BaseAddress, u32 RegOffset) +* @note C-style signature: +* u32 XV_HdmiTx_ReadReg(u32 BaseAddress, u32 RegOffset) * ******************************************************************************/ #define XV_HdmiTx_ReadReg(BaseAddress, RegOffset) \ - XV_HdmiTx_In32((BaseAddress) + ((u32)RegOffset)) + XV_HdmiTx_In32((BaseAddress) + ((u32)RegOffset)) /*****************************************************************************/ /** @@ -300,19 +300,19 @@ extern "C" { * If the component is implemented in a smaller width, only the least * significant data is written. * -* @param BaseAddress is the base address of the HDMI TX core instance. -* @param RegOffset is the register offset of the register (defined at -* the top of this file) to be written. -* @param Data is the 32-bit value to write into the register. +* @param BaseAddress is the base address of the HDMI TX core instance. +* @param RegOffset is the register offset of the register (defined at +* the top of this file) to be written. +* @param Data is the 32-bit value to write into the register. * -* @return None. +* @return None. * -* @note C-style signature: -* void XV_HdmiTx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* @note C-style signature: +* void XV_HdmiTx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) * ******************************************************************************/ #define XV_HdmiTx_WriteReg(BaseAddress, RegOffset, Data) \ - XV_HdmiTx_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data)) + XV_HdmiTx_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data)) /*@}*/ /************************** Function Prototypes ******************************/ @@ -325,4 +325,4 @@ extern "C" { } #endif -#endif /* end of protection macro */ \ No newline at end of file +#endif /* end of protection macro */ diff --git a/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_intr.c b/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_intr.c old mode 100755 new mode 100644 index 1ff671a2..de93a23d --- a/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_intr.c +++ b/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_intr.c @@ -86,44 +86,44 @@ static void HdmiTx_DdcIntrHandler(XV_HdmiTx *InstancePtr); * XV_HdmiTx_SetCallback() during initialization phase. An example delivered * with this driver demonstrates how this could be done. * -* @param InstancePtr is a pointer to the XV_HdmiTx instance that just -* interrupted. +* @param InstancePtr is a pointer to the XV_HdmiTx instance that just +* interrupted. * -* @return None. +* @return None. * -* @note None. +* @note None. * ******************************************************************************/ void XV_HdmiTx_IntrHandler(void *InstancePtr) { - u32 Data; - XV_HdmiTx *HdmiTxPtr = (XV_HdmiTx *)InstancePtr; + u32 Data; + XV_HdmiTx *HdmiTxPtr = (XV_HdmiTx *)InstancePtr; - /* Verify arguments */ - Xil_AssertVoid(HdmiTxPtr != NULL); - Xil_AssertVoid(HdmiTxPtr->IsReady == XIL_COMPONENT_IS_READY); + /* Verify arguments */ + Xil_AssertVoid(HdmiTxPtr != NULL); + Xil_AssertVoid(HdmiTxPtr->IsReady == XIL_COMPONENT_IS_READY); - /* PIO */ - Data = XV_HdmiTx_ReadReg(HdmiTxPtr->Config.BaseAddress, - (XV_HDMITX_PIO_STA_OFFSET)) & - (XV_HDMITX_PIO_STA_IRQ_MASK); + /* PIO */ + Data = XV_HdmiTx_ReadReg(HdmiTxPtr->Config.BaseAddress, + (XV_HDMITX_PIO_STA_OFFSET)) & + (XV_HDMITX_PIO_STA_IRQ_MASK); - /* Check for IRQ flag set */ - if (Data) { - /* Jump to PIO handler */ - HdmiTx_PioIntrHandler(HdmiTxPtr); - } + /* Check for IRQ flag set */ + if (Data) { + /* Jump to PIO handler */ + HdmiTx_PioIntrHandler(HdmiTxPtr); + } - /* DDC */ - Data = XV_HdmiTx_ReadReg(HdmiTxPtr->Config.BaseAddress, - (XV_HDMITX_DDC_STA_OFFSET)) & - (XV_HDMITX_DDC_STA_IRQ_MASK); + /* DDC */ + Data = XV_HdmiTx_ReadReg(HdmiTxPtr->Config.BaseAddress, + (XV_HDMITX_DDC_STA_OFFSET)) & + (XV_HDMITX_DDC_STA_IRQ_MASK); - /* Check for IRQ flag set */ - if (Data) { - /* Jump to DDC handler */ - HdmiTx_DdcIntrHandler(HdmiTxPtr); - } + /* Check for IRQ flag set */ + if (Data) { + /* Jump to DDC handler */ + HdmiTx_DdcIntrHandler(HdmiTxPtr); + } } /*****************************************************************************/ @@ -139,71 +139,71 @@ void XV_HdmiTx_IntrHandler(void *InstancePtr) * (XV_HDMITX_HANDLER_VS) VsCallback * * -* @param InstancePtr is a pointer to the HDMI TX core instance. -* @param HandlerType specifies the type of handler. -* @param CallbackFunc is the address of the callback function. -* @param CallbackRef is a user data item that will be passed to the -* callback function when it is invoked. +* @param InstancePtr is a pointer to the HDMI TX core instance. +* @param HandlerType specifies the type of handler. +* @param CallbackFunc is the address of the callback function. +* @param CallbackRef is a user data item that will be passed to the +* callback function when it is invoked. * * @return -* - XST_SUCCESS if callback function installed successfully. -* - XST_INVALID_PARAM when HandlerType is invalid. +* - XST_SUCCESS if callback function installed successfully. +* - XST_INVALID_PARAM when HandlerType is invalid. * -* @note Invoking this function for a handler that already has been -* installed replaces it with the new handler. +* @note Invoking this function for a handler that already has been +* installed replaces it with the new handler. * ******************************************************************************/ int XV_HdmiTx_SetCallback(XV_HdmiTx *InstancePtr, - u32 HandlerType, - void *CallbackFunc, - void *CallbackRef) + u32 HandlerType, + void *CallbackFunc, + void *CallbackRef) { - u32 Status; + u32 Status; - /* Verify arguments. */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(HandlerType >= (XV_HDMITX_HANDLER_CONNECT)); - Xil_AssertNonvoid(CallbackFunc != NULL); - Xil_AssertNonvoid(CallbackRef != NULL); + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(HandlerType >= (XV_HDMITX_HANDLER_CONNECT)); + Xil_AssertNonvoid(CallbackFunc != NULL); + Xil_AssertNonvoid(CallbackRef != NULL); - /* Check for handler type */ - switch (HandlerType) { - case (XV_HDMITX_HANDLER_CONNECT): - InstancePtr->ConnectCallback = (XV_HdmiTx_Callback)CallbackFunc; - InstancePtr->ConnectRef = CallbackRef; - InstancePtr->IsConnectCallbackSet = (TRUE); - Status = (XST_SUCCESS); - break; + /* Check for handler type */ + switch (HandlerType) { + case (XV_HDMITX_HANDLER_CONNECT): + InstancePtr->ConnectCallback = (XV_HdmiTx_Callback)CallbackFunc; + InstancePtr->ConnectRef = CallbackRef; + InstancePtr->IsConnectCallbackSet = (TRUE); + Status = (XST_SUCCESS); + break; - case (XV_HDMITX_HANDLER_VS): - InstancePtr->VsCallback = (XV_HdmiTx_Callback)CallbackFunc; - InstancePtr->VsRef = CallbackRef; - InstancePtr->IsVsCallbackSet = (TRUE); - Status = (XST_SUCCESS); - break; + case (XV_HDMITX_HANDLER_VS): + InstancePtr->VsCallback = (XV_HdmiTx_Callback)CallbackFunc; + InstancePtr->VsRef = CallbackRef; + InstancePtr->IsVsCallbackSet = (TRUE); + Status = (XST_SUCCESS); + break; - // Stream down - case (XV_HDMITX_HANDLER_STREAM_DOWN): - InstancePtr->StreamDownCallback = (XV_HdmiTx_Callback)CallbackFunc; - InstancePtr->StreamDownRef = CallbackRef; - InstancePtr->IsStreamDownCallbackSet = (TRUE); - Status = (XST_SUCCESS); - break; + // Stream down + case (XV_HDMITX_HANDLER_STREAM_DOWN): + InstancePtr->StreamDownCallback = (XV_HdmiTx_Callback)CallbackFunc; + InstancePtr->StreamDownRef = CallbackRef; + InstancePtr->IsStreamDownCallbackSet = (TRUE); + Status = (XST_SUCCESS); + break; - // Stream up - case (XV_HDMITX_HANDLER_STREAM_UP): - InstancePtr->StreamUpCallback = (XV_HdmiTx_Callback)CallbackFunc; - InstancePtr->StreamUpRef = CallbackRef; - InstancePtr->IsStreamUpCallbackSet = (TRUE); - Status = (XST_SUCCESS); - break; + // Stream up + case (XV_HDMITX_HANDLER_STREAM_UP): + InstancePtr->StreamUpCallback = (XV_HdmiTx_Callback)CallbackFunc; + InstancePtr->StreamUpRef = CallbackRef; + InstancePtr->IsStreamUpCallbackSet = (TRUE); + Status = (XST_SUCCESS); + break; - default: - Status = (XST_INVALID_PARAM); - break; - } + default: + Status = (XST_INVALID_PARAM); + break; + } - return Status; + return Status; } /*****************************************************************************/ @@ -215,95 +215,95 @@ int XV_HdmiTx_SetCallback(XV_HdmiTx *InstancePtr, * register. It determines the source of the interrupts and calls according * callbacks. * -* @param InstancePtr is a pointer to the HDMI TX core instance. +* @param InstancePtr is a pointer to the HDMI TX core instance. * -* @return None. +* @return None. * -* @note None. +* @note None. * ******************************************************************************/ static void HdmiTx_PioIntrHandler(XV_HdmiTx *InstancePtr) { - u32 Event; - u32 Data; + u32 Event; + u32 Data; - /* Read PIO IN Event register.*/ - Event = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_PIO_IN_EVT_OFFSET)); + /* Read PIO IN Event register.*/ + Event = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_PIO_IN_EVT_OFFSET)); - /* Clear event flags */ - XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_PIO_IN_EVT_OFFSET), - (Event)); + /* Clear event flags */ + XV_HdmiTx_WriteReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_PIO_IN_EVT_OFFSET), + (Event)); - /* Read data */ - Data = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_PIO_IN_OFFSET)); + /* Read data */ + Data = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_PIO_IN_OFFSET)); - /* HPD event has occurred */ - if ((Event) & (XV_HDMITX_PIO_IN_HPD_MASK)) { + /* HPD event has occurred */ + if ((Event) & (XV_HDMITX_PIO_IN_HPD_MASK)) { - // Check the HPD status - if ((Data) & (XV_HDMITX_PIO_IN_HPD_MASK)) - InstancePtr->Stream.IsConnected = (TRUE); // Set connected flag - else - InstancePtr->Stream.IsConnected = (FALSE); // Clear connected flag + // Check the HPD status + if ((Data) & (XV_HDMITX_PIO_IN_HPD_MASK)) + InstancePtr->Stream.IsConnected = (TRUE); // Set connected flag + else + InstancePtr->Stream.IsConnected = (FALSE); // Clear connected flag - // Check if user callback has been registered - if (InstancePtr->IsConnectCallbackSet) { - InstancePtr->ConnectCallback(InstancePtr->ConnectRef); - } - } + // Check if user callback has been registered + if (InstancePtr->IsConnectCallbackSet) { + InstancePtr->ConnectCallback(InstancePtr->ConnectRef); + } + } - /* Vsync event has occurred */ - if ((Event) & (XV_HDMITX_PIO_IN_VS_MASK)) { + /* Vsync event has occurred */ + if ((Event) & (XV_HDMITX_PIO_IN_VS_MASK)) { - // Check if user callback has been registered - if (InstancePtr->IsVsCallbackSet) { - InstancePtr->VsCallback(InstancePtr->VsRef); - } - } + // Check if user callback has been registered + if (InstancePtr->IsVsCallbackSet) { + InstancePtr->VsCallback(InstancePtr->VsRef); + } + } - /* Link ready event has occurred */ - if ((Event) & (XV_HDMITX_PIO_IN_LNK_RDY_MASK)) { + /* Link ready event has occurred */ + if ((Event) & (XV_HDMITX_PIO_IN_LNK_RDY_MASK)) { - // Check the link status - if ((Data) & (XV_HDMITX_PIO_IN_LNK_RDY_MASK)) { - // Set stream status to up - InstancePtr->Stream.State = XV_HDMITX_STATE_STREAM_UP; + // Check the link status + if ((Data) & (XV_HDMITX_PIO_IN_LNK_RDY_MASK)) { + // Set stream status to up + InstancePtr->Stream.State = XV_HDMITX_STATE_STREAM_UP; - /* Enable the AUX peripheral */ - XV_HdmiTx_AuxEnable(InstancePtr); + /* Enable the AUX peripheral */ + XV_HdmiTx_AuxEnable(InstancePtr); - /* Enable the AUX peripheral interrupt */ - XV_HdmiTx_AuxIntrEnable(InstancePtr); + /* Enable the AUX peripheral interrupt */ + XV_HdmiTx_AuxIntrEnable(InstancePtr); - /* Enable audio */ - //XV_HdmiTx_AudioEnable(InstancePtr); + /* Enable audio */ + //XV_HdmiTx_AudioEnable(InstancePtr); - // Check if user callback has been registered - if (InstancePtr->IsStreamUpCallbackSet) { - InstancePtr->StreamUpCallback(InstancePtr->StreamUpRef); - } - } + // Check if user callback has been registered + if (InstancePtr->IsStreamUpCallbackSet) { + InstancePtr->StreamUpCallback(InstancePtr->StreamUpRef); + } + } - // Link down - else { - // Set stream status to down - InstancePtr->Stream.State = XV_HDMITX_STATE_STREAM_DOWN; + // Link down + else { + // Set stream status to down + InstancePtr->Stream.State = XV_HDMITX_STATE_STREAM_DOWN; - /* Disable Audio */ - XV_HdmiTx_AudioDisable(InstancePtr); + /* Disable Audio */ + XV_HdmiTx_AudioDisable(InstancePtr); - /* Disable AUX */ - XV_HdmiTx_AuxDisable(InstancePtr); + /* Disable AUX */ + XV_HdmiTx_AuxDisable(InstancePtr); - // Check if user callback has been registered - if (InstancePtr->IsStreamDownCallbackSet) { - InstancePtr->StreamDownCallback(InstancePtr->StreamDownRef); - } - } - } + // Check if user callback has been registered + if (InstancePtr->IsStreamDownCallbackSet) { + InstancePtr->StreamDownCallback(InstancePtr->StreamDownRef); + } + } + } } /*****************************************************************************/ @@ -315,18 +315,18 @@ static void HdmiTx_PioIntrHandler(XV_HdmiTx *InstancePtr) * determines the state and based on that performs required operation. * * -* @param InstancePtr is a pointer to the HDMI TX core instance. +* @param InstancePtr is a pointer to the HDMI TX core instance. * -* @return None. +* @return None. * -* @note None. +* @note None. * ******************************************************************************/ static void HdmiTx_DdcIntrHandler(XV_HdmiTx *InstancePtr) { - u32 Data; + u32 Data; - /* Read DDC Status register */ - Data = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_DDC_STA_OFFSET)); + /* Read DDC Status register */ + Data = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_DDC_STA_OFFSET)); } diff --git a/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_selftest.c b/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_selftest.c old mode 100755 new mode 100644 index fa56c559..4c6b1124 --- a/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_selftest.c +++ b/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_selftest.c @@ -73,32 +73,32 @@ * * This function reads ID of HDMI TX PIO peripheral. * -* @param InstancePtr is a pointer to the XV_HdmiTx core instance. +* @param InstancePtr is a pointer to the XV_HdmiTx core instance. * * @return -* - XST_SUCCESS if PIO ID was matched. -* - XST_FAILURE if PIO ID was mismatched. +* - XST_SUCCESS if PIO ID was matched. +* - XST_FAILURE if PIO ID was mismatched. * -* @note None. +* @note None. * ******************************************************************************/ int XV_HdmiTx_SelfTest(XV_HdmiTx *InstancePtr) { - u32 RegValue; - u32 Status = (XST_SUCCESS); + u32 RegValue; + u32 Status = (XST_SUCCESS); - /* Verify argument. */ - Xil_AssertNonvoid(InstancePtr != NULL); + /* Verify argument. */ + Xil_AssertNonvoid(InstancePtr != NULL); - /* Read PIO peripheral Identification register */ - RegValue = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, - (XV_HDMITX_PIO_ID_OFFSET)); + /* Read PIO peripheral Identification register */ + RegValue = XV_HdmiTx_ReadReg(InstancePtr->Config.BaseAddress, + (XV_HDMITX_PIO_ID_OFFSET)); - RegValue = ((RegValue) >> (XV_HDMITX_SHIFT_16)) & (XV_HDMITX_MASK_16); + RegValue = ((RegValue) >> (XV_HDMITX_SHIFT_16)) & (XV_HDMITX_MASK_16); - if (RegValue != (XV_HDMITX_PIO_ID)) { - Status = (XST_FAILURE); - } + if (RegValue != (XV_HDMITX_PIO_ID)) { + Status = (XST_FAILURE); + } - return Status; + return Status; } diff --git a/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_sinit.c b/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_sinit.c old mode 100755 new mode 100644 index 781ce950..d4f20899 --- a/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_sinit.c +++ b/XilinxProcessorIPLib/drivers/v_hdmitx/src/xv_hdmitx_sinit.c @@ -76,35 +76,35 @@ * on the core id, DeviceId. The return value will refer to an entry in * the device configuration table defined in the xv_hdmitx_g.c file. * -* @param DeviceId is the unique core ID of the HDMI TX core for the -* lookup operation. +* @param DeviceId is the unique core ID of the HDMI TX core for the +* lookup operation. * -* @return XV_HdmiTx_LookupConfig returns a reference to a config record -* in the configuration table (in xv_hdmitx_g.c) corresponding -* to DeviceId, or NULL if no match is found. +* @return XV_HdmiTx_LookupConfig returns a reference to a config record +* in the configuration table (in xv_hdmitx_g.c) corresponding +* to DeviceId, or NULL if no match is found. * -* @note None. +* @note None. * ******************************************************************************/ XV_HdmiTx_Config *XV_HdmiTx_LookupConfig(u16 DeviceId) { - extern XV_HdmiTx_Config - XV_HdmiTx_ConfigTable[XPAR_XV_HDMITX_NUM_INSTANCES]; - XV_HdmiTx_Config *CfgPtr = NULL; - u32 Index; + extern XV_HdmiTx_Config + XV_HdmiTx_ConfigTable[XPAR_XV_HDMITX_NUM_INSTANCES]; + XV_HdmiTx_Config *CfgPtr = NULL; + u32 Index; - /* Checking for device id for which instance it is matching */ - for (Index = (u32)0x0; Index < (u32)(XPAR_XV_HDMITX_NUM_INSTANCES); - Index++) { + /* Checking for device id for which instance it is matching */ + for (Index = (u32)0x0; Index < (u32)(XPAR_XV_HDMITX_NUM_INSTANCES); + Index++) { - /* Assigning address of config table if both device ids - * are matched - */ - if (XV_HdmiTx_ConfigTable[Index].DeviceId == DeviceId) { - CfgPtr = &XV_HdmiTx_ConfigTable[Index]; - break; - } - } + /* Assigning address of config table if both device ids + * are matched + */ + if (XV_HdmiTx_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XV_HdmiTx_ConfigTable[Index]; + break; + } + } - return (XV_HdmiTx_Config *)CfgPtr; -} \ No newline at end of file + return (XV_HdmiTx_Config *)CfgPtr; +}