diff --git a/lib/sw_services/xilskey/src/include/xilskey_eps.h b/lib/sw_services/xilskey/src/include/xilskey_eps.h
index 1fef9ae3..bd090d0f 100644
--- a/lib/sw_services/xilskey/src/include/xilskey_eps.h
+++ b/lib/sw_services/xilskey/src/include/xilskey_eps.h
@@ -81,6 +81,14 @@ typedef struct {
 	 * Enable the ROM code 128K crc  eFUSE Bit
 	 */
 	u32 EnableRom128Crc;
+		/**
+	 * Disable DFT JTAG
+	 */
+	u32 DisableDftJtag;
+	/**
+	 * Disable DFT Mode
+	 */
+	u32 DisableDftMode;
 	/**
 	 * EnableRsaKeyHash: Enabling this RsaKeyHashValue[32] is written to
 	 * eFUSE array
diff --git a/lib/sw_services/xilskey/src/include/xilskey_utils.h b/lib/sw_services/xilskey/src/include/xilskey_utils.h
index 09905aeb..da4ca0fd 100644
--- a/lib/sw_services/xilskey/src/include/xilskey_utils.h
+++ b/lib/sw_services/xilskey/src/include/xilskey_utils.h
@@ -495,6 +495,9 @@ typedef enum {
 	XSK_EFUSEPS_ERROR_WRITE_WRITE_PROTECT_BIT=0x9600,
 	XSK_EFUSEPS_ERROR_READ_HASH_BEFORE_PROGRAMMING=0x9700,
 
+	XSK_EFUSEPS_ERROR_WRTIE_DFT_JTAG_DIS_BIT = 0x9800,
+	XSK_EFUSEPS_ERROR_WRTIE_DFT_MODE_DIS_BIT = 0x9900,
+
 	/**
 	 * XSKEfusePs_Read() error codes
 	 */
diff --git a/lib/sw_services/xilskey/src/xilskey_eps.c b/lib/sw_services/xilskey/src/xilskey_eps.c
index 571464fe..ab93e291 100644
--- a/lib/sw_services/xilskey/src/xilskey_eps.c
+++ b/lib/sw_services/xilskey/src/xilskey_eps.c
@@ -46,6 +46,8 @@
 * 2.00  hk      23/01/14 Changed PS efuse error codes for voltage out of range.
 * 2.1   sk      04/03/15 Initialized RSAKeyReadback with Zeros CR# 829723.
 * 3.00  vns     31/07/15 Removed redundant code to initialise timer.
+* 4.00  vns     09/10/15 Added DFT control bits programming fecility for
+*                        eFuse PS on Zynq. PR#862778
 *
 *****************************************************************************/
 
@@ -117,7 +119,11 @@ u32 XilSKey_EfusePs_Write(XilSKey_EPs *InstancePtr)
 		((InstancePtr->EnableRom128Crc != TRUE) &&
 		 (InstancePtr->EnableRom128Crc != FALSE)) ||
 		((InstancePtr->EnableRsaKeyHash != TRUE) &&
-		 (InstancePtr->EnableRsaKeyHash != FALSE)) ) {
+		 (InstancePtr->EnableRsaKeyHash != FALSE)) ||
+		((InstancePtr->DisableDftJtag != TRUE) &&
+		 (InstancePtr->DisableDftJtag != FALSE)) ||
+		((InstancePtr->DisableDftMode != TRUE) &&
+		 (InstancePtr->DisableDftMode != FALSE))) {
 		return XSK_EFUSEPS_ERROR_PS_PARAMETER_WRONG;
 	}
 
@@ -265,6 +271,26 @@ u32 XilSKey_EfusePs_Write(XilSKey_EPs *InstancePtr)
 		}
 	}
 
+	/* Programs 0xC eFuse bit to disable DFT JTAG */
+	if (InstancePtr->DisableDftJtag) {
+		Status = XilSKey_EfusePs_WriteWithXadcCheckAndVerify(
+				XSK_EFUSEPS_APB_DFT_JTAG_DISABLE, RefClk);
+		if (Status != XST_SUCCESS) {
+			RetValue = XSK_EFUSEPS_ERROR_WRTIE_DFT_JTAG_DIS_BIT + Status;
+			goto ExitCtrlResetStatus;
+		}
+	}
+
+	/* Programs 0xD eFuse bit to disable DFT Mode */
+	if (InstancePtr->DisableDftMode) {
+		Status = XilSKey_EfusePs_WriteWithXadcCheckAndVerify(
+				XSK_EFUSEPS_APB_DFT_MODE_DISABLE, RefClk);
+		if (Status != XST_SUCCESS) {
+			RetValue = XSK_EFUSEPS_ERROR_WRTIE_DFT_MODE_DIS_BIT + Status;
+			goto ExitCtrlResetStatus;
+		}
+	}
+
 ExitCtrlResetStatus:
 	/**
 	 * Disable Programming, write and read
diff --git a/lib/sw_services/xilskey/src/xilskey_epshw.h b/lib/sw_services/xilskey/src/xilskey_epshw.h
index a5df56bd..b681daf5 100644
--- a/lib/sw_services/xilskey/src/xilskey_epshw.h
+++ b/lib/sw_services/xilskey/src/xilskey_epshw.h
@@ -42,6 +42,7 @@
 * Ver   Who  	Date     Changes
 * ----- ---- 	-------- --------------------------------------------------------
 * 1.00a rpoolla 04/26/13 First release
+* 4.00  vns     09/10/15 Added DFT control bits addresses
  *
  *****************************************************************************/
 
@@ -262,6 +263,14 @@ extern "C" {
  * eFUSE APB address for RSA authentication enable offset
  */
 #define XSK_EFUSEPS_APB_RSA_AUTH_ENABLE_OFFSET 			(0x2C)
+/**
+ * eFUSE DFT JTAG disable
+ */
+#define XSK_EFUSEPS_APB_DFT_JTAG_DISABLE_OFFSET 			(0x30)
+/**
+ * eFUSE DFT mode disable
+ */
+#define XSK_EFUSEPS_APB_DFT_MODE_DISABLE_OFFSET 			(0x34)
 /**
  * eFUSE APB address for RSA uart status enable on MIO48 offset
  */
@@ -365,6 +374,10 @@ extern "C" {
  * eFUSE APB address for RSA authentication enable
  */
 #define XSK_EFUSEPS_APB_RSA_AUTH_ENABLE 			(XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_RSA_AUTH_ENABLE_OFFSET)
+/* eFuse DFT JTAG disable */
+#define XSK_EFUSEPS_APB_DFT_JTAG_DISABLE				(XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_DFT_JTAG_DISABLE_OFFSET)
+/* eFuse DFT mode disable */
+#define XSK_EFUSEPS_APB_DFT_MODE_DISABLE				(XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_DFT_MODE_DISABLE_OFFSET)
 /*
  * eFUSE APB address for RSA uart status enable on MIO48
  */