diff --git a/XilinxProcessorIPLib/drivers/dptx/data/dependencies.props b/XilinxProcessorIPLib/drivers/dptx/data/dependencies.props index 8cc88466..0ce1307f 100644 --- a/XilinxProcessorIPLib/drivers/dptx/data/dependencies.props +++ b/XilinxProcessorIPLib/drivers/dptx/data/dependencies.props @@ -1,5 +1,6 @@ xdptx_audio_example.c=xdptx_example_common.h,xdptx_example_common.c xdptx_intr_example.c=xdptx_example_common.h,xdptx_example_common.c +xdptx_mst_example.c=xdptx_example_common.h,xdptx_example_common.c xdptx_poll_example.c=xdptx_example_common.h,xdptx_example_common.c xdptx_selftest_example.c=xdptx_example_common.h,xdptx_example_common.c xdptx_timer_example.c=xdptx_example_common.h,xdptx_example_common.c diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/index.html b/XilinxProcessorIPLib/drivers/dptx/examples/index.html index 0a79dcc3..7bf7baae 100755 --- a/XilinxProcessorIPLib/drivers/dptx/examples/index.html +++ b/XilinxProcessorIPLib/drivers/dptx/examples/index.html @@ -12,6 +12,7 @@
* MODIFICATION HISTORY: @@ -175,6 +175,9 @@ u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr, { u32 Status; + /* Use single-stream transport (SST) mode for this example. */ + XDptx_MstCfgModeDisable(InstancePtr); + /* Do platform initialization here. This is hardware system specific - * it is up to the user to implement this function. */ Dptx_PlatformInit(); diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_mst_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_mst_example.c new file mode 100644 index 00000000..b1b21b7c --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_mst_example.c @@ -0,0 +1,325 @@ +/******************************************************************************* + * + * Copyright (C) 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdptx_mst_example.c + * + * Contains a design example using the XDptx driver in multi-stream transport + * (MST) mode. + * + * @note When topology discovery is enabled, the required stack size will + * be larger than the default that SDK sets of 0x400. Increase the + * stack size if the ALLOCATE_FROM_SINKLIST option is used. Testing + * was done with a stack size of 0x1000. + * @note For this example to display output, the user will need to + * implement initialization of the system (Dptx_PlatformInit) and, + * after training is complete, implement configuration of the video + * stream source in order to provide the DisplayPort core with + * input. See XAPP1178 for reference. + * @note The functions Dptx_PlatformInit and Dptx_StreamSrc* are declared + * extern in xdptx_example_common.h and are left up to the user to + * implement. + * + *+ * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ----------------------------------------------- + * 1.00a als 08/07/14 Initial creation. + *+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xdptx_example_common.h" + +/**************************** Constant Definitions ****************************/ + +/* The number of streams to enable. */ +#define NUM_STREAMS 4 + +/* This enables topology discovery which will create a list of sinks in the + * topology. If ALLOCATE_FROM_SINKLIST is defined, the streams will sent to + * to the sinks with the corresponding index. See the function calls for + * the XDptx_SetStreamSelectFromSinkList driver function below. */ +#define ALLOCATE_FROM_SINKLIST +#ifdef ALLOCATE_FROM_SINKLIST +/* Define the mapping between sinks and streams. The sink numbers are in the + * order that they are discovered by the XDptx_FindAccessibleDpDevices driver + * function. */ +#define STREAM1_USE_SINKNUM 0 +#define STREAM2_USE_SINKNUM 1 +#define STREAM3_USE_SINKNUM 2 +#define STREAM4_USE_SINKNUM 3 +#endif + +/* The video resolution from the display mode timings (DMT) table to use for + * each stream. */ +#define USE_VIDEO_MODE XDPTX_VM_1920x1080_60_P + +/* The color depth (bits per color component) to use for each stream. */ +#define USE_BPC 8 + +/**************************** Function Prototypes *****************************/ + +u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId); + +/**************************** Function Definitions ****************************/ + +/******************************************************************************/ +/** + * This function is the main function of the XDptx multi-stream transport (MST) + * example. + * + * @param None. + * + * @return + * - XST_FAILURE if the MST example was unsuccessful - system + * setup failed. + * + * @note Unless setup failed, main will never return since + * Dptx_MstExample is blocking. + * +*******************************************************************************/ +int main(void) +{ + /* Run the XDptx MST example. */ + Dptx_MstExample(&DptxInstance, DPTX_DEVICE_ID); + + return XST_FAILURE; +} + +/******************************************************************************/ +/** + * The main entry point for the multi-stream transport (MST) example using the + * XDptx driver. This function will either discover the topology and map streams + * to the sinks in the sink list, or map streams to relative addresses. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param DeviceId is the unique device ID of the DisplayPort TX core + * instance. + * + * @return + * - XST_FAILURE if the system setup failed. + * - XST_SUCCESS should never return since this function, if setup + * was successful, is blocking. + * + * @note If system setup was successful, this function is blocking. + * +*******************************************************************************/ +u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId) +{ + u32 Status; + XDptx_VideoMode VideoMode = USE_VIDEO_MODE; + u8 Bpc = USE_BPC; + u32 MaskVal; + + /* Enable multi-stream transport (MST) mode for this example. */ + XDptx_MstCfgModeEnable(InstancePtr); + if (NUM_STREAMS >= 1) { + XDptx_MstCfgStreamEnable(InstancePtr, XDPTX_STREAM_ID1); + } + if (NUM_STREAMS >= 2) { + XDptx_MstCfgStreamEnable(InstancePtr, XDPTX_STREAM_ID2); + } + if (NUM_STREAMS >= 3) { + XDptx_MstCfgStreamEnable(InstancePtr, XDPTX_STREAM_ID3); + } + if (NUM_STREAMS >= 4) { + XDptx_MstCfgStreamEnable(InstancePtr, XDPTX_STREAM_ID4); + } + + /* Do platform initialization here. This is hardware system specific - + * it is up to the user to implement this function. */ + Dptx_PlatformInit(); + /******************/ + + Status = Dptx_SetupExample(InstancePtr, DeviceId); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* A DisplayPort connection must exist at this point. See the interrupt + * and polling examples for waiting for connection events. */ + Status = Dptx_StartLink(InstancePtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE); + XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER); + + XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID1, Bpc); + XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID2, Bpc); + XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID3, Bpc); + XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID4, Bpc); + + Status = XDptx_GetRxCapabilities(InstancePtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + +#ifndef ALLOCATE_FROM_SINKLIST + u8 Lct; + u8 Rad[15]; + + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) { + Lct = 2; Rad[0] = 8; + XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID1, Lct, Rad); + } + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID2)) { + Lct = 3; Rad[0] = 1; Rad[1] = 8; + XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID2, Lct, Rad); + } + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID3)) { + Lct = 4; Rad[0] = 1; Rad[1] = 1; Rad[2] = 8; + XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID3, Lct, Rad); + } + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID4)) { + Lct = 4; Rad[0] = 1; Rad[1] = 1; Rad[2] = 9; + XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID4, Lct, Rad); + } + +#else + xil_printf("Find topology >>>\n"); + InstancePtr->Topology.NodeTotal = 0; + InstancePtr->Topology.SinkTotal = 0; + + XDptx_FindAccessibleDpDevices(InstancePtr, 1, NULL); + xil_printf("<<< Find topology DONE.\n"); + + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) { + XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID1, + STREAM1_USE_SINKNUM); + } + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) { + XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID2, + STREAM2_USE_SINKNUM); + } + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) { + XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID3, + STREAM3_USE_SINKNUM); + } + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) { + XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID4, + STREAM4_USE_SINKNUM); + } +#endif + + /* Disable MST for now. */ + XDptx_MstDisable(InstancePtr); + + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) { + XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID1, + VideoMode); + } + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID2)) { + XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID2, + VideoMode); + } + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID3)) { + XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID3, + VideoMode); + } + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID4)) { + XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID4, + VideoMode); + } + + /* Disable main stream to force sending of IDLE patterns. */ + XDptx_DisableMainLink(InstancePtr); + + /* Reset the transmitter. */ + XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, + XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK); + XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, 0x0); + + /* Set the video modes for each stream. */ + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) { + XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID1); + } + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID2)) { + XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID2); + } + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID3)) { + XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID3); + } + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID4)) { + XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID4); + } + + /* Configure video stream source or generator here. This function needs + * to be implemented in order for video to be displayed and is hardware + * system specific. It is up to the user to implement this function. */ + Dptx_StreamSrcSetup(InstancePtr); + Dptx_StreamSrcConfigure(InstancePtr); + Dptx_StreamSrcSync(InstancePtr); + //////////////////////////////////// + + /* Reset the transmitter. */ + XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, + XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK); + XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, 0x0); + + /* Mask interrupts while allocating payloads. */ + MaskVal = XDptx_ReadReg(InstancePtr->Config.BaseAddr, + XDPTX_INTERRUPT_MASK); + XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_INTERRUPT_MASK, + 0x3F); + + /* Allocate payloads. */ + XDptx_MstEnable(InstancePtr); + XDptx_AllocatePayloadStreams(InstancePtr); + + /* Reset the transmitter. */ + XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, + XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK); + XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, 0x0); + + /* Sync the stream source to the DisplayPort TX if needed. */ + Dptx_StreamSrcSync(InstancePtr); + //////////////////////////////////// + + /* Enable the main link. */ + XDptx_EnableMainLink(InstancePtr); + + /* Unmask interrupts. */ + XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_INTERRUPT_MASK, + MaskVal); + + /* Do not return. */ + while (1); + + return XST_SUCCESS; +} diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c index cd3e6194..c0a2e930 100644 --- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c @@ -42,11 +42,11 @@ * implement initialization of the system (Dptx_PlatformInit) and, * after training is complete, implement configuration of the video * stream source in order to provide the DisplayPort core with - * input (Dptx_ConfigureStreamSrc - called in - * xdptx_example_common.c). See XAPP1178 for reference. - * @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are - * declared extern in xdptx_example_common.h and are left up to the - * user to implement. + * input (Dptx_StreamSrc* - called in xdptx_example_common.c). See + * XAPP1178 for reference. + * @note The functions Dptx_PlatformInit and Dptx_StreamSrc* are declared + * extern in xdptx_example_common.h and are left up to the user to + * implement. * ** MODIFICATION HISTORY: diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c index a311465a..5b21c2bf 100644 --- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c @@ -45,11 +45,11 @@ * implement initialization of the system (Dptx_PlatformInit) and, * after training is complete, implement configuration of the video * stream source in order to provide the DisplayPort core with - * input (Dptx_ConfigureStreamSrc - called in - * xdptx_example_common.c). See XAPP1178 for reference. - * @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are - * declared extern in xdptx_example_common.h and are left up to the - * user to implement. + * input (Dptx_StreamSrc* - called in xdptx_example_common.c). See + * XAPP1178 for reference. + * @note The functions Dptx_PlatformInit and Dptx_StreamSrc* are declared + * extern in xdptx_example_common.h and are left up to the user to + * implement. * ** *******************************************************************************/ diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c index 7a135202..c1a829a8 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c @@ -878,9 +878,9 @@ u32 XDptx_ClearPayloadVcIdTable(XDptx *InstancePtr) * source to the target DisplayPort device. * @param DpcdAddress is the DPCD address of the target device that data * will be written to. - * @param BytesToRead is the number of bytes to write to the specified + * @param BytesToWrite is the number of bytes to write to the specified * DPCD address. - * @param ReadData is a pointer to a buffer that stores the data to write + * @param WriteData is a pointer to a buffer that stores the data to write * to the DPCD location. * * @return diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c index c1ff46e6..86cbcc04 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c @@ -93,6 +93,8 @@ static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel); * - Vertical back porch * * @param InstancePtr is a pointer to the XDptx instance. + * @param Stream is the stream number for which to calculate the MSA + * values. * * @return None. * @@ -253,6 +255,8 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream) * XDptx_VideoMode enumeration in xdptx.h lists the available video modes. * * @param InstancePtr is a pointer to the XDptx instance. + * @param Stream is the stream number for which the MSA values will be + * used for. * @param VideoMode is one of the enumerated standard video modes that is * used to determine the MSA values to be used. * @@ -300,6 +304,8 @@ void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr, u8 Stream, * Identification Data (EDID). * * @param InstancePtr is a pointer to the XDptx instance + * @param Stream is the stream number for which the MSA values will be + * used for. * * @return None. * @@ -385,7 +391,7 @@ void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr, u8 Stream) * This function takes a the main stream attributes from MsaConfigCustom and * copies them into InstancePtr->MsaConfig. If desired, given a base set of * attributes, the rest of the attributes may be derived. The minimal required - * main stream attributes that must be contained in the MsaConfigCustom + * main stream attributes (MSA) that must be contained in the MsaConfigCustom * structure are: * - Pixel clock (in KHz) * - Horizontal sync polarity @@ -400,6 +406,8 @@ void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr, u8 Stream) * - Horizontal front porch * * @param InstancePtr is a pointer to the XDptx instance. + * @param Stream is the stream number for which the MSA values will be + * used for. * @param MsaConfigCustom is the structure that will be used to copy the * main stream attributes from (into InstancePtr->MsaConfig). * @param Recalculate is a boolean enable that determines whether or not @@ -461,6 +469,7 @@ void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, u8 Stream, * This function sets the bits per color value of the video stream. * * @param InstancePtr is a pointer to the XDptx instance + * @param Stream is the stream number for which to set the color depth. * @param BitsPerColor is the new number of bits per color to use. * * @return None. @@ -484,6 +493,21 @@ void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 Stream, u8 BitsPerColor) XDptx_CfgMsaRecalculate(InstancePtr, Stream); } +/******************************************************************************/ +/** + * This function enables or disables synchronous clock mode for a video stream. + * + * @param InstancePtr is a pointer to the XDptx instance + * @param Stream is the stream number for which to enable or disable + * synchronous clock mode. + * @param Enable if set to 1, will enable synchronous clock mode. + * Otherwise, if set to 0, synchronous clock mode will be disabled. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ void XDptx_CfgMsaEnSynchClkMode(XDptx *InstancePtr, u8 Stream, u8 Enable) { XDptx_MainStreamAttributes *MsaConfig = @@ -512,6 +536,7 @@ void XDptx_CfgMsaEnSynchClkMode(XDptx *InstancePtr, u8 Stream, u8 Enable) * configuration structure. * * @param InstancePtr is a pointer to the XDptx instance + * @param Stream is the stream number for which to set the MSA values for. * * @return None. * @@ -535,6 +560,7 @@ void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream) * TX core. * * @param InstancePtr is a pointer to the XDptx instance. + * @param Stream is the stream number for which to clear the MSA values. * * @return None. * @@ -596,6 +622,7 @@ void XDptx_ClearMsaValues(XDptx *InstancePtr, u8 Stream) * structure. * * @param InstancePtr is a pointer to the XDptx instance. + * @param Stream is the stream number for which to set the MSA values for. * * @return None. ** MODIFICATION HISTORY: @@ -131,6 +131,9 @@ u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId, { u32 Status; + /* Use single-stream transport (SST) mode for this example. */ + XDptx_MstCfgModeDisable(InstancePtr); + /* Do platform initialization here. This is hardware system specific - * it is up to the user to implement this function. */ Dptx_PlatformInit(); diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h index 5592f9e1..17432a76 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h @@ -137,6 +137,19 @@ * function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler * function. * + * Multi-stream transport (MST) mode + * + * The driver handles MST mode functionality, including sideband messaging, + * topology discovery, virtual channel payload ID table management, and + * directing streams to different sinks. + * + * MST testing has been done at 5.40Gbps per 4 lanes, with 4 sinks in a daisy- + * chain configuration, with each stream having the same resolution. Extensive + * testing has been done at resolutions of 1080p for each of 1 to 4 streams and + * UHD/2 for each of 1 or 2 streams. Other resolutions have been tested as well, + * however with the current version of the driver, some monitors required a + * power cycle for all streams to come up. + * * Audio * * The driver does not handle audio. For an example as to how to configure and @@ -153,8 +166,24 @@ * it is recommended that application developers leave asserts on during * development. * - * Limitations + * Limitations and known issues * + * - For MST mode to correctly display, the current version of the driver + * requires that each of the DisplayPort TX streams be allocated without + * skipping streams (i.e. assign stream 1, stream 2, and stream 3 - problems + * were experienced if skipping stream 2 and assigning stream 4 instead). + * skipping monitors in a daisy chain is OK as long as they are assigned to + * streams in order. + * - In MST mode, the current version of the driver does not support removal of + * an allocated stream from the virtual channel payload ID table without + * clearing the entire table. + * - Some sideband messages have not been implemented in the current version of + * the driver for MST mode. Notable, reception of a CONNECTION_STATUS_NOTIFY + * sideband message. + * - Some monitors required a power cycle for all streams to come up at certain + * resolutions (outside of the 1080p and UHD/2 resolutions) during testing. + * Different resolutions for different streams were not tested. This will be + * investigated for the next SDK release. * - The driver does not handle audio. See the audio example in the driver * examples directory for the required sequence for enabling audio. * @@ -167,6 +196,7 @@ * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- * 1.00a als 05/17/14 Initial release. + * als 08/03/14 Initial MST addition. ** *******************************************************************************/ diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h index 1ea28ef9..a4fb7272 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h @@ -46,6 +46,7 @@ * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- * 1.00a als 05/17/14 Initial release. + * als 08/03/14 Initial MST addition. *