diff --git a/XilinxProcessorIPLib/drivers/axivdma/data/axivdma.mdd b/XilinxProcessorIPLib/drivers/axivdma/data/axivdma.mdd index 0b42e3c9..48a347ec 100755 --- a/XilinxProcessorIPLib/drivers/axivdma/data/axivdma.mdd +++ b/XilinxProcessorIPLib/drivers/axivdma/data/axivdma.mdd @@ -37,7 +37,7 @@ BEGIN driver axivdma OPTION supported_peripherals = (axi_vdma_v[4-9]_[0-9][0-9]_[a-z] axi_vdma_v[4-9]_[0-9]); OPTION driver_state = ACTIVE; OPTION copyfiles = all; - OPTION VERSION = 5.1; + OPTION VERSION = 6.0; OPTION NAME = axivdma; END driver diff --git a/XilinxProcessorIPLib/drivers/axivdma/data/axivdma.tcl b/XilinxProcessorIPLib/drivers/axivdma/data/axivdma.tcl index 82e799d1..77c1d9b2 100755 --- a/XilinxProcessorIPLib/drivers/axivdma/data/axivdma.tcl +++ b/XilinxProcessorIPLib/drivers/axivdma/data/axivdma.tcl @@ -59,9 +59,9 @@ #uses "xillib.tcl" proc generate {drv_handle} { - xdefine_vdma_include_file $drv_handle "xparameters.h" "XAxiVdma" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_NUM_FSTORES" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_AXI_MM2S_ACLK_FREQ_HZ" "C_AXI_S2MM_ACLK_FREQ_HZ" "C_MM2S_GENLOCK_MODE" "C_MM2S_GENLOCK_NUM_MASTERS" "C_S2MM_GENLOCK_MODE" "C_S2MM_GENLOCK_NUM_MASTERS" "C_INCLUDE_SG" "C_ENABLE_VIDPRMTR_READS" "C_USE_FSYNC" "C_FLUSH_ON_FSYNC" "C_MM2S_LINEBUFFER_DEPTH" "C_S2MM_LINEBUFFER_DEPTH" "C_INCLUDE_INTERNAL_GENLOCK" "C_S2MM_SOF_ENABLE" "C_M_AXIS_MM2S_TDATA_WIDTH" "C_S_AXIS_S2MM_TDATA_WIDTH" "C_ENABLE_DEBUG_INFO_1" "C_ENABLE_DEBUG_INFO_5" "C_ENABLE_DEBUG_INFO_6" "C_ENABLE_DEBUG_INFO_7" "C_ENABLE_DEBUG_INFO_9" "C_ENABLE_DEBUG_INFO_13" "C_ENABLE_DEBUG_INFO_14" "C_ENABLE_DEBUG_INFO_15" "C_ENABLE_DEBUG_ALL" - xdefine_vdma_canonical_xpars $drv_handle "xparameters.h" "AxiVdma" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_NUM_FSTORES" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_AXI_MM2S_ACLK_FREQ_HZ" "C_AXI_S2MM_ACLK_FREQ_HZ" "C_MM2S_GENLOCK_MODE" "C_MM2S_GENLOCK_NUM_MASTERS" "C_S2MM_GENLOCK_MODE" "C_S2MM_GENLOCK_NUM_MASTERS" "C_INCLUDE_SG" "C_ENABLE_VIDPRMTR_READS" "C_USE_FSYNC" "C_FLUSH_ON_FSYNC" "C_MM2S_LINEBUFFER_DEPTH" "C_S2MM_LINEBUFFER_DEPTH" "C_INCLUDE_INTERNAL_GENLOCK" "C_S2MM_SOF_ENABLE" "C_M_AXIS_MM2S_TDATA_WIDTH" "C_S_AXIS_S2MM_TDATA_WIDTH" "C_ENABLE_DEBUG_INFO_1" "C_ENABLE_DEBUG_INFO_5" "C_ENABLE_DEBUG_INFO_6" "C_ENABLE_DEBUG_INFO_7" "C_ENABLE_DEBUG_INFO_9" "C_ENABLE_DEBUG_INFO_13" "C_ENABLE_DEBUG_INFO_14" "C_ENABLE_DEBUG_INFO_15" "C_ENABLE_DEBUG_ALL" - ::hsi::utils::define_config_file $drv_handle "xaxivdma_g.c" "XAxiVdma" "DEVICE_ID" "C_BASEADDR" "C_NUM_FSTORES" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_ENABLE_VIDPRMTR_READS" "C_USE_FSYNC" "C_FLUSH_ON_FSYNC" "C_MM2S_LINEBUFFER_DEPTH" "C_S2MM_LINEBUFFER_DEPTH" "C_MM2S_GENLOCK_MODE" "C_S2MM_GENLOCK_MODE" "C_INCLUDE_INTERNAL_GENLOCK" "C_S2MM_SOF_ENABLE" "C_M_AXIS_MM2S_TDATA_WIDTH" "C_S_AXIS_S2MM_TDATA_WIDTH" "C_ENABLE_DEBUG_INFO_1" "C_ENABLE_DEBUG_INFO_5" "C_ENABLE_DEBUG_INFO_6" "C_ENABLE_DEBUG_INFO_7" "C_ENABLE_DEBUG_INFO_9" "C_ENABLE_DEBUG_INFO_13" "C_ENABLE_DEBUG_INFO_14" "C_ENABLE_DEBUG_INFO_15" "C_ENABLE_DEBUG_ALL" + xdefine_vdma_include_file $drv_handle "xparameters.h" "XAxiVdma" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_NUM_FSTORES" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_AXI_MM2S_ACLK_FREQ_HZ" "C_AXI_S2MM_ACLK_FREQ_HZ" "C_MM2S_GENLOCK_MODE" "C_MM2S_GENLOCK_NUM_MASTERS" "C_S2MM_GENLOCK_MODE" "C_S2MM_GENLOCK_NUM_MASTERS" "C_INCLUDE_SG" "C_ENABLE_VIDPRMTR_READS" "C_USE_FSYNC" "C_FLUSH_ON_FSYNC" "C_MM2S_LINEBUFFER_DEPTH" "C_S2MM_LINEBUFFER_DEPTH" "C_INCLUDE_INTERNAL_GENLOCK" "C_S2MM_SOF_ENABLE" "C_M_AXIS_MM2S_TDATA_WIDTH" "C_S_AXIS_S2MM_TDATA_WIDTH" "C_ENABLE_DEBUG_INFO_1" "C_ENABLE_DEBUG_INFO_5" "C_ENABLE_DEBUG_INFO_6" "C_ENABLE_DEBUG_INFO_7" "C_ENABLE_DEBUG_INFO_9" "C_ENABLE_DEBUG_INFO_13" "C_ENABLE_DEBUG_INFO_14" "C_ENABLE_DEBUG_INFO_15" "C_ENABLE_DEBUG_ALL" "c_addr_width" + xdefine_vdma_canonical_xpars $drv_handle "xparameters.h" "AxiVdma" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_NUM_FSTORES" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_AXI_MM2S_ACLK_FREQ_HZ" "C_AXI_S2MM_ACLK_FREQ_HZ" "C_MM2S_GENLOCK_MODE" "C_MM2S_GENLOCK_NUM_MASTERS" "C_S2MM_GENLOCK_MODE" "C_S2MM_GENLOCK_NUM_MASTERS" "C_INCLUDE_SG" "C_ENABLE_VIDPRMTR_READS" "C_USE_FSYNC" "C_FLUSH_ON_FSYNC" "C_MM2S_LINEBUFFER_DEPTH" "C_S2MM_LINEBUFFER_DEPTH" "C_INCLUDE_INTERNAL_GENLOCK" "C_S2MM_SOF_ENABLE" "C_M_AXIS_MM2S_TDATA_WIDTH" "C_S_AXIS_S2MM_TDATA_WIDTH" "C_ENABLE_DEBUG_INFO_1" "C_ENABLE_DEBUG_INFO_5" "C_ENABLE_DEBUG_INFO_6" "C_ENABLE_DEBUG_INFO_7" "C_ENABLE_DEBUG_INFO_9" "C_ENABLE_DEBUG_INFO_13" "C_ENABLE_DEBUG_INFO_14" "C_ENABLE_DEBUG_INFO_15" "C_ENABLE_DEBUG_ALL" "c_addr_width" + ::hsi::utils::define_config_file $drv_handle "xaxivdma_g.c" "XAxiVdma" "DEVICE_ID" "C_BASEADDR" "C_NUM_FSTORES" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_ENABLE_VIDPRMTR_READS" "C_USE_FSYNC" "C_FLUSH_ON_FSYNC" "C_MM2S_LINEBUFFER_DEPTH" "C_S2MM_LINEBUFFER_DEPTH" "C_MM2S_GENLOCK_MODE" "C_S2MM_GENLOCK_MODE" "C_INCLUDE_INTERNAL_GENLOCK" "C_S2MM_SOF_ENABLE" "C_M_AXIS_MM2S_TDATA_WIDTH" "C_S_AXIS_S2MM_TDATA_WIDTH" "C_ENABLE_DEBUG_INFO_1" "C_ENABLE_DEBUG_INFO_5" "C_ENABLE_DEBUG_INFO_6" "C_ENABLE_DEBUG_INFO_7" "C_ENABLE_DEBUG_INFO_9" "C_ENABLE_DEBUG_INFO_13" "C_ENABLE_DEBUG_INFO_14" "C_ENABLE_DEBUG_INFO_15" "C_ENABLE_DEBUG_ALL" "c_addr_width" } diff --git a/XilinxProcessorIPLib/drivers/axivdma/examples/xaxivdma_example_intr.c b/XilinxProcessorIPLib/drivers/axivdma/examples/xaxivdma_example_intr.c index 975afa00..0ff55790 100644 --- a/XilinxProcessorIPLib/drivers/axivdma/examples/xaxivdma_example_intr.c +++ b/XilinxProcessorIPLib/drivers/axivdma/examples/xaxivdma_example_intr.c @@ -121,8 +121,8 @@ #else #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \ DEFAULT SET TO 0x01000000 -#define DDR_BASE_ADDR 0x01000000 -#define DDR_HIGH_ADDR 0x0F000000 +#define DDR_BASE_ADDR 0x10000000 +#define DDR_HIGH_ADDR 0x20000000 #endif /* Memory space for the frame buffers @@ -172,9 +172,9 @@ * Note that SUBFRAME_HORIZONTAL_SIZE and SUBFRAME_VERTICAL_SIZE must ensure * to be inside the frame. */ -#define SUBFRAME_START_OFFSET (FRAME_HORIZONTAL_LEN * 5 + 32) -#define SUBFRAME_HORIZONTAL_SIZE 100 -#define SUBFRAME_VERTICAL_SIZE 100 +#define SUBFRAME_START_OFFSET (FRAME_HORIZONTAL_LEN * 5 + 64) +#define SUBFRAME_HORIZONTAL_SIZE 0x100 +#define SUBFRAME_VERTICAL_SIZE 0x100 /* Number of frames to work on, this is to set the frame count threshold * @@ -214,11 +214,11 @@ static XScuGic Intc; /* Instance of the Interrupt Controller */ * * Read and write sub-frame use the same settings */ -static u32 ReadFrameAddr; -static u32 WriteFrameAddr; -static u32 BlockStartOffset; -static u32 BlockHoriz; -static u32 BlockVert; +static UINTPTR ReadFrameAddr; +static UINTPTR WriteFrameAddr; +static UINTPTR BlockStartOffset; +static UINTPTR BlockHoriz; +static UINTPTR BlockVert; /* DMA channel setup */ @@ -441,6 +441,13 @@ int main(void) /* Enable your video IP interrupts if needed */ + /* Enable DMA read and write channel interrupts + * + * If interrupts overwhelms the system, please do not enable interrupt + */ + XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_ALL_MASK, XAXIVDMA_WRITE); + XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_ALL_MASK, XAXIVDMA_READ); + /* Start the DMA engine to transfer */ Status = StartTransfer(&AxiVdma); @@ -450,13 +457,6 @@ int main(void) return XST_FAILURE; } - /* Enable DMA read and write channel interrupts - * - * If interrupts overwhelms the system, please do not enable interrupt - */ - XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_ALL_MASK, XAXIVDMA_WRITE); - XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_ALL_MASK, XAXIVDMA_READ); - /* Every set of frame buffer finish causes a completion interrupt */ while ((WriteDone < NUM_TEST_FRAME_SETS) && !ReadError && @@ -503,7 +503,7 @@ int main(void) static int ReadSetup(XAxiVdma *InstancePtr) { int Index; - u32 Addr; + UINTPTR Addr; int Status; ReadCfg.VertSizeInput = SUBFRAME_VERTICAL_SIZE; @@ -569,7 +569,7 @@ static int ReadSetup(XAxiVdma *InstancePtr) static int WriteSetup(XAxiVdma * InstancePtr) { int Index; - u32 Addr; + UINTPTR Addr; int Status; WriteCfg.VertSizeInput = SUBFRAME_VERTICAL_SIZE; diff --git a/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma.c b/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma.c index 69ad9e5b..718fa70a 100644 --- a/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma.c +++ b/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma.c @@ -163,6 +163,7 @@ int XAxiVdma_CfgInitialize(XAxiVdma *InstancePtr, XAxiVdma_Config *CfgPtr, InstancePtr->HasS2Mm = CfgPtr->HasS2Mm; InstancePtr->UseFsync = CfgPtr->UseFsync; InstancePtr->InternalGenLock = CfgPtr->InternalGenLock; + InstancePtr->AddrWidth = CfgPtr->AddrWidth; if (XAxiVdma_Major(InstancePtr) < 3) { InstancePtr->HasSG = 1; @@ -205,6 +206,7 @@ int XAxiVdma_CfgInitialize(XAxiVdma *InstancePtr, XAxiVdma_Config *CfgPtr, RdChannel->HasDRE = CfgPtr->HasMm2SDRE; RdChannel->WordLength = CfgPtr->Mm2SWordLen >> 3; RdChannel->StreamWidth = CfgPtr->Mm2SStreamWidth >> 3; + RdChannel->AddrWidth = InstancePtr->AddrWidth; /* Internal GenLock */ RdChannel->GenLock = CfgPtr->Mm2SGenLock; @@ -266,6 +268,7 @@ int XAxiVdma_CfgInitialize(XAxiVdma *InstancePtr, XAxiVdma_Config *CfgPtr, WrChannel->StartAddrBase = InstancePtr->BaseAddr + XAXIVDMA_S2MM_ADDR_OFFSET; WrChannel->NumFrames = CfgPtr->MaxFrameStoreNum; + WrChannel->AddrWidth = InstancePtr->AddrWidth; /* Flush on Sync */ WrChannel->FlushonFsync = CfgPtr->FlushonFsync; @@ -1007,7 +1010,7 @@ int XAxiVdma_DmaConfig(XAxiVdma *InstancePtr, u16 Direction, * *****************************************************************************/ int XAxiVdma_DmaSetBufferAddr(XAxiVdma *InstancePtr, u16 Direction, - u32 *BufferAddrSet) + UINTPTR *BufferAddrSet) { XAxiVdma_Channel *Channel; diff --git a/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma.h b/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma.h index c46614bb..bb0413bb 100644 --- a/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma.h +++ b/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma.h @@ -396,7 +396,7 @@ typedef void (*XAxiVdma_ErrorCallBack) (void *CallBackRef, u32 ErrorMask); */ typedef struct { u16 DeviceId; /**< DeviceId is the unique ID of the device */ - u32 BaseAddress; /**< BaseAddress is the physical base address of the + UINTPTR BaseAddress; /**< BaseAddress is the physical base address of the * device's registers */ u16 MaxFrameStoreNum; /**< The maximum number of Frame Stores */ int HasMm2S; /**< Whether hw build has read channel */ @@ -447,6 +447,7 @@ typedef struct { int EnableAllDbgFeatures;/**< Enable all Debug features This corresponds to C_ENABLE_DEBUG_ALL configuration parameter */ + int AddrWidth; /**< Address Width */ } XAxiVdma_Config; /** @@ -464,7 +465,7 @@ typedef struct { int EnableSync; /**< Gen-Lock Mode? */ int PointNum; /**< Master we synchronize with */ int EnableFrameCounter; /**< Frame Counter Enable */ - u32 FrameStoreStartAddr[XAXIVDMA_MAX_FRAMESTORE]; + UINTPTR FrameStoreStartAddr[XAXIVDMA_MAX_FRAMESTORE]; /**< Start Addresses of Frame Store Buffers. */ int FixedFrameStoreAddr;/**< Fixed Frame Store Address index */ int GenLockRepeat; /**< Gen-Lock Repeat? */ @@ -497,7 +498,7 @@ typedef struct { * The XAxiVdma driver instance data. */ typedef struct { - u32 BaseAddr; /**< Memory address for this device */ + UINTPTR BaseAddr; /**< Memory address for this device */ int HasSG; /**< Whether hardware has SG engine */ int IsReady; /**< Whether driver is initialized */ @@ -516,6 +517,7 @@ typedef struct { XAxiVdma_Channel ReadChannel; /**< Channel to read from memory */ XAxiVdma_Channel WriteChannel; /**< Channel to write to memory */ + int AddrWidth; /**< Address Width */ } XAxiVdma; @@ -571,7 +573,7 @@ int XAxiVdma_StartReadFrame(XAxiVdma *InstancePtr, int XAxiVdma_DmaConfig(XAxiVdma *InstancePtr, u16 Direction, XAxiVdma_DmaSetup *DmaConfigPtr); int XAxiVdma_DmaSetBufferAddr(XAxiVdma *InstancePtr, u16 Direction, - u32 *BufferAddrSet); + UINTPTR *BufferAddrSet); int XAxiVdma_DmaStart(XAxiVdma *InstancePtr, u16 Direction); void XAxiVdma_DmaStop(XAxiVdma *InstancePtr, u16 Direction); void XAxiVdma_DmaRegisterDump(XAxiVdma *InstancePtr, u16 Direction); @@ -595,4 +597,3 @@ int XAxiVdma_Selftest(XAxiVdma * InstancePtr); #endif #endif /* end of protection macro */ -/** @} */ diff --git a/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma_channel.c b/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma_channel.c index 9ec38b85..23ae422d 100644 --- a/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma_channel.c +++ b/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma_channel.c @@ -207,7 +207,7 @@ void XAxiVdma_ChannelInit(XAxiVdma_Channel *Channel) } XAxiVdma_BdSetNextPtr(BdPtr, - XAXIVDMA_VIRT_TO_PHYS((u32)NextBdPtr)); + XAXIVDMA_VIRT_TO_PHYS((UINTPTR)NextBdPtr)); } Channel->AllCnt = NumFrames; @@ -215,11 +215,11 @@ void XAxiVdma_ChannelInit(XAxiVdma_Channel *Channel) /* Setup the BD addresses so that access the head/tail BDs fast * */ - Channel->HeadBdAddr = (u32)FirstBdPtr; - Channel->HeadBdPhysAddr = XAXIVDMA_VIRT_TO_PHYS((u32)FirstBdPtr); + Channel->HeadBdAddr = (UINTPTR)FirstBdPtr; + Channel->HeadBdPhysAddr = XAXIVDMA_VIRT_TO_PHYS((UINTPTR)FirstBdPtr); - Channel->TailBdAddr = (u32)LastBdPtr; - Channel->TailBdPhysAddr = XAXIVDMA_VIRT_TO_PHYS((u32)LastBdPtr); + Channel->TailBdAddr = (UINTPTR)LastBdPtr; + Channel->TailBdPhysAddr = XAXIVDMA_VIRT_TO_PHYS((UINTPTR)LastBdPtr); Channel->IsValid = 1; @@ -492,13 +492,13 @@ void XAxiVdma_ChannelStartFrmCntEnable(XAxiVdma_Channel *Channel) * to hold all the BDs. * *****************************************************************************/ -int XAxiVdma_ChannelSetBdAddrs(XAxiVdma_Channel *Channel, u32 BdAddrPhys, - u32 BdAddrVirt) +int XAxiVdma_ChannelSetBdAddrs(XAxiVdma_Channel *Channel, UINTPTR BdAddrPhys, + UINTPTR BdAddrVirt) { int NumFrames = Channel->AllCnt; int i; - u32 NextPhys = BdAddrPhys; - u32 CurrVirt = BdAddrVirt; + UINTPTR NextPhys = BdAddrPhys; + UINTPTR CurrVirt = BdAddrVirt; if (Channel->HasSG && XAxiVdma_ChannelIsBusy(Channel)) { xdbg_printf(XDBG_DEBUG_ERROR, @@ -851,12 +851,17 @@ int XAxiVdma_ChannelConfig(XAxiVdma_Channel *Channel, * *****************************************************************************/ int XAxiVdma_ChannelSetBufferAddr(XAxiVdma_Channel *Channel, - u32 *BufferAddrSet, int NumFrames) + UINTPTR *BufferAddrSet, int NumFrames) { int i; u32 WordLenBits; int HiFrmAddr = 0; - int FrmBound = (XAXIVDMA_MAX_FRAMESTORE)/2 - 1; + int FrmBound; + if (Channel->AddrWidth > 32) { + FrmBound = (XAXIVDMA_MAX_FRAMESTORE_64)/2 - 1; + } else { + FrmBound = (XAXIVDMA_MAX_FRAMESTORE)/2 - 1; + } int Loop16 = 0; if (!Channel->IsValid) { @@ -896,10 +901,25 @@ int XAxiVdma_ChannelSetBufferAddr(XAxiVdma_Channel *Channel, Loop16 = 0; } - XAxiVdma_WriteReg(Channel->StartAddrBase, - XAXIVDMA_START_ADDR_OFFSET + - Loop16 * XAXIVDMA_START_ADDR_LEN, - BufferAddrSet[i]); + if (Channel->AddrWidth > 32) { + /* For a 40-bit address XAXIVDMA_MAX_FRAMESTORE + * value should be set to 16 */ + XAxiVdma_WriteReg(Channel->StartAddrBase, + XAXIVDMA_START_ADDR_OFFSET + + Loop16 * XAXIVDMA_START_ADDR_LEN + i*4, + LOWER_32_BITS(BufferAddrSet[i])); + + XAxiVdma_WriteReg(Channel->StartAddrBase, + XAXIVDMA_START_ADDR_MSB_OFFSET + + Loop16 * XAXIVDMA_START_ADDR_LEN + i*4, + UPPER_32_BITS((u64)BufferAddrSet[i])); + } else { + XAxiVdma_WriteReg(Channel->StartAddrBase, + XAXIVDMA_START_ADDR_OFFSET + + Loop16 * XAXIVDMA_START_ADDR_LEN, + BufferAddrSet[i]); + } + if ((NumFrames > FrmBound) && (i == (NumFrames - 1))) XAxiVdma_ChannelHiFrmAddrDisable(Channel); @@ -1309,7 +1329,7 @@ u32 XAxiVdma_ChannelGetEnabledIntr(XAxiVdma_Channel *Channel) *****************************************************************************/ static u32 XAxiVdma_BdRead(XAxiVdma_Bd *BdPtr, int Offset) { - return (*(u32 *)((u32)BdPtr + Offset)); + return (*(u32 *)((UINTPTR)(void *)BdPtr + Offset)); } /*****************************************************************************/ @@ -1326,7 +1346,7 @@ static u32 XAxiVdma_BdRead(XAxiVdma_Bd *BdPtr, int Offset) *****************************************************************************/ static void XAxiVdma_BdWrite(XAxiVdma_Bd *BdPtr, int Offset, u32 Value) { - *(u32 *)((u32)BdPtr + Offset) = Value; + *(u32 *)((UINTPTR)(void *)BdPtr + Offset) = Value; return; } diff --git a/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma_hw.h b/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma_hw.h index 87c41f4f..17ea7c5e 100644 --- a/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma_hw.h +++ b/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma_hw.h @@ -96,6 +96,8 @@ extern "C" { */ #define XAXIVDMA_MAX_FRAMESTORE 32 /**< Maximum # of the frame store */ +#define XAXIVDMA_MAX_FRAMESTORE_64 16 /**< Maximum # of the frame store for 64 bit*/ + /*@}*/ /** @name Maximum transfer length @@ -164,6 +166,8 @@ extern "C" { #define XAXIVDMA_STRD_FRMDLY_OFFSET 0x00000008 /**< Horizontal size */ #define XAXIVDMA_START_ADDR_OFFSET 0x0000000C /**< Start of address */ #define XAXIVDMA_START_ADDR_LEN 0x00000004 /**< Each entry is 4 bytes */ +#define XAXIVDMA_START_ADDR_MSB_OFFSET 0x00000010 /**< Start of address */ + /*@}*/ /** @name Bitmasks of the XAXIVDMA_CR_OFFSET register diff --git a/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma_i.h b/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma_i.h index 90ec408f..5b2cc0c1 100644 --- a/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma_i.h +++ b/XilinxProcessorIPLib/drivers/axivdma/src/xaxivdma_i.h @@ -100,10 +100,10 @@ typedef struct { int WordLength; /* Word length */ int NumFrames; /* Number of frames to work on */ - u32 HeadBdPhysAddr; /* Physical address of the first BD */ - u32 HeadBdAddr; /* Virtual address of the first BD */ - u32 TailBdPhysAddr; /* Physical address of the last BD */ - u32 TailBdAddr; /* Virtual address of the last BD */ + UINTPTR HeadBdPhysAddr; /* Physical address of the first BD */ + UINTPTR HeadBdAddr; /* Virtual address of the first BD */ + UINTPTR TailBdPhysAddr; /* Physical address of the last BD */ + UINTPTR TailBdAddr; /* Virtual address of the last BD */ int Hsize; /* Horizontal size */ int Vsize; /* Vertical size saved for no-sg mode hw start */ @@ -115,6 +115,7 @@ typedef struct { XAxiVdma_Bd BDs[XAXIVDMA_MAX_FRAMESTORE] __attribute__((__aligned__(32))); /*Statically allocated BDs */ u32 DbgFeatureFlags; /* Debug Parameter Flags */ + int AddrWidth; }XAxiVdma_Channel; /* Duplicate layout of XAxiVdma_DmaSetup @@ -131,7 +132,7 @@ typedef struct { int EnableSync; /**< Gen-Lock Mode? */ int PointNum; /**< Master we synchronize with */ int EnableFrameCounter; /**< Frame Counter Enable */ - u32 FrameStoreStartAddr[XAXIVDMA_MAX_FRAMESTORE]; + UINTPTR FrameStoreStartAddr[XAXIVDMA_MAX_FRAMESTORE]; /**< Start Addresses of Frame Store Buffers. */ int FixedFrameStoreAddr;/**< Fixed Frame Store Address index */ int GenLockRepeat; /**< Gen-Lock Repeat? */ @@ -159,11 +160,11 @@ u32 XAxiVdma_ChannelGetEnabledIntr(XAxiVdma_Channel *Channel); void XAxiVdma_ChannelIntrClear(XAxiVdma_Channel *Channel, u32 IntrType); int XAxiVdma_ChannelStartTransfer(XAxiVdma_Channel *Channel, XAxiVdma_ChannelSetup *ChannelCfgPtr); -int XAxiVdma_ChannelSetBdAddrs(XAxiVdma_Channel *Channel, u32 BdAddrPhys, - u32 BdAddrVirt); +int XAxiVdma_ChannelSetBdAddrs(XAxiVdma_Channel *Channel, UINTPTR BdAddrPhys, + UINTPTR BdAddrVirt); int XAxiVdma_ChannelConfig(XAxiVdma_Channel *Channel, XAxiVdma_ChannelSetup *ChannelCfgPtr); -int XAxiVdma_ChannelSetBufferAddr(XAxiVdma_Channel *Channel, u32 *AddrSet, +int XAxiVdma_ChannelSetBufferAddr(XAxiVdma_Channel *Channel, UINTPTR *AddrSet, int NumFrames); int XAxiVdma_ChannelStart(XAxiVdma_Channel *Channel); void XAxiVdma_ChannelStop(XAxiVdma_Channel *Channel);