From 187e18e3dc968a2a5582bdfe58a4314de5473e53 Mon Sep 17 00:00:00 2001 From: Kedareswara rao Appana Date: Mon, 27 Jul 2015 15:07:15 +0530 Subject: [PATCH] axidma: Add support for 64-bit addressing This patch updates the driver to support 64-bit addressing. Signed-off-by: Kedareswara rao Appana Acked-by: Anirudha Sarangi --- .../drivers/axidma/data/axidma.mdd | 2 +- .../drivers/axidma/data/axidma.tcl | 6 +- .../axidma/examples/xaxidma_example_sg_poll.c | 15 +- .../examples/xaxidma_example_simple_poll.c | 10 +- .../drivers/axidma/src/xaxidma.c | 24 ++- .../drivers/axidma/src/xaxidma.h | 5 +- .../drivers/axidma/src/xaxidma_bd.c | 24 ++- .../drivers/axidma/src/xaxidma_bd.h | 21 ++- .../drivers/axidma/src/xaxidma_bdring.c | 155 ++++++++++++------ .../drivers/axidma/src/xaxidma_bdring.h | 27 +-- .../drivers/axidma/src/xaxidma_hw.h | 30 ++-- 11 files changed, 214 insertions(+), 105 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/axidma/data/axidma.mdd b/XilinxProcessorIPLib/drivers/axidma/data/axidma.mdd index 188edf78..773a39d3 100755 --- a/XilinxProcessorIPLib/drivers/axidma/data/axidma.mdd +++ b/XilinxProcessorIPLib/drivers/axidma/data/axidma.mdd @@ -37,7 +37,7 @@ BEGIN driver axidma OPTION supported_peripherals = (axi_dma_v[3-9]_[0-9][0-9]_[a-z] axi_dma_v[3-9]_[0-9]); OPTION driver_state = ACTIVE; OPTION copyfiles = all; - OPTION VERSION = 8.1; + OPTION VERSION = 9.0; OPTION NAME = axidma; END driver diff --git a/XilinxProcessorIPLib/drivers/axidma/data/axidma.tcl b/XilinxProcessorIPLib/drivers/axidma/data/axidma.tcl index 9206d435..f0f806f7 100755 --- a/XilinxProcessorIPLib/drivers/axidma/data/axidma.tcl +++ b/XilinxProcessorIPLib/drivers/axidma/data/axidma.tcl @@ -39,9 +39,9 @@ set periph_ninstances 0 proc generate {drv_handle} { - ::hsi::utils::define_include_file $drv_handle "xparameters.h" "XAxiDma" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_SG_INCLUDE_STSCNTRL_STRM" "C_INCLUDE_MM2S_DRE" "C_INCLUDE_S2MM_DRE" "C_INCLUDE_MM2S" "C_INCLUDE_S2MM" "C_M_AXI_MM2S_DATA_WIDTH" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_ENABLE_MULTI_CHANNEL" "C_NUM_MM2S_CHANNELS" "C_NUM_S2MM_CHANNELS" "C_MM2S_BURST_SIZE" "C_S2MM_BURST_SIZE" "C_MICRO_DMA" - ::hsi::utils::define_canonical_xpars $drv_handle "xparameters.h" "AxiDma" "DEVICE_ID" "C_BASEADDR" "C_SG_INCLUDE_STSCNTRL_STRM" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_ENABLE_MULTI_CHANNEL" "C_NUM_MM2S_CHANNELS" "C_NUM_S2MM_CHANNELS" "C_MM2S_BURST_SIZE" "C_S2MM_BURST_SIZE" "C_MICRO_DMA" - ::hsi::utils::define_config_file $drv_handle "xaxidma_g.c" "XAxiDma" "DEVICE_ID" "C_BASEADDR" "C_SG_INCLUDE_STSCNTRL_STRM" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_NUM_MM2S_CHANNELS" "C_NUM_S2MM_CHANNELS" "C_MM2S_BURST_SIZE" "C_S2MM_BURST_SIZE" "C_MICRO_DMA" + ::hsi::utils::define_include_file $drv_handle "xparameters.h" "XAxiDma" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_SG_INCLUDE_STSCNTRL_STRM" "C_INCLUDE_MM2S_DRE" "C_INCLUDE_S2MM_DRE" "C_INCLUDE_MM2S" "C_INCLUDE_S2MM" "C_M_AXI_MM2S_DATA_WIDTH" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_ENABLE_MULTI_CHANNEL" "C_NUM_MM2S_CHANNELS" "C_NUM_S2MM_CHANNELS" "C_MM2S_BURST_SIZE" "C_S2MM_BURST_SIZE" "C_MICRO_DMA" "c_addr_width" + ::hsi::utils::define_canonical_xpars $drv_handle "xparameters.h" "AxiDma" "DEVICE_ID" "C_BASEADDR" "C_SG_INCLUDE_STSCNTRL_STRM" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_ENABLE_MULTI_CHANNEL" "C_NUM_MM2S_CHANNELS" "C_NUM_S2MM_CHANNELS" "C_MM2S_BURST_SIZE" "C_S2MM_BURST_SIZE" "C_MICRO_DMA" "c_addr_width" + ::hsi::utils::define_config_file $drv_handle "xaxidma_g.c" "XAxiDma" "DEVICE_ID" "C_BASEADDR" "C_SG_INCLUDE_STSCNTRL_STRM" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_NUM_MM2S_CHANNELS" "C_NUM_S2MM_CHANNELS" "C_MM2S_BURST_SIZE" "C_S2MM_BURST_SIZE" "C_MICRO_DMA" "c_addr_width" } # diff --git a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_poll.c b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_poll.c index 73b0178d..5c4e3716 100644 --- a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_poll.c +++ b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_poll.c @@ -113,6 +113,8 @@ extern void xil_printf(const char *format, ...); #define DDR_BASE_ADDR XPAR_AXI_7SDDR_0_S_AXI_BASEADDR #elif XPAR_MIG7SERIES_0_BASEADDR #define DDR_BASE_ADDR XPAR_MIG7SERIES_0_BASEADDR +#elif XPAR_PSU_DDR_0_S_AXI_BASEADDR +#define MEMORY_BASE XPAR_PSU_DDR_0_S_AXI_BASEADDR #endif #ifndef DDR_BASE_ADDR @@ -133,6 +135,7 @@ extern void xil_printf(const char *format, ...); #define MAX_PKT_LEN 0x20 +#define MARK_UNCACHEABLE 0x701 #define TEST_START_VALUE 0xC @@ -196,6 +199,10 @@ int main(void) xil_printf("\r\n--- Entering main() --- \r\n"); +#ifdef __aarch64__ + Xil_SetTlbAttributes(MEM_BASE_ADDR, MARK_UNCACHEABLE); +#endif + Config = XAxiDma_LookupConfig(DMA_DEV_ID); if (!Config) { xil_printf("No config found for %d\r\n", DMA_DEV_ID); @@ -298,7 +305,7 @@ static int RxSetup(XAxiDma * AxiDmaInstPtr) XAxiDma_Bd *BdCurPtr; u32 BdCount; u32 FreeBdCount; - u32 RxBufferPtr; + UINTPTR RxBufferPtr; int Index; RxRingPtr = XAxiDma_GetRxRing(&AxiDma); @@ -507,7 +514,7 @@ static int SendPacket(XAxiDma * AxiDmaInstPtr) /* Flush the SrcBuffer before the DMA transfer, in case the Data Cache * is enabled */ - Xil_DCacheFlushRange((u32)TxPacket, MAX_PKT_LEN); + Xil_DCacheFlushRange((UINTPTR)TxPacket, MAX_PKT_LEN); /* Allocate a BD */ @@ -517,7 +524,7 @@ static int SendPacket(XAxiDma * AxiDmaInstPtr) } /* Set up the BD using the information of the packet to transmit */ - Status = XAxiDma_BdSetBufAddr(BdPtr, (u32) Packet); + Status = XAxiDma_BdSetBufAddr(BdPtr, (UINTPTR) Packet); if (Status != XST_SUCCESS) { xil_printf("Tx set buffer addr %x on BD %x failed %d\r\n", (unsigned int)Packet, (unsigned int)BdPtr, Status); @@ -590,7 +597,7 @@ static int CheckData(void) /* Invalidate the DestBuffer before receiving the data, in case the * Data Cache is enabled */ - Xil_DCacheInvalidateRange((u32)RxPacket, MAX_PKT_LEN); + Xil_DCacheInvalidateRange((UINTPTR)RxPacket, MAX_PKT_LEN); for(Index = 0; Index < MAX_PKT_LEN; Index++) { if (RxPacket[Index] != Value) { diff --git a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c index a9ef0700..06eb019b 100644 --- a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c +++ b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c @@ -276,19 +276,19 @@ int XAxiDma_SimplePollExample(u16 DeviceId) /* Flush the SrcBuffer before the DMA transfer, in case the Data Cache * is enabled */ - Xil_DCacheFlushRange((u32)TxBufferPtr, MAX_PKT_LEN); + Xil_DCacheFlushRange((UINTPTR)TxBufferPtr, MAX_PKT_LEN); for(Index = 0; Index < Tries; Index ++) { - Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) RxBufferPtr, + Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) RxBufferPtr, MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA); if (Status != XST_SUCCESS) { return XST_FAILURE; } - Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) TxBufferPtr, + Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) TxBufferPtr, MAX_PKT_LEN, XAXIDMA_DMA_TO_DEVICE); if (Status != XST_SUCCESS) { @@ -340,7 +340,9 @@ static int CheckData(void) /* Invalidate the DestBuffer before receiving the data, in case the * Data Cache is enabled */ - Xil_DCacheInvalidateRange((u32)RxPacket, MAX_PKT_LEN); +#ifndef __aarch64__ + Xil_DCacheInvalidateRange((UINTPTR)RxPacket, MAX_PKT_LEN); +#endif for(Index = 0; Index < MAX_PKT_LEN; Index++) { if (RxPacket[Index] != Value) { diff --git a/XilinxProcessorIPLib/drivers/axidma/src/xaxidma.c b/XilinxProcessorIPLib/drivers/axidma/src/xaxidma.c index fe8b310c..e53028db 100644 --- a/XilinxProcessorIPLib/drivers/axidma/src/xaxidma.c +++ b/XilinxProcessorIPLib/drivers/axidma/src/xaxidma.c @@ -151,6 +151,7 @@ int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config) InstancePtr->HasSg = Config->HasSg; InstancePtr->MicroDmaMode = Config->MicroDmaMode; + InstancePtr->AddrWidth = Config->AddrWidth; /* Get the number of channels */ InstancePtr->TxNumChannels = Config->Mm2sNumChannels; @@ -200,6 +201,11 @@ int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config) BaseAddr + XAXIDMA_TX_OFFSET; InstancePtr->TxBdRing.HasStsCntrlStrm = Config->HasStsCntrlStrm; + if (InstancePtr->AddrWidth > 32) + InstancePtr->TxBdRing.Addr_ext = 1; + else + InstancePtr->TxBdRing.Addr_ext = 0; + InstancePtr->TxBdRing.HasDRE = Config->HasMm2SDRE; InstancePtr->TxBdRing.DataWidth = ((unsigned int)Config->Mm2SDataWidth >> 3); @@ -229,6 +235,10 @@ int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config) ((Config->S2MmDataWidth / 4) * Config->S2MmBurstSize); } + if (InstancePtr->AddrWidth > 32) + InstancePtr->RxBdRing[Index].Addr_ext = 1; + else + InstancePtr->RxBdRing[Index].Addr_ext = 0; } } @@ -820,7 +830,7 @@ int XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr, int Direction, int Select) * Simple mode. * *****************************************************************************/ -int XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, u32 BuffAddr, u32 Length, +u32 XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, UINTPTR BuffAddr, u32 Length, int Direction) { u32 WordBits; @@ -880,7 +890,11 @@ int XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, u32 BuffAddr, u32 Length, XAxiDma_WriteReg(InstancePtr->TxBdRing.ChanBase, - XAXIDMA_SRCADDR_OFFSET, BuffAddr); + XAXIDMA_SRCADDR_OFFSET, LOWER_32_BITS(BuffAddr)); + if (InstancePtr->AddrWidth > 32) + XAxiDma_WriteReg(InstancePtr->TxBdRing.ChanBase, + XAXIDMA_SRCADDR_MSB_OFFSET, + UPPER_32_BITS(BuffAddr)); XAxiDma_WriteReg(InstancePtr->TxBdRing.ChanBase, XAXIDMA_CR_OFFSET, @@ -938,7 +952,11 @@ int XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, u32 BuffAddr, u32 Length, XAxiDma_WriteReg(InstancePtr->RxBdRing[RingIndex].ChanBase, - XAXIDMA_DESTADDR_OFFSET, BuffAddr); + XAXIDMA_DESTADDR_OFFSET, LOWER_32_BITS(BuffAddr)); + if (InstancePtr->AddrWidth > 32) + XAxiDma_WriteReg(InstancePtr->RxBdRing[RingIndex].ChanBase, + XAXIDMA_DESTADDR_MSB_OFFSET, + UPPER_32_BITS(BuffAddr)); XAxiDma_WriteReg(InstancePtr->RxBdRing[RingIndex].ChanBase, XAXIDMA_CR_OFFSET, diff --git a/XilinxProcessorIPLib/drivers/axidma/src/xaxidma.h b/XilinxProcessorIPLib/drivers/axidma/src/xaxidma.h index 38658b0a..0ad2366f 100644 --- a/XilinxProcessorIPLib/drivers/axidma/src/xaxidma.h +++ b/XilinxProcessorIPLib/drivers/axidma/src/xaxidma.h @@ -451,6 +451,7 @@ * test example to include it on peripheral test's(CR#823144). * 8.1 adk 29/01/15 Added the sefltest api (XAxiDma_Selftest) to the driver source files * (xaxidma_selftest.c) and called this from the selftest example +* 9.0 adk 27/07/15 Added support for 64-bit Addressing. * * * @@ -494,6 +495,7 @@ typedef struct XAxiDma { int TxNumChannels; int RxNumChannels; int MicroDmaMode; + int AddrWidth; /**< Address Width */ } XAxiDma; /** @@ -518,6 +520,7 @@ typedef struct { int Mm2SBurstSize; int S2MmBurstSize; int MicroDmaMode; + int AddrWidth; /**< Address Width */ } XAxiDma_Config; @@ -723,7 +726,7 @@ int XAxiDma_ResetIsDone(XAxiDma * InstancePtr); int XAxiDma_Pause(XAxiDma * InstancePtr); int XAxiDma_Resume(XAxiDma * InstancePtr); u32 XAxiDma_Busy(XAxiDma *InstancePtr,int Direction); -int XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, u32 BuffAddr, u32 Length, +u32 XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, UINTPTR BuffAddr, u32 Length, int Direction); int XAxiDma_SelectKeyHole(XAxiDma *InstancePtr, int Direction, int Select); int XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr, int Direction, int Select); diff --git a/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bd.c b/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bd.c index 8c3e2822..44782e2f 100644 --- a/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bd.c +++ b/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bd.c @@ -124,13 +124,16 @@ int XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr, u32 LenBytes, u32 LengthMask) * @note This function can be used only when DMA is in SG mode * *****************************************************************************/ -int XAxiDma_BdSetBufAddr(XAxiDma_Bd* BdPtr, u32 Addr) +u32 XAxiDma_BdSetBufAddr(XAxiDma_Bd* BdPtr, UINTPTR Addr) { u32 HasDRE; u8 WordLen; + u32 Addrlen; HasDRE = XAxiDma_BdRead(BdPtr, XAXIDMA_BD_HAS_DRE_OFFSET); WordLen = HasDRE & XAXIDMA_BD_WORDLEN_MASK; + Addrlen = XAxiDma_BdRead(BdPtr, XAXIDMA_BD_ADDRLEN_OFFSET); + if (Addr & (WordLen - 1)) { if ((HasDRE & XAXIDMA_BD_HAS_DRE_MASK) == 0) { @@ -142,10 +145,12 @@ int XAxiDma_BdSetBufAddr(XAxiDma_Bd* BdPtr, u32 Addr) } } - XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_OFFSET, Addr); + XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_OFFSET, LOWER_32_BITS(Addr)); + if (Addrlen) + XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_MSB_OFFSET, + UPPER_32_BITS(Addr)); return XST_SUCCESS; - } /*****************************************************************************/ @@ -164,8 +169,11 @@ int XAxiDma_BdSetBufAddr(XAxiDma_Bd* BdPtr, u32 Addr) * @note This function can be used only when DMA is in SG mode * *****************************************************************************/ -int XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd* BdPtr, u32 Addr) +u32 XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd* BdPtr, UINTPTR Addr) { + u32 Addrlen; + Addrlen = XAxiDma_BdRead(BdPtr, XAXIDMA_BD_ADDRLEN_OFFSET); + if (Addr & XAXIDMA_MICROMODE_MIN_BUF_ALIGN) { xil_printf("Error set buf addr %x and %x," " %x\r\n", Addr, XAXIDMA_MICROMODE_MIN_BUF_ALIGN, @@ -174,7 +182,11 @@ int XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd* BdPtr, u32 Addr) return XST_INVALID_PARAM; } - XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_OFFSET, Addr); + XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_OFFSET, + LOWER_32_BITS(Addr)); + if (Addrlen) + XAxiDma_BdWrite(BdPtr, XAXIDMA_BD_BUFA_MSB_OFFSET, + UPPER_32_BITS(Addr)); return XST_SUCCESS; } @@ -303,7 +315,7 @@ void XAxiDma_BdSetCtrl(XAxiDma_Bd* BdPtr, u32 Data) void XAxiDma_DumpBd(XAxiDma_Bd* BdPtr) { - xil_printf("Dump BD %x:\r\n", (unsigned int)BdPtr); + xil_printf("Dump BD %x:\r\n", (UINTPTR)BdPtr); xil_printf("\tNext Bd Ptr: %x\r\n", (unsigned int)XAxiDma_BdRead(BdPtr, XAXIDMA_BD_NDESC_OFFSET)); xil_printf("\tBuff addr: %x\r\n", diff --git a/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bd.h b/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bd.h index d796196b..dd7e5b60 100644 --- a/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bd.h +++ b/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bd.h @@ -132,7 +132,7 @@ extern "C" { * The XAxiDma_Bd is the type for a buffer descriptor (BD). */ -typedef u32 XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]; +typedef UINTPTR XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]; /***************** Macros (Inline Functions) Definitions *********************/ @@ -141,11 +141,16 @@ typedef u32 XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]; * Define methods to flush and invalidate cache for BDs should they be * located in cached memory. *****************************************************************************/ +#ifdef __aarch64__ +#define XAXIDMA_CACHE_FLUSH(BdPtr) +#define XAXIDMA_CACHE_INVALIDATE(BdPtr) +#else #define XAXIDMA_CACHE_FLUSH(BdPtr) \ - Xil_DCacheFlushRange((unsigned int)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES) + Xil_DCacheFlushRange((UINTPTR)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES) #define XAXIDMA_CACHE_INVALIDATE(BdPtr) \ - Xil_DCacheInvalidateRange((unsigned int)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES) + Xil_DCacheInvalidateRange((UINTPTR)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES) +#endif /*****************************************************************************/ /** @@ -163,7 +168,7 @@ typedef u32 XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]; * ******************************************************************************/ #define XAxiDma_BdRead(BaseAddress, Offset) \ - (*(u32*)((u32)(BaseAddress) + (u32)(Offset))) + (*(u32 *)((UINTPTR)((void *)(BaseAddress)) + (u32)(Offset))) /*****************************************************************************/ /** @@ -182,7 +187,7 @@ typedef u32 XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]; * ******************************************************************************/ #define XAxiDma_BdWrite(BaseAddress, Offset, Data) \ - (*(u32*)((u32)(BaseAddress) + (u32)(Offset)) = (Data)) + (*(u32 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u32)(Data) /*****************************************************************************/ /** @@ -199,7 +204,7 @@ typedef u32 XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]; * *****************************************************************************/ #define XAxiDma_BdClear(BdPtr) \ - memset((void *)(((u32)(BdPtr)) + XAXIDMA_BD_START_CLEAR), 0, \ + memset((void *)(((UINTPTR)(BdPtr)) + XAXIDMA_BD_START_CLEAR), 0, \ XAXIDMA_BD_BYTES_TO_CLEAR) /*****************************************************************************/ @@ -656,8 +661,8 @@ typedef u32 XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]; /************************** Function Prototypes ******************************/ int XAxiDma_BdSetLength(XAxiDma_Bd* BdPtr, u32 LenBytes, u32 LengthMask); -int XAxiDma_BdSetBufAddr(XAxiDma_Bd* BdPtr, u32 Addr); -int XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd* BdPtr, u32 Addr); +u32 XAxiDma_BdSetBufAddr(XAxiDma_Bd* BdPtr, UINTPTR Addr); +u32 XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd* BdPtr, UINTPTR Addr); int XAxiDma_BdSetAppWord(XAxiDma_Bd * BdPtr, int Offset, u32 Word); u32 XAxiDma_BdGetAppWord(XAxiDma_Bd * BdPtr, int Offset, int *Valid); void XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data); diff --git a/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bdring.c b/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bdring.c index 88734177..6eacbdd6 100644 --- a/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bdring.c +++ b/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bdring.c @@ -101,7 +101,7 @@ * *****************************************************************************/ #define XAXIDMA_VIRT_TO_PHYS(BdPtr) \ - ((u32)(BdPtr) + (RingPtr->FirstBdPhysAddr - RingPtr->FirstBdAddr)) + ((UINTPTR)(BdPtr) + (RingPtr->FirstBdPhysAddr - RingPtr->FirstBdAddr)) /****************************************************************************** * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around @@ -123,15 +123,15 @@ *****************************************************************************/ #define XAXIDMA_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \ { \ - u32 Addr = (u32)(BdPtr); \ + UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \ \ Addr += ((RingPtr)->Separation * (NumBd)); \ - if ((Addr > (RingPtr)->LastBdAddr) || ((u32)(BdPtr) > Addr)) \ + if ((Addr > (RingPtr)->LastBdAddr) || ((UINTPTR)(BdPtr) > Addr)) \ { \ Addr -= (RingPtr)->Length; \ } \ \ - (BdPtr) = (XAxiDma_Bd*)Addr; \ + (BdPtr) = (XAxiDma_Bd*)(void *)Addr; \ } /****************************************************************************** * Move the BdPtr argument backwards an arbitrary number of BDs wrapping @@ -153,10 +153,10 @@ *****************************************************************************/ #define XAXIDMA_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \ { \ - u32 Addr = (u32)(BdPtr); \ + UINTPTR Addr = (UINTPTR)(BdPtr); \ \ Addr -= ((RingPtr)->Separation * (NumBd)); \ - if ((Addr < (RingPtr)->FirstBdAddr) || ((u32)(BdPtr) < Addr)) \ + if ((Addr < (RingPtr)->FirstBdAddr) || ((UINTPTR)(BdPtr) < Addr)) \ { \ Addr += (RingPtr)->Length; \ } \ @@ -186,7 +186,7 @@ int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr) { u32 RegBase; - XAxiDma_Bd *BdPtr; + UINTPTR BdPtr; int RingIndex = RingPtr->RingIndex; /* BD list has yet to be created for this channel */ @@ -214,24 +214,38 @@ int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr) /* Put a valid BD pointer in the current BD pointer register * So, the hardware is ready to go when tail BD pointer is updated */ - BdPtr = (XAxiDma_Bd *)RingPtr->BdaRestart; + BdPtr = (UINTPTR)(void *)(RingPtr->BdaRestart); if (!XAxiDma_BdHwCompleted(BdPtr)) { if (RingPtr->IsRxChannel) { if (!RingIndex) { XAxiDma_WriteReg(RegBase, - XAXIDMA_CDESC_OFFSET, (u32)BdPtr); + XAXIDMA_CDESC_OFFSET, + (u32)(BdPtr & XAXIDMA_DESC_LSB_MASK)); + if (RingPtr->Addr_ext) + XAxiDma_WriteReg(RegBase, + XAXIDMA_CDESC_MSB_OFFSET, + UPPER_32_BITS(BdPtr)); } else { XAxiDma_WriteReg(RegBase, (XAXIDMA_RX_CDESC0_OFFSET + (RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), - (u32)BdPtr); + (u32)(BdPtr & XAXIDMA_DESC_LSB_MASK)); + if (RingPtr->Addr_ext) + XAxiDma_WriteReg(RegBase, + (XAXIDMA_RX_CDESC0_MSB_OFFSET + + (RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), + UPPER_32_BITS(BdPtr)); } } else { - XAxiDma_WriteReg(RegBase, XAXIDMA_CDESC_OFFSET, - (u32)BdPtr); + XAxiDma_WriteReg(RegBase, + XAXIDMA_CDESC_OFFSET, + (u32)(BdPtr & XAXIDMA_DESC_LSB_MASK)); + if (RingPtr->Addr_ext) + XAxiDma_WriteReg(RegBase, XAXIDMA_CDESC_MSB_OFFSET, + UPPER_32_BITS(BdPtr)); } } else { @@ -240,7 +254,7 @@ int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr) while (XAxiDma_BdHwCompleted(BdPtr)) { BdPtr = XAxiDma_BdRingNext(RingPtr, BdPtr); - if ((u32)BdPtr == (u32) RingPtr->BdaRestart) { + if ((UINTPTR)BdPtr == (UINTPTR) RingPtr->BdaRestart) { xdbg_printf(XDBG_DEBUG_ERROR, "StartBdRingHw: Cannot find valid cdesc\r\n"); @@ -251,19 +265,29 @@ int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr) if (RingPtr->IsRxChannel) { if (!RingIndex) { XAxiDma_WriteReg(RegBase, - XAXIDMA_CDESC_OFFSET, (u32)BdPtr); + XAXIDMA_CDESC_OFFSET,(u32) (BdPtr & XAXIDMA_DESC_LSB_MASK)); + if (RingPtr->Addr_ext) + XAxiDma_WriteReg(RegBase, XAXIDMA_CDESC_MSB_OFFSET, + UPPER_32_BITS(BdPtr)); } else { XAxiDma_WriteReg(RegBase, - (XAXIDMA_RX_CDESC0_OFFSET + - (RingIndex - 1) * - XAXIDMA_RX_NDESC_OFFSET), - (u32)BdPtr); + (XAXIDMA_RX_CDESC0_OFFSET + + (RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), + (u32)(BdPtr & XAXIDMA_DESC_LSB_MASK)); + if (RingPtr->Addr_ext) + XAxiDma_WriteReg(RegBase, + (XAXIDMA_RX_CDESC0_MSB_OFFSET + + (RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), + UPPER_32_BITS(BdPtr)); } } else { XAxiDma_WriteReg(RegBase, - XAXIDMA_CDESC_OFFSET, (u32)BdPtr); + XAXIDMA_CDESC_OFFSET, (u32)(BdPtr & XAXIDMA_DESC_LSB_MASK)); + if (RingPtr->Addr_ext) + XAxiDma_WriteReg(RegBase, XAXIDMA_CDESC_MSB_OFFSET, + UPPER_32_BITS(BdPtr)); } break; } @@ -315,12 +339,12 @@ int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr) * @note This function can be used only when DMA is in SG mode * *****************************************************************************/ -int XAxiDma_BdRingCreate(XAxiDma_BdRing *RingPtr, u32 PhysAddr, - u32 VirtAddr, u32 Alignment, int BdCount) +u32 XAxiDma_BdRingCreate(XAxiDma_BdRing *RingPtr, UINTPTR PhysAddr, + UINTPTR VirtAddr, u32 Alignment, int BdCount) { int i; - u32 BdVirtAddr; - u32 BdPhysAddr; + UINTPTR BdVirtAddr; + UINTPTR BdPhysAddr; if (BdCount <= 0) { @@ -395,8 +419,12 @@ int XAxiDma_BdRingCreate(XAxiDma_BdRing *RingPtr, u32 PhysAddr, BdVirtAddr = VirtAddr; BdPhysAddr = PhysAddr + RingPtr->Separation; for (i = 1; i < BdCount; i++) { + XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_ADDRLEN_OFFSET, + RingPtr->Addr_ext); XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_NDESC_OFFSET, - BdPhysAddr); + (BdPhysAddr & XAXIDMA_DESC_LSB_MASK)); + XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_NDESC_MSB_OFFSET, + UPPER_32_BITS(BdPhysAddr)); /* Put hardware information in the BDs */ @@ -413,7 +441,13 @@ int XAxiDma_BdRingCreate(XAxiDma_BdRing *RingPtr, u32 PhysAddr, } /* At the end of the ring, link the last BD back to the top */ - XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_NDESC_OFFSET, PhysAddr); + XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_ADDRLEN_OFFSET, + RingPtr->Addr_ext); + XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_NDESC_OFFSET, + (PhysAddr & XAXIDMA_DESC_LSB_MASK)); + XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_NDESC_MSB_OFFSET, + UPPER_32_BITS(PhysAddr)); + /* Setup the last BD's hardware information */ XAxiDma_BdWrite(BdVirtAddr, XAXIDMA_BD_HAS_STSCNTRL_OFFSET, @@ -469,7 +503,7 @@ int XAxiDma_BdRingCreate(XAxiDma_BdRing *RingPtr, u32 PhysAddr, int XAxiDma_BdRingClone(XAxiDma_BdRing * RingPtr, XAxiDma_Bd * SrcBdPtr) { int i; - u32 CurBd; + UINTPTR CurBd; u32 Save; XAxiDma_Bd TmpBd; @@ -511,8 +545,8 @@ int XAxiDma_BdRingClone(XAxiDma_BdRing * RingPtr, XAxiDma_Bd * SrcBdPtr) for (i = 0, CurBd = RingPtr->FirstBdAddr; i < RingPtr->AllCnt; i++, CurBd += RingPtr->Separation) { - memcpy((void *)((u32)CurBd + XAXIDMA_BD_START_CLEAR), - (void *)((u32)(&TmpBd) + XAXIDMA_BD_START_CLEAR), + memcpy((void *)((UINTPTR)CurBd + XAXIDMA_BD_START_CLEAR), + (void *)((UINTPTR)(&TmpBd) + XAXIDMA_BD_START_CLEAR), XAXIDMA_BD_BYTES_TO_CLEAR); XAXIDMA_CACHE_FLUSH(CurBd); @@ -571,20 +605,29 @@ int XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr) if (RingPtr->IsRxChannel) { if (!RingIndex) { XAxiDma_WriteReg(RingPtr->ChanBase, - XAXIDMA_TDESC_OFFSET, - XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)); + XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK)); + if (RingPtr->Addr_ext) + XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET, + UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail))); } else { XAxiDma_WriteReg(RingPtr->ChanBase, - (XAXIDMA_RX_TDESC0_OFFSET + - (RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), - XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)); + (XAXIDMA_RX_TDESC0_OFFSET + + (RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), + (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK )); + if (RingPtr->Addr_ext) + XAxiDma_WriteReg(RingPtr->ChanBase, + (XAXIDMA_RX_TDESC0_MSB_OFFSET + + (RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), + UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail))); } } else { XAxiDma_WriteReg(RingPtr->ChanBase, - XAXIDMA_TDESC_OFFSET, - XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)); + XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK)); + if (RingPtr->Addr_ext) + XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET, + UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail))); } } } @@ -1028,7 +1071,7 @@ int XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr, int NumBd, /* Flush the current BD so DMA core could see the updates */ XAXIDMA_CACHE_FLUSH(CurBdPtr); - CurBdPtr = XAxiDma_BdRingNext(RingPtr, CurBdPtr); + CurBdPtr = (XAxiDma_Bd *)((void *)XAxiDma_BdRingNext(RingPtr, CurBdPtr)); BdCr = XAxiDma_BdRead(CurBdPtr, XAXIDMA_BD_CTRL_LEN_OFFSET); BdSts = XAxiDma_BdRead(CurBdPtr, XAXIDMA_BD_STS_OFFSET); } @@ -1073,21 +1116,29 @@ int XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr, int NumBd, if (RingPtr->IsRxChannel) { if (!RingIndex) { XAxiDma_WriteReg(RingPtr->ChanBase, - XAXIDMA_TDESC_OFFSET, - XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)); + XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK)); + if (RingPtr->Addr_ext) + XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET, + UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail))); } else { XAxiDma_WriteReg(RingPtr->ChanBase, - (XAXIDMA_RX_TDESC0_OFFSET + - (RingIndex - 1) * - XAXIDMA_RX_NDESC_OFFSET), - XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)); + (XAXIDMA_RX_TDESC0_OFFSET + + (RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), + (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK )); + if (RingPtr->Addr_ext) + XAxiDma_WriteReg(RingPtr->ChanBase, + (XAXIDMA_RX_TDESC0_MSB_OFFSET + + (RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET), + UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail))); } } else { XAxiDma_WriteReg(RingPtr->ChanBase, - XAXIDMA_TDESC_OFFSET, - XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)); + XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK)); + if (RingPtr->Addr_ext) + XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET, + UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail))); } } @@ -1239,7 +1290,7 @@ int XAxiDma_BdRingFromHw(XAxiDma_BdRing * RingPtr, int BdLimit, } /* Move on to the next BD in work group */ - CurBdPtr = XAxiDma_BdRingNext(RingPtr, CurBdPtr); + CurBdPtr = (XAxiDma_Bd *)((void *)XAxiDma_BdRingNext(RingPtr, CurBdPtr)); } /* Subtract off any partial packet BDs found */ @@ -1309,8 +1360,8 @@ int XAxiDma_BdRingFree(XAxiDma_BdRing * RingPtr, int NumBd, xdbg_printf(XDBG_DEBUG_ERROR, "BdRingFree: Error free BDs: " "post count %d to free %d, PostHead %x to free ptr %x\r\n", RingPtr->PostCnt, NumBd, - (unsigned int)RingPtr->PostHead, - (unsigned int)BdSetPtr); + (UINTPTR)RingPtr->PostHead, + (UINTPTR)BdSetPtr); return XST_DMA_SG_LIST_ERROR; } @@ -1382,7 +1433,7 @@ int XAxiDma_BdRingCheck(XAxiDma_BdRing * RingPtr) } /* Verify internal pointers point to correct memory space */ - AddrV = (u32) RingPtr->FreeHead; + AddrV = (UINTPTR) RingPtr->FreeHead; if ((AddrV < RingPtr->FirstBdAddr) || (AddrV > RingPtr->LastBdAddr)) { xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: FreeHead wrong " @@ -1394,7 +1445,7 @@ int XAxiDma_BdRingCheck(XAxiDma_BdRing * RingPtr) return XST_DMA_SG_LIST_ERROR; } - AddrV = (u32) RingPtr->PreHead; + AddrV = (UINTPTR) RingPtr->PreHead; if ((AddrV < RingPtr->FirstBdAddr) || (AddrV > RingPtr->LastBdAddr)) { xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: PreHead wrong %x, " @@ -1406,7 +1457,7 @@ int XAxiDma_BdRingCheck(XAxiDma_BdRing * RingPtr) return XST_DMA_SG_LIST_ERROR; } - AddrV = (u32) RingPtr->HwHead; + AddrV = (UINTPTR) RingPtr->HwHead; if ((AddrV < RingPtr->FirstBdAddr) || (AddrV > RingPtr->LastBdAddr)) { xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: HwHead wrong %x, " @@ -1418,7 +1469,7 @@ int XAxiDma_BdRingCheck(XAxiDma_BdRing * RingPtr) return XST_DMA_SG_LIST_ERROR; } - AddrV = (u32) RingPtr->HwTail; + AddrV = (UINTPTR) RingPtr->HwTail; if ((AddrV < RingPtr->FirstBdAddr) || (AddrV > RingPtr->LastBdAddr)) { xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: HwTail wrong %x, " @@ -1430,7 +1481,7 @@ int XAxiDma_BdRingCheck(XAxiDma_BdRing * RingPtr) return XST_DMA_SG_LIST_ERROR; } - AddrV = (u32) RingPtr->PostHead; + AddrV = (UINTPTR) RingPtr->PostHead; if ((AddrV < RingPtr->FirstBdAddr) || (AddrV > RingPtr->LastBdAddr)) { xdbg_printf(XDBG_DEBUG_ERROR, "BdRingCheck: PostHead wrong " diff --git a/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bdring.h b/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bdring.h index 3cced9d0..3a4c87b3 100644 --- a/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bdring.h +++ b/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bdring.h @@ -112,13 +112,14 @@ typedef struct { int HasStsCntrlStrm; /**< Whether has stscntrl stream */ int HasDRE; int DataWidth; + int Addr_ext; u32 MaxTransferLen; - u32 FirstBdPhysAddr; /**< Physical address of 1st BD in list */ - u32 FirstBdAddr; /**< Virtual address of 1st BD in list */ - u32 LastBdAddr; /**< Virtual address of last BD in the list */ + UINTPTR FirstBdPhysAddr; /**< Physical address of 1st BD in list */ + UINTPTR FirstBdAddr; /**< Virtual address of 1st BD in list */ + UINTPTR LastBdAddr; /**< Virtual address of last BD in the list */ u32 Length; /**< Total size of ring in bytes */ - u32 Separation; /**< Number of bytes between the starting + UINTPTR Separation; /**< Number of bytes between the starting address of adjacent BDs */ XAxiDma_Bd *FreeHead; /**< First BD in the free group */ XAxiDma_Bd *PreHead; /**< First BD in the pre-work group */ @@ -157,7 +158,7 @@ typedef struct { * ******************************************************************************/ #define XAxiDma_BdRingCntCalc(Alignment, Bytes) \ - (int)((Bytes)/((sizeof(XAxiDma_Bd)+((Alignment)-1))&~((Alignment)-1))) + (uint32_t)((Bytes)/((sizeof(XAxiDma_Bd)+((Alignment)-1))&~((Alignment)-1))) /*****************************************************************************/ /** @@ -235,17 +236,17 @@ typedef struct { { \ if (!RingPtr->IsRxChannel) { \ (RingPtr)->BdaRestart = \ - (XAxiDma_Bd *)XAxiDma_ReadReg((RingPtr)->ChanBase, \ + XAxiDma_ReadReg((RingPtr)->ChanBase, \ XAXIDMA_CDESC_OFFSET); \ } else { \ if (!RingPtr->RingIndex) { \ (RingPtr)->BdaRestart = \ - (XAxiDma_Bd *)XAxiDma_ReadReg( \ + XAxiDma_ReadReg( \ (RingPtr)->ChanBase, \ XAXIDMA_CDESC_OFFSET); \ } else { \ (RingPtr)->BdaRestart = \ - (XAxiDma_Bd *)XAxiDma_ReadReg( \ + XAxiDma_ReadReg( \ (RingPtr)->ChanBase, \ (XAXIDMA_RX_CDESC0_OFFSET + \ (RingPtr->RingIndex - 1) * \ @@ -289,9 +290,9 @@ typedef struct { * *****************************************************************************/ #define XAxiDma_BdRingNext(RingPtr, BdPtr) \ - (((u32)(BdPtr) >= (RingPtr)->LastBdAddr) ? \ - (XAxiDma_Bd*)(RingPtr)->FirstBdAddr : \ - (XAxiDma_Bd*)((u32)(BdPtr) + (RingPtr)->Separation)) + (((UINTPTR)(BdPtr) >= (RingPtr)->LastBdAddr) ? \ + (UINTPTR)(RingPtr)->FirstBdAddr : \ + (UINTPTR)((UINTPTR)(BdPtr) + (RingPtr)->Separation)) /****************************************************************************/ /** @@ -495,8 +496,8 @@ typedef struct { */ int XAxiDma_StartBdRingHw(XAxiDma_BdRing* RingPtr); int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr); -int XAxiDma_BdRingCreate(XAxiDma_BdRing * RingPtr, u32 PhysAddr, - u32 VirtAddr, u32 Alignment, int BdCount); +u32 XAxiDma_BdRingCreate(XAxiDma_BdRing * RingPtr, UINTPTR PhysAddr, + UINTPTR VirtAddr, u32 Alignment, int BdCount); int XAxiDma_BdRingClone(XAxiDma_BdRing * RingPtr, XAxiDma_Bd * SrcBdPtr); int XAxiDma_BdRingAlloc(XAxiDma_BdRing * RingPtr, int NumBd, XAxiDma_Bd ** BdSetPtr); diff --git a/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_hw.h b/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_hw.h index 038fff50..a1d5bc6c 100644 --- a/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_hw.h +++ b/XilinxProcessorIPLib/drivers/axidma/src/xaxidma_hw.h @@ -116,19 +116,26 @@ extern "C" { * XAXIDMA_TX_OFFSET to get to TX channel, and XAXIDMA_RX_OFFSET to get to RX * channel */ -#define XAXIDMA_CR_OFFSET 0x00000000 /**< Channel control */ -#define XAXIDMA_SR_OFFSET 0x00000004 /**< Status */ -#define XAXIDMA_CDESC_OFFSET 0x00000008 /**< Current descriptor pointer */ -#define XAXIDMA_TDESC_OFFSET 0x00000010 /**< Tail descriptor pointer */ -#define XAXIDMA_SRCADDR_OFFSET 0x00000018 /**< Simple mode source address +#define XAXIDMA_CR_OFFSET 0x00000000 /**< Channel control */ +#define XAXIDMA_SR_OFFSET 0x00000004 /**< Status */ +#define XAXIDMA_CDESC_OFFSET 0x00000008 /**< Current descriptor pointer */ +#define XAXIDMA_CDESC_MSB_OFFSET 0x0000000C /**< Current descriptor pointer */ +#define XAXIDMA_TDESC_OFFSET 0x00000010 /**< Tail descriptor pointer */ +#define XAXIDMA_TDESC_MSB_OFFSET 0x00000014 /**< Tail descriptor pointer */ +#define XAXIDMA_SRCADDR_OFFSET 0x00000018 /**< Simple mode source address pointer */ -#define XAXIDMA_DESTADDR_OFFSET 0x00000018 /**< Simple mode destination address pointer */ -#define XAXIDMA_BUFFLEN_OFFSET 0x00000028 /**< Tail descriptor pointer */ -#define XAXIDMA_SGCTL_OFFSET 0x0000002c /**< SG Control Register */ +#define XAXIDMA_SRCADDR_MSB_OFFSET 0x0000001C /**< Simple mode source address + pointer */ +#define XAXIDMA_DESTADDR_OFFSET 0x00000018 /**< Simple mode destination address pointer */ +#define XAXIDMA_DESTADDR_MSB_OFFSET 0x0000001C /**< Simple mode destination address pointer */ +#define XAXIDMA_BUFFLEN_OFFSET 0x00000028 /**< Tail descriptor pointer */ +#define XAXIDMA_SGCTL_OFFSET 0x0000002c /**< SG Control Register */ /** Multi-Channel DMA Descriptor Offsets **/ #define XAXIDMA_RX_CDESC0_OFFSET 0x00000040 /**< Rx Current Descriptor 0 */ +#define XAXIDMA_RX_CDESC0_MSB_OFFSET 0x00000044 /**< Rx Current Descriptor 0 */ #define XAXIDMA_RX_TDESC0_OFFSET 0x00000048 /**< Rx Tail Descriptor 0 */ +#define XAXIDMA_RX_TDESC0_MSB_OFFSET 0x0000004C /**< Rx Tail Descriptor 0 */ #define XAXIDMA_RX_NDESC_OFFSET 0x00000020 /**< Rx Next Descriptor Offset */ /*@}*/ @@ -200,7 +207,9 @@ extern "C" { * @{ */ #define XAXIDMA_BD_NDESC_OFFSET 0x00 /**< Next descriptor pointer */ +#define XAXIDMA_BD_NDESC_MSB_OFFSET 0x04 /**< Next descriptor pointer */ #define XAXIDMA_BD_BUFA_OFFSET 0x08 /**< Buffer address */ +#define XAXIDMA_BD_BUFA_MSB_OFFSET 0x0C /**< Buffer address */ #define XAXIDMA_BD_MCCTL_OFFSET 0x10 /**< Multichannel Control Fields */ #define XAXIDMA_BD_STRIDE_VSIZE_OFFSET 0x14 /**< 2D Transfer Sizes */ #define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /**< Control/buffer length */ @@ -215,6 +224,7 @@ extern "C" { #define XAXIDMA_BD_ID_OFFSET 0x34 /**< Sw ID */ #define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /**< Whether has stscntrl strm */ #define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /**< Whether has DRE */ +#define XAXIDMA_BD_ADDRLEN_OFFSET 0x40 /**< Check for BD Addr */ #define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /**< Whether has DRE mask */ #define XAXIDMA_BD_WORDLEN_MASK 0xFF /**< Whether has DRE mask */ @@ -226,7 +236,7 @@ extern "C" { #define XAXIDMA_BD_BYTES_TO_CLEAR 48 /**< BD specific bytes to be * cleared */ -#define XAXIDMA_BD_NUM_WORDS 16 /**< Total number of words for +#define XAXIDMA_BD_NUM_WORDS 16U /**< Total number of words for * one BD*/ #define XAXIDMA_BD_HW_NUM_BYTES 52 /**< Number of bytes hw used */ @@ -235,7 +245,7 @@ extern "C" { #define XAXIDMA_LAST_APPWORD 4 /*@}*/ - +#define XAXIDMA_DESC_LSB_MASK (0xFFFFFFC0U) /**< LSB Address mask */ /** @name Bitmasks of XAXIDMA_BD_CTRL_OFFSET register * @{