From 19360973a68a05e2098dfe7461d6cdcf6ebe93c1 Mon Sep 17 00:00:00 2001 From: Venkata Naga Sai Krishna Kolapalli Date: Thu, 16 Apr 2015 12:36:53 +0530 Subject: [PATCH] gpiops_v3_1 : Add support for Zynq Ultrascale+ MP. This patch adds support for Zynq Ultrascale+ MP for driver source files. Signed-off-by: Venkata Naga Sai Krishna Kolapalli --- .../drivers/gpiops/src/xgpiops.c | 163 ++++++++++-------- .../drivers/gpiops/src/xgpiops.h | 25 +-- .../drivers/gpiops/src/xgpiops_hw.c | 45 +++-- .../drivers/gpiops/src/xgpiops_intr.c | 59 +++---- 4 files changed, 163 insertions(+), 129 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.c b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.c index 07db4043..ac52207a 100644 --- a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.c +++ b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.c @@ -49,6 +49,7 @@ * for output pins on all banks during initialization. * 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667. * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980. * * * @@ -95,6 +96,7 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr, u32 EffectiveAddr) { s32 Status = XST_SUCCESS; + u8 i; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(ConfigPtr != NULL); Xil_AssertNonvoid(EffectiveAddr != (u32)0); @@ -106,25 +108,42 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr, InstancePtr->GpioConfig.BaseAddr = EffectiveAddr; InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId; InstancePtr->Handler = StubHandler; + InstancePtr->Platform = XGetPlatform_Info(); + + /* Initialize the Bank data based on platform */ + if (InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) { + /* + * Max pins in the ZynqMP GPIO device + * 0 - 25, Bank 0 + * 26 - 51, Bank 1 + * 52 - 77, Bank 2 + * 78 - 109, Bank 3 + * 110 - 141, Bank 4 + * 142 - 173, Bank 5 + */ + InstancePtr->MaxPinNum = (u32)174; + InstancePtr->MaxBanks = (u8)6; + } else { + /* + * Max pins in the GPIO device + * 0 - 31, Bank 0 + * 32 - 53, Bank 1 + * 54 - 85, Bank 2 + * 86 - 117, Bank 3 + */ + InstancePtr->MaxPinNum = (u32)118; + InstancePtr->MaxBanks = (u8)4; + } /* * By default, interrupts are not masked in GPIO. Disable * interrupts for all pins in all the 4 banks. */ - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((u32)(1) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((u32)(2) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((u32)(3) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU); + for (i=0;iMaxBanks;i++) { + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU); + } /* * Indicate the component is now ready to use. @@ -141,7 +160,7 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr, * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. * * @return Current value of the Data register. * @@ -153,7 +172,7 @@ u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS); + Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks); return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) + @@ -167,7 +186,7 @@ u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Pin is the pin number for which the data has to be read. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. * See xgpiops.h for the mapping of the pin numbers in the banks. * * @return Current value of the Pin (0 or 1). @@ -183,7 +202,7 @@ u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); + Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); /* * Get the Bank number and Pin number within the bank. @@ -203,7 +222,7 @@ u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. * @param Data is the value to be written to the Data register. * * @return None. @@ -216,7 +235,7 @@ void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) + @@ -230,7 +249,7 @@ void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Pin is the pin number to which the Data is to be written. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. * @param Data is the data to be written to the specified pin (0 or 1). * * @return None. @@ -250,7 +269,7 @@ void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data) Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); + Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); /* * Get the Bank number and Pin number within the bank. @@ -287,7 +306,7 @@ void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. * @param Direction is the 32 bit mask of the Pin direction to be set for * all the pins in the Bank. Bits with 0 are set to Input mode, * bits with 1 are set to Output Mode. @@ -303,7 +322,7 @@ void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + @@ -317,7 +336,7 @@ void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Pin is the pin number to which the Data is to be written. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. * @param Direction is the direction to be set for the specified pin. * Valid values are 0 for Input Direction, 1 for Output Direction. * @@ -332,7 +351,7 @@ void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction) Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); + Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); Xil_AssertVoid(Direction <= (u32)1); /* @@ -362,7 +381,7 @@ void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. * * return Returns a 32 bit mask of the Direction register. Bits with 0 are * in Input mode, bits with 1 are in Output Mode. @@ -374,7 +393,7 @@ u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS); + Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks); return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + @@ -389,7 +408,7 @@ u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank) * @param InstancePtr is a pointer to the XGpioPs instance. * @param Pin is the pin number for which the Direction is to be * retrieved. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. * * @return Direction of the specified pin. * - 0 for Input Direction @@ -405,7 +424,7 @@ u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); + Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); /* * Get the Bank number and Pin number within the bank. @@ -424,7 +443,7 @@ u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. * @param OpEnable is the 32 bit mask of the Output Enables to be set for * all the pins in the Bank. The Output Enable of bits with 0 are * disabled, the Output Enable of bits with 1 are enabled. @@ -440,7 +459,7 @@ void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + @@ -454,7 +473,7 @@ void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Pin is the pin number to which the Data is to be written. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. * @param OpEnable specifies whether the Output Enable for the specified * pin should be enabled. * Valid values are 0 for Disabling Output Enable, @@ -473,7 +492,7 @@ void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable) Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); + Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); Xil_AssertVoid(OpEnable <= (u32)1); /* @@ -502,7 +521,7 @@ void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. * * return Returns a a 32 bit mask of the Output Enable register. * Bits with 0 are in Disabled state, bits with 1 are in @@ -515,7 +534,7 @@ u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS); + Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks); return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + @@ -530,7 +549,7 @@ u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank) * @param InstancePtr is a pointer to the XGpioPs instance. * @param Pin is the pin number for which the Output Enable status is to * be retrieved. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. * * @return Output Enable of the specified pin. * - 0 if Output Enable is disabled for this pin @@ -546,7 +565,7 @@ u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); + Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); /* * Get the Bank number and Pin number within the bank. @@ -576,41 +595,43 @@ u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin) *****************************************************************************/ void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank) { - /* - * This structure defines the mapping of the pin numbers to the banks when - * the driver APIs are used for working on the individual pins. - */ -#ifdef XPAR_PSU_GPIO_0_BASEADDR - u32 XGpioPsPinTable[] = { - (u32)25, /* 0 - 25, Bank 0 */ - (u32)51, /* 26 - 51, Bank 1 */ - (u32)77, /* 52 - 77, Bank 2 */ - (u32)109, /* 78 - 109, Bank 3 */ - (u32)141, /* 110 - 141, Bank 4 */ - (u32)173 /* 142 - 173 Bank 5 */ - }; - *BankNumber = 0U; - while (*BankNumber < 6U) { - if (PinNumber <= XGpioPsPinTable[*BankNumber]) { - break; - } - (*BankNumber)++; + u32 XGpioPsPinTable[6] = {0}; + u32 Platform = XGetPlatform_Info(); + + if (Platform == XPLAT_ZYNQ_ULTRA_MP) { + /* + * This structure defines the mapping of the pin numbers to the banks when + * the driver APIs are used for working on the individual pins. + */ + + XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */ + XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */ + XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */ + XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */ + XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */ + XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */ + + *BankNumber = 0U; + while (*BankNumber < 6U) { + if (PinNumber <= XGpioPsPinTable[*BankNumber]) { + break; } -#else - u32 XGpioPsPinTable[] = { - (u32)31, /* 0 - 31, Bank 0 */ - (u32)53, /* 32 - 53, Bank 1 */ - (u32)85, /* 54 - 85, Bank 2 */ - (u32)117 /* 86 - 117 Bank 3 */ - }; - *BankNumber = 0U; - while (*BankNumber < 4U) { - if (PinNumber <= XGpioPsPinTable[*BankNumber]) { - break; + (*BankNumber)++; } - (*BankNumber)++; - } -#endif + } else { + XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */ + XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */ + XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */ + XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */ + + *BankNumber = 0U; + while (*BankNumber < 4U) { + if (PinNumber <= XGpioPsPinTable[*BankNumber]) { + break; + } + (*BankNumber)++; + } + } if (*BankNumber == (u8)0) { *PinNumberInBank = PinNumber; } else { diff --git a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.h b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.h index df8baef9..d0ac1592 100644 --- a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.h +++ b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.h @@ -93,6 +93,7 @@ * 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number * passed to APIs. CR# 822636 * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980. * * * @@ -108,6 +109,7 @@ extern "C" { #include "xstatus.h" #include "xgpiops_hw.h" +#include "xplatform_info.h" /************************** Constant Definitions *****************************/ @@ -123,6 +125,7 @@ extern "C" { #define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */ /*@}*/ +#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */ #define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */ #define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */ #define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */ @@ -131,11 +134,15 @@ extern "C" { #ifdef XPAR_PSU_GPIO_0_BASEADDR #define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */ #define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */ +#endif -#define XGPIOPS_MAX_BANKS 0x06U /**< Max banks in a GPIO device */ -#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */ +#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a + * Zynq Ultrascale+ MP GPIO device + */ +#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */ -#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)174 /*< Max pins in the ZynqMP GPIO device +#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the + * Zynq Ultrascale+ MP GPIO device * 0 - 25, Bank 0 * 26 - 51, Bank 1 * 52 - 77, Bank 2 @@ -143,20 +150,13 @@ extern "C" { * 110 - 141, Bank 4 * 142 - 173, Bank 5 */ -#else - -#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a GPIO device */ -#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */ - -#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /*< Max pins in the GPIO device +#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device * 0 - 31, Bank 0 * 32 - 53, Bank 1 * 54 - 85, Bank 2 * 86 - 117, Bank 3 */ - -#endif /**************************** Type Definitions *******************************/ /****************************************************************************/ @@ -196,6 +196,9 @@ typedef struct { u32 IsReady; /**< Device is initialized and ready */ XGpioPs_Handler Handler; /**< Status handlers for all banks */ void *CallBackRef; /**< Callback ref for bank handlers */ + u32 Platform; /**< Platform data */ + u32 MaxPinNum; /**< Max pins in the GPIO device */ + u8 MaxBanks; /**< Max banks in a GPIO device */ } XGpioPs; /***************** Macros (Inline Functions) Definitions *********************/ diff --git a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_hw.c b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_hw.c index 7c68d69d..a116165c 100644 --- a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_hw.c +++ b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_hw.c @@ -43,6 +43,7 @@ * ----- ---- -------- ----------------------------------------------- * 1.02a hk 08/22/13 First Release * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980. * * * @@ -80,11 +81,18 @@ void XGpioPs_ResetHw(u32 BaseAddress) { u32 BankCount; + u32 Platform,MaxBanks; + Platform = XGetPlatform_Info(); + if (Platform == XPLAT_ZYNQ_ULTRA_MP) { + MaxBanks = (u32)6; + } else { + MaxBanks = (u32)4; + } /* * Write reset values to all mask data registers */ - for(BankCount = 2U; BankCount < (u32)XGPIOPS_MAX_BANKS; BankCount++) { + for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) { XGpioPs_WriteReg(BaseAddress, ((BankCount * XGPIOPS_DATA_MASK_OFFSET) + @@ -96,7 +104,7 @@ void XGpioPs_ResetHw(u32 BaseAddress) /* * Write reset values to all output data registers */ - for(BankCount = 2U; BankCount < (u32)XGPIOPS_MAX_BANKS; BankCount++) { + for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) { XGpioPs_WriteReg(BaseAddress, ((BankCount * XGPIOPS_DATA_BANK_OFFSET) + @@ -104,9 +112,9 @@ void XGpioPs_ResetHw(u32 BaseAddress) } /* - * Reset all registers of all 4 banks + * Reset all registers of all GPIO banks */ - for(BankCount = 0U; BankCount < (u32)XGPIOPS_MAX_BANKS; BankCount++) { + for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) { XGpioPs_WriteReg(BaseAddress, ((BankCount * XGPIOPS_REG_MASK_OFFSET) + @@ -157,19 +165,20 @@ void XGpioPs_ResetHw(u32 BaseAddress) XGpioPs_WriteReg(BaseAddress, (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), XGPIOPS_INTTYPE_BANK3_RESET); -#ifdef XPAR_PSU_GPIO_0_BASEADDR - /* - * Bank 4 Int type - */ - XGpioPs_WriteReg(BaseAddress, - (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), - XGPIOPS_INTTYPE_BANK4_RESET); - /* - * Bank 5 Int type - */ - XGpioPs_WriteReg(BaseAddress, - (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), - XGPIOPS_INTTYPE_BANK5_RESET); -#endif + + if (Platform == XPLAT_ZYNQ_ULTRA_MP) { + /* + * Bank 4 Int type + */ + XGpioPs_WriteReg(BaseAddress, + (((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), + XGPIOPS_INTTYPE_BANK4_RESET); + /* + * Bank 5 Int type + */ + XGpioPs_WriteReg(BaseAddress, + (((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), + XGPIOPS_INTTYPE_BANK5_RESET); + } } diff --git a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_intr.c b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_intr.c index f54f925b..33dd8b23 100644 --- a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_intr.c +++ b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_intr.c @@ -45,6 +45,7 @@ * 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number * passed to API's. CR# 822636 * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980. * * ******************************************************************************/ @@ -73,7 +74,7 @@ void StubHandler(void *CallBackRef, u32 Bank, u32 Status); * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. * @param Mask is the bit mask of the pins for which interrupts are to * be enabled. Bit positions of 1 will be enabled. Bit positions * of 0 will keep the previous setting. @@ -87,7 +88,7 @@ void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + @@ -101,7 +102,7 @@ void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Pin is the pin number for which the interrupt is to be enabled. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. * * @return None. * @@ -116,7 +117,7 @@ void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); + Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); /* * Get the Bank number and Pin number within the bank. @@ -137,7 +138,7 @@ void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. * @param Mask is the bit mask of the pins for which interrupts are * to be disabled. Bit positions of 1 will be disabled. Bit * positions of 0 will keep the previous setting. @@ -151,7 +152,7 @@ void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + @@ -165,7 +166,7 @@ void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Pin is the pin number for which the interrupt is to be disabled. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. * * @return None. * @@ -180,7 +181,7 @@ void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); + Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); /* * Get the Bank number and Pin number within the bank. @@ -200,7 +201,7 @@ void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. * * @return Enabled interrupt(s) in a 32-bit format. Bit positions with 1 * indicate that the interrupt for that pin is enabled, bit @@ -216,7 +217,7 @@ u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank) Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS); + Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks); IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + @@ -232,7 +233,7 @@ u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank) * @param InstancePtr is a pointer to the XGpioPs instance. * @param Pin is the pin number for which the interrupt enable status * is to be known. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. * * @return * - TRUE if the interrupt is enabled. @@ -249,7 +250,7 @@ u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); + Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); /* * Get the Bank number and Pin number within the bank. @@ -270,7 +271,7 @@ u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. * * @return The value read from Interrupt Status Register. * @@ -281,7 +282,7 @@ u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS); + Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks); return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + @@ -296,7 +297,7 @@ u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank) * @param InstancePtr is a pointer to the XGpioPs instance. * @param Pin is the pin number for which the interrupt enable status * is to be known. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. * * @return * - TRUE if the interrupt has occurred. @@ -313,7 +314,7 @@ u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); + Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); /* * Get the Bank number and Pin number within the bank. @@ -336,7 +337,7 @@ u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. * @param Mask is the mask of the interrupts to be cleared. Bit positions * of 1 will be cleared. Bit positions of 0 will not change the * previous interrupt status. @@ -348,7 +349,7 @@ void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); /* * Clear the currently pending interrupts. @@ -366,7 +367,7 @@ void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask) * * @param InstancePtr is a pointer to the XGpioPs instance. * @param Pin is the pin number for which the interrupt status is to be -* cleared. Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. +* cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. * * @note None. * @@ -379,7 +380,7 @@ void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); + Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); /* * Get the Bank number and Pin number within the bank. @@ -407,7 +408,7 @@ void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin) * * @param InstancePtr is a pointer to an XGpioPs instance. * @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. * @param IntrType is the 32 bit mask of the interrupt type. * 0 means Level Sensitive and 1 means Edge Sensitive. * @param IntrPolarity is the 32 bit mask of the interrupt polarity. @@ -432,7 +433,7 @@ void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType, { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + @@ -455,7 +456,7 @@ void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType, * * @param InstancePtr is a pointer to an XGpioPs instance. * @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. * @param IntrType returns the 32 bit mask of the interrupt type. * 0 means Level Sensitive and 1 means Edge Sensitive. * @param IntrPolarity returns the 32 bit mask of the interrupt @@ -477,7 +478,7 @@ void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType, { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); *IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + @@ -499,7 +500,7 @@ void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType, * * @param InstancePtr is a pointer to an XGpioPs instance. * @param Pin is the pin number whose IRQ type is to be set. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. * @param IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_* * defined in xgpiops.h to specify the IRQ type. * @@ -518,7 +519,7 @@ void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType) Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); + Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW); /* @@ -586,7 +587,7 @@ void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType) * * @param InstancePtr is a pointer to an XGpioPs instance. * @param Pin is the pin number whose IRQ type is to be obtained. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. * * @return None. * @@ -605,7 +606,7 @@ u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); + Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); /* * Get the Bank number and Pin number within the bank. @@ -706,7 +707,7 @@ void XGpioPs_IntrHandler(XGpioPs *InstancePtr) Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - for (Bank = 0U; Bank < XGPIOPS_MAX_BANKS; Bank++) { + for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) { IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank); if (IntrStatus != (u32)0) { IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,