diff --git a/XilinxProcessorIPLib/drivers/dp/data/dependencies.props b/XilinxProcessorIPLib/drivers/dp/data/dependencies.props index e503e0f4..17983bbf 100644 --- a/XilinxProcessorIPLib/drivers/dp/data/dependencies.props +++ b/XilinxProcessorIPLib/drivers/dp/data/dependencies.props @@ -1,7 +1,7 @@ -xdprx_intr_timer_example.c=xdprx_intr_timer_example.c -xdptx_audio_example.c=xdptx_example_common.h,xdptx_example_common.c -xdptx_intr_example.c=xdptx_example_common.h,xdptx_example_common.c -xdptx_mst_example.c=xdptx_example_common.h,xdptx_example_common.c -xdptx_poll_example.c=xdptx_example_common.h,xdptx_example_common.c -xdptx_selftest_example.c=xdptx_example_common.h,xdptx_example_common.c -xdptx_timer_example.c=xdptx_example_common.h,xdptx_example_common.c +xdp_selftest_example.c=xdp_selftest_example.c +xdp_rx_intr_timer_example.c=xdp_rx_intr_timer_example.c +xdp_tx_audio_example.c=xdp_tx_example_common.h,xdp_tx_example_common.c +xdp_tx_intr_example.c=xdp_tx_example_common.h,xdp_tx_example_common.c +xdp_tx_mst_example.c=xdp_tx_example_common.h,xdp_tx_example_common.c +xdp_tx_poll_example.c=xdp_tx_example_common.h,xdp_tx_example_common.c +xdp_tx_timer_example.c=xdp_tx_example_common.h,xdp_tx_example_common.c diff --git a/XilinxProcessorIPLib/drivers/dp/examples/index.html b/XilinxProcessorIPLib/drivers/dp/examples/index.html index eaec9b27..8b844ff1 100755 --- a/XilinxProcessorIPLib/drivers/dp/examples/index.html +++ b/XilinxProcessorIPLib/drivers/dp/examples/index.html @@ -10,13 +10,13 @@

Example applications for the dp driver.


Copyright © 1995-2015 Xilinx, Inc. All rights reserved.

diff --git a/XilinxProcessorIPLib/drivers/dp/examples/readme.txt b/XilinxProcessorIPLib/drivers/dp/examples/readme.txt index 60aa436b..98cfaec6 100644 --- a/XilinxProcessorIPLib/drivers/dp/examples/readme.txt +++ b/XilinxProcessorIPLib/drivers/dp/examples/readme.txt @@ -1,5 +1,5 @@ There is 1 DisplayPort RX example included in this directory: -1) xdprx_intr_timer_example.c : This interrupt with timer example shows how to +1) xdp_rx_intr_timer_example.c : This interrupt with timer example shows how to set up both the interrupt system with interrupt handlers and how to override the default sleep/delay functionality for MicroBlaze. A timer needs to exist in the hardware system and will be used for sleep/delay functionality inside @@ -10,13 +10,13 @@ There is 1 DisplayPort RX example included in this directory: built-in. Note: All example functions start with Dprx_*, while all driver functions start -with XDprx_*. +with XDp_*. There are 6 DisplayPort TX examples included in this directory: -1) xdptx_audio_example.c : This audio example, apart from training the main link - and outputting video, illustrates the sequence required for setting up audio - in the DisplayPort TX. This example requires that an audio source, such as a - S/PDIF instance be present and connected to the DisplayPort TX in the +1) xdp_tx_audio_example.c : This audio example, apart from training the main + link and outputting video, illustrates the sequence required for setting up + audio in the DisplayPort TX. This example requires that an audio source, such + as a S/PDIF instance be present and connected to the DisplayPort TX in the hardware system, and for the audio enable configuration parameter to be set for the instantiated DisplayPort TX. For audio to output, the user will need to implement the following functions: @@ -25,12 +25,12 @@ There are 6 DisplayPort TX examples included in this directory: b) Dptx_AudioSendInfoFrame : This function needs to set up and write an audio info frame as per user requirements. -2) xdptx_intr_example.c : This interrupt example shows how to set up the +2) xdp_tx_intr_example.c : This interrupt example shows how to set up the interrupt system and specify the interrupt handlers for when a DisplayPort interrupt event occurs. An interrupt controller with a connection to the DisplayPort interrupt signal needs to exist in the hardware system. -3) xdptx_mst_example.c : This multi-stream transport (MST) example shows how to +3) xdp_tx_mst_example.c : This multi-stream transport (MST) example shows how to use the driver's MST capabilities. Streams can be directed at sinks using two methods: a) After topology discover has created a sink list, streams may be assigned @@ -39,10 +39,10 @@ There are 6 DisplayPort TX examples included in this directory: discovery if their relative addresses (and total number of DisplayPort links) from the DisplayPort source is known beforehand. -4) xdptx_poll_example.c : This interrupt example shows how to poll the +4) xdp_tx_poll_example.c : This interrupt example shows how to poll the DisplayPort TX instance's registers for DisplayPort interrupt events. -5) xdptx_timer_example.c : This timer example shows how to override the default +5) xdp_tx_timer_example.c : This timer example shows how to override the default sleep/delay functionality for MicroBlaze. A timer needs to exist in the hardware system and will be used for sleep/delay functionality inside of a callback function. The default behavior in MicroBlaze for sleep/delay is to @@ -50,13 +50,13 @@ There are 6 DisplayPort TX examples included in this directory: For ARM/Zynq SoC systems, the supplied callback function will be ignored - the usleep function will be called since the SoC has a timer built-in. -6) xdptx_selftest_example.c : This self test example will perform a sanity check - on the state of the DisplayPort TX instance. It may be called prior to usage - of the core or after a reset to ensure that (a subset of) the registers hold - their default values. +6) xdp_tx_selftest_example.c : This self test example will perform a sanity + check on the state of the DisplayPort TX instance. It may be called prior to + usage of the core or after a reset to ensure that (a subset of) the registers + hold their default values. Each of these examples are meant to be used in conjunction with -xdptx_example_common.[ch] which holds common functionality for all examples. +xdp_tx_example_common.[ch] which holds common functionality for all examples. After importing the examples, these files will need to be manually copied into the example src/ directory. This code shows how to train the main link and set up a video stream. @@ -70,7 +70,7 @@ examples, the user will need to implement and link the following functions: timings and video attributes that correspond to the main stream attributes (MSA) configuration, is received by the DisplayPort Tx. The examples call this function from the Dptx_Run->Dptx_StartVideoStream functions in - xdptx_example_common.c. + xdp_tx_example_common.c. Note: All example functions start with Dptx_*, while all driver functions start -with XDptx_*. +with XDp_*. diff --git a/XilinxProcessorIPLib/drivers/dp/examples/xdprx_intr_timer_example.c b/XilinxProcessorIPLib/drivers/dp/examples/xdp_rx_intr_timer_example.c similarity index 83% rename from XilinxProcessorIPLib/drivers/dp/examples/xdprx_intr_timer_example.c rename to XilinxProcessorIPLib/drivers/dp/examples/xdp_rx_intr_timer_example.c index fdd11386..8394539c 100644 --- a/XilinxProcessorIPLib/drivers/dp/examples/xdprx_intr_timer_example.c +++ b/XilinxProcessorIPLib/drivers/dp/examples/xdp_rx_intr_timer_example.c @@ -32,9 +32,9 @@ /******************************************************************************/ /** * - * @file xdprx_intr_timer_example.c + * @file xdp_rx_intr_timer_example.c * - * Contains a design example using the XDprx driver with a user-defined hook + * Contains a design example using the XDp driver with a user-defined hook * for delay. The reasoning behind this is that MicroBlaze sleep is not very * accurate without a hardware timer. For systems that have a hardware timer, * the user may override the default MicroBlaze sleep with a function that will @@ -46,7 +46,8 @@ * This example will print out the detected resolution of the incoming * DisplayPort video stream. * This example is meant to take in the incoming DisplayPort video stream and - * output it over HDMI (pass-through). + * pass it through using the Dprd_Vidpipe* functions which are left for the user + * to implement. * * @note This example requires an AXI timer in the system. * @note For this example to work, the user will need to implement @@ -68,7 +69,7 @@ /******************************* Include Files ********************************/ -#include "xdprx.h" +#include "xdp.h" #include "xparameters.h" #ifdef XPAR_INTC_0_DEVICE_ID /* For MicroBlaze systems. */ @@ -107,10 +108,10 @@ XPAR_PROCESSOR_SUBSYSTEM_INTERCONNECT_AXI_INTC_1_DISPLAYPORT_0_AXI_INT_INTR /**************************** Function Prototypes *****************************/ -u32 Dprx_IntrTimerExample(XDprx *InstancePtr, u16 DeviceId, INTC *IntcPtr, +u32 Dprx_IntrTimerExample(XDp *InstancePtr, u16 DeviceId, INTC *IntcPtr, u16 IntrId, u16 DpIntrId, XTmrCtr *TimerCounterPtr); -static u32 Dprx_SetupExample(XDprx *InstancePtr, u16 DeviceId); -static u32 Dprx_SetupInterruptHandler(XDprx *InstancePtr, INTC *IntcPtr, +static u32 Dprx_SetupExample(XDp *InstancePtr, u16 DeviceId); +static u32 Dprx_SetupInterruptHandler(XDp *InstancePtr, INTC *IntcPtr, u16 IntrId, u16 DpIntrId); static void Dprx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds); static void Dprx_ResetVideoOutput(void *InstancePtr); @@ -127,12 +128,12 @@ static void Dprx_InterruptHandlerTp1(void *InstancePtr); static void Dprx_InterruptHandlerTp2(void *InstancePtr); static void Dprx_InterruptHandlerTp3(void *InstancePtr); -extern void Dprx_VidpipeConfig(XDprx *InstancePtr); +extern void Dprx_VidpipeConfig(XDp *InstancePtr); extern void Dprx_VidpipeReset(void); /*************************** Variable Declarations ****************************/ -XDprx DprxInstance; /* The Dprx instance. */ +XDp DpInstance; /* The Dp instance. */ INTC IntcInstance; /* The interrupt controller instance. */ XTmrCtr TimerCounterInst; /* The timer counter instance. */ @@ -144,9 +145,9 @@ u8 VBlankCount; /******************************************************************************/ /** - * This function is the main function of the XDprx interrupt with timer example. - * If the DprxIntrTimerExample function, which sets up the system succeeds, this - * function will wait for interrupts. + * This function is the main function of the XDp (operating in RX mode) + * interrupt with timer example. If the Dprx_IntrTimerExample function, which + * sets up the system succeeds, this function will wait for interrupts. * * @param None. * @@ -155,15 +156,15 @@ u8 VBlankCount; * setup failed. * * @note Unless setup failed, main will never return since - * DprxIntrTimerExample is blocking. + * Dprx_IntrTimerExample is blocking. * *******************************************************************************/ int main(void) { u32 Status; - /* Run the XDprx timer example. */ - Status = Dprx_IntrTimerExample(&DprxInstance, DPRX_DEVICE_ID, + /* Run the XDp (in RX mode) interrupt with timer example. */ + Status = Dprx_IntrTimerExample(&DpInstance, DPRX_DEVICE_ID, &IntcInstance, INTC_DEVICE_ID, DP_INTERRUPT_ID, &TimerCounterInst); if (Status != XST_SUCCESS) { @@ -175,11 +176,11 @@ int main(void) /******************************************************************************/ /** - * The main entry point for the interrupt with timer example using the XDprx + * The main entry point for the interrupt with timer example using the XDp * driver. This function will set up the system, interrupt controller and * interrupt handlers, and the custom sleep handler. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param DeviceId is the unique device ID of the DisplayPort RX core * instance. * @param IntcPtr is a pointer to the interrupt instance. @@ -196,7 +197,7 @@ int main(void) * @note None. * *******************************************************************************/ -u32 Dprx_IntrTimerExample(XDprx *InstancePtr, u16 DeviceId, INTC *IntcPtr, +u32 Dprx_IntrTimerExample(XDp *InstancePtr, u16 DeviceId, INTC *IntcPtr, u16 IntrId, u16 DpIntrId, XTmrCtr *TimerCounterPtr) { u32 Status; @@ -212,7 +213,7 @@ u32 Dprx_IntrTimerExample(XDprx *InstancePtr, u16 DeviceId, INTC *IntcPtr, * Note: This only has an affect for MicroBlaze systems since the Zynq * ARM SoC contains a timer, which is used when the driver calls the * delay function. */ - XDprx_SetUserTimerHandler(InstancePtr, &Dprx_CustomWaitUs, + XDp_SetUserTimerHandler(InstancePtr, &Dprx_CustomWaitUs, TimerCounterPtr); /* Setup interrupt handling in the system. */ @@ -239,7 +240,7 @@ u32 Dprx_IntrTimerExample(XDprx *InstancePtr, u16 DeviceId, INTC *IntcPtr, * configuration parameters will be retrieved based on the configuration * to the DisplayPort RX core instance with the specified device ID. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param DeviceId is the unique device ID of the DisplayPort RX core * instance. * @@ -251,7 +252,7 @@ u32 Dprx_IntrTimerExample(XDprx *InstancePtr, u16 DeviceId, INTC *IntcPtr, * @note None. * *******************************************************************************/ -static u32 Dprx_SetupExample(XDprx *InstancePtr, u16 DeviceId) +static u32 Dprx_SetupExample(XDp *InstancePtr, u16 DeviceId) { XDp_Config *ConfigPtr; u32 Status; @@ -263,13 +264,13 @@ static u32 Dprx_SetupExample(XDprx *InstancePtr, u16 DeviceId) } /* Copy the device configuration into the InstancePtr's Config * structure. */ - XDprx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr); + XDp_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr); - XDprx_SetLaneCount(InstancePtr, InstancePtr->Config.MaxLaneCount); - XDprx_SetLinkRate(InstancePtr, InstancePtr->Config.MaxLinkRate); + XDp_RxSetLaneCount(InstancePtr, InstancePtr->Config.MaxLaneCount); + XDp_RxSetLinkRate(InstancePtr, InstancePtr->Config.MaxLinkRate); /* Initialize the DisplayPort RX core. */ - Status = XDprx_InitializeRx(InstancePtr); + Status = XDp_Initialize(InstancePtr); if (Status != XST_SUCCESS) { return XST_FAILURE; } @@ -285,7 +286,7 @@ static u32 Dprx_SetupExample(XDprx *InstancePtr, u16 DeviceId) * to the processor. The user should modify this function to fit the * application. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param IntcPtr is a pointer to the interrupt instance. * @param IntrId is the unique device ID of the interrupt controller. * @param DpIntrId is the interrupt ID of the DisplayPort RX connection to @@ -299,33 +300,33 @@ static u32 Dprx_SetupExample(XDprx *InstancePtr, u16 DeviceId) * to the processor and the DisplayPort RX core. * *******************************************************************************/ -static u32 Dprx_SetupInterruptHandler(XDprx *InstancePtr, INTC *IntcPtr, +static u32 Dprx_SetupInterruptHandler(XDp *InstancePtr, INTC *IntcPtr, u16 IntrId, u16 DpIntrId) { u32 Status; /* Set the HPD interrupt handlers. */ - XDprx_SetIntrVmChangeHandler(InstancePtr, + XDp_RxSetIntrVmChangeHandler(InstancePtr, Dprx_InterruptHandlerVmChange, InstancePtr); - XDprx_SetIntrPowerStateHandler(InstancePtr, + XDp_RxSetIntrPowerStateHandler(InstancePtr, Dprx_InterruptHandlerPowerState, InstancePtr); - XDprx_SetIntrNoVideoHandler(InstancePtr, + XDp_RxSetIntrNoVideoHandler(InstancePtr, Dprx_InterruptHandlerNoVideo, InstancePtr); - XDprx_SetIntrVBlankHandler(InstancePtr, + XDp_RxSetIntrVBlankHandler(InstancePtr, Dprx_InterruptHandlerVBlank, InstancePtr); - XDprx_SetIntrTrainingLostHandler(InstancePtr, + XDp_RxSetIntrTrainingLostHandler(InstancePtr, Dprx_InterruptHandlerTrainingLost, InstancePtr); - XDprx_SetIntrVideoHandler(InstancePtr, + XDp_RxSetIntrVideoHandler(InstancePtr, Dprx_InterruptHandlerVideo, InstancePtr); - XDprx_SetIntrTrainingDoneHandler(InstancePtr, + XDp_RxSetIntrTrainingDoneHandler(InstancePtr, Dprx_InterruptHandlerTrainingDone, InstancePtr); - XDprx_SetIntrBwChangeHandler(InstancePtr, + XDp_RxSetIntrBwChangeHandler(InstancePtr, Dprx_InterruptHandlerBwChange, InstancePtr); - XDprx_SetIntrTp1Handler(InstancePtr, + XDp_RxSetIntrTp1Handler(InstancePtr, Dprx_InterruptHandlerTp1, InstancePtr); - XDprx_SetIntrTp2Handler(InstancePtr, + XDp_RxSetIntrTp2Handler(InstancePtr, Dprx_InterruptHandlerTp2, InstancePtr); - XDprx_SetIntrTp3Handler(InstancePtr, + XDp_RxSetIntrTp3Handler(InstancePtr, Dprx_InterruptHandlerTp3, InstancePtr); /* Initialize interrupt controller driver. */ @@ -351,10 +352,10 @@ static u32 Dprx_SetupInterruptHandler(XDprx *InstancePtr, INTC *IntcPtr, * the specific interrupt processing for the device. */ #ifdef XPAR_INTC_0_DEVICE_ID Status = XIntc_Connect(IntcPtr, DpIntrId, - (XInterruptHandler)XDprx_InterruptHandler, InstancePtr); + (XInterruptHandler)XDp_InterruptHandler, InstancePtr); #else Status = XScuGic_Connect(IntcPtr, DpIntrId, - (Xil_InterruptHandler)XDprx_InterruptHandler, InstancePtr); + (Xil_InterruptHandler)XDp_InterruptHandler, InstancePtr); #endif /* XPAR_INTC_0_DEVICE_ID */ if (Status != XST_SUCCESS) { return XST_FAILURE; @@ -388,43 +389,43 @@ static u32 Dprx_SetupInterruptHandler(XDprx *InstancePtr, INTC *IntcPtr, /******************************************************************************/ /** * This function is used to override the driver's default sleep functionality. - * For MicroBlaze systems, the XDprx_WaitUs driver function's default behavior + * For MicroBlaze systems, the XDp_WaitUs driver function's default behavior * is to use the MB_Sleep function from microblaze_sleep.h, which is implemented * in software and only has millisecond accuracy. For this reason, using a * hardware timer is preferrable. For ARM/Zynq SoC systems, the SoC's timer is - * used - XDprx_WaitUs will ignore this custom timer handler. + * used - XDp_WaitUs will ignore this custom timer handler. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * - * @note Use the XDprx_SetUserTimerHandler driver function to set this - * function as the handler for when the XDprx_WaitUs driver + * @note Use the XDp_SetUserTimerHandler driver function to set this + * function as the handler for when the XDp_WaitUs driver * function is called. * *******************************************************************************/ static void Dprx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds) { - XDprx *XDprx_InstancePtr = (XDprx *)InstancePtr; + XDp *XDp_InstancePtr = (XDp *)InstancePtr; u32 TimerVal; - XTmrCtr_Start(XDprx_InstancePtr->UserTimerPtr, 0); + XTmrCtr_Start(XDp_InstancePtr->UserTimerPtr, 0); /* Wait specified number of useconds. */ do { - TimerVal = XTmrCtr_GetValue(XDprx_InstancePtr->UserTimerPtr, 0); + TimerVal = XTmrCtr_GetValue(XDp_InstancePtr->UserTimerPtr, 0); } while (TimerVal < (MicroSeconds * - (XDprx_InstancePtr->Config.SAxiClkHz / 1000000))); + (XDp_InstancePtr->Config.SAxiClkHz / 1000000))); - XTmrCtr_Stop(XDprx_InstancePtr->UserTimerPtr, 0); + XTmrCtr_Stop(XDp_InstancePtr->UserTimerPtr, 0); } /******************************************************************************/ /** * This function is used to reset video output for this example. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -434,7 +435,7 @@ static void Dprx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds) static void Dprx_ResetVideoOutput(void *InstancePtr) { xil_printf("\tDisabling the display timing generator.\n"); - XDprx_DtgDis(InstancePtr); + XDp_RxDtgDis(InstancePtr); xil_printf("\tResetting the video output pipeline.\n"); /* This is hardware system specific - it is up to the user to implement @@ -449,14 +450,14 @@ static void Dprx_ResetVideoOutput(void *InstancePtr) /*******************/ xil_printf("\tRe-enabling the display timing generator.\n"); - XDprx_DtgEn(InstancePtr); + XDp_RxDtgEn(InstancePtr); } /******************************************************************************/ /** * This function will present the resolution of the incoming video stream. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -470,12 +471,12 @@ static void Dprx_DetectResolution(void *InstancePtr) u32 GetResCount = 0; do { - DpHres = (XDprx_ReadReg(((XDprx *)InstancePtr)->Config.BaseAddr, - XDPRX_MSA_HRES)); - DpVres = (XDprx_ReadReg(((XDprx *)InstancePtr)->Config.BaseAddr, - XDPRX_MSA_VHEIGHT)); + DpHres = (XDp_ReadReg(((XDp *)InstancePtr)->Config.BaseAddr, + XDP_RX_MSA_HRES)); + DpVres = (XDp_ReadReg(((XDp *)InstancePtr)->Config.BaseAddr, + XDP_RX_MSA_VHEIGHT)); GetResCount++; - XDprx_WaitUs(InstancePtr, 1000); + XDp_WaitUs(InstancePtr, 1000); } while (((DpHres == 0) || (DpVres == 0)) && (GetResCount < 2000)); xil_printf("\n*** Detected resolution: %d x %d ***\n", DpHres, DpVres); @@ -486,7 +487,7 @@ static void Dprx_DetectResolution(void *InstancePtr) * This function is the callback function for when a video mode chang interrupt * occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -499,7 +500,7 @@ static void Dprx_InterruptHandlerVmChange(void *InstancePtr) xil_printf("> Interrupt: video mode change.\n"); - Status = XDprx_CheckLinkStatus(InstancePtr); + Status = XDp_RxCheckLinkStatus(InstancePtr); if ((Status == XST_SUCCESS) && (VBlankCount >= 20)) { Dprx_ResetVideoOutput(InstancePtr); Dprx_DetectResolution(InstancePtr); @@ -511,7 +512,7 @@ static void Dprx_InterruptHandlerVmChange(void *InstancePtr) * This function is the callback function for when the power state interrupt * occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -527,7 +528,7 @@ static void Dprx_InterruptHandlerPowerState(void *InstancePtr) /** * This function is the callback function for when a no video interrupt occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -545,7 +546,7 @@ static void Dprx_InterruptHandlerNoVideo(void *InstancePtr) * This function is the callback function for when a vertical blanking interrupt * occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -566,10 +567,10 @@ static void Dprx_InterruptHandlerVBlank(void *InstancePtr) * outputting any video stream. */ if (VBlankCount >= 20) { VBlankEnable = 0; - XDprx_InterruptDisable(InstancePtr, - XDPRX_INTERRUPT_MASK_VBLANK_MASK); + XDp_RxInterruptDisable(InstancePtr, + XDP_RX_INTERRUPT_MASK_VBLANK_MASK); - Status = XDprx_CheckLinkStatus(InstancePtr); + Status = XDp_RxCheckLinkStatus(InstancePtr); if (Status == XST_SUCCESS) { Dprx_ResetVideoOutput(InstancePtr); Dprx_DetectResolution(InstancePtr); @@ -583,7 +584,7 @@ static void Dprx_InterruptHandlerVBlank(void *InstancePtr) * This function is the callback function for when a training lost interrupt * occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -596,11 +597,11 @@ static void Dprx_InterruptHandlerTrainingLost(void *InstancePtr) /* Re-enable vertical blanking interrupt and counter. */ VBlankEnable = 1; - XDprx_InterruptEnable(InstancePtr, XDPRX_INTERRUPT_MASK_VBLANK_MASK); + XDp_RxInterruptEnable(InstancePtr, XDP_RX_INTERRUPT_MASK_VBLANK_MASK); VBlankCount = 0; xil_printf("\tDisabling the display timing generator.\n"); - XDprx_DtgDis(InstancePtr); + XDp_RxDtgDis(InstancePtr); xil_printf("\tResetting the video output pipeline.\n"); /* This is hardware system specific - it is up to the user to implement * this function if needed. */ @@ -613,7 +614,7 @@ static void Dprx_InterruptHandlerTrainingLost(void *InstancePtr) * This function is the callback function for when a valid video interrupt * occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -631,7 +632,7 @@ static void Dprx_InterruptHandlerVideo(void *InstancePtr) * This function is the callback function for when a training done interrupt * occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -648,7 +649,7 @@ static void Dprx_InterruptHandlerTrainingDone(void *InstancePtr) * This function is the callback function for when a bandwidth change interrupt * occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -665,7 +666,7 @@ static void Dprx_InterruptHandlerBwChange(void *InstancePtr) * This function is the callback function for when a training pattern 1 * interrupt occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -682,7 +683,7 @@ static void Dprx_InterruptHandlerTp1(void *InstancePtr) * This function is the callback function for when a training pattern 2 * interrupt occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -699,7 +700,7 @@ static void Dprx_InterruptHandlerTp2(void *InstancePtr) * This function is the callback function for when a training pattern 3 * interrupt occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * diff --git a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_selftest_example.c b/XilinxProcessorIPLib/drivers/dp/examples/xdp_selftest_example.c similarity index 77% rename from XilinxProcessorIPLib/drivers/dp/examples/xdptx_selftest_example.c rename to XilinxProcessorIPLib/drivers/dp/examples/xdp_selftest_example.c index 9f4f8b43..e03beb8f 100644 --- a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_selftest_example.c +++ b/XilinxProcessorIPLib/drivers/dp/examples/xdp_selftest_example.c @@ -32,10 +32,10 @@ /******************************************************************************/ /** * - * @file xdptx_selftest_example.c + * @file xdp_selftest_example.c * - * Contains a design example using the XDptx driver. It performs a self test on - * the DisplayPort TX core that will compare many of the DisplayPort TX core's + * Contains a design example using the XDp driver. It performs a self test on + * the DisplayPort TX/RX core that will compare many of the DisplayPort core's * registers against their default reset values. * * @note None. @@ -45,24 +45,33 @@ * * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- - * 1.0 als 06/17/14 Initial creation. + * 1.0 als 01/20/15 Initial creation. * * *******************************************************************************/ /******************************* Include Files ********************************/ -#include "xdptx_example_common.h" +#include "xdp.h" +#include "xparameters.h" + +/**************************** Constant Definitions ****************************/ + +#define DP_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID /**************************** Function Prototypes *****************************/ -u32 Dptx_SelfTestExample(XDptx *InstancePtr, u16 DeviceId); +u32 Dp_SelfTestExample(XDp *InstancePtr, u16 DeviceId); + +/*************************** Variable Declarations ****************************/ + +XDp DpInstance; /**************************** Function Definitions ****************************/ /******************************************************************************/ /** - * This function is the main function of the XDptx selftest example. + * This function is the main function of the XDp selftest example. * * @param None. * @@ -79,23 +88,23 @@ int main(void) { u32 Status; - Status = Dptx_SelfTestExample(&DptxInstance, DPTX_DEVICE_ID); + Status = Dp_SelfTestExample(&DpInstance, DP_DEVICE_ID); if (Status != XST_SUCCESS) { - xil_printf("XDptx_SelfTest failed, check register values.\n"); + xil_printf("XDp_SelfTest failed, check register values.\n"); return XST_FAILURE; } - xil_printf("XDptx_SelfTest passed.\n"); + xil_printf("XDp_SelfTest passed.\n"); return Status; } /******************************************************************************/ /** - * The main entry point for the selftest example using the XDptx driver. This + * The main entry point for the selftest example using the XDp driver. This * function will check whether or not the DisplayPort TX's registers are at * their default reset values to ensure that the core is in a known and working * state. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param DeviceId is the unique device ID of the DisplayPort TX core * instance. * @@ -108,21 +117,21 @@ int main(void) * @note None. * *******************************************************************************/ -u32 Dptx_SelfTestExample(XDptx *InstancePtr, u16 DeviceId) +u32 Dp_SelfTestExample(XDp *InstancePtr, u16 DeviceId) { u32 Status; - XDptx_Config *ConfigPtr; + XDp_Config *ConfigPtr; /* Obtain the device configuration for the DisplayPort TX core. */ - ConfigPtr = XDptx_LookupConfig(DeviceId); + ConfigPtr = XDp_LookupConfig(DeviceId); if (!ConfigPtr) { return XST_FAILURE; } /* Copy the device configuration into the InstancePtr's Config * structure. */ - XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr); + XDp_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr); /* Run the self test. */ - Status = XDptx_SelfTest(InstancePtr); + Status = XDp_SelfTest(InstancePtr); return Status; } diff --git a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_audio_example.c b/XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_audio_example.c similarity index 76% rename from XilinxProcessorIPLib/drivers/dp/examples/xdptx_audio_example.c rename to XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_audio_example.c index 2d943a18..f76b1922 100644 --- a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_audio_example.c +++ b/XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_audio_example.c @@ -32,11 +32,11 @@ /******************************************************************************/ /** * - * @file xdptx_audio_example.c + * @file xdp_tx_audio_example.c * - * Contains a design example using the XDptx driver to train the main link and - * to display video. In this example application, the sequence to enable audio - * is illustrated. + * Contains a design example using the XDp driver (operating in TX mode) to + * train the main link and to display video. In this example application, the + * sequence to enable audio is illustrated. * * @note This example requires an audio source such as an S/PDIF instance * to be part of the hardware system. See XAPP1178 for reference. @@ -52,10 +52,10 @@ * @note For this example to display output, after training is complete, * the user will need to implement configuration of the video * stream source in order to provide the DisplayPort core with - * input (Dptx_StreamSrc* - called in xdptx_example_common.c). See + * input (Dptx_StreamSrc* - called in xdp_tx_example_common.c). See * XAPP1178 for reference. * @note The functions Dptx_PlatformInit and Dptx_StreamSrc* are declared - * extern in xdptx_example_common.h and are left up to the user to + * extern in xdp_tx_example_common.h and are left up to the user to * implement. The functions Dptx_ConfigureAudioSrc and * Dptx_AudioSendInfoFrame are present in this file and are also * left for the user to implement. @@ -65,27 +65,27 @@ * * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- - * 1.0 als 07/29/14 Initial creation. + * 1.0 als 01/20/15 Initial creation. * * *******************************************************************************/ /******************************* Include Files ********************************/ -#include "xdptx_example_common.h" +#include "xdp_tx_example_common.h" /**************************** Function Prototypes *****************************/ -u32 Dptx_AudioExample(XDptx *InstancePtr, u16 DeviceId); -static void Dptx_AudioInit(XDptx *InstancePtr); -static void Dptx_ConfigureAudioSrc(XDptx *InstancePtr); -static void Dptx_AudioSendInfoFrame(XDptx *InstancePtr); +u32 Dptx_AudioExample(XDp *InstancePtr, u16 DeviceId); +static void Dptx_AudioInit(XDp *InstancePtr); +static void Dptx_ConfigureAudioSrc(XDp *InstancePtr); +static void Dptx_AudioSendInfoFrame(XDp *InstancePtr); /**************************** Function Definitions ****************************/ /******************************************************************************/ /** - * This function is the main function of the XDptx audio example. + * This function is the main function of the XDp audio example. * * @param None. * @@ -100,8 +100,8 @@ int main(void) { u32 Status; - /* Run the XDptx audio example. */ - Status = Dptx_AudioExample(&DptxInstance, DPTX_DEVICE_ID); + /* Run the XDp audio example. */ + Status = Dptx_AudioExample(&DpInstance, DPTX_DEVICE_ID); if (Status != XST_SUCCESS) { return XST_FAILURE; } @@ -111,11 +111,11 @@ int main(void) /******************************************************************************/ /** - * The main entry point for the audio example using the XDptx driver. This + * The main entry point for the audio example using the XDp driver. This * function will set up audio, initiate link training, and a video stream will * start being sent over the main link. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param DeviceId is the unique device ID of the DisplayPort TX core * instance. * @@ -127,13 +127,13 @@ int main(void) * @note None. * *******************************************************************************/ -u32 Dptx_AudioExample(XDptx *InstancePtr, u16 DeviceId) +u32 Dptx_AudioExample(XDp *InstancePtr, u16 DeviceId) { u32 Status; /* Use single-stream transport (SST) mode for this example. Audio is * not supported in multi-stream transport (MST) mode. */ - XDptx_MstCfgModeDisable(InstancePtr); + XDp_TxMstCfgModeDisable(InstancePtr); /* Do platform initialization here. This is hardware system specific - * it is up to the user to implement this function. */ @@ -148,8 +148,8 @@ u32 Dptx_AudioExample(XDptx *InstancePtr, u16 DeviceId) /* Initialize DisplayPort audio. */ Dptx_AudioInit(InstancePtr); - XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE); - XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER); + XDp_TxEnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE); + XDp_TxSetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER); /* A sink monitor must be connected at this point. See the polling or * interrupt examples for how to wait for a connection event. */ @@ -167,7 +167,7 @@ u32 Dptx_AudioExample(XDptx *InstancePtr, u16 DeviceId) * to implement configuration of the audio stream and, if needed, sending of * the info frame. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -176,7 +176,7 @@ u32 Dptx_AudioExample(XDptx *InstancePtr, u16 DeviceId) * initialization. * *******************************************************************************/ -static void Dptx_AudioInit(XDptx *InstancePtr) +static void Dptx_AudioInit(XDp *InstancePtr) { u32 Fs; u32 MAud; @@ -185,8 +185,7 @@ static void Dptx_AudioInit(XDptx *InstancePtr) /* Disable audio in the DisplayPort TX. This will also flush the buffers * in the DisplayPort TX and set MUTE bit in VB-ID. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CONTROL, - 0x0); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_AUDIO_CONTROL, 0x0); /* Configure the audio source (the S/PDIF controller). It is up to the * user to implement this function. */ @@ -195,37 +194,38 @@ static void Dptx_AudioInit(XDptx *InstancePtr) /* Write audio info frame as per user requirements. This may be optional * for some systems. 8 writes are required to register - * XDPTX_TX_AUDIO_INFO_DATA. It is up to the user to implement this + * XDP_TX_AUDIO_INFO_DATA. It is up to the user to implement this * function. */ Dptx_AudioSendInfoFrame(InstancePtr); /*******************/ Fs = 48; /* KHz (32 | 44.1 | 48) */ - if (InstancePtr->LinkConfig.LinkRate == XDPTX_LINK_BW_SET_540GBPS) { + if (InstancePtr->TxInstance.LinkConfig.LinkRate == + XDP_TX_LINK_BW_SET_540GBPS) { MAud = 512 * Fs; } - else if (InstancePtr->LinkConfig.LinkRate == - XDPTX_LINK_BW_SET_270GBPS) { + else if (InstancePtr->TxInstance.LinkConfig.LinkRate == + XDP_TX_LINK_BW_SET_270GBPS) { MAud = 512 * Fs; } - else if (InstancePtr->LinkConfig.LinkRate == - XDPTX_LINK_BW_SET_162GBPS) { + else if (InstancePtr->TxInstance.LinkConfig.LinkRate == + XDP_TX_LINK_BW_SET_162GBPS) { MAud = 512 * Fs; } /* Write the channel count. The value is (actual count - 1). */ NumChs = 2; - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CHANNELS, + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_AUDIO_CHANNELS, NumChs - 1); /* NAud = 540000 | 270000 | 162000 */ - NAud = 27 * InstancePtr->LinkConfig.LinkRate * 1000; + NAud = 27 * InstancePtr->TxInstance.LinkConfig.LinkRate * 1000; - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_MAUD, MAud); - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_NAUD, NAud); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_AUDIO_MAUD, MAud); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_AUDIO_NAUD, NAud); /* Enable audio in the DisplayPort TX. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CONTROL, + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_AUDIO_CONTROL, 0x1); } @@ -233,7 +233,7 @@ static void Dptx_AudioInit(XDptx *InstancePtr) /** * This function needs to configure the audio source. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -241,7 +241,7 @@ static void Dptx_AudioInit(XDptx *InstancePtr) * documentation for reference. * *******************************************************************************/ -static void Dptx_ConfigureAudioSrc(XDptx *InstancePtr) +static void Dptx_ConfigureAudioSrc(XDp *InstancePtr) { xil_printf("Dptx_ConfigureAudioSrc: User defined function here.\n"); } @@ -250,7 +250,7 @@ static void Dptx_ConfigureAudioSrc(XDptx *InstancePtr) /** * This function needs to send an info frame as per user requirements. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -258,11 +258,11 @@ static void Dptx_ConfigureAudioSrc(XDptx *InstancePtr) * documentation for reference. * @note This may be optional for some systems. * @note A sequence of 8 writes are required to register - * XDPTX_TX_AUDIO_INFO_DATA. See XAPP1178 and the IP documentation + * XDP_TX_AUDIO_INFO_DATA. See XAPP1178 and the IP documentation * for reference. * *******************************************************************************/ -static void Dptx_AudioSendInfoFrame(XDptx *InstancePtr) +static void Dptx_AudioSendInfoFrame(XDp *InstancePtr) { xil_printf("Dptx_AudioSendInfoFrame: User defined function here.\n"); } diff --git a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_example_common.c b/XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_example_common.c similarity index 72% rename from XilinxProcessorIPLib/drivers/dp/examples/xdptx_example_common.c rename to XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_example_common.c index a40ae51c..817b565f 100644 --- a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_example_common.c +++ b/XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_example_common.c @@ -32,18 +32,19 @@ /******************************************************************************/ /** * - * @file xdptx_example_common.c + * @file xdp_tx_example_common.c * - * Contains a design example using the XDptx driver. It performs a self test on - * the DisplayPort TX core by training the main link at the maximum common - * capabilities between the TX and RX and checking the lane status. + * Contains a design example using the XDp driver (operating in TX mode). It + * performs a self test on the DisplayPort TX core by training the main link at + * the maximum common capabilities between the TX and RX and checking the lane + * status. * * @note The DisplayPort TX core does not work alone - video/audio * sources need to be set up in the system correctly, as well as * setting up the output path (for example, configuring the * hardware system with the DisplayPort TX core output to an FMC * card with DisplayPort output capabilities. Some platform - * initialization will need to happen prior to calling XDptx driver + * initialization will need to happen prior to calling XDp driver * functions. See XAPP1178 as a reference. * *
@@ -51,19 +52,18 @@
  *
  * Ver   Who  Date     Changes
  * ----- ---- -------- -----------------------------------------------
- * 1.0   als  06/17/14 Initial creation.
+ * 1.0   als  01/20/15 Initial creation.
  * 
* *******************************************************************************/ /******************************* Include Files ********************************/ -#include "xdptx_example_common.h" -#include "xstatus.h" +#include "xdp_tx_example_common.h" /**************************** Function Prototypes *****************************/ -static void Dptx_StartVideoStream(XDptx *InstancePtr); +static void Dptx_StartVideoStream(XDp *InstancePtr); /**************************** Function Definitions ****************************/ @@ -72,7 +72,7 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr); * This function will configure and establish a link with the receiver device, * afterwards, a video stream will start to be sent over the main link. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LaneCount is the number of lanes to use over the main link. * @param LinkRate is the link rate to use over the main link. * @@ -83,7 +83,7 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr); * @note None. * *******************************************************************************/ -u32 Dptx_Run(XDptx *InstancePtr) +u32 Dptx_Run(XDp *InstancePtr) { u32 Status; @@ -106,7 +106,7 @@ u32 Dptx_Run(XDptx *InstancePtr) * configuration parameters will be retrieved based on the configuration * to the DisplayPort TX core instance with the specified device ID. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param DeviceId is the unique device ID of the DisplayPort TX core * instance. * @@ -118,22 +118,22 @@ u32 Dptx_Run(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId) +u32 Dptx_SetupExample(XDp *InstancePtr, u16 DeviceId) { - XDptx_Config *ConfigPtr; + XDp_Config *ConfigPtr; u32 Status; /* Obtain the device configuration for the DisplayPort TX core. */ - ConfigPtr = XDptx_LookupConfig(DeviceId); + ConfigPtr = XDp_LookupConfig(DeviceId); if (!ConfigPtr) { return XST_FAILURE; } /* Copy the device configuration into the InstancePtr's Config * structure. */ - XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr); + XDp_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr); /* Initialize the DisplayPort TX core. */ - Status = XDptx_InitializeTx(InstancePtr); + Status = XDp_Initialize(InstancePtr); if (Status != XST_SUCCESS) { return XST_FAILURE; } @@ -145,7 +145,7 @@ u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId) /** * This function will configure and establish a link with the receiver device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS the if main link was successfully established. @@ -154,7 +154,7 @@ u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId) * @note None. * *******************************************************************************/ -u32 Dptx_StartLink(XDptx *InstancePtr) +u32 Dptx_StartLink(XDp *InstancePtr) { u32 VsLevelTx; u32 PeLevelTx; @@ -164,26 +164,26 @@ u32 Dptx_StartLink(XDptx *InstancePtr) /* Obtain the capabilities of the RX device by reading the monitor's * DPCD. */ - Status = XDptx_GetRxCapabilities(InstancePtr); + Status = XDp_TxGetRxCapabilities(InstancePtr); if (Status != XST_SUCCESS) { return XST_FAILURE; } #if (TRAIN_USE_MAX_LINK == 1) - LaneCount = InstancePtr->LinkConfig.MaxLaneCount; - LinkRate = InstancePtr->LinkConfig.MaxLinkRate; + LaneCount = InstancePtr->TxInstance.LinkConfig.MaxLaneCount; + LinkRate = InstancePtr->TxInstance.LinkConfig.MaxLinkRate; #else LaneCount = TRAIN_USE_LANE_COUNT; LinkRate = TRAIN_USE_LINK_RATE; #endif /* Check if the link is already trained */ - Status = XDptx_CheckLinkStatus(InstancePtr, LaneCount); + Status = XDp_TxCheckLinkStatus(InstancePtr, LaneCount); if (Status == XST_SUCCESS) { xil_printf("-> Link is already trained on %d lanes.\n", LaneCount); - if (XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_LINK_BW_SET) == LinkRate) { + if (XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_LINK_BW_SET) == LinkRate) { xil_printf("-> Link needs to be re-trained %d Mbps.\n", (270 * LinkRate)); } @@ -203,40 +203,40 @@ u32 Dptx_StartLink(XDptx *InstancePtr) return XST_FAILURE; } - XDptx_SetEnhancedFrameMode(InstancePtr, 1); - XDptx_SetDownspread(InstancePtr, 0); + XDp_TxSetEnhancedFrameMode(InstancePtr, 1); + XDp_TxSetDownspread(InstancePtr, 0); #if (TRAIN_USE_MAX_LINK == 1) /* Configure the main link based on the maximum common capabilities of * the DisplayPort TX core and the receiver device. */ - Status = XDptx_CfgMainLinkMax(InstancePtr); + Status = XDp_TxCfgMainLinkMax(InstancePtr); if (Status != XST_SUCCESS) { return XST_FAILURE; } #else - XDptx_SetLinkRate(InstancePtr, LinkRate); - XDptx_SetLaneCount(InstancePtr, LaneCount); + XDp_TxSetLinkRate(InstancePtr, LinkRate); + XDp_TxSetLaneCount(InstancePtr, LaneCount); #endif /* Train the link. */ xil_printf("******************************************\n"); - Status = XDptx_EstablishLink(InstancePtr); + Status = XDp_TxEstablishLink(InstancePtr); if (Status != XST_SUCCESS) { xil_printf("!!! Training failed !!!\n"); xil_printf("******************************************\n"); return XST_FAILURE; } - VsLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_PHY_VOLTAGE_DIFF_LANE_0); - PeLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_PHY_POSTCURSOR_LANE_0); + VsLevelTx = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_PHY_VOLTAGE_DIFF_LANE_0); + PeLevelTx = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_PHY_POSTCURSOR_LANE_0); xil_printf("!!! Training passed at LR:0x%02lx LC:%d !!!\n", - InstancePtr->LinkConfig.LinkRate, - InstancePtr->LinkConfig.LaneCount); + InstancePtr->TxInstance.LinkConfig.LinkRate, + InstancePtr->TxInstance.LinkConfig.LaneCount); xil_printf("VS:%d (TX:%d) PE:%d (TX:%d)\n", - InstancePtr->LinkConfig.VsLevel, VsLevelTx, - InstancePtr->LinkConfig.PeLevel, PeLevelTx); + InstancePtr->TxInstance.LinkConfig.VsLevel, VsLevelTx, + InstancePtr->TxInstance.LinkConfig.PeLevel, PeLevelTx); xil_printf("******************************************\n"); return XST_SUCCESS; @@ -251,7 +251,7 @@ u32 Dptx_StartLink(XDptx *InstancePtr) * - The connected monitor's preferred timing is used to determine the * video resolution (and associated timings) for the stream. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -263,34 +263,35 @@ u32 Dptx_StartLink(XDptx *InstancePtr) * a resolution of 640x480 is used at a refresh rate of 60Hz. * *******************************************************************************/ -static void Dptx_StartVideoStream(XDptx *InstancePtr) +static void Dptx_StartVideoStream(XDp *InstancePtr) { u32 Status; - u8 Edid[XDPTX_EDID_SIZE]; + u8 Edid[XDP_EDID_BLOCK_SIZE]; /* Set the bits per color. If not set, the default is 6. */ - XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID0, 8); + XDp_TxCfgMsaSetBpc(InstancePtr, XDP_TX_STREAM_ID1, 8); /* Set synchronous clock mode. */ - XDptx_CfgMsaEnSynchClkMode(InstancePtr, XDPTX_STREAM_ID0, 1); + XDp_TxCfgMsaEnSynchClkMode(InstancePtr, XDP_TX_STREAM_ID1, 1); - XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID0); - XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID1); - XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID2); - XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID3); + XDp_TxClearMsaValues(InstancePtr, XDP_TX_STREAM_ID1); + XDp_TxClearMsaValues(InstancePtr, XDP_TX_STREAM_ID2); + XDp_TxClearMsaValues(InstancePtr, XDP_TX_STREAM_ID3); + XDp_TxClearMsaValues(InstancePtr, XDP_TX_STREAM_ID4); /* Choose a method for selecting the video mode. There are 3 ways to do this: * 1) Use the preferred timing from the monitor's EDID: - * u8 Edid[XDPTX_EDID_SIZE]; - * XDptx_GetEdid(InstancePtr, Edid); - * XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr, XDPTX_STREAM_ID0, Edid); + * u8 Edid[XDP_EDID_BLOCK_SIZE]; + * XDp_TxGetEdid(InstancePtr, Edid); + * XDp_TxCfgMsaUseEdidPreferredTiming(InstancePtr, XDP_TX_STREAM_ID1, + * Edid); * * 2) Use a standard video timing mode (see mode_table.h): - * XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID0, - XDPTX_VM_640x480_60_P); + * XDp_TxCfgMsaUseStandardVideoMode(InstancePtr, XDP_TX_STREAM_ID1, + XVIDC_VM_640x480_60_P); * * 3) Use a custom configuration for the main stream attributes (MSA): - * XDptx_MainStreamAttributes MsaConfigCustom; + * XDp_TxMainStreamAttributes MsaConfigCustom; * MsaConfigCustom.Dmt.HResolution = 1280; * MsaConfigCustom.Dmt.VResolution = 1024; * MsaConfigCustom.Dmt.PixelClkKhz = 108000; @@ -302,37 +303,38 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr) * MsaConfigCustom.Dmt.VFrontPorch = 1; * MsaConfigCustom.Dmt.VSyncPulseWidth = 3; * MsaConfigCustom.Dmt.VBackPorch = 38; - * XDptx_CfgMsaUseCustom(InstancePtr, XDPTX_STREAM_ID0, + * XDp_TxCfgMsaUseCustom(InstancePtr, XDP_TX_STREAM_ID1, * &MsaConfigCustom, 1); * * To override the user pixel width: - * InstancePtr->MsaConfig[_STREAM#_].OverrideUserPixelWidth = 1; - * InstancePtr->MsaConfig[_STREAM#_].UserPixelWidth = _DESIRED_VALUE_; + * InstancePtr->TxInstance.MsaConfig[_STREAM#_].OverrideUserPixelWidth = 1; + * InstancePtr->TxInstance.MsaConfig[_STREAM#_].UserPixelWidth = + * _DESIRED_VALUE_; * Then, use one of the methods above to calculate the rest of the MSA. */ - Status = XDptx_GetEdid(InstancePtr, Edid); + Status = XDp_TxGetEdid(InstancePtr, Edid); if (Status == XST_SUCCESS) { - XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr, - XDPTX_STREAM_ID0, Edid); + XDp_TxCfgMsaUseEdidPreferredTiming(InstancePtr, + XDP_TX_STREAM_ID1, Edid); } else { - XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID0, - XDPTX_VM_640x480_60_P); + XDp_TxCfgMsaUseStandardVideoMode(InstancePtr, XDP_TX_STREAM_ID1, + XVIDC_VM_640x480_60_P); } /* Disable MST for this example. */ - XDptx_MstDisable(InstancePtr); + XDp_TxMstDisable(InstancePtr); /* Disable main stream to force sending of IDLE patterns. */ - XDptx_DisableMainLink(InstancePtr); + XDp_TxDisableMainLink(InstancePtr); /* Reset the transmitter. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, - XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK); - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, 0x0); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_SOFT_RESET, + XDP_TX_SOFT_RESET_VIDEO_STREAM_ALL_MASK); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_SOFT_RESET, 0x0); /* Set the DisplayPort TX video mode. */ - XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID0); + XDp_TxSetVideoMode(InstancePtr, XDP_TX_STREAM_ID1); /* Configure video stream source or generator here. These function need * to be implemented in order for video to be displayed and is hardware @@ -343,5 +345,5 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr) Dptx_StreamSrcSync(InstancePtr); /*********************************/ - XDptx_EnableMainLink(InstancePtr); + XDp_TxEnableMainLink(InstancePtr); } diff --git a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_example_common.h b/XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_example_common.h similarity index 81% rename from XilinxProcessorIPLib/drivers/dp/examples/xdptx_example_common.h rename to XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_example_common.h index 5e6b22f7..0614e0ac 100644 --- a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_example_common.h +++ b/XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_example_common.h @@ -32,18 +32,19 @@ /******************************************************************************/ /** * - * @file xdptx_example_common.h + * @file xdp_tx_example_common.h * - * Contains a design example using the XDptx driver. It performs a self test on - * the DisplayPort TX core by training the main link at the maximum common - * capabilities between the TX and RX and checking the lane status. + * Contains a design example using the XDp driver (operating in TX mode). It + * performs a self test on the DisplayPort TX core by training the main link at + * the maximum common capabilities between the TX and RX and checking the lane + * status. * * @note The DisplayPort TX core does not work alone - video/audio * sources need to be set up in the system correctly, as well as * setting up the output path (for example, configuring the * hardware system with the DisplayPort TX core output to an FMC * card with DisplayPort output capabilities. Some platform - * initialization will need to happen prior to calling XDptx driver + * initialization will need to happen prior to calling XDp driver * functions. See XAPP1178 as a reference. * *
@@ -51,22 +52,20 @@
  *
  * Ver   Who  Date     Changes
  * ----- ---- -------- -----------------------------------------------
- * 1.0   als  06/17/14 Initial creation.
+ * 1.0   als  01/20/15 Initial creation.
  * 
* *******************************************************************************/ -#ifndef XDPTX_EXAMPLE_COMMON_H_ +#ifndef XDP_TX_EXAMPLE_COMMON_H_ /* Prevent circular inclusions by using protection macros. */ -#define XDPTX_EXAMPLE_COMMON_H_ +#define XDP_TX_EXAMPLE_COMMON_H_ /******************************* Include Files ********************************/ -#include "xdptx.h" +#include "xdp.h" #include "xil_printf.h" -#include "xil_types.h" #include "xparameters.h" -#include "xstatus.h" /**************************** Constant Definitions ****************************/ @@ -83,7 +82,7 @@ * If set to 0, link training will return failure if the training failed using * the current lane count and link rate settings. * TRAIN_ADAPTIVE is used by the examples as input to the - * XDptx_EnableTrainAdaptive driver function. */ + * XDp_TxEnableTrainAdaptive driver function. */ #define TRAIN_ADAPTIVE 1 /* A value of 1 is used to indicate that the DisplayPort output path has a @@ -96,20 +95,20 @@ * a DisplayPort RX device, the level values specified to the DisplayPort TX * core will require some compensation. * TRAIN_HAS_REDRIVER is used by the examples as input to the - * XDptx_SetHasRedriverInPath driver function. + * XDp_TxSetHasRedriverInPath driver function. * Note: There are 16 possible voltage swing levels and 32 possible pre-emphasis * levels in the DisplayPort TX core that will be mapped to 4 possible * voltage swing and 4 possible pre-emphasis levels in the RX device. */ #define TRAIN_HAS_REDRIVER 1 /* The link rate setting to begin link training with. Valid values are: - * XDPTX_LINK_BW_SET_540GBPS, XDPTX_LINK_BW_SET_270GBPS, and - * XDPTX_LINK_BW_SET_162GBPS. */ -#define TRAIN_USE_LINK_RATE XDPTX_LINK_BW_SET_540GBPS + * XDP_TX_LINK_BW_SET_540GBPS, XDP_TX_LINK_BW_SET_270GBPS, and + * XDP_TX_LINK_BW_SET_162GBPS. */ +#define TRAIN_USE_LINK_RATE XDP_TX_LINK_BW_SET_540GBPS /* The lane count setting to begin link training with. Valid values are: - * XDPTX_LANE_COUNT_SET_4, XDPTX_LANE_COUNT_SET_2, and - * XDPTX_LANE_COUNT_SET_1. */ -#define TRAIN_USE_LANE_COUNT XDPTX_LANE_COUNT_SET_4 + * XDP_TX_LANE_COUNT_SET_4, XDP_TX_LANE_COUNT_SET_2, and + * XDP_TX_LANE_COUNT_SET_1. */ +#define TRAIN_USE_LANE_COUNT XDP_TX_LANE_COUNT_SET_4 /* If set to 1, TRAIN_USE_LINK_RATE and TRAIN_USE_LANE_COUNT will be ignored. * Instead, the maximum common link capabilities between the DisplayPort TX core * and the RX device will be used when establishing a link. @@ -121,16 +120,16 @@ /**************************** Function Prototypes *****************************/ extern u32 Dptx_PlatformInit(void); -extern u32 Dptx_StreamSrcSync(XDptx *InstancePtr); -extern u32 Dptx_StreamSrcSetup(XDptx *InstancePtr); -extern u32 Dptx_StreamSrcConfigure(XDptx *InstancePtr); +extern u32 Dptx_StreamSrcSync(XDp *InstancePtr); +extern u32 Dptx_StreamSrcSetup(XDp *InstancePtr); +extern u32 Dptx_StreamSrcConfigure(XDp *InstancePtr); -u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId); -u32 Dptx_StartLink(XDptx *InstancePtr); -u32 Dptx_Run(XDptx *InstancePtr); +u32 Dptx_SetupExample(XDp *InstancePtr, u16 DeviceId); +u32 Dptx_StartLink(XDp *InstancePtr); +u32 Dptx_Run(XDp *InstancePtr); /*************************** Variable Declarations ****************************/ -XDptx DptxInstance; +XDp DpInstance; -#endif /* XDPTX_EXAMPLE_COMMON_H_ */ +#endif /* XDP_TX_EXAMPLE_COMMON_H_ */ diff --git a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_intr_example.c b/XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_intr_example.c similarity index 80% rename from XilinxProcessorIPLib/drivers/dp/examples/xdptx_intr_example.c rename to XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_intr_example.c index 2b7243d2..dfd9545d 100644 --- a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_intr_example.c +++ b/XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_intr_example.c @@ -32,11 +32,12 @@ /******************************************************************************/ /** * - * @file xdptx_intr_example.c + * @file xdp_tx_intr_example.c * - * Contains a design example using the XDptx driver with interrupts. Upon Hot- - * Plug-Detect (HPD - DisplayPort cable is plugged/unplugged or the monitor is - * turned on/off), the main link will be trained. + * Contains a design example using the XDp driver (operating in TX mode) with + * interrupts. Upon Hot-Plug-Detect (HPD - DisplayPort cable is + * plugged/unplugged or the monitor is turned on/off), the main link will be + * trained. * * @note This example requires an interrupt controller connected to the * processor and the DisplayPort TX core in the system. @@ -44,10 +45,10 @@ * implement initialization of the system (Dptx_PlatformInit) and, * after training is complete, implement configuration of the video * stream source in order to provide the DisplayPort core with - * input (Dptx_StreamSrc* - called in xdptx_example_common.c). See + * input (Dptx_StreamSrc* - called in xdp_tx_example_common.c). See * XAPP1178 for reference. * @note The functions Dptx_PlatformInit and Dptx_StreamSrc* are declared - * extern in xdptx_example_common.h and are left up to the user to + * extern in xdp_tx_example_common.h and are left up to the user to * implement. * *
@@ -55,14 +56,14 @@
  *
  * Ver   Who  Date     Changes
  * ----- ---- -------- -----------------------------------------------
- * 1.0   als  06/17/14 Initial creation.
+ * 1.0   als  01/20/15 Initial creation.
  * 
* *******************************************************************************/ /******************************* Include Files ********************************/ -#include "xdptx_example_common.h" +#include "xdp_tx_example_common.h" #ifdef XPAR_INTC_0_DEVICE_ID /* For MicroBlaze systems. */ #include "xintc.h" @@ -97,12 +98,12 @@ /**************************** Function Prototypes *****************************/ -u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr, - u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler, - XDptx_HpdPulseHandler HpdPulseHandler); -static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr, - u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler, - XDptx_HpdPulseHandler HpdPulseHandler); +u32 Dptx_IntrExample(XDp *InstancePtr, u16 DeviceId, INTC *IntcPtr, + u16 IntrId, u16 DpIntrId, XDp_IntrHandler HpdEventHandler, + XDp_IntrHandler HpdPulseHandler); +static u32 Dptx_SetupInterruptHandler(XDp *InstancePtr, INTC *IntcPtr, + u16 IntrId, u16 DpIntrId, XDp_IntrHandler HpdEventHandler, + XDp_IntrHandler HpdPulseHandler); static void Dptx_HpdEventHandler(void *InstancePtr); static void Dptx_HpdPulseHandler(void *InstancePtr); @@ -134,7 +135,7 @@ INTC IntcInstance; /* The interrupt controller instance. */ int main(void) { /* Run the XDptx interrupt example. */ - Dptx_IntrExample(&DptxInstance, DPTX_DEVICE_ID, + Dptx_IntrExample(&DpInstance, DPTX_DEVICE_ID, &IntcInstance, INTC_DEVICE_ID, DP_INTERRUPT_ID, &Dptx_HpdEventHandler, &Dptx_HpdPulseHandler); @@ -143,11 +144,11 @@ int main(void) /******************************************************************************/ /** - * The main entry point for the interrupt example using the XDptx driver. This + * The main entry point for the interrupt example using the XDp driver. This * function will set up the system with interrupts and set up the Hot-Plug-Event * (HPD) handlers. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param DeviceId is the unique device ID of the DisplayPort TX core * instance. * @param IntcPtr is a pointer to the interrupt instance. @@ -169,14 +170,14 @@ int main(void) * events. * *******************************************************************************/ -u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr, - u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler, - XDptx_HpdPulseHandler HpdPulseHandler) +u32 Dptx_IntrExample(XDp *InstancePtr, u16 DeviceId, INTC *IntcPtr, + u16 IntrId, u16 DpIntrId, XDp_IntrHandler HpdEventHandler, + XDp_IntrHandler HpdPulseHandler) { u32 Status; /* Use single-stream transport (SST) mode for this example. */ - XDptx_MstCfgModeDisable(InstancePtr); + XDp_TxMstCfgModeDisable(InstancePtr); /* Do platform initialization here. This is hardware system specific - * it is up to the user to implement this function. */ @@ -188,8 +189,8 @@ u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr, return XST_FAILURE; } - XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE); - XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER); + XDp_TxEnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE); + XDp_TxSetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER); /* Setup interrupt handling in the system. */ Status = Dptx_SetupInterruptHandler(InstancePtr, IntcPtr, IntrId, @@ -213,7 +214,7 @@ u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr, * to the processor. The user should modify this function to fit the * application. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param IntcPtr is a pointer to the interrupt instance. * @param IntrId is the unique device ID of the interrupt controller. * @param DpIntrId is the interrupt ID of the DisplayPort TX connection to @@ -231,15 +232,15 @@ u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr, * to the processor and the DisplayPort TX core. * *******************************************************************************/ -static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr, - u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler, - XDptx_HpdPulseHandler HpdPulseHandler) +static u32 Dptx_SetupInterruptHandler(XDp *InstancePtr, INTC *IntcPtr, + u16 IntrId, u16 DpIntrId, XDp_IntrHandler HpdEventHandler, + XDp_IntrHandler HpdPulseHandler) { u32 Status; /* Set the HPD interrupt handlers. */ - XDptx_SetHpdEventHandler(InstancePtr, HpdEventHandler, InstancePtr); - XDptx_SetHpdPulseHandler(InstancePtr, HpdPulseHandler, InstancePtr); + XDp_TxSetHpdEventHandler(InstancePtr, HpdEventHandler, InstancePtr); + XDp_TxSetHpdPulseHandler(InstancePtr, HpdPulseHandler, InstancePtr); /* Initialize interrupt controller driver. */ #ifdef XPAR_INTC_0_DEVICE_ID @@ -264,10 +265,10 @@ static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr, * the specific interrupt processing for the device. */ #ifdef XPAR_INTC_0_DEVICE_ID Status = XIntc_Connect(IntcPtr, DpIntrId, - (XInterruptHandler)XDptx_HpdInterruptHandler, InstancePtr); + (XInterruptHandler)XDp_InterruptHandler, InstancePtr); #else Status = XScuGic_Connect(IntcPtr, DpIntrId, - (Xil_InterruptHandler)XDptx_HpdInterruptHandler, InstancePtr); + (Xil_InterruptHandler)XDp_InterruptHandler, InstancePtr); #endif /* XPAR_INTC_0_DEVICE_ID */ if (Status != XST_SUCCESS) { return XST_FAILURE; @@ -300,26 +301,26 @@ static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr, /******************************************************************************/ /** * This function is called when a Hot-Plug-Detect (HPD) event is received by the - * DisplayPort TX core. The XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK bit of the - * core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has + * DisplayPort TX core. The XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK bit of the + * core's XDP_TX_INTERRUPT_STATUS register indicates that an HPD event has * occurred. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * - * @note Use the XDptx_SetHpdEventHandler driver function to set this + * @note Use the XDp_TxSetHpdEventHandler driver function to set this * function as the handler for HPD pulses. * *******************************************************************************/ static void Dptx_HpdEventHandler(void *InstancePtr) { - XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr; + XDp *XDp_InstancePtr = (XDp *)InstancePtr; - if (XDptx_IsConnected(XDptx_InstancePtr)) { + if (XDp_TxIsConnected(XDp_InstancePtr)) { xil_printf("+===> HPD connection event detected.\n"); - Dptx_Run(XDptx_InstancePtr); + Dptx_Run(XDp_InstancePtr); } else { xil_printf("+===> HPD disconnection event detected.\n\n"); @@ -329,23 +330,23 @@ static void Dptx_HpdEventHandler(void *InstancePtr) /******************************************************************************/ /** * This function is called when a Hot-Plug-Detect (HPD) pulse is received by the - * DisplayPort TX core. The XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit - * of the core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has - * occurred. + * DisplayPort TX core. The XDP_TX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit + * of the core's XDP_TX_INTERRUPT_STATUS register indicates that an HPD event + * has occurred. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * - * @note Use the XDptx_SetHpdPulseHandler driver function to set this + * @note Use the XDp_TxSetHpdPulseHandler driver function to set this * function as the handler for HPD pulses. * *******************************************************************************/ static void Dptx_HpdPulseHandler(void *InstancePtr) { - XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr; + XDp *XDp_InstancePtr = (XDp *)InstancePtr; xil_printf("===> HPD pulse detected.\n"); - Dptx_Run(XDptx_InstancePtr); + Dptx_Run(XDp_InstancePtr); } diff --git a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_mst_example.c b/XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_mst_example.c similarity index 69% rename from XilinxProcessorIPLib/drivers/dp/examples/xdptx_mst_example.c rename to XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_mst_example.c index d5ffe00d..1a257f65 100644 --- a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_mst_example.c +++ b/XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_mst_example.c @@ -32,10 +32,10 @@ /******************************************************************************/ /** * - * @file xdptx_mst_example.c + * @file xdp_tx_mst_example.c * - * Contains a design example using the XDptx driver in multi-stream transport - * (MST) mode. + * Contains a design example using the XDp driver (operating in TX mode) in + * multi-stream transport (MST) mode. * * @note For this example to display output, the user will need to * implement initialization of the system (Dptx_PlatformInit) and, @@ -43,7 +43,7 @@ * stream source in order to provide the DisplayPort core with * input. See XAPP1178 for reference. * @note The functions Dptx_PlatformInit and Dptx_StreamSrc* are declared - * extern in xdptx_example_common.h and are left up to the user to + * extern in xdp_tx_example_common.h and are left up to the user to * implement. * @note Some setups may require introduction of delays when sending * sideband messages. @@ -53,15 +53,14 @@ * * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- - * 1.0 als 08/07/14 Initial creation. - * 2.0 als 09/23/14 Improved programming sequence for payload allocation. + * 1.0 als 01/20/15 Initial creation. * * *******************************************************************************/ /******************************* Include Files ********************************/ -#include "xdptx_example_common.h" +#include "xdp_tx_example_common.h" /**************************** Constant Definitions ****************************/ @@ -71,21 +70,21 @@ /* This enables topology discovery which will create a list of sinks in the * topology. If ALLOCATE_FROM_SINKLIST is defined, the streams will sent to * to the sinks with the corresponding index. See the function calls for - * the XDptx_SetStreamSelectFromSinkList driver function below. */ + * the XDp_TxSetStreamSelectFromSinkList driver function below. */ #define ALLOCATE_FROM_SINKLIST #ifdef ALLOCATE_FROM_SINKLIST /* Define the mapping between sinks and streams. The sink numbers are in the - * order that they are discovered by the XDptx_FindAccessibleDpDevices driver + * order that they are discovered by the XDp_TxFindAccessibleDpDevices driver * function. */ -#define STREAM0_USE_SINKNUM 0 -#define STREAM1_USE_SINKNUM 1 -#define STREAM2_USE_SINKNUM 2 -#define STREAM3_USE_SINKNUM 3 +#define STREAM1_USE_SINKNUM 0 +#define STREAM2_USE_SINKNUM 1 +#define STREAM3_USE_SINKNUM 2 +#define STREAM4_USE_SINKNUM 3 #endif /* The video resolution from the display mode timings (DMT) table to use for * each stream. */ -#define USE_VIDEO_MODE XDPTX_VM_1920x1080_60_P +#define USE_VIDEO_MODE XVIDC_VM_1920x1080_60_P /* The color depth (bits per color component) to use for each stream. */ #define USE_BPC 8 @@ -96,8 +95,8 @@ /**************************** Function Prototypes *****************************/ -u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId); -u32 Dptx_MstExampleRun(XDptx *InstancePtr); +u32 Dptx_MstExample(XDp *InstancePtr, u16 DeviceId); +u32 Dptx_MstExampleRun(XDp *InstancePtr); /**************************** Function Definitions ****************************/ @@ -119,7 +118,7 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr); int main(void) { /* Run the XDptx MST example. */ - Dptx_MstExample(&DptxInstance, DPTX_DEVICE_ID); + Dptx_MstExample(&DpInstance, DPTX_DEVICE_ID); return XST_FAILURE; } @@ -127,10 +126,10 @@ int main(void) /******************************************************************************/ /** * The main entry point for the multi-stream transport (MST) example using the - * XDptx driver. This function will either discover the topology and map streams + * XDp driver. This function will either discover the topology and map streams * to the sinks in the sink list, or map streams to relative addresses. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param DeviceId is the unique device ID of the DisplayPort TX core * instance. * @@ -142,7 +141,7 @@ int main(void) * @note If system setup was successful, this function is blocking. * *******************************************************************************/ -u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId) +u32 Dptx_MstExample(XDp *InstancePtr, u16 DeviceId) { u32 Status; @@ -156,7 +155,7 @@ u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId) return XST_FAILURE; } - Status = XDptx_MstCapable(InstancePtr); + Status = XDp_TxMstCapable(InstancePtr); if (Status != XST_SUCCESS) { /* If the immediate downstream RX device is an MST monitor and * the DisplayPort Configuration Data (DPCD) does not indicate @@ -187,7 +186,7 @@ u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId) /** * This function trains the link and allocates stream payloads. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param DeviceId is the unique device ID of the DisplayPort TX core * instance. * @@ -199,12 +198,12 @@ u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId) * @note None. * *******************************************************************************/ -u32 Dptx_MstExampleRun(XDptx *InstancePtr) +u32 Dptx_MstExampleRun(XDp *InstancePtr) { u32 Status; u32 MaskVal; u8 StreamIndex; - XDptx_VideoMode VideoMode = USE_VIDEO_MODE; + XVidC_VideoMode VideoMode = USE_VIDEO_MODE; u8 Bpc = USE_BPC; u8 NumStreams = NUM_STREAMS; @@ -214,8 +213,8 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr) NumStreams = InstancePtr->Config.NumMstStreams; } - XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE); - XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER); + XDp_TxEnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE); + XDp_TxSetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER); /* A DisplayPort connection must exist at this point. See the interrupt * and polling examples for waiting for connection events. */ @@ -226,26 +225,26 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr) } #ifdef USE_DELAYS_FOR_MST - InstancePtr->AuxDelayUs = 30000; - InstancePtr->SbMsgDelayUs = 100000; + InstancePtr->TxInstance.AuxDelayUs = 30000; + InstancePtr->TxInstance.SbMsgDelayUs = 100000; #else - InstancePtr->AuxDelayUs = 0; - InstancePtr->SbMsgDelayUs = 0; + InstancePtr->TxInstance.AuxDelayUs = 0; + InstancePtr->TxInstance.SbMsgDelayUs = 0; #endif - XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID0); - XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID1); - XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID2); - XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID3); + XDp_TxClearMsaValues(InstancePtr, XDP_TX_STREAM_ID1); + XDp_TxClearMsaValues(InstancePtr, XDP_TX_STREAM_ID2); + XDp_TxClearMsaValues(InstancePtr, XDP_TX_STREAM_ID3); + XDp_TxClearMsaValues(InstancePtr, XDP_TX_STREAM_ID4); #ifdef ALLOCATE_FROM_SINKLIST /* Run topology discovery to determine what devices are accessible to * the DisplayPort TX. */ xil_printf("Find topology >>>\n"); - InstancePtr->Topology.NodeTotal = 0; - InstancePtr->Topology.SinkTotal = 0; + InstancePtr->TxInstance.Topology.NodeTotal = 0; + InstancePtr->TxInstance.Topology.SinkTotal = 0; - Status = XDptx_DiscoverTopology(InstancePtr); + Status = XDp_TxDiscoverTopology(InstancePtr); if (Status != XST_SUCCESS) { xil_printf("!!! A LINK_ADDRESS response from a branch device " "in the MST topology was not successfully received.\n"); @@ -253,21 +252,21 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr) } xil_printf("<<< Find topology DONE; # of sinks found = %d.\n", - InstancePtr->Topology.SinkTotal); + InstancePtr->TxInstance.Topology.SinkTotal); - if (NumStreams > InstancePtr->Topology.SinkTotal) { - NumStreams = InstancePtr->Topology.SinkTotal; + if (NumStreams > InstancePtr->TxInstance.Topology.SinkTotal) { + NumStreams = InstancePtr->TxInstance.Topology.SinkTotal; } #endif /* Enable multi-stream transport (MST) mode for this example. */ - XDptx_MstCfgModeEnable(InstancePtr); + XDp_TxMstCfgModeEnable(InstancePtr); for (StreamIndex = 0; StreamIndex < NumStreams; StreamIndex++) { - XDptx_MstCfgStreamEnable(InstancePtr, XDPTX_STREAM_ID0 + + XDp_TxMstCfgStreamEnable(InstancePtr, XDP_TX_STREAM_ID1 + StreamIndex); } for (StreamIndex = NumStreams; StreamIndex < 4; StreamIndex++) { - XDptx_MstCfgStreamDisable(InstancePtr, XDPTX_STREAM_ID0 + + XDp_TxMstCfgStreamDisable(InstancePtr, XDP_TX_STREAM_ID1 + StreamIndex); } @@ -279,63 +278,67 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr) u8 Lct; u8 Rad[15]; - if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID0)) { + if (XDp_TxMstStreamIsEnabled(InstancePtr, XDP_TX_STREAM_ID1)) { Lct = 2; Rad[0] = 8; - XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID0, Lct, Rad); + XDp_TxSetStreamSinkRad(InstancePtr, XDP_TX_STREAM_ID1, Lct, + Rad); } - if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) { + if (XDp_TxMstStreamIsEnabled(InstancePtr, XDP_TX_STREAM_ID2)) { Lct = 3; Rad[0] = 1; Rad[1] = 8; - XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID1, Lct, Rad); + XDp_TxSetStreamSinkRad(InstancePtr, XDP_TX_STREAM_ID2, Lct, + Rad); } - if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID2)) { + if (XDp_TxMstStreamIsEnabled(InstancePtr, XDP_TX_STREAM_ID3)) { Lct = 4; Rad[0] = 1; Rad[1] = 1; Rad[2] = 8; - XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID2, Lct, Rad); + XDp_TxSetStreamSinkRad(InstancePtr, XDP_TX_STREAM_ID3, Lct, + Rad); } - if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID3)) { + if (XDp_TxMstStreamIsEnabled(InstancePtr, XDP_TX_STREAM_ID4)) { Lct = 4; Rad[0] = 1; Rad[1] = 1; Rad[2] = 9; - XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID3, Lct, Rad); + XDp_TxSetStreamSinkRad(InstancePtr, XDP_TX_STREAM_ID4, Lct, + Rad); } #else /* If topology discovery is used, associate a stream number with a sink * number from the sink list obtained during topology discovery. The * sinks are numbered in the order that they were found during topology * discovery. */ - if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID0)) { - XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID0, - STREAM0_USE_SINKNUM); + if (XDp_TxMstStreamIsEnabled(InstancePtr, XDP_TX_STREAM_ID1)) { + XDp_TxSetStreamSelectFromSinkList(InstancePtr, + XDP_TX_STREAM_ID1, STREAM1_USE_SINKNUM); } - if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) { - XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID1, - STREAM1_USE_SINKNUM); + if (XDp_TxMstStreamIsEnabled(InstancePtr, XDP_TX_STREAM_ID2)) { + XDp_TxSetStreamSelectFromSinkList(InstancePtr, + XDP_TX_STREAM_ID2, STREAM2_USE_SINKNUM); } - if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID2)) { - XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID2, - STREAM2_USE_SINKNUM); + if (XDp_TxMstStreamIsEnabled(InstancePtr, XDP_TX_STREAM_ID3)) { + XDp_TxSetStreamSelectFromSinkList(InstancePtr, + XDP_TX_STREAM_ID3, STREAM3_USE_SINKNUM); } - if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID3)) { - XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID3, - STREAM3_USE_SINKNUM); + if (XDp_TxMstStreamIsEnabled(InstancePtr, XDP_TX_STREAM_ID4)) { + XDp_TxSetStreamSelectFromSinkList(InstancePtr, + XDP_TX_STREAM_ID4, STREAM4_USE_SINKNUM); } #endif /* Reset MST mode in both the RX and TX. */ - XDptx_MstDisable(InstancePtr); - XDptx_MstEnable(InstancePtr); + XDp_TxMstDisable(InstancePtr); + XDp_TxMstEnable(InstancePtr); /* Set the main stream attributes (MSA) for each enabled stream (each * stream has an identical configuration). Then, set the configuration * for that stream in the corresponding DisplayPort TX registers. */ for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) { - if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID0 + - StreamIndex)) { - XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID0 + + if (XDp_TxMstStreamIsEnabled(InstancePtr, + XDP_TX_STREAM_ID1 + StreamIndex)) { + XDp_TxCfgMsaSetBpc(InstancePtr, XDP_TX_STREAM_ID1 + StreamIndex, Bpc); - XDptx_CfgMsaEnSynchClkMode(InstancePtr, - XDPTX_STREAM_ID0 + StreamIndex, 1); + XDp_TxCfgMsaEnSynchClkMode(InstancePtr, + XDP_TX_STREAM_ID1 + StreamIndex, 1); - XDptx_CfgMsaUseStandardVideoMode(InstancePtr, - XDPTX_STREAM_ID0 + StreamIndex, VideoMode); - XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID0 + + XDp_TxCfgMsaUseStandardVideoMode(InstancePtr, + XDP_TX_STREAM_ID1 + StreamIndex, VideoMode); + XDp_TxSetVideoMode(InstancePtr, XDP_TX_STREAM_ID1 + StreamIndex); } } @@ -349,35 +352,34 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr) //////////////////////////////////// /* Mask interrupts while allocating payloads. */ - MaskVal = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_INTERRUPT_MASK); - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_INTERRUPT_MASK, - 0x3F); + MaskVal = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_INTERRUPT_MASK); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_INTERRUPT_MASK, 0x3F); /* Clear the payload ID table first. */ - Status = XDptx_ClearPayloadVcIdTable(InstancePtr); + Status = XDp_TxClearPayloadVcIdTable(InstancePtr); if (Status != XST_SUCCESS) { return XST_DATA_LOST; } /* Allocate payloads. */ - Status = XDptx_AllocatePayloadStreams(InstancePtr); + Status = XDp_TxAllocatePayloadStreams(InstancePtr); if (Status != XST_SUCCESS) { return XST_DATA_LOST; } /* Enable the main link. */ - XDptx_EnableMainLink(InstancePtr); + XDp_TxEnableMainLink(InstancePtr); /* Unmask interrupts. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_INTERRUPT_MASK, + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_INTERRUPT_MASK, MaskVal); /* Do a final check to verify that the link wasn't lost. */ - Status = XDptx_CheckLinkStatus(InstancePtr, - InstancePtr->LinkConfig.LaneCount); + Status = XDp_TxCheckLinkStatus(InstancePtr, + InstancePtr->TxInstance.LinkConfig.LaneCount); if (Status != XST_SUCCESS) { - XDptx_WaitUs(InstancePtr, 10000); + XDp_WaitUs(InstancePtr, 10000); return XST_DATA_LOST; } diff --git a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_poll_example.c b/XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_poll_example.c similarity index 73% rename from XilinxProcessorIPLib/drivers/dp/examples/xdptx_poll_example.c rename to XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_poll_example.c index 333f6c7b..d93b630f 100644 --- a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_poll_example.c +++ b/XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_poll_example.c @@ -32,20 +32,21 @@ /******************************************************************************/ /** * - * @file xdptx_poll_example.c + * @file xdp_tx_poll_example.c * - * Contains a design example using the XDptx driver with polling. Once the - * polling detects a Hot-Plug-Detect event (HPD - DisplayPort cable is plugged/ - * unplugged or the monitor is turned on/off), the main link will be trained. + * Contains a design example using the XDp driver (operating in TX mode) with + * polling. Once the polling detects a Hot-Plug-Detect event (HPD - DisplayPort + * cable is plugged/unplugged or the monitor is turned on/off), the main link + * will be trained. * * @note For this example to display output, the user will need to * implement initialization of the system (Dptx_PlatformInit) and, * after training is complete, implement configuration of the video * stream source in order to provide the DisplayPort core with - * input (Dptx_StreamSrc* - called in xdptx_example_common.c). See + * input (Dptx_StreamSrc* - called in xdp_tx_example_common.c). See * XAPP1178 for reference. * @note The functions Dptx_PlatformInit and Dptx_StreamSrc* are declared - * extern in xdptx_example_common.h and are left up to the user to + * extern in xdp_tx_example_common.h and are left up to the user to * implement. * *
@@ -53,25 +54,25 @@
  *
  * Ver   Who  Date     Changes
  * ----- ---- -------- -----------------------------------------------
- * 1.0   als  06/17/14 Initial creation.
+ * 1.0   als  01/20/15 Initial creation.
  * 
* *******************************************************************************/ /******************************* Include Files ********************************/ -#include "xdptx_example_common.h" +#include "xdp_tx_example_common.h" /**************************** Function Prototypes *****************************/ -u32 Dptx_PollExample(XDptx *InstancePtr, u16 DeviceId); -static void Dptx_HpdPoll(XDptx *InstancePtr); +u32 Dptx_PollExample(XDp *InstancePtr, u16 DeviceId); +static void Dptx_HpdPoll(XDp *InstancePtr); /**************************** Function Definitions ****************************/ /******************************************************************************/ /** - * This function is the main function of the XDptx polling example. + * This function is the main function of the XDp polling example. * * @param None. * @@ -86,21 +87,21 @@ static void Dptx_HpdPoll(XDptx *InstancePtr); *******************************************************************************/ int main(void) { - /* Run the XDptx polling example. */ - Dptx_PollExample(&DptxInstance, DPTX_DEVICE_ID); + /* Run the XDp polling example. */ + Dptx_PollExample(&DpInstance, DPTX_DEVICE_ID); return XST_FAILURE; } /******************************************************************************/ /** - * The main entry point for the polling example using the XDptx driver. This + * The main entry point for the polling example using the XDp driver. This * function will set up the system. If this is successful, this example will * begin polling the Hot-Plug-Detect (HPD) status registers for HPD events. Once * a connection event or a pulse is detected, link training will commence (if * needed) and a video stream will start being sent over the main link. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param DeviceId is the unique device ID of the DisplayPort TX core * instance. * @@ -113,7 +114,7 @@ int main(void) * order to illustrate polling taking place for HPD events. * *******************************************************************************/ -u32 Dptx_PollExample(XDptx *InstancePtr, u16 DeviceId) +u32 Dptx_PollExample(XDp *InstancePtr, u16 DeviceId) { u32 Status; @@ -127,8 +128,8 @@ u32 Dptx_PollExample(XDptx *InstancePtr, u16 DeviceId) return XST_FAILURE; } - XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE); - XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER); + XDp_TxEnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE); + XDp_TxSetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER); /* Continuously poll for HPD events. */ while (1) { @@ -140,19 +141,19 @@ u32 Dptx_PollExample(XDptx *InstancePtr, u16 DeviceId) /******************************************************************************/ /** - * This function polls the XDPTX_INTERRUPT_SIG_STATE and XDPTX_INTERRUPT_STATUS - * registers for Hot-Plug-Detect (HPD) events and handles them accordingly. If a - * connection or pulse event is detected, link training will begin (if required) - * and a video stream will be initiated. + * This function polls the XDP_TX_INTERRUPT_SIG_STATE and + * XDP_TX_INTERRUPT_STATUS registers for Hot-Plug-Detect (HPD) events and + * handles them accordingly. If a connection or pulse event is detected, link + * training will begin (if required) and a video stream will be initiated. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * * @note None. * *******************************************************************************/ -static void Dptx_HpdPoll(XDptx *InstancePtr) +static void Dptx_HpdPoll(XDp *InstancePtr) { u32 InterruptSignalState; u32 InterruptStatus; @@ -162,20 +163,20 @@ static void Dptx_HpdPoll(XDptx *InstancePtr) u32 HpdDuration; /* Read interrupt registers. */ - InterruptSignalState = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_INTERRUPT_SIG_STATE); - InterruptStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_INTERRUPT_STATUS); + InterruptSignalState = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_INTERRUPT_SIG_STATE); + InterruptStatus = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_INTERRUPT_STATUS); /* Check for HPD events. */ HpdState = InterruptSignalState & - XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK; - HpdEvent = InterruptStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK; + XDP_TX_INTERRUPT_SIG_STATE_HPD_STATE_MASK; + HpdEvent = InterruptStatus & XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK; HpdPulseDetected = InterruptStatus & - XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK; + XDP_TX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK; if (HpdPulseDetected) { - HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_HPD_DURATION); + HpdDuration = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_HPD_DURATION); } /* HPD event handling. */ @@ -195,6 +196,6 @@ static void Dptx_HpdPoll(XDptx *InstancePtr) xil_printf("+===> HPD disconnection event detected.\n\n"); /* Disable main link. */ - XDptx_DisableMainLink(InstancePtr); + XDp_TxDisableMainLink(InstancePtr); } } diff --git a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_timer_example.c b/XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_timer_example.c similarity index 76% rename from XilinxProcessorIPLib/drivers/dp/examples/xdptx_timer_example.c rename to XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_timer_example.c index 541e73e9..3ee378f5 100644 --- a/XilinxProcessorIPLib/drivers/dp/examples/xdptx_timer_example.c +++ b/XilinxProcessorIPLib/drivers/dp/examples/xdp_tx_timer_example.c @@ -32,23 +32,23 @@ /******************************************************************************/ /** * - * @file xdptx_timer_example.c + * @file xdp_tx_timer_example.c * - * Contains a design example using the XDptx driver with a user-defined hook - * for delay. The reasoning behind this is that MicroBlaze sleep is not very - * accurate without a hardware timer. For systems that have a hardware timer, - * the user may override the default MicroBlaze sleep with a function that will - * use the hardware timer. + * Contains a design example using the XDp driver (operating in TX mode) with a + * user-defined hook for delay. The reasoning behind this is that MicroBlaze + * sleep is not very accurate without a hardware timer. For systems that have a + * hardware timer, the user may override the default MicroBlaze sleep with a + * function that will use the hardware timer. * * @note This example requires an AXI timer in the system. * @note For this example to display output, the user will need to * implement initialization of the system (Dptx_PlatformInit) and, * after training is complete, implement configuration of the video * stream source in order to provide the DisplayPort core with - * input (Dptx_StreamSrc* - called in xdptx_example_common.c). See + * input (Dptx_StreamSrc* - called in xdp_tx_example_common.c). See * XAPP1178 for reference. * @note The functions Dptx_PlatformInit and Dptx_StreamSrc* are declared - * extern in xdptx_example_common.h and are left up to the user to + * extern in xdp_tx_example_common.h and are left up to the user to * implement. * *
@@ -56,20 +56,20 @@
  *
  * Ver   Who  Date     Changes
  * ----- ---- -------- -----------------------------------------------
- * 1.0   als  06/17/14 Initial creation.
+ * 1.0   als  01/20/15 Initial creation.
  * 
* *******************************************************************************/ /******************************* Include Files ********************************/ -#include "xdptx_example_common.h" +#include "xdp_tx_example_common.h" #include "xtmrctr.h" /**************************** Function Prototypes *****************************/ -u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId, - XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc); +u32 Dptx_TimerExample(XDp *InstancePtr, u16 DeviceId, + XTmrCtr *TimerCounterPtr, XDp_TimerHandler UserSleepFunc); static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds); /*************************** Variable Declarations ****************************/ @@ -96,7 +96,7 @@ int main(void) u32 Status; /* Run the XDptx timer example. */ - Status = Dptx_TimerExample(&DptxInstance, DPTX_DEVICE_ID, + Status = Dptx_TimerExample(&DpInstance, DPTX_DEVICE_ID, &TimerCounterInst, &Dptx_CustomWaitUs); if (Status != XST_SUCCESS) { return XST_FAILURE; @@ -107,12 +107,12 @@ int main(void) /******************************************************************************/ /** - * The main entry point for the timer example using the XDptx driver. This + * The main entry point for the timer example using the XDp driver. This * function will set up the system and the custom sleep handler. If this is * successful, link training will commence and a video stream will start being * sent over the main link. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param DeviceId is the unique device ID of the DisplayPort TX core * instance. * @param TimerCounterPtr is a pointer to the timer instance. @@ -126,13 +126,13 @@ int main(void) * @note None. * *******************************************************************************/ -u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId, - XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc) +u32 Dptx_TimerExample(XDp *InstancePtr, u16 DeviceId, + XTmrCtr *TimerCounterPtr, XDp_TimerHandler UserSleepFunc) { u32 Status; /* Use single-stream transport (SST) mode for this example. */ - XDptx_MstCfgModeDisable(InstancePtr); + XDp_TxMstCfgModeDisable(InstancePtr); /* Do platform initialization here. This is hardware system specific - * it is up to the user to implement this function. */ @@ -145,15 +145,15 @@ u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId, * Note: This only has an affect for MicroBlaze systems since the Zynq * ARM SoC contains a timer, which is used when the driver calls the * delay function. */ - XDptx_SetUserTimerHandler(InstancePtr, UserSleepFunc, TimerCounterPtr); + XDp_SetUserTimerHandler(InstancePtr, UserSleepFunc, TimerCounterPtr); Status = Dptx_SetupExample(InstancePtr, DeviceId); if (Status != XST_SUCCESS) { return XST_FAILURE; } - XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE); - XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER); + XDp_TxEnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE); + XDp_TxSetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER); /* A sink monitor must be connected at this point. See the polling or * interrupt examples for how to wait for a connection event. */ @@ -168,34 +168,34 @@ u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId, /******************************************************************************/ /** * This function is used to override the driver's default sleep functionality. - * For MicroBlaze systems, the XDptx_WaitUs driver function's default behavior + * For MicroBlaze systems, the XDp_WaitUs driver function's default behavior * is to use the MB_Sleep function from microblaze_sleep.h, which is implemented * in software and only has millisecond accuracy. For this reason, using a * hardware timer is preferrable. For ARM/Zynq SoC systems, the SoC's timer is - * used - XDptx_WaitUs will ignore this custom timer handler. + * used - XDp_WaitUs will ignore this custom timer handler. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * - * @note Use the XDptx_SetUserTimerHandler driver function to set this - * function as the handler for when the XDptx_WaitUs driver + * @note Use the XDp_SetUserTimerHandler driver function to set this + * function as the handler for when the XDp_WaitUs driver * function is called. * *******************************************************************************/ static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds) { - XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr; + XDp *XDp_InstancePtr = (XDp *)InstancePtr; u32 TimerVal; - XTmrCtr_Start(XDptx_InstancePtr->UserTimerPtr, 0); + XTmrCtr_Start(XDp_InstancePtr->UserTimerPtr, 0); /* Wait specified number of useconds. */ do { - TimerVal = XTmrCtr_GetValue(XDptx_InstancePtr->UserTimerPtr, 0); + TimerVal = XTmrCtr_GetValue(XDp_InstancePtr->UserTimerPtr, 0); } while (TimerVal < (MicroSeconds * - (XDptx_InstancePtr->Config.SAxiClkHz / 1000000))); + (XDp_InstancePtr->Config.SAxiClkHz / 1000000))); - XTmrCtr_Stop(XDptx_InstancePtr->UserTimerPtr, 0); + XTmrCtr_Stop(XDp_InstancePtr->UserTimerPtr, 0); } diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdptx.c b/XilinxProcessorIPLib/drivers/dp/src/xdp.c similarity index 58% rename from XilinxProcessorIPLib/drivers/dp/src/xdptx.c rename to XilinxProcessorIPLib/drivers/dp/src/xdp.c index be4638be..34b5be6c 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdptx.c +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp.c @@ -1,6 +1,6 @@ /******************************************************************************* * - * Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,10 +32,10 @@ /******************************************************************************/ /** * - * @file xdptx.c + * @file xdp.c * - * Contains a minimal set of functions for the XDptx driver that allow access - * to all of the DisplayPort TX core's functionality. See xdptx.h for a detailed + * Contains a minimal set of functions for the XDp driver that allow access to + * all of the DisplayPort core's functionality. See xdp.h for a detailed * description of the driver. * * @note None. @@ -45,20 +45,14 @@ * * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- - * 1.0 als 05/17/14 Initial release. - * 2.0 als 09/21/14 Added XDptx_IsConnected (previously a macro). - * 3.0 als 12/16/14 Fixed XDptx_WaitPhyReady for maximum lane counts != 4. - * Force re-train during XDptx_EstablishLink. - * Modified XDptx_SetVswingPreemp usage to enable more - * efficient use of burst writes to a sink DPCD. + * 1.0 als 01/20/15 Initial release. * * *******************************************************************************/ /******************************* Include Files ********************************/ -#include "xdptx.h" -#include "xstatus.h" +#include "xdp.h" #if defined(__arm__) #include "sleep.h" #elif defined(__MICROBLAZE__) @@ -69,16 +63,16 @@ /**************************** Constant Definitions ****************************/ /* The maximum voltage swing level is 3. */ -#define XDPTX_MAXIMUM_VS_LEVEL 3 +#define XDP_TX_MAXIMUM_VS_LEVEL 3 /* The maximum pre-emphasis level is 3. */ -#define XDPTX_MAXIMUM_PE_LEVEL 3 +#define XDP_TX_MAXIMUM_PE_LEVEL 3 /* Error out if an AUX request yields a defer reply more than 50 times. */ -#define XDPTX_AUX_MAX_DEFER_COUNT 50 +#define XDP_AUX_MAX_DEFER_COUNT 50 /* Error out if an AUX request times out more than 50 times awaiting a reply. */ -#define XDPTX_AUX_MAX_TIMEOUT_COUNT 50 +#define XDP_AUX_MAX_TIMEOUT_COUNT 50 /* Error out if checking for a connected device times out more than 50 times. */ -#define XDPTX_IS_CONNECTED_MAX_TIMEOUT_COUNT 50 +#define XDP_IS_CONNECTED_MAX_TIMEOUT_COUNT 50 /****************************** Type Definitions ******************************/ @@ -87,13 +81,13 @@ * during the link training process. */ typedef enum { - XDPTX_TS_CLOCK_RECOVERY, - XDPTX_TS_CHANNEL_EQUALIZATION, - XDPTX_TS_ADJUST_LINK_RATE, - XDPTX_TS_ADJUST_LANE_COUNT, - XDPTX_TS_FAILURE, - XDPTX_TS_SUCCESS -} XDptx_TrainingState; + XDP_TX_TS_CLOCK_RECOVERY, + XDP_TX_TS_CHANNEL_EQUALIZATION, + XDP_TX_TS_ADJUST_LINK_RATE, + XDP_TX_TS_ADJUST_LANE_COUNT, + XDP_TX_TS_FAILURE, + XDP_TX_TS_SUCCESS +} XDp_TxTrainingState; /** * This typedef describes an AUX transaction. @@ -110,47 +104,50 @@ typedef struct { read from AUX read transactions or the data to write for AUX write transactions. */ -} XDptx_AuxTransaction; +} XDp_AuxTransaction; /**************************** Function Prototypes *****************************/ +/* Initialization functions. */ +static u32 XDp_TxInitialize(XDp *InstancePtr); +static u32 XDp_RxInitialize(XDp *InstancePtr); + /* Training functions. */ -static u32 XDptx_RunTraining(XDptx *InstancePtr); -static XDptx_TrainingState XDptx_TrainingStateClockRecovery(XDptx *InstancePtr); -static XDptx_TrainingState XDptx_TrainingStateChannelEqualization( - XDptx *InstancePtr); -static XDptx_TrainingState XDptx_TrainingStateAdjustLinkRate( - XDptx *InstancePtr); -static XDptx_TrainingState XDptx_TrainingStateAdjustLaneCount( - XDptx *InstancePtr); -static u32 XDptx_GetLaneStatusAdjReqs(XDptx *InstancePtr); -static u32 XDptx_CheckClockRecovery(XDptx *InstancePtr, u8 LaneCount); -static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount); -static void XDptx_SetVswingPreemp(XDptx *InstancePtr, u8 *AuxData); -static u32 XDptx_AdjVswingPreemp(XDptx *InstancePtr); -static u32 XDptx_SetTrainingPattern(XDptx *InstancePtr, u32 Pattern); -static u32 XDptx_GetTrainingDelay(XDptx *InstancePtr, - XDptx_TrainingState TrainingState); +static u32 XDp_TxRunTraining(XDp *InstancePtr); +static XDp_TxTrainingState XDp_TxTrainingStateClockRecovery(XDp *InstancePtr); +static XDp_TxTrainingState XDp_TxTrainingStateChannelEqualization( + XDp *InstancePtr); +static XDp_TxTrainingState XDp_TxTrainingStateAdjustLinkRate( + XDp *InstancePtr); +static XDp_TxTrainingState XDp_TxTrainingStateAdjustLaneCount( + XDp *InstancePtr); +static u32 XDp_TxGetLaneStatusAdjReqs(XDp *InstancePtr); +static u32 XDp_TxCheckClockRecovery(XDp *InstancePtr, u8 LaneCount); +static u32 XDp_TxCheckChannelEqualization(XDp *InstancePtr, u8 LaneCount); +static void XDp_TxSetVswingPreemp(XDp *InstancePtr, u8 *AuxData); +static u32 XDp_TxAdjVswingPreemp(XDp *InstancePtr); +static u32 XDp_TxSetTrainingPattern(XDp *InstancePtr, u32 Pattern); +static u32 XDp_TxGetTrainingDelay(XDp *InstancePtr, + XDp_TxTrainingState TrainingState); /* AUX transaction functions. */ -static u32 XDptx_AuxCommon(XDptx *InstancePtr, u32 CmdType, u32 Address, +static u32 XDp_TxAuxCommon(XDp *InstancePtr, u32 CmdType, u32 Address, u32 NumBytes, u8 *Data); -static u32 XDptx_AuxRequest(XDptx *InstancePtr, XDptx_AuxTransaction *Request); -static u32 XDptx_AuxRequestSend(XDptx *InstancePtr, - XDptx_AuxTransaction *Request); -static u32 XDptx_AuxWaitReply(XDptx *InstancePtr); -static u32 XDptx_AuxWaitReady(XDptx *InstancePtr); +static u32 XDp_TxAuxRequest(XDp *InstancePtr, XDp_AuxTransaction *Request); +static u32 XDp_TxAuxRequestSend(XDp *InstancePtr, XDp_AuxTransaction *Request); +static u32 XDp_TxAuxWaitReply(XDp *InstancePtr); +static u32 XDp_TxAuxWaitReady(XDp *InstancePtr); /* Miscellaneous functions. */ -static u32 XDptx_SetClkSpeed(XDptx *InstancePtr, u32 Speed); -static u32 XDptx_WaitPhyReady(XDptx *InstancePtr); +static u32 XDp_TxSetClkSpeed(XDp *InstancePtr, u32 Speed); +static u32 XDp_WaitPhyReady(XDp *InstancePtr, u32 Mask); /**************************** Function Definitions ****************************/ /******************************************************************************/ /** - * This function retrieves the configuration for this DisplayPort TX instance - * and fills in the InstancePtr->Config structure. + * This function retrieves the configuration for this DisplayPort instance and + * fills in the InstancePtr->Config structure. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param ConfigPtr is a pointer to the configuration structure that will * be used to copy the settings from. * @param EffectiveAddr is the device base address in the virtual memory @@ -163,7 +160,7 @@ static u32 XDptx_WaitPhyReady(XDptx *InstancePtr); * after this function is invoked. * *******************************************************************************/ -void XDptx_CfgInitialize(XDptx *InstancePtr, XDp_Config *ConfigPtr, +void XDp_CfgInitialize(XDp *InstancePtr, XDp_Config *ConfigPtr, u32 EffectiveAddr) { /* Verify arguments. */ @@ -197,101 +194,54 @@ void XDptx_CfgInitialize(XDptx *InstancePtr, XDp_Config *ConfigPtr, InstancePtr->Config.IsRx = ConfigPtr->IsRx; - /* Set the DisplayPort TX's voltage swing and pre-emphasis levels to - * their defaults. */ - XDptx_CfgTxVsOffset(InstancePtr, XDPTX_VS_LEVEL_OFFSET); - XDptx_CfgTxVsLevel(InstancePtr, 0, XDPTX_VS_LEVEL_0); - XDptx_CfgTxVsLevel(InstancePtr, 1, XDPTX_VS_LEVEL_1); - XDptx_CfgTxVsLevel(InstancePtr, 2, XDPTX_VS_LEVEL_2); - XDptx_CfgTxVsLevel(InstancePtr, 3, XDPTX_VS_LEVEL_3); - XDptx_CfgTxPeLevel(InstancePtr, 0, XDPTX_PE_LEVEL_0); - XDptx_CfgTxPeLevel(InstancePtr, 1, XDPTX_PE_LEVEL_1); - XDptx_CfgTxPeLevel(InstancePtr, 2, XDPTX_PE_LEVEL_2); - XDptx_CfgTxPeLevel(InstancePtr, 3, XDPTX_PE_LEVEL_3); + if (XDp_CfgGetCoreType(ConfigPtr) == XDP_TX) { + /* Set the DisplayPort TX's voltage swing and pre-emphasis + * levels to their defaults. */ + XDp_TxCfgTxVsOffset(InstancePtr, XDP_TX_VS_LEVEL_OFFSET); + XDp_TxCfgTxVsLevel(InstancePtr, 0, XDP_TX_VS_LEVEL_0); + XDp_TxCfgTxVsLevel(InstancePtr, 1, XDP_TX_VS_LEVEL_1); + XDp_TxCfgTxVsLevel(InstancePtr, 2, XDP_TX_VS_LEVEL_2); + XDp_TxCfgTxVsLevel(InstancePtr, 3, XDP_TX_VS_LEVEL_3); + XDp_TxCfgTxPeLevel(InstancePtr, 0, XDP_TX_PE_LEVEL_0); + XDp_TxCfgTxPeLevel(InstancePtr, 1, XDP_TX_PE_LEVEL_1); + XDp_TxCfgTxPeLevel(InstancePtr, 2, XDP_TX_PE_LEVEL_2); + XDp_TxCfgTxPeLevel(InstancePtr, 3, XDP_TX_PE_LEVEL_3); + } InstancePtr->IsReady = XIL_COMPONENT_IS_READY; } /******************************************************************************/ /** - * This function prepares the DisplayPort TX core for use. + * This function prepares the DisplayPort core for use depending on whether the + * core is operating in TX or RX mode. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return - * - XST_SUCCESS if the DisplayPort TX core was successfully + * - XST_SUCCESS if the DisplayPort core was successfully * initialized. * - XST_FAILURE otherwise. * * @note None. * *******************************************************************************/ -u32 XDptx_InitializeTx(XDptx *InstancePtr) +u32 XDp_Initialize(XDp *InstancePtr) { u32 Status; - u32 RegVal; - XDp_Config *Config = &InstancePtr->Config; /* Verify arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - /* Place the PHY (and GTTXRESET) into reset. */ - XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CONFIG, - XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK); - - /* Reset the video streams and AUX logic. */ - XDptx_WriteReg(Config->BaseAddr, XDPTX_SOFT_RESET, - XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK | - XDPTX_SOFT_RESET_AUX_MASK); - - /* Disable the DisplayPort TX core. */ - XDptx_WriteReg(Config->BaseAddr, XDPTX_ENABLE, 0); - - /* Set the clock divider. */ - RegVal = (XDptx_ReadReg(Config->BaseAddr, XDPTX_AUX_CLK_DIVIDER) & - ~XDPTX_AUX_CLK_DIVIDER_VAL_MASK) | - (Config->SAxiClkHz / 1000000); - XDptx_WriteReg(Config->BaseAddr, XDPTX_AUX_CLK_DIVIDER, RegVal); - - /* Set the DisplayPort TX core's clock speed. */ - switch (Config->MaxLinkRate) { - case XDPTX_LINK_BW_SET_540GBPS: - XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CLOCK_SELECT, - XDPTX_PHY_CLOCK_SELECT_540GBPS); - break; - case XDPTX_LINK_BW_SET_270GBPS: - XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CLOCK_SELECT, - XDPTX_PHY_CLOCK_SELECT_270GBPS); - break; - case XDPTX_LINK_BW_SET_162GBPS: - XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CLOCK_SELECT, - XDPTX_PHY_CLOCK_SELECT_162GBPS); - break; - default: - break; + if (XDp_CfgGetCoreType(&InstancePtr->Config) == XDP_TX) { + Status = XDp_TxInitialize(InstancePtr); + } + else { + Status = XDp_RxInitialize(InstancePtr); } - /* Bring the PHY (and GTTXRESET) out of reset. */ - XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CONFIG, - XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK); - - /* Wait for the PHY to be ready. */ - Status = XDptx_WaitPhyReady(InstancePtr); - if (Status != XST_SUCCESS) { - return XST_FAILURE; - } - - /* Enable the DisplayPort TX core. */ - XDptx_WriteReg(Config->BaseAddr, XDPTX_ENABLE, 1); - - /* Unmask Hot-Plug-Detect (HPD) interrupts. */ - XDptx_WriteReg(Config->BaseAddr, XDPTX_INTERRUPT_MASK, - ~XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK & - ~XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK & - ~XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK); - - return XST_SUCCESS; + return Status; } /******************************************************************************/ @@ -299,7 +249,7 @@ u32 XDptx_InitializeTx(XDptx *InstancePtr) * This function retrieves the RX device's capabilities from the RX device's * DisplayPort Configuration Data (DPCD). * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if the DisplayPort Configuration Data was read @@ -310,12 +260,12 @@ u32 XDptx_InitializeTx(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -u32 XDptx_GetRxCapabilities(XDptx *InstancePtr) +u32 XDp_TxGetRxCapabilities(XDp *InstancePtr) { u32 Status; - u8 *Dpcd = InstancePtr->RxConfig.DpcdRxCapsField; - XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; - XDp_Config *Config = &InstancePtr->Config; + u8 *Dpcd = InstancePtr->TxInstance.RxConfig.DpcdRxCapsField; + XDp_TxLinkConfig *LinkConfig = &InstancePtr->TxInstance.LinkConfig; + XDp_Config *ConfigPtr = &InstancePtr->Config; u8 RxMaxLinkRate; u8 RxMaxLaneCount; @@ -324,32 +274,32 @@ u32 XDptx_GetRxCapabilities(XDptx *InstancePtr) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(Dpcd != NULL); Xil_AssertNonvoid(LinkConfig != NULL); - Xil_AssertNonvoid(Config != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); - if (!XDptx_IsConnected(InstancePtr)) { + if (!XDp_TxIsConnected(InstancePtr)) { return XST_DEVICE_NOT_FOUND; } - Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_RECEIVER_CAP_FIELD_START, + Status = XDp_TxAuxRead(InstancePtr, XDP_DPCD_RECEIVER_CAP_FIELD_START, 16, Dpcd); if (Status != XST_SUCCESS) { return XST_FAILURE; } - RxMaxLinkRate = Dpcd[XDPTX_DPCD_MAX_LINK_RATE]; - RxMaxLaneCount = Dpcd[XDPTX_DPCD_MAX_LANE_COUNT] & - XDPTX_DPCD_MAX_LANE_COUNT_MASK; - LinkConfig->MaxLinkRate = (RxMaxLinkRate > Config->MaxLinkRate) ? - Config->MaxLinkRate : RxMaxLinkRate; - LinkConfig->MaxLaneCount = (RxMaxLaneCount > Config->MaxLaneCount) ? - Config->MaxLaneCount : RxMaxLaneCount; + RxMaxLinkRate = Dpcd[XDP_DPCD_MAX_LINK_RATE]; + RxMaxLaneCount = Dpcd[XDP_DPCD_MAX_LANE_COUNT] & + XDP_DPCD_MAX_LANE_COUNT_MASK; + LinkConfig->MaxLinkRate = (RxMaxLinkRate > ConfigPtr->MaxLinkRate) ? + ConfigPtr->MaxLinkRate : RxMaxLinkRate; + LinkConfig->MaxLaneCount = (RxMaxLaneCount > ConfigPtr->MaxLaneCount) ? + ConfigPtr->MaxLaneCount : RxMaxLaneCount; LinkConfig->SupportEnhancedFramingMode = - Dpcd[XDPTX_DPCD_MAX_LANE_COUNT] & - XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK; + Dpcd[XDP_DPCD_MAX_LANE_COUNT] & + XDP_DPCD_ENHANCED_FRAME_SUPPORT_MASK; LinkConfig->SupportDownspreadControl = - Dpcd[XDPTX_DPCD_MAX_DOWNSPREAD] & - XDPTX_DPCD_MAX_DOWNSPREAD_MASK; + Dpcd[XDP_DPCD_MAX_DOWNSPREAD] & + XDP_DPCD_MAX_DOWNSPREAD_MASK; return XST_SUCCESS; } @@ -359,7 +309,7 @@ u32 XDptx_GetRxCapabilities(XDptx *InstancePtr) * This function determines the common capabilities between the DisplayPort TX * core and the RX device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if main link settings were successfully set. @@ -369,31 +319,31 @@ u32 XDptx_GetRxCapabilities(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -u32 XDptx_CfgMainLinkMax(XDptx *InstancePtr) +u32 XDp_TxCfgMainLinkMax(XDp *InstancePtr) { u32 Status; - XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; + XDp_TxLinkConfig *LinkConfig = &InstancePtr->TxInstance.LinkConfig; /* Verify arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - /* The link rate and lane count will be checked in XDptx_SetLinkRate and - * XDptx_SetLaneCount. */ + /* The link rate and lane count will be checked in XDp_TxSetLinkRate and + * XDp_TxSetLaneCount. */ - if (!XDptx_IsConnected(InstancePtr)) { + if (!XDp_TxIsConnected(InstancePtr)) { return XST_DEVICE_NOT_FOUND; } /* Configure the main link to the maximum common link rate between the * DisplayPort TX core and the RX device. */ - Status = XDptx_SetLinkRate(InstancePtr, LinkConfig->MaxLinkRate); + Status = XDp_TxSetLinkRate(InstancePtr, LinkConfig->MaxLinkRate); if (Status != XST_SUCCESS) { return Status; } /* Configure the main link to the maximum common lane count between the * DisplayPort TX core and the RX device. */ - Status = XDptx_SetLaneCount(InstancePtr, LinkConfig->MaxLaneCount); + Status = XDp_TxSetLaneCount(InstancePtr, LinkConfig->MaxLaneCount); if (Status != XST_SUCCESS) { return Status; } @@ -406,7 +356,7 @@ u32 XDptx_CfgMainLinkMax(XDptx *InstancePtr) * This function checks if the link needs training and runs the training * sequence if training is required. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS was either already trained, or has been @@ -417,46 +367,41 @@ u32 XDptx_CfgMainLinkMax(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -u32 XDptx_EstablishLink(XDptx *InstancePtr) +u32 XDp_TxEstablishLink(XDp *InstancePtr) { u32 Status; u32 Status2; u32 ReenableMainLink; + XDp_TxLinkConfig *LinkConfig = &InstancePtr->TxInstance.LinkConfig; /* Verify arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid((InstancePtr->LinkConfig.LinkRate == - XDPTX_LINK_BW_SET_162GBPS) || - (InstancePtr->LinkConfig.LinkRate == - XDPTX_LINK_BW_SET_270GBPS) || - (InstancePtr->LinkConfig.LinkRate == - XDPTX_LINK_BW_SET_540GBPS)); - Xil_AssertNonvoid((InstancePtr->LinkConfig.LaneCount == - XDPTX_LANE_COUNT_SET_1) || - (InstancePtr->LinkConfig.LaneCount == - XDPTX_LANE_COUNT_SET_2) || - (InstancePtr->LinkConfig.LaneCount == - XDPTX_LANE_COUNT_SET_4)); + Xil_AssertNonvoid((LinkConfig->LinkRate == XDP_TX_LINK_BW_SET_162GBPS) || + (LinkConfig->LinkRate == XDP_TX_LINK_BW_SET_270GBPS) || + (LinkConfig->LinkRate == XDP_TX_LINK_BW_SET_540GBPS)); + Xil_AssertNonvoid((LinkConfig->LaneCount == XDP_TX_LANE_COUNT_SET_1) || + (LinkConfig->LaneCount == XDP_TX_LANE_COUNT_SET_2) || + (LinkConfig->LaneCount == XDP_TX_LANE_COUNT_SET_4)); - XDptx_ResetPhy(InstancePtr, XDPTX_PHY_CONFIG_PHY_RESET_MASK); + XDp_TxResetPhy(InstancePtr, XDP_TX_PHY_CONFIG_PHY_RESET_MASK); /* Disable main link during training. */ - ReenableMainLink = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_ENABLE_MAIN_STREAM); - XDptx_DisableMainLink(InstancePtr); + ReenableMainLink = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_ENABLE_MAIN_STREAM); + XDp_TxDisableMainLink(InstancePtr); /* Train main link. */ - Status = XDptx_RunTraining(InstancePtr); + Status = XDp_TxRunTraining(InstancePtr); /* Reenable main link after training if required. */ if (ReenableMainLink != 0) { - XDptx_EnableMainLink(InstancePtr); + XDp_TxEnableMainLink(InstancePtr); } /* Turn off the training pattern and enable scrambler. */ - Status2 = XDptx_SetTrainingPattern(InstancePtr, - XDPTX_TRAINING_PATTERN_SET_OFF); + Status2 = XDp_TxSetTrainingPattern(InstancePtr, + XDP_TX_TRAINING_PATTERN_SET_OFF); if ((Status != XST_SUCCESS) || (Status2 != XST_SUCCESS)) { return XST_FAILURE; } @@ -471,7 +416,7 @@ u32 XDptx_EstablishLink(XDptx *InstancePtr) * equalization, symbol lock, and interlane alignment for all lanes currently in * use. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LaneCount is the number of lanes to check. * * @return @@ -483,36 +428,36 @@ u32 XDptx_EstablishLink(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -u32 XDptx_CheckLinkStatus(XDptx *InstancePtr, u8 LaneCount) +u32 XDp_TxCheckLinkStatus(XDp *InstancePtr, u8 LaneCount) { u32 Status; u8 RetryCount = 0; - XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; + XDp_TxLinkConfig *LinkConfig = &InstancePtr->TxInstance.LinkConfig; /* Verify arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid((LaneCount == XDPTX_LANE_COUNT_SET_1) || - (LaneCount == XDPTX_LANE_COUNT_SET_2) || - (LaneCount == XDPTX_LANE_COUNT_SET_4)); + Xil_AssertNonvoid((LaneCount == XDP_TX_LANE_COUNT_SET_1) || + (LaneCount == XDP_TX_LANE_COUNT_SET_2) || + (LaneCount == XDP_TX_LANE_COUNT_SET_4)); - if (!XDptx_IsConnected(InstancePtr)) { + if (!XDp_TxIsConnected(InstancePtr)) { return XST_DEVICE_NOT_FOUND; } /* Retrieve AUX info. */ do { /* Get lane and adjustment requests. */ - Status = XDptx_GetLaneStatusAdjReqs(InstancePtr); + Status = XDp_TxGetLaneStatusAdjReqs(InstancePtr); if (Status != XST_SUCCESS) { /* The AUX read failed. */ return XST_FAILURE; } /* Check if the link needs training. */ - if ((XDptx_CheckClockRecovery( + if ((XDp_TxCheckClockRecovery( InstancePtr, LaneCount) == XST_SUCCESS) && - (XDptx_CheckChannelEqualization( + (XDp_TxCheckChannelEqualization( InstancePtr, LaneCount) == XST_SUCCESS)) { return XST_SUCCESS; } @@ -528,7 +473,7 @@ u32 XDptx_CheckLinkStatus(XDptx *InstancePtr, u8 LaneCount) /** * This function enables or disables downshifting during the training process. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Enable controls the downshift feature in the training process. * * @return None. @@ -536,23 +481,23 @@ u32 XDptx_CheckLinkStatus(XDptx *InstancePtr, u8 LaneCount) * @note None. * *******************************************************************************/ -void XDptx_EnableTrainAdaptive(XDptx *InstancePtr, u8 Enable) +void XDp_TxEnableTrainAdaptive(XDp *InstancePtr, u8 Enable) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid((Enable == 1) || (Enable == 0)); - InstancePtr->TrainAdaptive = Enable; + InstancePtr->TxInstance.TrainAdaptive = Enable; } /******************************************************************************/ /** * This function sets a software switch that signifies whether or not a redriver - * exists on the DisplayPort output path. XDptx_SetVswingPreemp uses this switch + * exists on the DisplayPort output path. XDp_TxSetVswingPreemp uses this switch * to determine which set of voltage swing and pre-emphasis values to use in the * TX core. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Set establishes that a redriver exists in the DisplayPort output * path. * @@ -561,13 +506,13 @@ void XDptx_EnableTrainAdaptive(XDptx *InstancePtr, u8 Enable) * @note None. * *******************************************************************************/ -void XDptx_SetHasRedriverInPath(XDptx *InstancePtr, u8 Set) +void XDp_TxSetHasRedriverInPath(XDp *InstancePtr, u8 Set) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid((Set == 1) || (Set == 0)); - InstancePtr->BoardChar.HasRedriverInPath = Set; + InstancePtr->TxInstance.BoardChar.HasRedriverInPath = Set; } /******************************************************************************/ @@ -577,7 +522,7 @@ void XDptx_SetHasRedriverInPath(XDptx *InstancePtr, u8 Set) * swing level value when pre-emphasis is used (when the pre-emphasis level not * equal to 0). * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Offset is the value to set for the voltage swing offset. * * @return None. @@ -585,13 +530,13 @@ void XDptx_SetHasRedriverInPath(XDptx *InstancePtr, u8 Set) * @note None. * *******************************************************************************/ -void XDptx_CfgTxVsOffset(XDptx *InstancePtr, u8 Offset) +void XDp_TxCfgTxVsOffset(XDp *InstancePtr, u8 Offset) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid((Offset >= 0) && (Offset < 16)); - InstancePtr->BoardChar.TxVsOffset = Offset; + InstancePtr->TxInstance.BoardChar.TxVsOffset = Offset; } /******************************************************************************/ @@ -599,7 +544,7 @@ void XDptx_CfgTxVsOffset(XDptx *InstancePtr, u8 Offset) * This function sets the voltage swing level value in the DisplayPort TX that * will be used during link training for a given voltage swing training level. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Level is the voltage swing training level to set the DisplayPort * TX level for. * @param TxLevel is the DisplayPort TX voltage swing level value to be @@ -612,14 +557,14 @@ void XDptx_CfgTxVsOffset(XDptx *InstancePtr, u8 Offset) * RX device. * *******************************************************************************/ -void XDptx_CfgTxVsLevel(XDptx *InstancePtr, u8 Level, u8 TxLevel) +void XDp_TxCfgTxVsLevel(XDp *InstancePtr, u8 Level, u8 TxLevel) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid((Level >= 0) && (Level < 4)); Xil_AssertVoid((TxLevel >= 0) && (TxLevel < 16)); - InstancePtr->BoardChar.TxVsLevels[Level] = TxLevel; + InstancePtr->TxInstance.BoardChar.TxVsLevels[Level] = TxLevel; } /******************************************************************************/ @@ -627,7 +572,7 @@ void XDptx_CfgTxVsLevel(XDptx *InstancePtr, u8 Level, u8 TxLevel) * This function sets the pre-emphasis level value in the DisplayPort TX that * will be used during link training for a given pre-emphasis training level. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Level is the pre-emphasis training level to set the DisplayPort * TX level for. * @param TxLevel is the DisplayPort TX pre-emphasis level value to be @@ -640,43 +585,43 @@ void XDptx_CfgTxVsLevel(XDptx *InstancePtr, u8 Level, u8 TxLevel) * RX device. * *******************************************************************************/ -void XDptx_CfgTxPeLevel(XDptx *InstancePtr, u8 Level, u8 TxLevel) +void XDp_TxCfgTxPeLevel(XDp *InstancePtr, u8 Level, u8 TxLevel) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid((Level >= 0) && (Level < 4)); Xil_AssertVoid((TxLevel >= 0) && (TxLevel < 32)); - InstancePtr->BoardChar.TxPeLevels[Level] = TxLevel; + InstancePtr->TxInstance.BoardChar.TxPeLevels[Level] = TxLevel; } /******************************************************************************/ /** * This function checks if there is a connected RX device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - TRUE if there is a connection. * - FALSE if there is no connection. * *******************************************************************************/ -u32 XDptx_IsConnected(XDptx *InstancePtr) +u32 XDp_TxIsConnected(XDp *InstancePtr) { u32 Status; u8 Retries = 0; do { - Status = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_INTERRUPT_SIG_STATE) & - XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK; + Status = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_INTERRUPT_SIG_STATE) & + XDP_TX_INTERRUPT_SIG_STATE_HPD_STATE_MASK; - if (Retries > XDPTX_IS_CONNECTED_MAX_TIMEOUT_COUNT) { + if (Retries > XDP_IS_CONNECTED_MAX_TIMEOUT_COUNT) { return 0; } Retries++; - XDptx_WaitUs(InstancePtr, 1000); + XDp_WaitUs(InstancePtr, 1000); } while (Status == 0); return 1; @@ -689,7 +634,7 @@ u32 XDptx_IsConnected(XDptx *InstancePtr) * message will be divided into multiple transactions which read a maximum of 16 * bytes each. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param DpcdAddress is the starting address to read from the RX device. * @param BytesToRead is the number of bytes to read from the RX device. * @param ReadData is a pointer to the data buffer that will be filled @@ -705,11 +650,11 @@ u32 XDptx_IsConnected(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -u32 XDptx_AuxRead(XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToRead, +u32 XDp_TxAuxRead(XDp *InstancePtr, u32 DpcdAddress, u32 BytesToRead, void *ReadData) { u32 Status; - XDptx_AuxTransaction Request; + XDp_AuxTransaction Request; /* Verify arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); @@ -718,12 +663,12 @@ u32 XDptx_AuxRead(XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToRead, Xil_AssertNonvoid(BytesToRead <= 0xFFFFF); Xil_AssertNonvoid(ReadData != NULL); - if (!XDptx_IsConnected(InstancePtr)) { + if (!XDp_TxIsConnected(InstancePtr)) { return XST_DEVICE_NOT_FOUND; } /* Send AUX read transaction. */ - Status = XDptx_AuxCommon(InstancePtr, XDPTX_AUX_CMD_READ, DpcdAddress, + Status = XDp_TxAuxCommon(InstancePtr, XDP_TX_AUX_CMD_READ, DpcdAddress, BytesToRead, (u8 *)ReadData); return Status; @@ -736,7 +681,7 @@ u32 XDptx_AuxRead(XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToRead, * write message will be divided into multiple transactions which write a * maximum of 16 bytes each. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param DpcdAddress is the starting address to write to the RX device. * @param BytesToWrite is the number of bytes to write to the RX device. * @param WriteData is a pointer to the data buffer that contains the data @@ -752,11 +697,11 @@ u32 XDptx_AuxRead(XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToRead, * @note None. * *******************************************************************************/ -u32 XDptx_AuxWrite(XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToWrite, +u32 XDp_TxAuxWrite(XDp *InstancePtr, u32 DpcdAddress, u32 BytesToWrite, void *WriteData) { u32 Status; - XDptx_AuxTransaction Request; + XDp_AuxTransaction Request; /* Verify arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); @@ -765,12 +710,12 @@ u32 XDptx_AuxWrite(XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToWrite, Xil_AssertNonvoid(BytesToWrite <= 0xFFFFF); Xil_AssertNonvoid(WriteData != NULL); - if (!XDptx_IsConnected(InstancePtr)) { + if (!XDp_TxIsConnected(InstancePtr)) { return XST_DEVICE_NOT_FOUND; } /* Send AUX write transaction. */ - Status = XDptx_AuxCommon(InstancePtr, XDPTX_AUX_CMD_WRITE, DpcdAddress, + Status = XDp_TxAuxCommon(InstancePtr, XDP_TX_AUX_CMD_WRITE, DpcdAddress, BytesToWrite, (u8 *)WriteData); return Status; @@ -788,7 +733,7 @@ u32 XDptx_AuxWrite(XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToWrite, * - 512, an I2C read is done on segptr=2; offset=0. * - etc. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param IicAddress is the address on the I2C bus of the target device. * @param Offset is the offset at the specified address of the targeted * I2C device that the read will start from. @@ -806,11 +751,11 @@ u32 XDptx_AuxWrite(XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToWrite, * @note None. * *******************************************************************************/ -u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u16 Offset, +u32 XDp_TxIicRead(XDp *InstancePtr, u8 IicAddress, u16 Offset, u16 BytesToRead, void *ReadData) { u32 Status; - XDptx_AuxTransaction Request; + XDp_AuxTransaction Request; u8 SegPtr; u16 NumBytesLeftInSeg; u16 BytesLeft; @@ -824,7 +769,7 @@ u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u16 Offset, Xil_AssertNonvoid(BytesToRead <= 0xFFFF); Xil_AssertNonvoid(ReadData != NULL); - if (!XDptx_IsConnected(InstancePtr)) { + if (!XDp_TxIsConnected(InstancePtr)) { return XST_DEVICE_NOT_FOUND; } @@ -839,7 +784,7 @@ u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u16 Offset, NumBytesLeftInSeg = 256 - Offset; /* Set the segment pointer to 0. */ - Status = XDptx_IicWrite(InstancePtr, XDPTX_SEGPTR_ADDR, 1, &SegPtr); + Status = XDp_TxIicWrite(InstancePtr, XDP_SEGPTR_ADDR, 1, &SegPtr); if (Status != XST_SUCCESS) { return Status; } @@ -857,13 +802,13 @@ u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u16 Offset, } /* Setup the I2C-over-AUX read transaction with the offset. */ - Status = XDptx_IicWrite(InstancePtr, IicAddress, 1, &Offset); + Status = XDp_TxIicWrite(InstancePtr, IicAddress, 1, &Offset); if (Status != XST_SUCCESS) { return Status; } /* Send I2C-over-AUX read transaction. */ - Status = XDptx_AuxCommon(InstancePtr, XDPTX_AUX_CMD_I2C_READ, + Status = XDp_TxAuxCommon(InstancePtr, XDP_TX_AUX_CMD_I2C_READ, IicAddress, CurrBytesToRead, (u8 *)ReadData); if (Status != XST_SUCCESS) { return Status; @@ -883,8 +828,8 @@ u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u16 Offset, Offset %= 256; SegPtr++; - Status = XDptx_IicWrite(InstancePtr, - XDPTX_SEGPTR_ADDR, 1, &SegPtr); + Status = XDp_TxIicWrite(InstancePtr, + XDP_SEGPTR_ADDR, 1, &SegPtr); if (Status != XST_SUCCESS) { return Status; } @@ -898,7 +843,7 @@ u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u16 Offset, /* Reset the segment pointer to 0. */ SegPtr = 0; - Status = XDptx_IicWrite(InstancePtr, XDPTX_SEGPTR_ADDR, 1, &SegPtr); + Status = XDp_TxIicWrite(InstancePtr, XDP_SEGPTR_ADDR, 1, &SegPtr); return Status; } @@ -907,7 +852,7 @@ u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u16 Offset, /** * This function performs an I2C write over the AUX channel. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param IicAddress is the address on the I2C bus of the target device. * @param BytesToWrite is the number of bytes to write. * @param WriteData is a pointer to a buffer which will be used as the @@ -923,11 +868,11 @@ u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u16 Offset, * @note None. * *******************************************************************************/ -u32 XDptx_IicWrite(XDptx *InstancePtr, u8 IicAddress, u8 BytesToWrite, +u32 XDp_TxIicWrite(XDp *InstancePtr, u8 IicAddress, u8 BytesToWrite, void *WriteData) { u32 Status; - XDptx_AuxTransaction Request; + XDp_AuxTransaction Request; /* Verify arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); @@ -936,12 +881,12 @@ u32 XDptx_IicWrite(XDptx *InstancePtr, u8 IicAddress, u8 BytesToWrite, Xil_AssertNonvoid(BytesToWrite <= 0xFF); Xil_AssertNonvoid(WriteData != NULL); - if (!XDptx_IsConnected(InstancePtr)) { + if (!XDp_TxIsConnected(InstancePtr)) { return XST_DEVICE_NOT_FOUND; } /* Send I2C-over-AUX read transaction. */ - Status = XDptx_AuxCommon(InstancePtr, XDPTX_AUX_CMD_I2C_WRITE, + Status = XDp_TxAuxCommon(InstancePtr, XDP_TX_AUX_CMD_I2C_WRITE, IicAddress, BytesToWrite, (u8 *)WriteData); return Status; @@ -952,7 +897,7 @@ u32 XDptx_IicWrite(XDptx *InstancePtr, u8 IicAddress, u8 BytesToWrite, * This function enables or disables 0.5% spreading of the clock for both the * DisplayPort and the RX device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Enable will downspread the main link signal if set to 1 and * disable downspreading if set to 0. * @@ -965,7 +910,7 @@ u32 XDptx_IicWrite(XDptx *InstancePtr, u8 IicAddress, u8 BytesToWrite, * @note None. * *******************************************************************************/ -u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable) +u32 XDp_TxSetDownspread(XDp *InstancePtr, u8 Enable) { u32 Status; u8 RegVal; @@ -975,31 +920,31 @@ u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid((Enable == 1) || (Enable == 0)); - if (!XDptx_IsConnected(InstancePtr)) { + if (!XDp_TxIsConnected(InstancePtr)) { return XST_DEVICE_NOT_FOUND; } - InstancePtr->LinkConfig.DownspreadControl = Enable; + InstancePtr->TxInstance.LinkConfig.DownspreadControl = Enable; /* Write downspread enable to the DisplayPort TX core. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_DOWNSPREAD_CTRL, - InstancePtr->LinkConfig.DownspreadControl); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_DOWNSPREAD_CTRL, + InstancePtr->TxInstance.LinkConfig.DownspreadControl); /* Preserve the current RX device settings. */ - Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_DOWNSPREAD_CTRL, 0x1, + Status = XDp_TxAuxRead(InstancePtr, XDP_DPCD_DOWNSPREAD_CTRL, 0x1, &RegVal); if (Status != XST_SUCCESS) { return XST_FAILURE; } - if (InstancePtr->LinkConfig.DownspreadControl) { - RegVal |= XDPTX_DPCD_SPREAD_AMP_MASK; + if (InstancePtr->TxInstance.LinkConfig.DownspreadControl) { + RegVal |= XDP_DPCD_SPREAD_AMP_MASK; } else { - RegVal &= ~XDPTX_DPCD_SPREAD_AMP_MASK; + RegVal &= ~XDP_DPCD_SPREAD_AMP_MASK; } /* Write downspread enable to the RX device. */ - Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_DOWNSPREAD_CTRL, 0x1, + Status = XDp_TxAuxWrite(InstancePtr, XDP_DPCD_DOWNSPREAD_CTRL, 0x1, &RegVal); if (Status != XST_SUCCESS) { return XST_FAILURE; @@ -1013,7 +958,7 @@ u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable) * This function enables or disables the enhanced framing symbol sequence for * both the DisplayPort TX core and the RX device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Enable will enable enhanced frame mode if set to 1 and disable * it if set to 0. * @@ -1026,7 +971,7 @@ u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable) * @note None. * *******************************************************************************/ -u32 XDptx_SetEnhancedFrameMode(XDptx *InstancePtr, u8 Enable) +u32 XDp_TxSetEnhancedFrameMode(XDp *InstancePtr, u8 Enable) { u32 Status; u8 RegVal; @@ -1036,31 +981,31 @@ u32 XDptx_SetEnhancedFrameMode(XDptx *InstancePtr, u8 Enable) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid((Enable == 1) || (Enable == 0)); - if (!XDptx_IsConnected(InstancePtr)) { + if (!XDp_TxIsConnected(InstancePtr)) { return XST_DEVICE_NOT_FOUND; } - InstancePtr->LinkConfig.EnhancedFramingMode = Enable; + InstancePtr->TxInstance.LinkConfig.EnhancedFramingMode = Enable; /* Write enhanced frame mode enable to the DisplayPort TX core. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENHANCED_FRAME_EN, - InstancePtr->LinkConfig.EnhancedFramingMode); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_ENHANCED_FRAME_EN, + InstancePtr->TxInstance.LinkConfig.EnhancedFramingMode); /* Preserve the current RX device settings. */ - Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 0x1, + Status = XDp_TxAuxRead(InstancePtr, XDP_DPCD_LANE_COUNT_SET, 0x1, &RegVal); if (Status != XST_SUCCESS) { return XST_FAILURE; } - if (InstancePtr->LinkConfig.EnhancedFramingMode) { - RegVal |= XDPTX_DPCD_ENHANCED_FRAME_EN_MASK; + if (InstancePtr->TxInstance.LinkConfig.EnhancedFramingMode) { + RegVal |= XDP_DPCD_ENHANCED_FRAME_EN_MASK; } else { - RegVal &= ~XDPTX_DPCD_ENHANCED_FRAME_EN_MASK; + RegVal &= ~XDP_DPCD_ENHANCED_FRAME_EN_MASK; } /* Write enhanced frame mode enable to the RX device. */ - Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 0x1, + Status = XDp_TxAuxWrite(InstancePtr, XDP_DPCD_LANE_COUNT_SET, 0x1, &RegVal); if (Status != XST_SUCCESS) { return XST_FAILURE; @@ -1074,7 +1019,7 @@ u32 XDptx_SetEnhancedFrameMode(XDptx *InstancePtr, u8 Enable) * This function sets the number of lanes to be used by the main link for both * the DisplayPort TX core and the RX device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LaneCount is the number of lanes to be used over the main link. * * @return @@ -1085,7 +1030,7 @@ u32 XDptx_SetEnhancedFrameMode(XDptx *InstancePtr, u8 Enable) * @note None. * *******************************************************************************/ -u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount) +u32 XDp_TxSetLaneCount(XDp *InstancePtr, u8 LaneCount) { u32 Status; u8 RegVal; @@ -1093,31 +1038,31 @@ u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount) /* Verify arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid((LaneCount == XDPTX_LANE_COUNT_SET_1) || - (LaneCount == XDPTX_LANE_COUNT_SET_2) || - (LaneCount == XDPTX_LANE_COUNT_SET_4)); + Xil_AssertNonvoid((LaneCount == XDP_TX_LANE_COUNT_SET_1) || + (LaneCount == XDP_TX_LANE_COUNT_SET_2) || + (LaneCount == XDP_TX_LANE_COUNT_SET_4)); - if (!XDptx_IsConnected(InstancePtr)) { + if (!XDp_TxIsConnected(InstancePtr)) { return XST_DEVICE_NOT_FOUND; } - InstancePtr->LinkConfig.LaneCount = LaneCount; + InstancePtr->TxInstance.LinkConfig.LaneCount = LaneCount; /* Write the new lane count to the DisplayPort TX core. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_LANE_COUNT_SET, - InstancePtr->LinkConfig.LaneCount); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_LANE_COUNT_SET, + InstancePtr->TxInstance.LinkConfig.LaneCount); /* Preserve the current RX device settings. */ - Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 0x1, + Status = XDp_TxAuxRead(InstancePtr, XDP_DPCD_LANE_COUNT_SET, 0x1, &RegVal); if (Status != XST_SUCCESS) { return XST_FAILURE; } - RegVal &= ~XDPTX_DPCD_LANE_COUNT_SET_MASK; - RegVal |= InstancePtr->LinkConfig.LaneCount; + RegVal &= ~XDP_DPCD_LANE_COUNT_SET_MASK; + RegVal |= InstancePtr->TxInstance.LinkConfig.LaneCount; /* Write the new lane count to the RX device. */ - Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 0x1, + Status = XDp_TxAuxWrite(InstancePtr, XDP_DPCD_LANE_COUNT_SET, 0x1, &RegVal); if (Status != XST_SUCCESS) { return XST_FAILURE; @@ -1131,12 +1076,12 @@ u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount) * This function sets the data rate to be used by the main link for both the * DisplayPort TX core and the RX device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkRate is the link rate to be used over the main link based on * one of the following selects: - * - XDPTX_LINK_BW_SET_162GBPS = 0x06 (for a 1.62 Gbps data rate) - * - XDPTX_LINK_BW_SET_270GBPS = 0x0A (for a 2.70 Gbps data rate) - * - XDPTX_LINK_BW_SET_540GBPS = 0x14 (for a 5.40 Gbps data rate) + * - XDP_TX_LINK_BW_SET_162GBPS = 0x06 (for a 1.62 Gbps data rate) + * - XDP_TX_LINK_BW_SET_270GBPS = 0x0A (for a 2.70 Gbps data rate) + * - XDP_TX_LINK_BW_SET_540GBPS = 0x14 (for a 5.40 Gbps data rate) * * @return * - XST_SUCCESS if setting the new link rate was successful. @@ -1146,34 +1091,34 @@ u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount) * @note None. * *******************************************************************************/ -u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate) +u32 XDp_TxSetLinkRate(XDp *InstancePtr, u8 LinkRate) { u32 Status; /* Verify arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid((LinkRate == XDPTX_LINK_BW_SET_162GBPS) || - (LinkRate == XDPTX_LINK_BW_SET_270GBPS) || - (LinkRate == XDPTX_LINK_BW_SET_540GBPS)); + Xil_AssertNonvoid((LinkRate == XDP_TX_LINK_BW_SET_162GBPS) || + (LinkRate == XDP_TX_LINK_BW_SET_270GBPS) || + (LinkRate == XDP_TX_LINK_BW_SET_540GBPS)); - if (!XDptx_IsConnected(InstancePtr)) { + if (!XDp_TxIsConnected(InstancePtr)) { return XST_DEVICE_NOT_FOUND; } /* Write a corresponding clock frequency to the DisplayPort TX core. */ switch (LinkRate) { - case XDPTX_LINK_BW_SET_162GBPS: - Status = XDptx_SetClkSpeed(InstancePtr, - XDPTX_PHY_CLOCK_SELECT_162GBPS); + case XDP_TX_LINK_BW_SET_162GBPS: + Status = XDp_TxSetClkSpeed(InstancePtr, + XDP_TX_PHY_CLOCK_SELECT_162GBPS); break; - case XDPTX_LINK_BW_SET_270GBPS: - Status = XDptx_SetClkSpeed(InstancePtr, - XDPTX_PHY_CLOCK_SELECT_270GBPS); + case XDP_TX_LINK_BW_SET_270GBPS: + Status = XDp_TxSetClkSpeed(InstancePtr, + XDP_TX_PHY_CLOCK_SELECT_270GBPS); break; - case XDPTX_LINK_BW_SET_540GBPS: - Status = XDptx_SetClkSpeed(InstancePtr, - XDPTX_PHY_CLOCK_SELECT_540GBPS); + case XDP_TX_LINK_BW_SET_540GBPS: + Status = XDp_TxSetClkSpeed(InstancePtr, + XDP_TX_PHY_CLOCK_SELECT_540GBPS); break; default: break; @@ -1182,15 +1127,15 @@ u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate) return XST_FAILURE; } - InstancePtr->LinkConfig.LinkRate = LinkRate; + InstancePtr->TxInstance.LinkConfig.LinkRate = LinkRate; /* Write new link rate to the DisplayPort TX core. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_LINK_BW_SET, - InstancePtr->LinkConfig.LinkRate); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_LINK_BW_SET, + InstancePtr->TxInstance.LinkConfig.LinkRate); /* Write new link rate to the RX device. */ - Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_LINK_BW_SET, 0x1, - &InstancePtr->LinkConfig.LinkRate); + Status = XDp_TxAuxWrite(InstancePtr, XDP_DPCD_LINK_BW_SET, 1, + &InstancePtr->TxInstance.LinkConfig.LinkRate); if (Status != XST_SUCCESS) { return XST_FAILURE; } @@ -1203,7 +1148,7 @@ u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate) * This function enables or disables scrambling of symbols for both the * DisplayPort and the RX device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Enable will enable or disable scrambling. * * @return @@ -1213,7 +1158,7 @@ u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate) * @note None. * *******************************************************************************/ -u32 XDptx_SetScrambler(XDptx *InstancePtr, u8 Enable) +u32 XDp_TxSetScrambler(XDp *InstancePtr, u8 Enable) { u32 Status; u8 RegVal; @@ -1223,26 +1168,26 @@ u32 XDptx_SetScrambler(XDptx *InstancePtr, u8 Enable) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid((Enable == 1) || (Enable == 0)); - InstancePtr->LinkConfig.ScramblerEn = Enable; + InstancePtr->TxInstance.LinkConfig.ScramblerEn = Enable; /* Write scrambler disable to the DisplayPort TX core. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SCRAMBLING_DISABLE, + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_SCRAMBLING_DISABLE, Enable ? 0x0 : 0x1); /* Preserve the current RX device settings. */ - Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_TP_SET, 0x1, &RegVal); + Status = XDp_TxAuxRead(InstancePtr, XDP_DPCD_TP_SET, 1, &RegVal); if (Status != XST_SUCCESS) { return XST_FAILURE; } if (Enable) { - RegVal &= ~XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK; + RegVal &= ~XDP_DPCD_TP_SET_SCRAMB_DIS_MASK; } else { - RegVal |= XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK; + RegVal |= XDP_DPCD_TP_SET_SCRAMB_DIS_MASK; } /* Write scrambler disable to the RX device. */ - Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_TP_SET, 0x1, &RegVal); + Status = XDp_TxAuxWrite(InstancePtr, XDP_DPCD_TP_SET, 1, &RegVal); if (Status != XST_SUCCESS) { return XST_FAILURE; } @@ -1254,59 +1199,59 @@ u32 XDptx_SetScrambler(XDptx *InstancePtr, u8 Enable) /** * This function enables the main link. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * * @note None. * *******************************************************************************/ -void XDptx_EnableMainLink(XDptx *InstancePtr) +void XDp_TxEnableMainLink(XDp *InstancePtr) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); /* Reset the scrambler. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, - XDPTX_FORCE_SCRAMBLER_RESET, 0x1); + XDp_WriteReg(InstancePtr->Config.BaseAddr, + XDP_TX_FORCE_SCRAMBLER_RESET, 0x1); /* Enable the main stream. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, - XDPTX_ENABLE_MAIN_STREAM, 0x1); + XDp_WriteReg(InstancePtr->Config.BaseAddr, + XDP_TX_ENABLE_MAIN_STREAM, 0x1); } /******************************************************************************/ /** * This function disables the main link. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * * @note None. * *******************************************************************************/ -void XDptx_DisableMainLink(XDptx *InstancePtr) +void XDp_TxDisableMainLink(XDp *InstancePtr) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); /* Reset the scrambler. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, - XDPTX_FORCE_SCRAMBLER_RESET, 0x1); + XDp_WriteReg(InstancePtr->Config.BaseAddr, + XDP_TX_FORCE_SCRAMBLER_RESET, 0x1); /* Disable the main stream. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, - XDPTX_ENABLE_MAIN_STREAM, 0x0); + XDp_WriteReg(InstancePtr->Config.BaseAddr, + XDP_TX_ENABLE_MAIN_STREAM, 0x0); } /******************************************************************************/ /** * This function does a PHY reset. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Reset is the type of reset to assert. * * @return None. @@ -1314,28 +1259,202 @@ void XDptx_DisableMainLink(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -void XDptx_ResetPhy(XDptx *InstancePtr, u32 Reset) +void XDp_TxResetPhy(XDp *InstancePtr, u32 Reset) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 0x0); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_ENABLE, 0x0); - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_PHY_CONFIG, Reset); - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_PHY_CONFIG, - XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK); - XDptx_WaitPhyReady(InstancePtr); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_PHY_CONFIG, Reset); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_PHY_CONFIG, + XDP_TX_PHY_CONFIG_PHY_RESET_ENABLE_MASK); + if (InstancePtr->Config.MaxLaneCount > 2) { + XDp_WaitPhyReady(InstancePtr, + XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK); + } + else { + XDp_WaitPhyReady(InstancePtr, + XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK); + } - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 0x1); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_ENABLE, 0x1); } /******************************************************************************/ /** - * This function installs a custom delay/sleep function to be used by the XDptx + * This function checks if the reciever's internal registers indicate that link + * training has complete. That is, training has achieved channel equalization, + * symbol lock, and interlane alignment for all lanes currently in use. + * + * @param InstancePtr is a pointer to the XDp instance. + * + * @return + * - XST_SUCCESS if the RX device has achieved clock recovery, + * channel equalization, symbol lock, and interlane alignment. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +u32 XDp_RxCheckLinkStatus(XDp *InstancePtr) +{ + u8 LaneCount; + u8 LaneStatus[2]; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + LaneCount = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_RX_DPCD_LANE_COUNT_SET); + + LaneStatus[0] = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_RX_DPCD_LANE01_STATUS); + LaneStatus[1] = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_RX_DPCD_LANE23_STATUS); + + switch (LaneCount) { + case 4: + if (LaneStatus[1] != 0x77) { + return XST_FAILURE; + } + case 2: + if ((LaneStatus[0] & 0x70) != 0x70) { + return XST_FAILURE; + } + case 1: + if ((LaneStatus[0] & 0x07) != 0x07) { + return XST_FAILURE; + } + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function enables the display timing generator (DTG). + * + * @param InstancePtr is a pointer to the XDp instance. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XDp_RxDtgEn(XDp *InstancePtr) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_SOFT_RESET, + XDP_RX_SOFT_RESET_VIDEO_MASK); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_SOFT_RESET, 0x0); + + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_DTG_ENABLE, 0x1); +} + +/******************************************************************************/ +/** + * This function disables the display timing generator (DTG). + * + * @param InstancePtr is a pointer to the XDp instance. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XDp_RxDtgDis(XDp *InstancePtr) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_DTG_ENABLE, 0x0); + + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_SOFT_RESET, + XDP_RX_SOFT_RESET_VIDEO_MASK); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_SOFT_RESET, 0x0); +} + +/******************************************************************************/ +/** + * This function sets the maximum data rate to be exposed in the RX device's + * DisplayPort Configuration Data (DPCD) registers. + * + * @param InstancePtr is a pointer to the XDp instance. + * @param LinkRate is the link rate to be used over the main link based on + * one of the following selects: + * - XDP_RX_LINK_BW_SET_162GBPS = 0x06 (for a 1.62 Gbps data rate) + * - XDP_RX_LINK_BW_SET_270GBPS = 0x0A (for a 2.70 Gbps data rate) + * - XDP_RX_LINK_BW_SET_540GBPS = 0x14 (for a 5.40 Gbps data rate) + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XDp_RxSetLinkRate(XDp *InstancePtr, u8 LinkRate) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((LinkRate == XDP_RX_OVER_LINK_BW_SET_162GBPS) || + (LinkRate == XDP_RX_OVER_LINK_BW_SET_270GBPS) || + (LinkRate == XDP_RX_OVER_LINK_BW_SET_540GBPS)); + + InstancePtr->RxInstance.LinkConfig.LinkRate = LinkRate; + + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_OVER_CTRL_DPCD, 0x1); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_OVER_LINK_BW_SET, + LinkRate); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_OVER_CTRL_DPCD, 0x0); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_LOCAL_EDID_VIDEO, + 0x1); +} + +/******************************************************************************/ +/** + * This function sets the maximum lane count to be exposed in the RX device's + * DisplayPort Configuration Data (DPCD) registers. + * + * @param InstancePtr is a pointer to the XDp instance. + * @param LaneCount is the number of lanes to be used over the main link. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XDp_RxSetLaneCount(XDp *InstancePtr, u8 LaneCount) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((LaneCount == XDP_RX_OVER_LANE_COUNT_SET_1) || + (LaneCount == XDP_RX_OVER_LANE_COUNT_SET_2) || + (LaneCount == XDP_RX_OVER_LANE_COUNT_SET_4)); + + InstancePtr->RxInstance.LinkConfig.LaneCount = LaneCount; + + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_OVER_CTRL_DPCD, 0x1); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_OVER_LANE_COUNT_SET, + LaneCount); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_OVER_CTRL_DPCD, 0x0); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_LOCAL_EDID_VIDEO, + 0x1); +} + +/******************************************************************************/ +/** + * This function installs a custom delay/sleep function to be used by the XDp * driver. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param CallbackFunc is the address to the callback function. * @param CallbackRef is the user data item (microseconds to delay) that * will be passed to the custom sleep/delay function when it is @@ -1346,8 +1465,8 @@ void XDptx_ResetPhy(XDptx *InstancePtr, u32 Reset) * @note None. * *******************************************************************************/ -void XDptx_SetUserTimerHandler(XDptx *InstancePtr, - XDp_TimerHandler CallbackFunc, void *CallbackRef) +void XDp_SetUserTimerHandler(XDp *InstancePtr, XDp_TimerHandler CallbackFunc, + void *CallbackRef) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); @@ -1360,7 +1479,7 @@ void XDptx_SetUserTimerHandler(XDptx *InstancePtr, /******************************************************************************/ /** - * This function is the delay/sleep function for the XDptx driver. For the Zynq + * This function is the delay/sleep function for the XDp driver. For the Zynq * family, there exists native sleep functionality. For MicroBlaze however, * there does not exist such functionality. In the MicroBlaze case, the default * method for delaying is to use a predetermined amount of loop iterations. This @@ -1369,7 +1488,7 @@ void XDptx_SetUserTimerHandler(XDptx *InstancePtr, * to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a * hardware timer is used. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param MicroSeconds is the number of microseconds to delay/sleep for. * * @return None. @@ -1377,7 +1496,7 @@ void XDptx_SetUserTimerHandler(XDptx *InstancePtr, * @note None. * *******************************************************************************/ -void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds) +void XDp_WaitUs(XDp *InstancePtr, u32 MicroSeconds) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); @@ -1404,6 +1523,173 @@ void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds) #endif } +/******************************************************************************/ +/** + * This function prepares the DisplayPort TX core for use. + * + * @param InstancePtr is a pointer to the XDp instance. + * + * @return + * - XST_SUCCESS if the DisplayPort TX core was successfully + * initialized. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static u32 XDp_TxInitialize(XDp *InstancePtr) +{ + u32 Status; + u32 RegVal; + XDp_Config *ConfigPtr = &InstancePtr->Config; + + /* Place the PHY (and GTTXRESET) into reset. */ + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_PHY_CONFIG, + XDP_TX_PHY_CONFIG_GT_ALL_RESET_MASK); + + /* Reset the video streams and AUX logic. */ + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_SOFT_RESET, + XDP_TX_SOFT_RESET_VIDEO_STREAM_ALL_MASK | + XDP_TX_SOFT_RESET_AUX_MASK); + + /* Disable the DisplayPort TX core. */ + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_ENABLE, 0); + + /* Set the clock divider. */ + RegVal = (XDp_ReadReg(ConfigPtr->BaseAddr, XDP_TX_AUX_CLK_DIVIDER) & + ~XDP_TX_AUX_CLK_DIVIDER_VAL_MASK) | + (ConfigPtr->SAxiClkHz / 1000000); + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_AUX_CLK_DIVIDER, RegVal); + + /* Set the DisplayPort TX core's clock speed. */ + switch (ConfigPtr->MaxLinkRate) { + case XDP_TX_LINK_BW_SET_540GBPS: + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_PHY_CLOCK_SELECT, + XDP_TX_PHY_CLOCK_SELECT_540GBPS); + break; + case XDP_TX_LINK_BW_SET_270GBPS: + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_PHY_CLOCK_SELECT, + XDP_TX_PHY_CLOCK_SELECT_270GBPS); + break; + case XDP_TX_LINK_BW_SET_162GBPS: + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_PHY_CLOCK_SELECT, + XDP_TX_PHY_CLOCK_SELECT_162GBPS); + break; + default: + break; + } + + /* Bring the PHY (and GTTXRESET) out of reset. */ + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_PHY_CONFIG, + XDP_TX_PHY_CONFIG_PHY_RESET_ENABLE_MASK); + + /* Wait for the PHY to be ready. */ + if (ConfigPtr->MaxLaneCount > 2) { + Status = XDp_WaitPhyReady(InstancePtr, + XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK); + } + else { + Status = XDp_WaitPhyReady(InstancePtr, + XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK); + } + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Enable the DisplayPort TX core. */ + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_ENABLE, 1); + + /* Unmask Hot-Plug-Detect (HPD) interrupts. */ + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_INTERRUPT_MASK, + ~XDP_TX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK & + ~XDP_TX_INTERRUPT_MASK_HPD_EVENT_MASK & + ~XDP_TX_INTERRUPT_MASK_HPD_IRQ_MASK); + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function prepares the DisplayPort RX core for use. + * + * @param InstancePtr is a pointer to the XDp instance. + * + * @return + * - XST_SUCCESS if the DisplayPort RX core was successfully + * initialized. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static u32 XDp_RxInitialize(XDp *InstancePtr) +{ + u32 Status; + + /* Disable the main link. */ + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_LINK_ENABLE, 0x0); + + /* Set the AUX clock divider. */ + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_AUX_CLK_DIVIDER, + (InstancePtr->Config.SAxiClkHz / 1000000)); + + /* Put both GT RX/TX and CPLL into reset. */ + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_PHY_CONFIG, + XDP_RX_PHY_CONFIG_GTPLL_RESET_MASK | + XDP_RX_PHY_CONFIG_GTRX_RESET_MASK); + + /* Release CPLL reset. */ + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_PHY_CONFIG, + XDP_RX_PHY_CONFIG_GTRX_RESET_MASK); + + /* Wait until all lane CPLLs have locked. */ + Status = XDp_WaitPhyReady(InstancePtr, + XDP_RX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK | + XDP_RX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Remove the reset from the PHY. */ + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_PHY_CONFIG, + XDP_RX_PHY_CONFIG_PHY_RESET_ENABLE_MASK); + + /* Wait until the PHY has completed the reset cycle. */ + Status = XDp_WaitPhyReady(InstancePtr, + XDP_RX_PHY_STATUS_ALL_LANES_READY_MASK | + XDP_RX_PHY_STATUS_PLL_FABRIC_LOCK_MASK | + XDP_RX_PHY_STATUS_RX_CLK_LOCK_MASK); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Enable the RX core. */ + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_LINK_ENABLE, 0x1); + + /* Set other user parameters. */ + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_MIN_VOLTAGE_SWING, + 0x01); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_SINK_COUNT, 0x01); + /* Set the AUX training interval. */ + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_OVER_CTRL_DPCD, 0x1); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_OVER_TP_SET, + (2 << XDP_RX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_SHIFT)); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_OVER_CTRL_DPCD, 0x0); + /* Set the link configuration.*/ + XDp_RxSetLinkRate(InstancePtr, + InstancePtr->RxInstance.LinkConfig.LinkRate); + XDp_RxSetLaneCount(InstancePtr, + InstancePtr->RxInstance.LinkConfig.LaneCount); + /* Set the interrupt masks. */ + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_INTERRUPT_MASK, + ~XDP_RX_INTERRUPT_MASK_ALL_MASK); + + /* Enable the display timing generator. */ + XDp_RxDtgEn(InstancePtr); + + return XST_SUCCESS; +} + /******************************************************************************/ /** * This function runs the link training process. It is implemented as a state @@ -1414,7 +1700,7 @@ void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds) * be re-attempted. If training fails at the minimal data rate, 1.62 Gbps with * a single lane, training will no longer re-attempt and fail. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if the training process succeeded. @@ -1423,50 +1709,50 @@ void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds) * @note None. * *******************************************************************************/ -static u32 XDptx_RunTraining(XDptx *InstancePtr) +static u32 XDp_TxRunTraining(XDp *InstancePtr) { u32 Status; - XDptx_TrainingState TrainingState = XDPTX_TS_CLOCK_RECOVERY; + XDp_TxTrainingState TrainingState = XDP_TX_TS_CLOCK_RECOVERY; while (1) { switch (TrainingState) { - case XDPTX_TS_CLOCK_RECOVERY: - TrainingState = XDptx_TrainingStateClockRecovery( + case XDP_TX_TS_CLOCK_RECOVERY: + TrainingState = XDp_TxTrainingStateClockRecovery( InstancePtr); break; - case XDPTX_TS_CHANNEL_EQUALIZATION: - TrainingState = XDptx_TrainingStateChannelEqualization( + case XDP_TX_TS_CHANNEL_EQUALIZATION: + TrainingState = XDp_TxTrainingStateChannelEqualization( InstancePtr); break; - case XDPTX_TS_ADJUST_LINK_RATE: - TrainingState = XDptx_TrainingStateAdjustLinkRate( + case XDP_TX_TS_ADJUST_LINK_RATE: + TrainingState = XDp_TxTrainingStateAdjustLinkRate( InstancePtr); break; - case XDPTX_TS_ADJUST_LANE_COUNT: - TrainingState = XDptx_TrainingStateAdjustLaneCount( + case XDP_TX_TS_ADJUST_LANE_COUNT: + TrainingState = XDp_TxTrainingStateAdjustLaneCount( InstancePtr); break; default: break; } - if (TrainingState == XDPTX_TS_SUCCESS) { + if (TrainingState == XDP_TX_TS_SUCCESS) { break; } - else if (TrainingState == XDPTX_TS_FAILURE) { + else if (TrainingState == XDP_TX_TS_FAILURE) { return XST_FAILURE; } - if ((InstancePtr->TrainAdaptive == 0) && - ((TrainingState == XDPTX_TS_ADJUST_LANE_COUNT) || - (TrainingState == XDPTX_TS_ADJUST_LINK_RATE))) { + if ((InstancePtr->TxInstance.TrainAdaptive == 0) && + ((TrainingState == XDP_TX_TS_ADJUST_LANE_COUNT) || + (TrainingState == XDP_TX_TS_ADJUST_LINK_RATE))) { return XST_FAILURE; } } /* Final status check. */ - Status = XDptx_CheckLinkStatus(InstancePtr, - InstancePtr->LinkConfig.LaneCount); + Status = XDp_TxCheckLinkStatus(InstancePtr, + InstancePtr->TxInstance.LinkConfig.LaneCount); if (Status != XST_SUCCESS) { return XST_FAILURE; } @@ -1496,61 +1782,61 @@ static u32 XDptx_RunTraining(XDptx *InstancePtr) * For a more detailed description of the clock recovery sequence, see section * 3.5.1.2.1 of the DisplayPort 1.2a specification document. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return The next training state: - * - XDPTX_TS_CHANNEL_EQUALIZATION if the clock recovery sequence + * - XDP_TX_TS_CHANNEL_EQUALIZATION if the clock recovery sequence * completed successfully. - * - XDPTX_TS_FAILURE if writing the drive settings to the RX + * - XDP_TX_TS_FAILURE if writing the drive settings to the RX * device was unsuccesful. - * - XDPTX_TS_ADJUST_LINK_RATE if the clock recovery sequence + * - XDP_TX_TS_ADJUST_LINK_RATE if the clock recovery sequence * did not complete successfully. * * @note None. * *******************************************************************************/ -static XDptx_TrainingState XDptx_TrainingStateClockRecovery(XDptx *InstancePtr) +static XDp_TxTrainingState XDp_TxTrainingStateClockRecovery(XDp *InstancePtr) { u32 Status; u32 DelayUs; u8 PrevVsLevel = 0; u8 SameVsLevelCount = 0; - XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; + XDp_TxLinkConfig *LinkConfig = &InstancePtr->TxInstance.LinkConfig; /* Obtain the required delay for clock recovery as specified by the * RX device. */ - DelayUs = XDptx_GetTrainingDelay(InstancePtr, XDPTX_TS_CLOCK_RECOVERY); + DelayUs = XDp_TxGetTrainingDelay(InstancePtr, XDP_TX_TS_CLOCK_RECOVERY); /* Start CRLock. */ /* Transmit training pattern 1. */ /* Disable the scrambler. */ /* Start from minimal voltage swing and pre-emphasis levels. */ - InstancePtr->LinkConfig.VsLevel = 0; - InstancePtr->LinkConfig.PeLevel = 0; - Status = XDptx_SetTrainingPattern(InstancePtr, - XDPTX_TRAINING_PATTERN_SET_TP1); + InstancePtr->TxInstance.LinkConfig.VsLevel = 0; + InstancePtr->TxInstance.LinkConfig.PeLevel = 0; + Status = XDp_TxSetTrainingPattern(InstancePtr, + XDP_TX_TRAINING_PATTERN_SET_TP1); if (Status != XST_SUCCESS) { - return XDPTX_TS_FAILURE; + return XDP_TX_TS_FAILURE; } while (1) { /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */ - XDptx_WaitUs(InstancePtr, DelayUs); + XDp_WaitUs(InstancePtr, DelayUs); /* Get lane and adjustment requests. */ - Status = XDptx_GetLaneStatusAdjReqs(InstancePtr); + Status = XDp_TxGetLaneStatusAdjReqs(InstancePtr); if (Status != XST_SUCCESS) { /* The AUX read failed. */ - return XDPTX_TS_FAILURE; + return XDP_TX_TS_FAILURE; } /* Check if all lanes have realized and maintained the frequency * lock and get adjustment requests. */ - Status = XDptx_CheckClockRecovery(InstancePtr, - InstancePtr->LinkConfig.LaneCount); + Status = XDp_TxCheckClockRecovery(InstancePtr, + InstancePtr->TxInstance.LinkConfig.LaneCount); if (Status == XST_SUCCESS) { - return XDPTX_TS_CHANNEL_EQUALIZATION; + return XDP_TX_TS_CHANNEL_EQUALIZATION; } /* Check if the same voltage swing for each lane has been used 5 @@ -1565,19 +1851,19 @@ static XDptx_TrainingState XDptx_TrainingStateClockRecovery(XDptx *InstancePtr) if (SameVsLevelCount >= 5) { break; } - if (LinkConfig->VsLevel == XDPTX_MAXIMUM_VS_LEVEL) { + if (LinkConfig->VsLevel == XDP_TX_MAXIMUM_VS_LEVEL) { break; } /* Adjust the drive settings as requested by the RX device. */ - Status = XDptx_AdjVswingPreemp(InstancePtr); + Status = XDp_TxAdjVswingPreemp(InstancePtr); if (Status != XST_SUCCESS) { /* The AUX write failed. */ - return XDPTX_TS_FAILURE; + return XDP_TX_TS_FAILURE; } } - return XDPTX_TS_ADJUST_LINK_RATE; + return XDP_TX_TS_ADJUST_LINK_RATE; } /******************************************************************************/ @@ -1603,79 +1889,80 @@ static XDptx_TrainingState XDptx_TrainingStateClockRecovery(XDptx *InstancePtr) * For a more detailed description of the channel equalization sequence, see * section 3.5.1.2.2 of the DisplayPort 1.2a specification document. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return The next training state: - * - XDPTX_TS_SUCCESS if training succeeded. - * - XDPTX_TS_FAILURE if writing the drive settings to the RX + * - XDP_TX_TS_SUCCESS if training succeeded. + * - XDP_TX_TS_FAILURE if writing the drive settings to the RX * device was unsuccesful. - * - XDPTX_TS_ADJUST_LINK_RATE if, after 5 loop iterations, the + * - XDP_TX_TS_ADJUST_LINK_RATE if, after 5 loop iterations, the * channel equalization sequence did not complete successfully. * * @note None. * *******************************************************************************/ -static XDptx_TrainingState XDptx_TrainingStateChannelEqualization( - XDptx *InstancePtr) +static XDp_TxTrainingState XDp_TxTrainingStateChannelEqualization( + XDp *InstancePtr) { u32 Status; u32 DelayUs; u32 IterationCount = 0; - XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; + XDp_TxLinkConfig *LinkConfig = &InstancePtr->TxInstance.LinkConfig; /* Obtain the required delay for channel equalization as specified by * the RX device. */ - DelayUs = XDptx_GetTrainingDelay(InstancePtr, - XDPTX_TS_CHANNEL_EQUALIZATION); + DelayUs = XDp_TxGetTrainingDelay(InstancePtr, + XDP_TX_TS_CHANNEL_EQUALIZATION); /* Start channel equalization. */ /* Write the current drive settings. */ /* Transmit training pattern 2/3. */ - if (InstancePtr->RxConfig.DpcdRxCapsField[XDPTX_DPCD_MAX_LANE_COUNT] & - XDPTX_DPCD_TPS3_SUPPORT_MASK) { - Status = XDptx_SetTrainingPattern(InstancePtr, - XDPTX_TRAINING_PATTERN_SET_TP3); + if (InstancePtr->TxInstance.RxConfig. + DpcdRxCapsField[XDP_DPCD_MAX_LANE_COUNT] & + XDP_DPCD_TPS3_SUPPORT_MASK) { + Status = XDp_TxSetTrainingPattern(InstancePtr, + XDP_TX_TRAINING_PATTERN_SET_TP3); } else { - Status = XDptx_SetTrainingPattern(InstancePtr, - XDPTX_TRAINING_PATTERN_SET_TP2); + Status = XDp_TxSetTrainingPattern(InstancePtr, + XDP_TX_TRAINING_PATTERN_SET_TP2); } if (Status != XST_SUCCESS) { - return XDPTX_TS_FAILURE; + return XDP_TX_TS_FAILURE; } while (IterationCount < 5) { /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */ - XDptx_WaitUs(InstancePtr, DelayUs); + XDp_WaitUs(InstancePtr, DelayUs); /* Get lane and adjustment requests. */ - Status = XDptx_GetLaneStatusAdjReqs(InstancePtr); + Status = XDp_TxGetLaneStatusAdjReqs(InstancePtr); if (Status != XST_SUCCESS) { /* The AUX read failed. */ - return XDPTX_TS_FAILURE; + return XDP_TX_TS_FAILURE; } /* Check that all lanes still have their clocks locked. */ - Status = XDptx_CheckClockRecovery(InstancePtr, - InstancePtr->LinkConfig.LaneCount); + Status = XDp_TxCheckClockRecovery(InstancePtr, + InstancePtr->TxInstance.LinkConfig.LaneCount); if (Status != XST_SUCCESS) { break; } /* Check that all lanes stihave accomplished channel * equalization, symbol lock, and interlane alignment. */ - Status = XDptx_CheckChannelEqualization(InstancePtr, - InstancePtr->LinkConfig.LaneCount); + Status = XDp_TxCheckChannelEqualization(InstancePtr, + InstancePtr->TxInstance.LinkConfig.LaneCount); if (Status == XST_SUCCESS) { - return XDPTX_TS_SUCCESS; + return XDP_TX_TS_SUCCESS; } /* Adjust the drive settings as requested by the RX device. */ - Status = XDptx_AdjVswingPreemp(InstancePtr); + Status = XDp_TxAdjVswingPreemp(InstancePtr); if (Status != XST_SUCCESS) { /* The AUX write failed. */ - return XDPTX_TS_FAILURE; + return XDP_TX_TS_FAILURE; } IterationCount++; @@ -1683,7 +1970,7 @@ static XDptx_TrainingState XDptx_TrainingStateChannelEqualization( /* Tried MaxIteration times with no success. Try a reduced bitrate * first, then reduce the number of lanes. */ - return XDPTX_TS_ADJUST_LINK_RATE; + return XDP_TX_TS_ADJUST_LINK_RATE; } /******************************************************************************/ @@ -1694,43 +1981,43 @@ static XDptx_TrainingState XDptx_TrainingStateChannelEqualization( * recovery) at the reduced data rate. If the data rate is already at 1.62 Gbps, * a downshift in lane count will be attempted. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return The next training state: - * - XDPTX_TS_ADJUST_LANE_COUNT if the minimal data rate is already + * - XDP_TX_TS_ADJUST_LANE_COUNT if the minimal data rate is already * in use. Re-attempt training at a reduced lane count. - * - XDPTX_TS_CLOCK_RECOVERY otherwise. Re-attempt training. + * - XDP_TX_TS_CLOCK_RECOVERY otherwise. Re-attempt training. * * @note None. * *******************************************************************************/ -static XDptx_TrainingState XDptx_TrainingStateAdjustLinkRate(XDptx *InstancePtr) +static XDp_TxTrainingState XDp_TxTrainingStateAdjustLinkRate(XDp *InstancePtr) { u32 Status; - switch (InstancePtr->LinkConfig.LinkRate) { - case XDPTX_LINK_BW_SET_540GBPS: - Status = XDptx_SetLinkRate(InstancePtr, - XDPTX_LINK_BW_SET_270GBPS); + switch (InstancePtr->TxInstance.LinkConfig.LinkRate) { + case XDP_TX_LINK_BW_SET_540GBPS: + Status = XDp_TxSetLinkRate(InstancePtr, + XDP_TX_LINK_BW_SET_270GBPS); if (Status != XST_SUCCESS) { - Status = XDPTX_TS_FAILURE; + Status = XDP_TX_TS_FAILURE; break; } - Status = XDPTX_TS_CLOCK_RECOVERY; + Status = XDP_TX_TS_CLOCK_RECOVERY; break; - case XDPTX_LINK_BW_SET_270GBPS: - Status = XDptx_SetLinkRate(InstancePtr, - XDPTX_LINK_BW_SET_162GBPS); + case XDP_TX_LINK_BW_SET_270GBPS: + Status = XDp_TxSetLinkRate(InstancePtr, + XDP_TX_LINK_BW_SET_162GBPS); if (Status != XST_SUCCESS) { - Status = XDPTX_TS_FAILURE; + Status = XDP_TX_TS_FAILURE; break; } - Status = XDPTX_TS_CLOCK_RECOVERY; + Status = XDP_TX_TS_CLOCK_RECOVERY; break; default: /* Already at the lowest link rate. Try reducing the lane * count next. */ - Status = XDPTX_TS_ADJUST_LANE_COUNT; + Status = XDP_TX_TS_ADJUST_LANE_COUNT; break; } @@ -1749,58 +2036,57 @@ static XDptx_TrainingState XDptx_TrainingStateAdjustLinkRate(XDptx *InstancePtr) * used with the reduced lane count to train at the main link at * the maximum bandwidth possible. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return The next training state: - * - XDPTX_TS_FAILURE if only one lane is already in use. - * - XDPTX_TS_CLOCK_RECOVERY otherwise. Re-attempt training. + * - XDP_TX_TS_FAILURE if only one lane is already in use. + * - XDP_TX_TS_CLOCK_RECOVERY otherwise. Re-attempt training. * * @note None. * *******************************************************************************/ -static XDptx_TrainingState XDptx_TrainingStateAdjustLaneCount( - XDptx *InstancePtr) +static XDp_TxTrainingState XDp_TxTrainingStateAdjustLaneCount(XDp *InstancePtr) { u32 Status; - XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; + XDp_TxLinkConfig *LinkConfig = &InstancePtr->TxInstance.LinkConfig; switch (LinkConfig->LaneCount) { - case XDPTX_LANE_COUNT_SET_4: - Status = XDptx_SetLaneCount(InstancePtr, - XDPTX_LANE_COUNT_SET_2); + case XDP_TX_LANE_COUNT_SET_4: + Status = XDp_TxSetLaneCount(InstancePtr, + XDP_TX_LANE_COUNT_SET_2); if (Status != XST_SUCCESS) { - Status = XDPTX_TS_FAILURE; + Status = XDP_TX_TS_FAILURE; break; } - Status = XDptx_SetLinkRate(InstancePtr, + Status = XDp_TxSetLinkRate(InstancePtr, LinkConfig->MaxLinkRate); if (Status != XST_SUCCESS) { - Status = XDPTX_TS_FAILURE; + Status = XDP_TX_TS_FAILURE; break; } - Status = XDPTX_TS_CLOCK_RECOVERY; + Status = XDP_TX_TS_CLOCK_RECOVERY; break; - case XDPTX_LANE_COUNT_SET_2: - Status = XDptx_SetLaneCount(InstancePtr, - XDPTX_LANE_COUNT_SET_1); + case XDP_TX_LANE_COUNT_SET_2: + Status = XDp_TxSetLaneCount(InstancePtr, + XDP_TX_LANE_COUNT_SET_1); if (Status != XST_SUCCESS) { - Status = XDPTX_TS_FAILURE; + Status = XDP_TX_TS_FAILURE; break; } - Status = XDptx_SetLinkRate(InstancePtr, + Status = XDp_TxSetLinkRate(InstancePtr, LinkConfig->MaxLinkRate); if (Status != XST_SUCCESS) { - Status = XDPTX_TS_FAILURE; + Status = XDP_TX_TS_FAILURE; break; } - Status = XDPTX_TS_CLOCK_RECOVERY; + Status = XDP_TX_TS_CLOCK_RECOVERY; break; default: /* Already at the lowest lane count. Training has failed at the * lowest lane count and link rate. */ - Status = XDPTX_TS_FAILURE; + Status = XDP_TX_TS_FAILURE; break; } @@ -1811,10 +2097,10 @@ static XDptx_TrainingState XDptx_TrainingStateAdjustLaneCount( /** * This function will do a burst AUX read from the RX device over the AUX * channel. The contents of the status registers will be stored for later use by - * XDptx_CheckClockRecovery, XDptx_CheckChannelEqualization, and - * XDptx_AdjVswingPreemp. + * XDp_TxCheckClockRecovery, XDp_TxCheckChannelEqualization, and + * XDp_TxAdjVswingPreemp. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if the AUX read was successful. @@ -1823,14 +2109,14 @@ static XDptx_TrainingState XDptx_TrainingStateAdjustLaneCount( * @note None. * *******************************************************************************/ -static u32 XDptx_GetLaneStatusAdjReqs(XDptx *InstancePtr) +static u32 XDp_TxGetLaneStatusAdjReqs(XDp *InstancePtr) { u32 Status; /* Read and store 4 bytes of lane status and 2 bytes of adjustment * requests. */ - Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_STATUS_LANE_0_1, - 6, InstancePtr->RxConfig.LaneStatusAdjReqs); + Status = XDp_TxAuxRead(InstancePtr, XDP_DPCD_STATUS_LANE_0_1, + 6, InstancePtr->TxInstance.RxConfig.LaneStatusAdjReqs); if (Status != XST_SUCCESS) { return XST_FAILURE; } @@ -1845,7 +2131,7 @@ static u32 XDptx_GetLaneStatusAdjReqs(XDptx *InstancePtr) * successful - the RX device's link clock and data recovery unit has realized * and maintained the frequency lock for all lanes currently in use. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LaneCount is the number of lanes to check. * * @return @@ -1856,34 +2142,34 @@ static u32 XDptx_GetLaneStatusAdjReqs(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -static u32 XDptx_CheckClockRecovery(XDptx *InstancePtr, u8 LaneCount) +static u32 XDp_TxCheckClockRecovery(XDp *InstancePtr, u8 LaneCount) { u32 Status; u8 AuxData[6]; - u8 *LaneStatus = InstancePtr->RxConfig.LaneStatusAdjReqs; + u8 *LaneStatus = InstancePtr->TxInstance.RxConfig.LaneStatusAdjReqs; /* Check that all LANEx_CR_DONE bits are set. */ switch (LaneCount) { - case XDPTX_LANE_COUNT_SET_4: + case XDP_TX_LANE_COUNT_SET_4: if (!(LaneStatus[1] & - XDPTX_DPCD_STATUS_LANE_3_CR_DONE_MASK)) { + XDP_DPCD_STATUS_LANE_3_CR_DONE_MASK)) { return XST_FAILURE; } if (!(LaneStatus[1] & - XDPTX_DPCD_STATUS_LANE_2_CR_DONE_MASK)) { + XDP_DPCD_STATUS_LANE_2_CR_DONE_MASK)) { return XST_FAILURE; } /* Drop through and check lane 1. */ - case XDPTX_LANE_COUNT_SET_2: + case XDP_TX_LANE_COUNT_SET_2: if (!(LaneStatus[0] & - XDPTX_DPCD_STATUS_LANE_1_CR_DONE_MASK)) { + XDP_DPCD_STATUS_LANE_1_CR_DONE_MASK)) { return XST_FAILURE; } /* Drop through and check lane 0. */ - case XDPTX_LANE_COUNT_SET_1: + case XDP_TX_LANE_COUNT_SET_1: if (!(LaneStatus[0] & - XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK)) { + XDP_DPCD_STATUS_LANE_0_CR_DONE_MASK)) { return XST_FAILURE; } default: @@ -1901,7 +2187,7 @@ static u32 XDptx_CheckClockRecovery(XDptx *InstancePtr, u8 LaneCount) * successful - the RX device has achieved channel equalization, symbol lock, * and interlane alignment for all lanes currently in use. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LaneCount is the number of lanes to check. * * @return @@ -1913,33 +2199,33 @@ static u32 XDptx_CheckClockRecovery(XDptx *InstancePtr, u8 LaneCount) * @note None. * *******************************************************************************/ -static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount) +static u32 XDp_TxCheckChannelEqualization(XDp *InstancePtr, u8 LaneCount) { u32 Status; u8 AuxData[6]; - u8 *LaneStatus = InstancePtr->RxConfig.LaneStatusAdjReqs; + u8 *LaneStatus = InstancePtr->TxInstance.RxConfig.LaneStatusAdjReqs; /* Check that all LANEx_CHANNEL_EQ_DONE bits are set. */ switch (LaneCount) { - case XDPTX_LANE_COUNT_SET_4: + case XDP_TX_LANE_COUNT_SET_4: if (!(LaneStatus[1] & - XDPTX_DPCD_STATUS_LANE_3_CE_DONE_MASK)) { + XDP_DPCD_STATUS_LANE_3_CE_DONE_MASK)) { return XST_FAILURE; } if (!(LaneStatus[1] & - XDPTX_DPCD_STATUS_LANE_2_CE_DONE_MASK)) { + XDP_DPCD_STATUS_LANE_2_CE_DONE_MASK)) { return XST_FAILURE; } /* Drop through and check lane 1. */ - case XDPTX_LANE_COUNT_SET_2: + case XDP_TX_LANE_COUNT_SET_2: if (!(LaneStatus[0] & - XDPTX_DPCD_STATUS_LANE_1_CE_DONE_MASK)) { + XDP_DPCD_STATUS_LANE_1_CE_DONE_MASK)) { return XST_FAILURE; } /* Drop through and check lane 0. */ - case XDPTX_LANE_COUNT_SET_1: + case XDP_TX_LANE_COUNT_SET_1: if (!(LaneStatus[0] & - XDPTX_DPCD_STATUS_LANE_0_CE_DONE_MASK)) { + XDP_DPCD_STATUS_LANE_0_CE_DONE_MASK)) { return XST_FAILURE; } default: @@ -1949,25 +2235,25 @@ static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount) /* Check that all LANEx_SYMBOL_LOCKED bits are set. */ switch (LaneCount) { - case XDPTX_LANE_COUNT_SET_4: + case XDP_TX_LANE_COUNT_SET_4: if (!(LaneStatus[1] & - XDPTX_DPCD_STATUS_LANE_3_SL_DONE_MASK)) { + XDP_DPCD_STATUS_LANE_3_SL_DONE_MASK)) { return XST_FAILURE; } if (!(LaneStatus[1] & - XDPTX_DPCD_STATUS_LANE_2_SL_DONE_MASK)) { + XDP_DPCD_STATUS_LANE_2_SL_DONE_MASK)) { return XST_FAILURE; } /* Drop through and check lane 1. */ - case XDPTX_LANE_COUNT_SET_2: + case XDP_TX_LANE_COUNT_SET_2: if (!(LaneStatus[0] & - XDPTX_DPCD_STATUS_LANE_1_SL_DONE_MASK)) { + XDP_DPCD_STATUS_LANE_1_SL_DONE_MASK)) { return XST_FAILURE; } /* Drop through and check lane 0. */ - case XDPTX_LANE_COUNT_SET_1: + case XDP_TX_LANE_COUNT_SET_1: if (!(LaneStatus[0] & - XDPTX_DPCD_STATUS_LANE_0_SL_DONE_MASK)) { + XDP_DPCD_STATUS_LANE_0_SL_DONE_MASK)) { return XST_FAILURE; } default: @@ -1977,7 +2263,7 @@ static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount) /* Check that interlane alignment is done. */ if (!(LaneStatus[2] & - XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK)) { + XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK)) { return XST_FAILURE; } @@ -1989,7 +2275,7 @@ static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount) * This function sets current voltage swing and pre-emphasis level settings from * the LinkConfig structure to hardware. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param AuxData is a pointer to the array used for preparing a burst * write over the AUX channel. * @@ -2001,23 +2287,25 @@ static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount) * represent the DisplayPort pre-emphasis levels. * *******************************************************************************/ -static void XDptx_SetVswingPreemp(XDptx *InstancePtr, u8 *AuxData) +static void XDp_TxSetVswingPreemp(XDp *InstancePtr, u8 *AuxData) { u32 Status; u8 Data; u8 Index; - u8 VsLevelRx = InstancePtr->LinkConfig.VsLevel; - u8 PeLevelRx = InstancePtr->LinkConfig.PeLevel; + u8 VsLevelRx = InstancePtr->TxInstance.LinkConfig.VsLevel; + u8 PeLevelRx = InstancePtr->TxInstance.LinkConfig.PeLevel; u32 VsLevel; u32 PeLevel; - if (InstancePtr->BoardChar.HasRedriverInPath == 0) { - PeLevel = InstancePtr->BoardChar.TxPeLevels[PeLevelRx]; - VsLevel = InstancePtr->BoardChar.TxVsLevels[VsLevelRx]; + if (InstancePtr->TxInstance.BoardChar.HasRedriverInPath == 0) { + PeLevel = + InstancePtr->TxInstance.BoardChar.TxPeLevels[PeLevelRx]; + VsLevel = + InstancePtr->TxInstance.BoardChar.TxVsLevels[VsLevelRx]; /* Need to compensate due to no redriver in the path. */ if (PeLevelRx != 0) { - VsLevel += InstancePtr->BoardChar.TxVsOffset; + VsLevel += InstancePtr->TxInstance.BoardChar.TxVsOffset; } } else { @@ -2033,30 +2321,31 @@ static void XDptx_SetVswingPreemp(XDptx *InstancePtr, u8 *AuxData) } /* Set up the data buffer for writing to the RX device. */ - Data = (PeLevelRx << XDPTX_DPCD_TRAINING_LANEX_SET_PE_SHIFT) | + Data = (PeLevelRx << XDP_DPCD_TRAINING_LANEX_SET_PE_SHIFT) | VsLevelRx; /* The maximum voltage swing has been reached. */ - if (VsLevelRx == XDPTX_MAXIMUM_VS_LEVEL) { - Data |= XDPTX_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK; + if (VsLevelRx == XDP_TX_MAXIMUM_VS_LEVEL) { + Data |= XDP_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK; } /* The maximum pre-emphasis level has been reached. */ - if (PeLevelRx == XDPTX_MAXIMUM_PE_LEVEL) { - Data |= XDPTX_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK; + if (PeLevelRx == XDP_TX_MAXIMUM_PE_LEVEL) { + Data |= XDP_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK; } memset(AuxData, Data, 4); - for (Index = 0; Index < InstancePtr->LinkConfig.LaneCount; Index++) { + for (Index = 0; Index < InstancePtr->TxInstance.LinkConfig.LaneCount; + Index++) { /* Disable pre-cursor levels. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, - XDPTX_PHY_PRECURSOR_LANE_0 + 4 * Index, 0x0); + XDp_WriteReg(InstancePtr->Config.BaseAddr, + XDP_TX_PHY_PRECURSOR_LANE_0 + 4 * Index, 0x0); /* Write new voltage swing levels to the TX registers. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, - XDPTX_PHY_VOLTAGE_DIFF_LANE_0 + 4 * Index, VsLevel); + XDp_WriteReg(InstancePtr->Config.BaseAddr, + XDP_TX_PHY_VOLTAGE_DIFF_LANE_0 + 4 * Index, VsLevel); /* Write new pre-emphasis levels to the TX registers. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, - XDPTX_PHY_POSTCURSOR_LANE_0 + 4 * Index, PeLevel); + XDp_WriteReg(InstancePtr->Config.BaseAddr, + XDP_TX_PHY_POSTCURSOR_LANE_0 + 4 * Index, PeLevel); } } @@ -2065,7 +2354,7 @@ static void XDptx_SetVswingPreemp(XDptx *InstancePtr, u8 *AuxData) * This function sets new voltage swing and pre-emphasis levels using the * adjustment requests obtained from the RX device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if the new levels were written successfully. @@ -2074,42 +2363,47 @@ static void XDptx_SetVswingPreemp(XDptx *InstancePtr, u8 *AuxData) * @note None. * *******************************************************************************/ -static u32 XDptx_AdjVswingPreemp(XDptx *InstancePtr) +static u32 XDp_TxAdjVswingPreemp(XDp *InstancePtr) { u32 Status; u8 Index; u8 VsLevelAdjReq[4]; u8 PeLevelAdjReq[4]; u8 AuxData[4]; - u8 *AdjReqs = &InstancePtr->RxConfig.LaneStatusAdjReqs[4]; + u8 *AdjReqs = &InstancePtr->TxInstance.RxConfig.LaneStatusAdjReqs[4]; /* Analyze the adjustment requests for changes in voltage swing and * pre-emphasis levels. */ - VsLevelAdjReq[0] = AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK; - VsLevelAdjReq[1] = (AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >> - XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT; - VsLevelAdjReq[2] = AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK; - VsLevelAdjReq[3] = (AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >> - XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT; - PeLevelAdjReq[0] = (AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >> - XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT; - PeLevelAdjReq[1] = (AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >> - XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT; - PeLevelAdjReq[2] = (AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >> - XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT; - PeLevelAdjReq[3] = (AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >> - XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT; + VsLevelAdjReq[0] = AdjReqs[0] & XDP_DPCD_ADJ_REQ_LANE_0_2_VS_MASK; + VsLevelAdjReq[1] = (AdjReqs[0] & XDP_DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >> + XDP_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT; + VsLevelAdjReq[2] = AdjReqs[1] & XDP_DPCD_ADJ_REQ_LANE_0_2_VS_MASK; + VsLevelAdjReq[3] = (AdjReqs[1] & XDP_DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >> + XDP_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT; + PeLevelAdjReq[0] = (AdjReqs[0] & XDP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >> + XDP_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT; + PeLevelAdjReq[1] = (AdjReqs[0] & XDP_DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >> + XDP_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT; + PeLevelAdjReq[2] = (AdjReqs[1] & XDP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >> + XDP_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT; + PeLevelAdjReq[3] = (AdjReqs[1] & XDP_DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >> + XDP_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT; /* Change the drive settings to match the adjustment requests. Use the * greatest level requested. */ - InstancePtr->LinkConfig.VsLevel = 0; - InstancePtr->LinkConfig.PeLevel = 0; - for (Index = 0; Index < InstancePtr->LinkConfig.LaneCount; Index++) { - if (VsLevelAdjReq[Index] >InstancePtr->LinkConfig.VsLevel) { - InstancePtr->LinkConfig.VsLevel = VsLevelAdjReq[Index]; + InstancePtr->TxInstance.LinkConfig.VsLevel = 0; + InstancePtr->TxInstance.LinkConfig.PeLevel = 0; + for (Index = 0; Index < InstancePtr->TxInstance.LinkConfig.LaneCount; + Index++) { + if (VsLevelAdjReq[Index] > + InstancePtr->TxInstance.LinkConfig.VsLevel) { + InstancePtr->TxInstance.LinkConfig.VsLevel = + VsLevelAdjReq[Index]; } - if (PeLevelAdjReq[Index] >InstancePtr->LinkConfig.PeLevel) { - InstancePtr->LinkConfig.PeLevel = PeLevelAdjReq[Index]; + if (PeLevelAdjReq[Index] > + InstancePtr->TxInstance.LinkConfig.PeLevel) { + InstancePtr->TxInstance.LinkConfig.PeLevel = + PeLevelAdjReq[Index]; } } @@ -2124,18 +2418,18 @@ static u32 XDptx_AdjVswingPreemp(XDptx *InstancePtr) * VS=2 Valid Valid * VS=3 Valid */ - if (InstancePtr->LinkConfig.PeLevel > - (4 - InstancePtr->LinkConfig.VsLevel)) { - InstancePtr->LinkConfig.PeLevel = - 4 - InstancePtr->LinkConfig.VsLevel; + if (InstancePtr->TxInstance.LinkConfig.PeLevel > + (4 - InstancePtr->TxInstance.LinkConfig.VsLevel)) { + InstancePtr->TxInstance.LinkConfig.PeLevel = + 4 - InstancePtr->TxInstance.LinkConfig.VsLevel; } /* Make the adjustments to both the DisplayPort TX core and the RX * device. */ - XDptx_SetVswingPreemp(InstancePtr, AuxData); + XDp_TxSetVswingPreemp(InstancePtr, AuxData); /* Write the voltage swing and pre-emphasis levels for each lane to the * RX device. */ - Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_TRAINING_LANE0_SET, + Status = XDp_TxAuxWrite(InstancePtr, XDP_DPCD_TRAINING_LANE0_SET, 4, AuxData); if (Status != XST_SUCCESS) { return XST_FAILURE; @@ -2149,12 +2443,12 @@ static u32 XDptx_AdjVswingPreemp(XDptx *InstancePtr) * This function sets the training pattern to be used during link training for * both the DisplayPort TX core and the RX device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Pattern selects the pattern to be used. One of the following: - * - XDPTX_TRAINING_PATTERN_SET_OFF - * - XDPTX_TRAINING_PATTERN_SET_TP1 - * - XDPTX_TRAINING_PATTERN_SET_TP2 - * - XDPTX_TRAINING_PATTERN_SET_TP3 + * - XDP_TX_TRAINING_PATTERN_SET_OFF + * - XDP_TX_TRAINING_PATTERN_SET_TP1 + * - XDP_TX_TRAINING_PATTERN_SET_TP2 + * - XDP_TX_TRAINING_PATTERN_SET_TP3 * * @return * - XST_SUCCESS if setting the pattern was successful. @@ -2163,31 +2457,31 @@ static u32 XDptx_AdjVswingPreemp(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -static u32 XDptx_SetTrainingPattern(XDptx *InstancePtr, u32 Pattern) +static u32 XDp_TxSetTrainingPattern(XDp *InstancePtr, u32 Pattern) { u32 Status; u8 AuxData[5]; /* Write to the DisplayPort TX core. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, - XDPTX_TRAINING_PATTERN_SET, Pattern); + XDp_WriteReg(InstancePtr->Config.BaseAddr, + XDP_TX_TRAINING_PATTERN_SET, Pattern); AuxData[0] = Pattern; /* Write scrambler disable to the DisplayPort TX core. */ switch (Pattern) { - case XDPTX_TRAINING_PATTERN_SET_OFF: - XDptx_WriteReg(InstancePtr->Config.BaseAddr, - XDPTX_SCRAMBLING_DISABLE, 0); - InstancePtr->LinkConfig.ScramblerEn = 1; + case XDP_TX_TRAINING_PATTERN_SET_OFF: + XDp_WriteReg(InstancePtr->Config.BaseAddr, + XDP_TX_SCRAMBLING_DISABLE, 0); + InstancePtr->TxInstance.LinkConfig.ScramblerEn = 1; break; - case XDPTX_TRAINING_PATTERN_SET_TP1: - case XDPTX_TRAINING_PATTERN_SET_TP2: - case XDPTX_TRAINING_PATTERN_SET_TP3: - AuxData[0] |= XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK; - XDptx_WriteReg(InstancePtr->Config.BaseAddr, - XDPTX_SCRAMBLING_DISABLE, 1); - InstancePtr->LinkConfig.ScramblerEn = 0; + case XDP_TX_TRAINING_PATTERN_SET_TP1: + case XDP_TX_TRAINING_PATTERN_SET_TP2: + case XDP_TX_TRAINING_PATTERN_SET_TP3: + AuxData[0] |= XDP_DPCD_TP_SET_SCRAMB_DIS_MASK; + XDp_WriteReg(InstancePtr->Config.BaseAddr, + XDP_TX_SCRAMBLING_DISABLE, 1); + InstancePtr->TxInstance.LinkConfig.ScramblerEn = 0; break; default: break; @@ -2195,10 +2489,10 @@ static u32 XDptx_SetTrainingPattern(XDptx *InstancePtr, u32 Pattern) /* Make the adjustments to both the DisplayPort TX core and the RX * device. */ - XDptx_SetVswingPreemp(InstancePtr, &AuxData[1]); + XDp_TxSetVswingPreemp(InstancePtr, &AuxData[1]); /* Write the voltage swing and pre-emphasis levels for each lane to the * RX device. */ - Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_TP_SET, + Status = XDp_TxAuxWrite(InstancePtr, XDP_DPCD_TP_SET, 5, AuxData); if (Status != XST_SUCCESS) { return XST_FAILURE; @@ -2212,26 +2506,26 @@ static u32 XDptx_SetTrainingPattern(XDptx *InstancePtr, u32 Pattern) * This function determines what the RX device's required training delay is for * link training. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param TrainingState is the current training state; either clock * recovery or channel equalization. * * @return The training delay specified in the RX device's DisplayPort * Configuration Data (DPCD) register, - * XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL. + * XDP_DPCD_TRAIN_AUX_RD_INTERVAL. * * @note None. * *******************************************************************************/ -static u32 XDptx_GetTrainingDelay(XDptx *InstancePtr, - XDptx_TrainingState TrainingState) +static u32 XDp_TxGetTrainingDelay(XDp *InstancePtr, + XDp_TxTrainingState TrainingState) { - u8 *Dpcd = InstancePtr->RxConfig.DpcdRxCapsField; + u8 *Dpcd = InstancePtr->TxInstance.RxConfig.DpcdRxCapsField; u16 Delay; - switch (Dpcd[XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL]) { - case XDPTX_DPCD_TRAIN_AUX_RD_INT_100_400US: - if (TrainingState == XDPTX_TS_CLOCK_RECOVERY) { + switch (Dpcd[XDP_DPCD_TRAIN_AUX_RD_INTERVAL]) { + case XDP_DPCD_TRAIN_AUX_RD_INT_100_400US: + if (TrainingState == XDP_TX_TS_CLOCK_RECOVERY) { /* Delay for the clock recovery phase. */ Delay = 100; } @@ -2240,16 +2534,16 @@ static u32 XDptx_GetTrainingDelay(XDptx *InstancePtr, Delay = 400; } break; - case XDPTX_DPCD_TRAIN_AUX_RD_INT_4MS: + case XDP_DPCD_TRAIN_AUX_RD_INT_4MS: Delay = 4000; break; - case XDPTX_DPCD_TRAIN_AUX_RD_INT_8MS: + case XDP_DPCD_TRAIN_AUX_RD_INT_8MS: Delay = 8000; break; - case XDPTX_DPCD_TRAIN_AUX_RD_INT_12MS: + case XDP_DPCD_TRAIN_AUX_RD_INT_12MS: Delay = 12000; break; - case XDPTX_DPCD_TRAIN_AUX_RD_INT_16MS: + case XDP_DPCD_TRAIN_AUX_RD_INT_16MS: Delay = 16000; break; default: @@ -2268,10 +2562,10 @@ static u32 XDptx_GetTrainingDelay(XDptx *InstancePtr, * If required, the reads and writes are split into multiple requests, each * acting on a maximum of 16 bytes. * - * @param InstancePtr is a pointer to the XDptx instance. - * @param CmdType is the type of AUX command (one of: XDPTX_AUX_CMD_READ, - * XDPTX_AUX_CMD_WRITE, XDPTX_AUX_CMD_I2C_READ, or - * XDPTX_AUX_CMD_I2C_WRITE. + * @param InstancePtr is a pointer to the XDp instance. + * @param CmdType is the type of AUX command (one of: XDP_TX_AUX_CMD_READ, + * XDP_TX_AUX_CMD_WRITE, XDP_TX_AUX_CMD_I2C_READ, or + * XDP_TX_AUX_CMD_I2C_WRITE. * @param Address is the starting address that the AUX transaction will * read/write from/to the RX device. * @param NumBytes is the number of bytes to read/write from/to the RX @@ -2288,11 +2582,11 @@ static u32 XDptx_GetTrainingDelay(XDptx *InstancePtr, * @note None. * *******************************************************************************/ -static u32 XDptx_AuxCommon(XDptx *InstancePtr, u32 CmdType, u32 Address, +static u32 XDp_TxAuxCommon(XDp *InstancePtr, u32 CmdType, u32 Address, u32 NumBytes, u8 *Data) { u32 Status; - XDptx_AuxTransaction Request; + XDp_AuxTransaction Request; u32 BytesLeft; /* Set the start address for AUX transactions. For I2C transactions, @@ -2303,8 +2597,8 @@ static u32 XDptx_AuxCommon(XDptx *InstancePtr, u32 CmdType, u32 Address, while (BytesLeft > 0) { Request.CmdCode = CmdType; - if ((CmdType == XDPTX_AUX_CMD_READ) || - (CmdType == XDPTX_AUX_CMD_WRITE)) { + if ((CmdType == XDP_TX_AUX_CMD_READ) || + (CmdType == XDP_TX_AUX_CMD_WRITE)) { /* Increment address for normal AUX transactions. */ Request.Address = Address + (NumBytes - BytesLeft); } @@ -2320,21 +2614,21 @@ static u32 XDptx_AuxCommon(XDptx *InstancePtr, u32 CmdType, u32 Address, } BytesLeft -= Request.NumBytes; - if ((CmdType == XDPTX_AUX_CMD_I2C_READ) && (BytesLeft > 0)) { + if ((CmdType == XDP_TX_AUX_CMD_I2C_READ) && (BytesLeft > 0)) { /* Middle of a transaction I2C read request. Override * the command code that was set to CmdType. */ - Request.CmdCode = XDPTX_AUX_CMD_I2C_READ_MOT; + Request.CmdCode = XDP_TX_AUX_CMD_I2C_READ_MOT; } - else if ((CmdType == XDPTX_AUX_CMD_I2C_WRITE) && + else if ((CmdType == XDP_TX_AUX_CMD_I2C_WRITE) && (BytesLeft > 0)) { /* Middle of a transaction I2C write request. Override * the command code that was set to CmdType. */ - Request.CmdCode = XDPTX_AUX_CMD_I2C_WRITE_MOT; + Request.CmdCode = XDP_TX_AUX_CMD_I2C_WRITE_MOT; } - XDptx_WaitUs(InstancePtr, InstancePtr->AuxDelayUs); + XDp_WaitUs(InstancePtr, InstancePtr->TxInstance.AuxDelayUs); - Status = XDptx_AuxRequest(InstancePtr, &Request); + Status = XDp_TxAuxRequest(InstancePtr, &Request); if (Status != XST_SUCCESS) { return Status; } @@ -2348,10 +2642,10 @@ static u32 XDptx_AuxCommon(XDptx *InstancePtr, u32 CmdType, u32 Address, * This function submits the supplied AUX request to the RX device over the AUX * channel. If waiting for a reply times out, or if the DisplayPort TX core * indicates that the request was deferred, the request is sent again (up to a - * maximum specified by XDPTX_AUX_MAX_DEFER_COUNT|XDPTX_AUX_MAX_TIMEOUT_COUNT). + * maximum specified by XDP_AUX_MAX_DEFER_COUNT|XDP_AUX_MAX_TIMEOUT_COUNT). * - * @param InstancePtr is a pointer to the XDptx instance. - * @param Request is a pointer to an initialized XDptx_AuxTransaction + * @param InstancePtr is a pointer to the XDp instance. + * @param Request is a pointer to an initialized XDp_AuxTransaction * structure containing the required information for issuing an * AUX command, as well as a write buffer used for write commands, * and a read buffer for read commands. @@ -2366,15 +2660,15 @@ static u32 XDptx_AuxCommon(XDptx *InstancePtr, u32 CmdType, u32 Address, * @note None. * *******************************************************************************/ -static u32 XDptx_AuxRequest(XDptx *InstancePtr, XDptx_AuxTransaction *Request) +static u32 XDp_TxAuxRequest(XDp *InstancePtr, XDp_AuxTransaction *Request) { u32 Status; u32 DeferCount = 0; u32 TimeoutCount = 0; - while ((DeferCount < XDPTX_AUX_MAX_DEFER_COUNT) && - (TimeoutCount < XDPTX_AUX_MAX_TIMEOUT_COUNT)) { - Status = XDptx_AuxWaitReady(InstancePtr); + while ((DeferCount < XDP_AUX_MAX_DEFER_COUNT) && + (TimeoutCount < XDP_AUX_MAX_TIMEOUT_COUNT)) { + Status = XDp_TxAuxWaitReady(InstancePtr); if (Status != XST_SUCCESS) { /* The RX device isn't ready yet. */ TimeoutCount++; @@ -2382,7 +2676,7 @@ static u32 XDptx_AuxRequest(XDptx *InstancePtr, XDptx_AuxTransaction *Request) } /* Send the request. */ - Status = XDptx_AuxRequestSend(InstancePtr, Request); + Status = XDp_TxAuxRequestSend(InstancePtr, Request); if (Status == XST_SEND_ERROR) { /* The request was deferred. */ DeferCount++; @@ -2397,7 +2691,7 @@ static u32 XDptx_AuxRequest(XDptx *InstancePtr, XDptx_AuxTransaction *Request) return Status; } - XDptx_WaitUs(InstancePtr, 100); + XDp_WaitUs(InstancePtr, 100); } /* The request was not successfully received by the RX device. */ @@ -2410,8 +2704,8 @@ static u32 XDptx_AuxRequest(XDptx *InstancePtr, XDptx_AuxTransaction *Request) * channel by writing the command, the destination address, (the write buffer * for write commands), and the data size to the DisplayPort TX core. * - * @param InstancePtr is a pointer to the XDptx instance. - * @param Request is a pointer to an initialized XDptx_AuxTransaction + * @param InstancePtr is a pointer to the XDp instance. + * @param Request is a pointer to an initialized XDp_AuxTransaction * structure containing the required information for issuing an AUX * command. * @@ -2424,63 +2718,62 @@ static u32 XDptx_AuxRequest(XDptx *InstancePtr, XDptx_AuxTransaction *Request) * @note None. * *******************************************************************************/ -static u32 XDptx_AuxRequestSend(XDptx *InstancePtr, - XDptx_AuxTransaction *Request) +static u32 XDp_TxAuxRequestSend(XDp *InstancePtr, XDp_AuxTransaction *Request) { u32 Status; u8 Index; /* Set the address for the request. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_AUX_ADDRESS, + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_AUX_ADDRESS, Request->Address); - if ((Request->CmdCode == XDPTX_AUX_CMD_WRITE) || - (Request->CmdCode == XDPTX_AUX_CMD_I2C_WRITE) || - (Request->CmdCode == XDPTX_AUX_CMD_I2C_WRITE_MOT)) { + if ((Request->CmdCode == XDP_TX_AUX_CMD_WRITE) || + (Request->CmdCode == XDP_TX_AUX_CMD_I2C_WRITE) || + (Request->CmdCode == XDP_TX_AUX_CMD_I2C_WRITE_MOT)) { /* Feed write data into the DisplayPort TX core's write FIFO. */ for (Index = 0; Index < Request->NumBytes; Index++) { - XDptx_WriteReg(InstancePtr->Config.BaseAddr, - XDPTX_AUX_WRITE_FIFO, Request->Data[Index]); + XDp_WriteReg(InstancePtr->Config.BaseAddr, + XDP_TX_AUX_WRITE_FIFO, Request->Data[Index]); } } /* Submit the command and the data size. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_AUX_CMD, - ((Request->CmdCode << XDPTX_AUX_CMD_SHIFT) | + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_AUX_CMD, + ((Request->CmdCode << XDP_TX_AUX_CMD_SHIFT) | ((Request->NumBytes - 1) & - XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK))); + XDP_TX_AUX_CMD_NBYTES_TRANSFER_MASK))); /* Check for a reply from the RX device to the submitted request. */ - Status = XDptx_AuxWaitReply(InstancePtr); + Status = XDp_TxAuxWaitReply(InstancePtr); if (Status != XST_SUCCESS) { /* Waiting for a reply timed out. */ return XST_ERROR_COUNT_MAX; } /* Analyze the reply. */ - Status = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_AUX_REPLY_CODE); - if ((Status == XDPTX_AUX_REPLY_CODE_DEFER) || - (Status == XDPTX_AUX_REPLY_CODE_I2C_DEFER)) { + Status = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_AUX_REPLY_CODE); + if ((Status == XDP_TX_AUX_REPLY_CODE_DEFER) || + (Status == XDP_TX_AUX_REPLY_CODE_I2C_DEFER)) { /* The request was deferred. */ return XST_SEND_ERROR; } - else if ((Status == XDPTX_AUX_REPLY_CODE_NACK) || - (Status == XDPTX_AUX_REPLY_CODE_I2C_NACK)) { + else if ((Status == XDP_TX_AUX_REPLY_CODE_NACK) || + (Status == XDP_TX_AUX_REPLY_CODE_I2C_NACK)) { /* The request was not acknowledged. */ return XST_FAILURE; } /* The request was acknowledged. */ - if ((Request->CmdCode == XDPTX_AUX_CMD_READ) || - (Request->CmdCode == XDPTX_AUX_CMD_I2C_READ) || - (Request->CmdCode == XDPTX_AUX_CMD_I2C_READ_MOT)) { + if ((Request->CmdCode == XDP_TX_AUX_CMD_READ) || + (Request->CmdCode == XDP_TX_AUX_CMD_I2C_READ) || + (Request->CmdCode == XDP_TX_AUX_CMD_I2C_READ_MOT)) { /* Obtain the read data from the reply FIFO. */ for (Index = 0; Index < Request->NumBytes; Index++) { - Request->Data[Index] = XDptx_ReadReg( + Request->Data[Index] = XDp_ReadReg( InstancePtr->Config.BaseAddr, - XDPTX_AUX_REPLY_DATA); + XDP_TX_AUX_REPLY_DATA); } } @@ -2492,7 +2785,7 @@ static u32 XDptx_AuxRequestSend(XDptx *InstancePtr, * This function waits for a reply indicating that the most recent AUX request * has been received by the RX device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if a reply was sent from the RX device. @@ -2501,27 +2794,27 @@ static u32 XDptx_AuxRequestSend(XDptx *InstancePtr, * @note None. * *******************************************************************************/ -static u32 XDptx_AuxWaitReply(XDptx *InstancePtr) +static u32 XDp_TxAuxWaitReply(XDp *InstancePtr) { u32 Timeout = 100; u32 Status; while (0 < Timeout) { - Status = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_INTERRUPT_STATUS); + Status = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_INTERRUPT_STATUS); /* Check for a timeout. */ - if (Status & XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK) { + if (Status & XDP_TX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK) { return XST_ERROR_COUNT_MAX; } /* Check for a reply. */ - if (Status & XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK) { + if (Status & XDP_TX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK) { return XST_SUCCESS; } Timeout--; - XDptx_WaitUs(InstancePtr, 20); + XDp_WaitUs(InstancePtr, 20); } return XST_ERROR_COUNT_MAX; @@ -2531,7 +2824,7 @@ static u32 XDptx_AuxWaitReply(XDptx *InstancePtr) /** * This function waits until another request is no longer in progress. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if the the RX device is no longer busy. @@ -2540,23 +2833,23 @@ static u32 XDptx_AuxWaitReply(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -static u32 XDptx_AuxWaitReady(XDptx *InstancePtr) +static u32 XDp_TxAuxWaitReady(XDp *InstancePtr) { u32 Status; u32 Timeout = 100; /* Wait until the DisplayPort TX core is ready. */ do { - Status = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_INTERRUPT_SIG_STATE); + Status = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_INTERRUPT_SIG_STATE); /* Protect against an infinite loop. */ if (!Timeout--) { return XST_ERROR_COUNT_MAX; } - XDptx_WaitUs(InstancePtr, 20); + XDp_WaitUs(InstancePtr, 20); } - while (Status & XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK); + while (Status & XDP_TX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK); return XST_SUCCESS; } @@ -2566,12 +2859,12 @@ static u32 XDptx_AuxWaitReady(XDptx *InstancePtr) * This function sets the clock frequency for the DisplayPort PHY corresponding * to a desired data rate. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Speed determines what clock frequency will be used based on one * of the following selects: - * - XDPTX_PHY_CLOCK_SELECT_162GBPS = 0x01 - * - XDPTX_PHY_CLOCK_SELECT_270GBPS = 0x03 - * - XDPTX_PHY_CLOCK_SELECT_540GBPS = 0x05 + * - XDP_TX_PHY_CLOCK_SELECT_162GBPS = 0x01 + * - XDP_TX_PHY_CLOCK_SELECT_270GBPS = 0x03 + * - XDP_TX_PHY_CLOCK_SELECT_540GBPS = 0x05 * * @return * - XST_SUCCESS if the reset for each lane is done after the clock @@ -2581,26 +2874,33 @@ static u32 XDptx_AuxWaitReady(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -static u32 XDptx_SetClkSpeed(XDptx *InstancePtr, u32 Speed) +static u32 XDp_TxSetClkSpeed(XDp *InstancePtr, u32 Speed) { u32 Status; u32 RegVal; /* Disable the DisplayPort TX core first. */ - RegVal = XDptx_ReadReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE); - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 0x0); + RegVal = XDp_ReadReg(InstancePtr->Config.BaseAddr, XDP_TX_ENABLE); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_ENABLE, 0x0); /* Change speed of the feedback clock. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, - XDPTX_PHY_CLOCK_SELECT, Speed); + XDp_WriteReg(InstancePtr->Config.BaseAddr, + XDP_TX_PHY_CLOCK_SELECT, Speed); /* Re-enable the DisplayPort TX core if it was previously enabled. */ if (RegVal != 0x0) { - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 0x1); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_ENABLE, 0x1); } /* Wait until the PHY is ready. */ - Status = XDptx_WaitPhyReady(InstancePtr); + if (InstancePtr->Config.MaxLaneCount > 2) { + Status = XDp_WaitPhyReady(InstancePtr, + XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK); + } + else { + Status = XDp_WaitPhyReady(InstancePtr, + XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK); + } if (Status != XST_SUCCESS) { return XST_FAILURE; } @@ -2612,7 +2912,7 @@ static u32 XDptx_SetClkSpeed(XDptx *InstancePtr, u32 Speed) /** * This function waits for the DisplayPort PHY to come out of reset. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_ERROR_COUNT_MAX if the PHY failed to be ready. @@ -2621,29 +2921,29 @@ static u32 XDptx_SetClkSpeed(XDptx *InstancePtr, u32 Speed) * @note None. * *******************************************************************************/ -static u32 XDptx_WaitPhyReady(XDptx *InstancePtr) +static u32 XDp_WaitPhyReady(XDp *InstancePtr, u32 Mask) { u16 Timeout = 20000; u32 PhyStatus; - u32 Mask; + u32 RegPhyStatus; - if (InstancePtr->Config.MaxLaneCount > 2) { - Mask = XDPTX_PHY_STATUS_ALL_LANES_READY_MASK; + if (XDp_CfgGetCoreType(&InstancePtr->Config) == XDP_TX) { + RegPhyStatus = XDP_TX_PHY_STATUS; } else { - Mask = XDPTX_PHY_STATUS_LANES_0_1_READY_MASK; + RegPhyStatus = XDP_RX_PHY_STATUS; } /* Wait until the PHY is ready. */ do { - PhyStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_PHY_STATUS) & Mask; + PhyStatus = XDp_ReadReg(InstancePtr->Config.BaseAddr, + RegPhyStatus) & Mask; /* Protect against an infinite loop. */ if (!Timeout--) { return XST_ERROR_COUNT_MAX; } - XDptx_WaitUs(InstancePtr, 20); + XDp_WaitUs(InstancePtr, 20); } while (PhyStatus != Mask); diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdp.h b/XilinxProcessorIPLib/drivers/dp/src/xdp.h index eaaca32d..04bc8b0e 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdp.h +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp.h @@ -94,21 +94,139 @@ * The DisplayPort (DP) driver consists of functions, structures, and * definitions: * 1) Specific to the DisplayPort TX mode of operation. - * - Prefix: XDptx_* and XDPTX_* + * - Prefix: XDp_Tx* and XDP_TX_* * 2) Specific to the DisplayPort RX mode of operation. - * - Prefix: XDprx_* and XDPRX_* + * - Prefix: XDp_Rx* and XDP_RX_* * 3) Common to both DisplayPort modes of operation. * - Prefix: XDp_* and XDP_* * - * Depending on whether the DisplayPort core is configured for TX or RX mode of - * operation, the set of registers and required functionality will be entirely - * different. - * - A detailed description of the DisplayPort TX functionality and - * associated functions may be found in xdptx.h. xdptx_hw.h contains - * definitions of the TX register space. - * - A detailed description of the DisplayPort RX functionality and - * associated functions may be found in xdprx.h. xdprx_hw.h contains - * definitions of the RX register space. + * Driver description: TX mode of operation + * + * The device driver enables higher-level software (e.g., an application) to + * configure and control a DisplayPort TX soft IP, communicate and control an + * RX device/sink monitor over the AUX channel, and to initialize and transmit + * data streams over the main link. This driver follows the DisplayPort 1.2a + * specification. + * + * This driver implements link layer functionality: a Link Policy Maker (LPM) + * and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification. + * - The LPM manages the main link and is responsible for keeping the link + * synchronized. It will establish a link with a downstream RX device by + * undergoing a link training sequence which consists of: + * - Clock recovery: The clock needs to be recovered and PLLs need to be + * locked for all lanes. + * - Channel equalization: All lanes need to achieve channel equalization + * and and symbol lock, as well as for interlane alignment to take place. + * - The SPM manages transportation of an isochronous stream. That is, it will + * initialize and maintain a video stream, establish a virtual channel to a + * sink monitor, and transmit the stream. + * + * Using AUX transactions to read/write from/to the sink's DisplayPort + * Configuration Data (DPCD) address space, the LPM obtains the link + * capabilities, obtains link configuration and link and sink status, and + * configures and controls the link and sink. The main link is trained this way. + * + * I2C-over-AUX transactions are used to obtain the sink's Extended Display + * Identification Data (EDID) which give information on the display capabilities + * of the monitor. The SPM may use this information to determine what available + * screen resolutions and video timing are possible. + * + * Driver description: RX mode of operation + * + * The device driver enables higher-level software (e.g., an application) to + * configure and control a DisplayPort RX soft IP. + * + * This driver gives applications the ability to configure the RX using various + * settings, handle and issue interrupts, and modify a subset of its DisplayPort + * Configuration Data (DPCD) fields. + * + * Link training is done automatically by the hardware. + * + * Interrupt processing: TX mode of operation + * + * For the driver to process interrupts, the application must set up the + * system's interrupt controller and connect the XDp_InterruptHandler function + * to service interrupts. When an interrupt occurs, XDp_InterruptHandler will + * check which mode of operation the DisplayPort core is running in, and will + * call the appropriate interrupt handler for that core + * (XDp_TxInterruptHandler or XDp_RxInterruptHandler - local to xdp_intr.c). + * + * Interrupt processing: TX mode of operation + * + * DisplayPort interrupts occur on the HPD signal line when the DisplayPort + * cable is connected/disconnected or when the RX device sends a pulse. The user + * hardware design must contain an interrupt controller which the DisplayPort + * TX instance's interrupt signal is connected to. The user application must + * enable interrupts in the system and set up the interrupt controller such that + * the XDp_TxHpdInterruptHandler handler will service DisplayPort interrupts. + * When the XDp_TxHpdInterruptHandler function is invoked, the handler will + * identify what type of DisplayPort interrupt has occurred, and will call + * either the HPD event handler function or the HPD pulse handler function, + * depending on whether a an HPD event on an HPD pulse event occurred. + * + * The DisplayPort TX's XDP_TX_INTERRUPT_STATUS register indicates the type of + * interrupt that has occured, and the XDp_TxInterruptHandler will use this + * information to decide which handler to call. An HPD event is identified if + * bit XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is + * identified from the XDP_TX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit. + * + * The HPD event handler may be set up by using the XDp_TxSetHpdEventHandler + * function and, for the HPD pulse handler, the XDp_TxSetHpdPulseHandler + * function. + * + * Interrupt processing: RX mode of operation + * + * The DisplayPort RX driver may generate a pulse on the hot-plug-detect (HPD) + * signal line using the XDp_RxGenerateHpdInterrupt function. This allows the RX + * to send an interrupt to the upstream TX device, useful for signaling the TX + * that it needs to do some checks for changes in downstream devices or a loss + * of link training. + * + * For RX interrupt handling of HPD events or events that happen internal to the + * RX, the user hardware design must contain an interrupt controller which the + * DisplayPort RX instance's interrupt signal is connected to. The user + * application must enable interrupts in the system and set up the interrupt + * controller such that the XDp_RxInterruptHandler handler will service + * interrupts. When the XDp_RxInterruptHandler function is invoked, the handler + * will identify what type of interrupt has occurred, and will call the + * appropriate interrupt handler. + * + * The DisplayPort RX's XDP_RX_INTERRUPT_CAUSE register indicates the type of + * interrupt that has occured, and the XDp_RxInterruptHandler will use this + * information to decide which handler to call. + * + * The handlers are set up using the XDp_RxSetIntr* functions. + * + * Specific interrupts may be enabled or disabled using the + * XDp_RxInterruptEnable and XDp_RxInterruptDisable functions. + * + * Multi-stream transport (MST) mode: TX mode of operation + * + * The current version of this driver doesn't support MST functionality when the + * core is configured do run in the RX mode of operation. + * + * The driver handles MST mode functionality in TX mode of operation, including + * sideband messaging, topology discovery, virtual channel payload ID table + * management, and directing streams to different sinks. + * + * MST testing has been done at all possible link rate/lane count/topology/ + * resolution/color depth combinations with each setting using following values: + * - Link rate: 1.62, 2.70, and 5.40Gbps per lane. + * - Lane count: 1, 2, and 4 lanes. + * - Number of sink displays: 1, 2, 3, and 4 sink displays in both a daisy-chain + * configuration and in a configuration using a combination of a 1-to-3 hub + * and daisy-chain. Each stream was using the same resolution. + * - Resolutions (60Hz): 640x480, 800x600, 1024x768, 1280x800, 1280x1024, + * 1360x768, 1400x1050, 1680x1050, 1920x1080, 1920x2160, and 3840x2160. + * - Color depths: 18, 24, 30, 36, and 48 bits per pixel. + * + * Audio + * + * The driver does not handle audio. For an example as to how to configure and + * transmit audio, examples/xdptx_audio_example.c illustrates the required + * sequence in the TX mode of operation. The user will need to configure the + * audio source connected to the Displayport TX instance and set up the audio + * info frame as per user requirements. * * Asserts * @@ -118,6 +236,23 @@ * it is recommended that application developers leave asserts on during * development. * + * Limitations: TX mode of operation + * + * - For MST mode to correctly display, the current version of the driver + * requires that each of the DisplayPort TX streams be allocated without + * skipping streams (i.e. assign stream 1, stream 2, and stream 3 - problems + * were experienced if skipping stream 2 and assigning stream 4 instead). + * skipping monitors in a daisy chain is OK as long as they are assigned to + * streams in order. + * - In MST mode, the current version of the driver does not support removal of + * an allocated stream from the virtual channel payload ID table without + * clearing the entire table. + * - Some sideband messages have not been implemented in the current version of + * the driver for MST mode. Notably, reception of a CONNECTION_STATUS_NOTIFY + * sideband message. + * - The driver does not handle audio. See the audio example in the driver + * examples directory for the required sequence for enabling audio. + * * @note For a 5.4Gbps link rate, a high performance 7 series FPGA is * required with a speed grade of -2 or -3. * @@ -126,7 +261,7 @@ * * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- - * 1.0 als 01/20/14 Initial release. + * 1.0 als 01/20/15 Initial release. * * *******************************************************************************/ @@ -139,8 +274,9 @@ #include "xil_assert.h" #include "xil_types.h" +#include "xdp_hw.h" +#include "xstatus.h" #include "xvidc.h" -/* xdprx.h and xdptx.h are included. They require some type definitions. */ /****************************** Type Definitions ******************************/ @@ -183,6 +319,250 @@ typedef struct { 0 = TX, 1 = RX. */ } XDp_Config; +/** + * This typedef contains configuration information about the RX device. + */ +typedef struct { + u8 DpcdRxCapsField[16]; /**< The first 16 bytes of the raw capabilities + field of the RX device's DisplayPort + Configuration Data (DPCD). */ + u8 LaneStatusAdjReqs[6];/**< This is a raw read of the RX device's + status registers. The first 4 bytes + correspond to the lane status associated + with clock recovery, channel + equalization, symbol lock, and interlane + alignment. The remaining 2 bytes + represent the pre-emphasis and voltage + swing level adjustments requested by the + RX device. */ +} XDp_TxSinkConfig; + +/** + * This typedef contains configuration information about the main link settings. + */ +typedef struct { + u8 LaneCount; /**< The current lane count of the main + link. */ + u8 LinkRate; /**< The current link rate of the main + link. */ + u8 ScramblerEn; /**< Symbol scrambling is currently in + use over the main link. */ + u8 EnhancedFramingMode; /**< Enhanced frame mode is currently in + use over the main link. */ + u8 DownspreadControl; /**< Downspread control is currently in + use over the main link. */ + u8 MaxLaneCount; /**< The maximum lane count of the main + link. */ + u8 MaxLinkRate; /**< The maximum link rate of the main + link. */ + u8 SupportEnhancedFramingMode; /**< Enhanced frame mode is supported by + the RX device. */ + u8 SupportDownspreadControl; /**< Downspread control is supported by + the RX device. */ + u8 VsLevel; /**< The current voltage swing level for + each lane. */ + u8 PeLevel; /**< The current pre-emphasis/cursor + level for each lane. */ + u8 Pattern; /**< The current pattern currently in + use over the main link. */ +} XDp_TxLinkConfig; + +/** + * This typedef contains the main stream attributes which determine how the + * video will be displayed. + */ +typedef struct { + XVidC_VideoTimingMode Vtm; /**< The video timing. */ + u32 PixelClockHz; /**< The pixel clock of the stream (in + Hz). */ + u32 HStart; /**< Horizontal blank start (in + pixels). */ + u32 VStart; /**< Vertical blank start (in lines). */ + u32 Misc0; /**< Miscellaneous stream attributes 0 + as specified by the DisplayPort + 1.2 specification. */ + u32 Misc1; /**< Miscellaneous stream attributes 1 + as specified by the DisplayPort + 1.2 specification. */ + u32 NVid; /**< N value for the video stream. */ + u32 UserPixelWidth; /**< The width of the user data input + port. */ + u32 DataPerLane; /**< Used to translate the number of + pixels per line to the native + internal 16-bit datapath. */ + u32 AvgBytesPerTU; /**< Average number of bytes per + transfer unit, scaled up by a + factor of 1000. */ + u32 TransferUnitSize; /**< Size of the transfer unit in the + framing logic. In MST mode, this + is also the number of time slots + that are alloted in the payload + ID table. */ + u32 InitWait; /**< Number of initial wait cycles at + the start of a new line by + the framing logic. */ + u32 BitsPerColor; /**< Number of bits per color + component. */ + u8 ComponentFormat; /**< The component format currently in + use by the video stream. */ + u8 DynamicRange; /**< The dynamic range currently in use + by the video stream. */ + u8 YCbCrColorimetry; /**< The YCbCr colorimetry currently in + use by the video stream. */ + u8 SynchronousClockMode; /**< Synchronous clock mode is currently + in use by the video stream. */ + u8 OverrideUserPixelWidth; /**< If set to 1, the value stored for + UserPixelWidth will be used as + the pixel width. */ +} XDp_TxMainStreamAttributes; + +/** + * This typedef describes a stream when the driver is running in multi-stream + * transport (MST) mode. + */ +typedef struct { + u8 LinkCountTotal; /** The total number of DisplayPort + links from the DisplayPort TX to + the sink device that this MST + stream is targeting.*/ + u8 RelativeAddress[15]; /** The relative address from the + DisplayPort TX to the sink + device that this MST stream is + targeting.*/ + u16 MstPbn; /**< Payload bandwidth number used to + allocate bandwidth for the MST + stream. */ + u8 MstStreamEnable; /**< In MST mode, enables the + corresponding stream for this + MSA configuration. */ +} XDp_TxMstStream; + +/** + * This typedef describes some board characteristics information that affects + * link training. + */ +typedef struct { + u8 HasRedriverInPath; /**< Redriver in path requires different voltage + swing and pre-emphasis. */ + u8 TxVsLevels[4]; /**< The voltage swing levels to be used by the + DisplayPort TX. */ + u8 TxPeLevels[4]; /**< The pre-emphasis/cursor level to be used by + the DisplayPort TX. */ + u8 TxVsOffset; /**< Voltage swing compensation offset used when + pre-emphasis is used. */ +} XDp_TxBoardChar; + +/** + * This typedef describes a downstream DisplayPort device when the driver is + * running in multi-stream transport (MST) mode. + */ +typedef struct { + u32 Guid[4]; /**< The global unique identifier (GUID) + of the device. */ + u8 RelativeAddress[15]; /**< The relative address from the + DisplayPort TX to this + device. */ + u8 DeviceType; /**< The type of DisplayPort device. + Either a branch or sink. */ + u8 LinkCountTotal; /**< The total number of DisplayPort + links connecting this device to + the DisplayPort TX. */ + u8 DpcdRev; /**< The revision of the device's + DisplayPort Configuration Data + (DPCD). For this device to + support MST features, this value + must represent a protocl version + greater or equal to 1.2. */ + u8 MsgCapStatus; /**< This device is capable of sending + and receiving sideband + messages. */ +} XDp_TxTopologyNode; + +/** + * This typedef describes a the entire topology of connected downstream + * DisplayPort devices (from the DisplayPort TX) when the driver is operating + * in multi-stream transport (MST) mode. + */ +typedef struct { + u8 NodeTotal; /**< The total number of nodes that were + found in the MST topology. */ + XDp_TxTopologyNode NodeTable[63]; /**< A table listing all the nodes in + the MST topology. */ + u8 SinkTotal; /**< The total number of sinks in the + MST topology. */ + XDp_TxTopologyNode *SinkList[63]; /**< A pointer list of sinks in the + MST topology. The entries will + point to the sinks in the + NodeTable. */ +} XDp_TxTopology; + +/** + * This typedef describes a port that is connected to a DisplayPort branch + * device. This structure is used when the driver is operating in multi-stream + * transport (MST) mode. + */ +typedef struct { + u8 InputPort; /**< Specifies that this port is an + input port. */ + u8 PeerDeviceType; /**< Specifies the device type connected + to this port. */ + u8 PortNum; /**< The port number of this port. */ + u8 MsgCapStatus; /**< This port or the device at this + port can send and receive MST + messages. */ + u8 DpDevPlugStatus; /**< There is a device connected to this + port. */ + + u8 LegacyDevPlugStatus; /**< This port is connected to a legacy + device. */ + u8 DpcdRev; /**< The DisplayPort Configuration Data + (DPCD) revision of the device + connected to this port. */ + u32 Guid[4]; /**< The global unique identifier (GUID) + of the device connected to this + port. */ + u8 NumSdpStreams; /**< The total number of Secondary-Data + Packet (SDP) streams that this + port can handle. */ + u8 NumSdpStreamSinks; /**< The number of SDP streams + associated with this port. */ +} XDp_TxSbMsgLinkAddressReplyPortDetail; + +/** + * This typedef describes a DisplayPort branch device. This structure is used + * when the driver is operating in multi-stream transport (MST) mode. + */ +typedef struct { + u8 ReplyType; /**< The reply type of the sideband + message. A value of 1 indicates + that the request wasn't + successful and the return data + will give the reason for a + negative-acknowledge (NACK). */ + u8 RequestId; /**< The request identifier of the + reply. This should correspond to + the request identifier for the + LINK_ADDRESS sideband message + request. */ + u32 Guid[4]; /**< The global unique identifier (GUID) + of the branch device. */ + u8 NumPorts; /**< The number of ports associated with + this branch device. */ + XDp_TxSbMsgLinkAddressReplyPortDetail PortDetails[16]; /**< An array + describing all ports attached to + this branch device. */ +} XDp_TxSbMsgLinkAddressReplyDeviceInfo; + +/** + * This typedef contains configuration information about the main link settings. + */ +typedef struct { + u8 LaneCount; /**< The current lane count of the main + link. */ + u8 LinkRate; /**< The current link rate of the main + link. */ +} XDp_RxLinkConfig; + /******************************************************************************/ /** * Callback type which represents a custom timer wait handler. This is only @@ -201,11 +581,364 @@ typedef struct { *******************************************************************************/ typedef void (*XDp_TimerHandler)(void *InstancePtr, u32 MicroSeconds); +/******************************************************************************/ +/** + * Callback type which represents the handler for interrupts. + * + * @param InstancePtr is a pointer to the XDp instance. + * + * @note None. + * +*******************************************************************************/ +typedef void (*XDp_IntrHandler)(void *InstancePtr); + +/** + * The XDp driver instance data representing the TX mode of operation. + */ +typedef struct { + u32 MstEnable; /**< Multi-stream transport + (MST) mode. Enables + functionality, allowing + multiple streams to be + sent over the main + link. */ + u8 TrainAdaptive; /**< Downshift lane count and + link rate if necessary + during training. */ + XDp_TxSinkConfig RxConfig; /**< Configuration structure for + the RX device. */ + XDp_TxLinkConfig LinkConfig; /**< Configuration structure for + the main link. */ + XDp_TxBoardChar BoardChar; /**< Some board characteristics + information that affects + link training. */ + XDp_TxMainStreamAttributes MsaConfig[4]; /**< Configuration structure + for the main stream + attributes (MSA). Each + stream has its own set + of attributes. When MST + mode is disabled, only + MsaConfig[0] is used. */ + XDp_TxMstStream MstStreamConfig[4]; /**< Configuration structure + for a multi-stream + transport (MST) + stream. */ + XDp_TxTopology Topology; /**< The topology of connected + downstream DisplayPort + devices when the driver + is running in MST + mode. */ + u32 AuxDelayUs; /**< Amount of latency in micro- + seconds to use between + AUX transactions. */ + u32 SbMsgDelayUs; /**< Amount of latency in micro- + seconds to use between + sideband messages for + multi-stream transport + (MST) mode. */ + XDp_IntrHandler HpdEventHandler; /**< Callback function for Hot- + Plug-Detect (HPD) event + interrupts. */ + void *HpdEventCallbackRef; /**< A pointer to the user data + passed to the HPD event + callback function. */ + XDp_IntrHandler HpdPulseHandler; /**< Callback function for Hot- + Plug-Detect (HPD) pulse + interrupts. */ + void *HpdPulseCallbackRef; /**< A pointer to the user data + passed to the HPD pulse + callback function. */ +} XDp_Tx; + +/** + * The XDp driver instance data representing the TX mode of operation. + */ +typedef struct { + XDp_RxLinkConfig LinkConfig; /**< Configuration structure for + the main link. */ + XDp_IntrHandler IntrVmChangeHandler; /**< Callback function for video + mode change + interrupts. */ + void *IntrVmChangeCallbackRef; /**< A pointer to the user data + passed to the video mode + change callback + function. */ + XDp_IntrHandler IntrPowerStateHandler; /**< Callback function for + power state change + interrupts. */ + void *IntrPowerStateCallbackRef; /**< A pointer to the user data + passed to the power + state change callback + function. */ + XDp_IntrHandler IntrNoVideoHandler; /**< Callback function for + no video interrupts. */ + void *IntrNoVideoCallbackRef; /**< A pointer to the user data + passed to the no video + callback function. */ + XDp_IntrHandler IntrVBlankHandler; /**< Callback function for + vertical blanking + interrupts. */ + void *IntrVBlankCallbackRef; /**< A pointer to the user data + passed to the vertical + blanking callback + function. */ + XDp_IntrHandler IntrTrainingLostHandler;/**< Callback function for + training lost + interrupts. */ + void *IntrTrainingLostCallbackRef; /**< A pointer to the user data + passed to the training + lost callback + function. */ + XDp_IntrHandler IntrVideoHandler; /**< Callback function for valid + video interrupts. */ + void *IntrVideoCallbackRef; /**< A pointer to the user data + passed to the valid + video callback + function. */ + XDp_IntrHandler IntrTrainingDoneHandler;/**< Callback function for + training done + interrupts. */ + void *IntrTrainingDoneCallbackRef; /**< A pointer to the user data + passed to the training + done callback + function. */ + XDp_IntrHandler IntrBwChangeHandler; /**< Callback function for + bandwidth change + interrupts. */ + void *IntrBwChangeCallbackRef; /**< A pointer to the user data + passed to the bandwidth + change callback + function. */ + XDp_IntrHandler IntrTp1Handler; /**< Callback function for + training pattern 1 + interrupts. */ + void *IntrTp1CallbackRef; /**< A pointer to the user data + passed to the training + pattern 1 callback + function. */ + XDp_IntrHandler IntrTp2Handler; /**< Callback function for + training pattern 2 + interrupts. */ + void *IntrTp2CallbackRef; /**< A pointer to the user data + passed to the training + pattern 2 callback + function. */ + XDp_IntrHandler IntrTp3Handler; /**< Callback function for + training pattern 3 + interrupts. */ + void *IntrTp3CallbackRef; /**< A pointer to the user data + passed to the training + pattern 3 callback + function. */ +} XDp_Rx; + +/** + * The XDp instance data. The user is required to allocate a variable of this + * type for every XDp device in the system. A pointer to a variable of this type + * is then passed to the driver API functions. + */ +typedef struct { + XDp_Config Config; /**< Configuration structure for + the DisplayPort TX + core. */ + u32 IsReady; /**< Device is initialized and + ready. */ + XDp_TimerHandler UserTimerWaitUs; /**< Custom user function for + delay/sleep. */ + void *UserTimerPtr; /**< Pointer to a timer instance + used by the custom user + delay/sleep function. */ + union { + XDp_Tx TxInstance; + XDp_Rx RxInstance; + }; +} XDp; + /**************************** Function Prototypes *****************************/ /* xdp_sinit.c: Configuration extraction function. */ XDp_Config *XDp_LookupConfig(u16 DeviceId); +/* xdp.c: Setup and initialization functions. */ +void XDp_CfgInitialize(XDp *InstancePtr, XDp_Config *ConfigPtr, + u32 EffectiveAddr); +u32 XDp_Initialize(XDp *InstancePtr); +u32 XDp_TxGetRxCapabilities(XDp *InstancePtr); + +/* xdp.c: TX link policy maker functions. */ +u32 XDp_TxCfgMainLinkMax(XDp *InstancePtr); +u32 XDp_TxEstablishLink(XDp *InstancePtr); +u32 XDp_TxCheckLinkStatus(XDp *InstancePtr, u8 LaneCount); +void XDp_TxEnableTrainAdaptive(XDp *InstancePtr, u8 Enable); +void XDp_TxSetHasRedriverInPath(XDp *InstancePtr, u8 Set); +void XDp_TxCfgTxVsOffset(XDp *InstancePtr, u8 Offset); +void XDp_TxCfgTxVsLevel(XDp *InstancePtr, u8 Level, u8 TxLevel); +void XDp_TxCfgTxPeLevel(XDp *InstancePtr, u8 Level, u8 TxLevel); + +/* xdp.c: TX AUX transaction functions. */ +u32 XDp_TxAuxRead(XDp *InstancePtr, u32 DpcdAddress, u32 BytesToRead, + void *ReadData); +u32 XDp_TxAuxWrite(XDp *InstancePtr, u32 DpcdAddress, u32 BytesToWrite, + void *WriteData); +u32 XDp_TxIicRead(XDp *InstancePtr, u8 IicAddress, u16 Offset, + u16 BytesToRead, void *ReadData); +u32 XDp_TxIicWrite(XDp *InstancePtr, u8 IicAddress, u8 BytesToWrite, + void *WriteData); + +/* xdp.c: TX functions for controlling the link configuration. */ +u32 XDp_TxSetDownspread(XDp *InstancePtr, u8 Enable); +u32 XDp_TxSetEnhancedFrameMode(XDp *InstancePtr, u8 Enable); +u32 XDp_TxSetLaneCount(XDp *InstancePtr, u8 LaneCount); +u32 XDp_TxSetLinkRate(XDp *InstancePtr, u8 LinkRate); +u32 XDp_TxSetScrambler(XDp *InstancePtr, u8 Enable); + +/* xdp.c: General usage functions. */ +void XDp_SetUserTimerHandler(XDp *InstancePtr, + XDp_TimerHandler CallbackFunc, void *CallbackRef); +void XDp_WaitUs(XDp *InstancePtr, u32 MicroSeconds); +u32 XDp_TxIsConnected(XDp *InstancePtr); +void XDp_TxEnableMainLink(XDp *InstancePtr); +void XDp_TxDisableMainLink(XDp *InstancePtr); +void XDp_TxResetPhy(XDp *InstancePtr, u32 Reset); +u32 XDp_RxCheckLinkStatus(XDp *InstancePtr); +void XDp_RxDtgEn(XDp *InstancePtr); +void XDp_RxDtgDis(XDp *InstancePtr); +void XDp_RxSetLinkRate(XDp *InstancePtr, u8 LinkRate); +void XDp_RxSetLaneCount(XDp *InstancePtr, u8 LaneCount); + +/* xdp_edid.c: EDID utility functions. */ +u32 XDp_TxGetEdid(XDp *InstancePtr, u8 *Edid); +u32 XDp_TxGetRemoteEdid(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress, u8 *Edid); +u32 XDp_TxGetEdidBlock(XDp *InstancePtr, u8 *Data, u8 BlockNum); +u32 XDp_TxGetRemoteEdidBlock(XDp *InstancePtr, u8 *Data, u8 BlockNum, + u8 LinkCountTotal, u8 *RelativeAddress); +u32 XDp_TxGetRemoteEdidDispIdExt(XDp *InstancePtr, u8 *Data, + u8 LinkCountTotal, u8 *RelativeAddress); +u32 XDp_TxGetDispIdDataBlock(u8 *DisplayIdRaw, u8 SectionTag, + u8 **DataBlockPtr); +u32 XDp_TxGetRemoteTiledDisplayDb(XDp *InstancePtr, u8 *EdidExt, + u8 LinkCountTotal, u8 *RelativeAddress, u8 **DataBlockPtr); + +/* xdp_intr.c: Interrupt handling functions. */ +void XDp_InterruptHandler(XDp *InstancePtr); +void XDp_TxSetHpdEventHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef); +void XDp_TxSetHpdPulseHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef); +void XDp_RxGenerateHpdInterrupt(XDp *InstancePtr, u16 DurationUs); +void XDp_RxInterruptEnable(XDp *InstancePtr, u32 Mask); +void XDp_RxInterruptDisable(XDp *InstancePtr, u32 Mask); +void XDp_RxSetIntrVmChangeHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef); +void XDp_RxSetIntrPowerStateHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef); +void XDp_RxSetIntrNoVideoHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef); +void XDp_RxSetIntrVBlankHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef); +void XDp_RxSetIntrTrainingLostHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef); +void XDp_RxSetIntrVideoHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef); +void XDp_RxSetIntrTrainingDoneHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef); +void XDp_RxSetIntrBwChangeHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef); +void XDp_RxSetIntrTp1Handler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef); +void XDp_RxSetIntrTp2Handler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef); +void XDp_RxSetIntrTp3Handler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef); + +/* xdp_mst.c: Multi-stream transport (MST) functions for enabling or disabling + * MST mode. */ +void XDp_TxMstCfgModeEnable(XDp *InstancePtr); +void XDp_TxMstCfgModeDisable(XDp *InstancePtr); +u32 XDp_TxMstCapable(XDp *InstancePtr); +u32 XDp_TxMstEnable(XDp *InstancePtr); +u32 XDp_TxMstDisable(XDp *InstancePtr); + +/* xdp_mst.c: Multi-stream transport (MST) functions for enabling or disabling + * MST streams and selecting their associated target sinks. */ +void XDp_TxMstCfgStreamEnable(XDp *InstancePtr, u8 Stream); +void XDp_TxMstCfgStreamDisable(XDp *InstancePtr, u8 Stream); +u8 XDp_TxMstStreamIsEnabled(XDp *InstancePtr, u8 Stream); +void XDp_TxSetStreamSelectFromSinkList(XDp *InstancePtr, u8 Stream, u8 + SinkNum); +void XDp_TxSetStreamSinkRad(XDp *InstancePtr, u8 Stream, u8 LinkCountTotal, + u8 *RelativeAddress); + +/* xdp_mst.c: Multi-stream transport (MST) functions related to MST topology + * discovery and management. */ +u32 XDp_TxDiscoverTopology(XDp *InstancePtr); +u32 XDp_TxFindAccessibleDpDevices(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress); +void XDp_TxTopologySwapSinks(XDp *InstancePtr, u8 Index0, u8 Index1); +void XDp_TxTopologySortSinksByTiling(XDp *InstancePtr); + +/* xdp_mst.c: Multi-stream transport (MST) functions for communicating + * with downstream DisplayPort devices. */ +u32 XDp_TxRemoteDpcdRead(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData); +u32 XDp_TxRemoteDpcdWrite(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData); +u32 XDp_TxRemoteIicRead(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress, u8 IicAddress, u16 Offset, u16 BytesToRead, + u8 *ReadData); +u32 XDp_TxRemoteIicWrite(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress, u8 IicAddress, u8 BytesToWrite, u8 *WriteData); + +/* xdp_mst.c: Multi-stream transport (MST) functions related to MST stream + * allocation. */ +u32 XDp_TxAllocatePayloadStreams(XDp *InstancePtr); +u32 XDp_TxAllocatePayloadVcIdTable(XDp *InstancePtr, u8 VcId, u8 Ts); +u32 XDp_TxClearPayloadVcIdTable(XDp *InstancePtr); + +/* xdp_mst.c: Multi-stream transport (MST) functions for issuing sideband + * messages. */ +u32 XDp_TxSendSbMsgRemoteDpcdWrite(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData); +u32 XDp_TxSendSbMsgRemoteDpcdRead(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData); +u32 XDp_TxSendSbMsgRemoteIicWrite(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress, u8 IicDeviceId, u8 BytesToWrite, u8 *WriteData); +u32 XDp_TxSendSbMsgRemoteIicRead(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress, u8 IicDeviceId, u8 Offset, u8 BytesToRead, + u8 *ReadData); +u32 XDp_TxSendSbMsgLinkAddress(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress, XDp_TxSbMsgLinkAddressReplyDeviceInfo *DeviceInfo); +u32 XDp_TxSendSbMsgEnumPathResources(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress, u16 *AvailPbn, u16 *FullPbn); +u32 XDp_TxSendSbMsgAllocatePayload(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress, u8 VcId, u16 Pbn); +u32 XDp_TxSendSbMsgClearPayloadIdTable(XDp *InstancePtr); + +/* xdp_mst.c: Multi-stream transport (MST) utility functions. */ +void XDp_TxWriteGuid(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, + u32 Guid[4]); +void XDp_TxGetGuid(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, + u32 *Guid); + +/* xdp_selftest.c: Self test function. */ +u32 XDp_SelfTest(XDp *InstancePtr); + +/* xdp_spm.c: Stream policy maker functions. */ +void XDp_TxCfgMsaRecalculate(XDp *InstancePtr, u8 Stream); +void XDp_TxCfgMsaUseStandardVideoMode(XDp *InstancePtr, u8 Stream, + XVidC_VideoMode VideoMode); +void XDp_TxCfgMsaUseEdidPreferredTiming(XDp *InstancePtr, u8 Stream, + u8 *Edid); +void XDp_TxCfgMsaUseCustom(XDp *InstancePtr, u8 Stream, + XDp_TxMainStreamAttributes *MsaConfigCustom, u8 Recalculate); +void XDp_TxCfgMsaSetBpc(XDp *InstancePtr, u8 Stream, u8 BitsPerColor); +void XDp_TxCfgMsaEnSynchClkMode(XDp *InstancePtr, u8 Stream, u8 Enable); +void XDp_TxSetVideoMode(XDp *InstancePtr, u8 Stream); +void XDp_TxClearMsaValues(XDp *InstancePtr, u8 Stream); +void XDp_TxSetMsaValues(XDp *InstancePtr, u8 Stream); +void XDp_RxSetUserPixelWidth(XDp *InstancePtr, u8 UserPixelWidth); + /******************* Macros (Inline Functions) Definitions ********************/ #define XDP_TX 0 @@ -230,11 +963,42 @@ XDp_Config *XDp_LookupConfig(u16 DeviceId); /******************************* Compatibility ********************************/ -#define XDptx_LookupConfig XDp_LookupConfig -#define XDptx_Config XDp_Config -#define XDptx_TimerHandler XDp_TimerHandler +#define XDptx_ReadReg XDp_ReadReg +#define XDprx_ReadReg XDp_ReadReg +#define XDptx_WriteReg XDp_WriteReg +#define XDprx_WriteReg XDp_WriteReg +#define XDptx_Config XDp_Config +#define XDprx_Config XDp_Config +#define XDptx_TimerHandler XDp_TimerHandler +#define XDprx_TimerHandler XDp_TimerHandler +#define XDptx_HpdEventHandler XDp_IntrHandler +#define XDptx_HpdPulseHandler XDp_IntrHandler +#define XDprx_IntrHandler XDp_IntrHandler -#include "xdprx.h" -#include "xdptx.h" +#define XDptx_LookupConfig XDp_LookupConfig +#define XDprx_LookupConfig XDp_LookupConfig +#define XDptx_CfgInitialize XDp_CfgInitialize +#define XDprx_CfgInitialize XDp_CfgInitialize +#define XDptx_InitializeTx XDp_Initialize +#define XDprx_InitializeRx XDp_Initialize +#define XDptx_WaitUs XDp_WaitUs +#define XDprx_WaitUs XDp_WaitUs +#define XDptx_SetUserTimerHandler XDp_SetUserTimerHandler +#define XDprx_SetUserTimerHandler XDp_SetUserTimerHandler +#define XDptx_SelfTest XDp_SelfTest +#define XDprx_SelfTest XDp_SelfTest +#define XDptx_HpdInterruptHandler XDp_InterruptHandler +#define XDprx_InterruptHandler XDp_InterruptHandler + +#define XDptx_ XDp_Tx +#define XDprx_ XDp_Rx +#define XDptx XDp +#define XDprx XDp + +#define XDPTX_DPCD_ XDP_DPCD_ +#define XDPTX_ XDP_TX_ +#define XDPRX_ XDP_RX_ +#define XDPTX XDP_TX +#define XDPRX XDP_RX #endif /* XDP_H_ */ diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdptx_edid.c b/XilinxProcessorIPLib/drivers/dp/src/xdp_edid.c similarity index 85% rename from XilinxProcessorIPLib/drivers/dp/src/xdptx_edid.c rename to XilinxProcessorIPLib/drivers/dp/src/xdp_edid.c index ec2f23d5..67ebe81a 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdptx_edid.c +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp_edid.c @@ -1,6 +1,6 @@ /******************************************************************************* * - * Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,10 +32,11 @@ /******************************************************************************/ /** * - * @file xdptx_edid.c + * @file xdp_edid.c * * This file contains functions related to accessing the Extended Display - * Identification Data (EDID) of a specified sink using the XDptx driver. + * Identification Data (EDID) of a specified sink using the XDp driver operating + * in TX mode. * * @note None. * @@ -44,15 +45,14 @@ * * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- - * 3.0 als 11/04/14 Initial release. + * 1.0 als 01/20/15 Initial release. * * *******************************************************************************/ /******************************* Include Files ********************************/ -#include "xdptx.h" -#include "xstatus.h" +#include "xdp.h" /**************************** Function Definitions ****************************/ @@ -61,7 +61,7 @@ * This function retrieves an immediately connected RX device's Extended Display * Identification Data (EDID) structure. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Edid is a pointer to the Edid buffer to save to. * * @return @@ -74,7 +74,7 @@ * @note None. * *******************************************************************************/ -u32 XDptx_GetEdid(XDptx *InstancePtr, u8 *Edid) +u32 XDp_TxGetEdid(XDp *InstancePtr, u8 *Edid) { u32 Status; @@ -84,7 +84,7 @@ u32 XDptx_GetEdid(XDptx *InstancePtr, u8 *Edid) Xil_AssertNonvoid(Edid != NULL); /* Retrieve the base EDID block = EDID block #0. */ - Status = XDptx_GetEdidBlock(InstancePtr, Edid, 0); + Status = XDp_TxGetEdidBlock(InstancePtr, Edid, 0); return Status; } @@ -94,7 +94,7 @@ u32 XDptx_GetEdid(XDptx *InstancePtr, u8 *Edid) * This function retrieves a remote RX device's Extended Display Identification * Data (EDID) structure. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkCountTotal is the number of DisplayPort links from the * DisplayPort source to the target DisplayPort device. * @param RelativeAddress is the relative address from the DisplayPort @@ -111,7 +111,7 @@ u32 XDptx_GetEdid(XDptx *InstancePtr, u8 *Edid) * @note None. * *******************************************************************************/ -u32 XDptx_GetRemoteEdid(XDptx *InstancePtr, u8 LinkCountTotal, +u32 XDp_TxGetRemoteEdid(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 *Edid) { u32 Status; @@ -124,7 +124,7 @@ u32 XDptx_GetRemoteEdid(XDptx *InstancePtr, u8 LinkCountTotal, Xil_AssertNonvoid(Edid != NULL); /* Retrieve the base EDID block = EDID block #0. */ - Status = XDptx_GetRemoteEdidBlock(InstancePtr, Edid, 0, LinkCountTotal, + Status = XDp_TxGetRemoteEdidBlock(InstancePtr, Edid, 0, LinkCountTotal, RelativeAddress); return Status; @@ -136,7 +136,7 @@ u32 XDptx_GetRemoteEdid(XDptx *InstancePtr, u8 LinkCountTotal, * Data (EDID) block given the block number. A block number of 0 represents the * base EDID and subsequent block numbers represent EDID extension blocks. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Data is a pointer to the data buffer to save the block data to. * @param BlockNum is the EDID block number to retrieve. * @@ -151,17 +151,17 @@ u32 XDptx_GetRemoteEdid(XDptx *InstancePtr, u8 LinkCountTotal, * @note None. * *******************************************************************************/ -u32 XDptx_GetEdidBlock(XDptx *InstancePtr, u8 *Data, u8 BlockNum) +u32 XDp_TxGetEdidBlock(XDp *InstancePtr, u8 *Data, u8 BlockNum) { u32 Status; u16 Offset; /* Calculate the I2C offset for the specified EDID block. */ - Offset = BlockNum * XDPTX_EDID_BLOCK_SIZE; + Offset = BlockNum * XDP_EDID_BLOCK_SIZE; /* Issue the I2C read for the specified EDID block. */ - Status = XDptx_IicRead(InstancePtr, XDPTX_EDID_ADDR, Offset, - XDPTX_EDID_BLOCK_SIZE, Data); + Status = XDp_TxIicRead(InstancePtr, XDP_EDID_ADDR, Offset, + XDP_EDID_BLOCK_SIZE, Data); return Status; } @@ -172,7 +172,7 @@ u32 XDptx_GetEdidBlock(XDptx *InstancePtr, u8 *Data, u8 BlockNum) * Data (EDID) block given the block number. A block number of 0 represents the * base EDID and subsequent block numbers represent EDID extension blocks. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Data is a pointer to the data buffer to save the block data to. * @param BlockNum is the EDID block number to retrieve. * @param LinkCountTotal is the total DisplayPort links connecting the @@ -191,18 +191,18 @@ u32 XDptx_GetEdidBlock(XDptx *InstancePtr, u8 *Data, u8 BlockNum) * @note None. * *******************************************************************************/ -u32 XDptx_GetRemoteEdidBlock(XDptx *InstancePtr, u8 *Data, u8 BlockNum, +u32 XDp_TxGetRemoteEdidBlock(XDp *InstancePtr, u8 *Data, u8 BlockNum, u8 LinkCountTotal, u8 *RelativeAddress) { u32 Status; u16 Offset; /* Calculate the I2C offset for the specified EDID block. */ - Offset = BlockNum * XDPTX_EDID_BLOCK_SIZE; + Offset = BlockNum * XDP_EDID_BLOCK_SIZE; /* Issue the I2C read for the specified EDID block. */ - Status = XDptx_RemoteIicRead(InstancePtr, LinkCountTotal, - RelativeAddress, XDPTX_EDID_ADDR, Offset, XDPTX_EDID_BLOCK_SIZE, + Status = XDp_TxRemoteIicRead(InstancePtr, LinkCountTotal, + RelativeAddress, XDP_EDID_ADDR, Offset, XDP_EDID_BLOCK_SIZE, Data); return Status; @@ -213,7 +213,7 @@ u32 XDptx_GetRemoteEdidBlock(XDptx *InstancePtr, u8 *Data, u8 BlockNum, * Search for and retrieve a downstream DisplayPort device's Extended Display * Identification Data (EDID) extension block of type DisplayID. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Data is a pointer to the data buffer to save the DisplayID to. * @param LinkCountTotal is the total DisplayPort links connecting the * DisplayPort TX to the targeted downstream device. @@ -231,7 +231,7 @@ u32 XDptx_GetRemoteEdidBlock(XDptx *InstancePtr, u8 *Data, u8 BlockNum, * @note None. * *******************************************************************************/ -u32 XDptx_GetRemoteEdidDispIdExt(XDptx *InstancePtr, u8 *Data, +u32 XDp_TxGetRemoteEdidDispIdExt(XDp *InstancePtr, u8 *Data, u8 LinkCountTotal, u8 *RelativeAddress) { u32 Status; @@ -239,22 +239,22 @@ u32 XDptx_GetRemoteEdidDispIdExt(XDptx *InstancePtr, u8 *Data, u8 ExtIndex; /* Get the base EDID block. */ - Status = XDptx_GetRemoteEdid(InstancePtr, LinkCountTotal, + Status = XDp_TxGetRemoteEdid(InstancePtr, LinkCountTotal, RelativeAddress, Data); if (Status != XST_SUCCESS) { return Status; } - NumExt = Data[XDPTX_EDID_EXT_BLOCK_COUNT]; + NumExt = Data[XDP_EDID_EXT_BLOCK_COUNT]; for (ExtIndex = 0; ExtIndex < NumExt; ExtIndex++) { /* Get an EDID extension block. */ - Status = XDptx_GetRemoteEdidBlock(InstancePtr, Data, + Status = XDp_TxGetRemoteEdidBlock(InstancePtr, Data, ExtIndex + 1, LinkCountTotal, RelativeAddress); if (Status != XST_SUCCESS) { return Status; } - if (XDptx_IsEdidExtBlockDispId(Data)) { + if (XDp_TxIsEdidExtBlockDispId(Data)) { /* The current extension block is of type DisplayID. */ return XST_SUCCESS; } @@ -286,31 +286,31 @@ u32 XDptx_GetRemoteEdidDispIdExt(XDptx *InstancePtr, u8 *Data, * section data block. * *******************************************************************************/ -u32 XDptx_GetDispIdDataBlock(u8 *DisplayIdRaw, u8 SectionTag, u8 **DataBlockPtr) +u32 XDp_TxGetDispIdDataBlock(u8 *DisplayIdRaw, u8 SectionTag, u8 **DataBlockPtr) { u8 Index; - u8 DispIdSize = DisplayIdRaw[XDPTX_DISPID_SIZE]; + u8 DispIdSize = DisplayIdRaw[XDP_TX_DISPID_SIZE]; u8 *DataBlock; /* Search for a section data block matching the specified tag. */ - for (Index = XDPTX_DISPID_PAYLOAD_START; Index < DispIdSize; Index++) { + for (Index = XDP_TX_DISPID_PAYLOAD_START; Index < DispIdSize; Index++) { DataBlock = &DisplayIdRaw[Index]; /* Check if the tag mataches the current section data block. */ - if (DataBlock[XDPTX_DISPID_DB_SEC_TAG] == SectionTag) { + if (DataBlock[XDP_TX_DISPID_DB_SEC_TAG] == SectionTag) { *DataBlockPtr = DataBlock; return XST_SUCCESS; } - if (DataBlock[XDPTX_DISPID_DB_SEC_SIZE] == 0) { + if (DataBlock[XDP_TX_DISPID_DB_SEC_SIZE] == 0) { /* End of valid section data blocks. */ break; } else { /* Increment the search index to skip the remaining * bytes of the current section data block. */ - Index += (XDPTX_DISPID_DB_SEC_SIZE + - DataBlock[XDPTX_DISPID_DB_SEC_SIZE]); + Index += (XDP_TX_DISPID_DB_SEC_SIZE + + DataBlock[XDP_TX_DISPID_DB_SEC_SIZE]); } } @@ -327,7 +327,7 @@ u32 XDptx_GetDispIdDataBlock(u8 *DisplayIdRaw, u8 SectionTag, u8 **DataBlockPtr) * DisplayID structure. The DisplayID structure is part of the Extended Display * Identification Data (EDID) in the form of an extension block. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param EdidExt is a pointer to the data area that will be filled by the * retrieved DisplayID extension block. * @param LinkCountTotal is the total DisplayPort links connecting the @@ -350,14 +350,14 @@ u32 XDptx_GetDispIdDataBlock(u8 *DisplayIdRaw, u8 SectionTag, u8 **DataBlockPtr) * EdidExt entry representing the TDT section data block. * *******************************************************************************/ -u32 XDptx_GetRemoteTiledDisplayDb(XDptx *InstancePtr, u8 *EdidExt, +u32 XDp_TxGetRemoteTiledDisplayDb(XDp *InstancePtr, u8 *EdidExt, u8 LinkCountTotal, u8 *RelativeAddress, u8 **DataBlockPtr) { u32 Status; u8 *EdidExtDispId; /* Obtain a DisplayID EDID extension block. */ - Status = XDptx_GetRemoteEdidDispIdExt(InstancePtr, EdidExt, + Status = XDp_TxGetRemoteEdidDispIdExt(InstancePtr, EdidExt, LinkCountTotal, RelativeAddress); if (Status != XST_SUCCESS) { /* The sink does not have a DisplayID EDID extension block. */ @@ -369,7 +369,7 @@ u32 XDptx_GetRemoteTiledDisplayDb(XDptx *InstancePtr, u8 *EdidExt, /* Obtain the tiled display topology block data from the DisplayId EDID * extension block. */ - Status = XDptx_GetDispIdDataBlock(EdidExtDispId, XDPTX_DISPID_TDT_TAG, + Status = XDp_TxGetDispIdDataBlock(EdidExtDispId, XDP_TX_DISPID_TDT_TAG, DataBlockPtr); if (Status != XST_SUCCESS) { /* The sink does not possess a DisplayID EDID data block with diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdp_hw.h b/XilinxProcessorIPLib/drivers/dp/src/xdp_hw.h new file mode 100644 index 00000000..9b9d6cfc --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp_hw.h @@ -0,0 +1,2448 @@ +/******************************************************************************* + * + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdp_hw.h + * + * This header file contains the identifiers and low-level driver functions (or + * macros) that can be used to access the device. High-level driver functions + * are defined in xdp.h. + * + * @note None. + * + *
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   als  01/20/15 Initial release.
+ * 
+ * +*******************************************************************************/ + +#ifndef XDP_HW_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XDP_HW_H_ + +/***************************** Include Files **********************************/ + +#include "xil_io.h" + +/************************** Constant Definitions ******************************/ + +/******************************************************************************/ +/** + * Address mapping for the DisplayPort core in TX mode. + * +*******************************************************************************/ +/** @name DPTX core registers: Link configuration field. + * @{ + */ +#define XDP_TX_LINK_BW_SET 0x0000 /**< Set main link bandwidth + setting. */ +#define XDP_TX_LANE_COUNT_SET 0x0004 /**< Set lane count setting. */ +#define XDP_TX_ENHANCED_FRAME_EN 0x0008 /**< Enable enhanced framing + symbol sequence. */ +#define XDP_TX_TRAINING_PATTERN_SET 0x000C /**< Set the link training + pattern. */ +#define XDP_TX_LINK_QUAL_PATTERN_SET 0x0010 /**< Transmit the link quality + pattern. */ +#define XDP_TX_SCRAMBLING_DISABLE 0x0014 /**< Disable scrambler and + transmit all symbols. */ +#define XDP_TX_DOWNSPREAD_CTRL 0x0018 /**< Enable a 0.5% spreading of + the clock. */ +#define XDP_TX_SOFT_RESET 0x001C /**< Software reset. */ +/* @} */ + +/** @name DPTX core registers: Core enables. + * @{ + */ +#define XDP_TX_ENABLE 0x0080 /**< Enable the basic operations + of the DisplayPort TX + core or output stuffing + symbols if disabled. */ +#define XDP_TX_ENABLE_MAIN_STREAM 0x0084 /**< Enable transmission of main + link video info. */ +#define XDP_TX_ENABLE_SEC_STREAM 0x0088 /**< Enable the transmission of + secondary link info. */ +#define XDP_TX_FORCE_SCRAMBLER_RESET 0x00C0 /**< Force a scrambler reset. */ +#define XDP_TX_MST_CONFIG 0x00D0 /**< Enable MST. */ +/* @} */ + +/** @name DPTX core registers: Core ID. + * @{ + */ +#define XDP_TX_VERSION 0x00F8 /**< Version and revision of the + DisplayPort core. */ +#define XDP_TX_CORE_ID 0x00FC /**< DisplayPort protocol + version and revision. */ +/* @} */ + +/** @name DPTX core registers: AUX channel interface. + * @{ + */ +#define XDP_TX_AUX_CMD 0x0100 /**< Initiates AUX commands. */ +#define XDP_TX_AUX_WRITE_FIFO 0x0104 /**< Write data for the current + AUX command. */ +#define XDP_TX_AUX_ADDRESS 0x0108 /**< Specifies the address of + current AUX command. */ +#define XDP_TX_AUX_CLK_DIVIDER 0x010C /**< Clock divider value for + generating the internal + 1MHz clock. */ +#define XDP_TX_USER_FIFO_OVERFLOW 0x0110 /**< Indicates an overflow in + user FIFO. */ +#define XDP_TX_INTERRUPT_SIG_STATE 0x0130 /**< The raw signal values for + interupt events. */ +#define XDP_TX_AUX_REPLY_DATA 0x0134 /**< Reply data received during + the AUX reply. */ +#define XDP_TX_AUX_REPLY_CODE 0x0138 /**< Reply code received from + the most recent AUX + command. */ +#define XDP_TX_AUX_REPLY_COUNT 0x013C /**< Number of reply + transactions receieved + over AUX. */ +#define XDP_TX_INTERRUPT_STATUS 0x0140 /**< Status for interrupt + events. */ +#define XDP_TX_INTERRUPT_MASK 0x0144 /**< Masks the specified + interrupt sources. */ +#define XDP_TX_REPLY_DATA_COUNT 0x0148 /**< Total number of data bytes + actually received during + a transaction. */ +#define XDP_TX_REPLY_STATUS 0x014C /**< Reply status of most recent + AUX transaction. */ +#define XDP_TX_HPD_DURATION 0x0150 /**< Duration of the HPD pulse + in microseconds. */ +/* @} */ + +/** @name DPTX core registers: Main stream attributes for SST / MST STREAM1. + * @{ + */ +#define XDP_TX_STREAM1_MSA_START 0x0180 /**< Start of the MSA registers + for stream 1. */ +#define XDP_TX_MAIN_STREAM_HTOTAL 0x0180 /**< Total number of clocks in + the horizontal framing + period. */ +#define XDP_TX_MAIN_STREAM_VTOTAL 0x0184 /**< Total number of lines in + the video frame. */ +#define XDP_TX_MAIN_STREAM_POLARITY 0x0188 /**< Polarity for the video + sync signals. */ +#define XDP_TX_MAIN_STREAM_HSWIDTH 0x018C /**< Width of the horizontal + sync pulse. */ +#define XDP_TX_MAIN_STREAM_VSWIDTH 0x0190 /**< Width of the vertical sync + pulse. */ +#define XDP_TX_MAIN_STREAM_HRES 0x0194 /**< Number of active pixels per + line (the horizontal + resolution). */ +#define XDP_TX_MAIN_STREAM_VRES 0x0198 /**< Number of active lines (the + vertical resolution). */ +#define XDP_TX_MAIN_STREAM_HSTART 0x019C /**< Number of clocks between + the leading edge of the + horizontal sync and the + start of active data. */ +#define XDP_TX_MAIN_STREAM_VSTART 0x01A0 /**< Number of lines between the + leading edge of the + vertical sync and the + first line of active + data. */ +#define XDP_TX_MAIN_STREAM_MISC0 0x01A4 /**< Miscellaneous stream + attributes. */ +#define XDP_TX_MAIN_STREAM_MISC1 0x01A8 /**< Miscellaneous stream + attributes. */ +#define XDP_TX_M_VID 0x01AC /**< M value for the video + stream as computed by + the source core in + asynchronous clock + mode. Must be written + in synchronous mode. */ +#define XDP_TX_TU_SIZE 0x01B0 /**< Size of a transfer unit in + the framing logic. */ +#define XDP_TX_N_VID 0x01B4 /**< N value for the video + stream as computed by + the source core in + asynchronous clock mode. + Must be written in + synchronous mode. */ +#define XDP_TX_USER_PIXEL_WIDTH 0x01B8 /**< Selects the width of the + user data input port. */ +#define XDP_TX_USER_DATA_COUNT_PER_LANE 0x01BC /**< Used to translate the + number of pixels per + line to the native + internal 16-bit + datapath. */ +#define XDP_TX_MAIN_STREAM_INTERLACED 0x01C0 /**< Video is interlaced. */ +#define XDP_TX_MIN_BYTES_PER_TU 0x01C4 /**< The minimum number of bytes + per transfer unit. */ +#define XDP_TX_FRAC_BYTES_PER_TU 0x01C8 /**< The fractional component + when calculated the + XDP_TX_MIN_BYTES_PER_TU + register value. */ +#define XDP_TX_INIT_WAIT 0x01CC /**< Number of initial wait + cycles at the start of a + new line by the framing + logic, allowing enough + data to be buffered in + the input FIFO. */ +#define XDP_TX_STREAM1 0x01D0 /**< Average stream symbol + timeslots per MTP + config. */ +#define XDP_TX_STREAM2 0x01D4 /**< Average stream symbol + timeslots per MTP + config. */ +#define XDP_TX_STREAM3 0x01D8 /**< Average stream symbol + timeslots per MTP + config. */ +#define XDP_TX_STREAM4 0x01DC /**< Average stream symbol + timeslots per MTP + config. */ +/* @} */ + +/** @name DPTX core registers: PHY configuration status. + * @{ + */ +#define XDP_TX_PHY_CONFIG 0x0200 /**< Transceiver PHY reset and + configuration. */ +#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_0 0x0220 /**< Controls the differential + voltage swing. */ +#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_1 0x0224 /**< Controls the differential + voltage swing. */ +#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_2 0x0228 /**< Controls the differential + voltage swing. */ +#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_3 0x022C /**< Controls the differential + voltage swing. */ +#define XDP_TX_PHY_TRANSMIT_PRBS7 0x0230 /**< Enable pseudo random bit + sequence 7 pattern + transmission for link + quality assessment. */ +#define XDP_TX_PHY_CLOCK_SELECT 0x0234 /**< Instructs the PHY PLL to + generate the proper + clock frequency for the + required link rate. */ +#define XDP_TX_PHY_POWER_DOWN 0x0238 /**< Controls PHY power down. */ +#define XDP_TX_PHY_PRECURSOR_LANE_0 0x023C /**< Controls the pre-cursor + level. */ +#define XDP_TX_PHY_PRECURSOR_LANE_1 0x0240 /**< Controls the pre-cursor + level. */ +#define XDP_TX_PHY_PRECURSOR_LANE_2 0x0244 /**< Controls the pre-cursor + level. */ +#define XDP_TX_PHY_PRECURSOR_LANE_3 0x0248 /**< Controls the pre-cursor + level. */ +#define XDP_TX_PHY_POSTCURSOR_LANE_0 0x024C /**< Controls the post-cursor + level. */ +#define XDP_TX_PHY_POSTCURSOR_LANE_1 0x0250 /**< Controls the post-cursor + level. */ +#define XDP_TX_PHY_POSTCURSOR_LANE_2 0x0254 /**< Controls the post-cursor + level. */ +#define XDP_TX_PHY_POSTCURSOR_LANE_3 0x0258 /**< Controls the post-cursor + level. */ +#define XDP_TX_PHY_STATUS 0x0280 /**< Current PHY status. */ +#define XDP_TX_GT_DRP_COMMAND 0x02A0 /**< Provides acces to the GT + DRP ports. */ +#define XDP_TX_GT_DRP_READ_DATA 0x02A4 /**< Provides access to GT DRP + read data. */ +#define XDP_TX_GT_DRP_CHANNEL_STATUS 0x02A8 /**< Provides access to GT DRP + channel status. */ +/* @} */ + +/** @name DPTX core registers: DisplayPort audio. + * @{ + */ +#define XDP_TX_AUDIO_CONTROL 0x0300 /**< Enables audio stream + packets in main link and + buffer control. */ +#define XDP_TX_AUDIO_CHANNELS 0x0304 /**< Used to input active + channel count. */ +#define XDP_TX_AUDIO_INFO_DATA(NUM) (0x0308 + 4 * (NUM - 1)) /**< Word + formatted as per CEA + 861-C info frame. */ +#define XDP_TX_AUDIO_MAUD 0x0328 /**< M value of audio stream + as computed by the + DisplayPort TX core when + audio and link clocks + are synchronous. */ +#define XDP_TX_AUDIO_NAUD 0x032C /**< N value of audio stream + as computed by the + DisplayPort TX core when + audio and link clocks + are synchronous. */ +#define XDP_TX_AUDIO_EXT_DATA(NUM) (0x0330 + 4 * (NUM - 1)) /**< Word + formatted as per + extension packet. */ +/* @} */ + +/** @name DPTX core registers: Main stream attributes for MST STREAM2, 3, and 4. + * @{ + */ +#define XDP_TX_STREAM2_MSA_START 0x0500 /**< Start of the MSA registers + for stream 2. */ +#define XDP_TX_STREAM2_MSA_START_OFFSET (XDP_TX_STREAM2_MSA_START - \ + XDP_TX_STREAM1_MSA_START) /**< The MSA registers for + stream 2 are at an + offset from the + corresponding registers + of stream 1. */ +#define XDP_TX_STREAM3_MSA_START 0x0550 /**< Start of the MSA registers + for stream 3. */ +#define XDP_TX_STREAM3_MSA_START_OFFSET (XDP_TX_STREAM3_MSA_START - \ + XDP_TX_STREAM1_MSA_START) /**< The MSA registers for + stream 3 are at an + offset from the + corresponding registers + of stream 1. */ +#define XDP_TX_STREAM4_MSA_START 0x05A0 /**< Start of the MSA registers + for stream 4. */ +#define XDP_TX_STREAM4_MSA_START_OFFSET (XDP_TX_STREAM4_MSA_START - \ + XDP_TX_STREAM1_MSA_START) /**< The MSA registers for + stream 4 are at an + offset from the + corresponding registers + of stream 1. */ +/* @} */ + +#define XDP_TX_VC_PAYLOAD_BUFFER_ADDR 0x0800 /**< Virtual channel payload + table (0xFF bytes). */ + +/******************************************************************************/ + +/** @name DPTX core masks, shifts, and register values. + * @{ + */ +/* 0x000: LINK_BW_SET */ +#define XDP_TX_LINK_BW_SET_162GBPS 0x06 /**< 1.62 Gbps link rate. */ +#define XDP_TX_LINK_BW_SET_270GBPS 0x0A /**< 2.70 Gbps link rate. */ +#define XDP_TX_LINK_BW_SET_540GBPS 0x14 /**< 5.40 Gbps link rate. */ +/* 0x001: LANE_COUNT_SET */ +#define XDP_TX_LANE_COUNT_SET_1 0x01 /**< Lane count of 1. */ +#define XDP_TX_LANE_COUNT_SET_2 0x02 /**< Lane count of 2. */ +#define XDP_TX_LANE_COUNT_SET_4 0x04 /**< Lane count of 4. */ +/* 0x00C: TRAINING_PATTERN_SET */ +#define XDP_TX_TRAINING_PATTERN_SET_OFF 0x0 /**< Training off. */ +#define XDP_TX_TRAINING_PATTERN_SET_TP1 0x1 /**< Training pattern 1 used for + clock recovery. */ +#define XDP_TX_TRAINING_PATTERN_SET_TP2 0x2 /**< Training pattern 2 used for + channel equalization. */ +#define XDP_TX_TRAINING_PATTERN_SET_TP3 0x3 /**< Training pattern 3 used for + channel equalization for + cores with DP v1.2. */ +/* 0x010: LINK_QUAL_PATTERN_SET */ +#define XDP_TX_LINK_QUAL_PATTERN_SET_OFF 0x0 /**< Link quality test pattern + not transmitted. */ +#define XDP_TX_LINK_QUAL_PATTERN_SET_D102_TEST \ + 0x1 /**< D10.2 unscrambled test + pattern transmitted. */ +#define XDP_TX_LINK_QUAL_PATTERN_SET_SER_MES \ + 0x2 /**< Symbol error rate + measurement pattern + transmitted. */ +#define XDP_TX_LINK_QUAL_PATTERN_SET_PRBS7 \ + 0x3 /**< Pseudo random bit sequence + 7 transmitted. */ +/* 0x01C: SOFTWARE_RESET */ +#define XDP_TX_SOFT_RESET_VIDEO_STREAM1_MASK \ + 0x00000001 /**< Reset video logic. */ +#define XDP_TX_SOFT_RESET_VIDEO_STREAM2_MASK \ + 0x00000002 /**< Reset video logic. */ +#define XDP_TX_SOFT_RESET_VIDEO_STREAM3_MASK \ + 0x00000004 /**< Reset video logic. */ +#define XDP_TX_SOFT_RESET_VIDEO_STREAM4_MASK \ + 0x00000008 /**< Reset video logic. */ +#define XDP_TX_SOFT_RESET_AUX_MASK \ + 0x00000080 /**< Reset AUX logic. */ +#define XDP_TX_SOFT_RESET_VIDEO_STREAM_ALL_MASK \ + 0x0000000F /**< Reset video logic for all + streams. */ +/* 0x0D0: TX_MST_CONFIG */ +#define XDP_TX_MST_CONFIG_MST_EN_MASK \ + 0x00000001 /**< Enable MST. */ +#define XDP_TX_MST_CONFIG_VCP_UPDATED_MASK \ + 0x00000002 /**< The VC payload has been + updated in the sink. */ +/* 0x0F8: VERSION */ +#define XDP_TX_VERSION_INTER_REV_MASK \ + 0x0000000F /**< Internal revision. */ +#define XDP_TX_VERSION_CORE_PATCH_MASK \ + 0x00000030 /**< Core patch details. */ +#define XDP_TX_VERSION_CORE_PATCH_SHIFT \ + 8 /**< Shift bits for core patch + details. */ +#define XDP_TX_VERSION_CORE_VER_REV_MASK \ + 0x000000C0 /**< Core version revision. */ +#define XDP_TX_VERSION_CORE_VER_REV_SHIFT \ + 12 /**< Shift bits for core version + revision. */ +#define XDP_TX_VERSION_CORE_VER_MNR_MASK \ + 0x00000F00 /**< Core minor version. */ +#define XDP_TX_VERSION_CORE_VER_MNR_SHIFT \ + 16 /**< Shift bits for core minor + version. */ +#define XDP_TX_VERSION_CORE_VER_MJR_MASK \ + 0x0000F000 /**< Core major version. */ +#define XDP_TX_VERSION_CORE_VER_MJR_SHIFT \ + 24 /**< Shift bits for core major + version. */ +/* 0x0FC: CORE_ID */ +#define XDP_TX_CORE_ID_TYPE_MASK 0x0000000F /**< Core type. */ +#define XDP_TX_CORE_ID_TYPE_TX 0x0 /**< Core is a transmitter. */ +#define XDP_TX_CORE_ID_TYPE_RX 0x1 /**< Core is a receiver. */ +#define XDP_TX_CORE_ID_DP_REV_MASK \ + 0x000000F0 /**< DisplayPort protocol + revision. */ +#define XDP_TX_CORE_ID_DP_REV_SHIFT \ + 8 /**< Shift bits for DisplayPort + protocol revision. */ +#define XDP_TX_CORE_ID_DP_MNR_VER_MASK \ + 0x00000F00 /**< DisplayPort protocol minor + version. */ +#define XDP_TX_CORE_ID_DP_MNR_VER_SHIFT \ + 16 /**< Shift bits for DisplayPort + protocol major + version. */ +#define XDP_TX_CORE_ID_DP_MJR_VER_MASK \ + 0x0000F000 /**< DisplayPort protocol major + version. */ +#define XDP_TX_CORE_ID_DP_MJR_VER_SHIFT \ + 24 /**< Shift bits for DisplayPort + protocol major + version. */ +/* 0x100: AUX_CMD */ +#define XDP_TX_AUX_CMD_NBYTES_TRANSFER_MASK \ + 0x0000000F /**< Number of bytes to transfer + with the current AUX + command. */ +#define XDP_TX_AUX_CMD_MASK 0x00000F00 /**< AUX command. */ +#define XDP_TX_AUX_CMD_SHIFT 8 /**< Shift bits for command. */ +#define XDP_TX_AUX_CMD_I2C_WRITE 0x0 /**< I2C-over-AUX write + command. */ +#define XDP_TX_AUX_CMD_I2C_READ 0x1 /**< I2C-over-AUX read + command. */ +#define XDP_TX_AUX_CMD_I2C_WRITE_STATUS 0x2 /**< I2C-over-AUX write status + command. */ +#define XDP_TX_AUX_CMD_I2C_WRITE_MOT 0x4 /**< I2C-over-AUX write MOT + (middle-of-transaction) + command. */ +#define XDP_TX_AUX_CMD_I2C_READ_MOT 0x5 /**< I2C-over-AUX read MOT + (middle-of-transaction) + command. */ +#define XDP_TX_AUX_CMD_I2C_WRITE_STATUS_MOT \ + 0x6 /**< I2C-over-AUX write status + MOT (middle-of- + transaction) command. */ +#define XDP_TX_AUX_CMD_WRITE 0x8 /**< AUX write command. */ +#define XDP_TX_AUX_CMD_READ 0x9 /**< AUX read command. */ +#define XDP_TX_AUX_CMD_ADDR_ONLY_TRANSFER_EN \ + 0x00001000 /**< Address only transfer + enable (STOP will be + sent after command). */ +/* 0x10C: AUX_CLK_DIVIDER */ +#define XDP_TX_AUX_CLK_DIVIDER_VAL_MASK 0x00FF /**< Clock divider value. */ +#define XDP_TX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK \ + 0xFF00 /**< AUX (noise) signal width + filter. */ +#define XDP_TX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT \ + 8 /**< Shift bits for AUX signal + width filter. */ +/* 0x130: INTERRUPT_SIG_STATE */ +#define XDP_TX_INTERRUPT_SIG_STATE_HPD_STATE_MASK \ + 0x00000001 /**< Raw state of the HPD pin on + the DP connector. */ +#define XDP_TX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK \ + 0x00000002 /**< A request is currently + being sent. */ +#define XDP_TX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK \ + 0x00000004 /**< A reply is currently being + received. */ +#define XDP_TX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK \ + 0x00000008 /**< A reply timeout has + occurred. */ +/* 0x138: AUX_REPLY_CODE */ +#define XDP_TX_AUX_REPLY_CODE_ACK 0x0 /**< AUX command ACKed. */ +#define XDP_TX_AUX_REPLY_CODE_I2C_ACK 0x0 /**< I2C-over-AUX command + not ACKed. */ +#define XDP_TX_AUX_REPLY_CODE_NACK 0x1 /**< AUX command not ACKed. */ +#define XDP_TX_AUX_REPLY_CODE_DEFER 0x2 /**< AUX command deferred. */ +#define XDP_TX_AUX_REPLY_CODE_I2C_NACK 0x4 /**< I2C-over-AUX command not + ACKed. */ +#define XDP_TX_AUX_REPLY_CODE_I2C_DEFER 0x8 /**< I2C-over-AUX command + deferred. */ +/* 0x140: INTERRUPT_STATUS */ +#define XDP_TX_INTERRUPT_STATUS_HPD_IRQ_MASK \ + 0x00000001 /**< Detected an IRQ framed with + the proper timing on the + HPD signal. */ +#define XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK \ + 0x00000002 /**< Detected the presence of + the HPD signal. */ +#define XDP_TX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK \ + 0x00000004 /**< An AUX reply transaction + has been detected. */ +#define XDP_TX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK \ + 0x00000008 /**< A reply timeout has + occurred. */ +#define XDP_TX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK \ + 0x00000010 /**< A pulse on the HPD line was + detected. */ +#define XDP_TX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK \ + 0x00000020 /**< Extended packet has been + transmitted and the core + is ready to accept a new + packet. */ +/* 0x144: INTERRUPT_MASK */ +#define XDP_TX_INTERRUPT_MASK_HPD_IRQ_MASK \ + 0x00000001 /**< Mask HPD IRQ interrupt. */ +#define XDP_TX_INTERRUPT_MASK_HPD_EVENT_MASK \ + 0x00000002 /**< Mask HPD event + interrupt. */ +#define XDP_TX_INTERRUPT_MASK_REPLY_RECEIVED_MASK \ + 0x00000004 /**< Mask reply received + interrupt. */ +#define XDP_TX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK \ + 0x00000008 /**< Mask reply received + interrupt. */ +#define XDP_TX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK \ + 0x00000010 /**< Mask HPD pulse detected + interrupt. */ +#define XDP_TX_INTERRUPT_MASK_EXT_PKT_TXD_MASK \ + 0x00000020 /**< Mask extended packet + transmit interrupt. */ +/* 0x14C: REPLY_STATUS */ +#define XDP_TX_REPLY_STATUS_REPLY_RECEIVED_MASK \ + 0x00000001 /**< AUX transaction is complete + and a valid reply + transaction received. */ +#define XDP_TX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK \ + 0x00000002 /**< AUX reply is currently + being received. */ +#define XDP_TX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK \ + 0x00000004 /**< AUX request is currently + being transmitted. */ +#define XDP_TX_REPLY_STATUS_REPLY_ERROR_MASK \ + 0x00000008 /**< Detected an error in the + AUX reply of the most + recent transaction. */ +#define XDP_TX_REPLY_STATUS_REPLY_STATUS_STATE_MASK \ + 0x00000FF0 /**< Internal AUX reply state + machine status bits. */ +#define XDP_TX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT \ + 4 /**< Shift bits for the internal + AUX reply state machine + status. */ +/* 0x188, 0x508, 0x558, 0x5A8: MAIN_STREAM[1-4]_POLARITY */ +#define XDP_TX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK \ + 0x00000001 /**< Polarity of the horizontal + sync pulse. */ +#define XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK \ + 0x00000002 /**< Polarity of the vertical + sync pulse. */ +#define XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT \ + 1 /**< Shift bits for polarity of + the vertical sync + pulse. */ +/* 0x1A4, 0x524, 0x574, 0x5C4: MAIN_STREAM[1-4]_MISC0 */ +#define XDP_TX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK \ + 0x00000001 /**< Synchronous clock. */ +#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK \ + 0x00000006 /**< Component format. */ +#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT \ + 1 /**< Shift bits for component + format. */ +#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB \ + 0x0 /**< Stream's component format + is RGB. */ +#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 \ + 0x1 /**< Stream's component format + is YcbCr 4:2:2. */ +#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 \ + 0x2 /**< Stream's component format + is YcbCr 4:4:4. */ +#define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK \ + 0x00000008 /**< Dynamic range. */ +#define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT \ + 3 /**< Shift bits for dynamic + range. */ +#define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK \ + 0x00000010 /**< YCbCr colorimetry. */ +#define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT \ + 4 /**< Shift bits for YCbCr + colorimetry. */ +#define XDP_TX_MAIN_STREAMX_MISC0_BDC_MASK \ + 0x000000E0 /**< Bit depth per color + component (BDC). */ +#define XDP_TX_MAIN_STREAMX_MISC0_BDC_SHIFT \ + 5 /**< Shift bits for BDC.*/ +#define XDP_TX_MAIN_STREAMX_MISC0_BDC_6BPC \ + 0x0 /**< 6 bits per component.*/ +#define XDP_TX_MAIN_STREAMX_MISC0_BDC_8BPC \ + 0x1 /**< 8 bits per component.*/ +#define XDP_TX_MAIN_STREAMX_MISC0_BDC_10BPC \ + 0x2 /**< 10 bits per component.*/ +#define XDP_TX_MAIN_STREAMX_MISC0_BDC_12BPC \ + 0x3 /**< 12 bits per component.*/ +#define XDP_TX_MAIN_STREAMX_MISC0_BDC_16BPC \ + 0x4 /**< 16 bits per component.*/ +/* 0x1A8, 0x528, 0x578, 0x5C8: MAIN_STREAM[1-4]_MISC1 */ +#define XDP_TX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK \ + 0x00000001 /**< Interlaced vertical total + even. */ +#define XDP_TX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK \ + 0x00000006 /**< Stereo video attribute. */ +#define XDP_TX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT \ + 1 /**< Shift bits for stereo video + attribute. */ +/* 0x200: PHY_CONFIG */ +#define XDP_TX_PHY_CONFIG_PHY_RESET_ENABLE_MASK \ + 0x0000000 /**< Release reset. */ +#define XDP_TX_PHY_CONFIG_PHY_RESET_MASK \ + 0x0000001 /**< Hold the PHY in reset. */ +#define XDP_TX_PHY_CONFIG_GTTX_RESET_MASK \ + 0x0000002 /**< Hold GTTXRESET in reset. */ +#define XDP_TX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK \ + 0x0000100 /**< Hold TX_PHY_PMA reset. */ +#define XDP_TX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK \ + 0x0000200 /**< Hold TX_PHY_PCS reset. */ +#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK \ + 0x0000400 /**< Set TX_PHY_POLARITY. */ +#define XDP_TX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK \ + 0x0001000 /**< Set TX_PHY_PRBSFORCEERR. */ +#define XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK \ + 0x000E000 /**< Set TX_PHY_LOOPBACK. */ +#define XDP_TX_PHY_CONFIG_GT_ALL_RESET_MASK \ + 0x0000003 /**< Rest GT and PHY. */ +/* 0x234: PHY_CLOCK_SELECT */ +#define XDP_TX_PHY_CLOCK_SELECT_162GBPS 0x1 /**< 1.62 Gbps link. */ +#define XDP_TX_PHY_CLOCK_SELECT_270GBPS 0x3 /**< 2.70 Gbps link. */ +#define XDP_TX_PHY_CLOCK_SELECT_540GBPS 0x5 /**< 5.40 Gbps link. */ +/* 0x0220, 0x0224, 0x0228, 0x022C: XDP_TX_PHY_VOLTAGE_DIFF_LANE_[0-3] */ +#define XDP_TX_VS_LEVEL_0 0x2 /**< Voltage swing level 0. */ +#define XDP_TX_VS_LEVEL_1 0x5 /**< Voltage swing level 1. */ +#define XDP_TX_VS_LEVEL_2 0x8 /**< Voltage swing level 2. */ +#define XDP_TX_VS_LEVEL_3 0xF /**< Voltage swing level 3. */ +#define XDP_TX_VS_LEVEL_OFFSET 0x4 /**< Voltage swing compensation + offset used when there's + no redriver in display + path. */ +/* 0x024C, 0x0250, 0x0254, 0x0258: XDP_TX_PHY_POSTCURSOR_LANE_[0-3] */ +#define XDP_TX_PE_LEVEL_0 0x00 /**< Pre-emphasis level 0. */ +#define XDP_TX_PE_LEVEL_1 0x0E /**< Pre-emphasis level 1. */ +#define XDP_TX_PE_LEVEL_2 0x14 /**< Pre-emphasis level 2. */ +#define XDP_TX_PE_LEVEL_3 0x1B /**< Pre-emphasis level 3. */ +/* 0x280: PHY_STATUS */ +#define XDP_TX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK \ + 0x00000003 /**< Reset done for lanes + 0 and 1. */ +#define XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK \ + 0x0000000C /**< Reset done for lanes + 2 and 3. */ +#define XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT \ + 2 /**< Shift bits for reset done + for lanes 2 and 3. */ +#define XDP_TX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK \ + 0x00000010 /**< PLL locked for lanes + 0 and 1. */ +#define XDP_TX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK \ + 0x00000020 /**< PLL locked for lanes + 2 and 3. */ +#define XDP_TX_PHY_STATUS_PLL_FABRIC_LOCK_MASK \ + 0x00000040 /**< FPGA fabric clock PLL + locked. */ +#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK \ + 0x00030000 /**< TX buffer status lane 0. */ +#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT \ + 16 /**< Shift bits for TX buffer + status lane 0. */ +#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_0_MASK \ + 0x000C0000 /**< TX error on lane 0. */ +#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT \ + 18 /**< Shift bits for TX error on + lane 0. */ +#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK \ + 0x00300000 /**< TX buffer status lane 1. */ +#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT \ + 20 /**< Shift bits for TX buffer + status lane 1. */ +#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_1_MASK \ + 0x00C00000 /**< TX error on lane 1. */ +#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT \ + 22 /**< Shift bits for TX error on + lane 1. */ +#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK \ + 0x03000000 /**< TX buffer status lane 2. */ +#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT \ + 24 /**< Shift bits for TX buffer + status lane 2. */ +#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_2_MASK \ + 0x0C000000 /**< TX error on lane 2. */ +#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT \ + 26 /**< Shift bits for TX error on + lane 2. */ +#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK \ + 0x30000000 /**< TX buffer status lane 3. */ +#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT \ + 28 /**< Shift bits for TX buffer + status lane 3. */ +#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_3_MASK \ + 0xC0000000 /**< TX error on lane 3. */ +#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT \ + 30 /**< Shift bits for TX error on + lane 3. */ +#define XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK \ + 0x00000013 /**< Lanes 0 and 1 are ready. */ +#define XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK \ + 0x0000003F /**< All lanes are ready. */ +/* 0x2A0: XDP_TX_GT_DRP_COMMAND */ +#define XDP_TX_GT_DRP_COMMAND_DRP_ADDR_MASK \ + 0x000F /**< DRP address. */ +#define XDP_TX_GT_DRP_COMMAND_DRP_RW_CMD_MASK \ + 0x0080 /**< DRP read/write command + (Read=0, Write=1). */ +#define XDP_TX_GT_DRP_COMMAND_DRP_W_DATA_MASK \ + 0xFF00 /**< DRP write data. */ +#define XDP_TX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT \ + 16 /**< Shift bits for DRP write + data. */ +/* @} */ + +/******************************************************************************/ + +/******************************************************************************/ +/** + * Address mapping for the DisplayPort core in RX mode. + * +*******************************************************************************/ + +/** @name DPRX core registers: Receiver core configuration. + * @{ + */ +#define XDP_RX_LINK_ENABLE 0x000 /**< Enable the receiver + core. */ +#define XDP_RX_AUX_CLK_DIVIDER 0x004 /**< Clock divider value for + generating the internal + 1MHz clock. */ +#define XDP_RX_DTG_ENABLE 0x00C /**< Enables the display timing + generator (DTG). */ +#define XDP_RX_USER_PIXEL_WIDTH 0x010 /**< Selects the width of the + user data input port. */ +#define XDP_RX_INTERRUPT_MASK 0x014 /**< Masks the specified + interrupt sources for + stream 1. */ +#define XDP_RX_MISC_CTRL 0x018 /**< Miscellaneous control of + RX behavior. */ +#define XDP_RX_SOFT_RESET 0x01C /**< Software reset. */ +/* @} */ + +/** @name DPRX core registers: AUX channel status. + * @{ + */ +#define XDP_RX_AUX_REQ_IN_PROGRESS 0x020 /**< Indicates the receipt of an + AUX channel request. */ +#define XDP_RX_REQ_ERROR_COUNT 0x024 /**< Provides a running total of + errors detected on + inbound AUX channel + requests. */ +#define XDP_RX_REQ_COUNT 0x028 /**< Provides a running total of + the number of AUX + requests received. */ +#define XDP_RX_HPD_INTERRUPT 0x02C /**< Instructs the DisplayPort + RX core to assert an + interrupt to the TX + using the HPD signal. */ +#define XDP_RX_REQ_CLK_WIDTH 0x030 /**< Holds the half period of + the recovered AUX + clock. */ +#define XDP_RX_REQ_CMD 0x034 /**< Provides the most recent + AUX command received. */ +#define XDP_RX_REQ_ADDRESS 0x038 /**< Contains the address field + of the most recent AUX + request. */ +#define XDP_RX_REQ_LENGTH 0x03C /**< Contains length of the most + recent AUX request. */ +/* @} */ + +/** @name DPRX core registers: Interrupt registers. + * @{ + */ +#define XDP_RX_INTERRUPT_CAUSE 0x040 /**< Indicates the cause of + pending host interrupts + for stream 1, training, + payload allocation, and + for the AUX channel. */ +#define XDP_RX_INTERRUPT_MASK_1 0x044 /**< Masks the specified + interrupt sources for + streams 2, 3, 4. */ +#define XDP_RX_INTERRUPT_CAUSE_1 0x048 /**< Indicates the cause of a + pending host interrupts + for streams 2, 3, 4. */ +#define XDP_RX_HSYNC_WIDTH 0x050 /**< Controls the timing of the + active-high horizontal + sync pulse generated + by the display timing + generator (DTG). */ +#define XDP_RX_FAST_I2C_DIVIDER 0x060 /**< Fast I2C mode clock divider + value. */ +/* @} */ + +/** @name DPRX core registers: DPCD fields. + * @{ + */ +#define XDP_RX_LOCAL_EDID_VIDEO 0x084 /**< Indicates the presence of + EDID information for the + video stream. */ +#define XDP_RX_LOCAL_EDID_AUDIO 0x088 /**< Indicates the presence of + EDID information for the + audio stream. */ +#define XDP_RX_REMOTE_CMD 0x08C /**< Used for passing remote + information to the + DisplayPort TX. */ +#define XDP_RX_DEVICE_SERVICE_IRQ 0x090 /**< Indicates the DPCD + DEVICE_SERVICE_IRQ_ + VECTOR state. */ +#define XDP_RX_VIDEO_UNSUPPORTED 0x094 /**< DPCD register bit to inform + the DisplayPort TX that + video data is not + supported. */ +#define XDP_RX_AUDIO_UNSUPPORTED 0x098 /**< DPCD register bit to inform + the DisplayPort TX that + audio data is not + supported. */ +#define XDP_RX_OVER_LINK_BW_SET 0x09C /**< Used to override the main + link bandwidth setting + in the DPCD. */ +#define XDP_RX_OVER_LANE_COUNT_SET 0x0A0 /**< Used to override the lane + count setting in the + DPCD. */ +#define XDP_RX_OVER_TP_SET 0x0A4 /**< Used to override the link + training pattern in the + DPCD. */ +#define XDP_RX_OVER_TRAINING_LANE0_SET 0x0A8 /**< Used to override the + TRAINING_LANE0_SET + register in the DPCD. */ +#define XDP_RX_OVER_TRAINING_LANE1_SET 0x0AC /**< Used to override the + TRAINING_LANE1_SET + register in the DPCD. */ +#define XDP_RX_OVER_TRAINING_LANE2_SET 0x0B0 /**< Used to override the + TRAINING_LANE2_SET + register in the DPCD. */ +#define XDP_RX_OVER_TRAINING_LANE3_SET 0x0B4 /**< Used to override the + TRAINING_LANE3_SET + register in the DPCD. */ +#define XDP_RX_OVER_CTRL_DPCD 0x0B8 /**< Used to enable AXI/APB + write access to the DPCD + capability structure. */ +#define XDP_RX_OVER_DOWNSPREAD_CTRL 0x0BC /**< Used to override downspread + control in the DPCD. */ +#define XDP_RX_OVER_LINK_QUAL_LANE0_SET 0x0C0 /**< Used to override the + LINK_QUAL_LANE0_SET + register in the DPCD. */ +#define XDP_RX_OVER_LINK_QUAL_LANE1_SET 0x0C4 /**< Used to override the + LINK_QUAL_LANE1_SET + register in the DPCD. */ +#define XDP_RX_OVER_LINK_QUAL_LANE2_SET 0x0C8 /**< Used to override the + LINK_QUAL_LANE2_SET + register in the DPCD. */ +#define XDP_RX_OVER_LINK_QUAL_LANE3_SET 0x0CC /**< Used to override the + LINK_QUAL_LANE3_SET + register in the DPCD. */ +#define XDP_RX_MST_CAP 0x0D0 /**< Used to enable or disable + MST capability. */ +#define XDP_RX_SINK_COUNT 0x0D4 /**< The sink device count. */ +#define XDP_RX_GUID0 0x0E0 /**< Lower 4 bytes of the DPCD's + GUID field. */ +#define XDP_RX_GUID1 0x0E4 /**< Bytes 4 to 7 of the DPCD's + GUID field. */ +#define XDP_RX_GUID2 0x0E8 /**< Bytes 8 to 11 of the DPCD's + GUID field. */ +#define XDP_RX_GUID3 0x0EC /**< Upper 4 bytes of the DPCD's + GUID field. */ +#define XDP_RX_OVER_GUID 0x0F0 /**< Used to override the GUID + field in the DPCD with + what is stored in + XDP_RX_GUID[0-3]. */ +/* @} */ + +/** @name DPRX core registers: Core ID. + * @{ + */ +#define XDP_RX_VERSION 0x0F8 /**< Version and revision of the + DisplayPort core. */ +#define XDP_RX_CORE_ID 0x0FC /**< DisplayPort protocol + version and revision. */ +/* @} */ + +/** @name DPRX core registers: User video status. + * @{ + */ +#define XDP_RX_USER_FIFO_OVERFLOW 0x110 /**< Indicates an overflow in + user FIFO. */ +#define XDP_RX_USER_VSYNC_STATE 0x114 /**< Provides a mechanism for + the host processor to + monitor the state of the + video data path. */ +/* @} */ + +/** @name DPRX core registers: PHY configuration and status. + * @{ + */ +#define XDP_RX_PHY_CONFIG 0x200 /**< Transceiver PHY reset and + configuration. */ +#define XDP_RX_PHY_STATUS 0x208 /**< Current PHY status. */ +#define XDP_RX_PHY_POWER_DOWN 0x210 /**< Control PHY power down. */ +#define XDP_RX_MIN_VOLTAGE_SWING 0x214 /**< Specifies the minimum + voltage swing required + during training before + a link can be reliably + established and advanced + configuration for link + training. */ +#define XDP_RX_CDR_CONTROL_CONFIG 0x21C /**< Control the configuration + for clock and data + recovery. */ +#define XDP_RX_GT_DRP_COMMAND 0x2A0 /**< Provides access to the GT + DRP ports. */ +#define XDP_RX_GT_DRP_READ_DATA 0x2A4 /**< Provides access to GT DRP + read data. */ +#define XDP_RX_GT_DRP_CH_STATUS 0x2A8 /**< Provides access to GT DRP + channel status. */ +/* @} */ + +/** @name DPRX core registers: Audio. + * @{ + */ +#define XDP_RX_AUDIO_CONTROL 0x300 /**< Enables audio stream + packets in main link. */ +#define XDP_RX_AUDIO_INFO_DATA(NUM) (0x304 + 4 * (NUM - 1)) /**< Word + formatted as per CEA + 861-C info frame. */ +#define XDP_RX_AUDIO_MAUD 0x324 /**< M value of audio stream + as decoded from audio + time stamp packet. */ +#define XDP_RX_AUDIO_NAUD 0x328 /**< N value of audio stream + as decoded from audio + time stamp packet. */ +#define XDP_RX_AUDIO_STATUS 0x32C /**< Status of audio stream. */ +#define XDP_RX_AUDIO_EXT_DATA(NUM) (0x330 + 4 * (NUM - 1)) /**< Word + formatted as per + extension packet. */ +/* @} */ + +/** @name DPRX core registers: DPCD configuration space. + * @{ + */ +#define XDP_RX_DPCD_LINK_BW_SET 0x400 /**< Current link bandwidth + setting as exposed in + the RX DPCD. */ +#define XDP_RX_DPCD_LANE_COUNT_SET 0x404 /**< Current lane count + setting as exposed in + the RX DPCD. */ +#define XDP_RX_DPCD_ENHANCED_FRAME_EN 0x408 /**< Current setting for + enhanced framing symbol + mode as exposed in the + RX DPCD. */ +#define XDP_RX_DPCD_TRAINING_PATTERN_SET 0x40C /**< Current training pattern + setting as exposed in + the RX DPCD. */ +#define XDP_RX_DPCD_LINK_QUALITY_PATTERN_SET 0x410 /**< Current value of the + link quality pattern + field as exposed in the + RX DPCD. */ +#define XDP_RX_DPCD_RECOVERED_CLOCK_OUT_EN 0x414 /**< Value of the output clock + enable field as exposed + in the RX DPCD. */ +#define XDP_RX_DPCD_SCRAMBLING_DISABLE 0x418 /**< Value of the scrambling + disable field as exposed + in the RX DPCD. */ +#define XDP_RX_DPCD_SYMBOL_ERROR_COUNT_SELECT 0x41C /**< Current value of the + symbol error count + select field as exposed + in the RX DPCD. */ +#define XDP_RX_DPCD_TRAINING_LANE_0_SET 0x420 /**< The RX DPCD value used by + the TX during link + training to configure + the RX PHY lane 0. */ +#define XDP_RX_DPCD_TRAINING_LANE_1_SET 0x424 /**< The RX DPCD value used by + the TX during link + training to configure + the RX PHY lane 1. */ +#define XDP_RX_DPCD_TRAINING_LANE_2_SET 0x428 /**< The RX DPCD value used by + the TX during link + training to configure + the RX PHY lane 2. */ +#define XDP_RX_DPCD_TRAINING_LANE_3_SET 0x42C /**< The RX DPCD value Used by + the TX during link + training to configure + the RX PHY lane 3. */ +#define XDP_RX_DPCD_DOWNSPREAD_CONTROL 0x430 /**< The RX DPCD value that + is used by the TX to + inform the RX that + downspreading has been + enabled. */ +#define XDP_RX_DPCD_MAIN_LINK_CHANNEL_CODING_SET 0x434 /**< 8B/10B encoding + setting as exposed in + the RX DPCD. */ +#define XDP_RX_DPCD_SET_POWER_STATE 0x438 /**< Power state requested by + the TX as exposed in the + RX DPCD. */ +#define XDP_RX_DPCD_LANE01_STATUS 0x43C /**< Link training status for + lanes 0 and 1 as exposed + in the RX DPCD. */ +#define XDP_RX_DPCD_LANE23_STATUS 0x440 /**< Link training status for + lanes 2 and 3 as exposed + in the RX DPCD. */ +#define XDP_RX_DPCD_SOURCE_OUI_VALUE 0x444 /** The RX DPCD value used by + the TX to set the + organizationally unique + identifier (OUI). */ +#define XDP_RX_DPCD_SYM_ERR_CNT01 0x448 /** The symbol error counter + values for lanes 0 and 1 + as exposed in the RX + DPCD. */ +#define XDP_RX_DPCD_SYM_ERR_CNT23 0x44C /** The symbol error counter + values for lanes 2 and 3 + as exposed in the RX + DPCD. */ +/* @} */ + +/** @name DPRX core registers: Main stream attributes for SST / MST STREAM1. + * @{ + */ +#define XDP_RX_STREAM1_MSA_START 0x500 /**< Start of the MSA registers + for stream 1. */ +#define XDP_RX_MSA_HRES 0x500 /**< Number of active pixels per + line (the horizontal + resolution). */ +#define XDP_RX_MSA_HSPOL 0x504 /**< The horizontal sync + polarity. */ +#define XDP_RX_MSA_HSWIDTH 0x508 /**< Width of the horizontal + sync pulse. */ +#define XDP_RX_MSA_HSTART 0x50C /**< Number of clocks between + the leading edge of the + horizontal sync and the + start of active data. */ +#define XDP_RX_MSA_HTOTAL 0x510 /**< Total number of clocks in + the horizontal framing + period. */ +#define XDP_RX_MSA_VHEIGHT 0x514 /**< Number of active lines (the + vertical resolution). */ +#define XDP_RX_MSA_VSPOL 0x518 /**< The vertical sync + polarity. */ +#define XDP_RX_MSA_VSWIDTH 0x51C /**< Width of the vertical + sync pulse. */ +#define XDP_RX_MSA_VSTART 0x520 /**< Number of lines between the + leading edge of the + vertical sync and the + first line of active + data. */ +#define XDP_RX_MSA_VTOTAL 0x524 /**< Total number of lines in + the video frame. */ +#define XDP_RX_MSA_MISC0 0x528 /**< Miscellaneous stream + attributes. */ +#define XDP_RX_MSA_MISC1 0x52C /**< Miscellaneous stream + attributes. */ +#define XDP_RX_MSA_MVID 0x530 /**< Used to recover the video + clock from the link + clock. */ +#define XDP_RX_MSA_NVID 0x534 /**< Used to recover the video + clock from the link + clock. */ +#define XDP_RX_MSA_VBID 0x538 /**< The most recently received + VB-ID value. */ +/* @} */ + +/** @name DPRX core registers: Main stream attributes for MST STREAM2, 3, and 4. + * @{ + */ +#define XDP_RX_STREAM2_MSA_START 0x540 /**< Start of the MSA registers + for stream 2. */ +#define XDP_RX_STREAM2_MSA_START_OFFSET (XDP_RX_STREAM2_MSA_START - \ + XDP_RX_STREAM1_MSA_START) /**< The MSA registers for + stream 2 are at an + offset from the + corresponding registers + of stream 1. */ +#define XDP_RX_STREAM3_MSA_START 0x580 /**< Start of the MSA registers + for stream 3. */ +#define XDP_RX_STREAM3_MSA_START_OFFSET (XDP_RX_STREAM3_MSA_START - \ + XDP_RX_STREAM1_MSA_START) /**< The MSA registers for + stream 3 are at an + offset from the + corresponding registers + of stream 1. */ +#define XDP_RX_STREAM4_MSA_START 0x5C0 /**< Start of the MSA registers + for stream 4. */ +#define XDP_RX_STREAM4_MSA_START_OFFSET (XDP_RX_STREAM4_MSA_START - \ + XDP_RX_STREAM1_MSA_START) /**< The MSA registers for + stream 4 are at an + offset from the + corresponding registers + of stream 1. */ +/* @} */ + +/** @name DPRX core registers: MST field for sideband message buffers and the + * virtual channel payload table. + * @{ + */ +#define XDP_RX_DOWN_REQ 0xA00 /**< Down request buffer address + space. */ +#define XDP_RX_DOWN_REP 0xB00 /**< Down reply buffer address + space. */ +#define XDP_RX_VC_PAYLOAD_TABLE 0x800 /**< Virtual channel payload + table (0xFF bytes). */ +#define XDP_RX_VC_PAYLOAD_TABLE_ID_SLOT(SlotNum) \ + (XDP_RX_VC_PAYLOAD_TABLE + SlotNum) +/* @} */ + +/** @name DPRX core registers: Vendor specific DPCD. + * @{ + */ +#define XDP_RX_SOURCE_DEVICE_SPECIFIC_FIELD 0xE00 /**< User access to the source + specific field as + exposed in the RX + DPCD (0xFF bytes). */ +#define XDP_RX_SOURCE_DEVICE_SPECIFIC_FIELD_REG(RegNum) \ + (XDP_RX_SOURCE_DEVICE_SPECIFIC_FIELD + (4 * RegNum)) +#define XDP_RX_SINK_DEVICE_SPECIFIC_FIELD 0xF00 /**< User access to the sink + specific field as + exposed in the RX + DPCD (0xFF bytes). */ +#define XDP_RX_SINK_DEVICE_SPECIFIC_FIELD_REG(RegNum) \ + (XDP_RX_SINK_DEVICE_SPECIFIC_FIELD + (4 * RegNum)) +/* @} */ + +/******************************************************************************/ + +/** @name DPRX core masks, shifts, and register values. + * @{ + */ +/* 0x004: AUX_CLK_DIVIDER */ +#define XDP_RX_AUX_CLK_DIVIDER_VAL_MASK 0x00FF /**< Clock divider value. */ +#define XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK \ + 0xFF00 /**< AUX (noise) signal width + filter. */ +#define XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT \ + 8 /**< Shift bits for AUX signal + width filter. */ +/* 0x010: USER_PIXEL_WIDTH */ +#define XDP_RX_USER_PIXEL_WIDTH_1 0x1 /**< Single pixel wide + interface. */ +#define XDP_RX_USER_PIXEL_WIDTH_2 0x2 /**< Dual pixel output mode. */ +#define XDP_RX_USER_PIXEL_WIDTH_4 0x4 /**< Quad pixel output mode. */ +/* 0x014: INTERRUPT_MASK */ +#define XDP_RX_INTERRUPT_MASK_VM_CHANGE_MASK \ + 0x00001 /**< Mask the interrupt + assertion for a + resolution change, as + detected from the MSA + fields. */ +#define XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK \ + 0x00002 /**< Mask the interrupt + assertion for a power + state change. */ +#define XDP_RX_INTERRUPT_MASK_NO_VIDEO_MASK \ + 0x00004 /**< Mask the interrupt + assertion for the + no-video condition being + detected after active + video received. */ +#define XDP_RX_INTERRUPT_MASK_VBLANK_MASK \ + 0x00008 /**< Mask the interrupt + assertion for the start + of the blanking + interval. */ +#define XDP_RX_INTERRUPT_MASK_TRAINING_LOST_MASK \ + 0x00010 /**< Mask the interrupt + assertion for training + loss on active lanes. */ +#define XDP_RX_INTERRUPT_MASK_VIDEO_MASK 0x00040 /**< Mask the interrupt + assertion for a valid + video frame being + detected on the main + link. Video interrupt is + set after a delay of 8 + video frames following a + valid scrambler reset + character. */ +#define XDP_RX_INTERRUPT_MASK_INFO_PKT_MASK \ + 0x00100 /**< Mask the interrupt + assertion for an audio + info packet being + received. */ +#define XDP_RX_INTERRUPT_MASK_EXT_PKT_MASK \ + 0x00200 /**< Mask the interrupt + assertion for an audio + extension packet being + received. */ +#define XDP_RX_INTERRUPT_MASK_VCP_ALLOC_MASK \ + 0x00400 /**< Mask the interrupt + assertion for a virtual + channel payload being + allocated. */ +#define XDP_RX_INTERRUPT_MASK_VCP_DEALLOC_MASK \ + 0x00800 /**< Mask the interrupt + assertion for a virtual + channel payload being + allocated. */ +#define XDP_RX_INTERRUPT_MASK_DOWN_REPLY_MASK \ + 0x01000 /**< Mask the interrupt + assertion for a + downstream reply being + ready. */ +#define XDP_RX_INTERRUPT_MASK_DOWN_REQUEST_MASK \ + 0x02000 /**< Mask the interrupt + assertion for a + downstream request being + ready. */ +#define XDP_RX_INTERRUPT_MASK_TRAINING_DONE_MASK \ + 0x04000 /**< Mask the interrupt + assertion for link + training completion. */ +#define XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK \ + 0x08000 /**< Mask the interrupt + assertion for a change + in bandwidth. */ +#define XDP_RX_INTERRUPT_MASK_TP1_MASK 0x10000 /**< Mask the interrupt + assertion for start of + training pattern 1. */ +#define XDP_RX_INTERRUPT_MASK_TP2_MASK 0x20000 /**< Mask the interrupt + assertion for start of + training pattern 2. */ +#define XDP_RX_INTERRUPT_MASK_TP3_MASK 0x40000 /**< Mask the interrupt + assertion for start of + training pattern 3. */ +#define XDP_RX_INTERRUPT_MASK_ALL_MASK 0x7FFFF /**< Mask all interrupts. */ +/* 0x018: MISC_CTRL */ +#define XDP_RX_MISC_CTRL_USE_FILT_MSA_MASK \ + 0x1 /**< When set, two matching + values must be detected + for each field of the + MSA values before the + associated register is + updated internally. */ +#define XDP_RX_MISC_CTRL_LONG_I2C_USE_DEFER_MASK \ + 0x2 /**< When set, the long I2C + write data transfwers + are responded to using + DEFER instead of partial + ACKs. */ +#define XDP_RX_MISC_CTRL_I2C_USE_AUX_DEFER_MASK \ + 0x4 /**< When set, I2C DEFERs will + be sent as AUX DEFERs to + the source device. */ +/* 0x01C: SOFT_RESET */ +#define XDP_RX_SOFT_RESET_VIDEO_MASK 0x01 /**< Reset the video logic. */ +#define XDP_RX_SOFT_RESET_AUX_MASK 0x80 /**< Reset the AUX logic. */ +/* 0x02C: HPD_INTERRUPT */ +#define XDP_RX_HPD_INTERRUPT_ASSERT_MASK \ + 0x00000001 /**< Instructs the RX core to + assert an interrupt to + the TX using the HPD + signal. */ +#define XDP_RX_HPD_INTERRUPT_LENGTH_US_MASK \ + 0xFFFF0000 /**< The length of the HPD pulse + to generate (in + microseconds). */ +#define XDP_RX_HPD_INTERRUPT_LENGTH_US_SHIFT 16 /**< Shift bits for the HPD + pulse length. */ +/* 0x040: INTERRUPT_CAUSE */ +#define XDP_RX_INTERRUPT_CAUSE_VM_CHANGE_MASK \ + XDP_RX_INTERRUPT_MASK_VM_CHANGE_MASK /**< Interrupt caused by a + resolution change, as + detected from the MSA + fields. */ +#define XDP_RX_INTERRUPT_CAUSE_POWER_STATE_MASK \ + XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK /**< Interrupt caused by a + power state change. */ +#define XDP_RX_INTERRUPT_CAUSE_NO_VIDEO_MASK \ + XDP_RX_INTERRUPT_MASK_NO_VIDEO_MASK /**< Interrupt caused by the + no-video condition being + detected after active + video received. */ +#define XDP_RX_INTERRUPT_CAUSE_VBLANK_MASK \ + XDP_RX_INTERRUPT_MASK_VBLANK_MASK /**< Interrupt caused by the + start of the blanking + interval. */ +#define XDP_RX_INTERRUPT_CAUSE_TRAINING_LOST_MASK \ + XDP_RX_INTERRUPT_MASK_TRAINING_LOST_MASK /**< Interrupt caused by + training loss on active + lanes. */ +#define XDP_RX_INTERRUPT_CAUSE_VIDEO_MASK \ + XDP_RX_INTERRUPT_MASK_VIDEO_MASK /**< Interrupt caused by a + valid video frame being + detected on the main + link. Video interrupt is + set after a delay of 8 + video frames following a + valid scrambler reset + character. */ +#define XDP_RX_INTERRUPT_CAUSE_INFO_PKT_MASK \ + XDP_RX_INTERRUPT_MASK_INFO_PKT_MASK /**< Interrupt caused by an + audio info packet being + received. */ +#define XDP_RX_INTERRUPT_CAUSE_EXT_PKT_MASK \ + XDP_RX_INTERRUPT_MASK_EXT_PKT_MASK /**< Interrupt caused by an + audio extension packet + being received. */ +#define XDP_RX_INTERRUPT_CAUSE_VCP_ALLOC_MASK \ + XDP_RX_INTERRUPT_MASK_VCP_ALLOC_MASK /**< Interrupt caused by a + virtual channel payload + being allocated. */ +#define XDP_RX_INTERRUPT_CAUSE_VCP_DEALLOC_MASK \ + XDP_RX_INTERRUPT_MASK_VCP_DEALLOC_MASK /**< Interrupt caused by a + virtual channel payload + being allocated. */ +#define XDP_RX_INTERRUPT_CAUSE_DOWN_REPLY_MASK \ + XDP_RX_INTERRUPT_MASK_DOWN_REPLY_MASK /**< Interrupt caused by a + downstream reply being + ready. */ +#define XDP_RX_INTERRUPT_CAUSE_DOWN_REQUEST_MASK \ + XDP_RX_INTERRUPT_MASK_DOWN_REQUEST_MASK /**< Interrupt caused by a + downstream request being + ready. */ +#define XDP_RX_INTERRUPT_CAUSE_TRAINING_DONE_MASK \ + XDP_RX_INTERRUPT_MASK_TRAINING_DONE_MASK /**< Interrupt caused by link + training completion. */ +#define XDP_RX_INTERRUPT_CAUSE_BW_CHANGE_MASK \ + XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK /**< Interrupt caused by a + change in bandwidth. */ +#define XDP_RX_INTERRUPT_CAUSE_TP1_MASK \ + XDP_RX_INTERRUPT_MASK_TP1_MASK /**< Interrupt caused by the + start of training + pattern 1. */ +#define XDP_RX_INTERRUPT_CAUSE_TP2_MASK \ + XDP_RX_INTERRUPT_MASK_TP2_MASK /**< Interrupt caused by the + start of training + pattern 2. */ +#define XDP_RX_INTERRUPT_CAUSE_TP3_MASK \ + XDP_RX_INTERRUPT_MASK_TP3_MASK /**< Interrupt caused by the + start of training + pattern 3. */ +/* 0x044: INTERRUPT_MASK_1 */ +#define XDP_RX_INTERRUPT_MASK_1_EXT_PKT_STREAM234_MASK(Stream) \ + (0x00001 << ((Stream - 2) * 6)) /**< Mask the interrupt + assertion for an audio + extension packet being + received for stream + 2, 3, or 4. */ +#define XDP_RX_INTERRUPT_MASK_1_INFO_PKT_STREAM234_MASK(Stream) \ + (0x00002 << ((Stream - 2) * 6)) /**< Mask the interrupt + assertion for an audio + info packet being + received for stream + 2, 3, or 4. */ +#define XDP_RX_INTERRUPT_MASK_1_VM_CHANGE_STREAM234_MASK(Stream) \ + (0x00004 << ((Stream - 2) * 6)) /**< Mask the interrupt + assertion for a + resolution change, as + detected from the MSA + fields for stream 2, 3, + or 4. */ +#define XDP_RX_INTERRUPT_MASK_1_NO_VIDEO_STREAM234_MASK(Stream) \ + (0x00008 << ((Stream - 2) * 6)) /**< Mask the interrupt + assertion for the + no-video condition being + detected after active + video received for + stream 2, 3, or 4. */ +#define XDP_RX_INTERRUPT_MASK_1_VBLANK_STREAM234_MASK(Stream) \ + (0x00010 << ((Stream - 2) * 6)) /**< Mask the interrupt + assertion for the start + of the blanking interval + for stream 2, 3, or + 4. */ +#define XDP_RX_INTERRUPT_MASK_1_VIDEO_STREAM234_MASK(Stream) \ + (0x00020 << ((Stream - 2) * 6)) /**< Mask the interrupt + assertion for a valid + video frame being + detected on the main + link for stream 2, 3, + or 4. */ +/* 0x048: INTERRUPT_CAUSE_1 */ +#define XDP_RX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK(Stream) \ + XDP_RX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK(Stream) /**< Interrupt + caused by an audio + extension packet being + received for stream 2, + 3, or 4. */ +#define XDP_RX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK(Stream) \ + XDP_RX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK(Stream) /**< Interrupt + caused by an audio info + packet being received + for stream 2, 3, or + 4. */ +#define XDP_RX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK(Stream) \ + XDP_RX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK(Stream) /**< Interrupt + caused by a resolution + change, as detected from + the MSA fields for + stream 2, 3, or 4. */ +#define XDP_RX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK(Stream) \ + XDP_RX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK(Stream) /**< Interrupt + caused by the no-video + condition being detected + after active video + received for stream 2, + 3, or 4. */ +#define XDP_RX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK(Stream) \ + XDP_RX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK(Stream) /**< Interrupt + caused by the start of + the blanking interval + for stream 2, 3, or + 4. */ +#define XDP_RX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK(Stream) \ + XDP_RX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK(Stream) /**< Interrupt + caused by a valid video + frame being detected on + the main link for + stream 2, 3, or 4. */ +/* 0x050: HSYNC_WIDTH */ +#define XDP_RX_HSYNC_WIDTH_PULSE_WIDTH_MASK \ + 0x00FF /**< Specifies the number of + clock cycles the + horizontal sync pulse is + asserted. */ +#define XDP_RX_HSYNC_WIDTH_FRONT_PORCH_MASK \ + 0xFF00 /**< Defines the number of video + clock cycles to place + between the last pixel + of active data and the + start of the horizontal + sync pulse (the front + porch). */ +#define XDP_RX_HSYNC_WIDTH_FRONT_PORCH_SHIFT 8 /**< Shift bits for the front + porch. */ +/* 0x090: DEVICE_SERVICE_IRQ */ +#define XDP_RX_DEVICE_SERVICE_IRQ_NEW_REMOTE_CMD_MASK \ + 0x01 /**< Indicates that a new + command is present in + the REMOTE_CMD + register. */ +#define XDP_RX_DEVICE_SERVICE_IRQ_SINK_SPECIFIC_IRQ_MASK \ + 0x02 /**< Reflects the + SINK_SPECIFIC_IRQ + state. */ +#define XDP_RX_DEVICE_SERVICE_IRQ_NEW_DOWN_REPLY_MASK \ + 0x10 /**< Indicates a new DOWN_REPLY + buffer message is + ready. */ +/* 0x09C: OVER_LINK_BW_SET */ +#define XDP_RX_OVER_LINK_BW_SET_162GBPS 0x06 /**< 1.62 Gbps link rate. */ +#define XDP_RX_OVER_LINK_BW_SET_270GBPS 0x0A /**< 2.70 Gbps link rate. */ +#define XDP_RX_OVER_LINK_BW_SET_540GBPS 0x14 /**< 5.40 Gbps link rate. */ + +/* 0x0A0: OVER_LANE_COUNT_SET */ +#define XDP_RX_OVER_LANE_COUNT_SET_MASK 0x1F /**< The lane count override + value. */ +#define XDP_RX_OVER_LANE_COUNT_SET_1 0x1 /**< Lane count of 1. */ +#define XDP_RX_OVER_LANE_COUNT_SET_2 0x2 /**< Lane count of 2. */ +#define XDP_RX_OVER_LANE_COUNT_SET_4 0x4 /**< Lane count of 4. */ +#define XDP_RX_OVER_LANE_COUNT_SET_TPS3_SUPPORTED_MASK \ + 0x20 /**< Capability override for + training pattern 3. */ +#define XDP_RX_OVER_LANE_COUNT_SET_ENHANCED_FRAME_CAP_MASK \ + 0x80 /**< Capability override for + enhanced framing. */ +/* 0x0A4: OVER_TP_SET */ +#define XDP_RX_OVER_TP_SET_TP_SELECT_MASK \ + 0x0003 /**< Training pattern select + override. */ +#define XDP_RX_OVER_TP_SET_LQP_SET_MASK \ + 0x000C /**< Link quality pattern set + override. */ +#define XDP_RX_OVER_TP_SET_LQP_SET_SHIFT 2 /**< Shift bits for link quality + pattern set override. */ +#define XDP_RX_OVER_TP_SET_REC_CLK_OUT_EN_MASK \ + 0x0010 /**< Recovered clock output + enable override. */ +#define XDP_RX_OVER_TP_SET_SCRAMBLER_DISABLE_MASK \ + 0x0020 /**< Scrambling disable + override. */ +#define XDP_RX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_MASK \ + 0x00C0 /**< Symbol error count + override. */ +#define XDP_RX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_SHIFT \ + 6 /**< Shift bits for symbol error + count override. */ +#define XDP_RX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_MASK \ + 0xFF00 /**< Training AUX read interval + override. */ +#define XDP_RX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_SHIFT \ + 8 /**< Shift bits for training AUX + read interval + override. */ +/* 0x0A8, 0x0AC, 0x0B0, 0x0B4: OVER_TRAINING_LANEX_SET */ +#define XDP_RX_OVER_TRAINING_LANEX_SET_VS_SET_MASK \ + 0x03 /**< Voltage swing set + override. */ +#define XDP_RX_OVER_TRAINING_LANEX_SET_MAX_VS_MASK \ + 0x04 /**< Maximum voltage swing + override. */ +#define XDP_RX_OVER_TRAINING_LANEX_SET_PE_SET_MASK \ + 0x18 /**< Pre-emphasis set + override. */ +#define XDP_RX_OVER_TRAINING_LANEX_SET_PE_SET_SHIFT \ + 3 /**< Shift bits for pre-emphasis + set override. */ +#define XDP_RX_OVER_TRAINING_LANEX_SET_MAX_PE_MASK \ + 0x20 /**< Maximum pre-emphasis + override. */ +/* 0x0F8 : VERSION_REGISTER */ +#define XDP_RX_VERSION_INTER_REV_MASK \ + 0x0000000F /**< Internal revision. */ +#define XDP_RX_VERSION_CORE_PATCH_MASK \ + 0x00000030 /**< Core patch details. */ +#define XDP_RX_VERSION_CORE_PATCH_SHIFT \ + 8 /**< Shift bits for core patch + details. */ +#define XDP_RX_VERSION_CORE_VER_REV_MASK \ + 0x000000C0 /**< Core version revision. */ +#define XDP_RX_VERSION_CORE_VER_REV_SHIFT \ + 12 /**< Shift bits for core version + revision. */ +#define XDP_RX_VERSION_CORE_VER_MNR_MASK \ + 0x00000F00 /**< Core minor version. */ +#define XDP_RX_VERSION_CORE_VER_MNR_SHIFT \ + 16 /**< Shift bits for core minor + version. */ +#define XDP_RX_VERSION_CORE_VER_MJR_MASK \ + 0x0000F000 /**< Core major version. */ +#define XDP_RX_VERSION_CORE_VER_MJR_SHIFT \ + 24 /**< Shift bits for core major + version. */ +/* 0x0FC : CORE_ID */ +#define XDP_RX_CORE_ID_TYPE_MASK 0x0000000F /**< Core type. */ +#define XDP_RX_CORE_ID_TYPE_TX 0x0 /**< Core is a transmitter. */ +#define XDP_RX_CORE_ID_TYPE_RX 0x1 /**< Core is a receiver. */ +#define XDP_RX_CORE_ID_DP_REV_MASK \ + 0x000000F0 /**< DisplayPort protocol + revision. */ +#define XDP_RX_CORE_ID_DP_REV_SHIFT \ + 8 /**< Shift bits for DisplayPort + protocol revision. */ +#define XDP_RX_CORE_ID_DP_MNR_VER_MASK \ + 0x00000F00 /**< DisplayPort protocol minor + version. */ +#define XDP_RX_CORE_ID_DP_MNR_VER_SHIFT \ + 16 /**< Shift bits for DisplayPort + protocol major + version. */ +#define XDP_RX_CORE_ID_DP_MJR_VER_MASK \ + 0x0000F000 /**< DisplayPort protocol major + version. */ +#define XDP_RX_CORE_ID_DP_MJR_VER_SHIFT \ + 24 /**< Shift bits for DisplayPort + protocol major + version. */ +/* 0x110: USER_FIFO_OVERFLOW */ +#define XDP_RX_USER_FIFO_OVERFLOW_FLAG_STREAMX_MASK(Stream) \ + (Stream) /**< Indicates that the internal + FIFO has detected on + overflow condition for + the specified stream. */ +#define XDP_RX_USER_FIFO_OVERFLOW_VID_UNPACK_STREAMX_MASK(Stream) \ + (Stream << 4) /**< Indicates that the video + unpack FIFO has + overflown for the + specified stream. */ +#define XDP_RX_USER_FIFO_OVERFLOW_VID_TIMING_STREAMX_MASK(Stream) \ + (Stream << 8) /**< Indicates that the video + timing FIFO has + overflown for the + specified stream. */ +/* 0x114: USER_VSYNC_STATE */ +#define XDP_RX_USER_VSYNC_STATE_STREAMX_MASK(Stream) \ + (Stream) /**< The state of the vertical + sync pulse for the + specified stream. */ +/* 0x200: PHY_CONFIG */ +#define XDP_RX_PHY_CONFIG_PHY_RESET_ENABLE_MASK \ + 0x00000000 /**< Release reset. */ +#define XDP_RX_PHY_CONFIG_GTPLL_RESET_MASK \ + 0x00000001 /**< Hold the GTPLL in reset. */ +#define XDP_RX_PHY_CONFIG_GTRX_RESET_MASK \ + 0x00000002 /**< Hold GTRXRESET in reset. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_PMA_RESET_MASK \ + 0x00000100 /**< Hold RX_PHY_PMA reset. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_PCS_RESET_MASK \ + 0x00000200 /**< Hold RX_PHY_PCS reset. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_BUF_RESET_MASK \ + 0x00000400 /**< Hold RX_PHY_BUF reset. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_DFE_LPM_RESET_MASK \ + 0x00000800 /**< Hold RX_PHY_DFE_LPM + reset. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_MASK \ + 0x00001000 /**< Set RX_PHY_POLARITY. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_LOOPBACK_MASK \ + 0x0000E000 /**< Set RX_PHY_LOOPBACK. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_EYESCANRESET_MASK \ + 0x00010000 /**< Set RX_PHY_EYESCANRESET. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_EYESCANTRIGGER_MASK \ + 0x00020000 /**< Set RX_PHY_ + EYESCANTRIGGER. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_PRBSCNTRESET_MASK \ + 0x00040000 /**< Set RX_PHY_PRBSCNTRESET. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_RXLPMHFHOLD_MASK \ + 0x00080000 /**< Set RX_PHY_RXLPMHFHOLD. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_RXLPMLFHOLD_MASK \ + 0x00100000 /**< Set RX_PHY_RXLPMLFHOLD. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_RXLPMHFOVERDEN_MASK \ + 0x00200000 /**< Set RX_PHY_ + RXLPMHFOVERDEN. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_CDRHOLD_MASK \ + 0x00400000 /**< Set RX_PHY_CDRHOLD. */ +#define XDP_RX_PHY_CONFIG_RESET_AT_TRAIN_ITER_MASK \ + 0x00800000 /**< Issue reset at every + training iteration. */ +#define XDP_RX_PHY_CONFIG_RESET_AT_LINK_RATE_CHANGE_MASK \ + 0x01000000 /**< Issue reset at every link + rate change. */ +#define XDP_RX_PHY_CONFIG_RESET_AT_TP1_START_MASK \ + 0x02000000 /**< Issue reset at start of + training pattern 1. */ +#define XDP_RX_PHY_CONFIG_EN_CFG_RX_PHY_POLARITY_MASK \ + 0x04000000 /**< Enable the individual lane + polarity. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE0_MASK \ + 0x08000000 /**< Configure RX_PHY_POLARITY + for lane 0. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE1_MASK \ + 0x10000000 /**< Configure RX_PHY_POLARITY + for lane 1. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE2_MASK \ + 0x20000000 /**< Configure RX_PHY_POLARITY + for lane 2. */ +#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE3_MASK \ + 0x40000000 /**< Configure RX_PHY_POLARITY + for lane 3. */ +#define XDP_RX_PHY_CONFIG_GT_ALL_RESET_MASK \ + 0x00000003 /**< Rest GT and PHY. */ +/* 0x208: PHY_STATUS */ +#define XDP_RX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK \ + 0x00000003 /**< Reset done for lanes + 0 and 1. */ +#define XDP_RX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK \ + 0x0000000C /**< Reset done for lanes + 2 and 3. */ +#define XDP_RX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT \ + 2 /**< Shift bits for reset done + for lanes 2 and 3. */ +#define XDP_RX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK \ + 0x00000010 /**< PLL locked for lanes + 0 and 1. */ +#define XDP_RX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK \ + 0x00000020 /**< PLL locked for lanes + 2 and 3. */ +#define XDP_RX_PHY_STATUS_PLL_FABRIC_LOCK_MASK \ + 0x00000040 /**< FPGA fabric clock PLL + locked. */ +#define XDP_RX_PHY_STATUS_RX_CLK_LOCK_MASK \ + 0x00000080 /**< Receiver clock locked. */ +#define XDP_RX_PHY_STATUS_PRBSERR_LANE_0_MASK \ + 0x00000100 /**< PRBS error on lane 0. */ +#define XDP_RX_PHY_STATUS_PRBSERR_LANE_1_MASK \ + 0x00000200 /**< PRBS error on lane 1. */ +#define XDP_RX_PHY_STATUS_PRBSERR_LANE_2_MASK \ + 0x00000400 /**< PRBS error on lane 2. */ +#define XDP_RX_PHY_STATUS_PRBSERR_LANE_3_MASK \ + 0x00000800 /**< PRBS error on lane 3. */ +#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_0_MASK \ + 0x00001000 /**< RX voltage low on lane + 0. */ +#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_1_MASK \ + 0x00002000 /**< RX voltage low on lane + 1. */ +#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_2_MASK \ + 0x00004000 /**< RX voltage low on lane + 2. */ +#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_3_MASK \ + 0x00008000 /**< RX voltage low on lane + 3. */ +#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_0_MASK \ + 0x00010000 /**< Lane aligment status for + lane 0. */ +#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_1_MASK \ + 0x00020000 /**< Lane aligment status for + lane 1. */ +#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_2_MASK \ + 0x00040000 /**< Lane aligment status for + lane 2. */ +#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_3_MASK \ + 0x00080000 /**< Lane aligment status for + lane 3. */ +#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_0_MASK \ + 0x00100000 /**< Symbol lock status for + lane 0. */ +#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_1_MASK \ + 0x00200000 /**< Symbol lock status for + lane 1. */ +#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_2_MASK \ + 0x00400000 /**< Symbol lock status for + lane 2. */ +#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_3_MASK \ + 0x00800000 /**< Symbol lock status for + lane 3. */ +#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_MASK \ + 0x03000000 /**< RX buffer status lane 0. */ +#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_SHIFT \ + 24 /**< Shift bits for RX buffer + status lane 0. */ +#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_1_MASK \ + 0x0C000000 /**< RX buffer status lane 1. */ +#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUE_LANE_1_SHIFT \ + 26 /**< Shift bits for RX buffer + status lane 1. */ +#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_MASK \ + 0x30000000 /**< RX buffer status lane 2. */ +#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_SHIFT \ + 28 /**< Shift bits for RX buffer + status lane 2. */ +#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_MASK \ + 0xC0000000 /**< RX buffer status lane 3. */ +#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_SHIFT \ + 30 /**< Shift bits for RX buffer + status lane 3. */ +#define XDP_RX_PHY_STATUS_LANES_0_1_READY_MASK \ + 0x00000013 /**< Lanes 0 and 1 are ready. */ +#define XDP_RX_PHY_STATUS_ALL_LANES_READY_MASK \ + 0x0000003F /**< All lanes are ready. */ +/* 0x210: PHY_POWER_DOWN */ +#define XDP_RX_PHY_POWER_DOWN_LANE_0_MASK 0x1 /**< Power down the PHY for lane + 0. */ +#define XDP_RX_PHY_POWER_DOWN_LANE_1_MASK 0x2 /**< Power down the PHY for lane + 1. */ +#define XDP_RX_PHY_POWER_DOWN_LANE_2_MASK 0x4 /**< Power down the PHY for lane + 2. */ +#define XDP_RX_PHY_POWER_DOWN_LANE_3_MASK 0x8 /**< Power down the PHY for lane + 3. */ +/* @} */ + +/******************************************************************************/ + +/******************************************************************************/ +/** + * Address mapping for the DisplayPort Configuration Data (DPCD) of the + * downstream device. + * +*******************************************************************************/ +/** @name DisplayPort Configuration Data: Receiver capability field. + * @{ + */ +#define XDP_DPCD_REV 0x00000 +#define XDP_DPCD_MAX_LINK_RATE 0x00001 +#define XDP_DPCD_MAX_LANE_COUNT 0x00002 +#define XDP_DPCD_MAX_DOWNSPREAD 0x00003 +#define XDP_DPCD_NORP_PWR_V_CAP 0x00004 +#define XDP_DPCD_DOWNSP_PRESENT 0x00005 +#define XDP_DPCD_ML_CH_CODING_CAP 0x00006 +#define XDP_DPCD_DOWNSP_COUNT_MSA_OUI 0x00007 +#define XDP_DPCD_RX_PORT0_CAP_0 0x00008 +#define XDP_DPCD_RX_PORT0_CAP_1 0x00009 +#define XDP_DPCD_RX_PORT1_CAP_0 0x0000A +#define XDP_DPCD_RX_PORT1_CAP_1 0x0000B +#define XDP_DPCD_I2C_SPEED_CTL_CAP 0x0000C +#define XDP_DPCD_EDP_CFG_CAP 0x0000D +#define XDP_DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E +#define XDP_DPCD_ADAPTER_CAP 0x0000F +#define XDP_DPCD_FAUX_CAP 0x00020 +#define XDP_DPCD_MSTM_CAP 0x00021 +#define XDP_DPCD_NUM_AUDIO_EPS 0x00022 +#define XDP_DPCD_AV_GRANULARITY 0x00023 +#define XDP_DPCD_AUD_DEC_LAT_7_0 0x00024 +#define XDP_DPCD_AUD_DEC_LAT_15_8 0x00025 +#define XDP_DPCD_AUD_PP_LAT_7_0 0x00026 +#define XDP_DPCD_AUD_PP_LAT_15_8 0x00027 +#define XDP_DPCD_VID_INTER_LAT 0x00028 +#define XDP_DPCD_VID_PROG_LAT 0x00029 +#define XDP_DPCD_REP_LAT 0x0002A +#define XDP_DPCD_AUD_DEL_INS_7_0 0x0002B +#define XDP_DPCD_AUD_DEL_INS_15_8 0x0002C +#define XDP_DPCD_AUD_DEL_INS_23_16 0x0002D +#define XDP_DPCD_GUID 0x00030 +#define XDP_DPCD_RX_GTC_VALUE_7_0 0x00054 +#define XDP_DPCD_RX_GTC_VALUE_15_8 0x00055 +#define XDP_DPCD_RX_GTC_VALUE_23_16 0x00056 +#define XDP_DPCD_RX_GTC_VALUE_31_24 0x00057 +#define XDP_DPCD_RX_GTC_MSTR_REQ 0x00058 +#define XDP_DPCD_RX_GTC_FREQ_LOCK_DONE 0x00059 +#define XDP_DPCD_DOWNSP_0_CAP 0x00080 +#define XDP_DPCD_DOWNSP_1_CAP 0x00081 +#define XDP_DPCD_DOWNSP_2_CAP 0x00082 +#define XDP_DPCD_DOWNSP_3_CAP 0x00083 +#define XDP_DPCD_DOWNSP_0_DET_CAP 0x00080 +#define XDP_DPCD_DOWNSP_1_DET_CAP 0x00084 +#define XDP_DPCD_DOWNSP_2_DET_CAP 0x00088 +#define XDP_DPCD_DOWNSP_3_DET_CAP 0x0008C +/* @} */ + +/** @name DisplayPort Configuration Data: Link configuration field. + * @{ + */ +#define XDP_DPCD_LINK_BW_SET 0x00100 +#define XDP_DPCD_LANE_COUNT_SET 0x00101 +#define XDP_DPCD_TP_SET 0x00102 +#define XDP_DPCD_TRAINING_LANE0_SET 0x00103 +#define XDP_DPCD_TRAINING_LANE1_SET 0x00104 +#define XDP_DPCD_TRAINING_LANE2_SET 0x00105 +#define XDP_DPCD_TRAINING_LANE3_SET 0x00106 +#define XDP_DPCD_DOWNSPREAD_CTRL 0x00107 +#define XDP_DPCD_ML_CH_CODING_SET 0x00108 +#define XDP_DPCD_I2C_SPEED_CTL_SET 0x00109 +#define XDP_DPCD_EDP_CFG_SET 0x0010A +#define XDP_DPCD_LINK_QUAL_LANE0_SET 0x0010B +#define XDP_DPCD_LINK_QUAL_LANE1_SET 0x0010C +#define XDP_DPCD_LINK_QUAL_LANE2_SET 0x0010D +#define XDP_DPCD_LINK_QUAL_LANE3_SET 0x0010E +#define XDP_DPCD_TRAINING_LANE0_1_SET2 0x0010F +#define XDP_DPCD_TRAINING_LANE2_3_SET2 0x00110 +#define XDP_DPCD_MSTM_CTRL 0x00111 +#define XDP_DPCD_AUDIO_DELAY_7_0 0x00112 +#define XDP_DPCD_AUDIO_DELAY_15_8 0x00113 +#define XDP_DPCD_AUDIO_DELAY_23_6 0x00114 +#define XDP_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED 0x00118 +#define XDP_DPCD_FAUX_MODE_CTRL 0x00120 +#define XDP_DPCD_FAUX_FORWARD_CH_DRIVE_SET 0x00121 +#define XDP_DPCD_BACK_CH_STATUS 0x00122 +#define XDP_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT 0x00123 +#define XDP_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME 0x00125 +#define XDP_DPCD_TX_GTC_VALUE_7_0 0x00154 +#define XDP_DPCD_TX_GTC_VALUE_15_8 0x00155 +#define XDP_DPCD_TX_GTC_VALUE_23_16 0x00156 +#define XDP_DPCD_TX_GTC_VALUE_31_24 0x00157 +#define XDP_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN 0x00158 +#define XDP_DPCD_TX_GTC_FREQ_LOCK_DONE 0x00159 +#define XDP_DPCD_ADAPTER_CTRL 0x001A0 +#define XDP_DPCD_BRANCH_DEVICE_CTRL 0x001A1 +#define XDP_DPCD_PAYLOAD_ALLOCATE_SET 0x001C0 +#define XDP_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x001C1 +#define XDP_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x001C2 +/* @} */ + +/** @name DisplayPort Configuration Data: Link/sink status field. + * @{ + */ +#define XDP_DPCD_SINK_COUNT 0x00200 +#define XDP_DPCD_DEVICE_SERVICE_IRQ 0x00201 +#define XDP_DPCD_STATUS_LANE_0_1 0x00202 +#define XDP_DPCD_STATUS_LANE_2_3 0x00203 +#define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED 0x00204 +#define XDP_DPCD_SINK_STATUS 0x00205 +#define XDP_DPCD_ADJ_REQ_LANE_0_1 0x00206 +#define XDP_DPCD_ADJ_REQ_LANE_2_3 0x00207 +#define XDP_DPCD_TRAINING_SCORE_LANE_0 0x00208 +#define XDP_DPCD_TRAINING_SCORE_LANE_1 0x00209 +#define XDP_DPCD_TRAINING_SCORE_LANE_2 0x0020A +#define XDP_DPCD_TRAINING_SCORE_LANE_3 0x0020B +#define XDP_DPCD_ADJ_REQ_PC2 0x0020C +#define XDP_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT 0x0020D +#define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_0 0x00210 +#define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_1 0x00212 +#define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_2 0x00214 +#define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_3 0x00216 +/* @} */ + +/** @name DisplayPort Configuration Data: Automated testing sub-field. + * @{ + */ +#define XDP_DPCD_FAUX_FORWARD_CH_STATUS 0x00280 +#define XDP_DPCD_FAUX_BACK_CH_DRIVE_SET 0x00281 +#define XDP_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL 0x00282 +#define XDP_DPCD_PAYLOAD_TABLE_UPDATE_STATUS 0x002C0 +#define XDP_DPCD_VC_PAYLOAD_ID_SLOT(SlotNum) \ + (XDP_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum) +/* @} */ + +/** @name DisplayPort Configuration Data: Sink control field. + * @{ + */ +#define XDP_DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600 +/* @} */ + +/** @name DisplayPort Configuration Data: Sideband message buffers. + * @{ + */ +#define XDP_DPCD_DOWN_REQ 0x01000 +#define XDP_DPCD_UP_REP 0x01200 +#define XDP_DPCD_DOWN_REP 0x01400 +#define XDP_DPCD_UP_REQ 0x01600 +/* @} */ + +/** @name DisplayPort Configuration Data: Event status indicator field. + * @{ + */ +#define XDP_DPCD_SINK_COUNT_ESI 0x02002 +#define XDP_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x02003 +#define XDP_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x02004 +#define XDP_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0 0x02005 +#define XDP_DPCD_SINK_LANE0_1_STATUS 0x0200C +#define XDP_DPCD_SINK_LANE2_3_STATUS 0x0200D +#define XDP_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI 0x0200E +#define XDP_DPCD_SINK_STATUS_ESI 0x0200F +/* @} */ + +/** @name DisplayPort Configuration Data: Field addresses and sizes. + * @{ + */ +#define XDP_DPCD_RECEIVER_CAP_FIELD_START XDP_DPCD_REV +#define XDP_DPCD_RECEIVER_CAP_FIELD_SIZE 0x100 +#define XDP_DPCD_LINK_CFG_FIELD_START XDP_DPCD_LINK_BW_SET +#define XDP_DPCD_LINK_CFG_FIELD_SIZE 0x100 +#define XDP_DPCD_LINK_SINK_STATUS_FIELD_START XDP_DPCD_SINK_COUNT +#define XDP_DPCD_LINK_SINK_STATUS_FIELD_SIZE 0x17 +/* @} */ + +/******************************************************************************/ + +/** @name DisplayPort Configuration Data: Receiver capability field masks, + * shifts, and register values. + * @{ + */ +/* 0x00000: DPCD_REV */ +#define XDP_DPCD_REV_MNR_MASK 0x0F +#define XDP_DPCD_REV_MJR_MASK 0xF0 +#define XDP_DPCD_REV_MJR_SHIFT 4 +/* 0x00001: MAX_LINK_RATE */ +#define XDP_DPCD_MAX_LINK_RATE_162GBPS 0x06 +#define XDP_DPCD_MAX_LINK_RATE_270GBPS 0x0A +#define XDP_DPCD_MAX_LINK_RATE_540GBPS 0x14 +/* 0x00002: MAX_LANE_COUNT */ +#define XDP_DPCD_MAX_LANE_COUNT_MASK 0x1F +#define XDP_DPCD_MAX_LANE_COUNT_1 0x01 +#define XDP_DPCD_MAX_LANE_COUNT_2 0x02 +#define XDP_DPCD_MAX_LANE_COUNT_4 0x04 +#define XDP_DPCD_TPS3_SUPPORT_MASK 0x40 +#define XDP_DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80 +/* 0x00003: MAX_DOWNSPREAD */ +#define XDP_DPCD_MAX_DOWNSPREAD_MASK 0x01 +#define XDP_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK 0x40 +/* 0x00005: DOWNSP_PRESENT */ +#define XDP_DPCD_DOWNSP_PRESENT_MASK 0x01 +#define XDP_DPCD_DOWNSP_TYPE_MASK 0x06 +#define XDP_DPCD_DOWNSP_TYPE_SHIFT 1 +#define XDP_DPCD_DOWNSP_TYPE_DP 0x0 +#define XDP_DPCD_DOWNSP_TYPE_AVGA_ADVII 0x1 +#define XDP_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP 0x2 +#define XDP_DPCD_DOWNSP_TYPE_OTHERS 0x3 +#define XDP_DPCD_DOWNSP_FORMAT_CONV_MASK 0x08 +#define XDP_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK 0x10 +/* 0x00006, 0x00108: ML_CH_CODING_SUPPORT, ML_CH_CODING_SET */ +#define XDP_DPCD_ML_CH_CODING_MASK 0x01 +/* 0x00007: DOWNSP_COUNT_MSA_OUI */ +#define XDP_DPCD_DOWNSP_COUNT_MASK 0x0F +#define XDP_DPCD_MSA_TIMING_PAR_IGNORED_MASK 0x40 +#define XDP_DPCD_OUI_SUPPORT_MASK 0x80 +/* 0x00008, 0x0000A: RX_PORT[0-1]_CAP_0 */ +#define XDP_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK 0x02 +#define XDP_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK 0x04 +/* 0x0000C, 0x00109: I2C_SPEED_CTL_CAP, I2C_SPEED_CTL_SET */ +#define XDP_DPCD_I2C_SPEED_CTL_NONE 0x00 +#define XDP_DPCD_I2C_SPEED_CTL_1KBIPS 0x01 +#define XDP_DPCD_I2C_SPEED_CTL_5KBIPS 0x02 +#define XDP_DPCD_I2C_SPEED_CTL_10KBIPS 0x04 +#define XDP_DPCD_I2C_SPEED_CTL_100KBIPS 0x08 +#define XDP_DPCD_I2C_SPEED_CTL_400KBIPS 0x10 +#define XDP_DPCD_I2C_SPEED_CTL_1MBIPS 0x20 +/* 0x0000E: TRAIN_AUX_RD_INTERVAL */ +#define XDP_DPCD_TRAIN_AUX_RD_INT_100_400US 0x00 +#define XDP_DPCD_TRAIN_AUX_RD_INT_4MS 0x01 +#define XDP_DPCD_TRAIN_AUX_RD_INT_8MS 0x02 +#define XDP_DPCD_TRAIN_AUX_RD_INT_12MS 0x03 +#define XDP_DPCD_TRAIN_AUX_RD_INT_16MS 0x04 +/* 0x00020: DPCD_FAUX_CAP */ +#define XDP_DPCD_FAUX_CAP_MASK 0x01 +/* 0x00021: MSTM_CAP */ +#define XDP_DPCD_MST_CAP_MASK 0x01 +/* 0x00080, 0x00081|4, 0x00082|8, 0x00083|C: DOWNSP_X_(DET_)CAP */ +#define XDP_DPCD_DOWNSP_X_CAP_TYPE_MASK 0x07 +#define XDP_DPCD_DOWNSP_X_CAP_TYPE_DP 0x0 +#define XDP_DPCD_DOWNSP_X_CAP_TYPE_AVGA 0x1 +#define XDP_DPCD_DOWNSP_X_CAP_TYPE_DVI 0x2 +#define XDP_DPCD_DOWNSP_X_CAP_TYPE_HDMI 0x3 +#define XDP_DPCD_DOWNSP_X_CAP_TYPE_OTHERS 0x4 +#define XDP_DPCD_DOWNSP_X_CAP_TYPE_DPPP 0x5 +#define XDP_DPCD_DOWNSP_X_CAP_HPD_MASK 0x80 +#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK 0xF0 +#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT 4 +#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60 0x1 +#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50 0x2 +#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60 0x3 +#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50 0x4 +#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60 0x5 +#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50 0x7 +/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */ +#define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK 0x03 +#define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_8 0x0 +#define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_10 0x1 +#define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_12 0x2 +#define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_16 0x3 +/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */ +#define XDP_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK 0x01 +#define XDP_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK 0x02 +#define XDP_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK 0x04 +/* @} */ + +/** @name DisplayPort Configuration Data: Link configuration field masks, + * shifts, and register values. + * @{ + */ +/* 0x00100: XDP_DPCD_LINK_BW_SET */ +#define XDP_DPCD_LINK_BW_SET_162GBPS 0x06 +#define XDP_DPCD_LINK_BW_SET_270GBPS 0x0A +#define XDP_DPCD_LINK_BW_SET_540GBPS 0x14 +/* 0x00101: LANE_COUNT_SET */ +#define XDP_DPCD_LANE_COUNT_SET_MASK 0x1F +#define XDP_DPCD_LANE_COUNT_SET_1 0x01 +#define XDP_DPCD_LANE_COUNT_SET_2 0x02 +#define XDP_DPCD_LANE_COUNT_SET_4 0x04 +#define XDP_DPCD_ENHANCED_FRAME_EN_MASK 0x80 +/* 0x00102: TP_SET */ +#define XDP_DPCD_TP_SEL_MASK 0x03 +#define XDP_DPCD_TP_SEL_OFF 0x0 +#define XDP_DPCD_TP_SEL_TP1 0x1 +#define XDP_DPCD_TP_SEL_TP2 0x2 +#define XDP_DPCD_TP_SEL_TP3 0x3 +#define XDP_DPCD_TP_SET_LQP_MASK 0x06 +#define XDP_DPCD_TP_SET_LQP_SHIFT 2 +#define XDP_DPCD_TP_SET_LQP_OFF 0x0 +#define XDP_DPCD_TP_SET_LQP_D102_TEST 0x1 +#define XDP_DPCD_TP_SET_LQP_SER_MES 0x2 +#define XDP_DPCD_TP_SET_LQP_PRBS7 0x3 +#define XDP_DPCD_TP_SET_REC_CLK_OUT_EN_MASK 0x10 +#define XDP_DPCD_TP_SET_SCRAMB_DIS_MASK 0x20 +#define XDP_DPCD_TP_SET_SE_COUNT_SEL_MASK 0xC0 +#define XDP_DPCD_TP_SET_SE_COUNT_SEL_SHIFT 6 +#define XDP_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE 0x0 +#define XDP_DPCD_TP_SET_SE_COUNT_SEL_DE 0x1 +#define XDP_DPCD_TP_SET_SE_COUNT_SEL_ISE 0x2 +/* 0x00103-0x00106: TRAINING_LANE[0-3]_SET */ +#define XDP_DPCD_TRAINING_LANEX_SET_VS_MASK 0x03 +#define XDP_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04 +#define XDP_DPCD_TRAINING_LANEX_SET_PE_MASK 0x18 +#define XDP_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 +#define XDP_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20 +/* 0x00107: DOWNSPREAD_CTRL */ +#define XDP_DPCD_SPREAD_AMP_MASK 0x10 +#define XDP_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK 0x80 +/* 0x00108: ML_CH_CODING_SET - Same as 0x00006: ML_CH_CODING_SUPPORT */ +/* 0x00109: I2C_SPEED_CTL_SET - Same as 0x0000C: I2C_SPEED_CTL_CAP */ +/* 0x0010F-0x00110: TRAINING_LANE[0_1-2_3]_SET2 */ +#define XDP_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK 0x03 +#define XDP_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK 0x04 +#define XDP_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK 0x30 +#define XDP_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT 4 +#define XDP_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK 0x40 +/* 0x00111: MSTM_CTRL */ +#define XDP_DPCD_MST_EN_MASK 0x01 +#define XDP_DPCD_UP_REQ_EN_MASK 0x02 +#define XDP_DPCD_UP_IS_SRC_MASK 0x03 +/* @} */ + +/** @name DisplayPort Configuration Data: Link/sink status field masks, shifts, + * and register values. + * @{ + */ +/* 0x00202: STATUS_LANE_0_1 */ +#define XDP_DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01 +#define XDP_DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02 +#define XDP_DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04 +#define XDP_DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10 +#define XDP_DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20 +#define XDP_DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40 +/* 0x00202: STATUS_LANE_2_3 */ +#define XDP_DPCD_STATUS_LANE_2_CR_DONE_MASK 0x01 +#define XDP_DPCD_STATUS_LANE_2_CE_DONE_MASK 0x02 +#define XDP_DPCD_STATUS_LANE_2_SL_DONE_MASK 0x04 +#define XDP_DPCD_STATUS_LANE_3_CR_DONE_MASK 0x10 +#define XDP_DPCD_STATUS_LANE_3_CE_DONE_MASK 0x20 +#define XDP_DPCD_STATUS_LANE_3_SL_DONE_MASK 0x40 +/* 0x00204: LANE_ALIGN_STATUS_UPDATED */ +#define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK \ + 0x01 +#define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK \ + 0x40 +#define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK \ + 0x80 +/* 0x00205: SINK_STATUS */ +#define XDP_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK 0x01 +#define XDP_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK 0x02 + +/* 0x00206, 0x00207: ADJ_REQ_LANE_[0,2]_[1,3] */ +#define XDP_DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03 +#define XDP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C +#define XDP_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2 +#define XDP_DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30 +#define XDP_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4 +#define XDP_DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0 +#define XDP_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6 +/* 0x0020C: ADJ_REQ_PC2 */ +#define XDP_DPCD_ADJ_REQ_PC2_LANE_0_MASK 0x03 +#define XDP_DPCD_ADJ_REQ_PC2_LANE_1_MASK 0x0C +#define XDP_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT 2 +#define XDP_DPCD_ADJ_REQ_PC2_LANE_2_MASK 0x30 +#define XDP_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT 4 +#define XDP_DPCD_ADJ_REQ_PC2_LANE_3_MASK 0xC0 +#define XDP_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT 6 +/* @} */ + +/******************************************************************************/ + +/******************************************************************************/ +/** + * Address mapping for the Extended Display Identification Data (EDID) of the + * downstream device. + * +*******************************************************************************/ +/** @name Extended Display Identification Data: Field addresses and sizes. + * @{ + */ +#define XDP_SEGPTR_ADDR 0x30 +#define XDP_EDID_ADDR 0x50 +#define XDP_EDID_BLOCK_SIZE 128 +#define XDP_EDID_DTD_DD(Num) (0x36 + (18 * Num)) +#define XDP_EDID_PTM XDP_EDID_DTD_DD(0) +#define XDP_EDID_EXT_BLOCK_COUNT 0x7E +/* @} */ + +/** @name Extended Display Identification Data: Register offsets for the + * Detailed Timing Descriptor (DTD). + * @{ + */ +#define XDP_EDID_DTD_PIXEL_CLK_KHZ_LSB 0x00 +#define XDP_EDID_DTD_PIXEL_CLK_KHZ_MSB 0x01 +#define XDP_EDID_DTD_HRES_LSB 0x02 +#define XDP_EDID_DTD_HBLANK_LSB 0x03 +#define XDP_EDID_DTD_HRES_HBLANK_U4 0x04 +#define XDP_EDID_DTD_VRES_LSB 0x05 +#define XDP_EDID_DTD_VBLANK_LSB 0x06 +#define XDP_EDID_DTD_VRES_VBLANK_U4 0x07 +#define XDP_EDID_DTD_HFPORCH_LSB 0x08 +#define XDP_EDID_DTD_HSPW_LSB 0x09 +#define XDP_EDID_DTD_VFPORCH_VSPW_L4 0x0A +#define XDP_EDID_DTD_XFPORCH_XSPW_U2 0x0B +#define XDP_EDID_DTD_HIMGSIZE_MM_LSB 0x0C +#define XDP_EDID_DTD_VIMGSIZE_MM_LSB 0x0D +#define XDP_EDID_DTD_XIMGSIZE_MM_U4 0x0E +#define XDP_EDID_DTD_HBORDER 0x0F +#define XDP_EDID_DTD_VBORDER 0x10 +#define XDP_EDID_DTD_SIGNAL 0x11 + +/** @name Extended Display Identification Data: Masks, shifts, and register + * values. + * @{ + */ +#define XDP_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK 0x0F +#define XDP_EDID_DTD_XRES_XBLANK_U4_XRES_MASK 0xF0 +#define XDP_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT 4 +#define XDP_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK 0x0F +#define XDP_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK 0xF0 +#define XDP_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT 4 +#define XDP_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK 0xC0 +#define XDP_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK 0x30 +#define XDP_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK 0x0C +#define XDP_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK 0x03 +#define XDP_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT 6 +#define XDP_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT 4 +#define XDP_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT 2 +#define XDP_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK 0x0F +#define XDP_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK 0xF0 +#define XDP_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT 4 +#define XDP_EDID_DTD_SIGNAL_HPOLARITY_MASK 0x02 +#define XDP_EDID_DTD_SIGNAL_VPOLARITY_MASK 0x04 +#define XDP_EDID_DTD_SIGNAL_HPOLARITY_SHIFT 1 +#define XDP_EDID_DTD_SIGNAL_VPOLARITY_SHIFT 2 +/* @} */ + +/** @name Extended Display Identification Data: Register offsets for the + * DisplayID extension block. + * @{ + */ +#define XDP_EDID_EXT_BLOCK_TAG 0x00 +#define XDP_TX_DISPID_VER_REV 0x00 +#define XDP_TX_DISPID_SIZE 0x01 +#define XDP_TX_DISPID_TYPE 0x02 +#define XDP_TX_DISPID_EXT_COUNT 0x03 +#define XDP_TX_DISPID_PAYLOAD_START 0x04 +#define XDP_TX_DISPID_DB_SEC_TAG 0x00 +#define XDP_TX_DISPID_DB_SEC_REV 0x01 +#define XDP_TX_DISPID_DB_SEC_SIZE 0x02 +/* @} */ + +/** @name Extended Display Identification Data: Masks, shifts, and register + * values for the DisplayID extension block. + * @{ + */ +#define XDP_EDID_EXT_BLOCK_TAG_DISPID 0x70 +#define XDP_TX_DISPID_TDT_TAG 0x12 +/* @} */ + +/** @name Extended Display Identification Data: Register offsets for the + * Tiled Display Topology (TDT) section data block. + * @{ + */ +#define XDP_TX_DISPID_TDT_TOP0 0x04 +#define XDP_TX_DISPID_TDT_TOP1 0x05 +#define XDP_TX_DISPID_TDT_TOP2 0x06 +#define XDP_TX_DISPID_TDT_HSIZE0 0x07 +#define XDP_TX_DISPID_TDT_HSIZE1 0x08 +#define XDP_TX_DISPID_TDT_VSIZE0 0x09 +#define XDP_TX_DISPID_TDT_VSIZE1 0x0A +#define XDP_TX_DISPID_TDT_VENID0 0x10 +#define XDP_TX_DISPID_TDT_VENID1 0x11 +#define XDP_TX_DISPID_TDT_VENID2 0x12 +#define XDP_TX_DISPID_TDT_PCODE0 0x13 +#define XDP_TX_DISPID_TDT_PCODE1 0x14 +#define XDP_TX_DISPID_TDT_SN0 0x15 +#define XDP_TX_DISPID_TDT_SN1 0x16 +#define XDP_TX_DISPID_TDT_SN2 0x17 +#define XDP_TX_DISPID_TDT_SN3 0x18 +/* @} */ + +/** @name Extended Display Identification Data: Masks, shifts, and register + * values for the Tiled Display Topology (TDT) section data block. + * @{ + */ +#define XDP_TX_DISPID_TDT_TOP0_HTOT_L_SHIFT 4 +#define XDP_TX_DISPID_TDT_TOP0_HTOT_L_MASK (0xF << 4) +#define XDP_TX_DISPID_TDT_TOP0_VTOT_L_MASK 0xF +#define XDP_TX_DISPID_TDT_TOP1_HLOC_L_SHIFT 4 +#define XDP_TX_DISPID_TDT_TOP1_HLOC_L_MASK (0xF << 4) +#define XDP_TX_DISPID_TDT_TOP1_VLOC_L_MASK 0xF +#define XDP_TX_DISPID_TDT_TOP2_HTOT_H_SHIFT 6 +#define XDP_TX_DISPID_TDT_TOP2_HTOT_H_MASK (0x3 << 6) +#define XDP_TX_DISPID_TDT_TOP2_VTOT_H_SHIFT 4 +#define XDP_TX_DISPID_TDT_TOP2_VTOT_H_MASK (0x3 << 4) +#define XDP_TX_DISPID_TDT_TOP2_HLOC_H_SHIFT 2 +#define XDP_TX_DISPID_TDT_TOP2_HLOC_H_MASK (0x3 << 2) +#define XDP_TX_DISPID_TDT_TOP2_VLOC_H_MASK 0x3 +/* @} */ + +/******************************************************************************/ +/** + * Multi-stream transport (MST) definitions. + * +*******************************************************************************/ +/** @name Stream identification. + * @{ + */ +#define XDP_TX_STREAM_ID1 1 +#define XDP_TX_STREAM_ID2 2 +#define XDP_TX_STREAM_ID3 3 +#define XDP_TX_STREAM_ID4 4 +/* @} */ + +/** @name Sideband message codes when the driver is in MST mode. + * @{ + */ +#define XDP_TX_SBMSG_LINK_ADDRESS 0x01 +#define XDP_TX_SBMSG_ENUM_PATH_RESOURCES 0x10 +#define XDP_TX_SBMSG_ALLOCATE_PAYLOAD 0x11 +#define XDP_TX_SBMSG_CLEAR_PAYLOAD_ID_TABLE 0x14 +#define XDP_TX_SBMSG_REMOTE_DPCD_READ 0x20 +#define XDP_TX_SBMSG_REMOTE_DPCD_WRITE 0x21 +#define XDP_TX_SBMSG_REMOTE_I2C_READ 0x22 +#define XDP_TX_SBMSG_REMOTE_I2C_WRITE 0x23 +/* @} */ + +/******************* Macros (Inline Functions) Definitions ********************/ + +/** @name Register access macro definitions. + * @{ + */ +#define XDp_In32 Xil_In32 +#define XDp_Out32 Xil_Out32 +/* @} */ + +/******************************************************************************/ +/** + * This is a low-level function that reads from the specified register. + * + * @param BaseAddress is the base address of the device. + * @param RegOffset is the register offset to be read from. + * + * @return The 32-bit value of the specified register. + * + * @note C-style signature: + * u32 XDp_ReadReg(u32 BaseAddress, u32 RegOffset) + * +*******************************************************************************/ +#define XDp_ReadReg(BaseAddress, RegOffset) \ + XDp_In32((BaseAddress) + (RegOffset)) + +/******************************************************************************/ +/** + * This is a low-level function that writes to the specified register. + * + * @param BaseAddress is the base address of the device. + * @param RegOffset is the register offset to write to. + * @param Data is the 32-bit data to write to the specified register. + * + * @return None. + * + * @note C-style signature: + * void XDp_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) + * +*******************************************************************************/ +#define XDp_WriteReg(BaseAddress, RegOffset, Data) \ + XDp_Out32((BaseAddress) + (RegOffset), (Data)) + + +/******************************************************************************/ +/** + * Check if an Extended Display Identification Data (EDID) extension block is of + * type DisplayID. + * + * @param Ext is a pointer to the EDID extension block under comparison. + * + * @return + * - 1 if the extension block is of type DisplayID. + * - Otherwise. + * + * @note C-style signature: + * u8 XDp_TxIsEdidExtBlockDispId(u8 *Ext) + * +*******************************************************************************/ +#define XDp_TxIsEdidExtBlockDispId(Ext) \ + (Ext[XDP_EDID_EXT_BLOCK_TAG] == XDP_EDID_EXT_BLOCK_TAG_DISPID) + +/******************************************************************************/ +/** + * Given a Tiled Display Topology (TDT) data block, retrieve the total number of + * horizontal tiles in the tiled display. The TDT block is part of an Extended + * Display Identification Data (EDID) extension block of type DisplayID. + * + * @param Tdt is a pointer to the TDT data block. + * + * @return The total number of horizontal tiles in the tiled display. + * + * @note C-style signature: + * u8 XDp_TxGetDispIdTdtHTotal(u8 *Tdt) + * +*******************************************************************************/ +#define XDp_TxGetDispIdTdtHTotal(Tdt) \ + (((((Tdt[XDP_TX_DISPID_TDT_TOP2] & XDP_TX_DISPID_TDT_TOP2_HTOT_H_MASK) \ + >> XDP_TX_DISPID_TDT_TOP2_HTOT_H_SHIFT) << 4) | \ + ((Tdt[XDP_TX_DISPID_TDT_TOP0] & XDP_TX_DISPID_TDT_TOP0_HTOT_L_MASK) >> \ + XDP_TX_DISPID_TDT_TOP0_HTOT_L_SHIFT)) + 1) + +/******************************************************************************/ +/** + * Given a Tiled Display Topology (TDT) data block, retrieve the total number of + * vertical tiles in the tiled display. The TDT block is part of an Extended + * Display Identification Data (EDID) extension block of type DisplayID. + * + * @param Tdt is a pointer to the TDT data block. + * + * @return The total number of vertical tiles in the tiled display. + * + * @note C-style signature: + * u8 XDp_TxGetDispIdTdtVTotal(u8 *Tdt) + * +*******************************************************************************/ +#define XDp_TxGetDispIdTdtVTotal(Tdt) \ + (((((Tdt[XDP_TX_DISPID_TDT_TOP2] & XDP_TX_DISPID_TDT_TOP2_VTOT_H_MASK) \ + >> XDP_TX_DISPID_TDT_TOP2_VTOT_H_SHIFT) << 4) | \ + (Tdt[XDP_TX_DISPID_TDT_TOP0] & XDP_TX_DISPID_TDT_TOP0_VTOT_L_MASK)) + 1) + +/******************************************************************************/ +/** + * Given a Tiled Display Topology (TDT) data block, retrieve the horizontal tile + * location in the tiled display. The TDT block is part of an Extended Display + * Identification Data (EDID) extension block of type DisplayID. + * + * @param Tdt is a pointer to the TDT data block. + * + * @return The horizontal tile location in the tiled display represented by + * the specified TDT. + * + * @note C-style signature: + * u8 XDp_TxGetDispIdTdtHLoc(u8 *Tdt) + * +*******************************************************************************/ +#define XDp_TxGetDispIdTdtHLoc(Tdt) \ + ((((Tdt[XDP_TX_DISPID_TDT_TOP2] & XDP_TX_DISPID_TDT_TOP2_HLOC_H_MASK) \ + >> XDP_TX_DISPID_TDT_TOP2_HLOC_H_SHIFT) << 4) | \ + ((Tdt[XDP_TX_DISPID_TDT_TOP1] & XDP_TX_DISPID_TDT_TOP1_HLOC_L_MASK) >> \ + XDP_TX_DISPID_TDT_TOP1_HLOC_L_SHIFT)) + +/******************************************************************************/ +/** + * Given a Tiled Display Topology (TDT) data block, retrieve the vertical tile + * location in the tiled display. The TDT block is part of an Extended Display + * Identification Data (EDID) extension block of type DisplayID. + * + * @param Tdt is a pointer to the TDT data block. + * + * @return The vertical tile location in the tiled display represented by + * the specified TDT. + * + * @note C-style signature: + * u8 XDp_TxGetDispIdTdtVLoc(u8 *Tdt) + * +*******************************************************************************/ +#define XDp_TxGetDispIdTdtVLoc(Tdt) \ + (((Tdt[XDP_TX_DISPID_TDT_TOP2] & XDP_TX_DISPID_TDT_TOP2_VLOC_H_MASK) << \ + 4) | (Tdt[XDP_TX_DISPID_TDT_TOP1] & XDP_TX_DISPID_TDT_TOP1_VLOC_L_MASK)) + +/******************************************************************************/ +/** + * Given a Tiled Display Topology (TDT) data block, retrieve the total number of + * tiles in the tiled display. The TDT block is part of an Extended Display + * Identification Data (EDID) extension block of type DisplayID. + * + * @param Tdt is a pointer to the TDT data block. + * + * @return The total number of tiles in the tiled display. + * + * @note C-style signature: + * u8 XDp_TxGetDispIdTdtNumTiles(u8 *Tdt) + * +*******************************************************************************/ +#define XDp_TxGetDispIdTdtNumTiles(Tdt) \ + (XDp_TxGetDispIdTdtHTotal(Tdt) * XDp_TxGetDispIdTdtVTotal(Tdt)) + +/******************************************************************************/ +/** + * Given a Tiled Display Topology (TDT) data block, calculate the tiling order + * of the associated tile. The TDT block is part of an Extended Display + * Identification Data (EDID) extension block of type DisplayID. + * The tiling order starts at 0 for x,y coordinate 0,0 and increments as the + * horizontal location increases. Once the last horizontal tile has been + * reached, the next tile in the order is 0,y+1. + * + * @param Tdt is a pointer to the TDT data block. + * + * @return The total number of horizontal tiles in the tiled display. + * + * @note C-style signature: + * u8 XDp_TxGetDispIdTdtTileOrder(u8 *Tdt) + * +*******************************************************************************/ +#define XDp_TxGetDispIdTdtTileOrder(Tdt) \ + ((XDp_TxGetDispIdTdtVLoc(Tdt) * XDp_TxGetDispIdTdtHTotal(Tdt)) + \ + XDp_TxGetDispIdTdtHLoc(Tdt)) + +#endif /* XDP_HW_H_ */ diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdprx_intr.c b/XilinxProcessorIPLib/drivers/dp/src/xdp_intr.c similarity index 52% rename from XilinxProcessorIPLib/drivers/dp/src/xdprx_intr.c rename to XilinxProcessorIPLib/drivers/dp/src/xdp_intr.c index 5a76336e..e7730d6b 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdprx_intr.c +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp_intr.c @@ -32,9 +32,9 @@ /******************************************************************************/ /** * - * @file xdprx_intr.c + * @file xdp_intr.c * - * This file contains functions related to XDprx interrupt handling. + * This file contains functions related to XDp interrupt handling. * * @note None. * @@ -43,118 +43,48 @@ * * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- - * 1.0 als 01/20/14 Initial release. + * 1.0 als 01/20/15 Initial release. * * *******************************************************************************/ /******************************* Include Files ********************************/ -#include "xdprx.h" +#include "xdp.h" + +/**************************** Function Prototypes *****************************/ + +static void XDp_TxInterruptHandler(XDp *InstancePtr); +static void XDp_RxInterruptHandler(XDp *InstancePtr); /**************************** Function Definitions ****************************/ /******************************************************************************/ /** - * This function is the interrupt handler for the XDprx driver. + * This function is the interrupt handler for the XDp driver. + * When an interrupt happens, this interrupt handler will check which TX/RX mode + * of operation the core is running in, and will call the appropriate interrupt + * handler. The called interrupt handler will first detect what kind of + * interrupt happened, then decides which callback function to invoke. * - * When an interrupt happens, it first detects what kind of interrupt happened, - * then decides which callback function to invoke. - * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * * @note None. * *******************************************************************************/ -void XDprx_InterruptHandler(XDprx *InstancePtr) +void XDp_InterruptHandler(XDp *InstancePtr) { - u32 IntrStatus; - u8 IntrVmChange, IntrPowerState, IntrNoVideo, IntrVBlank, - IntrTrainingLost, IntrVideo, IntrTrainingDone, IntrBwChange, - IntrTp1, IntrTp2, IntrTp3; - /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - /* Determine what kind of interrupt(s) occurred. - * Note: XDPRX_INTERRUPT_CAUSE is an RC (read-clear) register. */ - IntrStatus = XDprx_ReadReg(InstancePtr->Config.BaseAddr, - XDPRX_INTERRUPT_CAUSE); - IntrVmChange = (IntrStatus & XDPRX_INTERRUPT_CAUSE_VM_CHANGE_MASK); - IntrPowerState = (IntrStatus & XDPRX_INTERRUPT_CAUSE_POWER_STATE_MASK); - IntrNoVideo = (IntrStatus & XDPRX_INTERRUPT_CAUSE_NO_VIDEO_MASK); - IntrVBlank = (IntrStatus & XDPRX_INTERRUPT_CAUSE_VBLANK_MASK); - IntrTrainingLost = (IntrStatus & - XDPRX_INTERRUPT_CAUSE_TRAINING_LOST_MASK); - IntrVideo = (IntrStatus & XDPRX_INTERRUPT_CAUSE_VIDEO_MASK); - IntrTrainingDone = (IntrStatus & - XDPRX_INTERRUPT_CAUSE_TRAINING_DONE_MASK); - IntrBwChange = (IntrStatus & XDPRX_INTERRUPT_CAUSE_BW_CHANGE_MASK); - IntrTp1 = (IntrStatus & XDPRX_INTERRUPT_CAUSE_TP1_MASK); - IntrTp2 = (IntrStatus & XDPRX_INTERRUPT_CAUSE_TP2_MASK); - IntrTp3 = (IntrStatus & XDPRX_INTERRUPT_CAUSE_TP3_MASK); - - /* Training pattern 1 has started. */ - if (IntrTp1) { - InstancePtr->IntrTp1Handler(InstancePtr->IntrTp1CallbackRef); + if (XDp_CfgGetCoreType(&InstancePtr->Config) == XDP_TX) { + XDp_TxInterruptHandler(InstancePtr); } - /* Training pattern 2 has started. */ - if (IntrTp2) { - InstancePtr->IntrTp2Handler(InstancePtr->IntrTp2CallbackRef); - } - /* Training pattern 3 has started. */ - if (IntrTp3) { - InstancePtr->IntrTp3Handler(InstancePtr->IntrTp3CallbackRef); - } - /* Training lost - the link has been lost. */ - if (IntrTrainingLost) { - InstancePtr->IntrTrainingLostHandler( - InstancePtr->IntrTrainingLostCallbackRef); - } - /* The link has been trained. */ - else if (IntrTrainingDone) { - InstancePtr->IntrTrainingDoneHandler( - InstancePtr->IntrTrainingDoneCallbackRef); - } - - /* A change has been detected in the current video transmitted on the - * link as indicated by the main stream attributes (MSA) fields. The - * horizontal and vertical resolution parameters are monitored for - * changes. */ - if (IntrVmChange) { - InstancePtr->IntrVmChangeHandler( - InstancePtr->IntrVmChangeCallbackRef); - } - /* The VerticalBlanking_Flag in the VB-ID field of the received stream - * indicates the start of the vertical blanking interval. */ - if (IntrVBlank) { - InstancePtr->IntrVBlankHandler( - InstancePtr->IntrVBlankCallbackRef); - } - /* The receiver has detected the no-video flags in the VB-ID field after - * active video has been received. */ - if (IntrNoVideo) { - InstancePtr->IntrNoVideoHandler( - InstancePtr->IntrNoVideoCallbackRef); - } - /* A valid video frame is detected on the main link. */ - else if (IntrVideo) { - InstancePtr->IntrVideoHandler( - InstancePtr->IntrVideoCallbackRef); - } - - /* The transmitter has requested a change in the current power state of - * the receiver core. */ - if (IntrPowerState) { - InstancePtr->IntrPowerStateHandler( - InstancePtr->IntrPowerStateCallbackRef); - } - /* A change in the bandwidth has been detected. */ - if (IntrBwChange) { - InstancePtr->IntrBwChangeHandler( - InstancePtr->IntrBwChangeCallbackRef); + else { + XDp_RxInterruptHandler(InstancePtr); } } @@ -163,7 +93,7 @@ void XDprx_InterruptHandler(XDprx *InstancePtr) * This function generates a pulse on the hot-plug-detect (HPD) line of the * specified duration. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param DurationUs is the duration of the HPD pulse, in microseconds. * * @return None. @@ -171,22 +101,22 @@ void XDprx_InterruptHandler(XDprx *InstancePtr) * @note None. * *******************************************************************************/ -void XDprx_GenerateHpdInterrupt(XDprx *InstancePtr, u16 DurationUs) +void XDp_RxGenerateHpdInterrupt(XDp *InstancePtr, u16 DurationUs) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_HPD_INTERRUPT, - (DurationUs << XDPRX_HPD_INTERRUPT_LENGTH_US_SHIFT) | - XDPRX_HPD_INTERRUPT_ASSERT_MASK); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_HPD_INTERRUPT, + (DurationUs << XDP_RX_HPD_INTERRUPT_LENGTH_US_SHIFT) | + XDP_RX_HPD_INTERRUPT_ASSERT_MASK); } /******************************************************************************/ /** * This function enables interrupts associated with the specified mask. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Mask specifies which interrupts should be enabled. Bits set to * 1 will enable the corresponding interrupts. * @@ -195,7 +125,7 @@ void XDprx_GenerateHpdInterrupt(XDprx *InstancePtr, u16 DurationUs) * @note None. * *******************************************************************************/ -void XDprx_InterruptEnable(XDprx *InstancePtr, u32 Mask) +void XDp_RxInterruptEnable(XDp *InstancePtr, u32 Mask) { u32 MaskVal; @@ -203,10 +133,10 @@ void XDprx_InterruptEnable(XDprx *InstancePtr, u32 Mask) Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - MaskVal = XDprx_ReadReg(InstancePtr->Config.BaseAddr, - XDPRX_INTERRUPT_CAUSE); + MaskVal = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_RX_INTERRUPT_CAUSE); MaskVal &= ~Mask; - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_INTERRUPT_MASK, + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_INTERRUPT_MASK, MaskVal); } @@ -214,7 +144,7 @@ void XDprx_InterruptEnable(XDprx *InstancePtr, u32 Mask) /** * This function disables interrupts associated with the specified mask. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Mask specifies which interrupts should be disabled. Bits set to * 1 will disable the corresponding interrupts. * @@ -223,7 +153,7 @@ void XDprx_InterruptEnable(XDprx *InstancePtr, u32 Mask) * @note None. * *******************************************************************************/ -void XDprx_InterruptDisable(XDprx *InstancePtr, u32 Mask) +void XDp_RxInterruptDisable(XDp *InstancePtr, u32 Mask) { u32 MaskVal; @@ -231,19 +161,74 @@ void XDprx_InterruptDisable(XDprx *InstancePtr, u32 Mask) Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - MaskVal = XDprx_ReadReg(InstancePtr->Config.BaseAddr, - XDPRX_INTERRUPT_CAUSE); + MaskVal = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_RX_INTERRUPT_CAUSE); MaskVal |= Mask; - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_INTERRUPT_MASK, + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_INTERRUPT_MASK, MaskVal); } + +/******************************************************************************/ +/** + * This function installs a callback function for when a hot-plug-detect event + * interrupt occurs. + * + * @param InstancePtr is a pointer to the XDp instance. + * @param CallbackFunc is the address to the callback function. + * @param CallbackRef is the user data item that will be passed to the + * callback function when it is invoked. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XDp_TxSetHpdEventHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(CallbackFunc != NULL); + Xil_AssertVoid(CallbackRef != NULL); + + InstancePtr->TxInstance.HpdEventHandler = CallbackFunc; + InstancePtr->TxInstance.HpdEventCallbackRef = CallbackRef; +} + +/******************************************************************************/ +/** + * This function installs a callback function for when a hot-plug-detect pulse + * interrupt occurs. + * + * @param InstancePtr is a pointer to the XDp instance. + * @param CallbackFunc is the address to the callback function. + * @param CallbackRef is the user data item that will be passed to the + * callback function when it is invoked. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XDp_TxSetHpdPulseHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(CallbackFunc != NULL); + Xil_AssertVoid(CallbackRef != NULL); + + InstancePtr->TxInstance.HpdPulseHandler = CallbackFunc; + InstancePtr->TxInstance.HpdPulseCallbackRef = CallbackRef; +} + /******************************************************************************/ /** * This function installs a callback function for when a video mode change * interrupt occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param CallbackFunc is the address to the callback function. * @param CallbackRef is the user data item that will be passed to the * callback function when it is invoked. @@ -253,16 +238,16 @@ void XDprx_InterruptDisable(XDprx *InstancePtr, u32 Mask) * @note None. * *******************************************************************************/ -void XDprx_SetIntrVmChangeHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef) +void XDp_RxSetIntrVmChangeHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(CallbackFunc != NULL); Xil_AssertVoid(CallbackRef != NULL); - InstancePtr->IntrVmChangeHandler = CallbackFunc; - InstancePtr->IntrVmChangeCallbackRef = CallbackRef; + InstancePtr->RxInstance.IntrVmChangeHandler = CallbackFunc; + InstancePtr->RxInstance.IntrVmChangeCallbackRef = CallbackRef; } /******************************************************************************/ @@ -270,7 +255,7 @@ void XDprx_SetIntrVmChangeHandler(XDprx *InstancePtr, * This function installs a callback function for when the power state interrupt * occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param CallbackFunc is the address to the callback function. * @param CallbackRef is the user data item that will be passed to the * callback function when it is invoked. @@ -280,16 +265,16 @@ void XDprx_SetIntrVmChangeHandler(XDprx *InstancePtr, * @note None. * *******************************************************************************/ -void XDprx_SetIntrPowerStateHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef) +void XDp_RxSetIntrPowerStateHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(CallbackFunc != NULL); Xil_AssertVoid(CallbackRef != NULL); - InstancePtr->IntrPowerStateHandler = CallbackFunc; - InstancePtr->IntrPowerStateCallbackRef = CallbackRef; + InstancePtr->RxInstance.IntrPowerStateHandler = CallbackFunc; + InstancePtr->RxInstance.IntrPowerStateCallbackRef = CallbackRef; } /******************************************************************************/ @@ -297,7 +282,7 @@ void XDprx_SetIntrPowerStateHandler(XDprx *InstancePtr, * This function installs a callback function for when a no video interrupt * occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param CallbackFunc is the address to the callback function. * @param CallbackRef is the user data item that will be passed to the * callback function when it is invoked. @@ -307,16 +292,16 @@ void XDprx_SetIntrPowerStateHandler(XDprx *InstancePtr, * @note None. * *******************************************************************************/ -void XDprx_SetIntrNoVideoHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef) +void XDp_RxSetIntrNoVideoHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(CallbackFunc != NULL); Xil_AssertVoid(CallbackRef != NULL); - InstancePtr->IntrNoVideoHandler = CallbackFunc; - InstancePtr->IntrNoVideoCallbackRef = CallbackRef; + InstancePtr->RxInstance.IntrNoVideoHandler = CallbackFunc; + InstancePtr->RxInstance.IntrNoVideoCallbackRef = CallbackRef; } /******************************************************************************/ @@ -324,7 +309,7 @@ void XDprx_SetIntrNoVideoHandler(XDprx *InstancePtr, * This function installs a callback function for when a vertical blanking * interrupt occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param CallbackFunc is the address to the callback function. * @param CallbackRef is the user data item that will be passed to the * callback function when it is invoked. @@ -334,16 +319,16 @@ void XDprx_SetIntrNoVideoHandler(XDprx *InstancePtr, * @note None. * *******************************************************************************/ -void XDprx_SetIntrVBlankHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef) +void XDp_RxSetIntrVBlankHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(CallbackFunc != NULL); Xil_AssertVoid(CallbackRef != NULL); - InstancePtr->IntrVBlankHandler = CallbackFunc; - InstancePtr->IntrVBlankCallbackRef = CallbackRef; + InstancePtr->RxInstance.IntrVBlankHandler = CallbackFunc; + InstancePtr->RxInstance.IntrVBlankCallbackRef = CallbackRef; } /******************************************************************************/ @@ -351,7 +336,7 @@ void XDprx_SetIntrVBlankHandler(XDprx *InstancePtr, * This function installs a callback function for when a training lost interrupt * occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param CallbackFunc is the address to the callback function. * @param CallbackRef is the user data item that will be passed to the * callback function when it is invoked. @@ -361,16 +346,16 @@ void XDprx_SetIntrVBlankHandler(XDprx *InstancePtr, * @note None. * *******************************************************************************/ -void XDprx_SetIntrTrainingLostHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef) +void XDp_RxSetIntrTrainingLostHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(CallbackFunc != NULL); Xil_AssertVoid(CallbackRef != NULL); - InstancePtr->IntrTrainingLostHandler = CallbackFunc; - InstancePtr->IntrTrainingLostCallbackRef = CallbackRef; + InstancePtr->RxInstance.IntrTrainingLostHandler = CallbackFunc; + InstancePtr->RxInstance.IntrTrainingLostCallbackRef = CallbackRef; } /******************************************************************************/ @@ -378,7 +363,7 @@ void XDprx_SetIntrTrainingLostHandler(XDprx *InstancePtr, * This function installs a callback function for when a valid video interrupt * occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param CallbackFunc is the address to the callback function. * @param CallbackRef is the user data item that will be passed to the * callback function when it is invoked. @@ -388,16 +373,16 @@ void XDprx_SetIntrTrainingLostHandler(XDprx *InstancePtr, * @note None. * *******************************************************************************/ -void XDprx_SetIntrVideoHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef) +void XDp_RxSetIntrVideoHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(CallbackFunc != NULL); Xil_AssertVoid(CallbackRef != NULL); - InstancePtr->IntrVideoHandler = CallbackFunc; - InstancePtr->IntrVideoCallbackRef = CallbackRef; + InstancePtr->RxInstance.IntrVideoHandler = CallbackFunc; + InstancePtr->RxInstance.IntrVideoCallbackRef = CallbackRef; } /******************************************************************************/ @@ -405,7 +390,7 @@ void XDprx_SetIntrVideoHandler(XDprx *InstancePtr, * This function installs a callback function for when a training done interrupt * occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param CallbackFunc is the address to the callback function. * @param CallbackRef is the user data item that will be passed to the * callback function when it is invoked. @@ -415,16 +400,16 @@ void XDprx_SetIntrVideoHandler(XDprx *InstancePtr, * @note None. * *******************************************************************************/ -void XDprx_SetIntrTrainingDoneHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef) +void XDp_RxSetIntrTrainingDoneHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(CallbackFunc != NULL); Xil_AssertVoid(CallbackRef != NULL); - InstancePtr->IntrTrainingDoneHandler = CallbackFunc; - InstancePtr->IntrTrainingDoneCallbackRef = CallbackRef; + InstancePtr->RxInstance.IntrTrainingDoneHandler = CallbackFunc; + InstancePtr->RxInstance.IntrTrainingDoneCallbackRef = CallbackRef; } /******************************************************************************/ @@ -432,7 +417,7 @@ void XDprx_SetIntrTrainingDoneHandler(XDprx *InstancePtr, * This function installs a callback function for when a bandwidth change * interrupt occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param CallbackFunc is the address to the callback function. * @param CallbackRef is the user data item that will be passed to the * callback function when it is invoked. @@ -442,16 +427,16 @@ void XDprx_SetIntrTrainingDoneHandler(XDprx *InstancePtr, * @note None. * *******************************************************************************/ -void XDprx_SetIntrBwChangeHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef) +void XDp_RxSetIntrBwChangeHandler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(CallbackFunc != NULL); Xil_AssertVoid(CallbackRef != NULL); - InstancePtr->IntrBwChangeHandler = CallbackFunc; - InstancePtr->IntrBwChangeCallbackRef = CallbackRef; + InstancePtr->RxInstance.IntrBwChangeHandler = CallbackFunc; + InstancePtr->RxInstance.IntrBwChangeCallbackRef = CallbackRef; } /******************************************************************************/ @@ -459,7 +444,7 @@ void XDprx_SetIntrBwChangeHandler(XDprx *InstancePtr, * This function installs a callback function for when a training pattern 1 * interrupt occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param CallbackFunc is the address to the callback function. * @param CallbackRef is the user data item that will be passed to the * callback function when it is invoked. @@ -469,16 +454,16 @@ void XDprx_SetIntrBwChangeHandler(XDprx *InstancePtr, * @note None. * *******************************************************************************/ -void XDprx_SetIntrTp1Handler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef) +void XDp_RxSetIntrTp1Handler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(CallbackFunc != NULL); Xil_AssertVoid(CallbackRef != NULL); - InstancePtr->IntrTp1Handler = CallbackFunc; - InstancePtr->IntrTp1CallbackRef = CallbackRef; + InstancePtr->RxInstance.IntrTp1Handler = CallbackFunc; + InstancePtr->RxInstance.IntrTp1CallbackRef = CallbackRef; } /******************************************************************************/ @@ -486,7 +471,7 @@ void XDprx_SetIntrTp1Handler(XDprx *InstancePtr, * This function installs a callback function for when a training pattern 2 * interrupt occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param CallbackFunc is the address to the callback function. * @param CallbackRef is the user data item that will be passed to the * callback function when it is invoked. @@ -496,16 +481,16 @@ void XDprx_SetIntrTp1Handler(XDprx *InstancePtr, * @note None. * *******************************************************************************/ -void XDprx_SetIntrTp2Handler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef) +void XDp_RxSetIntrTp2Handler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(CallbackFunc != NULL); Xil_AssertVoid(CallbackRef != NULL); - InstancePtr->IntrTp2Handler = CallbackFunc; - InstancePtr->IntrTp2CallbackRef = CallbackRef; + InstancePtr->RxInstance.IntrTp2Handler = CallbackFunc; + InstancePtr->RxInstance.IntrTp2CallbackRef = CallbackRef; } /******************************************************************************/ @@ -513,7 +498,7 @@ void XDprx_SetIntrTp2Handler(XDprx *InstancePtr, * This function installs a callback function for when a training pattern 3 * interrupt occurs. * - * @param InstancePtr is a pointer to the XDprx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param CallbackFunc is the address to the callback function. * @param CallbackRef is the user data item that will be passed to the * callback function when it is invoked. @@ -523,14 +508,187 @@ void XDprx_SetIntrTp2Handler(XDprx *InstancePtr, * @note None. * *******************************************************************************/ -void XDprx_SetIntrTp3Handler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef) +void XDp_RxSetIntrTp3Handler(XDp *InstancePtr, + XDp_IntrHandler CallbackFunc, void *CallbackRef) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(CallbackFunc != NULL); Xil_AssertVoid(CallbackRef != NULL); - InstancePtr->IntrTp3Handler = CallbackFunc; - InstancePtr->IntrTp3CallbackRef = CallbackRef; + InstancePtr->RxInstance.IntrTp3Handler = CallbackFunc; + InstancePtr->RxInstance.IntrTp3CallbackRef = CallbackRef; +} + +/******************************************************************************/ +/** + * This function is the interrupt handler for the XDp driver operating in TX + * mode. + * + * When an interrupt happens, it first detects what kind of interrupt happened, + * then decides which callback function to invoke. + * + * @param InstancePtr is a pointer to the XDp instance. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +static void XDp_TxInterruptHandler(XDp *InstancePtr) +{ + u32 IntrStatus; + u8 HpdEventDetected; + u8 HpdPulseDetected; + u32 HpdDuration; + u32 IntrMask; + + /* Determine what kind of interrupt occurred. + * Note: XDP_TX_INTERRUPT_STATUS is an RC (read-clear) register. */ + IntrStatus = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_INTERRUPT_STATUS); + IntrStatus &= ~XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_INTERRUPT_MASK); + IntrMask = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_INTERRUPT_MASK); + + HpdEventDetected = IntrStatus & XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK; + HpdPulseDetected = IntrStatus & + XDP_TX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK; + + if (HpdEventDetected) { + /* Mask interrupts while event handling is taking place. API + * will error out in case of a disconnection event anyway. */ + XDp_WriteReg(InstancePtr->Config.BaseAddr, + XDP_TX_INTERRUPT_MASK, IntrMask | + XDP_TX_INTERRUPT_MASK_HPD_EVENT_MASK); + + InstancePtr->TxInstance.HpdEventHandler( + InstancePtr->TxInstance.HpdEventCallbackRef); + } + else if (HpdPulseDetected && XDp_TxIsConnected(InstancePtr)) { + /* Mask interrupts while event handling is taking place. */ + XDp_WriteReg(InstancePtr->Config.BaseAddr, + XDP_TX_INTERRUPT_MASK, IntrMask | + XDP_TX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK); + + /* The source device must debounce the incoming HPD signal by + * sampling the value at an interval greater than 0.500 ms. An + * HPD pulse should be of width 0.5 ms - 1.0 ms. */ + HpdDuration = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_TX_HPD_DURATION); + if (HpdDuration >= 500) { + InstancePtr->TxInstance.HpdPulseHandler( + InstancePtr->TxInstance.HpdPulseCallbackRef); + } + } + + /* Unmask previously masked interrupts once handling is done. */ + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_INTERRUPT_MASK, + IntrMask); +} + +/******************************************************************************/ +/** + * This function is the interrupt handler for the XDp driver operating in RX + * mode. + * + * When an interrupt happens, it first detects what kind of interrupt happened, + * then decides which callback function to invoke. + * + * @param InstancePtr is a pointer to the XDp instance. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +static void XDp_RxInterruptHandler(XDp *InstancePtr) +{ + u32 IntrStatus; + u8 IntrVmChange, IntrPowerState, IntrNoVideo, IntrVBlank, + IntrTrainingLost, IntrVideo, IntrTrainingDone, IntrBwChange, + IntrTp1, IntrTp2, IntrTp3; + + /* Determine what kind of interrupt(s) occurred. + * Note: XDP_RX_INTERRUPT_CAUSE is an RC (read-clear) register. */ + IntrStatus = XDp_ReadReg(InstancePtr->Config.BaseAddr, + XDP_RX_INTERRUPT_CAUSE); + IntrVmChange = (IntrStatus & XDP_RX_INTERRUPT_CAUSE_VM_CHANGE_MASK); + IntrPowerState = (IntrStatus & XDP_RX_INTERRUPT_CAUSE_POWER_STATE_MASK); + IntrNoVideo = (IntrStatus & XDP_RX_INTERRUPT_CAUSE_NO_VIDEO_MASK); + IntrVBlank = (IntrStatus & XDP_RX_INTERRUPT_CAUSE_VBLANK_MASK); + IntrTrainingLost = (IntrStatus & + XDP_RX_INTERRUPT_CAUSE_TRAINING_LOST_MASK); + IntrVideo = (IntrStatus & XDP_RX_INTERRUPT_CAUSE_VIDEO_MASK); + IntrTrainingDone = (IntrStatus & + XDP_RX_INTERRUPT_CAUSE_TRAINING_DONE_MASK); + IntrBwChange = (IntrStatus & XDP_RX_INTERRUPT_CAUSE_BW_CHANGE_MASK); + IntrTp1 = (IntrStatus & XDP_RX_INTERRUPT_CAUSE_TP1_MASK); + IntrTp2 = (IntrStatus & XDP_RX_INTERRUPT_CAUSE_TP2_MASK); + IntrTp3 = (IntrStatus & XDP_RX_INTERRUPT_CAUSE_TP3_MASK); + + /* Training pattern 1 has started. */ + if (IntrTp1) { + InstancePtr->RxInstance.IntrTp1Handler( + InstancePtr->RxInstance.IntrTp1CallbackRef); + } + /* Training pattern 2 has started. */ + if (IntrTp2) { + InstancePtr->RxInstance.IntrTp2Handler( + InstancePtr->RxInstance.IntrTp2CallbackRef); + } + /* Training pattern 3 has started. */ + if (IntrTp3) { + InstancePtr->RxInstance.IntrTp3Handler( + InstancePtr->RxInstance.IntrTp3CallbackRef); + } + /* Training lost - the link has been lost. */ + if (IntrTrainingLost) { + InstancePtr->RxInstance.IntrTrainingLostHandler( + InstancePtr->RxInstance.IntrTrainingLostCallbackRef); + } + /* The link has been trained. */ + else if (IntrTrainingDone) { + InstancePtr->RxInstance.IntrTrainingDoneHandler( + InstancePtr->RxInstance.IntrTrainingDoneCallbackRef); + } + + /* A change has been detected in the current video transmitted on the + * link as indicated by the main stream attributes (MSA) fields. The + * horizontal and vertical resolution parameters are monitored for + * changes. */ + if (IntrVmChange) { + InstancePtr->RxInstance.IntrVmChangeHandler( + InstancePtr->RxInstance.IntrVmChangeCallbackRef); + } + /* The VerticalBlanking_Flag in the VB-ID field of the received stream + * indicates the start of the vertical blanking interval. */ + if (IntrVBlank) { + InstancePtr->RxInstance.IntrVBlankHandler( + InstancePtr->RxInstance.IntrVBlankCallbackRef); + } + /* The receiver has detected the no-video flags in the VB-ID field after + * active video has been received. */ + if (IntrNoVideo) { + InstancePtr->RxInstance.IntrNoVideoHandler( + InstancePtr->RxInstance.IntrNoVideoCallbackRef); + } + /* A valid video frame is detected on the main link. */ + else if (IntrVideo) { + InstancePtr->RxInstance.IntrVideoHandler( + InstancePtr->RxInstance.IntrVideoCallbackRef); + } + + /* The transmitter has requested a change in the current power state of + * the receiver core. */ + if (IntrPowerState) { + InstancePtr->RxInstance.IntrPowerStateHandler( + InstancePtr->RxInstance.IntrPowerStateCallbackRef); + } + /* A change in the bandwidth has been detected. */ + if (IntrBwChange) { + InstancePtr->RxInstance.IntrBwChangeHandler( + InstancePtr->RxInstance.IntrBwChangeCallbackRef); + } } diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdptx_mst.c b/XilinxProcessorIPLib/drivers/dp/src/xdp_mst.c similarity index 81% rename from XilinxProcessorIPLib/drivers/dp/src/xdptx_mst.c rename to XilinxProcessorIPLib/drivers/dp/src/xdp_mst.c index fff48d1d..934f2c6a 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdptx_mst.c +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp_mst.c @@ -1,6 +1,6 @@ /******************************************************************************* * - * Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,23 +32,14 @@ /******************************************************************************/ /** * - * @file xdptx_mst.c + * @file xdp_mst.c * *
  * MODIFICATION HISTORY:
  *
  * Ver   Who  Date     Changes
  * ----- ---- -------- -----------------------------------------------
- * 1.0   als  08/03/14 Initial release.
- * 2.0   als  09/21/14 Improvements to topology discovery and sideband messages.
- * 3.0   als  12/16/14 Updated to use common video library.
- *                     Stream naming now starts at 1 to follow IP.
- *                     Added topology reordering functions:
- *                         XDptx_TopologySwapSinks,
- *                         XDptx_TopologySortSinksByTiling
- *                     Added wrapper functions for remote DPCD/I2C read/writes:
- *                         XDptx_RemoteDpcdRead, XDptx_RemoteDpcdWrite,
- *                         XDptx_RemoteIicRead, XDptx_RemoteIicWrite
+ * 1.0   als  01/20/15 Initial release.
  * 
* *******************************************************************************/ @@ -56,17 +47,16 @@ /******************************* Include Files ********************************/ #include "string.h" -#include "xdptx.h" -#include "xstatus.h" +#include "xdp.h" /**************************** Constant Definitions ****************************/ /* Error out if waiting for a sideband message reply or waiting for the payload * ID table to be updated takes more than 5000 AUX read iterations. */ -#define XDPTX_MAX_SBMSG_REPLY_TIMEOUT_COUNT 5000 +#define XDP_TX_MAX_SBMSG_REPLY_TIMEOUT_COUNT 5000 /* Error out if waiting for the RX device to indicate that it has received an * ACT trigger takes more than 30 AUX read iterations. */ -#define XDPTX_VCP_TABLE_MAX_TIMEOUT_COUNT 30 +#define XDP_TX_VCP_TABLE_MAX_TIMEOUT_COUNT 30 /****************************** Type Definitions ******************************/ @@ -110,7 +100,7 @@ typedef struct u8 MsgHeaderLength; /**< The number of data bytes stored as part of the sideband message header. */ -} XDptx_SidebandMsgHeader; +} XDp_SidebandMsgHeader; /** * This typedef stores the sideband message body. @@ -124,18 +114,18 @@ typedef struct body. */ u8 Crc; /**< The cyclic-redundancy check (CRC) value of the body data. */ -} XDptx_SidebandMsgBody; +} XDp_SidebandMsgBody; /** * This typedef stores the entire sideband message. */ typedef struct { - XDptx_SidebandMsgHeader Header; /**< The header segment of the sideband + XDp_SidebandMsgHeader Header; /**< The header segment of the sideband message. */ - XDptx_SidebandMsgBody Body; /**< The body segment of the sideband + XDp_SidebandMsgBody Body; /**< The body segment of the sideband message. */ -} XDptx_SidebandMsg; +} XDp_SidebandMsg; /** * This typedef describes a sideband message reply. @@ -145,39 +135,39 @@ typedef struct u8 Length; /**< The number of bytes of reply data. */ u8 Data[256]; /**< The raw reply data. */ -} XDptx_SidebandReply; +} XDp_SidebandReply; /**************************** Function Prototypes *****************************/ -static void XDptx_IssueGuid(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress, XDptx_Topology *Topology, +static void XDp_TxIssueGuid(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress, XDp_TxTopology *Topology, u32 *Guid); -static void XDptx_AddBranchToList(XDptx *InstancePtr, - XDptx_SbMsgLinkAddressReplyDeviceInfo *DeviceInfo, +static void XDp_TxAddBranchToList(XDp *InstancePtr, + XDp_TxSbMsgLinkAddressReplyDeviceInfo *DeviceInfo, u8 LinkCountTotal, u8 *RelativeAddress); -static void XDptx_AddSinkToList(XDptx *InstancePtr, - XDptx_SbMsgLinkAddressReplyPortDetail *SinkDevice, +static void XDp_TxAddSinkToList(XDp *InstancePtr, + XDp_TxSbMsgLinkAddressReplyPortDetail *SinkDevice, u8 LinkCountTotal, u8 *RelativeAddress); -static void XDptx_GetDeviceInfoFromSbMsgLinkAddress( - XDptx_SidebandReply *SbReply, - XDptx_SbMsgLinkAddressReplyDeviceInfo *FormatReply); -static u32 XDptx_GetFirstAvailableTs(XDptx *InstancePtr, u8 *FirstTs); -static u32 XDptx_SendActTrigger(XDptx *InstancePtr); -static u32 XDptx_SendSbMsg(XDptx *InstancePtr, XDptx_SidebandMsg *Msg); -static u32 XDptx_ReceiveSbMsg(XDptx *InstancePtr, XDptx_SidebandReply *SbReply); -static u32 XDptx_WaitSbReply(XDptx *InstancePtr); -static u32 XDptx_Transaction2MsgFormat(u8 *Transaction, XDptx_SidebandMsg *Msg); -static u8 XDptx_Crc4CalculateHeader(XDptx_SidebandMsgHeader *Header); -static u8 XDptx_Crc8CalculateBody(XDptx_SidebandMsgBody *Body); -static u8 XDptx_CrcCalculate(const u8 *Data, u32 NumberOfBits, u8 Polynomial); -static u32 XDptx_IsSameTileDisplay(u8 *DispIdSecTile0, u8 *DispIdSecTile1); +static void XDp_TxGetDeviceInfoFromSbMsgLinkAddress( + XDp_SidebandReply *SbReply, + XDp_TxSbMsgLinkAddressReplyDeviceInfo *FormatReply); +static u32 XDp_TxGetFirstAvailableTs(XDp *InstancePtr, u8 *FirstTs); +static u32 XDp_TxSendActTrigger(XDp *InstancePtr); +static u32 XDp_TxSendSbMsg(XDp *InstancePtr, XDp_SidebandMsg *Msg); +static u32 XDp_TxReceiveSbMsg(XDp *InstancePtr, XDp_SidebandReply *SbReply); +static u32 XDp_TxWaitSbReply(XDp *InstancePtr); +static u32 XDp_TxTransaction2MsgFormat(u8 *Transaction, XDp_SidebandMsg *Msg); +static u8 XDp_TxCrc4CalculateHeader(XDp_SidebandMsgHeader *Header); +static u8 XDp_TxCrc8CalculateBody(XDp_SidebandMsgBody *Body); +static u8 XDp_TxCrcCalculate(const u8 *Data, u32 NumberOfBits, u8 Polynomial); +static u32 XDp_TxIsSameTileDisplay(u8 *DispIdSecTile0, u8 *DispIdSecTile1); /**************************** Variable Definitions ****************************/ /** * This table contains a list of global unique identifiers (GUIDs) that will be * issued when exploring the topology using the algorithm in the - * XDptx_FindAccessibleDpDevices function. + * XDp_TxFindAccessibleDpDevices function. */ u32 GuidTable[16][4] = { {0x12341234, 0x43214321, 0x56785678, 0x87658765}, @@ -204,26 +194,26 @@ u32 GuidTable[16][4] = { /** * This function will enable multi-stream transport (MST) mode for the driver. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * * @note None. * *******************************************************************************/ -void XDptx_MstCfgModeEnable(XDptx *InstancePtr) +void XDp_TxMstCfgModeEnable(XDp *InstancePtr) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - InstancePtr->MstEnable = 1; + InstancePtr->TxInstance.MstEnable = 1; } /******************************************************************************/ /** * This function will disable multi-stream transport (MST) mode for the driver. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * @@ -231,12 +221,12 @@ void XDptx_MstCfgModeEnable(XDptx *InstancePtr) * (SST) mode. * *******************************************************************************/ -void XDptx_MstCfgModeDisable(XDptx *InstancePtr) +void XDp_TxMstCfgModeDisable(XDp *InstancePtr) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - InstancePtr->MstEnable = 0; + InstancePtr->TxInstance.MstEnable = 0; } /******************************************************************************/ @@ -246,7 +236,7 @@ void XDptx_MstCfgModeDisable(XDptx *InstancePtr) * version of 1.2 or higher is required and the MST capability bit in the DPCD * must be set for this function to return XST_SUCCESS. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if the RX device is MST capable. @@ -258,7 +248,7 @@ void XDptx_MstCfgModeDisable(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -u32 XDptx_MstCapable(XDptx *InstancePtr) +u32 XDp_TxMstCapable(XDp *InstancePtr) { u32 Status; u8 AuxData; @@ -274,7 +264,7 @@ u32 XDptx_MstCapable(XDptx *InstancePtr) /* Check that the RX device has a DisplayPort Configuration Data (DPCD) * version greater than or equal to 1.2 to be able to support MST * functionality. */ - Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_REV, 1, &AuxData); + Status = XDp_TxAuxRead(InstancePtr, XDP_DPCD_REV, 1, &AuxData); if (Status != XST_SUCCESS) { /* The AUX read transaction failed. */ return Status; @@ -284,13 +274,13 @@ u32 XDptx_MstCapable(XDptx *InstancePtr) } /* Check if the RX device has MST capabilities.. */ - Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_MSTM_CAP, 1, &AuxData); + Status = XDp_TxAuxRead(InstancePtr, XDP_DPCD_MSTM_CAP, 1, &AuxData); if (Status != XST_SUCCESS) { /* The AUX read transaction failed. */ return Status; } - else if ((AuxData & XDPTX_DPCD_MST_CAP_MASK) != - XDPTX_DPCD_MST_CAP_MASK) { + else if ((AuxData & XDP_DPCD_MST_CAP_MASK) != + XDP_DPCD_MST_CAP_MASK) { return XST_NO_FEATURE; } @@ -302,7 +292,7 @@ u32 XDptx_MstCapable(XDptx *InstancePtr) * This function will enable multi-stream transport (MST) mode in both the * DisplayPort TX and the immediate downstream RX device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if MST mode has been successful enabled in @@ -319,7 +309,7 @@ u32 XDptx_MstCapable(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -u32 XDptx_MstEnable(XDptx *InstancePtr) +u32 XDp_TxMstEnable(XDp *InstancePtr) { u32 Status; u8 AuxData; @@ -329,7 +319,7 @@ u32 XDptx_MstEnable(XDptx *InstancePtr) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); /* Check if the immediate downstream RX device has MST capabilities. */ - Status = XDptx_MstCapable(InstancePtr); + Status = XDp_TxMstCapable(InstancePtr); if (Status != XST_SUCCESS) { /* The RX device is not downstream capable. */ return Status; @@ -337,7 +327,7 @@ u32 XDptx_MstEnable(XDptx *InstancePtr) /* HPD long pulse used for upstream notification. */ AuxData = 0; - Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_BRANCH_DEVICE_CTRL, 1, + Status = XDp_TxAuxWrite(InstancePtr, XDP_DPCD_BRANCH_DEVICE_CTRL, 1, &AuxData); if (Status != XST_SUCCESS) { /* The AUX write transaction failed. */ @@ -346,19 +336,19 @@ u32 XDptx_MstEnable(XDptx *InstancePtr) /* Enable MST in the immediate branch device and tell it that its * upstream device is a source (the DisplayPort TX). */ - AuxData = XDPTX_DPCD_UP_IS_SRC_MASK | XDPTX_DPCD_UP_REQ_EN_MASK | - XDPTX_DPCD_MST_EN_MASK; - Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_MSTM_CTRL, 1, &AuxData); + AuxData = XDP_DPCD_UP_IS_SRC_MASK | XDP_DPCD_UP_REQ_EN_MASK | + XDP_DPCD_MST_EN_MASK; + Status = XDp_TxAuxWrite(InstancePtr, XDP_DPCD_MSTM_CTRL, 1, &AuxData); if (Status != XST_SUCCESS) { /* The AUX write transaction failed. */ return Status; } /* Enable MST in the DisplayPort TX. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_MST_CONFIG, - XDPTX_TX_MST_CONFIG_MST_EN_MASK); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_MST_CONFIG, + XDP_TX_MST_CONFIG_MST_EN_MASK); - XDptx_MstCfgModeEnable(InstancePtr); + XDp_TxMstCfgModeEnable(InstancePtr); return XST_SUCCESS; } @@ -368,7 +358,7 @@ u32 XDptx_MstEnable(XDptx *InstancePtr) * This function will disable multi-stream transport (MST) mode in both the * DisplayPort TX and the immediate downstream RX device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if MST mode has been successful disabled in @@ -380,7 +370,7 @@ u32 XDptx_MstEnable(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -u32 XDptx_MstDisable(XDptx *InstancePtr) +u32 XDp_TxMstDisable(XDp *InstancePtr) { u32 Status; u8 AuxData; @@ -391,16 +381,16 @@ u32 XDptx_MstDisable(XDptx *InstancePtr) /* Disable MST mode in the immediate branch device. */ AuxData = 0; - Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_MSTM_CTRL, 1, &AuxData); + Status = XDp_TxAuxWrite(InstancePtr, XDP_DPCD_MSTM_CTRL, 1, &AuxData); if (Status != XST_SUCCESS) { /* The AUX write transaction failed. */ return Status; } /* Disable MST mode in the DisplayPort TX. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_MST_CONFIG, 0x0); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_MST_CONFIG, 0x0); - XDptx_MstCfgModeDisable(InstancePtr); + XDp_TxMstCfgModeDisable(InstancePtr); return XST_SUCCESS; } @@ -409,7 +399,7 @@ u32 XDptx_MstDisable(XDptx *InstancePtr) /** * This function will check whether * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Stream is the stream ID to check for enable/disable status. * * @return @@ -419,23 +409,24 @@ u32 XDptx_MstDisable(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -u8 XDptx_MstStreamIsEnabled(XDptx *InstancePtr, u8 Stream) +u8 XDp_TxMstStreamIsEnabled(XDp *InstancePtr, u8 Stream) { /* Verify arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertNonvoid((Stream == XDP_TX_STREAM_ID1) || + (Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) || + (Stream == XDP_TX_STREAM_ID4)); - return InstancePtr->MstStreamConfig[Stream - 1].MstStreamEnable; + return InstancePtr->TxInstance. + MstStreamConfig[Stream - 1].MstStreamEnable; } /******************************************************************************/ /** - * This function will configure the InstancePtr->MstStreamConfig structure to - * enable the specified stream. + * This function will configure the InstancePtr->TxInstance.MstStreamConfig + * structure to enable the specified stream. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Stream is the stream ID that will be enabled. * * @return None. @@ -443,23 +434,23 @@ u8 XDptx_MstStreamIsEnabled(XDptx *InstancePtr, u8 Stream) * @note None. * *******************************************************************************/ -void XDptx_MstCfgStreamEnable(XDptx *InstancePtr, u8 Stream) +void XDp_TxMstCfgStreamEnable(XDp *InstancePtr, u8 Stream) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) || + (Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) || + (Stream == XDP_TX_STREAM_ID4)); - InstancePtr->MstStreamConfig[Stream - 1].MstStreamEnable = 1; + InstancePtr->TxInstance.MstStreamConfig[Stream - 1].MstStreamEnable = 1; } /******************************************************************************/ /** - * This function will configure the InstancePtr->MstStreamConfig structure to - * disable the specified stream. + * This function will configure the InstancePtr->TxInstance.MstStreamConfig + * structure to disable the specified stream. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Stream is the stream ID that will be disabled. * * @return None. @@ -467,23 +458,23 @@ void XDptx_MstCfgStreamEnable(XDptx *InstancePtr, u8 Stream) * @note None. * *******************************************************************************/ -void XDptx_MstCfgStreamDisable(XDptx *InstancePtr, u8 Stream) +void XDp_TxMstCfgStreamDisable(XDp *InstancePtr, u8 Stream) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) || + (Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) || + (Stream == XDP_TX_STREAM_ID4)); - InstancePtr->MstStreamConfig[Stream - 1].MstStreamEnable = 0; + InstancePtr->TxInstance.MstStreamConfig[Stream - 1].MstStreamEnable = 0; } /******************************************************************************/ /** * This function will map a stream to a downstream DisplayPort TX device that is - * associated with a sink from the InstancePtr->Topology.SinkList. + * associated with a sink from the InstancePtr->TxInstance.Topology.SinkList. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Stream is the stream ID that will be mapped to a DisplayPort * device. * @param SinkNum is the sink ID in the sink list that will be mapped to @@ -491,27 +482,27 @@ void XDptx_MstCfgStreamDisable(XDptx *InstancePtr, u8 Stream) * * @return None. * - * @note The contents of the InstancePtr->MstStreamConfig[Stream] will be - * modified. + * @note The contents of the InstancePtr->TxInstance. + * MstStreamConfig[Stream] will be modified. * @note The topology will need to be determined prior to calling this - * function using the XDptx_FindAccessibleDpDevices. + * function using the XDp_TxFindAccessibleDpDevices. * *******************************************************************************/ -void XDptx_SetStreamSelectFromSinkList(XDptx *InstancePtr, u8 Stream, u8 +void XDp_TxSetStreamSelectFromSinkList(XDp *InstancePtr, u8 Stream, u8 SinkNum) { u8 Index; - XDptx_MstStream *MstStream; - XDptx_Topology *Topology; + XDp_TxMstStream *MstStream; + XDp_TxTopology *Topology; /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) || + (Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) || + (Stream == XDP_TX_STREAM_ID4)); - MstStream = &InstancePtr->MstStreamConfig[Stream - 1]; - Topology = &InstancePtr->Topology; + MstStream = &InstancePtr->TxInstance.MstStreamConfig[Stream - 1]; + Topology = &InstancePtr->TxInstance.Topology; MstStream->LinkCountTotal = Topology->SinkList[SinkNum]->LinkCountTotal; for (Index = 0; Index < MstStream->LinkCountTotal - 1; Index++) { @@ -525,7 +516,7 @@ void XDptx_SetStreamSelectFromSinkList(XDptx *InstancePtr, u8 Stream, u8 * This function will map a stream to a downstream DisplayPort TX device * determined by the relative address. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Stream is the stream number that will be mapped to a DisplayPort * device. * @param LinkCountTotal is the total DisplayPort links connecting the @@ -535,25 +526,25 @@ void XDptx_SetStreamSelectFromSinkList(XDptx *InstancePtr, u8 Stream, u8 * * @return None. * - * @note The contents of the InstancePtr->MstStreamConfig[Stream] will be - * modified. + * @note The contents of the InstancePtr->TxInstance. + * MstStreamConfig[Stream] will be modified. * *******************************************************************************/ -void XDptx_SetStreamSinkRad(XDptx *InstancePtr, u8 Stream, u8 LinkCountTotal, +void XDp_TxSetStreamSinkRad(XDp *InstancePtr, u8 Stream, u8 LinkCountTotal, u8 *RelativeAddress) { u8 Index; - XDptx_MstStream *MstStream; + XDp_TxMstStream *MstStream; /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) || + (Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) || + (Stream == XDP_TX_STREAM_ID4)); Xil_AssertVoid(LinkCountTotal > 0); Xil_AssertVoid(RelativeAddress != NULL); - MstStream = &InstancePtr->MstStreamConfig[Stream - 1]; + MstStream = &InstancePtr->TxInstance.MstStreamConfig[Stream - 1]; MstStream->LinkCountTotal = LinkCountTotal; for (Index = 0; Index < MstStream->LinkCountTotal - 1; Index++) { @@ -571,22 +562,22 @@ void XDptx_SetStreamSinkRad(XDptx *InstancePtr, u8 Stream, u8 LinkCountTotal, * the details of the sink, add it to the topology's node table, as well as * add it to the topology's sink list. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if the topology discovery is successful. * - XST_FAILURE otherwise - if sending a LINK_ADDRESS sideband * message to one of the branch devices in the topology failed. * - * @note The contents of the InstancePtr->Topology structure will be - * modified. + * @note The contents of the InstancePtr->TxInstance.Topology structure + * will be modified. * *******************************************************************************/ -u32 XDptx_DiscoverTopology(XDptx *InstancePtr) +u32 XDp_TxDiscoverTopology(XDp *InstancePtr) { u8 RelativeAddress[15]; - return XDptx_FindAccessibleDpDevices(InstancePtr, 1, RelativeAddress); + return XDp_TxFindAccessibleDpDevices(InstancePtr, 1, RelativeAddress); } /******************************************************************************/ @@ -600,7 +591,7 @@ u32 XDptx_DiscoverTopology(XDptx *InstancePtr) * the details of the sink, add it to the topology's node table, as well as * add it to the topology's sink list. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkCountTotal is the total DisplayPort links connecting the * DisplayPort TX to the current downstream device in the * recursion. @@ -613,20 +604,20 @@ u32 XDptx_DiscoverTopology(XDptx *InstancePtr) * - XST_FAILURE otherwise - if sending a LINK_ADDRESS sideband * message to one of the branch devices in the topology failed. * - * @note The contents of the InstancePtr->Topology structure will be - * modified. + * @note The contents of the InstancePtr->TxInstance.Topology structure + * will be modified. * *******************************************************************************/ -u32 XDptx_FindAccessibleDpDevices(XDptx *InstancePtr, u8 LinkCountTotal, +u32 XDp_TxFindAccessibleDpDevices(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress) { u32 Status; u8 Index; u8 NumDownBranches = 0; u8 OverallFailures = 0; - XDptx_Topology *Topology; - XDptx_SbMsgLinkAddressReplyPortDetail *PortDetails; - static XDptx_SbMsgLinkAddressReplyDeviceInfo DeviceInfo; + XDp_TxTopology *Topology; + XDp_TxSbMsgLinkAddressReplyPortDetail *PortDetails; + static XDp_TxSbMsgLinkAddressReplyDeviceInfo DeviceInfo; /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); @@ -634,11 +625,11 @@ u32 XDptx_FindAccessibleDpDevices(XDptx *InstancePtr, u8 LinkCountTotal, Xil_AssertVoid(LinkCountTotal > 0); Xil_AssertVoid((RelativeAddress != NULL) || (LinkCountTotal == 1)); - Topology = &InstancePtr->Topology; + Topology = &InstancePtr->TxInstance.Topology; /* Send a LINK_ADDRESS sideband message to the branch device in order to * obtain information on it and its downstream devices. */ - Status = XDptx_SendSbMsgLinkAddress(InstancePtr, LinkCountTotal, + Status = XDp_TxSendSbMsgLinkAddress(InstancePtr, LinkCountTotal, RelativeAddress, &DeviceInfo); if (Status != XST_SUCCESS) { /* The LINK_ADDRESS was sent to a device that cannot reply; exit @@ -647,11 +638,11 @@ u32 XDptx_FindAccessibleDpDevices(XDptx *InstancePtr, u8 LinkCountTotal, } /* Write GUID to the branch device if it doesn't already have one. */ - XDptx_IssueGuid(InstancePtr, LinkCountTotal, RelativeAddress, Topology, + XDp_TxIssueGuid(InstancePtr, LinkCountTotal, RelativeAddress, Topology, DeviceInfo.Guid); /* Add the branch device to the topology table. */ - XDptx_AddBranchToList(InstancePtr, &DeviceInfo, LinkCountTotal, + XDp_TxAddBranchToList(InstancePtr, &DeviceInfo, LinkCountTotal, RelativeAddress); /* Downstream devices will be an extra link away from the source than @@ -673,12 +664,12 @@ u32 XDptx_FindAccessibleDpDevices(XDptx *InstancePtr, u8 LinkCountTotal, (PortDetails->DpcdRev >= 0x12)) { /* Write GUID to the branch device if it * doesn't already have one. */ - XDptx_IssueGuid(InstancePtr, + XDp_TxIssueGuid(InstancePtr, LinkCountTotal, RelativeAddress, Topology, PortDetails->Guid); } - XDptx_AddSinkToList(InstancePtr, PortDetails, + XDp_TxAddSinkToList(InstancePtr, PortDetails, LinkCountTotal, RelativeAddress); } @@ -699,7 +690,7 @@ u32 XDptx_FindAccessibleDpDevices(XDptx *InstancePtr, u8 LinkCountTotal, /* Found a branch device; recurse the algorithm to see what * DisplayPort devices are connected to it with the appended * RAD. */ - Status = XDptx_FindAccessibleDpDevices(InstancePtr, + Status = XDp_TxFindAccessibleDpDevices(InstancePtr, LinkCountTotal, RelativeAddress); if (Status != XST_SUCCESS) { /* Keep trying to discover the topology, but the top @@ -723,7 +714,7 @@ u32 XDptx_FindAccessibleDpDevices(XDptx *InstancePtr, u8 LinkCountTotal, * is so that functions that use the sink list will act on the sinks in a * different order. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Index0 is the sink list's index of one of the sink pointers to * be swapped. * @param Index1 is the sink list's index of the other sink pointer to be @@ -734,20 +725,21 @@ u32 XDptx_FindAccessibleDpDevices(XDptx *InstancePtr, u8 LinkCountTotal, * @note None. * *******************************************************************************/ -void XDptx_TopologySwapSinks(XDptx *InstancePtr, u8 Index0, u8 Index1) +void XDp_TxTopologySwapSinks(XDp *InstancePtr, u8 Index0, u8 Index1) { - XDptx_TopologyNode *TmpSink = InstancePtr->Topology.SinkList[Index0]; + XDp_TxTopologyNode *TmpSink = + InstancePtr->TxInstance.Topology.SinkList[Index0]; - InstancePtr->Topology.SinkList[Index0] = - InstancePtr->Topology.SinkList[Index1]; + InstancePtr->TxInstance.Topology.SinkList[Index0] = + InstancePtr->TxInstance.Topology.SinkList[Index1]; - InstancePtr->Topology.SinkList[Index1] = TmpSink; + InstancePtr->TxInstance.Topology.SinkList[Index1] = TmpSink; } /******************************************************************************/ /** * Order the sink list with all sinks of the same tiled display being sorted by - * 'tile order'. Refer to the XDptx_GetDispIdTdtTileOrder macro on how to + * 'tile order'. Refer to the XDp_TxGetDispIdTdtTileOrder macro on how to * determine the 'tile order'. Sinks of a tiled display will have an index in * the sink list that is lower than all indices of other sinks within that same * tiled display that have a greater 'tile order'. @@ -757,17 +749,17 @@ void XDptx_TopologySwapSinks(XDptx *InstancePtr, u8 Index0, u8 Index1) * order' will be acted upon first relative to the other sinks in the same tiled * display. Multiple tiled displays may exist in the sink list. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return None. * * @note None. * *******************************************************************************/ -void XDptx_TopologySortSinksByTiling(XDptx *InstancePtr) +void XDp_TxTopologySortSinksByTiling(XDp *InstancePtr) { u32 Status; - XDptx_TopologyNode *CurrSink, *CmpSink; + XDp_TxTopologyNode *CurrSink, *CmpSink; u8 CurrIndex, CmpIndex, NewIndex; u8 CurrEdidExt[128], CmpEdidExt[128]; u8 *CurrTdt, *CmpTdt; @@ -775,10 +767,11 @@ void XDptx_TopologySortSinksByTiling(XDptx *InstancePtr) u8 SameTileDispCount, SameTileDispNum; for (CurrIndex = 0; CurrIndex < - (InstancePtr->Topology.SinkTotal - 1); CurrIndex++) { - CurrSink = InstancePtr->Topology.SinkList[CurrIndex]; + (InstancePtr->TxInstance.Topology.SinkTotal - 1); + CurrIndex++) { + CurrSink = InstancePtr->TxInstance.Topology.SinkList[CurrIndex]; - Status = XDptx_GetRemoteTiledDisplayDb(InstancePtr, CurrEdidExt, + Status = XDp_TxGetRemoteTiledDisplayDb(InstancePtr, CurrEdidExt, CurrSink->LinkCountTotal, CurrSink->RelativeAddress, &CurrTdt); if (Status != XST_SUCCESS) { @@ -788,22 +781,24 @@ void XDptx_TopologySortSinksByTiling(XDptx *InstancePtr) /* Start by using the tiling parameters of the current sink * index. */ - CurrTileOrder = XDptx_GetDispIdTdtTileOrder(CurrTdt); + CurrTileOrder = XDp_TxGetDispIdTdtTileOrder(CurrTdt); NewIndex = CurrIndex; SameTileDispCount = 1; - SameTileDispNum = XDptx_GetDispIdTdtNumTiles(CurrTdt); + SameTileDispNum = XDp_TxGetDispIdTdtNumTiles(CurrTdt); /* Try to find a sink that is part of the same tiled display, * but has a smaller tile location - the sink with a smallest * tile location should be ordered first in the topology's sink * list. */ for (CmpIndex = (CurrIndex + 1); - (CmpIndex < InstancePtr->Topology.SinkTotal) + (CmpIndex < + InstancePtr->TxInstance.Topology.SinkTotal) && (SameTileDispCount < SameTileDispNum); CmpIndex++) { - CmpSink = InstancePtr->Topology.SinkList[CmpIndex]; + CmpSink = InstancePtr->TxInstance.Topology.SinkList[ + CmpIndex]; - Status = XDptx_GetRemoteTiledDisplayDb( + Status = XDp_TxGetRemoteTiledDisplayDb( InstancePtr, CmpEdidExt, CmpSink->LinkCountTotal, CmpSink->RelativeAddress, &CmpTdt); @@ -812,7 +807,7 @@ void XDptx_TopologySortSinksByTiling(XDptx *InstancePtr) continue; } - if (!XDptx_IsSameTileDisplay(CurrTdt, CmpTdt)) { + if (!XDp_TxIsSameTileDisplay(CurrTdt, CmpTdt)) { /* The sink under comparison does not belong to * the same tiled display. */ continue; @@ -821,7 +816,7 @@ void XDptx_TopologySortSinksByTiling(XDptx *InstancePtr) /* Keep track of the sink with a tile location that * should be ordered first out of the remaining sinks * that are part of the same tiled display. */ - CmpTileOrder = XDptx_GetDispIdTdtTileOrder(CmpTdt); + CmpTileOrder = XDp_TxGetDispIdTdtTileOrder(CmpTdt); if (CurrTileOrder > CmpTileOrder) { CurrTileOrder = CmpTileOrder; NewIndex = CmpIndex; @@ -833,7 +828,7 @@ void XDptx_TopologySortSinksByTiling(XDptx *InstancePtr) * part of the same tiled display, but has a smaller tile * location. */ if (CurrIndex != NewIndex) { - XDptx_TopologySwapSinks(InstancePtr, CurrIndex, + XDp_TxTopologySwapSinks(InstancePtr, CurrIndex, NewIndex); } } @@ -847,7 +842,7 @@ void XDptx_TopologySortSinksByTiling(XDptx *InstancePtr) * The read message will be divided into multiple transactions which read a * maximum of 16 bytes each. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkCountTotal is the number of DisplayPort links from the * DisplayPort source to the target DisplayPort device. * @param RelativeAddress is the relative address from the DisplayPort @@ -873,14 +868,14 @@ void XDptx_TopologySortSinksByTiling(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -u32 XDptx_RemoteDpcdRead(XDptx *InstancePtr, u8 LinkCountTotal, +u32 XDp_TxRemoteDpcdRead(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData) { u32 Status; /* Target RX device is immediately connected to the TX. */ if (LinkCountTotal == 1) { - Status = XDptx_AuxRead(InstancePtr, DpcdAddress, BytesToRead, + Status = XDp_TxAuxRead(InstancePtr, DpcdAddress, BytesToRead, ReadData); return Status; } @@ -900,7 +895,7 @@ u32 XDptx_RemoteDpcdRead(XDptx *InstancePtr, u8 LinkCountTotal, } /* Send remote DPCD read sideband message. */ - Status = XDptx_SendSbMsgRemoteDpcdRead(InstancePtr, + Status = XDp_TxSendSbMsgRemoteDpcdRead(InstancePtr, LinkCountTotal, RelativeAddress, DpcdAddress, CurrBytesToRead, ReadData); if (Status != XST_SUCCESS) { @@ -930,7 +925,7 @@ u32 XDptx_RemoteDpcdRead(XDptx *InstancePtr, u8 LinkCountTotal, * The write message will be divided into multiple transactions which write a * maximum of 16 bytes each. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkCountTotal is the number of DisplayPort links from the * DisplayPort source to the target DisplayPort device. * @param RelativeAddress is the relative address from the DisplayPort @@ -956,14 +951,14 @@ u32 XDptx_RemoteDpcdRead(XDptx *InstancePtr, u8 LinkCountTotal, * @note None. * *******************************************************************************/ -u32 XDptx_RemoteDpcdWrite(XDptx *InstancePtr, u8 LinkCountTotal, +u32 XDp_TxRemoteDpcdWrite(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData) { u32 Status; /* Target RX device is immediately connected to the TX. */ if (LinkCountTotal == 1) { - Status = XDptx_AuxWrite(InstancePtr, DpcdAddress, BytesToWrite, + Status = XDp_TxAuxWrite(InstancePtr, DpcdAddress, BytesToWrite, WriteData); return Status; } @@ -983,7 +978,7 @@ u32 XDptx_RemoteDpcdWrite(XDptx *InstancePtr, u8 LinkCountTotal, } /* Send remote DPCD write sideband message. */ - Status = XDptx_SendSbMsgRemoteDpcdWrite(InstancePtr, + Status = XDp_TxSendSbMsgRemoteDpcdWrite(InstancePtr, LinkCountTotal, RelativeAddress, DpcdAddress, CurrBytesToWrite, WriteData); if (Status != XST_SUCCESS) { @@ -1019,7 +1014,7 @@ u32 XDptx_RemoteDpcdWrite(XDptx *InstancePtr, u8 LinkCountTotal, * - 512, an I2C read is done on segptr=2; offset=0. * - etc. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkCountTotal is the number of DisplayPort links from the * DisplayPort source to the target DisplayPort device. * @param RelativeAddress is the relative address from the DisplayPort @@ -1047,7 +1042,7 @@ u32 XDptx_RemoteDpcdWrite(XDptx *InstancePtr, u8 LinkCountTotal, * @note None. * *******************************************************************************/ -u32 XDptx_RemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, +u32 XDp_TxRemoteIicRead(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u16 Offset, u16 BytesToRead, u8 *ReadData) { @@ -1055,7 +1050,7 @@ u32 XDptx_RemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, /* Target RX device is immediately connected to the TX. */ if (LinkCountTotal == 1) { - Status = XDptx_IicRead(InstancePtr, IicAddress, Offset, + Status = XDp_TxIicRead(InstancePtr, IicAddress, Offset, BytesToRead, ReadData); return Status; } @@ -1074,8 +1069,8 @@ u32 XDptx_RemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, NumBytesLeftInSeg = 256 - Offset; /* Set the segment pointer to 0. */ - Status = XDptx_RemoteIicWrite(InstancePtr, LinkCountTotal, - RelativeAddress, XDPTX_SEGPTR_ADDR, 1, &SegPtr); + Status = XDp_TxRemoteIicWrite(InstancePtr, LinkCountTotal, + RelativeAddress, XDP_SEGPTR_ADDR, 1, &SegPtr); if (Status != XST_SUCCESS) { return Status; } @@ -1096,7 +1091,7 @@ u32 XDptx_RemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, } /* Send remote I2C read sideband message. */ - Status = XDptx_SendSbMsgRemoteIicRead(InstancePtr, + Status = XDp_TxSendSbMsgRemoteIicRead(InstancePtr, LinkCountTotal, RelativeAddress, IicAddress, Offset, BytesLeft, ReadData); if (Status != XST_SUCCESS) { @@ -1122,9 +1117,9 @@ u32 XDptx_RemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, Offset %= 256; NumBytesLeftInSeg = 256; - Status = XDptx_RemoteIicWrite(InstancePtr, + Status = XDp_TxRemoteIicWrite(InstancePtr, LinkCountTotal, RelativeAddress, - XDPTX_SEGPTR_ADDR, 1, &SegPtr); + XDP_SEGPTR_ADDR, 1, &SegPtr); if (Status != XST_SUCCESS) { return Status; } @@ -1133,8 +1128,8 @@ u32 XDptx_RemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, /* Reset the segment pointer to 0. */ SegPtr = 0; - Status = XDptx_RemoteIicWrite(InstancePtr, LinkCountTotal, - RelativeAddress, XDPTX_SEGPTR_ADDR, 1, &SegPtr); + Status = XDp_TxRemoteIicWrite(InstancePtr, LinkCountTotal, + RelativeAddress, XDP_SEGPTR_ADDR, 1, &SegPtr); return Status; } @@ -1145,7 +1140,7 @@ u32 XDptx_RemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, * case message is directed at the RX device connected immediately to the TX, * the message is sent over the AUX channel. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkCountTotal is the number of DisplayPort links from the * DisplayPort source to the target DisplayPort device. * @param RelativeAddress is the relative address from the DisplayPort @@ -1171,7 +1166,7 @@ u32 XDptx_RemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, * @note None. * *******************************************************************************/ -u32 XDptx_RemoteIicWrite(XDptx *InstancePtr, u8 LinkCountTotal, +u32 XDp_TxRemoteIicWrite(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u8 BytesToWrite, u8 *WriteData) { @@ -1179,12 +1174,12 @@ u32 XDptx_RemoteIicWrite(XDptx *InstancePtr, u8 LinkCountTotal, /* Target RX device is immediately connected to the TX. */ if (LinkCountTotal == 1) { - Status = XDptx_IicWrite(InstancePtr, IicAddress, BytesToWrite, + Status = XDp_TxIicWrite(InstancePtr, IicAddress, BytesToWrite, WriteData); } /* Send remote I2C sideband message. */ else { - Status = XDptx_SendSbMsgRemoteIicWrite(InstancePtr, + Status = XDp_TxSendSbMsgRemoteIicWrite(InstancePtr, LinkCountTotal, RelativeAddress, IicAddress, BytesToWrite, WriteData); } @@ -1196,7 +1191,7 @@ u32 XDptx_RemoteIicWrite(XDptx *InstancePtr, u8 LinkCountTotal, /** * This function will allocate bandwidth for all enabled stream. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if the payload ID tables were successfully updated @@ -1215,12 +1210,12 @@ u32 XDptx_RemoteIicWrite(XDptx *InstancePtr, u8 LinkCountTotal, * @note None. * *******************************************************************************/ -u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr) +u32 XDp_TxAllocatePayloadStreams(XDp *InstancePtr) { u32 Status; u8 StreamIndex; - XDptx_MstStream *MstStream; - XDptx_MainStreamAttributes *MsaConfig; + XDp_TxMstStream *MstStream; + XDp_TxMainStreamAttributes *MsaConfig; /* Verify arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); @@ -1229,11 +1224,13 @@ u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr) /* Allocate the payload table for each stream in both the DisplayPort TX * and RX device. */ for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) { - MstStream = &InstancePtr->MstStreamConfig[StreamIndex]; - MsaConfig = &InstancePtr->MsaConfig[StreamIndex]; + MstStream = + &InstancePtr->TxInstance.MstStreamConfig[StreamIndex]; + MsaConfig = + &InstancePtr->TxInstance.MsaConfig[StreamIndex]; - if (XDptx_MstStreamIsEnabled(InstancePtr, StreamIndex + 1)) { - Status = XDptx_AllocatePayloadVcIdTable(InstancePtr, + if (XDp_TxMstStreamIsEnabled(InstancePtr, StreamIndex + 1)) { + Status = XDp_TxAllocatePayloadVcIdTable(InstancePtr, StreamIndex + 1, MsaConfig->TransferUnitSize); if (Status != XST_SUCCESS) { return Status; @@ -1242,17 +1239,18 @@ u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr) } /* Generate an ACT event. */ - Status = XDptx_SendActTrigger(InstancePtr); + Status = XDp_TxSendActTrigger(InstancePtr); if (Status != XST_SUCCESS) { return Status; } /* Send ALLOCATE_PAYLOAD request. */ for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) { - MstStream = &InstancePtr->MstStreamConfig[StreamIndex]; + MstStream = + &InstancePtr->TxInstance.MstStreamConfig[StreamIndex]; - if (XDptx_MstStreamIsEnabled(InstancePtr, StreamIndex + 1)) { - Status = XDptx_SendSbMsgAllocatePayload(InstancePtr, + if (XDp_TxMstStreamIsEnabled(InstancePtr, StreamIndex + 1)) { + Status = XDp_TxSendSbMsgAllocatePayload(InstancePtr, MstStream->LinkCountTotal, MstStream->RelativeAddress, StreamIndex + 1, MstStream->MstPbn); @@ -1272,7 +1270,7 @@ u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr) * on the path to the target device specified by LinkCountTotal and * RelativeAddress. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param VcId is the unique virtual channel ID to allocate into the * payload ID tables. * @param Ts is the number of timeslots to allocate in the payload ID @@ -1294,7 +1292,7 @@ u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -u32 XDptx_AllocatePayloadVcIdTable(XDptx *InstancePtr, u8 VcId, u8 Ts) +u32 XDp_TxAllocatePayloadVcIdTable(XDp *InstancePtr, u8 VcId, u8 Ts) { u32 Status; u8 AuxData[3]; @@ -1309,8 +1307,8 @@ u32 XDptx_AllocatePayloadVcIdTable(XDptx *InstancePtr, u8 VcId, u8 Ts) /* Clear the VC payload ID table updated bit. */ AuxData[0] = 0x1; - Status = XDptx_AuxWrite(InstancePtr, - XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS, 1, AuxData); + Status = XDp_TxAuxWrite(InstancePtr, + XDP_DPCD_PAYLOAD_TABLE_UPDATE_STATUS, 1, AuxData); if (Status != XST_SUCCESS) { /* The AUX write transaction failed. */ return Status; @@ -1318,7 +1316,7 @@ u32 XDptx_AllocatePayloadVcIdTable(XDptx *InstancePtr, u8 VcId, u8 Ts) if (VcId != 0) { /* Find next available timeslot. */ - Status = XDptx_GetFirstAvailableTs(InstancePtr, &StartTs); + Status = XDp_TxGetFirstAvailableTs(InstancePtr, &StartTs); if (Status != XST_SUCCESS) { /* The AUX read transaction failed. */ return Status; @@ -1335,11 +1333,11 @@ u32 XDptx_AllocatePayloadVcIdTable(XDptx *InstancePtr, u8 VcId, u8 Ts) /* Allocate timeslots in TX. */ for (Index = StartTs; Index < (StartTs + Ts); Index++) { - XDptx_WriteReg(InstancePtr->Config.BaseAddr, - (XDPTX_VC_PAYLOAD_BUFFER_ADDR + (4 * Index)), VcId); + XDp_WriteReg(InstancePtr->Config.BaseAddr, + (XDP_TX_VC_PAYLOAD_BUFFER_ADDR + (4 * Index)), VcId); } - XDptx_WaitUs(InstancePtr, 1000); + XDp_WaitUs(InstancePtr, 1000); /* Allocate timeslots in sink. */ @@ -1354,7 +1352,7 @@ u32 XDptx_AllocatePayloadVcIdTable(XDptx *InstancePtr, u8 VcId, u8 Ts) else { AuxData[2] = Ts; } - Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_PAYLOAD_ALLOCATE_SET, 3, + Status = XDp_TxAuxWrite(InstancePtr, XDP_DPCD_PAYLOAD_ALLOCATE_SET, 3, AuxData); if (Status != XST_SUCCESS) { /* The AUX write transaction failed. */ @@ -1363,15 +1361,15 @@ u32 XDptx_AllocatePayloadVcIdTable(XDptx *InstancePtr, u8 VcId, u8 Ts) /* Wait for the VC table to be updated. */ do { - Status = XDptx_AuxRead(InstancePtr, - XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS, 1, AuxData); + Status = XDp_TxAuxRead(InstancePtr, + XDP_DPCD_PAYLOAD_TABLE_UPDATE_STATUS, 1, AuxData); if (Status != XST_SUCCESS) { /* The AUX read transaction failed. */ return Status; } } while ((AuxData[0] & 0x01) != 0x01); - XDptx_WaitUs(InstancePtr, 1000); + XDp_WaitUs(InstancePtr, 1000); return XST_SUCCESS; } @@ -1381,7 +1379,7 @@ u32 XDptx_AllocatePayloadVcIdTable(XDptx *InstancePtr, u8 VcId, u8 Ts) * This function will clear the virtual channel payload ID table in both the * DisplayPort TX and all downstream DisplayPort devices. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if the payload ID tables were successfully @@ -1397,7 +1395,7 @@ u32 XDptx_AllocatePayloadVcIdTable(XDptx *InstancePtr, u8 VcId, u8 Ts) * @note None. * *******************************************************************************/ -u32 XDptx_ClearPayloadVcIdTable(XDptx *InstancePtr) +u32 XDp_TxClearPayloadVcIdTable(XDp *InstancePtr) { u32 Status; u8 Index; @@ -1406,13 +1404,13 @@ u32 XDptx_ClearPayloadVcIdTable(XDptx *InstancePtr) Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Status = XDptx_AllocatePayloadVcIdTable(InstancePtr, 0, 64); + Status = XDp_TxAllocatePayloadVcIdTable(InstancePtr, 0, 64); if (Status != XST_SUCCESS) { return Status; } /* Send CLEAR_PAYLOAD_ID_TABLE request. */ - Status = XDptx_SendSbMsgClearPayloadIdTable(InstancePtr); + Status = XDp_TxSendSbMsgClearPayloadIdTable(InstancePtr); return Status; } @@ -1423,7 +1421,7 @@ u32 XDptx_ClearPayloadVcIdTable(XDptx *InstancePtr) * some data to the specified DisplayPort Configuration Data (DPCD) address of a * downstream DisplayPort device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkCountTotal is the number of DisplayPort links from the * DisplayPort source to the target DisplayPort device. * @param RelativeAddress is the relative address from the DisplayPort @@ -1449,12 +1447,12 @@ u32 XDptx_ClearPayloadVcIdTable(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -u32 XDptx_SendSbMsgRemoteDpcdWrite(XDptx *InstancePtr, u8 LinkCountTotal, +u32 XDp_TxSendSbMsgRemoteDpcdWrite(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData) { u32 Status; - XDptx_SidebandMsg Msg; - XDptx_SidebandReply SbMsgReply; + XDp_SidebandMsg Msg; + XDp_SidebandReply SbMsgReply; u8 Index; /* Verify arguments. */ @@ -1478,10 +1476,10 @@ u32 XDptx_SendSbMsgRemoteDpcdWrite(XDptx *InstancePtr, u8 LinkCountTotal, Msg.Header.StartOfMsgTransaction = 1; Msg.Header.EndOfMsgTransaction = 1; Msg.Header.MsgSequenceNum = 0; - Msg.Header.Crc = XDptx_Crc4CalculateHeader(&Msg.Header); + Msg.Header.Crc = XDp_TxCrc4CalculateHeader(&Msg.Header); /* Prepare the sideband message body. */ - Msg.Body.MsgData[0] = XDPTX_SBMSG_REMOTE_DPCD_WRITE; + Msg.Body.MsgData[0] = XDP_TX_SBMSG_REMOTE_DPCD_WRITE; Msg.Body.MsgData[1] = (RelativeAddress[Msg.Header.LinkCountTotal - 1] << 4) | (DpcdAddress >> 16); Msg.Body.MsgData[2] = (DpcdAddress & 0x0000FF00) >> 8; @@ -1491,16 +1489,16 @@ u32 XDptx_SendSbMsgRemoteDpcdWrite(XDptx *InstancePtr, u8 LinkCountTotal, Msg.Body.MsgData[5 + Index] = WriteData[Index]; } Msg.Body.MsgDataLength = Msg.Header.MsgBodyLength - 1; - Msg.Body.Crc = XDptx_Crc8CalculateBody(&Msg.Body); + Msg.Body.Crc = XDp_TxCrc8CalculateBody(&Msg.Body); /* Submit the REMOTE_DPCD_WRITE transaction message request. */ - Status = XDptx_SendSbMsg(InstancePtr, &Msg); + Status = XDp_TxSendSbMsg(InstancePtr, &Msg); if (Status != XST_SUCCESS) { /* The AUX write transaction used to send the sideband message * failed. */ return Status; } - Status = XDptx_ReceiveSbMsg(InstancePtr, &SbMsgReply); + Status = XDp_TxReceiveSbMsg(InstancePtr, &SbMsgReply); return Status; } @@ -1511,7 +1509,7 @@ u32 XDptx_SendSbMsgRemoteDpcdWrite(XDptx *InstancePtr, u8 LinkCountTotal, * from the specified DisplayPort Configuration Data (DPCD) address of a * downstream DisplayPort device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkCountTotal is the number of DisplayPort links from the * DisplayPort source to the target DisplayPort device. * @param RelativeAddress is the relative address from the DisplayPort @@ -1539,12 +1537,12 @@ u32 XDptx_SendSbMsgRemoteDpcdWrite(XDptx *InstancePtr, u8 LinkCountTotal, * @note None. * *******************************************************************************/ -u32 XDptx_SendSbMsgRemoteDpcdRead(XDptx *InstancePtr, u8 LinkCountTotal, +u32 XDp_TxSendSbMsgRemoteDpcdRead(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData) { u32 Status; - XDptx_SidebandMsg Msg; - XDptx_SidebandReply SbMsgReply; + XDp_SidebandMsg Msg; + XDp_SidebandReply SbMsgReply; u8 Index; /* Verify arguments. */ @@ -1568,26 +1566,26 @@ u32 XDptx_SendSbMsgRemoteDpcdRead(XDptx *InstancePtr, u8 LinkCountTotal, Msg.Header.StartOfMsgTransaction = 1; Msg.Header.EndOfMsgTransaction = 1; Msg.Header.MsgSequenceNum = 0; - Msg.Header.Crc = XDptx_Crc4CalculateHeader(&Msg.Header); + Msg.Header.Crc = XDp_TxCrc4CalculateHeader(&Msg.Header); /* Prepare the sideband message body. */ - Msg.Body.MsgData[0] = XDPTX_SBMSG_REMOTE_DPCD_READ; + Msg.Body.MsgData[0] = XDP_TX_SBMSG_REMOTE_DPCD_READ; Msg.Body.MsgData[1] = (RelativeAddress[Msg.Header.LinkCountTotal - 1] << 4) | (DpcdAddress >> 16); Msg.Body.MsgData[2] = (DpcdAddress & 0x0000FF00) >> 8; Msg.Body.MsgData[3] = (DpcdAddress & 0x000000FF); Msg.Body.MsgData[4] = BytesToRead; Msg.Body.MsgDataLength = Msg.Header.MsgBodyLength - 1; - Msg.Body.Crc = XDptx_Crc8CalculateBody(&Msg.Body); + Msg.Body.Crc = XDp_TxCrc8CalculateBody(&Msg.Body); /* Submit the REMOTE_DPCD_READ transaction message request. */ - Status = XDptx_SendSbMsg(InstancePtr, &Msg); + Status = XDp_TxSendSbMsg(InstancePtr, &Msg); if (Status != XST_SUCCESS) { /* The AUX write transaction used to send the sideband message * failed. */ return Status; } - Status = XDptx_ReceiveSbMsg(InstancePtr, &SbMsgReply); + Status = XDp_TxReceiveSbMsg(InstancePtr, &SbMsgReply); if (Status != XST_SUCCESS) { /* Either the reply indicates a NACK, an AUX read or write * transaction failed, there was a time out waiting for a reply, @@ -1608,12 +1606,12 @@ u32 XDptx_SendSbMsgRemoteDpcdRead(XDptx *InstancePtr, u8 LinkCountTotal, return XST_SUCCESS; } -u32 XDptx_SendSbMsgRemoteIicWrite(XDptx *InstancePtr, u8 LinkCountTotal, +u32 XDp_TxSendSbMsgRemoteIicWrite(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 BytesToWrite, u8 *WriteData) { u32 Status; - XDptx_SidebandMsg Msg; - XDptx_SidebandReply SbMsgReply; + XDp_SidebandMsg Msg; + XDp_SidebandReply SbMsgReply; u8 Index; /* Verify arguments. */ @@ -1637,10 +1635,10 @@ u32 XDptx_SendSbMsgRemoteIicWrite(XDptx *InstancePtr, u8 LinkCountTotal, Msg.Header.StartOfMsgTransaction = 1; Msg.Header.EndOfMsgTransaction = 1; Msg.Header.MsgSequenceNum = 0; - Msg.Header.Crc = XDptx_Crc4CalculateHeader(&Msg.Header); + Msg.Header.Crc = XDp_TxCrc4CalculateHeader(&Msg.Header); /* Prepare the sideband message body. */ - Msg.Body.MsgData[0] = XDPTX_SBMSG_REMOTE_I2C_WRITE; + Msg.Body.MsgData[0] = XDP_TX_SBMSG_REMOTE_I2C_WRITE; Msg.Body.MsgData[1] = RelativeAddress[Msg.Header.LinkCountTotal - 1] << 4; Msg.Body.MsgData[2] = IicDeviceId; /* Write I2C device ID. */ Msg.Body.MsgData[3] = BytesToWrite; /* Number of bytes to write. */ @@ -1648,16 +1646,16 @@ u32 XDptx_SendSbMsgRemoteIicWrite(XDptx *InstancePtr, u8 LinkCountTotal, Msg.Body.MsgData[Index + 4] = WriteData[Index]; } Msg.Body.MsgDataLength = Msg.Header.MsgBodyLength - 1; - Msg.Body.Crc = XDptx_Crc8CalculateBody(&Msg.Body); + Msg.Body.Crc = XDp_TxCrc8CalculateBody(&Msg.Body); /* Submit the REMOTE_I2C_WRITE transaction message request. */ - Status = XDptx_SendSbMsg(InstancePtr, &Msg); + Status = XDp_TxSendSbMsg(InstancePtr, &Msg); if (Status != XST_SUCCESS) { /* The AUX write transaction used to send the sideband message * failed. */ return Status; } - Status = XDptx_ReceiveSbMsg(InstancePtr, &SbMsgReply); + Status = XDp_TxReceiveSbMsg(InstancePtr, &SbMsgReply); return Status; } @@ -1667,7 +1665,7 @@ u32 XDptx_SendSbMsgRemoteIicWrite(XDptx *InstancePtr, u8 LinkCountTotal, * This function will send a REMOTE_I2C_READ sideband message which will read * from the specified I2C address of a downstream DisplayPort device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkCountTotal is the number of DisplayPort links from the * DisplayPort source to the target DisplayPort device. * @param RelativeAddress is the relative address from the DisplayPort @@ -1695,13 +1693,13 @@ u32 XDptx_SendSbMsgRemoteIicWrite(XDptx *InstancePtr, u8 LinkCountTotal, * @note None. * *******************************************************************************/ -u32 XDptx_SendSbMsgRemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, +u32 XDp_TxSendSbMsgRemoteIicRead(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 Offset, u8 BytesToRead, u8 *ReadData) { u32 Status; - XDptx_SidebandMsg Msg; - XDptx_SidebandReply SbMsgReply; + XDp_SidebandMsg Msg; + XDp_SidebandReply SbMsgReply; u8 Index; /* Verify arguments. */ @@ -1725,10 +1723,10 @@ u32 XDptx_SendSbMsgRemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, Msg.Header.StartOfMsgTransaction = 1; Msg.Header.EndOfMsgTransaction = 1; Msg.Header.MsgSequenceNum = 0; - Msg.Header.Crc = XDptx_Crc4CalculateHeader(&Msg.Header); + Msg.Header.Crc = XDp_TxCrc4CalculateHeader(&Msg.Header); /* Prepare the sideband message body. */ - Msg.Body.MsgData[0] = XDPTX_SBMSG_REMOTE_I2C_READ; + Msg.Body.MsgData[0] = XDP_TX_SBMSG_REMOTE_I2C_READ; Msg.Body.MsgData[1] = (RelativeAddress[Msg.Header.LinkCountTotal - 1] << 4) | 1; Msg.Body.MsgData[2] = IicDeviceId; /* Write I2C device ID. */ @@ -1738,16 +1736,16 @@ u32 XDptx_SendSbMsgRemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, Msg.Body.MsgData[6] = IicDeviceId; /* Read I2C device ID. */ Msg.Body.MsgData[7] = BytesToRead; Msg.Body.MsgDataLength = Msg.Header.MsgBodyLength - 1; - Msg.Body.Crc = XDptx_Crc8CalculateBody(&Msg.Body); + Msg.Body.Crc = XDp_TxCrc8CalculateBody(&Msg.Body); /* Submit the REMOTE_I2C_READ transaction message request. */ - Status = XDptx_SendSbMsg(InstancePtr, &Msg); + Status = XDp_TxSendSbMsg(InstancePtr, &Msg); if (Status != XST_SUCCESS) { /* The AUX write transaction used to send the sideband message * failed. */ return Status; } - Status = XDptx_ReceiveSbMsg(InstancePtr, &SbMsgReply); + Status = XDp_TxReceiveSbMsg(InstancePtr, &SbMsgReply); if (Status != XST_SUCCESS) { /* Either the reply indicates a NACK, an AUX read or write * transaction failed, there was a time out waiting for a reply, @@ -1775,7 +1773,7 @@ u32 XDptx_SendSbMsgRemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, * for that device and some device information for each of the ports connected * to the branch device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkCountTotal is the number of DisplayPort links from the * DisplayPort source to the target DisplayPort branch device. * @param RelativeAddress is the relative address from the DisplayPort @@ -1800,12 +1798,12 @@ u32 XDptx_SendSbMsgRemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, * reply. * *******************************************************************************/ -u32 XDptx_SendSbMsgLinkAddress(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress, XDptx_SbMsgLinkAddressReplyDeviceInfo *DeviceInfo) +u32 XDp_TxSendSbMsgLinkAddress(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress, XDp_TxSbMsgLinkAddressReplyDeviceInfo *DeviceInfo) { u32 Status; - XDptx_SidebandMsg Msg; - XDptx_SidebandReply SbMsgReply; + XDp_SidebandMsg Msg; + XDp_SidebandReply SbMsgReply; u8 Index; /* Verify arguments. */ @@ -1827,29 +1825,29 @@ u32 XDptx_SendSbMsgLinkAddress(XDptx *InstancePtr, u8 LinkCountTotal, Msg.Header.StartOfMsgTransaction = 1; Msg.Header.EndOfMsgTransaction = 1; Msg.Header.MsgSequenceNum = 0; - Msg.Header.Crc = XDptx_Crc4CalculateHeader(&Msg.Header); + Msg.Header.Crc = XDp_TxCrc4CalculateHeader(&Msg.Header); /* Prepare the sideband message body. */ - Msg.Body.MsgData[0] = XDPTX_SBMSG_LINK_ADDRESS; + Msg.Body.MsgData[0] = XDP_TX_SBMSG_LINK_ADDRESS; Msg.Body.MsgDataLength = Msg.Header.MsgBodyLength - 1; - Msg.Body.Crc = XDptx_Crc8CalculateBody(&Msg.Body); + Msg.Body.Crc = XDp_TxCrc8CalculateBody(&Msg.Body); /* Submit the LINK_ADDRESS transaction message request. */ - Status = XDptx_SendSbMsg(InstancePtr, &Msg); + Status = XDp_TxSendSbMsg(InstancePtr, &Msg); if (Status != XST_SUCCESS) { /* The AUX write transaction used to send the sideband message * failed. */ return Status; } - Status = XDptx_ReceiveSbMsg(InstancePtr, &SbMsgReply); + Status = XDp_TxReceiveSbMsg(InstancePtr, &SbMsgReply); if (Status != XST_SUCCESS) { /* Either the reply indicates a NACK, an AUX read or write * transaction failed, there was a time out waiting for a reply, * or a CRC check failed. */ return Status; } - XDptx_GetDeviceInfoFromSbMsgLinkAddress(&SbMsgReply, DeviceInfo); + XDp_TxGetDeviceInfoFromSbMsgLinkAddress(&SbMsgReply, DeviceInfo); return XST_SUCCESS; } @@ -1860,7 +1858,7 @@ u32 XDptx_SendSbMsgLinkAddress(XDptx *InstancePtr, u8 LinkCountTotal, * determine the available payload bandwidth number (PBN) for a path to a target * device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkCountTotal is the number of DisplayPort links from the * DisplayPort source to the target DisplayPort device. * @param RelativeAddress is the relative address from the DisplayPort @@ -1889,12 +1887,12 @@ u32 XDptx_SendSbMsgLinkAddress(XDptx *InstancePtr, u8 LinkCountTotal, * reply. * *******************************************************************************/ -u32 XDptx_SendSbMsgEnumPathResources(XDptx *InstancePtr, u8 LinkCountTotal, +u32 XDp_TxSendSbMsgEnumPathResources(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u16 *AvailPbn, u16 *FullPbn) { u32 Status; - XDptx_SidebandMsg Msg; - XDptx_SidebandReply SbMsgReply; + XDp_SidebandMsg Msg; + XDp_SidebandReply SbMsgReply; u8 Index; /* Verify arguments. */ @@ -1917,23 +1915,23 @@ u32 XDptx_SendSbMsgEnumPathResources(XDptx *InstancePtr, u8 LinkCountTotal, Msg.Header.StartOfMsgTransaction = 1; Msg.Header.EndOfMsgTransaction = 1; Msg.Header.MsgSequenceNum = 0; - Msg.Header.Crc = XDptx_Crc4CalculateHeader(&Msg.Header); + Msg.Header.Crc = XDp_TxCrc4CalculateHeader(&Msg.Header); /* Prepare the sideband message body. */ - Msg.Body.MsgData[0] = XDPTX_SBMSG_ENUM_PATH_RESOURCES; + Msg.Body.MsgData[0] = XDP_TX_SBMSG_ENUM_PATH_RESOURCES; Msg.Body.MsgData[1] = (RelativeAddress[Msg.Header.LinkCountTotal - 1] << 4); Msg.Body.MsgDataLength = Msg.Header.MsgBodyLength - 1; - Msg.Body.Crc = XDptx_Crc8CalculateBody(&Msg.Body); + Msg.Body.Crc = XDp_TxCrc8CalculateBody(&Msg.Body); /* Submit the LINK_ADDRESS transaction message request. */ - Status = XDptx_SendSbMsg(InstancePtr, &Msg); + Status = XDp_TxSendSbMsg(InstancePtr, &Msg); if (Status != XST_SUCCESS) { /* The AUX write transaction used to send the sideband message * failed. */ return Status; } - Status = XDptx_ReceiveSbMsg(InstancePtr, &SbMsgReply); + Status = XDp_TxReceiveSbMsg(InstancePtr, &SbMsgReply); if (Status != XST_SUCCESS) { /* Either the reply indicates a NACK, an AUX read or write * transaction failed, there was a time out waiting for a reply, @@ -1953,7 +1951,7 @@ u32 XDptx_SendSbMsgEnumPathResources(XDptx *InstancePtr, u8 LinkCountTotal, * allocate bandwidth for a virtual channel in the payload ID tables of the * downstream devices connecting the DisplayPort TX to the target device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkCountTotal is the number of DisplayPort links from the * DisplayPort source to the target DisplayPort device. * @param RelativeAddress is the relative address from the DisplayPort @@ -1979,12 +1977,12 @@ u32 XDptx_SendSbMsgEnumPathResources(XDptx *InstancePtr, u8 LinkCountTotal, * the target device. * *******************************************************************************/ -u32 XDptx_SendSbMsgAllocatePayload(XDptx *InstancePtr, u8 LinkCountTotal, +u32 XDp_TxSendSbMsgAllocatePayload(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 VcId, u16 Pbn) { u32 Status; - XDptx_SidebandMsg Msg; - XDptx_SidebandReply SbMsgReply; + XDp_SidebandMsg Msg; + XDp_SidebandReply SbMsgReply; u8 Index; /* Verify arguments. */ @@ -2007,26 +2005,26 @@ u32 XDptx_SendSbMsgAllocatePayload(XDptx *InstancePtr, u8 LinkCountTotal, Msg.Header.StartOfMsgTransaction = 1; Msg.Header.EndOfMsgTransaction = 1; Msg.Header.MsgSequenceNum = 0; - Msg.Header.Crc = XDptx_Crc4CalculateHeader(&Msg.Header); + Msg.Header.Crc = XDp_TxCrc4CalculateHeader(&Msg.Header); /* Prepare the sideband message body. */ - Msg.Body.MsgData[0] = XDPTX_SBMSG_ALLOCATE_PAYLOAD; + Msg.Body.MsgData[0] = XDP_TX_SBMSG_ALLOCATE_PAYLOAD; Msg.Body.MsgData[1] = (RelativeAddress[Msg.Header.LinkCountTotal - 1] << 4); Msg.Body.MsgData[2] = VcId; Msg.Body.MsgData[3] = (Pbn >> 8); Msg.Body.MsgData[4] = (Pbn & 0xFFFFFFFF); Msg.Body.MsgDataLength = Msg.Header.MsgBodyLength - 1; - Msg.Body.Crc = XDptx_Crc8CalculateBody(&Msg.Body); + Msg.Body.Crc = XDp_TxCrc8CalculateBody(&Msg.Body); /* Submit the ALLOCATE_PAYLOAD transaction message request. */ - Status = XDptx_SendSbMsg(InstancePtr, &Msg); + Status = XDp_TxSendSbMsg(InstancePtr, &Msg); if (Status != XST_SUCCESS) { /* The AUX write transaction used to send the sideband message * failed. */ return Status; } - Status = XDptx_ReceiveSbMsg(InstancePtr, &SbMsgReply); + Status = XDp_TxReceiveSbMsg(InstancePtr, &SbMsgReply); return Status; } @@ -2036,7 +2034,7 @@ u32 XDptx_SendSbMsgAllocatePayload(XDptx *InstancePtr, u8 LinkCountTotal, * This function will send a CLEAR_PAYLOAD_ID_TABLE sideband message which will * de-allocate all virtual channel payload ID tables. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if the reply to the sideband message was @@ -2053,11 +2051,11 @@ u32 XDptx_SendSbMsgAllocatePayload(XDptx *InstancePtr, u8 LinkCountTotal, * downstream devices. * *******************************************************************************/ -u32 XDptx_SendSbMsgClearPayloadIdTable(XDptx *InstancePtr) +u32 XDp_TxSendSbMsgClearPayloadIdTable(XDp *InstancePtr) { u32 Status; - XDptx_SidebandMsg Msg; - XDptx_SidebandReply SbMsgReply; + XDp_SidebandMsg Msg; + XDp_SidebandReply SbMsgReply; /* Verify arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); @@ -2072,21 +2070,21 @@ u32 XDptx_SendSbMsgClearPayloadIdTable(XDptx *InstancePtr) Msg.Header.StartOfMsgTransaction = 1; Msg.Header.EndOfMsgTransaction = 1; Msg.Header.MsgSequenceNum = 0; - Msg.Header.Crc = XDptx_Crc4CalculateHeader(&Msg.Header); + Msg.Header.Crc = XDp_TxCrc4CalculateHeader(&Msg.Header); /* Prepare the sideband message body. */ - Msg.Body.MsgData[0] = XDPTX_SBMSG_CLEAR_PAYLOAD_ID_TABLE; + Msg.Body.MsgData[0] = XDP_TX_SBMSG_CLEAR_PAYLOAD_ID_TABLE; Msg.Body.MsgDataLength = Msg.Header.MsgBodyLength - 1; - Msg.Body.Crc = XDptx_Crc8CalculateBody(&Msg.Body); + Msg.Body.Crc = XDp_TxCrc8CalculateBody(&Msg.Body); /* Submit the CLEAR_PAYLOAD_ID_TABLE transaction message request. */ - Status = XDptx_SendSbMsg(InstancePtr, &Msg); + Status = XDp_TxSendSbMsg(InstancePtr, &Msg); if (Status != XST_SUCCESS) { /* The AUX write transaction used to send the sideband message * failed. */ return Status; } - Status = XDptx_ReceiveSbMsg(InstancePtr, &SbMsgReply); + Status = XDp_TxReceiveSbMsg(InstancePtr, &SbMsgReply); return Status; } @@ -2096,7 +2094,7 @@ u32 XDptx_SendSbMsgClearPayloadIdTable(XDptx *InstancePtr) * This function will write a global unique identifier (GUID) to the target * DisplayPort device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkCountTotal is the number of DisplayPort links from the * DisplayPort source to the target device. * @param RelativeAddress is the relative address from the DisplayPort @@ -2108,7 +2106,7 @@ u32 XDptx_SendSbMsgClearPayloadIdTable(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -void XDptx_WriteGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, +void XDp_TxWriteGuid(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 Guid[4]) { u8 AuxData[16]; @@ -2128,8 +2126,8 @@ void XDptx_WriteGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, 0xFF; } - XDptx_RemoteDpcdWrite(InstancePtr, LinkCountTotal, RelativeAddress, - XDPTX_DPCD_GUID, 16, AuxData); + XDp_TxRemoteDpcdWrite(InstancePtr, LinkCountTotal, RelativeAddress, + XDP_DPCD_GUID, 16, AuxData); } /******************************************************************************/ @@ -2137,7 +2135,7 @@ void XDptx_WriteGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, * This function will obtain the global unique identifier (GUID) for the target * DisplayPort device. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkCountTotal is the number of DisplayPort links from the * DisplayPort source to the target device. * @param RelativeAddress is the relative address from the DisplayPort @@ -2150,7 +2148,7 @@ void XDptx_WriteGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, * @note None. * *******************************************************************************/ -void XDptx_GetGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, +void XDp_TxGetGuid(XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 *Guid) { u8 Index; @@ -2163,8 +2161,8 @@ void XDptx_GetGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, Xil_AssertVoid((RelativeAddress != NULL) || (LinkCountTotal == 1)); Xil_AssertVoid(Guid != NULL); - XDptx_RemoteDpcdRead(InstancePtr, LinkCountTotal, RelativeAddress, - XDPTX_DPCD_GUID, 16, Data); + XDp_TxRemoteDpcdRead(InstancePtr, LinkCountTotal, RelativeAddress, + XDP_DPCD_GUID, 16, Data); memset(Guid, 0, 16); for (Index = 0; Index < 16; Index++) { @@ -2179,7 +2177,7 @@ void XDptx_GetGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, * unique identifier (GUID). If it doesn't (the GUID is all zeros), then it will * issue one. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param LinkCountTotal is the number of DisplayPort links from the * DisplayPort source to the target device. * @param RelativeAddress is the relative address from the DisplayPort @@ -2193,16 +2191,16 @@ void XDptx_GetGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, * @note The GUID will be issued from the GuidTable. * *******************************************************************************/ -static void XDptx_IssueGuid(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress, XDptx_Topology *Topology, u32 *Guid) +static void XDp_TxIssueGuid(XDp *InstancePtr, u8 LinkCountTotal, + u8 *RelativeAddress, XDp_TxTopology *Topology, u32 *Guid) { - XDptx_GetGuid(InstancePtr, LinkCountTotal, RelativeAddress, Guid); + XDp_TxGetGuid(InstancePtr, LinkCountTotal, RelativeAddress, Guid); if ((Guid[0] == 0) && (Guid[1] == 0) && (Guid[2] == 0) && (Guid[3] == 0)) { - XDptx_WriteGuid(InstancePtr, LinkCountTotal, RelativeAddress, + XDp_TxWriteGuid(InstancePtr, LinkCountTotal, RelativeAddress, GuidTable[Topology->NodeTotal]); - XDptx_GetGuid(InstancePtr, LinkCountTotal, RelativeAddress, + XDp_TxGetGuid(InstancePtr, LinkCountTotal, RelativeAddress, Guid); } } @@ -2212,7 +2210,7 @@ static void XDptx_IssueGuid(XDptx *InstancePtr, u8 LinkCountTotal, * This function will copy the branch device's information into the topology's * node table. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param DeviceInfo is a pointer to the device information of the branch * device to add to the list. * @param LinkCountTotal is the number of DisplayPort links from the @@ -2225,16 +2223,16 @@ static void XDptx_IssueGuid(XDptx *InstancePtr, u8 LinkCountTotal, * @note None. * *******************************************************************************/ -static void XDptx_AddBranchToList(XDptx *InstancePtr, - XDptx_SbMsgLinkAddressReplyDeviceInfo *DeviceInfo, +static void XDp_TxAddBranchToList(XDp *InstancePtr, + XDp_TxSbMsgLinkAddressReplyDeviceInfo *DeviceInfo, u8 LinkCountTotal, u8 *RelativeAddress) { u8 Index; - XDptx_TopologyNode *TopologyNode; + XDp_TxTopologyNode *TopologyNode; /* Add this node to the topology's node list. */ - TopologyNode = &InstancePtr->Topology.NodeTable[ - InstancePtr->Topology.NodeTotal]; + TopologyNode = &InstancePtr->TxInstance.Topology.NodeTable[ + InstancePtr->TxInstance.Topology.NodeTotal]; for (Index = 0; Index < 4; Index++) { TopologyNode->Guid[Index] = DeviceInfo->Guid[Index]; @@ -2248,7 +2246,7 @@ static void XDptx_AddBranchToList(XDptx *InstancePtr, TopologyNode->MsgCapStatus = 1; /* The branch device has been added to the topology node list. */ - InstancePtr->Topology.NodeTotal++; + InstancePtr->TxInstance.Topology.NodeTotal++; } /******************************************************************************/ @@ -2256,7 +2254,7 @@ static void XDptx_AddBranchToList(XDptx *InstancePtr, * This function will copy the sink device's information into the topology's * node table and also add this entry into the topology's sink list. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param SinkDevice is a pointer to the device information of the sink * device to add to the lists. * @param LinkCountTotal is the number of DisplayPort links from the @@ -2270,13 +2268,13 @@ static void XDptx_AddBranchToList(XDptx *InstancePtr, * topology structure. * *******************************************************************************/ -static void XDptx_AddSinkToList(XDptx *InstancePtr, - XDptx_SbMsgLinkAddressReplyPortDetail *SinkDevice, +static void XDp_TxAddSinkToList(XDp *InstancePtr, + XDp_TxSbMsgLinkAddressReplyPortDetail *SinkDevice, u8 LinkCountTotal, u8 *RelativeAddress) { u8 Index; - XDptx_Topology *Topology = &InstancePtr->Topology; - XDptx_TopologyNode *TopologyNode; + XDp_TxTopology *Topology = &InstancePtr->TxInstance.Topology; + XDp_TxTopologyNode *TopologyNode; /* Add this node to the topology's node list. */ TopologyNode = &Topology->NodeTable[Topology->NodeTotal]; @@ -2322,12 +2320,12 @@ static void XDptx_AddSinkToList(XDptx *InstancePtr, * @note None. * *******************************************************************************/ -static void XDptx_GetDeviceInfoFromSbMsgLinkAddress(XDptx_SidebandReply - *SbReply, XDptx_SbMsgLinkAddressReplyDeviceInfo *FormatReply) +static void XDp_TxGetDeviceInfoFromSbMsgLinkAddress(XDp_SidebandReply + *SbReply, XDp_TxSbMsgLinkAddressReplyDeviceInfo *FormatReply) { u8 ReplyIndex = 0; u8 Index, Index2; - XDptx_SbMsgLinkAddressReplyPortDetail *PortDetails; + XDp_TxSbMsgLinkAddressReplyPortDetail *PortDetails; /* Determine the device information from the sideband message reply * structure. */ @@ -2383,7 +2381,7 @@ static void XDptx_GetDeviceInfoFromSbMsgLinkAddress(XDptx_SidebandReply * This function will read the payload ID table from the immediate downstream RX * device and determine what the first available time slot is in the table. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if the immediate downstream RX device's payload ID @@ -2398,13 +2396,13 @@ static void XDptx_GetDeviceInfoFromSbMsgLinkAddress(XDptx_SidebandReply * @note None. * *******************************************************************************/ -static u32 XDptx_GetFirstAvailableTs(XDptx *InstancePtr, u8 *FirstTs) +static u32 XDp_TxGetFirstAvailableTs(XDp *InstancePtr, u8 *FirstTs) { u32 Status; u8 Index; u8 AuxData[64]; - Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_VC_PAYLOAD_ID_SLOT(1), + Status = XDp_TxAuxRead(InstancePtr, XDP_DPCD_VC_PAYLOAD_ID_SLOT(1), 64, AuxData); if (Status != XST_SUCCESS) { /* The AUX read transaction failed. */ @@ -2430,7 +2428,7 @@ static u32 XDptx_GetFirstAvailableTs(XDptx *InstancePtr, u8 *FirstTs) * This function will send a sideband message by creating a data array from the * supplied sideband message structure and submitting an AUX write transaction. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if the RX device indicates that the ACT trigger @@ -2445,37 +2443,37 @@ static u32 XDptx_GetFirstAvailableTs(XDptx *InstancePtr, u8 *FirstTs) * @note None. * *******************************************************************************/ -static u32 XDptx_SendActTrigger(XDptx *InstancePtr) +static u32 XDp_TxSendActTrigger(XDp *InstancePtr) { u32 Status; u8 AuxData; u8 TimeoutCount = 0; - XDptx_WaitUs(InstancePtr, 10000); + XDp_WaitUs(InstancePtr, 10000); - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_MST_CONFIG, 0x3); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_MST_CONFIG, 0x3); do { - Status = XDptx_AuxRead(InstancePtr, - XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS, 1, &AuxData); + Status = XDp_TxAuxRead(InstancePtr, + XDP_DPCD_PAYLOAD_TABLE_UPDATE_STATUS, 1, &AuxData); if (Status != XST_SUCCESS) { /* The AUX read transaction failed. */ return Status; } /* Error out if timed out. */ - if (TimeoutCount > XDPTX_VCP_TABLE_MAX_TIMEOUT_COUNT) { + if (TimeoutCount > XDP_TX_VCP_TABLE_MAX_TIMEOUT_COUNT) { return XST_ERROR_COUNT_MAX; } TimeoutCount++; - XDptx_WaitUs(InstancePtr, 1000); + XDp_WaitUs(InstancePtr, 1000); } while ((AuxData & 0x02) != 0x02); /* Clear the ACT event received bit. */ AuxData = 0x2; - Status = XDptx_AuxWrite(InstancePtr, - XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS, 1, &AuxData); + Status = XDp_TxAuxWrite(InstancePtr, + XDP_DPCD_PAYLOAD_TABLE_UPDATE_STATUS, 1, &AuxData); if (Status != XST_SUCCESS) { /* The AUX write transaction failed. */ return Status; @@ -2489,7 +2487,7 @@ static u32 XDptx_SendActTrigger(XDptx *InstancePtr) * This function will send a sideband message by creating a data array from the * supplied sideband message structure and submitting an AUX write transaction. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Msg is a pointer to the sideband message structure that holds * the contents of the data to be submitted. * @@ -2503,21 +2501,21 @@ static u32 XDptx_SendActTrigger(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -static u32 XDptx_SendSbMsg(XDptx *InstancePtr, XDptx_SidebandMsg *Msg) +static u32 XDp_TxSendSbMsg(XDp *InstancePtr, XDp_SidebandMsg *Msg) { u32 Status; u8 AuxData[10+63]; - XDptx_SidebandMsgHeader *Header = &Msg->Header; - XDptx_SidebandMsgBody *Body = &Msg->Body; + XDp_SidebandMsgHeader *Header = &Msg->Header; + XDp_SidebandMsgBody *Body = &Msg->Body; u8 Index; - XDptx_WaitUs(InstancePtr, InstancePtr->SbMsgDelayUs); + XDp_WaitUs(InstancePtr, InstancePtr->TxInstance.SbMsgDelayUs); /* First, clear the DOWN_REP_MSG_RDY in case the RX device is in a weird * state. */ AuxData[0] = 0x10; - Status = XDptx_AuxWrite(InstancePtr, - XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0, 1, + Status = XDp_TxAuxWrite(InstancePtr, + XDP_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0, 1, AuxData); if (Status != XST_SUCCESS) { return Status; @@ -2554,7 +2552,7 @@ static u32 XDptx_SendSbMsg(XDptx *InstancePtr, XDptx_SidebandMsg *Msg) AuxData[Index + Header->MsgHeaderLength] = Body->Crc; /* Submit the LINK_ADDRESS transaction message request. */ - Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_DOWN_REQ, + Status = XDp_TxAuxWrite(InstancePtr, XDP_DPCD_DOWN_REQ, Msg->Header.MsgHeaderLength + Msg->Header.MsgBodyLength, AuxData); @@ -2566,7 +2564,7 @@ static u32 XDptx_SendSbMsg(XDptx *InstancePtr, XDptx_SidebandMsg *Msg) * This function will wait for a sideband message reply and fill in the SbReply * structure with the reply data for use by higher-level functions. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param SbReply is a pointer to the reply structure that this function * will fill in for use by higher-level functions. * @@ -2583,35 +2581,35 @@ static u32 XDptx_SendSbMsg(XDptx *InstancePtr, XDptx_SidebandMsg *Msg) * @note None. * *******************************************************************************/ -static u32 XDptx_ReceiveSbMsg(XDptx *InstancePtr, XDptx_SidebandReply *SbReply) +static u32 XDp_TxReceiveSbMsg(XDp *InstancePtr, XDp_SidebandReply *SbReply) { u32 Status; u8 Index = 0; u8 AuxData[80]; - XDptx_SidebandMsg Msg; + XDp_SidebandMsg Msg; SbReply->Length = 0; do { - XDptx_WaitUs(InstancePtr, InstancePtr->SbMsgDelayUs); + XDp_WaitUs(InstancePtr, InstancePtr->TxInstance.SbMsgDelayUs); /* Wait for a reply. */ - Status = XDptx_WaitSbReply(InstancePtr); + Status = XDp_TxWaitSbReply(InstancePtr); if (Status != XST_SUCCESS) { return Status; } /* Receive reply. */ - Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_DOWN_REP, 80, + Status = XDp_TxAuxRead(InstancePtr, XDP_DPCD_DOWN_REP, 80, AuxData); if (Status != XST_SUCCESS) { /* The AUX read transaction failed. */ return Status; } - /* Convert the reply transaction into XDptx_SidebandReply + /* Convert the reply transaction into XDp_SidebandReply * format. */ - Status = XDptx_Transaction2MsgFormat(AuxData, &Msg); + Status = XDp_TxTransaction2MsgFormat(AuxData, &Msg); if (Status != XST_SUCCESS) { /* The CRC of the header or the body did not match the * calculated value. */ @@ -2626,8 +2624,8 @@ static u32 XDptx_ReceiveSbMsg(XDptx *InstancePtr, XDptx_SidebandReply *SbReply) /* Clear. */ AuxData[0] = 0x10; - Status = XDptx_AuxWrite(InstancePtr, - XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0, + Status = XDp_TxAuxWrite(InstancePtr, + XDP_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0, 1, AuxData); if (Status != XST_SUCCESS) { /* The AUX write transaction failed. */ @@ -2650,7 +2648,7 @@ static u32 XDptx_ReceiveSbMsg(XDptx *InstancePtr, XDptx_SidebandReply *SbReply) * DisplayPort TX indicates that a sideband reply is ready to be received by * the source. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * * @return * - XST_SUCCESS if a reply message is ready. @@ -2663,15 +2661,15 @@ static u32 XDptx_ReceiveSbMsg(XDptx *InstancePtr, XDptx_SidebandReply *SbReply) * @note None. * *******************************************************************************/ -static u32 XDptx_WaitSbReply(XDptx *InstancePtr) +static u32 XDp_TxWaitSbReply(XDp *InstancePtr) { u32 Status; u8 AuxData; u16 TimeoutCount = 0; do { - Status = XDptx_AuxRead(InstancePtr, - XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0, + Status = XDp_TxAuxRead(InstancePtr, + XDP_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0, 1, &AuxData); if (Status != XST_SUCCESS) { /* The AUX read transaction failed. */ @@ -2679,12 +2677,12 @@ static u32 XDptx_WaitSbReply(XDptx *InstancePtr) } /* Error out if timed out. */ - if (TimeoutCount > XDPTX_MAX_SBMSG_REPLY_TIMEOUT_COUNT) { + if (TimeoutCount > XDP_TX_MAX_SBMSG_REPLY_TIMEOUT_COUNT) { return XST_ERROR_COUNT_MAX; } TimeoutCount++; - XDptx_WaitUs(InstancePtr, 1000); + XDp_WaitUs(InstancePtr, 1000); } while ((AuxData & 0x10) != 0x10); @@ -2694,7 +2692,7 @@ static u32 XDptx_WaitSbReply(XDptx *InstancePtr) /******************************************************************************/ /** * This function will take a byte array and convert it into a sideband message - * format by filling in the XDptx_SidebandMsg structure with the array data. + * format by filling in the XDp_SidebandMsg structure with the array data. * * @param Transaction is the pointer to the data used to fill in the * sideband message structure. @@ -2710,10 +2708,10 @@ static u32 XDptx_WaitSbReply(XDptx *InstancePtr) * @note None. * *******************************************************************************/ -static u32 XDptx_Transaction2MsgFormat(u8 *Transaction, XDptx_SidebandMsg *Msg) +static u32 XDp_TxTransaction2MsgFormat(u8 *Transaction, XDp_SidebandMsg *Msg) { - XDptx_SidebandMsgHeader *Header = &Msg->Header; - XDptx_SidebandMsgBody *Body = &Msg->Body; + XDp_SidebandMsgHeader *Header = &Msg->Header; + XDp_SidebandMsgBody *Body = &Msg->Body; u8 Index = 0; u8 CrcCheck; @@ -2752,7 +2750,7 @@ static u32 XDptx_Transaction2MsgFormat(u8 *Transaction, XDptx_SidebandMsg *Msg) Header->Crc = Transaction[Header->MsgHeaderLength] & 0x0F; Header->MsgHeaderLength++; /* Verify the header CRC. */ - CrcCheck = XDptx_Crc4CalculateHeader(Header); + CrcCheck = XDp_TxCrc4CalculateHeader(Header); if (CrcCheck != Header->Crc) { /* The calculated CRC for the header did not match the * response. */ @@ -2767,7 +2765,7 @@ static u32 XDptx_Transaction2MsgFormat(u8 *Transaction, XDptx_SidebandMsg *Msg) } Body->Crc = Transaction[Header->MsgHeaderLength + Index]; /* Verify the body CRC. */ - CrcCheck = XDptx_Crc8CalculateBody(Body); + CrcCheck = XDp_TxCrc8CalculateBody(Body); if (CrcCheck != Body->Crc) { /* The calculated CRC for the body did not match the * response. */ @@ -2782,7 +2780,7 @@ static u32 XDptx_Transaction2MsgFormat(u8 *Transaction, XDptx_SidebandMsg *Msg) * This function will perform a cyclic redundancy check (CRC) on the header of a * sideband message using a generator polynomial of 4. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Header is a pointer sideband message header that the CRC * algorithm is to be run on. * @@ -2790,10 +2788,10 @@ static u32 XDptx_Transaction2MsgFormat(u8 *Transaction, XDptx_SidebandMsg *Msg) * message header. * * @note The header is divided into 4-bit nibbles for use by the lower- - * level XDptx_CrcCalculate function. + * level XDp_TxCrcCalculate function. * *******************************************************************************/ -static u8 XDptx_Crc4CalculateHeader(XDptx_SidebandMsgHeader *Header) +static u8 XDp_TxCrc4CalculateHeader(XDp_SidebandMsgHeader *Header) { u8 Nibbles[20]; u8 RadOffset = 0; @@ -2822,7 +2820,7 @@ static u8 XDptx_Crc4CalculateHeader(XDptx_SidebandMsgHeader *Header) Nibbles[4 + RadOffset] = (Header->StartOfMsgTransaction << 3) | (Header->EndOfMsgTransaction << 2) | Header->MsgSequenceNum; - return XDptx_CrcCalculate(Nibbles, 4 * (5 + RadOffset), 4); + return XDp_TxCrcCalculate(Nibbles, 4 * (5 + RadOffset), 4); } /******************************************************************************/ @@ -2830,7 +2828,7 @@ static u8 XDptx_Crc4CalculateHeader(XDptx_SidebandMsgHeader *Header) * This function will perform a cyclic redundancy check (CRC) on the body of a * sideband message using a generator polynomial of 8. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Body is a pointer sideband message body that the CRC algorithm * is to be run on. * @@ -2840,9 +2838,9 @@ static u8 XDptx_Crc4CalculateHeader(XDptx_SidebandMsgHeader *Header) * @note None. * *******************************************************************************/ -static u8 XDptx_Crc8CalculateBody(XDptx_SidebandMsgBody *Body) +static u8 XDp_TxCrc8CalculateBody(XDp_SidebandMsgBody *Body) { - return XDptx_CrcCalculate(Body->MsgData, 8 * Body->MsgDataLength, 8); + return XDp_TxCrcCalculate(Body->MsgData, 8 * Body->MsgDataLength, 8); } /******************************************************************************/ @@ -2862,7 +2860,7 @@ static u8 XDptx_Crc8CalculateBody(XDptx_SidebandMsgBody *Body) * @note None. * *******************************************************************************/ -static u8 XDptx_CrcCalculate(const u8 *Data, u32 NumberOfBits, u8 Polynomial) +static u8 XDp_TxCrcCalculate(const u8 *Data, u32 NumberOfBits, u8 Polynomial) { u8 BitMask; u8 BitShift; @@ -2949,26 +2947,26 @@ static u8 XDptx_CrcCalculate(const u8 *Data, u32 NumberOfBits, u8 Polynomial) * @note None. * *******************************************************************************/ -static u32 XDptx_IsSameTileDisplay(u8 *TileDisp0, u8 *TileDisp1) +static u32 XDp_TxIsSameTileDisplay(u8 *TileDisp0, u8 *TileDisp1) { - if ((TileDisp0[XDPTX_DISPID_TDT_VENID0] != - TileDisp1[XDPTX_DISPID_TDT_VENID0]) || - (TileDisp0[XDPTX_DISPID_TDT_VENID1] != - TileDisp1[XDPTX_DISPID_TDT_VENID1]) || - (TileDisp0[XDPTX_DISPID_TDT_VENID2] != - TileDisp1[XDPTX_DISPID_TDT_VENID2]) || - (TileDisp0[XDPTX_DISPID_TDT_PCODE0] != - TileDisp1[XDPTX_DISPID_TDT_PCODE0]) || - (TileDisp0[XDPTX_DISPID_TDT_PCODE1] != - TileDisp1[XDPTX_DISPID_TDT_PCODE1]) || - (TileDisp0[XDPTX_DISPID_TDT_SN0] != - TileDisp1[XDPTX_DISPID_TDT_SN0]) || - (TileDisp0[XDPTX_DISPID_TDT_SN1] != - TileDisp1[XDPTX_DISPID_TDT_SN1]) || - (TileDisp0[XDPTX_DISPID_TDT_SN2] != - TileDisp1[XDPTX_DISPID_TDT_SN2]) || - (TileDisp0[XDPTX_DISPID_TDT_SN3] != - TileDisp1[XDPTX_DISPID_TDT_SN3]) ) { + if ((TileDisp0[XDP_TX_DISPID_TDT_VENID0] != + TileDisp1[XDP_TX_DISPID_TDT_VENID0]) || + (TileDisp0[XDP_TX_DISPID_TDT_VENID1] != + TileDisp1[XDP_TX_DISPID_TDT_VENID1]) || + (TileDisp0[XDP_TX_DISPID_TDT_VENID2] != + TileDisp1[XDP_TX_DISPID_TDT_VENID2]) || + (TileDisp0[XDP_TX_DISPID_TDT_PCODE0] != + TileDisp1[XDP_TX_DISPID_TDT_PCODE0]) || + (TileDisp0[XDP_TX_DISPID_TDT_PCODE1] != + TileDisp1[XDP_TX_DISPID_TDT_PCODE1]) || + (TileDisp0[XDP_TX_DISPID_TDT_SN0] != + TileDisp1[XDP_TX_DISPID_TDT_SN0]) || + (TileDisp0[XDP_TX_DISPID_TDT_SN1] != + TileDisp1[XDP_TX_DISPID_TDT_SN1]) || + (TileDisp0[XDP_TX_DISPID_TDT_SN2] != + TileDisp1[XDP_TX_DISPID_TDT_SN2]) || + (TileDisp0[XDP_TX_DISPID_TDT_SN3] != + TileDisp1[XDP_TX_DISPID_TDT_SN3]) ) { return 0; } diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdp_selftest.c b/XilinxProcessorIPLib/drivers/dp/src/xdp_selftest.c new file mode 100644 index 00000000..178fe5a4 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp_selftest.c @@ -0,0 +1,339 @@ +/******************************************************************************* + * + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xdp_selftest.c + * + * This file contains a diagnostic self-test function for the XDp driver. It + * will check many of the DisplayPort core's register values against the default + * reset values as a sanity-check that the core is ready to be used. + * + * @note None. + * + *
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   als  01/20/15 Initial release.
+ * 
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xdp.h" + +/**************************** Function Prototypes *****************************/ + +static u32 XDp_TxSelfTest(XDp *InstancePtr); +static u32 XDp_RxSelfTest(XDp *InstancePtr); + +/**************************** Variable Definitions ****************************/ + +/** + * This table contains the default values for the DisplayPort TX core's general + * usage registers. + */ +u32 TxResetValues[53][2] = +{ + {XDP_TX_LINK_BW_SET, 0}, + {XDP_TX_LANE_COUNT_SET, 0}, + {XDP_TX_ENHANCED_FRAME_EN, 0}, + {XDP_TX_TRAINING_PATTERN_SET, 0}, + {XDP_TX_LINK_QUAL_PATTERN_SET, 0}, + {XDP_TX_SCRAMBLING_DISABLE, 0}, + {XDP_TX_DOWNSPREAD_CTRL, 0}, + {XDP_TX_SOFT_RESET, 0}, + {XDP_TX_ENABLE, 0}, + {XDP_TX_ENABLE_MAIN_STREAM, 0}, + {XDP_TX_ENABLE_SEC_STREAM, 0}, + {XDP_TX_FORCE_SCRAMBLER_RESET, 0}, + {XDP_TX_MST_CONFIG, 0}, + {XDP_TX_AUX_CMD, 0}, + {XDP_TX_AUX_WRITE_FIFO, 0}, + {XDP_TX_AUX_ADDRESS, 0}, + {XDP_TX_AUX_CLK_DIVIDER, 0}, + {XDP_TX_USER_FIFO_OVERFLOW, 0}, + {XDP_TX_AUX_REPLY_DATA, 0}, + {XDP_TX_AUX_REPLY_CODE, 0}, + {XDP_TX_AUX_REPLY_COUNT, 0}, + {XDP_TX_INTERRUPT_MASK, 0x3F}, + {XDP_TX_REPLY_DATA_COUNT, 0}, + {XDP_TX_REPLY_STATUS, 0x10}, + {XDP_TX_STREAM1, 0}, + {XDP_TX_STREAM2, 0}, + {XDP_TX_STREAM3, 0}, + {XDP_TX_STREAM4, 0}, + {XDP_TX_PHY_CONFIG, 0x03}, + {XDP_TX_PHY_VOLTAGE_DIFF_LANE_0, 0}, + {XDP_TX_PHY_VOLTAGE_DIFF_LANE_1, 0}, + {XDP_TX_PHY_VOLTAGE_DIFF_LANE_2, 0}, + {XDP_TX_PHY_VOLTAGE_DIFF_LANE_3, 0}, + {XDP_TX_PHY_TRANSMIT_PRBS7, 0}, + {XDP_TX_PHY_CLOCK_SELECT, 0}, + {XDP_TX_PHY_POWER_DOWN, 0}, + {XDP_TX_PHY_PRECURSOR_LANE_0, 0}, + {XDP_TX_PHY_PRECURSOR_LANE_1, 0}, + {XDP_TX_PHY_PRECURSOR_LANE_2, 0}, + {XDP_TX_PHY_PRECURSOR_LANE_3, 0}, + {XDP_TX_PHY_POSTCURSOR_LANE_0, 0}, + {XDP_TX_PHY_POSTCURSOR_LANE_1, 0}, + {XDP_TX_PHY_POSTCURSOR_LANE_2, 0}, + {XDP_TX_PHY_POSTCURSOR_LANE_3, 0}, + {XDP_TX_GT_DRP_COMMAND, 0}, + {XDP_TX_GT_DRP_READ_DATA, 0}, + {XDP_TX_GT_DRP_CHANNEL_STATUS, 0}, + {XDP_TX_AUDIO_CONTROL, 0}, + {XDP_TX_AUDIO_CHANNELS, 0}, + {XDP_TX_AUDIO_INFO_DATA(1), 0}, + {XDP_TX_AUDIO_MAUD, 0}, + {XDP_TX_AUDIO_NAUD, 0}, + {XDP_TX_AUDIO_EXT_DATA(1), 0} +}; + +/** + * This table contains the default values for the DisplayPort TX core's main + * stream attribute (MSA) registers. + */ +u32 TxResetValuesMsa[20][2] = +{ + {XDP_TX_MAIN_STREAM_HTOTAL, 0}, + {XDP_TX_MAIN_STREAM_VTOTAL, 0}, + {XDP_TX_MAIN_STREAM_POLARITY, 0}, + {XDP_TX_MAIN_STREAM_HSWIDTH, 0}, + {XDP_TX_MAIN_STREAM_VSWIDTH, 0}, + {XDP_TX_MAIN_STREAM_HRES, 0}, + {XDP_TX_MAIN_STREAM_VRES, 0}, + {XDP_TX_MAIN_STREAM_HSTART, 0}, + {XDP_TX_MAIN_STREAM_VSTART, 0}, + {XDP_TX_MAIN_STREAM_MISC0, 0}, + {XDP_TX_MAIN_STREAM_MISC1, 0}, + {XDP_TX_M_VID, 0}, + {XDP_TX_TU_SIZE, 0}, + {XDP_TX_N_VID, 0}, + {XDP_TX_USER_PIXEL_WIDTH, 0}, + {XDP_TX_USER_DATA_COUNT_PER_LANE, 0}, + {XDP_TX_MAIN_STREAM_INTERLACED, 0}, + {XDP_TX_MIN_BYTES_PER_TU, 0}, + {XDP_TX_FRAC_BYTES_PER_TU, 0}, + {XDP_TX_INIT_WAIT, 32} +}; + +/** + * This table contains the default values for the DisplayPort RX core's general + * usage registers. + */ +u32 RxResetValues[46][2] = +{ + {XDP_RX_LINK_ENABLE, 0}, + {XDP_RX_AUX_CLK_DIVIDER, 0}, + {XDP_RX_DTG_ENABLE, 0}, + {XDP_RX_USER_PIXEL_WIDTH, 0}, + {XDP_RX_INTERRUPT_MASK, 0x7FFF}, + {XDP_RX_MISC_CTRL, 0}, + {XDP_RX_SOFT_RESET, 0}, + {XDP_RX_AUX_REQ_IN_PROGRESS, 0}, + {XDP_RX_REQ_ERROR_COUNT, 0}, + {XDP_RX_REQ_COUNT, 0}, + {XDP_RX_HPD_INTERRUPT, 0}, + {XDP_RX_REQ_CLK_WIDTH, 0}, + {XDP_RX_REQ_CMD, 0}, + {XDP_RX_REQ_ADDRESS, 0}, + {XDP_RX_REQ_LENGTH, 0}, + {XDP_RX_INTERRUPT_CAUSE, 0}, + {XDP_RX_INTERRUPT_MASK_1, 0}, + {XDP_RX_INTERRUPT_CAUSE_1, 0}, + {XDP_RX_HSYNC_WIDTH, 0xF0F}, + {XDP_RX_FAST_I2C_DIVIDER, 0}, + {XDP_RX_LOCAL_EDID_VIDEO, 0}, + {XDP_RX_LOCAL_EDID_AUDIO, 0}, + {XDP_RX_REMOTE_CMD, 0}, + {XDP_RX_DEVICE_SERVICE_IRQ, 0}, + {XDP_RX_VIDEO_UNSUPPORTED, 0}, + {XDP_RX_AUDIO_UNSUPPORTED, 0}, + {XDP_RX_OVER_LINK_BW_SET, 0}, + {XDP_RX_OVER_LANE_COUNT_SET, 0}, + {XDP_RX_OVER_TP_SET, 0}, + {XDP_RX_OVER_TRAINING_LANE0_SET, 0}, + {XDP_RX_OVER_TRAINING_LANE1_SET, 0}, + {XDP_RX_OVER_TRAINING_LANE2_SET, 0}, + {XDP_RX_OVER_TRAINING_LANE3_SET, 0}, + {XDP_RX_OVER_CTRL_DPCD, 0}, + {XDP_RX_OVER_DOWNSPREAD_CTRL, 0}, + {XDP_RX_OVER_LINK_QUAL_LANE0_SET, 0}, + {XDP_RX_OVER_LINK_QUAL_LANE1_SET, 0}, + {XDP_RX_OVER_LINK_QUAL_LANE2_SET, 0}, + {XDP_RX_OVER_LINK_QUAL_LANE3_SET, 0}, + {XDP_RX_MST_CAP, 0}, + {XDP_RX_SINK_COUNT, 0}, + {XDP_RX_GUID0, 0}, + {XDP_RX_GUID1, 0}, + {XDP_RX_GUID2, 0}, + {XDP_RX_GUID3, 0}, + {XDP_RX_OVER_GUID, 0} +}; + +/**************************** Function Definitions ****************************/ + +/******************************************************************************/ +/** + * This function runs a self-test on the XDp driver/device depending on whether + * the core is operating in TX or RX mode. The sanity test checks whether or not + * all tested registers hold their default reset values. + * + * @param InstancePtr is a pointer to the XDp instance. + * + * @return + * - XST_SUCCESS if the self-test passed - all tested registers + * hold their default reset values. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +u32 XDp_SelfTest(XDp *InstancePtr) +{ + u32 Status; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XDp_CfgGetCoreType(&InstancePtr->Config) == XDP_TX) { + Status = XDp_TxSelfTest(InstancePtr); + } + else { + Status = XDp_RxSelfTest(InstancePtr); + } + + return Status; +} + +/******************************************************************************/ +/** + * This function runs a self-test on the XDp driver/device. The sanity test + * checks whether or not all tested registers hold their default reset values. + * + * @param InstancePtr is a pointer to the XDp instance. + * + * @return + * - XST_SUCCESS if the self-test passed - all tested registers + * hold their default reset values. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static u32 XDp_TxSelfTest(XDp *InstancePtr) +{ + u8 Index; + u8 StreamIndex; + u32 StreamOffset; + u32 Val; + + /* Compare general usage registers with their default values. */ + for (Index = 0; Index < 53; Index++) { + Val = XDp_ReadReg(InstancePtr->Config.BaseAddr, + TxResetValues[Index][0]); + /* Fail if register does not hold default value. */ + if (Val != TxResetValues[Index][1]) { + return XST_FAILURE; + } + } + + /* Compare main stream attribute (MSA) registers for all 4 streams with + * their default values. */ + for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) { + /* Determine the MSA register offset for each stream. */ + if (StreamIndex == 0) { + StreamOffset = 0; + } + else if (StreamIndex == 1) { + StreamOffset = XDP_TX_STREAM2_MSA_START_OFFSET; + } + else if (StreamIndex == 2) { + StreamOffset = XDP_TX_STREAM3_MSA_START_OFFSET; + } + else if (StreamIndex == 3) { + StreamOffset = XDP_TX_STREAM4_MSA_START_OFFSET; + } + + for (Index = 0; Index < 20; Index++) { + Val = XDp_ReadReg(InstancePtr->Config.BaseAddr, + StreamOffset + TxResetValuesMsa[Index][0]); + /* Fail if register does not hold default value. */ + if (Val != TxResetValuesMsa[Index][1]) { + return XST_FAILURE; + } + } + } + + /* All tested registers hold their default reset values. */ + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function runs a self-test on the XDp driver/device running in RX mode. + * The sanity test checks whether or not all tested registers hold their default + * reset values. + * + * @param InstancePtr is a pointer to the XDp instance. + * + * @return + * - XST_SUCCESS if the self-test passed - all tested registers + * hold their default reset values. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static u32 XDp_RxSelfTest(XDp *InstancePtr) +{ + u8 Index; + u32 Val; + + /* Compare general usage registers with their default values. */ + for (Index = 0; Index < 46; Index++) { + Val = XDp_ReadReg(InstancePtr->Config.BaseAddr, + RxResetValues[Index][0]); + /* Fail if register does not hold default value. */ + if (Val != RxResetValues[Index][1]) { + return XST_FAILURE; + } + } + + /* All tested registers hold their default reset values. */ + return XST_SUCCESS; +} diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdp_sinit.c b/XilinxProcessorIPLib/drivers/dp/src/xdp_sinit.c index 094d4c4a..8fbc246f 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdp_sinit.c +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp_sinit.c @@ -50,7 +50,7 @@ /******************************* Include Files ********************************/ -#include "xdptx.h" +#include "xdp.h" #include "xparameters.h" /*************************** Variable Declarations ****************************/ diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdptx_spm.c b/XilinxProcessorIPLib/drivers/dp/src/xdp_spm.c similarity index 65% rename from XilinxProcessorIPLib/drivers/dp/src/xdptx_spm.c rename to XilinxProcessorIPLib/drivers/dp/src/xdp_spm.c index 288e7f3d..189c4318 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdptx_spm.c +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp_spm.c @@ -1,6 +1,6 @@ /******************************************************************************* * - * Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,11 +32,12 @@ /******************************************************************************/ /** * - * @file xdptx_spm.c + * @file xdp_spm.c * - * This file contains the stream policy maker functions for the XDptx driver. - * These functions set up the DisplayPort TX core's main stream attributes that - * determine how a video stream will be displayed. + * This file contains the stream policy maker functions for the XDp driver. + * These functions set up the DisplayPort TX core's main stream attributes (MSA) + * that determine how a video stream will be displayed and also some DisplayPort + * RX MSA-related functions. * * @note None. * @@ -45,23 +46,18 @@ * * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- - * 1.0 als 05/17/14 Initial release. - * als 08/03/14 Initial MST addition. - * 3.0 als 12/16/14 Updated to use common video library. - * Stream naming now starts at 1 to follow IP. + * 1.0 als 01/20/15 Initial release. * * *******************************************************************************/ /******************************* Include Files ********************************/ -#include "xdptx.h" -#include "xdptx_hw.h" -#include "xstatus.h" +#include "xdp.h" /**************************** Function Prototypes *****************************/ -static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel); +static void XDp_TxCalculateTs(XDp *InstancePtr, u8 Stream, u8 BitsPerPixel); /**************************** Function Definitions ****************************/ @@ -93,7 +89,7 @@ static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel); * - Vertical sync pulse width * - Vertical back porch * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Stream is the stream number for which to calculate the MSA * values. * @@ -104,31 +100,31 @@ static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel); * calculated values are untouched in the MsaConfig structure. * *******************************************************************************/ -void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream) +void XDp_TxCfgMsaRecalculate(XDp *InstancePtr, u8 Stream) { u32 VideoBw; u32 LinkBw; u32 WordsPerLine; u8 BitsPerPixel; - XDptx_MainStreamAttributes *MsaConfig; - XDptx_LinkConfig *LinkConfig; + XDp_TxMainStreamAttributes *MsaConfig; + XDp_TxLinkConfig *LinkConfig; /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) || + (Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) || + (Stream == XDP_TX_STREAM_ID4)); - MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; - LinkConfig = &InstancePtr->LinkConfig; + MsaConfig = &InstancePtr->TxInstance.MsaConfig[Stream - 1]; + LinkConfig = &InstancePtr->TxInstance.LinkConfig; /* Verify the rest of the values used. */ - Xil_AssertVoid((LinkConfig->LinkRate == XDPTX_LINK_BW_SET_162GBPS) || - (LinkConfig->LinkRate == XDPTX_LINK_BW_SET_270GBPS) || - (LinkConfig->LinkRate == XDPTX_LINK_BW_SET_540GBPS)); - Xil_AssertVoid((LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_1) || - (LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_2) || - (LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4)); + Xil_AssertVoid((LinkConfig->LinkRate == XDP_TX_LINK_BW_SET_162GBPS) || + (LinkConfig->LinkRate == XDP_TX_LINK_BW_SET_270GBPS) || + (LinkConfig->LinkRate == XDP_TX_LINK_BW_SET_540GBPS)); + Xil_AssertVoid((LinkConfig->LaneCount == XDP_TX_LANE_COUNT_SET_1) || + (LinkConfig->LaneCount == XDP_TX_LANE_COUNT_SET_2) || + (LinkConfig->LaneCount == XDP_TX_LANE_COUNT_SET_4)); Xil_AssertVoid((MsaConfig->SynchronousClockMode == 0) || (MsaConfig->SynchronousClockMode == 1)); Xil_AssertVoid((MsaConfig->DynamicRange == 0) || @@ -145,11 +141,11 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream) * capabilities of the DisplayPort TX core. */ if (MsaConfig->OverrideUserPixelWidth == 0) { if ((MsaConfig->PixelClockHz > 300000000) && - (LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4)) { + (LinkConfig->LaneCount == XDP_TX_LANE_COUNT_SET_4)) { MsaConfig->UserPixelWidth = 4; } else if ((MsaConfig->PixelClockHz > 75000000) && - (LinkConfig->LaneCount != XDPTX_LANE_COUNT_SET_1)) { + (LinkConfig->LaneCount != XDP_TX_LANE_COUNT_SET_1)) { MsaConfig->UserPixelWidth = 2; } else { @@ -166,35 +162,35 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream) /* Miscellaneous attributes. */ if (MsaConfig->BitsPerColor == 6) { - MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC; + MsaConfig->Misc0 = XDP_TX_MAIN_STREAMX_MISC0_BDC_6BPC; } else if (MsaConfig->BitsPerColor == 8) { - MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC; + MsaConfig->Misc0 = XDP_TX_MAIN_STREAMX_MISC0_BDC_8BPC; } else if (MsaConfig->BitsPerColor == 10) { - MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC; + MsaConfig->Misc0 = XDP_TX_MAIN_STREAMX_MISC0_BDC_10BPC; } else if (MsaConfig->BitsPerColor == 12) { - MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC; + MsaConfig->Misc0 = XDP_TX_MAIN_STREAMX_MISC0_BDC_12BPC; } else if (MsaConfig->BitsPerColor == 16) { - MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC; + MsaConfig->Misc0 = XDP_TX_MAIN_STREAMX_MISC0_BDC_16BPC; } MsaConfig->Misc0 = (MsaConfig->Misc0 << - XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT) | + XDP_TX_MAIN_STREAMX_MISC0_BDC_SHIFT) | (MsaConfig->YCbCrColorimetry << - XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) | + XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) | (MsaConfig->DynamicRange << - XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) | + XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) | (MsaConfig->ComponentFormat << - XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) | + XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) | (MsaConfig->SynchronousClockMode); MsaConfig->Misc1 = 0; /* Determine the number of bits per pixel for the specified color * component format. */ if (MsaConfig->ComponentFormat == - XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422) { + XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422) { /* YCbCr422 color component format. */ BitsPerPixel = MsaConfig->BitsPerColor * 2; } @@ -212,13 +208,14 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream) MsaConfig->DataPerLane = WordsPerLine - LinkConfig->LaneCount; if ((WordsPerLine % LinkConfig->LaneCount) != 0) { - MsaConfig->DataPerLane += (WordsPerLine % LinkConfig->LaneCount); + MsaConfig->DataPerLane += + (WordsPerLine % LinkConfig->LaneCount); } - if (InstancePtr->MstEnable == 1) { + if (InstancePtr->TxInstance.MstEnable == 1) { /* Do time slot (and payload bandwidth number) calculations for * MST. */ - XDptx_CalculateTs(InstancePtr, Stream, BitsPerPixel); + XDp_TxCalculateTs(InstancePtr, Stream, BitsPerPixel); MsaConfig->InitWait = 0; } @@ -252,10 +249,10 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream) /** * This function sets the Main Stream Attribute (MSA) values in the * configuration structure to match one of the standard display mode timings - * from the XDptx_DmtModes[] standard Display Monitor Timing (DMT) table. The - * XDptx_VideoMode enumeration in xdptx.h lists the available video modes. + * from the XDp_TxDmtModes[] standard Display Monitor Timing (DMT) table. The + * XDp_TxVideoMode enumeration in xvidc.h lists the available video modes. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Stream is the stream number for which the MSA values will be * used for. * @param VideoMode is one of the enumerated standard video modes that is @@ -263,23 +260,23 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream) * * @return None. * - * @note The InstancePtr->MsaConfig structure is modified to reflect the - * MSA values associated to the specified video mode. + * @note The InstancePtr->TxInstance.MsaConfig structure is modified to + * reflect the MSA values associated to the specified video mode. * *******************************************************************************/ -void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr, u8 Stream, +void XDp_TxCfgMsaUseStandardVideoMode(XDp *InstancePtr, u8 Stream, XVidC_VideoMode VideoMode) { - XDptx_MainStreamAttributes *MsaConfig; + XDp_TxMainStreamAttributes *MsaConfig; /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(VideoMode < XVIDC_VM_NUM_SUPPORTED); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) || + (Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) || + (Stream == XDP_TX_STREAM_ID4)); - MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; + MsaConfig = &InstancePtr->TxInstance.MsaConfig[Stream - 1]; /* Configure the MSA values from the display monitor DMT table. */ MsaConfig->Vtm.VmId = XVidC_VideoTimingModes[VideoMode].VmId; @@ -322,7 +319,7 @@ void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr, u8 Stream, XVidC_GetPixelClockHzByVmId(MsaConfig->Vtm.VmId); /* Calculate the rest of the MSA values. */ - XDptx_CfgMsaRecalculate(InstancePtr, Stream); + XDp_TxCfgMsaRecalculate(InstancePtr, Stream); } /******************************************************************************/ @@ -332,86 +329,86 @@ void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr, u8 Stream, * Timing Mode (PTM) information is stored in the sink's Extended Display * Identification Data (EDID). * - * @param InstancePtr is a pointer to the XDptx instance + * @param InstancePtr is a pointer to the XDp instance. * @param Stream is the stream number for which the MSA values will be * used for. * @param Edid is a pointer to the Edid to use for the specified stream. * * @return None. * - * @note The InstancePtr->MsaConfig structure is modified to reflect the - * main stream attribute values associated to the preferred timing - * of the sink monitor. + * @note The InstancePtr->TxInstance.MsaConfig structure is modified to + * reflect the main stream attribute values associated to the + * preferred timing of the sink monitor. * *******************************************************************************/ -void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr, u8 Stream, u8 *Edid) +void XDp_TxCfgMsaUseEdidPreferredTiming(XDp *InstancePtr, u8 Stream, u8 *Edid) { - XDptx_MainStreamAttributes *MsaConfig; + XDp_TxMainStreamAttributes *MsaConfig; u8 *Ptm; /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) || + (Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) || + (Stream == XDP_TX_STREAM_ID4)); Xil_AssertVoid(Edid != NULL); - MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; - Ptm = &Edid[XDPTX_EDID_PTM]; + MsaConfig = &InstancePtr->TxInstance.MsaConfig[Stream - 1]; + Ptm = &Edid[XDP_EDID_PTM]; /* Configure the MSA values with the PTM information as * specified by the preferred Detailed Timing Descriptor (DTD) of the * monitor's EDID. * Note, the PTM is only required for EDID versions 1.3 a newer. Earlier * versions may not contain this information. */ - u16 HBlank = ((Ptm[XDPTX_EDID_DTD_HRES_HBLANK_U4] & - XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) | - Ptm[XDPTX_EDID_DTD_HBLANK_LSB]; + u16 HBlank = ((Ptm[XDP_EDID_DTD_HRES_HBLANK_U4] & + XDP_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) | + Ptm[XDP_EDID_DTD_HBLANK_LSB]; - u16 VBlank = ((Ptm[XDPTX_EDID_DTD_VRES_VBLANK_U4] & - XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) | - Ptm[XDPTX_EDID_DTD_VBLANK_LSB]; + u16 VBlank = ((Ptm[XDP_EDID_DTD_VRES_VBLANK_U4] & + XDP_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) | + Ptm[XDP_EDID_DTD_VBLANK_LSB]; MsaConfig->Vtm.Timing.HActive = - (((Ptm[XDPTX_EDID_DTD_HRES_HBLANK_U4] & - XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >> - XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) | - Ptm[XDPTX_EDID_DTD_HRES_LSB]; + (((Ptm[XDP_EDID_DTD_HRES_HBLANK_U4] & + XDP_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >> + XDP_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) | + Ptm[XDP_EDID_DTD_HRES_LSB]; MsaConfig->Vtm.Timing.VActive = - (((Ptm[XDPTX_EDID_DTD_VRES_VBLANK_U4] & - XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >> - XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) | - Ptm[XDPTX_EDID_DTD_VRES_LSB]; + (((Ptm[XDP_EDID_DTD_VRES_VBLANK_U4] & + XDP_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >> + XDP_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) | + Ptm[XDP_EDID_DTD_VRES_LSB]; - MsaConfig->PixelClockHz = (((Ptm[XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB] << - 8) | Ptm[XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB]) * 10) * 1000; + MsaConfig->PixelClockHz = (((Ptm[XDP_EDID_DTD_PIXEL_CLK_KHZ_MSB] << + 8) | Ptm[XDP_EDID_DTD_PIXEL_CLK_KHZ_LSB]) * 10) * 1000; MsaConfig->Vtm.Timing.HFrontPorch = - (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] & - XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK) >> - XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT) << 8) | - Ptm[XDPTX_EDID_DTD_HFPORCH_LSB]; + (((Ptm[XDP_EDID_DTD_XFPORCH_XSPW_U2] & + XDP_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK) >> + XDP_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT) << 8) | + Ptm[XDP_EDID_DTD_HFPORCH_LSB]; MsaConfig->Vtm.Timing.HSyncWidth = - (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] & - XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK) >> - XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT) << 8) | - Ptm[XDPTX_EDID_DTD_HSPW_LSB]; + (((Ptm[XDP_EDID_DTD_XFPORCH_XSPW_U2] & + XDP_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK) >> + XDP_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT) << 8) | + Ptm[XDP_EDID_DTD_HSPW_LSB]; MsaConfig->Vtm.Timing.F0PVFrontPorch = - (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] & - XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK) >> - XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT) << 8) | - ((Ptm[XDPTX_EDID_DTD_VFPORCH_VSPW_L4] & - XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK) >> - XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT); + (((Ptm[XDP_EDID_DTD_XFPORCH_XSPW_U2] & + XDP_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK) >> + XDP_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT) << 8) | + ((Ptm[XDP_EDID_DTD_VFPORCH_VSPW_L4] & + XDP_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK) >> + XDP_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT); MsaConfig->Vtm.Timing.F0PVSyncWidth = - ((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] & - XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK) << 8) | - (Ptm[XDPTX_EDID_DTD_VFPORCH_VSPW_L4] & - XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK); + ((Ptm[XDP_EDID_DTD_XFPORCH_XSPW_U2] & + XDP_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK) << 8) | + (Ptm[XDP_EDID_DTD_VFPORCH_VSPW_L4] & + XDP_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK); /* Compute video mode timing values. */ MsaConfig->Vtm.Timing.HBackPorch = HBlank - @@ -439,16 +436,16 @@ void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr, u8 Stream, u8 *Edid) MsaConfig->Vtm.VmId = XVIDC_VM_USE_EDID_PREFERRED; /* Calculate the rest of the MSA values. */ - XDptx_CfgMsaRecalculate(InstancePtr, Stream); + XDp_TxCfgMsaRecalculate(InstancePtr, Stream); } /******************************************************************************/ /** * This function takes a the main stream attributes from MsaConfigCustom and - * copies them into InstancePtr->MsaConfig. If desired, given a base set of - * attributes, the rest of the attributes may be derived. The minimal required - * main stream attributes (MSA) that must be contained in the MsaConfigCustom - * structure are: + * copies them into InstancePtr->TxInstance.MsaConfig. If desired, given a base + * set of attributes, the rest of the attributes may be derived. The minimal + * required main stream attributes (MSA) that must be contained in the + * MsaConfigCustom structure are: * - Pixel clock (in Hz) * - Frame rate * - Horizontal active resolution @@ -464,33 +461,34 @@ void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr, u8 Stream, u8 *Edid) * - Vertical total * - Vertical sync polarity * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Stream is the stream number for which the MSA values will be * used for. * @param MsaConfigCustom is the structure that will be used to copy the - * main stream attributes from (into InstancePtr->MsaConfig). + * main stream attributes from (into + * InstancePtr->TxInstance.MsaConfig). * @param Recalculate is a boolean enable that determines whether or not * the main stream attributes should be recalculated. * * @return None. * - * @note The InstancePtr->MsaConfig structure is modified with the new - * values. + * @note The InstancePtr->TxInstance.MsaConfig structure is modified with + * the new values. * *******************************************************************************/ -void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, u8 Stream, - XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate) +void XDp_TxCfgMsaUseCustom(XDp *InstancePtr, u8 Stream, + XDp_TxMainStreamAttributes *MsaConfigCustom, u8 Recalculate) { - XDptx_MainStreamAttributes *MsaConfig; + XDp_TxMainStreamAttributes *MsaConfig; /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) || + (Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) || + (Stream == XDP_TX_STREAM_ID4)); Xil_AssertVoid(MsaConfigCustom != NULL); - MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; + MsaConfig = &InstancePtr->TxInstance.MsaConfig[Stream - 1]; /* Copy the MSA values from the user configuration structure. */ MsaConfig->PixelClockHz = MsaConfigCustom->PixelClockHz; @@ -531,7 +529,7 @@ void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, u8 Stream, if (Recalculate) { /* Calculate the rest of the MSA values. */ - XDptx_CfgMsaRecalculate(InstancePtr, Stream); + XDp_TxCfgMsaRecalculate(InstancePtr, Stream); } else { /* Use the custom values for the rest. */ @@ -552,39 +550,40 @@ void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, u8 Stream, /** * This function sets the bits per color value of the video stream. * - * @param InstancePtr is a pointer to the XDptx instance + * @param InstancePtr is a pointer to the XDp instance. * @param Stream is the stream number for which to set the color depth. * @param BitsPerColor is the new number of bits per color to use. * * @return None. * - * @note The InstancePtr->MsaConfig structure is modified to reflect the - * new main stream attributes associated with a new bits per color - * value. + * @note The InstancePtr->TxInstance.MsaConfig structure is modified to + * reflect the new main stream attributes associated with a new + * bits per color value. * *******************************************************************************/ -void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 Stream, u8 BitsPerColor) +void XDp_TxCfgMsaSetBpc(XDp *InstancePtr, u8 Stream, u8 BitsPerColor) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) || + (Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) || + (Stream == XDP_TX_STREAM_ID4)); Xil_AssertVoid((BitsPerColor == 6) || (BitsPerColor == 8) || (BitsPerColor == 10) || (BitsPerColor == 12) || (BitsPerColor == 16)); - InstancePtr->MsaConfig[Stream - 1].BitsPerColor = BitsPerColor; + InstancePtr->TxInstance.MsaConfig[Stream - 1].BitsPerColor = + BitsPerColor; /* Calculate the rest of the MSA values. */ - XDptx_CfgMsaRecalculate(InstancePtr, Stream); + XDp_TxCfgMsaRecalculate(InstancePtr, Stream); } /******************************************************************************/ /** * This function enables or disables synchronous clock mode for a video stream. * - * @param InstancePtr is a pointer to the XDptx instance + * @param InstancePtr is a pointer to the XDp instance. * @param Stream is the stream number for which to enable or disable * synchronous clock mode. * @param Enable if set to 1, will enable synchronous clock mode. @@ -595,28 +594,29 @@ void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 Stream, u8 BitsPerColor) * @note None. * *******************************************************************************/ -void XDptx_CfgMsaEnSynchClkMode(XDptx *InstancePtr, u8 Stream, u8 Enable) +void XDp_TxCfgMsaEnSynchClkMode(XDp *InstancePtr, u8 Stream, u8 Enable) { - XDptx_MainStreamAttributes *MsaConfig; + XDp_TxMainStreamAttributes *MsaConfig; /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) || + (Stream == XDP_TX_STREAM_ID2) || + (Stream == XDP_TX_STREAM_ID3) || + (Stream == XDP_TX_STREAM_ID4)); Xil_AssertVoid((Enable == 0) || (Enable == 1)); - MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; + MsaConfig = &InstancePtr->TxInstance.MsaConfig[Stream - 1]; MsaConfig->SynchronousClockMode = Enable; if (Enable == 1) { MsaConfig->Misc0 |= (1 << - XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT); + XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT); } else { MsaConfig->Misc0 &= ~(1 << - XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT); + XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT); } } @@ -626,7 +626,7 @@ void XDptx_CfgMsaEnSynchClkMode(XDptx *InstancePtr, u8 Stream, u8 Enable) * TX core and sets them to the values specified in the main stream attributes * configuration structure. * - * @param InstancePtr is a pointer to the XDptx instance + * @param InstancePtr is a pointer to the XDp instance. * @param Stream is the stream number for which to set the MSA values for. * * @return None. @@ -634,17 +634,17 @@ void XDptx_CfgMsaEnSynchClkMode(XDptx *InstancePtr, u8 Stream, u8 Enable) * @note None. * *******************************************************************************/ -void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream) +void XDp_TxSetVideoMode(XDp *InstancePtr, u8 Stream) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) || + (Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) || + (Stream == XDP_TX_STREAM_ID4)); - XDptx_ClearMsaValues(InstancePtr, Stream); - XDptx_SetMsaValues(InstancePtr, Stream); + XDp_TxClearMsaValues(InstancePtr, Stream); + XDp_TxSetMsaValues(InstancePtr, Stream); } /******************************************************************************/ @@ -652,7 +652,7 @@ void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream) * This function clears the main stream attributes registers of the DisplayPort * TX core. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Stream is the stream number for which to clear the MSA values. * * @return None. @@ -660,60 +660,61 @@ void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream) * @note None. * *******************************************************************************/ -void XDptx_ClearMsaValues(XDptx *InstancePtr, u8 Stream) +void XDp_TxClearMsaValues(XDp *InstancePtr, u8 Stream) { XDp_Config *Config; - u32 StreamOffset[4] = {0, XDPTX_STREAM2_MSA_START_OFFSET, - XDPTX_STREAM3_MSA_START_OFFSET, XDPTX_STREAM4_MSA_START_OFFSET}; + u32 StreamOffset[4] = {0, XDP_TX_STREAM2_MSA_START_OFFSET, + XDP_TX_STREAM3_MSA_START_OFFSET, + XDP_TX_STREAM4_MSA_START_OFFSET}; /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) || + (Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) || + (Stream == XDP_TX_STREAM_ID4)); Config = &InstancePtr->Config; - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL + + XDp_WriteReg(Config->BaseAddr, XDP_TX_MAIN_STREAM_HTOTAL + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL + + XDp_WriteReg(Config->BaseAddr, XDP_TX_MAIN_STREAM_VTOTAL + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY + + XDp_WriteReg(Config->BaseAddr, XDP_TX_MAIN_STREAM_POLARITY + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH + + XDp_WriteReg(Config->BaseAddr, XDP_TX_MAIN_STREAM_HSWIDTH + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH + + XDp_WriteReg(Config->BaseAddr, XDP_TX_MAIN_STREAM_VSWIDTH + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES + + XDp_WriteReg(Config->BaseAddr, XDP_TX_MAIN_STREAM_HRES + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES + + XDp_WriteReg(Config->BaseAddr, XDP_TX_MAIN_STREAM_VRES + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART + + XDp_WriteReg(Config->BaseAddr, XDP_TX_MAIN_STREAM_HSTART + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART + + XDp_WriteReg(Config->BaseAddr, XDP_TX_MAIN_STREAM_VSTART + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0 + + XDp_WriteReg(Config->BaseAddr, XDP_TX_MAIN_STREAM_MISC0 + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1 + + XDp_WriteReg(Config->BaseAddr, XDP_TX_MAIN_STREAM_MISC1 + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH + + XDp_WriteReg(Config->BaseAddr, XDP_TX_USER_PIXEL_WIDTH + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE + + XDp_WriteReg(Config->BaseAddr, XDP_TX_USER_DATA_COUNT_PER_LANE + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID + + XDp_WriteReg(Config->BaseAddr, XDP_TX_M_VID + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID + + XDp_WriteReg(Config->BaseAddr, XDP_TX_N_VID + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_STREAM1 + (Stream - 1) * 4, 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE + + XDp_WriteReg(Config->BaseAddr, XDP_TX_STREAM1 + (Stream - 1) * 4, 0); + XDp_WriteReg(Config->BaseAddr, XDP_TX_TU_SIZE + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU + + XDp_WriteReg(Config->BaseAddr, XDP_TX_MIN_BYTES_PER_TU + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU + + XDp_WriteReg(Config->BaseAddr, XDP_TX_FRAC_BYTES_PER_TU + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT + + XDp_WriteReg(Config->BaseAddr, XDP_TX_INIT_WAIT + StreamOffset[Stream - 1], 0); } @@ -723,7 +724,7 @@ void XDptx_ClearMsaValues(XDptx *InstancePtr, u8 Stream) * core with the values specified in the main stream attributes configuration * structure. * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Stream is the stream number for which to set the MSA values for. * * @return None. @@ -731,81 +732,110 @@ void XDptx_ClearMsaValues(XDptx *InstancePtr, u8 Stream) * @note None. * *******************************************************************************/ -void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream) +void XDp_TxSetMsaValues(XDp *InstancePtr, u8 Stream) { - XDp_Config *Config; - XDptx_MainStreamAttributes *MsaConfig; - u32 StreamOffset[4] = {0, XDPTX_STREAM2_MSA_START_OFFSET, - XDPTX_STREAM3_MSA_START_OFFSET, XDPTX_STREAM4_MSA_START_OFFSET}; + XDp_Config *ConfigPtr; + XDp_TxMainStreamAttributes *MsaConfig; + u32 StreamOffset[4] = {0, XDP_TX_STREAM2_MSA_START_OFFSET, + XDP_TX_STREAM3_MSA_START_OFFSET, + XDP_TX_STREAM4_MSA_START_OFFSET}; /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) || + (Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) || + (Stream == XDP_TX_STREAM_ID4)); - Config = &InstancePtr->Config; - MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; + ConfigPtr = &InstancePtr->Config; + MsaConfig = &InstancePtr->TxInstance.MsaConfig[Stream - 1]; /* Set the main stream attributes to the associated DisplayPort TX core * registers. */ - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_MAIN_STREAM_HTOTAL + StreamOffset[Stream - 1], MsaConfig->Vtm.Timing.HTotal); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_MAIN_STREAM_VTOTAL + StreamOffset[Stream - 1], MsaConfig->Vtm.Timing.F0PVTotal); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_MAIN_STREAM_POLARITY + StreamOffset[Stream - 1], MsaConfig->Vtm.Timing.HSyncPolarity | (MsaConfig->Vtm.Timing.VSyncPolarity << - XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT)); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH + + XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT)); + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_MAIN_STREAM_HSWIDTH + StreamOffset[Stream - 1], MsaConfig->Vtm.Timing.HSyncWidth); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_MAIN_STREAM_VSWIDTH + StreamOffset[Stream - 1], MsaConfig->Vtm.Timing.F0PVSyncWidth); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_MAIN_STREAM_HRES + StreamOffset[Stream - 1], MsaConfig->Vtm.Timing.HActive); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_MAIN_STREAM_VRES + StreamOffset[Stream - 1], MsaConfig->Vtm.Timing.VActive); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_MAIN_STREAM_HSTART + StreamOffset[Stream - 1], MsaConfig->HStart); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_MAIN_STREAM_VSTART + StreamOffset[Stream - 1], MsaConfig->VStart); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0 + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_MAIN_STREAM_MISC0 + StreamOffset[Stream - 1], MsaConfig->Misc0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1 + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_MAIN_STREAM_MISC1 + StreamOffset[Stream - 1], MsaConfig->Misc1); - XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_M_VID + StreamOffset[Stream - 1], MsaConfig->PixelClockHz / 1000); - XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_N_VID + StreamOffset[Stream - 1], MsaConfig->NVid); - XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_USER_PIXEL_WIDTH + StreamOffset[Stream - 1], MsaConfig->UserPixelWidth); - XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_USER_DATA_COUNT_PER_LANE + StreamOffset[Stream - 1], MsaConfig->DataPerLane); /* Set the transfer unit values to the associated DisplayPort TX core * registers. */ - if (InstancePtr->MstEnable == 1) { - XDptx_WriteReg(Config->BaseAddr, - XDPTX_STREAM1 + (Stream - 1) * 4, + if (InstancePtr->TxInstance.MstEnable == 1) { + XDp_WriteReg(ConfigPtr->BaseAddr, + XDP_TX_STREAM1 + (Stream - 1) * 4, ((MsaConfig->AvgBytesPerTU / 1000) << 16) | (MsaConfig->AvgBytesPerTU % 1000)); } - XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_TU_SIZE + StreamOffset[Stream - 1], MsaConfig->TransferUnitSize); - XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_MIN_BYTES_PER_TU + StreamOffset[Stream - 1], MsaConfig->AvgBytesPerTU / 1000); - XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_FRAC_BYTES_PER_TU + StreamOffset[Stream - 1], MsaConfig->AvgBytesPerTU % 1000); - XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT + + XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_INIT_WAIT + StreamOffset[Stream - 1], MsaConfig->InitWait); } +/******************************************************************************/ +/** + * This function configures the number of pixels output through the user data + * interface. + * + * @param InstancePtr is a pointer to the XDp instance. + * @param UserPixelWidth is the user pixel width to be configured. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XDp_RxSetUserPixelWidth(XDp *InstancePtr, u8 UserPixelWidth) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((UserPixelWidth == 1) || (UserPixelWidth == 2) || + (UserPixelWidth == 4)); + + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_USER_PIXEL_WIDTH, + UserPixelWidth); + + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_SOFT_RESET, 0x1); + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_SOFT_RESET, 0x0); +} + /******************************************************************************/ /** * When the driver is in multi-stream transport (MST) mode, this function will @@ -814,7 +844,7 @@ void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream) * required for allocating the bandwidth, and the average bytes per transfer * unit (both the integer and the fractional part). * - * @param InstancePtr is a pointer to the XDptx instance. + * @param InstancePtr is a pointer to the XDp instance. * @param Stream is the stream number to make the calculations for. * @param BitsPerPixel is the number of bits that is used to store one * pixel. @@ -824,11 +854,11 @@ void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream) * @note None. * *******************************************************************************/ -static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel) +static void XDp_TxCalculateTs(XDp *InstancePtr, u8 Stream, u8 BitsPerPixel) { - XDptx_MainStreamAttributes *MsaConfig = - &InstancePtr->MsaConfig[Stream - 1]; - XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; + XDp_TxMainStreamAttributes *MsaConfig = + &InstancePtr->TxInstance.MsaConfig[Stream - 1]; + XDp_TxLinkConfig *LinkConfig = &InstancePtr->TxInstance.LinkConfig; double PeakPixelBw; u32 LinkBw; double Average_StreamSymbolTimeSlotsPerMTP; @@ -842,19 +872,20 @@ static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel) LinkBw = (LinkConfig->LaneCount * LinkConfig->LinkRate * 27); /* Calculate the payload bandiwdth number (PBN). */ - InstancePtr->MstStreamConfig[Stream - 1].MstPbn = + InstancePtr->TxInstance.MstStreamConfig[Stream - 1].MstPbn = 1.006 * PeakPixelBw * ((double)64 / 54); /* Ceil - round up if required, avoiding overhead of math.h. */ if ((double)(1.006 * PeakPixelBw * ((double)64 / 54)) > - ((double)InstancePtr->MstStreamConfig[Stream - 1].MstPbn)) { - InstancePtr->MstStreamConfig[Stream - 1].MstPbn++; + ((double)InstancePtr->TxInstance.MstStreamConfig[ + Stream - 1].MstPbn)) { + InstancePtr->TxInstance.MstStreamConfig[Stream - 1].MstPbn++; } /* Calculate the average stream symbol time slots per MTP. */ Average_StreamSymbolTimeSlotsPerMTP = (64.0 * PeakPixelBw / LinkBw); MaximumTarget_Average_StreamSymbolTimeSlotsPerMTP = (54.0 * - ((double)InstancePtr->MstStreamConfig[Stream - 1].MstPbn / - LinkBw)); + ((double)InstancePtr->TxInstance.MstStreamConfig[Stream - 1]. + MstPbn / LinkBw)); /* The target value to be found needs to follow the condition: * Average_StreamSymbolTimeSlotsPerMTP <= @@ -898,7 +929,7 @@ static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel) } /* Determine the PBN for the stream. */ - InstancePtr->MstStreamConfig[Stream - 1].MstPbn = + InstancePtr->TxInstance.MstStreamConfig[Stream - 1].MstPbn = MsaConfig->TransferUnitSize * (LinkConfig->LaneCount * LinkConfig->LinkRate / 2); } diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdprx.c b/XilinxProcessorIPLib/drivers/dp/src/xdprx.c deleted file mode 100644 index fb857cad..00000000 --- a/XilinxProcessorIPLib/drivers/dp/src/xdprx.c +++ /dev/null @@ -1,510 +0,0 @@ -/******************************************************************************* - * - * Copyright (C) 2015 Xilinx, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * Use of the Software is limited solely to applications: - * (a) running on a Xilinx device, or - * (b) that interact with a Xilinx device through a bus or interconnect. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Except as contained in this notice, the name of the Xilinx shall not be used - * in advertising or otherwise to promote the sale, use or other dealings in - * this Software without prior written authorization from Xilinx. - * -*******************************************************************************/ -/******************************************************************************/ -/** - * - * @file xdprx.c - * - * Contains a minimal set of functions for the XDprx driver that allow access - * to all of the DisplayPort RX core's functionality. See xdprx.h for a detailed - * description of the driver. - * - * @note None. - * - *
- * MODIFICATION HISTORY:
- *
- * Ver   Who  Date     Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0   als  01/20/14 Initial release.
- * 
- * -*******************************************************************************/ - -/******************************* Include Files ********************************/ - -#include "xdprx.h" -#include "xstatus.h" -#if defined(__arm__) -#include "sleep.h" -#elif defined(__MICROBLAZE__) -#include "microblaze_sleep.h" -#endif - -/**************************** Function Prototypes *****************************/ - -static u32 XDprx_WaitPhyReady(XDprx *InstancePtr, u8 Mask); - -/**************************** Function Definitions ****************************/ - -/******************************************************************************/ -/** - * This function retrieves the configuration for this DisplayPort RX instance - * and fills in the InstancePtr->Config structure. - * - * @param InstancePtr is a pointer to the XDprx instance. - * @param ConfigPtr is a pointer to the configuration structure that will - * be used to copy the settings from. - * @param EffectiveAddr is the device base address in the virtual memory - * space. If the address translation is not used, then the physical - * address is passed. - * - * @return None. - * - * @note Unexpected errors may occur if the address mapping is changed - * after this function is invoked. - * -*******************************************************************************/ -void XDprx_CfgInitialize(XDprx *InstancePtr, XDp_Config *ConfigPtr, - u32 EffectiveAddr) -{ - /* Verify arguments. */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(ConfigPtr != NULL); - Xil_AssertVoid(EffectiveAddr != 0x0); - - InstancePtr->IsReady = 0; - - InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; - InstancePtr->Config.BaseAddr = EffectiveAddr; - InstancePtr->Config.SAxiClkHz = ConfigPtr->SAxiClkHz; - - InstancePtr->Config.MaxLaneCount = ConfigPtr->MaxLaneCount; - InstancePtr->Config.MaxLinkRate = ConfigPtr->MaxLinkRate; - - InstancePtr->Config.MaxBitsPerColor = ConfigPtr->MaxBitsPerColor; - InstancePtr->Config.QuadPixelEn = ConfigPtr->QuadPixelEn; - InstancePtr->Config.DualPixelEn = ConfigPtr->DualPixelEn; - InstancePtr->Config.YCrCbEn = ConfigPtr->YCrCbEn; - InstancePtr->Config.YOnlyEn = ConfigPtr->YOnlyEn; - InstancePtr->Config.PayloadDataWidth = ConfigPtr->PayloadDataWidth; - - InstancePtr->Config.SecondaryChEn = ConfigPtr->SecondaryChEn; - InstancePtr->Config.NumAudioChs = ConfigPtr->NumAudioChs; - - InstancePtr->Config.MstSupport = ConfigPtr->MstSupport; - InstancePtr->Config.NumMstStreams = ConfigPtr->NumMstStreams; - - InstancePtr->Config.DpProtocol = ConfigPtr->DpProtocol; - - InstancePtr->Config.IsRx = ConfigPtr->IsRx; - - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; -} - -/******************************************************************************/ -/** - * This function prepares the DisplayPort RX core for use. - * - * @param InstancePtr is a pointer to the XDprx instance. - * - * @return - * - XST_SUCCESS if the DisplayPort RX core was successfully - * initialized. - * - XST_FAILURE otherwise. - * - * @note None. - * -*******************************************************************************/ -u32 XDprx_InitializeRx(XDprx *InstancePtr) -{ - u32 Status; - - /* Verify arguments. */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* Disable the main link. */ - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_LINK_ENABLE, 0x0); - - /* Set the AUX clock divider. */ - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_AUX_CLK_DIVIDER, - (InstancePtr->Config.SAxiClkHz / 1000000)); - - /* Put both GT RX/TX and CPLL into reset. */ - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_PHY_CONFIG, - XDPRX_PHY_CONFIG_GTPLL_RESET_MASK | - XDPRX_PHY_CONFIG_GTRX_RESET_MASK); - - /* Release CPLL reset. */ - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_PHY_CONFIG, - XDPRX_PHY_CONFIG_GTRX_RESET_MASK); - - /* Wait until all lane CPLLs have locked. */ - Status = XDprx_WaitPhyReady(InstancePtr, - XDPRX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK | - XDPRX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK); - if (Status != XST_SUCCESS) { - return XST_FAILURE; - } - - /* Remove the reset from the PHY. */ - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_PHY_CONFIG, - XDPRX_PHY_CONFIG_PHY_RESET_ENABLE_MASK); - - /* Wait until the PHY has completed the reset cycle. */ - Status = XDprx_WaitPhyReady(InstancePtr, - XDPRX_PHY_STATUS_ALL_LANES_READY_MASK | - XDPRX_PHY_STATUS_PLL_FABRIC_LOCK_MASK | - XDPRX_PHY_STATUS_RX_CLK_LOCK_MASK); - if (Status != XST_SUCCESS) { - return XST_FAILURE; - } - - /* Enable the RX core. */ - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_LINK_ENABLE, 0x1); - - /* Set other user parameters. */ - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_MIN_VOLTAGE_SWING, - 0x01); - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SINK_COUNT, 0x01); - /* Set the AUX training interval. */ - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD, 0x1); - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_TP_SET, - (2 << XDPRX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_SHIFT)); - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD, 0x0); - /* Set the link configuration.*/ - XDprx_SetLinkRate(InstancePtr, InstancePtr->LinkConfig.LinkRate); - XDprx_SetLaneCount(InstancePtr, InstancePtr->LinkConfig.LaneCount); - /* Set the interrupt masks. */ - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_INTERRUPT_MASK, - ~XDPRX_INTERRUPT_MASK_ALL_MASK); - - /* Enable the display timing generator. */ - XDprx_DtgEn(InstancePtr); - - return XST_SUCCESS; -} - -/******************************************************************************/ -/** - * This function checks if the reciever's internal registers indicate that link - * training has complete. That is, training has achieved channel equalization, - * symbol lock, and interlane alignment for all lanes currently in use. - * - * @param InstancePtr is a pointer to the XDprx instance. - * - * @return - * - XST_SUCCESS if the RX device has achieved clock recovery, - * channel equalization, symbol lock, and interlane alignment. - * - XST_FAILURE otherwise. - * - * @note None. - * -*******************************************************************************/ -u32 XDprx_CheckLinkStatus(XDprx *InstancePtr) -{ - u8 LaneCount; - u8 LaneStatus[2]; - - /* Verify arguments. */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - LaneCount = XDprx_ReadReg(InstancePtr->Config.BaseAddr, - XDPRX_DPCD_LANE_COUNT_SET); - - LaneStatus[0] = XDprx_ReadReg(InstancePtr->Config.BaseAddr, - XDPRX_DPCD_LANE01_STATUS); - LaneStatus[1] = XDprx_ReadReg(InstancePtr->Config.BaseAddr, - XDPRX_DPCD_LANE23_STATUS); - - switch (LaneCount) { - case 4: - if (LaneStatus[1] != 0x77) { - return XST_FAILURE; - } - case 2: - if ((LaneStatus[0] & 0x70) != 0x70) { - return XST_FAILURE; - } - case 1: - if ((LaneStatus[0] & 0x07) != 0x07) { - return XST_FAILURE; - } - } - - return XST_SUCCESS; -} - -/******************************************************************************/ -/** - * This function enables the display timing generator (DTG). - * - * @param InstancePtr is a pointer to the XDprx instance. - * - * @return None. - * - * @note None. - * -*******************************************************************************/ -void XDprx_DtgEn(XDprx *InstancePtr) -{ - /* Verify arguments. */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, - XDPRX_SOFT_RESET_VIDEO_MASK); - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x0); - - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_DTG_ENABLE, 0x1); -} - -/******************************************************************************/ -/** - * This function disables the display timing generator (DTG). - * - * @param InstancePtr is a pointer to the XDprx instance. - * - * @return None. - * - * @note None. - * -*******************************************************************************/ -void XDprx_DtgDis(XDprx *InstancePtr) -{ - /* Verify arguments. */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_DTG_ENABLE, 0x0); - - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, - XDPRX_SOFT_RESET_VIDEO_MASK); - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x0); -} - -/******************************************************************************/ -/** - * This function sets the maximum data rate to be exposed in the RX device's - * DisplayPort Configuration Data (DPCD) registers. - * - * @param InstancePtr is a pointer to the XDprx instance. - * @param LinkRate is the link rate to be used over the main link based on - * one of the following selects: - * - XDPRX_LINK_BW_SET_162GBPS = 0x06 (for a 1.62 Gbps data rate) - * - XDPRX_LINK_BW_SET_270GBPS = 0x0A (for a 2.70 Gbps data rate) - * - XDPRX_LINK_BW_SET_540GBPS = 0x14 (for a 5.40 Gbps data rate) - * - * @return None. - * - * @note None. - * -*******************************************************************************/ -void XDprx_SetLinkRate(XDprx *InstancePtr, u8 LinkRate) -{ - /* Verify arguments. */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((LinkRate == XDPRX_OVER_LINK_BW_SET_162GBPS) || - (LinkRate == XDPRX_OVER_LINK_BW_SET_270GBPS) || - (LinkRate == XDPRX_OVER_LINK_BW_SET_540GBPS)); - - InstancePtr->LinkConfig.LinkRate = LinkRate; - - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD, 0x1); - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_LINK_BW_SET, - LinkRate); - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD, 0x0); - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_LOCAL_EDID_VIDEO, - 0x1); -} - -/******************************************************************************/ -/** - * This function sets the maximum lane count to be exposed in the RX device's - * DisplayPort Configuration Data (DPCD) registers. - * - * @param InstancePtr is a pointer to the XDprx instance. - * @param LaneCount is the number of lanes to be used over the main link. - * - * @return None. - * - * @note None. - * -*******************************************************************************/ -void XDprx_SetLaneCount(XDprx *InstancePtr, u8 LaneCount) -{ - /* Verify arguments. */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((LaneCount == XDPRX_OVER_LANE_COUNT_SET_1) || - (LaneCount == XDPRX_OVER_LANE_COUNT_SET_2) || - (LaneCount == XDPRX_OVER_LANE_COUNT_SET_4)); - - InstancePtr->LinkConfig.LaneCount = LaneCount; - - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD, 0x1); - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_LANE_COUNT_SET, - LaneCount); - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_OVER_CTRL_DPCD, 0x0); - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_LOCAL_EDID_VIDEO, - 0x1); -} - -/******************************************************************************/ -/** - * This function configures the number of pixels output through the user data - * interface. - * - * @param InstancePtr is a pointer to the XDprx instance. - * @param UserPixelWidth is the user pixel width to be configured. - * - * @return None. - * - * @note None. - * -*******************************************************************************/ -void XDprx_SetUserPixelWidth(XDprx *InstancePtr, u8 UserPixelWidth) -{ - /* Verify arguments. */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((UserPixelWidth == 1) || (UserPixelWidth == 2) || - (UserPixelWidth == 4)); - - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_USER_PIXEL_WIDTH, - UserPixelWidth); - - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x1); - XDprx_WriteReg(InstancePtr->Config.BaseAddr, XDPRX_SOFT_RESET, 0x0); -} - -/******************************************************************************/ -/** - * This function installs a custom delay/sleep function to be used by the XDprx - * driver. - * - * @param InstancePtr is a pointer to the XDprx instance. - * @param CallbackFunc is the address to the callback function. - * @param CallbackRef is the user data item (microseconds to delay) that - * will be passed to the custom sleep/delay function when it is - * invoked. - * - * @return None. - * - * @note None. - * -*******************************************************************************/ -void XDprx_SetUserTimerHandler(XDprx *InstancePtr, - XDp_TimerHandler CallbackFunc, void *CallbackRef) -{ - /* Verify arguments. */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(CallbackFunc != NULL); - Xil_AssertVoid(CallbackRef != NULL); - - InstancePtr->UserTimerWaitUs = CallbackFunc; - InstancePtr->UserTimerPtr = CallbackRef; -} - -/******************************************************************************/ -/** - * This function is the delay/sleep function for the XDprx driver. For the Zynq - * family, there exists native sleep functionality. For MicroBlaze however, - * there does not exist such functionality. In the MicroBlaze case, the default - * method for delaying is to use a predetermined amount of loop iterations. This - * method is prone to inaccuracy and dependent on system configuration; for - * greater accuracy, the user may supply their own delay/sleep handler, pointed - * to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a - * hardware timer is used. - * - * @param InstancePtr is a pointer to the XDprx instance. - * @param MicroSeconds is the number of microseconds to delay/sleep for. - * - * @return None. - * - * @note None. - * -*******************************************************************************/ -void XDprx_WaitUs(XDprx *InstancePtr, u32 MicroSeconds) -{ - /* Verify arguments. */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - if (MicroSeconds == 0) { - return; - } - -#if defined(__arm__) - /* Wait the requested amount of time. */ - usleep(MicroSeconds); -#elif defined(__MICROBLAZE__) - if (InstancePtr->UserTimerWaitUs != NULL) { - /* Use the timer handler specified by the user for better - * accuracy. */ - InstancePtr->UserTimerWaitUs(InstancePtr, MicroSeconds); - } - else { - /* MicroBlaze sleep only has millisecond accuracy. Round up. */ - u32 MilliSeconds = (MicroSeconds + 999) / 1000; - MB_Sleep(MilliSeconds); - } -#endif -} - -/******************************************************************************/ -/** - * This function waits for the DisplayPort PHY to come out of reset. - * - * @param InstancePtr is a pointer to the XDprx instance. - * @param Mask specifies which bits to wait for the PHY to be ready on. - * - * @return - * - XST_ERROR_COUNT_MAX if the PHY failed to be ready. - * - XST_SUCCESS otherwise. - * - * @note None. - * -*******************************************************************************/ -static u32 XDprx_WaitPhyReady(XDprx *InstancePtr, u8 Mask) -{ - u16 Timeout = 20000; - u32 PhyStatus; - - /* Wait until the PHY is ready. */ - do { - PhyStatus = XDprx_ReadReg(InstancePtr->Config.BaseAddr, - XDPRX_PHY_STATUS) & Mask; - - /* Protect against an infinite loop. */ - if (!Timeout--) { - return XST_ERROR_COUNT_MAX; - } - XDprx_WaitUs(InstancePtr, 20); - } - while (PhyStatus != Mask); - - return XST_SUCCESS; -} diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdprx.h b/XilinxProcessorIPLib/drivers/dp/src/xdprx.h deleted file mode 100644 index ebc33cb9..00000000 --- a/XilinxProcessorIPLib/drivers/dp/src/xdprx.h +++ /dev/null @@ -1,272 +0,0 @@ -/******************************************************************************* - * - * Copyright (C) 2015 Xilinx, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * Use of the Software is limited solely to applications: - * (a) running on a Xilinx device, or - * (b) that interact with a Xilinx device through a bus or interconnect. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Except as contained in this notice, the name of the Xilinx shall not be used - * in advertising or otherwise to promote the sale, use or other dealings in - * this Software without prior written authorization from Xilinx. - * -*******************************************************************************/ -/******************************************************************************/ -/** - * - * @file xdprx.h - * - * The Xilinx DisplayPort receiver (DPRX) driver. This driver supports the - * Xilinx DisplayPort soft IP core in receive (RX) mode. - * - * Driver description - * - * The device driver enables higher-level software (e.g., an application) to - * configure and control a DisplayPort RX soft IP. - * - * This driver gives applications the ability to configure the RX using various - * settings, handle and issue interrupts, and modify a subset of its DisplayPort - * Configuration Data (DPCD) fields. - * - * Interrupt processing - * - * The DisplayPort RX driver may generate a pulse on the hot-plug-detect (HPD) - * signal line using the XDprx_GenerateHpdInterrupt function. This allows the RX - * to send an interrupt to the upstream TX device, useful for signaling the TX - * that it needs to do some checks for changes in downstream devices or a loss - * of link training. - * - * For RX interrupt handling of HPD events or events that happen internal to the - * RX, the user hardware design must contain an interrupt controller which the - * DisplayPort RX instance's interrupt signal is connected to. The user - * application must enable interrupts in the system and set up the interrupt - * controller such that the XDprx_InterruptHandler handler will service - * interrupts. When the XDprx_InterruptHandler function is invoked, the handler - * will identify what type of interrupt has occurred, and will call the - * appropriate interrupt handler. - * - * The DisplayPort RX's XDPRX_INTERRUPT_CAUSE register indicates the type of - * interrupt that has occured, and the XDprx_InterruptHandler will use this - * information to decide which handler to call. - * - * The handlers are set up using the XDprx_SetIntr* functions. - * - * Specific interrupts may be enabled or disabled using the - * XDprx_InterruptEnable and XDprx_InterruptDisable functions. - * - * Multi-stream transport (MST) mode - * - * The DisplayPort RX driver does not support MST functionality in 2015.1. - * - * Audio - * - * The driver does not handle audio. - * - * @note None. - * - *
- * MODIFICATION HISTORY:
- *
- * Ver   Who  Date     Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0   als  01/20/14 Initial release.
- * 
- * -*******************************************************************************/ - -#ifndef XDPRX_H_ -/* Prevent circular inclusions by using protection macros. */ -#define XDPRX_H_ - -/******************************* Include Files ********************************/ - -#include "xdp.h" -#include "xdprx_hw.h" - -/****************************** Type Definitions ******************************/ - -/** - * This typedef contains configuration information about the main link settings. - */ -typedef struct { - u8 LaneCount; /**< The current lane count of the main - link. */ - u8 LinkRate; /**< The current link rate of the main - link. */ -} XDprx_LinkConfig; - -/******************************************************************************/ -/** - * Callback type which represents the handler for interrupts. - * - * @param InstancePtr is a pointer to the XDprx instance. - * - * @note None. - * -*******************************************************************************/ -typedef void (*XDprx_IntrHandler)(void *InstancePtr); - -/** - * The XDprx driver instance data. The user is required to allocate a variable - * of this type for every XDprx device in the system. A pointer to a variable of - * this type is then passed to the driver API functions. - */ -typedef struct { - XDp_Config Config; /**< Configuration structure for - the DisplayPort RX - core. It is important to - keep this member first - in the XDprx order. */ - u32 IsReady; /**< Device is initialized and - ready. */ - XDprx_LinkConfig LinkConfig; /**< Configuration structure for - the main link. */ - XDp_TimerHandler UserTimerWaitUs; /**< Custom user function for - delay/sleep. */ - void *UserTimerPtr; /**< Pointer to a timer instance - used by the custom user - delay/sleep function. */ - XDprx_IntrHandler IntrVmChangeHandler; /**< Callback function for video - mode change - interrupts. */ - void *IntrVmChangeCallbackRef; /**< A pointer to the user data - passed to the video mode - change callback - function. */ - XDprx_IntrHandler IntrPowerStateHandler; /**< Callback function for - power state change - interrupts. */ - void *IntrPowerStateCallbackRef; /**< A pointer to the user data - passed to the power - state change callback - function. */ - XDprx_IntrHandler IntrNoVideoHandler; /**< Callback function for - no video interrupts. */ - void *IntrNoVideoCallbackRef; /**< A pointer to the user data - passed to the no video - callback function. */ - XDprx_IntrHandler IntrVBlankHandler; /**< Callback function for - vertical blanking - interrupts. */ - void *IntrVBlankCallbackRef; /**< A pointer to the user data - passed to the vertical - blanking callback - function. */ - XDprx_IntrHandler IntrTrainingLostHandler; /**< Callback function for - training lost - interrupts. */ - void *IntrTrainingLostCallbackRef; /**< A pointer to the user data - passed to the training - lost callback - function. */ - XDprx_IntrHandler IntrVideoHandler; /**< Callback function for valid - video interrupts. */ - void *IntrVideoCallbackRef; /**< A pointer to the user data - passed to the valid - video callback - function. */ - XDprx_IntrHandler IntrTrainingDoneHandler; /**< Callback function for - training done - interrupts. */ - void *IntrTrainingDoneCallbackRef; /**< A pointer to the user data - passed to the training - done callback - function. */ - XDprx_IntrHandler IntrBwChangeHandler; /**< Callback function for - bandwidth change - interrupts. */ - void *IntrBwChangeCallbackRef; /**< A pointer to the user data - passed to the bandwidth - change callback - function. */ - XDprx_IntrHandler IntrTp1Handler; /**< Callback function for - training pattern 1 - interrupts. */ - void *IntrTp1CallbackRef; /**< A pointer to the user data - passed to the training - pattern 1 callback - function. */ - XDprx_IntrHandler IntrTp2Handler; /**< Callback function for - training pattern 2 - interrupts. */ - void *IntrTp2CallbackRef; /**< A pointer to the user data - passed to the training - pattern 2 callback - function. */ - XDprx_IntrHandler IntrTp3Handler; /**< Callback function for - training pattern 3 - interrupts. */ - void *IntrTp3CallbackRef; /**< A pointer to the user data - passed to the training - pattern 3 callback - function. */ -} XDprx; - -/**************************** Function Prototypes *****************************/ - -/* xdprx.c: Setup and initialization functions. */ -void XDprx_CfgInitialize(XDprx *InstancePtr, XDp_Config *ConfigPtr, - u32 EffectiveAddr); -u32 XDprx_InitializeRx(XDprx *InstancePtr); - -/* xdprx.c: General usage functions. */ -u32 XDprx_CheckLinkStatus(XDprx *InstancePtr); -void XDprx_DtgEn(XDprx *InstancePtr); -void XDprx_DtgDis(XDprx *InstancePtr); -void XDprx_SetLinkRate(XDprx *InstancePtr, u8 LinkRate); -void XDprx_SetLaneCount(XDprx *InstancePtr, u8 LaneCount); -void XDprx_SetUserPixelWidth(XDprx *InstancePtr, u8 UserPixelWidth); -void XDprx_SetUserTimerHandler(XDprx *InstancePtr, - XDp_TimerHandler CallbackFunc, void *CallbackRef); -void XDprx_WaitUs(XDprx *InstancePtr, u32 MicroSeconds); - -/* xdprx_intr.c: Interrupt handling functions. */ -void XDprx_InterruptHandler(XDprx *InstancePtr); -void XDprx_GenerateHpdInterrupt(XDprx *InstancePtr, u16 DurationUs); -void XDprx_InterruptEnable(XDprx *InstancePtr, u32 Mask); -void XDprx_InterruptDisable(XDprx *InstancePtr, u32 Mask); -void XDprx_SetIntrVmChangeHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef); -void XDprx_SetIntrPowerStateHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef); -void XDprx_SetIntrNoVideoHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef); -void XDprx_SetIntrVBlankHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef); -void XDprx_SetIntrTrainingLostHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef); -void XDprx_SetIntrVideoHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef); -void XDprx_SetIntrTrainingDoneHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef); -void XDprx_SetIntrBwChangeHandler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef); -void XDprx_SetIntrTp1Handler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef); -void XDprx_SetIntrTp2Handler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef); -void XDprx_SetIntrTp3Handler(XDprx *InstancePtr, - XDprx_IntrHandler CallbackFunc, void *CallbackRef); - -/* xdprx_selftest.c: Self test function. */ -u32 XDprx_SelfTest(XDprx *InstancePtr); - -#endif /* XDPRX_H_ */ diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdprx_hw.h b/XilinxProcessorIPLib/drivers/dp/src/xdprx_hw.h deleted file mode 100644 index ae9231cb..00000000 --- a/XilinxProcessorIPLib/drivers/dp/src/xdprx_hw.h +++ /dev/null @@ -1,1121 +0,0 @@ -/******************************************************************************* - * - * Copyright (C) 2015 Xilinx, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * Use of the Software is limited solely to applications: - * (a) running on a Xilinx device, or - * (b) that interact with a Xilinx device through a bus or interconnect. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Except as contained in this notice, the name of the Xilinx shall not be used - * in advertising or otherwise to promote the sale, use or other dealings in - * this Software without prior written authorization from Xilinx. - * -*******************************************************************************/ -/******************************************************************************/ -/** - * - * @file xdprx_hw.h - * - * This header file contains the identifiers and low-level driver functions (or - * macros) that can be used to access the device. High-level driver functions - * are defined in xdprx.h. - * - * @note None. - * - *
- * MODIFICATION HISTORY:
- *
- * Ver   Who  Date     Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0   als  01/20/14 Initial release.
- * 
- * -*******************************************************************************/ - -#ifndef XDPRX_HW_H_ -/* Prevent circular inclusions by using protection macros. */ -#define XDPRX_HW_H_ - -/***************************** Include Files **********************************/ - -#include "xil_io.h" - -/************************** Constant Definitions ******************************/ - -/** @name DPRX core registers: Receiver core configuration. - * @{ - */ -#define XDPRX_LINK_ENABLE 0x000 /**< Enable the receiver - core. */ -#define XDPRX_AUX_CLK_DIVIDER 0x004 /**< Clock divider value for - generating the internal - 1MHz clock. */ -#define XDPRX_DTG_ENABLE 0x00C /**< Enables the display timing - generator (DTG). */ -#define XDPRX_USER_PIXEL_WIDTH 0x010 /**< Selects the width of the - user data input port. */ -#define XDPRX_INTERRUPT_MASK 0x014 /**< Masks the specified - interrupt sources for - stream 1. */ -#define XDPRX_MISC_CTRL 0x018 /**< Miscellaneous control of - RX behavior. */ -#define XDPRX_SOFT_RESET 0x01C /**< Software reset. */ -/* @} */ - -/** @name DPRX core registers: AUX channel status. - * @{ - */ -#define XDPRX_AUX_REQ_IN_PROGRESS 0x020 /**< Indicates the receipt of an - AUX channel request. */ -#define XDPRX_REQ_ERROR_COUNT 0x024 /**< Provides a running total of - errors detected on - inbound AUX channel - requests. */ -#define XDPRX_REQ_COUNT 0x028 /**< Provides a running total of - the number of AUX - requests received. */ -#define XDPRX_HPD_INTERRUPT 0x02C /**< Instructs the DisplayPort - RX core to assert an - interrupt to the TX - using the HPD signal. */ -#define XDPRX_REQ_CLK_WIDTH 0x030 /**< Holds the half period of - the recovered AUX - clock. */ -#define XDPRX_REQ_CMD 0x034 /**< Provides the most recent - AUX command received. */ -#define XDPRX_REQ_ADDRESS 0x038 /**< Contains the address field - of the most recent AUX - request. */ -#define XDPRX_REQ_LENGTH 0x03C /**< Contains length of the most - recent AUX request. */ -/* @} */ - -/** @name DPRX core registers: Interrupt registers. - * @{ - */ -#define XDPRX_INTERRUPT_CAUSE 0x040 /**< Indicates the cause of - pending host interrupts - for stream 1, training, - payload allocation, and - for the AUX channel. */ -#define XDPRX_INTERRUPT_MASK_1 0x044 /**< Masks the specified - interrupt sources for - streams 2, 3, 4. */ -#define XDPRX_INTERRUPT_CAUSE_1 0x048 /**< Indicates the cause of a - pending host interrupts - for streams 2, 3, 4. */ -#define XDPRX_HSYNC_WIDTH 0x050 /**< Controls the timing of the - active-high horizontal - sync pulse generated - by the display timing - generator (DTG). */ -#define XDPRX_FAST_I2C_DIVIDER 0x060 /**< Fast I2C mode clock divider - value. */ -/* @} */ - -/** @name DPRX core registers: DPCD fields. - * @{ - */ -#define XDPRX_LOCAL_EDID_VIDEO 0x084 /**< Indicates the presence of - EDID information for the - video stream. */ -#define XDPRX_LOCAL_EDID_AUDIO 0x088 /**< Indicates the presence of - EDID information for the - audio stream. */ -#define XDPRX_REMOTE_CMD 0x08C /**< Used for passing remote - information to the - DisplayPort TX. */ -#define XDPRX_DEVICE_SERVICE_IRQ 0x090 /**< Indicates the DPCD - DEVICE_SERVICE_IRQ_ - VECTOR state. */ -#define XDPRX_VIDEO_UNSUPPORTED 0x094 /**< DPCD register bit to inform - the DisplayPort TX that - video data is not - supported. */ -#define XDPRX_AUDIO_UNSUPPORTED 0x098 /**< DPCD register bit to inform - the DisplayPort TX that - audio data is not - supported. */ -#define XDPRX_OVER_LINK_BW_SET 0x09C /**< Used to override the main - link bandwidth setting - in the DPCD. */ -#define XDPRX_OVER_LANE_COUNT_SET 0x0A0 /**< Used to override the lane - count setting in the - DPCD. */ -#define XDPRX_OVER_TP_SET 0x0A4 /**< Used to override the link - training pattern in the - DPCD. */ -#define XDPRX_OVER_TRAINING_LANE0_SET 0x0A8 /**< Used to override the - TRAINING_LANE0_SET - register in the DPCD. */ -#define XDPRX_OVER_TRAINING_LANE1_SET 0x0AC /**< Used to override the - TRAINING_LANE1_SET - register in the DPCD. */ -#define XDPRX_OVER_TRAINING_LANE2_SET 0x0B0 /**< Used to override the - TRAINING_LANE2_SET - register in the DPCD. */ -#define XDPRX_OVER_TRAINING_LANE3_SET 0x0B4 /**< Used to override the - TRAINING_LANE3_SET - register in the DPCD. */ -#define XDPRX_OVER_CTRL_DPCD 0x0B8 /**< Used to enable AXI/APB - write access to the DPCD - capability structure. */ -#define XDPRX_OVER_DOWNSPREAD_CTRL 0x0BC /**< Used to override downspread - control in the DPCD. */ -#define XDPRX_OVER_LINK_QUAL_LANE0_SET 0x0C0 /**< Used to override the - LINK_QUAL_LANE0_SET - register in the DPCD. */ -#define XDPRX_OVER_LINK_QUAL_LANE1_SET 0x0C4 /**< Used to override the - LINK_QUAL_LANE1_SET - register in the DPCD. */ -#define XDPRX_OVER_LINK_QUAL_LANE2_SET 0x0C8 /**< Used to override the - LINK_QUAL_LANE2_SET - register in the DPCD. */ -#define XDPRX_OVER_LINK_QUAL_LANE3_SET 0x0CC /**< Used to override the - LINK_QUAL_LANE3_SET - register in the DPCD. */ -#define XDPRX_MST_CAP 0x0D0 /**< Used to enable or disable - MST capability. */ -#define XDPRX_SINK_COUNT 0x0D4 /**< The sink device count. */ -#define XDPRX_GUID0 0x0E0 /**< Lower 4 bytes of the DPCD's - GUID field. */ -#define XDPRX_GUID1 0x0E4 /**< Bytes 4 to 7 of the DPCD's - GUID field. */ -#define XDPRX_GUID2 0x0E8 /**< Bytes 8 to 11 of the DPCD's - GUID field. */ -#define XDPRX_GUID3 0x0EC /**< Upper 4 bytes of the DPCD's - GUID field. */ -#define XDPRX_OVER_GUID 0x0F0 /**< Used to override the GUID - field in the DPCD with - what is stored in - XDPRX_GUID[0-3]. */ -/* @} */ - -/** @name DPRX core registers: Core ID. - * @{ - */ -#define XDPRX_VERSION 0x0F8 /**< Version and revision of the - DisplayPort core. */ -#define XDPRX_CORE_ID 0x0FC /**< DisplayPort protocol - version and revision. */ -/* @} */ - -/** @name DPRX core registers: User video status. - * @{ - */ -#define XDPRX_USER_FIFO_OVERFLOW 0x110 /**< Indicates an overflow in - user FIFO. */ -#define XDPRX_USER_VSYNC_STATE 0x114 /**< Provides a mechanism for - the host processor to - monitor the state of the - video data path. */ -/* @} */ - -/** @name DPRX core registers: PHY configuration and status. - * @{ - */ -#define XDPRX_PHY_CONFIG 0x200 /**< Transceiver PHY reset and - configuration. */ -#define XDPRX_PHY_STATUS 0x208 /**< Current PHY status. */ -#define XDPRX_PHY_POWER_DOWN 0x210 /**< Control PHY power down. */ -#define XDPRX_MIN_VOLTAGE_SWING 0x214 /**< Specifies the minimum - voltage swing required - during training before - a link can be reliably - established and advanced - configuration for link - training. */ -#define XDPRX_CDR_CONTROL_CONFIG 0x21C /**< Control the configuration - for clock and data - recovery. */ -#define XDPRX_GT_DRP_COMMAND 0x2A0 /**< Provides access to the GT - DRP ports. */ -#define XDPRX_GT_DRP_READ_DATA 0x2A4 /**< Provides access to GT DRP - read data. */ -#define XDPRX_GT_DRP_CH_STATUS 0x2A8 /**< Provides access to GT DRP - channel status. */ -/* @} */ - -/** @name DPRX core registers: Audio. - * @{ - */ -#define XDPRX_RX_AUDIO_CONTROL 0x300 /**< Enables audio stream - packets in main link. */ -#define XDPRX_RX_AUDIO_INFO_DATA(NUM) (0x304 + 4 * (NUM - 1)) /**< Word - formatted as per CEA - 861-C info frame. */ -#define XDPRX_RX_AUDIO_MAUD 0x324 /**< M value of audio stream - as decoded from audio - time stamp packet. */ -#define XDPRX_RX_AUDIO_NAUD 0x328 /**< N value of audio stream - as decoded from audio - time stamp packet. */ -#define XDPRX_RX_AUDIO_STATUS 0x32C /**< Status of audio stream. */ -#define XDPRX_RX_AUDIO_EXT_DATA(NUM) (0x330 + 4 * (NUM - 1)) /**< Word - formatted as per - extension packet. */ -/* @} */ - -/** @name DPRX core registers: DPCD configuration space. - * @{ - */ -#define XDPRX_DPCD_LINK_BW_SET 0x400 /**< Current link bandwidth - setting as exposed in - the RX DPCD. */ -#define XDPRX_DPCD_LANE_COUNT_SET 0x404 /**< Current lane count - setting as exposed in - the RX DPCD. */ -#define XDPRX_DPCD_ENHANCED_FRAME_EN 0x408 /**< Current setting for - enhanced framing symbol - mode as exposed in the - RX DPCD. */ -#define XDPRX_DPCD_TRAINING_PATTERN_SET 0x40C /**< Current training pattern - setting as exposed in - the RX DPCD. */ -#define XDPRX_DPCD_LINK_QUALITY_PATTERN_SET 0x410 /**< Current value of the link - quality pattern - field as exposed in the - RX DPCD. */ -#define XDPRX_DPCD_RECOVERED_CLOCK_OUT_EN 0x414 /**< Value of the output clock - enable field as exposed - in the RX DPCD. */ -#define XDPRX_DPCD_SCRAMBLING_DISABLE 0x418 /**< Value of the scrambling - disable field as exposed - in the RX DPCD. */ -#define XDPRX_DPCD_SYMBOL_ERROR_COUNT_SELECT 0x41C /**< Current value of the - symbol error count - select field as exposed - in the RX DPCD. */ -#define XDPRX_DPCD_TRAINING_LANE_0_SET 0x420 /**< The RX DPCD value used by - the TX during link - training to configure - the RX PHY lane 0. */ -#define XDPRX_DPCD_TRAINING_LANE_1_SET 0x424 /**< The RX DPCD value used by - the TX during link - training to configure - the RX PHY lane 1. */ -#define XDPRX_DPCD_TRAINING_LANE_2_SET 0x428 /**< The RX DPCD value used by - the TX during link - training to configure - the RX PHY lane 2. */ -#define XDPRX_DPCD_TRAINING_LANE_3_SET 0x42C /**< The RX DPCD value Used by - the TX during link - training to configure - the RX PHY lane 3. */ -#define XDPRX_DPCD_DOWNSPREAD_CONTROL 0x430 /**< The RX DPCD value that - is used by the TX to - inform the RX that - downspreading has been - enabled. */ -#define XDPRX_DPCD_MAIN_LINK_CHANNEL_CODING_SET 0x434 /**< 8B/10B encoding - setting as exposed in - the RX DPCD. */ -#define XDPRX_DPCD_SET_POWER_STATE 0x438 /**< Power state requested by - the TX as exposed in the - RX DPCD. */ -#define XDPRX_DPCD_LANE01_STATUS 0x43C /**< Link training status for - lanes 0 and 1 as exposed - in the RX DPCD. */ -#define XDPRX_DPCD_LANE23_STATUS 0x440 /**< Link training status for - lanes 2 and 3 as exposed - in the RX DPCD. */ -#define XDPRX_DPCD_SOURCE_OUI_VALUE 0x444 /** The RX DPCD value used by - the TX to set the - organizationally unique - identifier (OUI). */ -#define XDPRX_DPCD_SYM_ERR_CNT01 0x448 /** The symbol error counter - values for lanes 0 and 1 - as exposed in the RX - DPCD. */ -#define XDPRX_DPCD_SYM_ERR_CNT23 0x44C /** The symbol error counter - values for lanes 2 and 3 - as exposed in the RX - DPCD. */ -/* @} */ - -/** @name DPRX core registers: Main stream attributes for SST / MST STREAM1. - * @{ - */ -#define XDPRX_STREAM1_MSA_START 0x500 /**< Start of the MSA registers - for stream 1. */ -#define XDPRX_MSA_HRES 0x500 /**< Number of active pixels per - line (the horizontal - resolution). */ -#define XDPRX_MSA_HSPOL 0x504 /**< The horizontal sync - polarity. */ -#define XDPRX_MSA_HSWIDTH 0x508 /**< Width of the horizontal - sync pulse. */ -#define XDPRX_MSA_HSTART 0x50C /**< Number of clocks between - the leading edge of the - horizontal sync and the - start of active data. */ -#define XDPRX_MSA_HTOTAL 0x510 /**< Total number of clocks in - the horizontal framing - period. */ -#define XDPRX_MSA_VHEIGHT 0x514 /**< Number of active lines (the - vertical resolution). */ -#define XDPRX_MSA_VSPOL 0x518 /**< The vertical sync - polarity. */ -#define XDPRX_MSA_VSWIDTH 0x51C /**< Width of the vertical - sync pulse. */ -#define XDPRX_MSA_VSTART 0x520 /**< Number of lines between the - leading edge of the - vertical sync and the - first line of active - data. */ -#define XDPRX_MSA_VTOTAL 0x524 /**< Total number of lines in - the video frame. */ -#define XDPRX_MSA_MISC0 0x528 /**< Miscellaneous stream - attributes. */ -#define XDPRX_MSA_MISC1 0x52C /**< Miscellaneous stream - attributes. */ -#define XDPRX_MSA_MVID 0x530 /**< Used to recover the video - clock from the link - clock. */ -#define XDPRX_MSA_NVID 0x534 /**< Used to recover the video - clock from the link - clock. */ -#define XDPRX_MSA_VBID 0x538 /**< The most recently received - VB-ID value. */ -/* @} */ - -/** @name DPRX core registers: Main stream attributes for MST STREAM2, 3, and 4. - * @{ - */ -#define XDPRX_STREAM2_MSA_START 0x540 /**< Start of the MSA registers - for stream 2. */ -#define XDPRX_STREAM2_MSA_START_OFFSET (XDPRX_STREAM2_MSA_START - \ - XDPRX_STREAM1_MSA_START) /**< The MSA registers for - stream 2 are at an - offset from the - corresponding registers - of stream 1. */ -#define XDPRX_STREAM3_MSA_START 0x580 /**< Start of the MSA registers - for stream 3. */ -#define XDPRX_STREAM3_MSA_START_OFFSET (XDPRX_STREAM3_MSA_START - \ - XDPRX_STREAM1_MSA_START) /**< The MSA registers for - stream 3 are at an - offset from the - corresponding registers - of stream 1. */ -#define XDPRX_STREAM4_MSA_START 0x5C0 /**< Start of the MSA registers - for stream 4. */ -#define XDPRX_STREAM4_MSA_START_OFFSET (XDPRX_STREAM4_MSA_START - \ - XDPRX_STREAM1_MSA_START) /**< The MSA registers for - stream 4 are at an - offset from the - corresponding registers - of stream 1. */ -/* @} */ - -/** @name DPRX core registers: MST field for sideband message buffers and the - * virtual channel payload table. - * @{ - */ -#define XDPRX_DOWN_REQ 0xA00 /**< Down request buffer address - space. */ -#define XDPRX_DOWN_REP 0xB00 /**< Down reply buffer address - space. */ -#define XDPRX_VC_PAYLOAD_TABLE 0x800 /**< Virtual channel payload - table (0xFF bytes). */ -#define XDPRX_VC_PAYLOAD_TABLE_ID_SLOT(SlotNum) \ - (XDPRX_VC_PAYLOAD_TABLE + SlotNum) -/* @} */ - -/** @name DPRX core registers: Vendor specific DPCD. - * @{ - */ -#define XDPRX_SOURCE_DEVICE_SPECIFIC_FIELD 0xE00 /**< User access to the source - specific field as - exposed in the RX - DPCD (0xFF bytes). */ -#define XDPRX_SOURCE_DEVICE_SPECIFIC_FIELD_REG(RegNum) \ - (XDPRX_SOURCE_DEVICE_SPECIFIC_FIELD + (4 * RegNum)) -#define XDPRX_SINK_DEVICE_SPECIFIC_FIELD 0xF00 /**< User access to the sink - specific field as - exposed in the RX - DPCD (0xFF bytes). */ -#define XDPRX_SINK_DEVICE_SPECIFIC_FIELD_REG(RegNum) \ - (XDPRX_SINK_DEVICE_SPECIFIC_FIELD + (4 * RegNum)) -/* @} */ - -/******************************************************************************/ - -/** @name DPRX core masks, shifts, and register values. - * @{ - */ -/* 0x004: AUX_CLK_DIVIDER */ -#define XDPRX_AUX_CLK_DIVIDER_VAL_MASK 0x00FF /**< Clock divider value. */ -#define XDPRX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK \ - 0xFF00 /**< AUX (noise) signal width - filter. */ -#define XDPRX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT \ - 8 /**< Shift bits for AUX signal - width filter. */ -/* 0x010: USER_PIXEL_WIDTH */ -#define XDPRX_USER_PIXEL_WIDTH_1 0x1 /**< Single pixel wide - interface. */ -#define XDPRX_USER_PIXEL_WIDTH_2 0x2 /**< Dual pixel output mode. */ -#define XDPRX_USER_PIXEL_WIDTH_4 0x4 /**< Quad pixel output mode. */ -/* 0x014: INTERRUPT_MASK */ -#define XDPRX_INTERRUPT_MASK_VM_CHANGE_MASK \ - 0x00001 /**< Mask the interrupt - assertion for a - resolution change, as - detected from the MSA - fields. */ -#define XDPRX_INTERRUPT_MASK_POWER_STATE_MASK \ - 0x00002 /**< Mask the interrupt - assertion for a power - state change. */ -#define XDPRX_INTERRUPT_MASK_NO_VIDEO_MASK \ - 0x00004 /**< Mask the interrupt - assertion for the - no-video condition being - detected after active - video received. */ -#define XDPRX_INTERRUPT_MASK_VBLANK_MASK \ - 0x00008 /**< Mask the interrupt - assertion for the start - of the blanking - interval. */ -#define XDPRX_INTERRUPT_MASK_TRAINING_LOST_MASK \ - 0x00010 /**< Mask the interrupt - assertion for training - loss on active lanes. */ -#define XDPRX_INTERRUPT_MASK_VIDEO_MASK 0x00040 /**< Mask the interrupt - assertion for a valid - video frame being - detected on the main - link. Video interrupt is - set after a delay of 8 - video frames following a - valid scrambler reset - character. */ -#define XDPRX_INTERRUPT_MASK_INFO_PKT_MASK \ - 0x00100 /**< Mask the interrupt - assertion for an audio - info packet being - received. */ -#define XDPRX_INTERRUPT_MASK_EXT_PKT_MASK \ - 0x00200 /**< Mask the interrupt - assertion for an audio - extension packet being - received. */ -#define XDPRX_INTERRUPT_MASK_VCP_ALLOC_MASK \ - 0x00400 /**< Mask the interrupt - assertion for a virtual - channel payload being - allocated. */ -#define XDPRX_INTERRUPT_MASK_VCP_DEALLOC_MASK \ - 0x00800 /**< Mask the interrupt - assertion for a virtual - channel payload being - allocated. */ -#define XDPRX_INTERRUPT_MASK_DOWN_REPLY_MASK \ - 0x01000 /**< Mask the interrupt - assertion for a - downstream reply being - ready. */ -#define XDPRX_INTERRUPT_MASK_DOWN_REQUEST_MASK \ - 0x02000 /**< Mask the interrupt - assertion for a - downstream request being - ready. */ -#define XDPRX_INTERRUPT_MASK_TRAINING_DONE_MASK \ - 0x04000 /**< Mask the interrupt - assertion for link - training completion. */ -#define XDPRX_INTERRUPT_MASK_BW_CHANGE_MASK \ - 0x08000 /**< Mask the interrupt - assertion for a change - in bandwidth. */ -#define XDPRX_INTERRUPT_MASK_TP1_MASK 0x10000 /**< Mask the interrupt - assertion for start of - training pattern 1. */ -#define XDPRX_INTERRUPT_MASK_TP2_MASK 0x20000 /**< Mask the interrupt - assertion for start of - training pattern 2. */ -#define XDPRX_INTERRUPT_MASK_TP3_MASK 0x40000 /**< Mask the interrupt - assertion for start of - training pattern 3. */ -#define XDPRX_INTERRUPT_MASK_ALL_MASK 0x7FFFF /**< Mask all interrupts. */ -/* 0x018: MISC_CTRL */ -#define XDPRX_MISC_CTRL_USE_FILT_MSA_MASK \ - 0x1 /**< When set, two matching - values must be detected - for each field of the - MSA values before the - associated register is - updated internally. */ -#define XDPRX_MISC_CTRL_LONG_I2C_USE_DEFER_MASK \ - 0x2 /**< When set, the long I2C - write data transfwers - are responded to using - DEFER instead of partial - ACKs. */ -#define XDPRX_MISC_CTRL_I2C_USE_AUX_DEFER_MASK \ - 0x4 /**< When set, I2C DEFERs will - be sent as AUX DEFERs to - the source device. */ -/* 0x01C: SOFT_RESET */ -#define XDPRX_SOFT_RESET_VIDEO_MASK 0x01 /**< Reset the video logic. */ -#define XDPRX_SOFT_RESET_AUX_MASK 0x80 /**< Reset the AUX logic. */ -/* 0x02C: HPD_INTERRUPT */ -#define XDPRX_HPD_INTERRUPT_ASSERT_MASK \ - 0x00000001 /**< Instructs the RX core to - assert an interrupt to - the TX using the HPD - signal. */ -#define XDPRX_HPD_INTERRUPT_LENGTH_US_MASK \ - 0xFFFF0000 /**< The length of the HPD pulse - to generate (in - microseconds). */ -#define XDPRX_HPD_INTERRUPT_LENGTH_US_SHIFT 16 /**< Shift bits for the HPD - pulse length. */ -/* 0x040: INTERRUPT_CAUSE */ -#define XDPRX_INTERRUPT_CAUSE_VM_CHANGE_MASK \ - XDPRX_INTERRUPT_MASK_VM_CHANGE_MASK /**< Interrupt caused by a - resolution change, as - detected from the MSA - fields. */ -#define XDPRX_INTERRUPT_CAUSE_POWER_STATE_MASK \ - XDPRX_INTERRUPT_MASK_POWER_STATE_MASK /**< Interrupt caused by a - power state change. */ -#define XDPRX_INTERRUPT_CAUSE_NO_VIDEO_MASK \ - XDPRX_INTERRUPT_MASK_NO_VIDEO_MASK /**< Interrupt caused by the - no-video condition being - detected after active - video received. */ -#define XDPRX_INTERRUPT_CAUSE_VBLANK_MASK \ - XDPRX_INTERRUPT_MASK_VBLANK_MASK /**< Interrupt caused by the - start of the blanking - interval. */ -#define XDPRX_INTERRUPT_CAUSE_TRAINING_LOST_MASK \ - XDPRX_INTERRUPT_MASK_TRAINING_LOST_MASK /**< Interrupt caused by - training loss on active - lanes. */ -#define XDPRX_INTERRUPT_CAUSE_VIDEO_MASK \ - XDPRX_INTERRUPT_MASK_VIDEO_MASK /**< Interrupt caused by a valid - video frame being - detected on the main - link. Video interrupt is - set after a delay of 8 - video frames following a - valid scrambler reset - character. */ -#define XDPRX_INTERRUPT_CAUSE_INFO_PKT_MASK \ - XDPRX_INTERRUPT_MASK_INFO_PKT_MASK /**< Interrupt caused by an - audio info packet being - received. */ -#define XDPRX_INTERRUPT_CAUSE_EXT_PKT_MASK \ - XDPRX_INTERRUPT_MASK_EXT_PKT_MASK /**< Interrupt caused by an - audio extension packet - being received. */ -#define XDPRX_INTERRUPT_CAUSE_VCP_ALLOC_MASK \ - XDPRX_INTERRUPT_MASK_VCP_ALLOC_MASK /**< Interrupt caused by a - virtual channel payload - being allocated. */ -#define XDPRX_INTERRUPT_CAUSE_VCP_DEALLOC_MASK \ - XDPRX_INTERRUPT_MASK_VCP_DEALLOC_MASK /**< Interrupt caused by a - virtual channel payload - being allocated. */ -#define XDPRX_INTERRUPT_CAUSE_DOWN_REPLY_MASK \ - XDPRX_INTERRUPT_MASK_DOWN_REPLY_MASK /**< Interrupt caused by a - downstream reply being - ready. */ -#define XDPRX_INTERRUPT_CAUSE_DOWN_REQUEST_MASK \ - XDPRX_INTERRUPT_MASK_DOWN_REQUEST_MASK /**< Interrupt caused by a - downstream request being - ready. */ -#define XDPRX_INTERRUPT_CAUSE_TRAINING_DONE_MASK \ - XDPRX_INTERRUPT_MASK_TRAINING_DONE_MASK /**< Interrupt caused by link - training completion. */ -#define XDPRX_INTERRUPT_CAUSE_BW_CHANGE_MASK \ - XDPRX_INTERRUPT_MASK_BW_CHANGE_MASK /**< Interrupt caused by a - change in bandwidth. */ -#define XDPRX_INTERRUPT_CAUSE_TP1_MASK \ - XDPRX_INTERRUPT_MASK_TP1_MASK /**< Interrupt caused by the - start of training - pattern 1. */ -#define XDPRX_INTERRUPT_CAUSE_TP2_MASK \ - XDPRX_INTERRUPT_MASK_TP2_MASK /**< Interrupt caused by the - start of training - pattern 2. */ -#define XDPRX_INTERRUPT_CAUSE_TP3_MASK \ - XDPRX_INTERRUPT_MASK_TP3_MASK /**< Interrupt caused by the - start of training - pattern 3. */ -/* 0x044: INTERRUPT_MASK_1 */ -#define XDPRX_INTERRUPT_MASK_1_EXT_PKT_STREAM234_MASK(Stream) \ - (0x00001 << ((Stream - 2) * 6)) /**< Mask the interrupt - assertion for an audio - extension packet being - received for stream - 2, 3, or 4. */ -#define XDPRX_INTERRUPT_MASK_1_INFO_PKT_STREAM234_MASK(Stream) \ - (0x00002 << ((Stream - 2) * 6)) /**< Mask the interrupt - assertion for an audio - info packet being - received for stream - 2, 3, or 4. */ -#define XDPRX_INTERRUPT_MASK_1_VM_CHANGE_STREAM234_MASK(Stream) \ - (0x00004 << ((Stream - 2) * 6)) /**< Mask the interrupt - assertion for a - resolution change, as - detected from the MSA - fields for stream 2, 3, - or 4. */ -#define XDPRX_INTERRUPT_MASK_1_NO_VIDEO_STREAM234_MASK(Stream) \ - (0x00008 << ((Stream - 2) * 6)) /**< Mask the interrupt - assertion for the - no-video condition being - detected after active - video received for - stream 2, 3, or 4. */ -#define XDPRX_INTERRUPT_MASK_1_VBLANK_STREAM234_MASK(Stream) \ - (0x00010 << ((Stream - 2) * 6)) /**< Mask the interrupt - assertion for the start - of the blanking interval - for stream 2, 3, or - 4. */ -#define XDPRX_INTERRUPT_MASK_1_VIDEO_STREAM234_MASK(Stream) \ - (0x00020 << ((Stream - 2) * 6)) /**< Mask the interrupt - assertion for a valid - video frame being - detected on the main - link for stream 2, 3, - or 4. */ -/* 0x048: INTERRUPT_CAUSE_1 */ -#define XDPRX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK(Stream) \ - XDPRX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK(Stream) /**< Interrupt - caused by an audio - extension packet being - received for stream 2, - 3, or 4. */ -#define XDPRX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK(Stream) \ - XDPRX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK(Stream) /**< Interrupt - caused by an audio info - packet being received - for stream 2, 3, or - 4. */ -#define XDPRX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK(Stream) \ - XDPRX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK(Stream) /**< Interrupt - caused by a resolution - change, as detected from - the MSA fields for - stream 2, 3, or 4. */ -#define XDPRX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK(Stream) \ - XDPRX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK(Stream) /**< Interrupt - caused by the no-video - condition being detected - after active video - received for stream 2, - 3, or 4. */ -#define XDPRX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK(Stream) \ - XDPRX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK(Stream) /**< Interrupt - caused by the start of - the blanking interval - for stream 2, 3, or - 4. */ -#define XDPRX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK(Stream) \ - XDPRX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK(Stream) /**< Interrupt - caused by a valid video - frame being detected on - the main link for - stream 2, 3, or 4. */ -/* 0x050: HSYNC_WIDTH */ -#define XDPRX_HSYNC_WIDTH_PULSE_WIDTH_MASK \ - 0x00FF /**< Specifies the number of - clock cycles the - horizontal sync pulse is - asserted. */ -#define XDPRX_HSYNC_WIDTH_FRONT_PORCH_MASK \ - 0xFF00 /**< Defines the number of video - clock cycles to place - between the last pixel - of active data and the - start of the horizontal - sync pulse (the front - porch). */ -#define XDPRX_HSYNC_WIDTH_FRONT_PORCH_SHIFT 8 /**< Shift bits for the front - porch. */ -/* 0x090: DEVICE_SERVICE_IRQ */ -#define XDPRX_DEVICE_SERVICE_IRQ_NEW_REMOTE_CMD_MASK \ - 0x01 /**< Indicates that a new - command is present in - the REMOTE_CMD - register. */ -#define XDPRX_DEVICE_SERVICE_IRQ_SINK_SPECIFIC_IRQ_MASK \ - 0x02 /**< Reflects the - SINK_SPECIFIC_IRQ - state. */ -#define XDPRX_DEVICE_SERVICE_IRQ_NEW_DOWN_REPLY_MASK \ - 0x10 /**< Indicates a new DOWN_REPLY - buffer message is - ready. */ -/* 0x09C: OVER_LINK_BW_SET */ -#define XDPRX_OVER_LINK_BW_SET_162GBPS 0x06 /**< 1.62 Gbps link rate. */ -#define XDPRX_OVER_LINK_BW_SET_270GBPS 0x0A /**< 2.70 Gbps link rate. */ -#define XDPRX_OVER_LINK_BW_SET_540GBPS 0x14 /**< 5.40 Gbps link rate. */ - -/* 0x0A0: OVER_LANE_COUNT_SET */ -#define XDPRX_OVER_LANE_COUNT_SET_MASK 0x1F /**< The lane count override - value. */ -#define XDPRX_OVER_LANE_COUNT_SET_1 0x1 /**< Lane count of 1. */ -#define XDPRX_OVER_LANE_COUNT_SET_2 0x2 /**< Lane count of 2. */ -#define XDPRX_OVER_LANE_COUNT_SET_4 0x4 /**< Lane count of 4. */ -#define XDPRX_OVER_LANE_COUNT_SET_TPS3_SUPPORTED_MASK \ - 0x20 /**< Capability override for - training pattern 3. */ -#define XDPRX_OVER_LANE_COUNT_SET_ENHANCED_FRAME_CAP_MASK \ - 0x80 /**< Capability override for - enhanced framing. */ -/* 0x0A4: OVER_TP_SET */ -#define XDPRX_OVER_TP_SET_TP_SELECT_MASK \ - 0x0003 /**< Training pattern select - override. */ -#define XDPRX_OVER_TP_SET_LQP_SET_MASK \ - 0x000C /**< Link quality pattern set - override. */ -#define XDPRX_OVER_TP_SET_LQP_SET_SHIFT 2 /**< Shift bits for link quality - pattern set override. */ -#define XDPRX_OVER_TP_SET_REC_CLK_OUT_EN_MASK \ - 0x0010 /**< Recovered clock output - enable override. */ -#define XDPRX_OVER_TP_SET_SCRAMBLER_DISABLE_MASK \ - 0x0020 /**< Scrambling disable - override. */ -#define XDPRX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_MASK \ - 0x00C0 /**< Symbol error count - override. */ -#define XDPRX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_SHIFT \ - 6 /**< Shift bits for symbol error - count override. */ -#define XDPRX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_MASK \ - 0xFF00 /**< Training AUX read interval - override. */ -#define XDPRX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_SHIFT \ - 8 /**< Shift bits for training AUX - read interval - override. */ -/* 0x0A8, 0x0AC, 0x0B0, 0x0B4: OVER_TRAINING_LANEX_SET */ -#define XDPRX_OVER_TRAINING_LANEX_SET_VS_SET_MASK \ - 0x03 /**< Voltage swing set - override. */ -#define XDPRX_OVER_TRAINING_LANEX_SET_MAX_VS_MASK \ - 0x04 /**< Maximum voltage swing - override. */ -#define XDPRX_OVER_TRAINING_LANEX_SET_PE_SET_MASK \ - 0x18 /**< Pre-emphasis set - override. */ -#define XDPRX_OVER_TRAINING_LANEX_SET_PE_SET_SHIFT \ - 3 /**< Shift bits for pre-emphasis - set override. */ -#define XDPRX_OVER_TRAINING_LANEX_SET_MAX_PE_MASK \ - 0x20 /**< Maximum pre-emphasis - override. */ -/* 0x0F8 : VERSION_REGISTER */ -#define XDPRX_VERSION_INTER_REV_MASK \ - 0x0000000F /**< Internal revision. */ -#define XDPRX_VERSION_CORE_PATCH_MASK \ - 0x00000030 /**< Core patch details. */ -#define XDPRX_VERSION_CORE_PATCH_SHIFT \ - 8 /**< Shift bits for core patch - details. */ -#define XDPRX_VERSION_CORE_VER_REV_MASK \ - 0x000000C0 /**< Core version revision. */ -#define XDPRX_VERSION_CORE_VER_REV_SHIFT \ - 12 /**< Shift bits for core version - revision. */ -#define XDPRX_VERSION_CORE_VER_MNR_MASK \ - 0x00000F00 /**< Core minor version. */ -#define XDPRX_VERSION_CORE_VER_MNR_SHIFT \ - 16 /**< Shift bits for core minor - version. */ -#define XDPRX_VERSION_CORE_VER_MJR_MASK \ - 0x0000F000 /**< Core major version. */ -#define XDPRX_VERSION_CORE_VER_MJR_SHIFT \ - 24 /**< Shift bits for core major - version. */ -/* 0x0FC : CORE_ID */ -#define XDPRX_CORE_ID_TYPE_MASK 0x0000000F /**< Core type. */ -#define XDPRX_CORE_ID_TYPE_TX 0x0 /**< Core is a transmitter. */ -#define XDPRX_CORE_ID_TYPE_RX 0x1 /**< Core is a receiver. */ -#define XDPRX_CORE_ID_DP_REV_MASK \ - 0x000000F0 /**< DisplayPort protocol - revision. */ -#define XDPRX_CORE_ID_DP_REV_SHIFT \ - 8 /**< Shift bits for DisplayPort - protocol revision. */ -#define XDPRX_CORE_ID_DP_MNR_VER_MASK \ - 0x00000F00 /**< DisplayPort protocol minor - version. */ -#define XDPRX_CORE_ID_DP_MNR_VER_SHIFT \ - 16 /**< Shift bits for DisplayPort - protocol major - version. */ -#define XDPRX_CORE_ID_DP_MJR_VER_MASK \ - 0x0000F000 /**< DisplayPort protocol major - version. */ -#define XDPRX_CORE_ID_DP_MJR_VER_SHIFT \ - 24 /**< Shift bits for DisplayPort - protocol major - version. */ -/* 0x110: USER_FIFO_OVERFLOW */ -#define XDPRX_USER_FIFO_OVERFLOW_FLAG_STREAMX_MASK(Stream) \ - (Stream) /**< Indicates that the internal - FIFO has detected on - overflow condition for - the specified stream. */ -#define XDPRX_USER_FIFO_OVERFLOW_VID_UNPACK_STREAMX_MASK(Stream) \ - (Stream << 4) /**< Indicates that the video - unpack FIFO has - overflown for the - specified stream. */ -#define XDPRX_USER_FIFO_OVERFLOW_VID_TIMING_STREAMX_MASK(Stream) \ - (Stream << 8) /**< Indicates that the video - timing FIFO has - overflown for the - specified stream. */ -/* 0x114: USER_VSYNC_STATE */ -#define XDPRX_USER_VSYNC_STATE_STREAMX_MASK(Stream) \ - (Stream) /**< The state of the vertical - sync pulse for the - specified stream. */ -/* 0x200: PHY_CONFIG */ -#define XDPRX_PHY_CONFIG_PHY_RESET_ENABLE_MASK \ - 0x00000000 /**< Release reset. */ -#define XDPRX_PHY_CONFIG_GTPLL_RESET_MASK \ - 0x00000001 /**< Hold the GTPLL in reset. */ -#define XDPRX_PHY_CONFIG_GTRX_RESET_MASK \ - 0x00000002 /**< Hold GTRXRESET in reset. */ -#define XDPRX_PHY_CONFIG_RX_PHY_PMA_RESET_MASK \ - 0x00000100 /**< Hold RX_PHY_PMA reset. */ -#define XDPRX_PHY_CONFIG_RX_PHY_PCS_RESET_MASK \ - 0x00000200 /**< Hold RX_PHY_PCS reset. */ -#define XDPRX_PHY_CONFIG_RX_PHY_BUF_RESET_MASK \ - 0x00000400 /**< Hold RX_PHY_BUF reset. */ -#define XDPRX_PHY_CONFIG_RX_PHY_DFE_LPM_RESET_MASK \ - 0x00000800 /**< Hold RX_PHY_DFE_LPM - reset. */ -#define XDPRX_PHY_CONFIG_RX_PHY_POLARITY_MASK \ - 0x00001000 /**< Set RX_PHY_POLARITY. */ -#define XDPRX_PHY_CONFIG_RX_PHY_LOOPBACK_MASK \ - 0x0000E000 /**< Set RX_PHY_LOOPBACK. */ -#define XDPRX_PHY_CONFIG_RX_PHY_EYESCANRESET_MASK \ - 0x00010000 /**< Set RX_PHY_EYESCANRESET. */ -#define XDPRX_PHY_CONFIG_RX_PHY_EYESCANTRIGGER_MASK \ - 0x00020000 /**< Set RX_PHY_ - EYESCANTRIGGER. */ -#define XDPRX_PHY_CONFIG_RX_PHY_PRBSCNTRESET_MASK \ - 0x00040000 /**< Set RX_PHY_PRBSCNTRESET. */ -#define XDPRX_PHY_CONFIG_RX_PHY_RXLPMHFHOLD_MASK \ - 0x00080000 /**< Set RX_PHY_RXLPMHFHOLD. */ -#define XDPRX_PHY_CONFIG_RX_PHY_RXLPMLFHOLD_MASK \ - 0x00100000 /**< Set RX_PHY_RXLPMLFHOLD. */ -#define XDPRX_PHY_CONFIG_RX_PHY_RXLPMHFOVERDEN_MASK \ - 0x00200000 /**< Set RX_PHY_ - RXLPMHFOVERDEN. */ -#define XDPRX_PHY_CONFIG_RX_PHY_CDRHOLD_MASK \ - 0x00400000 /**< Set RX_PHY_CDRHOLD. */ -#define XDPRX_PHY_CONFIG_RESET_AT_TRAIN_ITER_MASK \ - 0x00800000 /**< Issue reset at every - training iteration. */ -#define XDPRX_PHY_CONFIG_RESET_AT_LINK_RATE_CHANGE_MASK \ - 0x01000000 /**< Issue reset at every link - rate change. */ -#define XDPRX_PHY_CONFIG_RESET_AT_TP1_START_MASK \ - 0x02000000 /**< Issue reset at start of - training pattern 1. */ -#define XDPRX_PHY_CONFIG_EN_CFG_RX_PHY_POLARITY_MASK \ - 0x04000000 /**< Enable the individual lane - polarity. */ -#define XDPRX_PHY_CONFIG_RX_PHY_POLARITY_LANE0_MASK \ - 0x08000000 /**< Configure RX_PHY_POLARITY - for lane 0. */ -#define XDPRX_PHY_CONFIG_RX_PHY_POLARITY_LANE1_MASK \ - 0x10000000 /**< Configure RX_PHY_POLARITY - for lane 1. */ -#define XDPRX_PHY_CONFIG_RX_PHY_POLARITY_LANE2_MASK \ - 0x20000000 /**< Configure RX_PHY_POLARITY - for lane 2. */ -#define XDPRX_PHY_CONFIG_RX_PHY_POLARITY_LANE3_MASK \ - 0x40000000 /**< Configure RX_PHY_POLARITY - for lane 3. */ -#define XDPRX_PHY_CONFIG_GT_ALL_RESET_MASK \ - 0x00000003 /**< Rest GT and PHY. */ - - - - - - - - - - - - - -/* 0x208: PHY_STATUS */ -#define XDPRX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK \ - 0x00000003 /**< Reset done for lanes - 0 and 1. */ -#define XDPRX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK \ - 0x0000000C /**< Reset done for lanes - 2 and 3. */ -#define XDPRX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT \ - 2 /**< Shift bits for reset done - for lanes 2 and 3. */ -#define XDPRX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK \ - 0x00000010 /**< PLL locked for lanes - 0 and 1. */ -#define XDPRX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK \ - 0x00000020 /**< PLL locked for lanes - 2 and 3. */ -#define XDPRX_PHY_STATUS_PLL_FABRIC_LOCK_MASK \ - 0x00000040 /**< FPGA fabric clock PLL - locked. */ -#define XDPRX_PHY_STATUS_RX_CLK_LOCK_MASK \ - 0x00000080 /**< Receiver clock locked. */ -#define XDPRX_PHY_STATUS_PRBSERR_LANE_0_MASK \ - 0x00000100 /**< PRBS error on lane 0. */ -#define XDPRX_PHY_STATUS_PRBSERR_LANE_1_MASK \ - 0x00000200 /**< PRBS error on lane 1. */ -#define XDPRX_PHY_STATUS_PRBSERR_LANE_2_MASK \ - 0x00000400 /**< PRBS error on lane 2. */ -#define XDPRX_PHY_STATUS_PRBSERR_LANE_3_MASK \ - 0x00000800 /**< PRBS error on lane 3. */ -#define XDPRX_PHY_STATUS_RX_VLOW_LANE_0_MASK \ - 0x00001000 /**< RX voltage low on lane - 0. */ -#define XDPRX_PHY_STATUS_RX_VLOW_LANE_1_MASK \ - 0x00002000 /**< RX voltage low on lane - 1. */ -#define XDPRX_PHY_STATUS_RX_VLOW_LANE_2_MASK \ - 0x00004000 /**< RX voltage low on lane - 2. */ -#define XDPRX_PHY_STATUS_RX_VLOW_LANE_3_MASK \ - 0x00008000 /**< RX voltage low on lane - 3. */ -#define XDPRX_PHY_STATUS_LANE_ALIGN_LANE_0_MASK \ - 0x00010000 /**< Lane aligment status for - lane 0. */ -#define XDPRX_PHY_STATUS_LANE_ALIGN_LANE_1_MASK \ - 0x00020000 /**< Lane aligment status for - lane 1. */ -#define XDPRX_PHY_STATUS_LANE_ALIGN_LANE_2_MASK \ - 0x00040000 /**< Lane aligment status for - lane 2. */ -#define XDPRX_PHY_STATUS_LANE_ALIGN_LANE_3_MASK \ - 0x00080000 /**< Lane aligment status for - lane 3. */ -#define XDPRX_PHY_STATUS_SYM_LOCK_LANE_0_MASK \ - 0x00100000 /**< Symbol lock status for - lane 0. */ -#define XDPRX_PHY_STATUS_SYM_LOCK_LANE_1_MASK \ - 0x00200000 /**< Symbol lock status for - lane 1. */ -#define XDPRX_PHY_STATUS_SYM_LOCK_LANE_2_MASK \ - 0x00400000 /**< Symbol lock status for - lane 2. */ -#define XDPRX_PHY_STATUS_SYM_LOCK_LANE_3_MASK \ - 0x00800000 /**< Symbol lock status for - lane 3. */ -#define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_MASK \ - 0x03000000 /**< RX buffer status lane 0. */ -#define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_SHIFT \ - 24 /**< Shift bits for RX buffer - status lane 0. */ -#define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_1_MASK \ - 0x0C000000 /**< RX buffer status lane 1. */ -#define XDPRX_PHY_STATUS_RX_BUFFER_STATUE_LANE_1_SHIFT \ - 26 /**< Shift bits for RX buffer - status lane 1. */ -#define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_MASK \ - 0x30000000 /**< RX buffer status lane 2. */ -#define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_SHIFT \ - 28 /**< Shift bits for RX buffer - status lane 2. */ -#define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_MASK \ - 0xC0000000 /**< RX buffer status lane 3. */ -#define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_SHIFT \ - 30 /**< Shift bits for RX buffer - status lane 3. */ -#define XDPRX_PHY_STATUS_LANES_0_1_READY_MASK \ - 0x00000013 /**< Lanes 0 and 1 are ready. */ -#define XDPRX_PHY_STATUS_ALL_LANES_READY_MASK \ - 0x0000003F /**< All lanes are ready. */ -/* 0x210: PHY_POWER_DOWN */ -#define XDPRX_PHY_POWER_DOWN_LANE_0_MASK 0x1 /**< Power down the PHY for lane - 0. */ -#define XDPRX_PHY_POWER_DOWN_LANE_1_MASK 0x2 /**< Power down the PHY for lane - 1. */ -#define XDPRX_PHY_POWER_DOWN_LANE_2_MASK 0x4 /**< Power down the PHY for lane - 2. */ -#define XDPRX_PHY_POWER_DOWN_LANE_3_MASK 0x8 /**< Power down the PHY for lane - 3. */ -/* @} */ - -/******************* Macros (Inline Functions) Definitions ********************/ - -/** @name Register access macro definitions. - * @{ - */ -#define XDprx_In32 Xil_In32 -#define XDprx_Out32 Xil_Out32 -/* @} */ - -/******************************************************************************/ -/** - * This is a low-level function that reads from the specified register. - * - * @param BaseAddress is the base address of the device. - * @param RegOffset is the register offset to be read from. - * - * @return The 32-bit value of the specified register. - * - * @note C-style signature: - * u32 XDprx_ReadReg(u32 BaseAddress, u32 RegOffset) - * -*******************************************************************************/ -#define XDprx_ReadReg(BaseAddress, RegOffset) \ - XDprx_In32((BaseAddress) + (RegOffset)) - -/******************************************************************************/ -/** - * This is a low-level function that writes to the specified register. - * - * @param BaseAddress is the base address of the device. - * @param RegOffset is the register offset to write to. - * @param Data is the 32-bit data to write to the specified register. - * - * @return None. - * - * @note C-style signature: - * void XDprx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) - * -*******************************************************************************/ -#define XDprx_WriteReg(BaseAddress, RegOffset, Data) \ - XDprx_Out32((BaseAddress) + (RegOffset), (Data)) - -#endif /* XDPRX_HW_H_ */ diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdprx_selftest.c b/XilinxProcessorIPLib/drivers/dp/src/xdprx_selftest.c deleted file mode 100644 index daa3c7f6..00000000 --- a/XilinxProcessorIPLib/drivers/dp/src/xdprx_selftest.c +++ /dev/null @@ -1,148 +0,0 @@ -/******************************************************************************* - * - * Copyright (C) 2015 Xilinx, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * Use of the Software is limited solely to applications: - * (a) running on a Xilinx device, or - * (b) that interact with a Xilinx device through a bus or interconnect. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Except as contained in this notice, the name of the Xilinx shall not be used - * in advertising or otherwise to promote the sale, use or other dealings in - * this Software without prior written authorization from Xilinx. - * -*******************************************************************************/ -/******************************************************************************/ -/** - * - * @file xdprx_selftest.c - * - * This file contains a diagnostic self-test function for the XDprx driver. It - * will check many of the DisplayPort RX's register values against the default - * reset values as a sanity-check that the core is ready to be used. - * - * @note None. - * - *
- * MODIFICATION HISTORY:
- *
- * Ver   Who  Date     Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0   als  01/20/15 Initial release.
- * 
- * -*******************************************************************************/ - -/******************************* Include Files ********************************/ - -#include "xdprx.h" -#include "xstatus.h" - -/**************************** Variable Definitions ****************************/ - -/** - * This table contains the default values for the DisplayPort TX core's general - * usage registers. - */ -u32 ResetValues[46][2] = -{ - {XDPRX_LINK_ENABLE, 0}, - {XDPRX_AUX_CLK_DIVIDER, 0}, - {XDPRX_DTG_ENABLE, 0}, - {XDPRX_USER_PIXEL_WIDTH, 0}, - {XDPRX_INTERRUPT_MASK, 0x7FFF}, - {XDPRX_MISC_CTRL, 0}, - {XDPRX_SOFT_RESET, 0}, - {XDPRX_AUX_REQ_IN_PROGRESS, 0}, - {XDPRX_REQ_ERROR_COUNT, 0}, - {XDPRX_REQ_COUNT, 0}, - {XDPRX_HPD_INTERRUPT, 0}, - {XDPRX_REQ_CLK_WIDTH, 0}, - {XDPRX_REQ_CMD, 0}, - {XDPRX_REQ_ADDRESS, 0}, - {XDPRX_REQ_LENGTH, 0}, - {XDPRX_INTERRUPT_CAUSE, 0}, - {XDPRX_INTERRUPT_MASK_1, 0}, - {XDPRX_INTERRUPT_CAUSE_1, 0}, - {XDPRX_HSYNC_WIDTH, 0xF0F}, - {XDPRX_FAST_I2C_DIVIDER, 0}, - {XDPRX_LOCAL_EDID_VIDEO, 0}, - {XDPRX_LOCAL_EDID_AUDIO, 0}, - {XDPRX_REMOTE_CMD, 0}, - {XDPRX_DEVICE_SERVICE_IRQ, 0}, - {XDPRX_VIDEO_UNSUPPORTED, 0}, - {XDPRX_AUDIO_UNSUPPORTED, 0}, - {XDPRX_OVER_LINK_BW_SET, 0}, - {XDPRX_OVER_LANE_COUNT_SET, 0}, - {XDPRX_OVER_TP_SET, 0}, - {XDPRX_OVER_TRAINING_LANE0_SET, 0}, - {XDPRX_OVER_TRAINING_LANE1_SET, 0}, - {XDPRX_OVER_TRAINING_LANE2_SET, 0}, - {XDPRX_OVER_TRAINING_LANE3_SET, 0}, - {XDPRX_OVER_CTRL_DPCD, 0}, - {XDPRX_OVER_DOWNSPREAD_CTRL, 0}, - {XDPRX_OVER_LINK_QUAL_LANE0_SET, 0}, - {XDPRX_OVER_LINK_QUAL_LANE1_SET, 0}, - {XDPRX_OVER_LINK_QUAL_LANE2_SET, 0}, - {XDPRX_OVER_LINK_QUAL_LANE3_SET, 0}, - {XDPRX_MST_CAP, 0}, - {XDPRX_SINK_COUNT, 0}, - {XDPRX_GUID0, 0}, - {XDPRX_GUID1, 0}, - {XDPRX_GUID2, 0}, - {XDPRX_GUID3, 0}, - {XDPRX_OVER_GUID, 0} -}; - -/**************************** Function Definitions ****************************/ - -/******************************************************************************/ -/** - * This function runs a self-test on the XDprx driver/device. The sanity test - * checks whether or not all tested registers hold their default reset values. - * - * @param InstancePtr is a pointer to the XDprx instance. - * - * @return - * - XST_SUCCESS if the self-test passed - all tested registers - * hold their default reset values. - * - XST_FAILURE otherwise. - * - * @note None. - * -*******************************************************************************/ -u32 XDprx_SelfTest(XDprx *InstancePtr) -{ - u8 Index; - u32 Val; - - /* Compare general usage registers with their default values. */ - for (Index = 0; Index < 46; Index++) { - Val = XDprx_ReadReg(InstancePtr->Config.BaseAddr, - ResetValues[Index][0]); - /* Fail if register does not hold default value. */ - if (Val != ResetValues[Index][1]) { - return XST_FAILURE; - } - } - - /* All tested registers hold their default reset values. */ - return XST_SUCCESS; -} diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdptx.h b/XilinxProcessorIPLib/drivers/dp/src/xdptx.h deleted file mode 100644 index 65eea3fd..00000000 --- a/XilinxProcessorIPLib/drivers/dp/src/xdptx.h +++ /dev/null @@ -1,660 +0,0 @@ -/******************************************************************************* - * - * Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * Use of the Software is limited solely to applications: - * (a) running on a Xilinx device, or - * (b) that interact with a Xilinx device through a bus or interconnect. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Except as contained in this notice, the name of the Xilinx shall not be used - * in advertising or otherwise to promote the sale, use or other dealings in - * this Software without prior written authorization from Xilinx. - * -*******************************************************************************/ -/******************************************************************************/ -/** - * - * @file xdptx.h - * - * The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the - * Xilinx DisplayPort soft IP core in source (TX) mode. This driver follows the - * DisplayPort 1.2a specification. - * - * Driver description - * - * The device driver enables higher-level software (e.g., an application) to - * configure and control a DisplayPort TX soft IP, communicate and control an - * RX device/sink monitor over the AUX channel, and to initialize and transmit - * data streams over the main link. - * - * This driver implements link layer functionality: a Link Policy Maker (LPM) - * and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification. - * - The LPM manages the main link and is responsible for keeping the link - * synchronized. It will establish a link with a downstream RX device by - * undergoing a link training sequence which consists of: - * - Clock recovery: The clock needs to be recovered and PLLs need to be - * locked for all lanes. - * - Channel equalization: All lanes need to achieve channel equalization - * and and symbol lock, as well as for interlane alignment to take place. - * - The SPM manages transportation of an isochronous stream. That is, it will - * initialize and maintain a video stream, establish a virtual channel to a - * sink monitor, and transmit the stream. - * - * Using AUX transactions to read/write from/to the sink's DisplayPort - * Configuration Data (DPCD) address space, the LPM obtains the link - * capabilities, obtains link configuration and link and sink status, and - * configures and controls the link and sink. The main link is trained this way. - * - * I2C-over-AUX transactions are used to obtain the sink's Extended Display - * Identification Data (EDID) which give information on the display capabilities - * of the monitor. The SPM may use this information to determine what available - * screen resolutions and video timing are possible. - * - * Interrupt processing - * - * DisplayPort interrupts occur on the HPD signal line when the DisplayPort - * cable is connected/disconnected or when the RX device sends a pulse. The user - * hardware design must contain an interrupt controller which the DisplayPort - * TX instance's interrupt signal is connected to. The user application must - * enable interrupts in the system and set up the interrupt controller such that - * the XDptx_HpdInterruptHandler handler will service DisplayPort interrupts. - * When the XDptx_HpdInterruptHandler function is invoked, the handler will - * identify what type of DisplayPort interrupt has occurred, and will call - * either the HPD event handler function or the HPD pulse handler function, - * depending on whether a an HPD event on an HPD pulse event occurred. - * - * The DisplayPort TX's XDPTX_INTERRUPT_STATUS register indicates the type of - * interrupt that has occured, and the XDptx_HpdInterruptHandler will use this - * information to decide which handler to call. An HPD event is identified if - * bit XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is - * identified from the XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit. - * - * The HPD event handler may be set up by using the XDptx_SetHpdEventHandler - * function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler - * function. - * - * Multi-stream transport (MST) mode - * - * The driver handles MST mode functionality, including sideband messaging, - * topology discovery, virtual channel payload ID table management, and - * directing streams to different sinks. - * - * MST testing has been done at all possible link rate/lane count/topology/ - * resolution/color depth combinations with each setting using following values: - * - Link rate: 1.62, 2.70, and 5.40Gbps per lane. - * - Lane count: 1, 2, and 4 lanes. - * - Number of sink displays: 1, 2, 3, and 4 sink displays in both a daisy-chain - * configuration and in a configuration using a combination of a 1-to-3 hub - * and daisy-chain. Each stream was using the same resolution. - * - Resolutions (60Hz): 640x480, 800x600, 1024x768, 1280x800, 1280x1024, - * 1360x768, 1400x1050, 1680x1050, 1920x1080, 1920x2160, and 3840x2160. - * - Color depths: 18, 24, 30, 36, and 48 bits per pixel. - * - * Audio - * - * The driver does not handle audio. For an example as to how to configure and - * transmit audio, examples/xdptx_audio_example.c illustrates the required - * sequence. The user will need to configure the audio source connected to the - * Displayport TX instance and set up the audio info frame as per user - * requirements. - * - * Limitations - * - * - For MST mode to correctly display, the current version of the driver - * requires that each of the DisplayPort TX streams be allocated without - * skipping streams (i.e. assign stream 1, stream 2, and stream 3 - problems - * were experienced if skipping stream 2 and assigning stream 4 instead). - * skipping monitors in a daisy chain is OK as long as they are assigned to - * streams in order. - * - In MST mode, the current version of the driver does not support removal of - * an allocated stream from the virtual channel payload ID table without - * clearing the entire table. - * - Some sideband messages have not been implemented in the current version of - * the driver for MST mode. Notably, reception of a CONNECTION_STATUS_NOTIFY - * sideband message. - * - The driver does not handle audio. See the audio example in the driver - * examples directory for the required sequence for enabling audio. - * - * @note None. - * - *
- * MODIFICATION HISTORY:
- *
- * Ver   Who  Date     Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0   als  05/17/14 Initial release.
- *       als  08/03/14 Initial MST addition.
- * 2.0   als  09/21/14 Added XDptx_DiscoverTopology function and changed
- *                     XDptx_IsConnected from macro to function.
- * 3.0   als  12/16/14 Updated to use common video library.
- *                     Added topology reordering functions:
- *                         XDptx_TopologySwapSinks,
- *                         XDptx_TopologySortSinksByTiling
- *                     Added wrapper functions for remote DPCD/I2C read/writes:
- *                         XDptx_RemoteDpcdRead, XDptx_RemoteDpcdWrite,
- *                         XDptx_RemoteIicRead, XDptx_RemoteIicWrite
- *                     Added EDID utility functions:
- *                         XDptx_GetRemoteEdid, XDptx_GetEdidBlock,
- *                         XDptx_GetRemoteEdidBlock,
- *                         XDptx_GetRemoteEdidDispIdExt,
- *                         XDptx_GetDispIdDataBlock,
- *                         XDptx_GetRemoteTiledDisplayDb
- *                     Remove unused arguments from functions:
- *                         LinkCountTotal, RelativeAddress from
- *                             XDptx_AllocatePayloadVcIdTable
- *                         RegStartAddress from XDptx_IicWrite
- * 
- * -*******************************************************************************/ - -#ifndef XDPTX_H_ -/* Prevent circular inclusions by using protection macros. */ -#define XDPTX_H_ - -/******************************* Include Files ********************************/ - -#include "xdp.h" -#include "xdptx_hw.h" - -/****************************** Type Definitions ******************************/ - -/** - * This typedef contains configuration information about the RX device. - */ -typedef struct { - u8 DpcdRxCapsField[16]; /**< The first 16 bytes of the raw capabilities - field of the RX device's DisplayPort - Configuration Data (DPCD). */ - u8 LaneStatusAdjReqs[6];/**< This is a raw read of the RX device's - status registers. The first 4 bytes - correspond to the lane status associated - with clock recovery, channel - equalization, symbol lock, and interlane - alignment. The remaining 2 bytes - represent the pre-emphasis and voltage - swing level adjustments requested by the - RX device. */ -} XDptx_SinkConfig; - -/** - * This typedef contains configuration information about the main link settings. - */ -typedef struct { - u8 LaneCount; /**< The current lane count of the main - link. */ - u8 LinkRate; /**< The current link rate of the main - link. */ - u8 ScramblerEn; /**< Symbol scrambling is currently in - use over the main link. */ - u8 EnhancedFramingMode; /**< Enhanced frame mode is currently in - use over the main link. */ - u8 DownspreadControl; /**< Downspread control is currently in - use over the main link. */ - u8 MaxLaneCount; /**< The maximum lane count of the main - link. */ - u8 MaxLinkRate; /**< The maximum link rate of the main - link. */ - u8 SupportEnhancedFramingMode; /**< Enhanced frame mode is supported by - the RX device. */ - u8 SupportDownspreadControl; /**< Downspread control is supported by - the RX device. */ - u8 VsLevel; /**< The current voltage swing level for - each lane. */ - u8 PeLevel; /**< The current pre-emphasis/cursor - level for each lane. */ - u8 Pattern; /**< The current pattern currently in - use over the main link. */ -} XDptx_LinkConfig; - -/** - * This typedef contains the main stream attributes which determine how the - * video will be displayed. - */ -typedef struct { - XVidC_VideoTimingMode Vtm; /**< The video timing. */ - u32 PixelClockHz; /**< The pixel clock of the stream (in - Hz). */ - u32 HStart; /**< Horizontal blank start (in - pixels). */ - u32 VStart; /**< Vertical blank start (in lines). */ - u32 Misc0; /**< Miscellaneous stream attributes 0 - as specified by the DisplayPort - 1.2 specification. */ - u32 Misc1; /**< Miscellaneous stream attributes 1 - as specified by the DisplayPort - 1.2 specification. */ - u32 NVid; /**< N value for the video stream. */ - u32 UserPixelWidth; /**< The width of the user data input - port. */ - u32 DataPerLane; /**< Used to translate the number of - pixels per line to the native - internal 16-bit datapath. */ - u32 AvgBytesPerTU; /**< Average number of bytes per - transfer unit, scaled up by a - factor of 1000. */ - u32 TransferUnitSize; /**< Size of the transfer unit in the - framing logic. In MST mode, this - is also the number of time slots - that are alloted in the payload - ID table. */ - u32 InitWait; /**< Number of initial wait cycles at - the start of a new line by - the framing logic. */ - u32 BitsPerColor; /**< Number of bits per color - component. */ - u8 ComponentFormat; /**< The component format currently in - use by the video stream. */ - u8 DynamicRange; /**< The dynamic range currently in use - by the video stream. */ - u8 YCbCrColorimetry; /**< The YCbCr colorimetry currently in - use by the video stream. */ - u8 SynchronousClockMode; /**< Synchronous clock mode is currently - in use by the video stream. */ - u8 OverrideUserPixelWidth; /**< If set to 1, the value stored for - UserPixelWidth will be used as - the pixel width. */ -} XDptx_MainStreamAttributes; - -/** - * This typedef describes a stream when the driver is running in multi-stream - * transport (MST) mode. - */ -typedef struct { - u8 LinkCountTotal; /** The total number of DisplayPort - links from the DisplayPort TX to - the sink device that this MST - stream is targeting.*/ - u8 RelativeAddress[15]; /** The relative address from the - DisplayPort TX to the sink - device that this MST stream is - targeting.*/ - u16 MstPbn; /**< Payload bandwidth number used to - allocate bandwidth for the MST - stream. */ - u8 MstStreamEnable; /**< In MST mode, enables the - corresponding stream for this - MSA configuration. */ -} XDptx_MstStream; - -/** - * This typedef describes some board characteristics information that affects - * link training. - */ -typedef struct { - u8 HasRedriverInPath; /**< Redriver in path requires different voltage - swing and pre-emphasis. */ - u8 TxVsLevels[4]; /**< The voltage swing levels to be used by the - DisplayPort TX. */ - u8 TxPeLevels[4]; /**< The pre-emphasis/cursor level to be used by - the DisplayPort TX. */ - u8 TxVsOffset; /**< Voltage swing compensation offset used when - pre-emphasis is used. */ -} XDptx_BoardChar; - -/** - * This typedef describes a downstream DisplayPort device when the driver is - * running in multi-stream transport (MST) mode. - */ -typedef struct { - u32 Guid[4]; /**< The global unique identifier (GUID) - of the device. */ - u8 RelativeAddress[15]; /**< The relative address from the - DisplayPort TX to this - device. */ - u8 DeviceType; /**< The type of DisplayPort device. - Either a branch or sink. */ - u8 LinkCountTotal; /**< The total number of DisplayPort - links connecting this device to - the DisplayPort TX. */ - u8 DpcdRev; /**< The revision of the device's - DisplayPort Configuration Data - (DPCD). For this device to - support MST features, this value - must represent a protocl version - greater or equal to 1.2. */ - u8 MsgCapStatus; /**< This device is capable of sending - and receiving sideband - messages. */ -} XDptx_TopologyNode; - -/** - * This typedef describes a the entire topology of connected downstream - * DisplayPort devices (from the DisplayPort TX) when the driver is operating - * in multi-stream transport (MST) mode. - */ -typedef struct { - u8 NodeTotal; /**< The total number of nodes that were - found in the MST topology. */ - XDptx_TopologyNode NodeTable[63]; /**< A table listing all the nodes in - the MST topology. */ - u8 SinkTotal; /**< The total number of sinks in the - MST topology. */ - XDptx_TopologyNode *SinkList[63]; /**< A pointer list of sinks in the - MST topology. The entries will - point to the sinks in the - NodeTable. */ -} XDptx_Topology; - -/** - * This typedef describes a port that is connected to a DisplayPort branch - * device. This structure is used when the driver is operating in multi-stream - * transport (MST) mode. - */ -typedef struct { - u8 InputPort; /**< Specifies that this port is an - input port. */ - u8 PeerDeviceType; /**< Specifies the device type connected - to this port. */ - u8 PortNum; /**< The port number of this port. */ - u8 MsgCapStatus; /**< This port or the device at this - port can send and receive MST - messages. */ - u8 DpDevPlugStatus; /**< There is a device connected to this - port. */ - - u8 LegacyDevPlugStatus; /**< This port is connected to a legacy - device. */ - u8 DpcdRev; /**< The DisplayPort Configuration Data - (DPCD) revision of the device - connected to this port. */ - u32 Guid[4]; /**< The global unique identifier (GUID) - of the device connected to this - port. */ - u8 NumSdpStreams; /**< The total number of Secondary-Data - Packet (SDP) streams that this - port can handle. */ - u8 NumSdpStreamSinks; /**< The number of SDP streams - associated with this port. */ -} XDptx_SbMsgLinkAddressReplyPortDetail; - -/** - * This typedef describes a DisplayPort branch device. This structure is used - * when the driver is operating in multi-stream transport (MST) mode. - */ -typedef struct { - u8 ReplyType; /**< The reply type of the sideband - message. A value of 1 indicates - that the request wasn't - successful and the return data - will give the reason for a - negative-acknowledge (NACK). */ - u8 RequestId; /**< The request identifier of the - reply. This should correspond to - the request identifier for the - LINK_ADDRESS sideband message - request. */ - u32 Guid[4]; /**< The global unique identifier (GUID) - of the branch device. */ - u8 NumPorts; /**< The number of ports associated with - this branch device. */ - XDptx_SbMsgLinkAddressReplyPortDetail PortDetails[16]; /**< An array - describing all ports attached to - this branch device. */ -} XDptx_SbMsgLinkAddressReplyDeviceInfo; - -/******************************************************************************/ -/** - * Callback type which represents the handler for a Hot-Plug-Detect (HPD) event - * interrupt. - * - * @param InstancePtr is a pointer to the XDptx instance. - * - * @note None. - * -*******************************************************************************/ -typedef void (*XDptx_HpdEventHandler)(void *InstancePtr); - -/******************************************************************************/ -/** - * Callback type which represents the handler for a Hot-Plug-Detect (HPD) pulse - * interrupt. - * - * @param InstancePtr is a pointer to the XDptx instance. - * - * @note None. - * -*******************************************************************************/ -typedef void (*XDptx_HpdPulseHandler)(void *InstancePtr); - -/** - * The XDptx driver instance data. The user is required to allocate a variable - * of this type for every XDptx device in the system. A pointer to a variable of - * this type is then passed to the driver API functions. - */ -typedef struct { - XDp_Config Config; /**< Configuration structure for - the DisplayPort TX - core. It is important to - keep this member first - in the XDptx order. */ - u32 MstEnable; /**< Multi-stream transport - (MST) mode. Enables - functionality, allowing - multiple streams to be - sent over the main - link. */ - u32 IsReady; /**< Device is initialized and - ready. */ - u8 TrainAdaptive; /**< Downshift lane count and - link rate if necessary - during training. */ - XDptx_SinkConfig RxConfig; /**< Configuration structure for - the RX device. */ - XDptx_LinkConfig LinkConfig; /**< Configuration structure for - the main link. */ - XDptx_BoardChar BoardChar; /**< Some board characteristics - information that affects - link training. */ - XDptx_MainStreamAttributes MsaConfig[4]; /**< Configuration structure - for the main stream - attributes (MSA). Each - stream has its own set - of attributes. When MST - mode is disabled, only - MsaConfig[0] is used. */ - XDptx_MstStream MstStreamConfig[4]; /**< Configuration structure - for a multi-stream - transport (MST) - stream. */ - XDptx_Topology Topology; /**< The topology of connected - downstream DisplayPort - devices when the driver - is running in MST - mode. */ - u32 AuxDelayUs; /**< Amount of latency in micro- - seconds to use between - AUX transactions. */ - u32 SbMsgDelayUs; /**< Amount of latency in micro- - seconds to use between - sideband messages for - multi-stream transport - (MST) mode. */ - XDp_TimerHandler UserTimerWaitUs; /**< Custom user function for - delay/sleep. */ - void *UserTimerPtr; /**< Pointer to a timer instance - used by the custom user - delay/sleep function. */ - XDptx_HpdEventHandler HpdEventHandler; /**< Callback function for Hot- - Plug-Detect (HPD) event - interrupts. */ - void *HpdEventCallbackRef; /**< A pointer to the user data - passed to the HPD event - callback function. */ - XDptx_HpdPulseHandler HpdPulseHandler; /**< Callback function for Hot- - Plug-Detect (HPD) pulse - interrupts. */ - void *HpdPulseCallbackRef; /**< A pointer to the user data - passed to the HPD pulse - callback function. */ -} XDptx; - -/**************************** Function Prototypes *****************************/ - -/* xdptx.c: Setup and initialization functions. */ -void XDptx_CfgInitialize(XDptx *InstancePtr, XDp_Config *ConfigPtr, - u32 EffectiveAddr); -u32 XDptx_InitializeTx(XDptx *InstancePtr); -u32 XDptx_GetRxCapabilities(XDptx *InstancePtr); - -/* xdptx.c: Link policy maker functions. */ -u32 XDptx_CfgMainLinkMax(XDptx *InstancePtr); -u32 XDptx_EstablishLink(XDptx *InstancePtr); -u32 XDptx_CheckLinkStatus(XDptx *InstancePtr, u8 LaneCount); -void XDptx_EnableTrainAdaptive(XDptx *InstancePtr, u8 Enable); -void XDptx_SetHasRedriverInPath(XDptx *InstancePtr, u8 Set); -void XDptx_CfgTxVsOffset(XDptx *InstancePtr, u8 Offset); -void XDptx_CfgTxVsLevel(XDptx *InstancePtr, u8 Level, u8 TxLevel); -void XDptx_CfgTxPeLevel(XDptx *InstancePtr, u8 Level, u8 TxLevel); - -/* xdptx.c: AUX transaction functions. */ -u32 XDptx_AuxRead(XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToRead, - void *ReadData); -u32 XDptx_AuxWrite(XDptx *InstancePtr, u32 DpcdAddress, u32 BytesToWrite, - void *WriteData); -u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u16 Offset, - u16 BytesToRead, void *ReadData); -u32 XDptx_IicWrite(XDptx *InstancePtr, u8 IicAddress, u8 BytesToWrite, - void *WriteData); - -/* xdptx.c: Functions for controlling the link configuration. */ -u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable); -u32 XDptx_SetEnhancedFrameMode(XDptx *InstancePtr, u8 Enable); -u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount); -u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate); -u32 XDptx_SetScrambler(XDptx *InstancePtr, u8 Enable); - -/* xdptx.c: General usage functions. */ -u32 XDptx_IsConnected(XDptx *InstancePtr); -void XDptx_EnableMainLink(XDptx *InstancePtr); -void XDptx_DisableMainLink(XDptx *InstancePtr); -void XDptx_ResetPhy(XDptx *InstancePtr, u32 Reset); -void XDptx_SetUserTimerHandler(XDptx *InstancePtr, - XDp_TimerHandler CallbackFunc, void *CallbackRef); -void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds); - -/* xdptx_spm.c: Stream policy maker functions. */ -void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream); -void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr, u8 Stream, - XVidC_VideoMode VideoMode); -void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr, u8 Stream, - u8 *Edid); -void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, u8 Stream, - XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate); -void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 Stream, u8 BitsPerColor); -void XDptx_CfgMsaEnSynchClkMode(XDptx *InstancePtr, u8 Stream, u8 Enable); -void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream); -void XDptx_ClearMsaValues(XDptx *InstancePtr, u8 Stream); -void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream); - -/* xdptx_intr.c: Interrupt handling functions. */ -void XDptx_HpdInterruptHandler(XDptx *InstancePtr); -void XDptx_SetHpdEventHandler(XDptx *InstancePtr, - XDptx_HpdEventHandler CallbackFunc, void *CallbackRef); -void XDptx_SetHpdPulseHandler(XDptx *InstancePtr, - XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef); - -/* xdptx_selftest.c: Self test function. */ -u32 XDptx_SelfTest(XDptx *InstancePtr); - -/* xdptx_mst.c: Multi-stream transport (MST) functions for enabling or disabling - * MST mode. */ -void XDptx_MstCfgModeEnable(XDptx *InstancePtr); -void XDptx_MstCfgModeDisable(XDptx *InstancePtr); -u32 XDptx_MstCapable(XDptx *InstancePtr); -u32 XDptx_MstEnable(XDptx *InstancePtr); -u32 XDptx_MstDisable(XDptx *InstancePtr); - -/* xdptx_mst.c: Multi-stream transport (MST) functions for enabling or disabling - * MST streams and selecting their associated target sinks. */ -void XDptx_MstCfgStreamEnable(XDptx *InstancePtr, u8 Stream); -void XDptx_MstCfgStreamDisable(XDptx *InstancePtr, u8 Stream); -u8 XDptx_MstStreamIsEnabled(XDptx *InstancePtr, u8 Stream); -void XDptx_SetStreamSelectFromSinkList(XDptx *InstancePtr, u8 Stream, u8 - SinkNum); -void XDptx_SetStreamSinkRad(XDptx *InstancePtr, u8 Stream, u8 LinkCountTotal, - u8 *RelativeAddress); - -/* xdptx_mst.c: Multi-stream transport (MST) functions related to MST topology - * discovery and management. */ -u32 XDptx_DiscoverTopology(XDptx *InstancePtr); -u32 XDptx_FindAccessibleDpDevices(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress); -void XDptx_TopologySwapSinks(XDptx *InstancePtr, u8 Index0, u8 Index1); -void XDptx_TopologySortSinksByTiling(XDptx *InstancePtr); - -/* xdptx_mst.c: Multi-stream transport (MST) functions for communicating - * with downstream DisplayPort devices. */ -u32 XDptx_RemoteDpcdRead(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData); -u32 XDptx_RemoteDpcdWrite(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData); -u32 XDptx_RemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress, u8 IicAddress, u16 Offset, u16 BytesToRead, - u8 *ReadData); -u32 XDptx_RemoteIicWrite(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress, u8 IicAddress, u8 BytesToWrite, u8 *WriteData); - -/* xdptx_mst.c: Multi-stream transport (MST) functions related to MST stream - * allocation. */ -u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr); -u32 XDptx_AllocatePayloadVcIdTable(XDptx *InstancePtr, u8 VcId, u8 Ts); -u32 XDptx_ClearPayloadVcIdTable(XDptx *InstancePtr); - -/* xdptx_mst.c: Multi-stream transport (MST) functions for issuing sideband - * messages. */ -u32 XDptx_SendSbMsgRemoteDpcdWrite(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData); -u32 XDptx_SendSbMsgRemoteDpcdRead(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData); -u32 XDptx_SendSbMsgRemoteIicWrite(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress, u8 IicDeviceId, u8 BytesToWrite, u8 *WriteData); -u32 XDptx_SendSbMsgRemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress, u8 IicDeviceId, u8 Offset, u8 BytesToRead, - u8 *ReadData); -u32 XDptx_SendSbMsgLinkAddress(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress, XDptx_SbMsgLinkAddressReplyDeviceInfo *DeviceInfo); -u32 XDptx_SendSbMsgEnumPathResources(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress, u16 *AvailPbn, u16 *FullPbn); -u32 XDptx_SendSbMsgAllocatePayload(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress, u8 VcId, u16 Pbn); -u32 XDptx_SendSbMsgClearPayloadIdTable(XDptx *InstancePtr); - -/* xdptx_mst.c: Multi-stream transport (MST) utility functions. */ -void XDptx_WriteGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, - u32 Guid[4]); -void XDptx_GetGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, - u32 *Guid); - -/* xdptx_edid.c: EDID utility functions. */ -u32 XDptx_GetEdid(XDptx *InstancePtr, u8 *Edid); -u32 XDptx_GetRemoteEdid(XDptx *InstancePtr, u8 LinkCountTotal, - u8 *RelativeAddress, u8 *Edid); -u32 XDptx_GetEdidBlock(XDptx *InstancePtr, u8 *Data, u8 BlockNum); -u32 XDptx_GetRemoteEdidBlock(XDptx *InstancePtr, u8 *Data, u8 BlockNum, - u8 LinkCountTotal, u8 *RelativeAddress); -u32 XDptx_GetRemoteEdidDispIdExt(XDptx *InstancePtr, u8 *Data, - u8 LinkCountTotal, u8 *RelativeAddress); -u32 XDptx_GetDispIdDataBlock(u8 *DisplayIdRaw, u8 SectionTag, - u8 **DataBlockPtr); -u32 XDptx_GetRemoteTiledDisplayDb(XDptx *InstancePtr, u8 *EdidExt, - u8 LinkCountTotal, u8 *RelativeAddress, u8 **DataBlockPtr); - -#endif /* XDPTX_H_ */ diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdptx_hw.h b/XilinxProcessorIPLib/drivers/dp/src/xdptx_hw.h deleted file mode 100644 index 876d178a..00000000 --- a/XilinxProcessorIPLib/drivers/dp/src/xdptx_hw.h +++ /dev/null @@ -1,1439 +0,0 @@ -/******************************************************************************* - * - * Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * Use of the Software is limited solely to applications: - * (a) running on a Xilinx device, or - * (b) that interact with a Xilinx device through a bus or interconnect. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Except as contained in this notice, the name of the Xilinx shall not be used - * in advertising or otherwise to promote the sale, use or other dealings in - * this Software without prior written authorization from Xilinx. - * -*******************************************************************************/ -/******************************************************************************/ -/** - * - * @file xdptx_hw.h - * - * This header file contains the identifiers and low-level driver functions (or - * macros) that can be used to access the device. High-level driver functions - * are defined in xdptx.h. - * - * @note None. - * - *
- * MODIFICATION HISTORY:
- *
- * Ver   Who  Date     Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0   als  05/17/14 Initial release.
- *       als  08/03/14 Initial MST addition.
- * 3.0   als  12/16/14 Stream naming now starts at 1 to follow IP.
- * 
- * -*******************************************************************************/ - -#ifndef XDPTX_HW_H_ -/* Prevent circular inclusions by using protection macros. */ -#define XDPTX_HW_H_ - -/***************************** Include Files **********************************/ - -#include "xil_io.h" - -/************************** Constant Definitions ******************************/ - -/******************************************************************************/ -/** - * Address mapping for the DisplayPort TX core. - * -*******************************************************************************/ -/** @name DPTX core registers: Link configuration field. - * @{ - */ -#define XDPTX_LINK_BW_SET 0x0000 /**< Set main link bandwidth - setting. */ -#define XDPTX_LANE_COUNT_SET 0x0004 /**< Set lane count setting. */ -#define XDPTX_ENHANCED_FRAME_EN 0x0008 /**< Enable enhanced framing - symbol sequence. */ -#define XDPTX_TRAINING_PATTERN_SET 0x000C /**< Set the link training - pattern. */ -#define XDPTX_LINK_QUAL_PATTERN_SET 0x0010 /**< Transmit the link quality - pattern. */ -#define XDPTX_SCRAMBLING_DISABLE 0x0014 /**< Disable scrambler and - transmit all symbols. */ -#define XDPTX_DOWNSPREAD_CTRL 0x0018 /**< Enable a 0.5% spreading of - the clock. */ -#define XDPTX_SOFT_RESET 0x001C /**< Software reset. */ -/* @} */ - -/** @name DPTX core registers: Core enables. - * @{ - */ -#define XDPTX_ENABLE 0x0080 /**< Enable the basic operations - of the DisplayPort TX - core or output stuffing - symbols if disabled. */ -#define XDPTX_ENABLE_MAIN_STREAM 0x0084 /**< Enable transmission of main - link video info. */ -#define XDPTX_ENABLE_SEC_STREAM 0x0088 /**< Enable the transmission of - secondary link info. */ -#define XDPTX_FORCE_SCRAMBLER_RESET 0x00C0 /**< Force a scrambler reset. */ -#define XDPTX_TX_MST_CONFIG 0x00D0 /**< Enable MST. */ -/* @} */ - -/** @name DPTX core registers: Core ID. - * @{ - */ -#define XDPTX_VERSION 0x00F8 /**< Version and revision of the - DisplayPort core. */ -#define XDPTX_CORE_ID 0x00FC /**< DisplayPort protocol - version and revision. */ -/* @} */ - -/** @name DPTX core registers: AUX channel interface. - * @{ - */ -#define XDPTX_AUX_CMD 0x0100 /**< Initiates AUX commands. */ -#define XDPTX_AUX_WRITE_FIFO 0x0104 /**< Write data for the current - AUX command. */ -#define XDPTX_AUX_ADDRESS 0x0108 /**< Specifies the address of - current AUX command. */ -#define XDPTX_AUX_CLK_DIVIDER 0x010C /**< Clock divider value for - generating the internal - 1MHz clock. */ -#define XDPTX_TX_USER_FIFO_OVERFLOW 0x0110 /**< Indicates an overflow in - user FIFO. */ -#define XDPTX_INTERRUPT_SIG_STATE 0x0130 /**< The raw signal values for - interupt events. */ -#define XDPTX_AUX_REPLY_DATA 0x0134 /**< Reply data received during - the AUX reply. */ -#define XDPTX_AUX_REPLY_CODE 0x0138 /**< Reply code received from - the most recent AUX - command. */ -#define XDPTX_AUX_REPLY_COUNT 0x013C /**< Number of reply - transactions receieved - over AUX. */ -#define XDPTX_INTERRUPT_STATUS 0x0140 /**< Status for interrupt - events. */ -#define XDPTX_INTERRUPT_MASK 0x0144 /**< Masks the specified - interrupt sources. */ -#define XDPTX_REPLY_DATA_COUNT 0x0148 /**< Total number of data bytes - actually received during - a transaction. */ -#define XDPTX_REPLY_STATUS 0x014C /**< Reply status of most recent - AUX transaction. */ -#define XDPTX_HPD_DURATION 0x0150 /**< Duration of the HPD pulse - in microseconds. */ -/* @} */ - -/** @name DPTX core registers: Main stream attributes for SST / MST STREAM1. - * @{ - */ -#define XDPTX_STREAM1_MSA_START 0x0180 /**< Start of the MSA registers - for stream 1. */ -#define XDPTX_MAIN_STREAM_HTOTAL 0x0180 /**< Total number of clocks in - the horizontal framing - period. */ -#define XDPTX_MAIN_STREAM_VTOTAL 0x0184 /**< Total number of lines in - the video frame. */ -#define XDPTX_MAIN_STREAM_POLARITY 0x0188 /**< Polarity for the video - sync signals. */ -#define XDPTX_MAIN_STREAM_HSWIDTH 0x018C /**< Width of the horizontal - sync pulse. */ -#define XDPTX_MAIN_STREAM_VSWIDTH 0x0190 /**< Width of the vertical sync - pulse. */ -#define XDPTX_MAIN_STREAM_HRES 0x0194 /**< Number of active pixels per - line (the horizontal - resolution). */ -#define XDPTX_MAIN_STREAM_VRES 0x0198 /**< Number of active lines (the - vertical resolution). */ -#define XDPTX_MAIN_STREAM_HSTART 0x019C /**< Number of clocks between - the leading edge of the - horizontal sync and the - start of active data. */ -#define XDPTX_MAIN_STREAM_VSTART 0x01A0 /**< Number of lines between the - leading edge of the - vertical sync and the - first line of active - data. */ -#define XDPTX_MAIN_STREAM_MISC0 0x01A4 /**< Miscellaneous stream - attributes. */ -#define XDPTX_MAIN_STREAM_MISC1 0x01A8 /**< Miscellaneous stream - attributes. */ -#define XDPTX_M_VID 0x01AC /**< M value for the video - stream as computed by - the source core in - asynchronous clock - mode. Must be written - in synchronous mode. */ -#define XDPTX_TU_SIZE 0x01B0 /**< Size of a transfer unit in - the framing logic. */ -#define XDPTX_N_VID 0x01B4 /**< N value for the video - stream as computed by - the source core in - asynchronous clock mode. - Must be written in - synchronous mode. */ -#define XDPTX_USER_PIXEL_WIDTH 0x01B8 /**< Selects the width of the - user data input port. */ -#define XDPTX_USER_DATA_COUNT_PER_LANE 0x01BC /**< Used to translate the - number of pixels per - line to the native - internal 16-bit - datapath. */ -#define XDPTX_MAIN_STREAM_INTERLACED 0x01C0 /**< Video is interlaced. */ -#define XDPTX_MIN_BYTES_PER_TU 0x01C4 /**< The minimum number of bytes - per transfer unit. */ -#define XDPTX_FRAC_BYTES_PER_TU 0x01C8 /**< The fractional component - when calculated the - XDPTX_MIN_BYTES_PER_TU - register value. */ -#define XDPTX_INIT_WAIT 0x01CC /**< Number of initial wait - cycles at the start of a - new line by the framing - logic, allowing enough - data to be buffered in - the input FIFO. */ -#define XDPTX_STREAM1 0x01D0 /**< Average stream symbol - timeslots per MTP - config. */ -#define XDPTX_STREAM2 0x01D4 /**< Average stream symbol - timeslots per MTP - config. */ -#define XDPTX_STREAM3 0x01D8 /**< Average stream symbol - timeslots per MTP - config. */ -#define XDPTX_STREAM4 0x01DC /**< Average stream symbol - timeslots per MTP - config. */ -/* @} */ - -/** @name DPTX core registers: PHY configuration status. - * @{ - */ -#define XDPTX_PHY_CONFIG 0x0200 /**< Transceiver PHY reset and - configuration. */ -#define XDPTX_PHY_VOLTAGE_DIFF_LANE_0 0x0220 /**< Controls the differential - voltage swing. */ -#define XDPTX_PHY_VOLTAGE_DIFF_LANE_1 0x0224 /**< Controls the differential - voltage swing. */ -#define XDPTX_PHY_VOLTAGE_DIFF_LANE_2 0x0228 /**< Controls the differential - voltage swing. */ -#define XDPTX_PHY_VOLTAGE_DIFF_LANE_3 0x022C /**< Controls the differential - voltage swing. */ -#define XDPTX_PHY_TRANSMIT_PRBS7 0x0230 /**< Enable pseudo random bit - sequence 7 pattern - transmission for link - quality assessment. */ -#define XDPTX_PHY_CLOCK_SELECT 0x0234 /**< Instructs the PHY PLL to - generate the proper - clock frequency for the - required link rate. */ -#define XDPTX_TX_PHY_POWER_DOWN 0x0238 /**< Controls PHY power down. */ -#define XDPTX_PHY_PRECURSOR_LANE_0 0x023C /**< Controls the pre-cursor - level. */ -#define XDPTX_PHY_PRECURSOR_LANE_1 0x0240 /**< Controls the pre-cursor - level. */ -#define XDPTX_PHY_PRECURSOR_LANE_2 0x0244 /**< Controls the pre-cursor - level. */ -#define XDPTX_PHY_PRECURSOR_LANE_3 0x0248 /**< Controls the pre-cursor - level. */ -#define XDPTX_PHY_POSTCURSOR_LANE_0 0x024C /**< Controls the post-cursor - level. */ -#define XDPTX_PHY_POSTCURSOR_LANE_1 0x0250 /**< Controls the post-cursor - level. */ -#define XDPTX_PHY_POSTCURSOR_LANE_2 0x0254 /**< Controls the post-cursor - level. */ -#define XDPTX_PHY_POSTCURSOR_LANE_3 0x0258 /**< Controls the post-cursor - level. */ -#define XDPTX_PHY_STATUS 0x0280 /**< Current PHY status. */ -#define XDPTX_GT_DRP_COMMAND 0x02A0 /**< Provides acces to the GT - DRP ports. */ -#define XDPTX_GT_DRP_READ_DATA 0x02A4 /**< Provides access to GT DRP - read data. */ -#define XDPTX_GT_DRP_CHANNEL_STATUS 0x02A8 /**< Provides access to GT DRP - channel status. */ -/* @} */ - -/** @name DPTX core registers: DisplayPort audio. - * @{ - */ -#define XDPTX_TX_AUDIO_CONTROL 0x0300 /**< Enables audio stream - packets in main link and - buffer control. */ -#define XDPTX_TX_AUDIO_CHANNELS 0x0304 /**< Used to input active - channel count. */ -#define XDPTX_TX_AUDIO_INFO_DATA(NUM) (0x0308 + 4 * (NUM - 1)) /**< Word - formatted as per CEA - 861-C info frame. */ -#define XDPTX_TX_AUDIO_MAUD 0x0328 /**< M value of audio stream - as computed by the - DisplayPort TX core when - audio and link clocks - are synchronous. */ -#define XDPTX_TX_AUDIO_NAUD 0x032C /**< N value of audio stream - as computed by the - DisplayPort TX core when - audio and link clocks - are synchronous. */ -#define XDPTX_TX_AUDIO_EXT_DATA(NUM) (0x0330 + 4 * (NUM - 1)) /**< Word - formatted as per - extension packet. */ -/* @} */ - -/** @name DPTX core registers: Main stream attributes for MST STREAM2, 3, and 4. - * @{ - */ -#define XDPTX_STREAM2_MSA_START 0x0500 /**< Start of the MSA registers - for stream 2. */ -#define XDPTX_STREAM2_MSA_START_OFFSET (XDPTX_STREAM2_MSA_START - \ - XDPTX_STREAM1_MSA_START) /**< The MSA registers for - stream 2 are at an - offset from the - corresponding registers - of stream 1. */ -#define XDPTX_STREAM3_MSA_START 0x0550 /**< Start of the MSA registers - for stream 3. */ -#define XDPTX_STREAM3_MSA_START_OFFSET (XDPTX_STREAM3_MSA_START - \ - XDPTX_STREAM1_MSA_START) /**< The MSA registers for - stream 3 are at an - offset from the - corresponding registers - of stream 1. */ -#define XDPTX_STREAM4_MSA_START 0x05A0 /**< Start of the MSA registers - for stream 4. */ -#define XDPTX_STREAM4_MSA_START_OFFSET (XDPTX_STREAM4_MSA_START - \ - XDPTX_STREAM1_MSA_START) /**< The MSA registers for - stream 4 are at an - offset from the - corresponding registers - of stream 1. */ -/* @} */ - -#define XDPTX_VC_PAYLOAD_BUFFER_ADDR 0x0800 /**< Virtual channel payload - table (0xFF bytes). */ - -/******************************************************************************/ - -/** @name DPTX core masks, shifts, and register values. - * @{ - */ -/* 0x000: LINK_BW_SET */ -#define XDPTX_LINK_BW_SET_162GBPS 0x06 /**< 1.62 Gbps link rate. */ -#define XDPTX_LINK_BW_SET_270GBPS 0x0A /**< 2.70 Gbps link rate. */ -#define XDPTX_LINK_BW_SET_540GBPS 0x14 /**< 5.40 Gbps link rate. */ -/* 0x001: LANE_COUNT_SET */ -#define XDPTX_LANE_COUNT_SET_1 0x01 /**< Lane count of 1. */ -#define XDPTX_LANE_COUNT_SET_2 0x02 /**< Lane count of 2. */ -#define XDPTX_LANE_COUNT_SET_4 0x04 /**< Lane count of 4. */ -/* 0x00C: TRAINING_PATTERN_SET */ -#define XDPTX_TRAINING_PATTERN_SET_OFF 0x0 /**< Training off. */ -#define XDPTX_TRAINING_PATTERN_SET_TP1 0x1 /**< Training pattern 1 used for - clock recovery. */ -#define XDPTX_TRAINING_PATTERN_SET_TP2 0x2 /**< Training pattern 2 used for - channel equalization. */ -#define XDPTX_TRAINING_PATTERN_SET_TP3 0x3 /**< Training pattern 3 used for - channel equalization for - cores with DP v1.2. */ -/* 0x010: LINK_QUAL_PATTERN_SET */ -#define XDPTX_LINK_QUAL_PATTERN_SET_OFF 0x0 /**< Link quality test pattern - not transmitted. */ -#define XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST \ - 0x1 /**< D10.2 unscrambled test - pattern transmitted. */ -#define XDPTX_LINK_QUAL_PATTERN_SET_SER_MES \ - 0x2 /**< Symbol error rate - measurement pattern - transmitted. */ -#define XDPTX_LINK_QUAL_PATTERN_SET_PRBS7 \ - 0x3 /**< Pseudo random bit sequence - 7 transmitted. */ -/* 0x01C: SOFTWARE_RESET */ -#define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK \ - 0x00000001 /**< Reset video logic. */ -#define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK \ - 0x00000002 /**< Reset video logic. */ -#define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK \ - 0x00000004 /**< Reset video logic. */ -#define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK \ - 0x00000008 /**< Reset video logic. */ -#define XDPTX_SOFT_RESET_AUX_MASK \ - 0x00000080 /**< Reset AUX logic. */ -#define XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK \ - 0x0000000F /**< Reset video logic for all - streams. */ -/* 0x0D0: TX_MST_CONFIG */ -#define XDPTX_TX_MST_CONFIG_MST_EN_MASK \ - 0x00000001 /**< Enable MST. */ -#define XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK \ - 0x00000002 /**< The VC payload has been - updated in the sink. */ -/* 0x0F8: VERSION */ -#define XDPTX_VERSION_INTER_REV_MASK \ - 0x0000000F /**< Internal revision. */ -#define XDPTX_VERSION_CORE_PATCH_MASK \ - 0x00000030 /**< Core patch details. */ -#define XDPTX_VERSION_CORE_PATCH_SHIFT \ - 8 /**< Shift bits for core patch - details. */ -#define XDPTX_VERSION_CORE_VER_REV_MASK \ - 0x000000C0 /**< Core version revision. */ -#define XDPTX_VERSION_CORE_VER_REV_SHIFT \ - 12 /**< Shift bits for core version - revision. */ -#define XDPTX_VERSION_CORE_VER_MNR_MASK \ - 0x00000F00 /**< Core minor version. */ -#define XDPTX_VERSION_CORE_VER_MNR_SHIFT \ - 16 /**< Shift bits for core minor - version. */ -#define XDPTX_VERSION_CORE_VER_MJR_MASK \ - 0x0000F000 /**< Core major version. */ -#define XDPTX_VERSION_CORE_VER_MJR_SHIFT \ - 24 /**< Shift bits for core major - version. */ -/* 0x0FC: CORE_ID */ -#define XDPTX_CORE_ID_TYPE_MASK 0x0000000F /**< Core type. */ -#define XDPTX_CORE_ID_TYPE_TX 0x0 /**< Core is a transmitter. */ -#define XDPTX_CORE_ID_TYPE_RX 0x1 /**< Core is a receiver. */ -#define XDPTX_CORE_ID_DP_REV_MASK \ - 0x000000F0 /**< DisplayPort protocol - revision. */ -#define XDPTX_CORE_ID_DP_REV_SHIFT \ - 8 /**< Shift bits for DisplayPort - protocol revision. */ -#define XDPTX_CORE_ID_DP_MNR_VER_MASK \ - 0x00000F00 /**< DisplayPort protocol minor - version. */ -#define XDPTX_CORE_ID_DP_MNR_VER_SHIFT \ - 16 /**< Shift bits for DisplayPort - protocol major - version. */ -#define XDPTX_CORE_ID_DP_MJR_VER_MASK \ - 0x0000F000 /**< DisplayPort protocol major - version. */ -#define XDPTX_CORE_ID_DP_MJR_VER_SHIFT \ - 24 /**< Shift bits for DisplayPort - protocol major - version. */ -/* 0x100: AUX_CMD */ -#define XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK \ - 0x0000000F /**< Number of bytes to transfer - with the current AUX - command. */ -#define XDPTX_AUX_CMD_MASK 0x00000F00 /**< AUX command. */ -#define XDPTX_AUX_CMD_SHIFT 8 /**< Shift bits for command. */ -#define XDPTX_AUX_CMD_I2C_WRITE 0x0 /**< I2C-over-AUX write - command. */ -#define XDPTX_AUX_CMD_I2C_READ 0x1 /**< I2C-over-AUX read - command. */ -#define XDPTX_AUX_CMD_I2C_WRITE_STATUS 0x2 /**< I2C-over-AUX write status - command. */ -#define XDPTX_AUX_CMD_I2C_WRITE_MOT 0x4 /**< I2C-over-AUX write MOT - (middle-of-transaction) - command. */ -#define XDPTX_AUX_CMD_I2C_READ_MOT 0x5 /**< I2C-over-AUX read MOT - (middle-of-transaction) - command. */ -#define XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT \ - 0x6 /**< I2C-over-AUX write status - MOT (middle-of- - transaction) command. */ -#define XDPTX_AUX_CMD_WRITE 0x8 /**< AUX write command. */ -#define XDPTX_AUX_CMD_READ 0x9 /**< AUX read command. */ -#define XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN \ - 0x00001000 /**< Address only transfer - enable (STOP will be - sent after command). */ -/* 0x10C: AUX_CLK_DIVIDER */ -#define XDPTX_AUX_CLK_DIVIDER_VAL_MASK 0x00FF /**< Clock divider value. */ -#define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK \ - 0xFF00 /**< AUX (noise) signal width - filter. */ -#define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT \ - 8 /**< Shift bits for AUX signal - width filter. */ -/* 0x130: INTERRUPT_SIG_STATE */ -#define XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK \ - 0x00000001 /**< Raw state of the HPD pin on - the DP connector. */ -#define XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK \ - 0x00000002 /**< A request is currently - being sent. */ -#define XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK \ - 0x00000004 /**< A reply is currently being - received. */ -#define XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK \ - 0x00000008 /**< A reply timeout has - occurred. */ -/* 0x138: AUX_REPLY_CODE */ -#define XDPTX_AUX_REPLY_CODE_ACK 0x0 /**< AUX command ACKed. */ -#define XDPTX_AUX_REPLY_CODE_I2C_ACK 0x0 /**< I2C-over-AUX command - not ACKed. */ -#define XDPTX_AUX_REPLY_CODE_NACK 0x1 /**< AUX command not ACKed. */ -#define XDPTX_AUX_REPLY_CODE_DEFER 0x2 /**< AUX command deferred. */ -#define XDPTX_AUX_REPLY_CODE_I2C_NACK 0x4 /**< I2C-over-AUX command not - ACKed. */ -#define XDPTX_AUX_REPLY_CODE_I2C_DEFER 0x8 /**< I2C-over-AUX command - deferred. */ -/* 0x140: INTERRUPT_STATUS */ -#define XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK \ - 0x00000001 /**< Detected an IRQ framed with - the proper timing on the - HPD signal. */ -#define XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK \ - 0x00000002 /**< Detected the presence of - the HPD signal. */ -#define XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK \ - 0x00000004 /**< An AUX reply transaction - has been detected. */ -#define XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK \ - 0x00000008 /**< A reply timeout has - occurred. */ -#define XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK \ - 0x00000010 /**< A pulse on the HPD line was - detected. */ -#define XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK \ - 0x00000020 /**< Extended packet has been - transmitted and the core - is ready to accept a new - packet. */ -/* 0x144: INTERRUPT_MASK */ -#define XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK \ - 0x00000001 /**< Mask HPD IRQ interrupt. */ -#define XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK \ - 0x00000002 /**< Mask HPD event - interrupt. */ -#define XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK \ - 0x00000004 /**< Mask reply received - interrupt. */ -#define XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK \ - 0x00000008 /**< Mask reply received - interrupt. */ -#define XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK \ - 0x00000010 /**< Mask HPD pulse detected - interrupt. */ -#define XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK \ - 0x00000020 /**< Mask extended packet - transmit interrupt. */ -/* 0x14C: REPLY_STATUS */ -#define XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK \ - 0x00000001 /**< AUX transaction is complete - and a valid reply - transaction received. */ -#define XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK \ - 0x00000002 /**< AUX reply is currently - being received. */ -#define XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK \ - 0x00000004 /**< AUX request is currently - being transmitted. */ -#define XDPTX_REPLY_STATUS_REPLY_ERROR_MASK \ - 0x00000008 /**< Detected an error in the - AUX reply of the most - recent transaction. */ -#define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK \ - 0x00000FF0 /**< Internal AUX reply state - machine status bits. */ -#define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT \ - 4 /**< Shift bits for the internal - AUX reply state machine - status. */ -/* 0x188, 0x508, 0x558, 0x5A8: MAIN_STREAM[1-4]_POLARITY */ -#define XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK \ - 0x00000001 /**< Polarity of the horizontal - sync pulse. */ -#define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK \ - 0x00000002 /**< Polarity of the vertical - sync pulse. */ -#define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT \ - 1 /**< Shift bits for polarity of - the vertical sync - pulse. */ -/* 0x1A4, 0x524, 0x574, 0x5C4: MAIN_STREAM[1-4]_MISC0 */ -#define XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK \ - 0x00000001 /**< Synchronous clock. */ -#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK \ - 0x00000006 /**< Component format. */ -#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT \ - 1 /**< Shift bits for component - format. */ -#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB \ - 0x0 /**< Stream's component format - is RGB. */ -#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 \ - 0x1 /**< Stream's component format - is YcbCr 4:2:2. */ -#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 \ - 0x2 /**< Stream's component format - is YcbCr 4:4:4. */ -#define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK \ - 0x00000008 /**< Dynamic range. */ -#define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT \ - 3 /**< Shift bits for dynamic - range. */ -#define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK \ - 0x00000010 /**< YCbCr colorimetry. */ -#define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT \ - 4 /**< Shift bits for YCbCr - colorimetry. */ -#define XDPTX_MAIN_STREAMX_MISC0_BDC_MASK \ - 0x000000E0 /**< Bit depth per color - component (BDC). */ -#define XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT \ - 5 /**< Shift bits for BDC.*/ -#define XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC \ - 0x0 /**< 6 bits per component.*/ -#define XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC \ - 0x1 /**< 8 bits per component.*/ -#define XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC \ - 0x2 /**< 10 bits per component.*/ -#define XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC \ - 0x3 /**< 12 bits per component.*/ -#define XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC \ - 0x4 /**< 16 bits per component.*/ -/* 0x1A8, 0x528, 0x578, 0x5C8: MAIN_STREAM[1-4]_MISC1 */ -#define XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK \ - 0x00000001 /**< Interlaced vertical total - even. */ -#define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK \ - 0x00000006 /**< Stereo video attribute. */ -#define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT \ - 1 /**< Shift bits for stereo video - attribute. */ -/* 0x200: PHY_CONFIG */ -#define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK \ - 0x0000000 /**< Release reset. */ -#define XDPTX_PHY_CONFIG_PHY_RESET_MASK \ - 0x0000001 /**< Hold the PHY in reset. */ -#define XDPTX_PHY_CONFIG_GTTX_RESET_MASK \ - 0x0000002 /**< Hold GTTXRESET in reset. */ -#define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK \ - 0x0000100 /**< Hold TX_PHY_PMA reset. */ -#define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK \ - 0x0000200 /**< Hold TX_PHY_PCS reset. */ -#define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK \ - 0x0000400 /**< Set TX_PHY_POLARITY. */ -#define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK \ - 0x0001000 /**< Set TX_PHY_PRBSFORCEERR. */ -#define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK \ - 0x000E000 /**< Set TX_PHY_LOOPBACK. */ -#define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK \ - 0x0000003 /**< Rest GT and PHY. */ -/* 0x234: PHY_CLOCK_SELECT */ -#define XDPTX_PHY_CLOCK_SELECT_162GBPS 0x1 /**< 1.62 Gbps link. */ -#define XDPTX_PHY_CLOCK_SELECT_270GBPS 0x3 /**< 2.70 Gbps link. */ -#define XDPTX_PHY_CLOCK_SELECT_540GBPS 0x5 /**< 5.40 Gbps link. */ -/* 0x0220, 0x0224, 0x0228, 0x022C: XDPTX_PHY_VOLTAGE_DIFF_LANE_[0-3] */ -#define XDPTX_VS_LEVEL_0 0x2 /**< Voltage swing level 0. */ -#define XDPTX_VS_LEVEL_1 0x5 /**< Voltage swing level 1. */ -#define XDPTX_VS_LEVEL_2 0x8 /**< Voltage swing level 2. */ -#define XDPTX_VS_LEVEL_3 0xF /**< Voltage swing level 3. */ -#define XDPTX_VS_LEVEL_OFFSET 0x4 /**< Voltage swing compensation - offset used when there's - no redriver in display - path. */ -/* 0x024C, 0x0250, 0x0254, 0x0258: XDPTX_PHY_POSTCURSOR_LANE_[0-3] */ -#define XDPTX_PE_LEVEL_0 0x00 /**< Pre-emphasis level 0. */ -#define XDPTX_PE_LEVEL_1 0x0E /**< Pre-emphasis level 1. */ -#define XDPTX_PE_LEVEL_2 0x14 /**< Pre-emphasis level 2. */ -#define XDPTX_PE_LEVEL_3 0x1B /**< Pre-emphasis level 3. */ -/* 0x280: PHY_STATUS */ -#define XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK \ - 0x00000003 /**< Reset done for lanes - 0 and 1. */ -#define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK \ - 0x0000000C /**< Reset done for lanes - 2 and 3. */ -#define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT \ - 2 /**< Shift bits for reset done - for lanes 2 and 3. */ -#define XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK \ - 0x00000010 /**< PLL locked for lanes - 0 and 1. */ -#define XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK \ - 0x00000020 /**< PLL locked for lanes - 2 and 3. */ -#define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK \ - 0x00000040 /**< FPGA fabric clock PLL - locked. */ -#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK \ - 0x00030000 /**< TX buffer status lane 0. */ -#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT \ - 16 /**< Shift bits for TX buffer - status lane 0. */ -#define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK \ - 0x000C0000 /**< TX error on lane 0. */ -#define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT \ - 18 /**< Shift bits for TX error on - lane 0. */ -#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK \ - 0x00300000 /**< TX buffer status lane 1. */ -#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT \ - 20 /**< Shift bits for TX buffer - status lane 1. */ -#define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK \ - 0x00C00000 /**< TX error on lane 1. */ -#define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT \ - 22 /**< Shift bits for TX error on - lane 1. */ -#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK \ - 0x03000000 /**< TX buffer status lane 2. */ -#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT \ - 24 /**< Shift bits for TX buffer - status lane 2. */ -#define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK \ - 0x0C000000 /**< TX error on lane 2. */ -#define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT \ - 26 /**< Shift bits for TX error on - lane 2. */ -#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK \ - 0x30000000 /**< TX buffer status lane 3. */ -#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT \ - 28 /**< Shift bits for TX buffer - status lane 3. */ -#define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK \ - 0xC0000000 /**< TX error on lane 3. */ -#define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT \ - 30 /**< Shift bits for TX error on - lane 3. */ -#define XDPTX_PHY_STATUS_LANES_0_1_READY_MASK \ - 0x00000013 /**< Lanes 0 and 1 are ready. */ -#define XDPTX_PHY_STATUS_ALL_LANES_READY_MASK \ - 0x0000003F /**< All lanes are ready. */ -/* 0x2A0: XDPTX_GT_DRP_COMMAND */ -#define XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK \ - 0x000F /**< DRP address. */ -#define XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK \ - 0x0080 /**< DRP read/write command - (Read=0, Write=1). */ -#define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK \ - 0xFF00 /**< DRP write data. */ -#define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT \ - 16 /**< Shift bits for DRP write - data. */ -/* @} */ - -/******************************************************************************/ - -/******************************************************************************/ -/** - * Address mapping for the DisplayPort Configuration Data (DPCD) of the - * downstream device. - * -*******************************************************************************/ -/** @name DisplayPort Configuration Data: Receiver capability field. - * @{ - */ -#define XDPTX_DPCD_REV 0x00000 -#define XDPTX_DPCD_MAX_LINK_RATE 0x00001 -#define XDPTX_DPCD_MAX_LANE_COUNT 0x00002 -#define XDPTX_DPCD_MAX_DOWNSPREAD 0x00003 -#define XDPTX_DPCD_NORP_PWR_V_CAP 0x00004 -#define XDPTX_DPCD_DOWNSP_PRESENT 0x00005 -#define XDPTX_DPCD_ML_CH_CODING_CAP 0x00006 -#define XDPTX_DPCD_DOWNSP_COUNT_MSA_OUI 0x00007 -#define XDPTX_DPCD_RX_PORT0_CAP_0 0x00008 -#define XDPTX_DPCD_RX_PORT0_CAP_1 0x00009 -#define XDPTX_DPCD_RX_PORT1_CAP_0 0x0000A -#define XDPTX_DPCD_RX_PORT1_CAP_1 0x0000B -#define XDPTX_DPCD_I2C_SPEED_CTL_CAP 0x0000C -#define XDPTX_DPCD_EDP_CFG_CAP 0x0000D -#define XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E -#define XDPTX_DPCD_ADAPTER_CAP 0x0000F -#define XDPTX_DPCD_FAUX_CAP 0x00020 -#define XDPTX_DPCD_MSTM_CAP 0x00021 -#define XDPTX_DPCD_NUM_AUDIO_EPS 0x00022 -#define XDPTX_DPCD_AV_GRANULARITY 0x00023 -#define XDPTX_DPCD_AUD_DEC_LAT_7_0 0x00024 -#define XDPTX_DPCD_AUD_DEC_LAT_15_8 0x00025 -#define XDPTX_DPCD_AUD_PP_LAT_7_0 0x00026 -#define XDPTX_DPCD_AUD_PP_LAT_15_8 0x00027 -#define XDPTX_DPCD_VID_INTER_LAT 0x00028 -#define XDPTX_DPCD_VID_PROG_LAT 0x00029 -#define XDPTX_DPCD_REP_LAT 0x0002A -#define XDPTX_DPCD_AUD_DEL_INS_7_0 0x0002B -#define XDPTX_DPCD_AUD_DEL_INS_15_8 0x0002C -#define XDPTX_DPCD_AUD_DEL_INS_23_16 0x0002D -#define XDPTX_DPCD_GUID 0x00030 -#define XDPTX_DPCD_RX_GTC_VALUE_7_0 0x00054 -#define XDPTX_DPCD_RX_GTC_VALUE_15_8 0x00055 -#define XDPTX_DPCD_RX_GTC_VALUE_23_16 0x00056 -#define XDPTX_DPCD_RX_GTC_VALUE_31_24 0x00057 -#define XDPTX_DPCD_RX_GTC_MSTR_REQ 0x00058 -#define XDPTX_DPCD_RX_GTC_FREQ_LOCK_DONE 0x00059 -#define XDPTX_DPCD_DOWNSP_0_CAP 0x00080 -#define XDPTX_DPCD_DOWNSP_1_CAP 0x00081 -#define XDPTX_DPCD_DOWNSP_2_CAP 0x00082 -#define XDPTX_DPCD_DOWNSP_3_CAP 0x00083 -#define XDPTX_DPCD_DOWNSP_0_DET_CAP 0x00080 -#define XDPTX_DPCD_DOWNSP_1_DET_CAP 0x00084 -#define XDPTX_DPCD_DOWNSP_2_DET_CAP 0x00088 -#define XDPTX_DPCD_DOWNSP_3_DET_CAP 0x0008C -/* @} */ - -/** @name DisplayPort Configuration Data: Link configuration field. - * @{ - */ -#define XDPTX_DPCD_LINK_BW_SET 0x00100 -#define XDPTX_DPCD_LANE_COUNT_SET 0x00101 -#define XDPTX_DPCD_TP_SET 0x00102 -#define XDPTX_DPCD_TRAINING_LANE0_SET 0x00103 -#define XDPTX_DPCD_TRAINING_LANE1_SET 0x00104 -#define XDPTX_DPCD_TRAINING_LANE2_SET 0x00105 -#define XDPTX_DPCD_TRAINING_LANE3_SET 0x00106 -#define XDPTX_DPCD_DOWNSPREAD_CTRL 0x00107 -#define XDPTX_DPCD_ML_CH_CODING_SET 0x00108 -#define XDPTX_DPCD_I2C_SPEED_CTL_SET 0x00109 -#define XDPTX_DPCD_EDP_CFG_SET 0x0010A -#define XDPTX_DPCD_LINK_QUAL_LANE0_SET 0x0010B -#define XDPTX_DPCD_LINK_QUAL_LANE1_SET 0x0010C -#define XDPTX_DPCD_LINK_QUAL_LANE2_SET 0x0010D -#define XDPTX_DPCD_LINK_QUAL_LANE3_SET 0x0010E -#define XDPTX_DPCD_TRAINING_LANE0_1_SET2 0x0010F -#define XDPTX_DPCD_TRAINING_LANE2_3_SET2 0x00110 -#define XDPTX_DPCD_MSTM_CTRL 0x00111 -#define XDPTX_DPCD_AUDIO_DELAY_7_0 0x00112 -#define XDPTX_DPCD_AUDIO_DELAY_15_8 0x00113 -#define XDPTX_DPCD_AUDIO_DELAY_23_6 0x00114 -#define XDPTX_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED 0x00118 -#define XDPTX_DPCD_FAUX_MODE_CTRL 0x00120 -#define XDPTX_DPCD_FAUX_FORWARD_CH_DRIVE_SET 0x00121 -#define XDPTX_DPCD_BACK_CH_STATUS 0x00122 -#define XDPTX_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT 0x00123 -#define XDPTX_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME 0x00125 -#define XDPTX_DPCD_TX_GTC_VALUE_7_0 0x00154 -#define XDPTX_DPCD_TX_GTC_VALUE_15_8 0x00155 -#define XDPTX_DPCD_TX_GTC_VALUE_23_16 0x00156 -#define XDPTX_DPCD_TX_GTC_VALUE_31_24 0x00157 -#define XDPTX_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN 0x00158 -#define XDPTX_DPCD_TX_GTC_FREQ_LOCK_DONE 0x00159 -#define XDPTX_DPCD_ADAPTER_CTRL 0x001A0 -#define XDPTX_DPCD_BRANCH_DEVICE_CTRL 0x001A1 -#define XDPTX_DPCD_PAYLOAD_ALLOCATE_SET 0x001C0 -#define XDPTX_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x001C1 -#define XDPTX_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x001C2 -/* @} */ - -/** @name DisplayPort Configuration Data: Link/sink status field. - * @{ - */ -#define XDPTX_DPCD_SINK_COUNT 0x00200 -#define XDPTX_DPCD_DEVICE_SERVICE_IRQ 0x00201 -#define XDPTX_DPCD_STATUS_LANE_0_1 0x00202 -#define XDPTX_DPCD_STATUS_LANE_2_3 0x00203 -#define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED 0x00204 -#define XDPTX_DPCD_SINK_STATUS 0x00205 -#define XDPTX_DPCD_ADJ_REQ_LANE_0_1 0x00206 -#define XDPTX_DPCD_ADJ_REQ_LANE_2_3 0x00207 -#define XDPTX_DPCD_TRAINING_SCORE_LANE_0 0x00208 -#define XDPTX_DPCD_TRAINING_SCORE_LANE_1 0x00209 -#define XDPTX_DPCD_TRAINING_SCORE_LANE_2 0x0020A -#define XDPTX_DPCD_TRAINING_SCORE_LANE_3 0x0020B -#define XDPTX_DPCD_ADJ_REQ_PC2 0x0020C -#define XDPTX_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT 0x0020D -#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_0 0x00210 -#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_1 0x00212 -#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_2 0x00214 -#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_3 0x00216 -/* @} */ - -/** @name DisplayPort Configuration Data: Automated testing sub-field. - * @{ - */ -#define XDPTX_DPCD_FAUX_FORWARD_CH_STATUS 0x00280 -#define XDPTX_DPCD_FAUX_BACK_CH_DRIVE_SET 0x00281 -#define XDPTX_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL 0x00282 -#define XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS 0x002C0 -#define XDPTX_DPCD_VC_PAYLOAD_ID_SLOT(SlotNum) \ - (XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum) -/* @} */ - -/** @name DisplayPort Configuration Data: Sink control field. - * @{ - */ -#define XDPTX_DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600 -/* @} */ - -/** @name DisplayPort Configuration Data: Sideband message buffers. - * @{ - */ -#define XDPTX_DPCD_DOWN_REQ 0x01000 -#define XDPTX_DPCD_UP_REP 0x01200 -#define XDPTX_DPCD_DOWN_REP 0x01400 -#define XDPTX_DPCD_UP_REQ 0x01600 -/* @} */ - -/** @name DisplayPort Configuration Data: Event status indicator field. - * @{ - */ -#define XDPTX_DPCD_SINK_COUNT_ESI 0x02002 -#define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x02003 -#define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x02004 -#define XDPTX_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0 0x02005 -#define XDPTX_DPCD_SINK_LANE0_1_STATUS 0x0200C -#define XDPTX_DPCD_SINK_LANE2_3_STATUS 0x0200D -#define XDPTX_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI 0x0200E -#define XDPTX_DPCD_SINK_STATUS_ESI 0x0200F -/* @} */ - -/** @name DisplayPort Configuration Data: Field addresses and sizes. - * @{ - */ -#define XDPTX_DPCD_RECEIVER_CAP_FIELD_START XDPTX_DPCD_REV -#define XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE 0x100 -#define XDPTX_DPCD_LINK_CFG_FIELD_START XDPTX_DPCD_LINK_BW_SET -#define XDPTX_DPCD_LINK_CFG_FIELD_SIZE 0x100 -#define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_START XDPTX_DPCD_SINK_COUNT -#define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_SIZE 0x17 -/* @} */ - -/******************************************************************************/ - -/** @name DisplayPort Configuration Data: Receiver capability field masks, - * shifts, and register values. - * @{ - */ -/* 0x00000: DPCD_REV */ -#define XDPTX_DPCD_REV_MNR_MASK 0x0F -#define XDPTX_DPCD_REV_MJR_MASK 0xF0 -#define XDPTX_DPCD_REV_MJR_SHIFT 4 -/* 0x00001: MAX_LINK_RATE */ -#define XDPTX_DPCD_MAX_LINK_RATE_162GBPS 0x06 -#define XDPTX_DPCD_MAX_LINK_RATE_270GBPS 0x0A -#define XDPTX_DPCD_MAX_LINK_RATE_540GBPS 0x14 -/* 0x00002: MAX_LANE_COUNT */ -#define XDPTX_DPCD_MAX_LANE_COUNT_MASK 0x1F -#define XDPTX_DPCD_MAX_LANE_COUNT_1 0x01 -#define XDPTX_DPCD_MAX_LANE_COUNT_2 0x02 -#define XDPTX_DPCD_MAX_LANE_COUNT_4 0x04 -#define XDPTX_DPCD_TPS3_SUPPORT_MASK 0x40 -#define XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80 -/* 0x00003: MAX_DOWNSPREAD */ -#define XDPTX_DPCD_MAX_DOWNSPREAD_MASK 0x01 -#define XDPTX_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK 0x40 -/* 0x00005: DOWNSP_PRESENT */ -#define XDPTX_DPCD_DOWNSP_PRESENT_MASK 0x01 -#define XDPTX_DPCD_DOWNSP_TYPE_MASK 0x06 -#define XDPTX_DPCD_DOWNSP_TYPE_SHIFT 1 -#define XDPTX_DPCD_DOWNSP_TYPE_DP 0x0 -#define XDPTX_DPCD_DOWNSP_TYPE_AVGA_ADVII 0x1 -#define XDPTX_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP 0x2 -#define XDPTX_DPCD_DOWNSP_TYPE_OTHERS 0x3 -#define XDPTX_DPCD_DOWNSP_FORMAT_CONV_MASK 0x08 -#define XDPTX_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK 0x10 -/* 0x00006, 0x00108: ML_CH_CODING_SUPPORT, ML_CH_CODING_SET */ -#define XDPTX_DPCD_ML_CH_CODING_MASK 0x01 -/* 0x00007: DOWNSP_COUNT_MSA_OUI */ -#define XDPTX_DPCD_DOWNSP_COUNT_MASK 0x0F -#define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_MASK 0x40 -#define XDPTX_DPCD_OUI_SUPPORT_MASK 0x80 -/* 0x00008, 0x0000A: RX_PORT[0-1]_CAP_0 */ -#define XDPTX_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK 0x02 -#define XDPTX_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK 0x04 -/* 0x0000C, 0x00109: I2C_SPEED_CTL_CAP, I2C_SPEED_CTL_SET */ -#define XDPTX_DPCD_I2C_SPEED_CTL_NONE 0x00 -#define XDPTX_DPCD_I2C_SPEED_CTL_1KBIPS 0x01 -#define XDPTX_DPCD_I2C_SPEED_CTL_5KBIPS 0x02 -#define XDPTX_DPCD_I2C_SPEED_CTL_10KBIPS 0x04 -#define XDPTX_DPCD_I2C_SPEED_CTL_100KBIPS 0x08 -#define XDPTX_DPCD_I2C_SPEED_CTL_400KBIPS 0x10 -#define XDPTX_DPCD_I2C_SPEED_CTL_1MBIPS 0x20 -/* 0x0000E: TRAIN_AUX_RD_INTERVAL */ -#define XDPTX_DPCD_TRAIN_AUX_RD_INT_100_400US 0x00 -#define XDPTX_DPCD_TRAIN_AUX_RD_INT_4MS 0x01 -#define XDPTX_DPCD_TRAIN_AUX_RD_INT_8MS 0x02 -#define XDPTX_DPCD_TRAIN_AUX_RD_INT_12MS 0x03 -#define XDPTX_DPCD_TRAIN_AUX_RD_INT_16MS 0x04 -/* 0x00020: DPCD_FAUX_CAP */ -#define XDPTX_DPCD_FAUX_CAP_MASK 0x01 -/* 0x00021: MSTM_CAP */ -#define XDPTX_DPCD_MST_CAP_MASK 0x01 -/* 0x00080, 0x00081|4, 0x00082|8, 0x00083|C: DOWNSP_X_(DET_)CAP */ -#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_MASK 0x07 -#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DP 0x0 -#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_AVGA 0x1 -#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DVI 0x2 -#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_HDMI 0x3 -#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_OTHERS 0x4 -#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DPPP 0x5 -#define XDPTX_DPCD_DOWNSP_X_CAP_HPD_MASK 0x80 -#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK 0xF0 -#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT 4 -#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60 0x1 -#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50 0x2 -#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60 0x3 -#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50 0x4 -#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60 0x5 -#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50 0x7 -/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */ -#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK 0x03 -#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_8 0x0 -#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_10 0x1 -#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_12 0x2 -#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_16 0x3 -/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */ -#define XDPTX_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK 0x01 -#define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK 0x02 -#define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK 0x04 -/* @} */ - -/** @name DisplayPort Configuration Data: Link configuration field masks, - * shifts, and register values. - * @{ - */ -/* 0x00100: XDPTX_DPCD_LINK_BW_SET */ -#define XDPTX_DPCD_LINK_BW_SET_162GBPS 0x06 -#define XDPTX_DPCD_LINK_BW_SET_270GBPS 0x0A -#define XDPTX_DPCD_LINK_BW_SET_540GBPS 0x14 -/* 0x00101: LANE_COUNT_SET */ -#define XDPTX_DPCD_LANE_COUNT_SET_MASK 0x1F -#define XDPTX_DPCD_LANE_COUNT_SET_1 0x01 -#define XDPTX_DPCD_LANE_COUNT_SET_2 0x02 -#define XDPTX_DPCD_LANE_COUNT_SET_4 0x04 -#define XDPTX_DPCD_ENHANCED_FRAME_EN_MASK 0x80 -/* 0x00102: TP_SET */ -#define XDPTX_DPCD_TP_SEL_MASK 0x03 -#define XDPTX_DPCD_TP_SEL_OFF 0x0 -#define XDPTX_DPCD_TP_SEL_TP1 0x1 -#define XDPTX_DPCD_TP_SEL_TP2 0x2 -#define XDPTX_DPCD_TP_SEL_TP3 0x3 -#define XDPTX_DPCD_TP_SET_LQP_MASK 0x06 -#define XDPTX_DPCD_TP_SET_LQP_SHIFT 2 -#define XDPTX_DPCD_TP_SET_LQP_OFF 0x0 -#define XDPTX_DPCD_TP_SET_LQP_D102_TEST 0x1 -#define XDPTX_DPCD_TP_SET_LQP_SER_MES 0x2 -#define XDPTX_DPCD_TP_SET_LQP_PRBS7 0x3 -#define XDPTX_DPCD_TP_SET_REC_CLK_OUT_EN_MASK 0x10 -#define XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK 0x20 -#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_MASK 0xC0 -#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_SHIFT 6 -#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE 0x0 -#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE 0x1 -#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_ISE 0x2 -/* 0x00103-0x00106: TRAINING_LANE[0-3]_SET */ -#define XDPTX_DPCD_TRAINING_LANEX_SET_VS_MASK 0x03 -#define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04 -#define XDPTX_DPCD_TRAINING_LANEX_SET_PE_MASK 0x18 -#define XDPTX_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 -#define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20 -/* 0x00107: DOWNSPREAD_CTRL */ -#define XDPTX_DPCD_SPREAD_AMP_MASK 0x10 -#define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK 0x80 -/* 0x00108: ML_CH_CODING_SET - Same as 0x00006: ML_CH_CODING_SUPPORT */ -/* 0x00109: I2C_SPEED_CTL_SET - Same as 0x0000C: I2C_SPEED_CTL_CAP */ -/* 0x0010F-0x00110: TRAINING_LANE[0_1-2_3]_SET2 */ -#define XDPTX_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK 0x03 -#define XDPTX_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK 0x04 -#define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK 0x30 -#define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT 4 -#define XDPTX_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK 0x40 -/* 0x00111: MSTM_CTRL */ -#define XDPTX_DPCD_MST_EN_MASK 0x01 -#define XDPTX_DPCD_UP_REQ_EN_MASK 0x02 -#define XDPTX_DPCD_UP_IS_SRC_MASK 0x03 -/* @} */ - -/** @name DisplayPort Configuration Data: Link/sink status field masks, shifts, - * and register values. - * @{ - */ -/* 0x00202: STATUS_LANE_0_1 */ -#define XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01 -#define XDPTX_DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02 -#define XDPTX_DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04 -#define XDPTX_DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10 -#define XDPTX_DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20 -#define XDPTX_DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40 -/* 0x00202: STATUS_LANE_2_3 */ -#define XDPTX_DPCD_STATUS_LANE_2_CR_DONE_MASK 0x01 -#define XDPTX_DPCD_STATUS_LANE_2_CE_DONE_MASK 0x02 -#define XDPTX_DPCD_STATUS_LANE_2_SL_DONE_MASK 0x04 -#define XDPTX_DPCD_STATUS_LANE_3_CR_DONE_MASK 0x10 -#define XDPTX_DPCD_STATUS_LANE_3_CE_DONE_MASK 0x20 -#define XDPTX_DPCD_STATUS_LANE_3_SL_DONE_MASK 0x40 -/* 0x00204: LANE_ALIGN_STATUS_UPDATED */ -#define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK \ - 0x01 -#define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK \ - 0x40 -#define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK \ - 0x80 -/* 0x00205: SINK_STATUS */ -#define XDPTX_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK 0x01 -#define XDPTX_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK 0x02 - -/* 0x00206, 0x00207: ADJ_REQ_LANE_[0,2]_[1,3] */ -#define XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03 -#define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C -#define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2 -#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30 -#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4 -#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0 -#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6 -/* 0x0020C: ADJ_REQ_PC2 */ -#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_0_MASK 0x03 -#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_MASK 0x0C -#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT 2 -#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_MASK 0x30 -#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT 4 -#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_MASK 0xC0 -#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT 6 -/* @} */ - -/******************************************************************************/ - -/******************************************************************************/ -/** - * Address mapping for the Extended Display Identification Data (EDID) of the - * downstream device. - * -*******************************************************************************/ -/** @name Extended Display Identification Data: Field addresses and sizes. - * @{ - */ -#define XDPTX_SEGPTR_ADDR 0x30 -#define XDPTX_EDID_ADDR 0x50 -#define XDPTX_EDID_BLOCK_SIZE 128 -#define XDPTX_EDID_DTD_DD(Num) (0x36 + (18 * Num)) -#define XDPTX_EDID_PTM XDPTX_EDID_DTD_DD(0) -#define XDPTX_EDID_EXT_BLOCK_COUNT 0x7E -/* @} */ - -/** @name Extended Display Identification Data: Register offsets for the - * Detailed Timing Descriptor (DTD). - * @{ - */ -#define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB 0x00 -#define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB 0x01 -#define XDPTX_EDID_DTD_HRES_LSB 0x02 -#define XDPTX_EDID_DTD_HBLANK_LSB 0x03 -#define XDPTX_EDID_DTD_HRES_HBLANK_U4 0x04 -#define XDPTX_EDID_DTD_VRES_LSB 0x05 -#define XDPTX_EDID_DTD_VBLANK_LSB 0x06 -#define XDPTX_EDID_DTD_VRES_VBLANK_U4 0x07 -#define XDPTX_EDID_DTD_HFPORCH_LSB 0x08 -#define XDPTX_EDID_DTD_HSPW_LSB 0x09 -#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4 0x0A -#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2 0x0B -#define XDPTX_EDID_DTD_HIMGSIZE_MM_LSB 0x0C -#define XDPTX_EDID_DTD_VIMGSIZE_MM_LSB 0x0D -#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4 0x0E -#define XDPTX_EDID_DTD_HBORDER 0x0F -#define XDPTX_EDID_DTD_VBORDER 0x10 -#define XDPTX_EDID_DTD_SIGNAL 0x11 - -/** @name Extended Display Identification Data: Masks, shifts, and register - * values. - * @{ - */ -#define XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK 0x0F -#define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK 0xF0 -#define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT 4 -#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK 0x0F -#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK 0xF0 -#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT 4 -#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK 0xC0 -#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK 0x30 -#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK 0x0C -#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK 0x03 -#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT 6 -#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT 4 -#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT 2 -#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK 0x0F -#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK 0xF0 -#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT 4 -#define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_MASK 0x02 -#define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_MASK 0x04 -#define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_SHIFT 1 -#define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_SHIFT 2 -/* @} */ - -/** @name Extended Display Identification Data: Register offsets for the - * DisplayID extension block. - * @{ - */ -#define XDPTX_EDID_EXT_BLOCK_TAG 0x00 -#define XDPTX_DISPID_VER_REV 0x00 -#define XDPTX_DISPID_SIZE 0x01 -#define XDPTX_DISPID_TYPE 0x02 -#define XDPTX_DISPID_EXT_COUNT 0x03 -#define XDPTX_DISPID_PAYLOAD_START 0x04 -#define XDPTX_DISPID_DB_SEC_TAG 0x00 -#define XDPTX_DISPID_DB_SEC_REV 0x01 -#define XDPTX_DISPID_DB_SEC_SIZE 0x02 -/* @} */ - -/** @name Extended Display Identification Data: Masks, shifts, and register - * values for the DisplayID extension block. - * @{ - */ -#define XDPTX_EDID_EXT_BLOCK_TAG_DISPID 0x70 -#define XDPTX_DISPID_TDT_TAG 0x12 -/* @} */ - -/** @name Extended Display Identification Data: Register offsets for the - * Tiled Display Topology (TDT) section data block. - * @{ - */ -#define XDPTX_DISPID_TDT_TOP0 0x04 -#define XDPTX_DISPID_TDT_TOP1 0x05 -#define XDPTX_DISPID_TDT_TOP2 0x06 -#define XDPTX_DISPID_TDT_HSIZE0 0x07 -#define XDPTX_DISPID_TDT_HSIZE1 0x08 -#define XDPTX_DISPID_TDT_VSIZE0 0x09 -#define XDPTX_DISPID_TDT_VSIZE1 0x0A -#define XDPTX_DISPID_TDT_VENID0 0x10 -#define XDPTX_DISPID_TDT_VENID1 0x11 -#define XDPTX_DISPID_TDT_VENID2 0x12 -#define XDPTX_DISPID_TDT_PCODE0 0x13 -#define XDPTX_DISPID_TDT_PCODE1 0x14 -#define XDPTX_DISPID_TDT_SN0 0x15 -#define XDPTX_DISPID_TDT_SN1 0x16 -#define XDPTX_DISPID_TDT_SN2 0x17 -#define XDPTX_DISPID_TDT_SN3 0x18 -/* @} */ - -/** @name Extended Display Identification Data: Masks, shifts, and register - * values for the Tiled Display Topology (TDT) section data block. - * @{ - */ -#define XDPTX_DISPID_TDT_TOP0_HTOT_L_SHIFT 4 -#define XDPTX_DISPID_TDT_TOP0_HTOT_L_MASK (0xF << 4) -#define XDPTX_DISPID_TDT_TOP0_VTOT_L_MASK 0xF -#define XDPTX_DISPID_TDT_TOP1_HLOC_L_SHIFT 4 -#define XDPTX_DISPID_TDT_TOP1_HLOC_L_MASK (0xF << 4) -#define XDPTX_DISPID_TDT_TOP1_VLOC_L_MASK 0xF -#define XDPTX_DISPID_TDT_TOP2_HTOT_H_SHIFT 6 -#define XDPTX_DISPID_TDT_TOP2_HTOT_H_MASK (0x3 << 6) -#define XDPTX_DISPID_TDT_TOP2_VTOT_H_SHIFT 4 -#define XDPTX_DISPID_TDT_TOP2_VTOT_H_MASK (0x3 << 4) -#define XDPTX_DISPID_TDT_TOP2_HLOC_H_SHIFT 2 -#define XDPTX_DISPID_TDT_TOP2_HLOC_H_MASK (0x3 << 2) -#define XDPTX_DISPID_TDT_TOP2_VLOC_H_MASK 0x3 -/* @} */ - -/******************************************************************************/ -/** - * Multi-stream transport (MST) definitions. - * -*******************************************************************************/ -/** @name Stream identification. - * @{ - */ -#define XDPTX_STREAM_ID1 1 -#define XDPTX_STREAM_ID2 2 -#define XDPTX_STREAM_ID3 3 -#define XDPTX_STREAM_ID4 4 -/* @} */ - -/** @name Sideband message codes when the driver is in MST mode. - * @{ - */ -#define XDPTX_SBMSG_LINK_ADDRESS 0x01 -#define XDPTX_SBMSG_ENUM_PATH_RESOURCES 0x10 -#define XDPTX_SBMSG_ALLOCATE_PAYLOAD 0x11 -#define XDPTX_SBMSG_CLEAR_PAYLOAD_ID_TABLE 0x14 -#define XDPTX_SBMSG_REMOTE_DPCD_READ 0x20 -#define XDPTX_SBMSG_REMOTE_DPCD_WRITE 0x21 -#define XDPTX_SBMSG_REMOTE_I2C_READ 0x22 -#define XDPTX_SBMSG_REMOTE_I2C_WRITE 0x23 -/* @} */ - -/******************* Macros (Inline Functions) Definitions ********************/ - -/** @name Register access macro definitions. - * @{ - */ -#define XDptx_In32 Xil_In32 -#define XDptx_Out32 Xil_Out32 -/* @} */ - -/******************************************************************************/ -/** - * This is a low-level function that reads from the specified register. - * - * @param BaseAddress is the base address of the device. - * @param RegOffset is the register offset to be read from. - * - * @return The 32-bit value of the specified register. - * - * @note C-style signature: - * u32 XDptx_ReadReg(u32 BaseAddress, u32 RegOffset) - * -*******************************************************************************/ -#define XDptx_ReadReg(BaseAddress, RegOffset) \ - XDptx_In32((BaseAddress) + (RegOffset)) - -/******************************************************************************/ -/** - * This is a low-level function that writes to the specified register. - * - * @param BaseAddress is the base address of the device. - * @param RegOffset is the register offset to write to. - * @param Data is the 32-bit data to write to the specified register. - * - * @return None. - * - * @note C-style signature: - * void XDptx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) - * -*******************************************************************************/ -#define XDptx_WriteReg(BaseAddress, RegOffset, Data) \ - XDptx_Out32((BaseAddress) + (RegOffset), (Data)) - - -/******************************************************************************/ -/** - * Check if an Extended Display Identification Data (EDID) extension block is of - * type DisplayID. - * - * @param Ext is a pointer to the EDID extension block under comparison. - * - * @return - * - 1 if the extension block is of type DisplayID. - * - Otherwise. - * - * @note C-style signature: - * u8 XDptx_IsEdidExtBlockDispId(u8 *Ext) - * -*******************************************************************************/ -#define XDptx_IsEdidExtBlockDispId(Ext) \ - (Ext[XDPTX_EDID_EXT_BLOCK_TAG] == XDPTX_EDID_EXT_BLOCK_TAG_DISPID) - -/******************************************************************************/ -/** - * Given a Tiled Display Topology (TDT) data block, retrieve the total number of - * horizontal tiles in the tiled display. The TDT block is part of an Extended - * Display Identification Data (EDID) extension block of type DisplayID. - * - * @param Tdt is a pointer to the TDT data block. - * - * @return The total number of horizontal tiles in the tiled display. - * - * @note C-style signature: - * u8 XDptx_GetDispIdTdtHTotal(u8 *Tdt) - * -*******************************************************************************/ -#define XDptx_GetDispIdTdtHTotal(Tdt) \ - (((((Tdt[XDPTX_DISPID_TDT_TOP2] & XDPTX_DISPID_TDT_TOP2_HTOT_H_MASK) \ - >> XDPTX_DISPID_TDT_TOP2_HTOT_H_SHIFT) << 4) | \ - ((Tdt[XDPTX_DISPID_TDT_TOP0] & XDPTX_DISPID_TDT_TOP0_HTOT_L_MASK) >> \ - XDPTX_DISPID_TDT_TOP0_HTOT_L_SHIFT)) + 1) - -/******************************************************************************/ -/** - * Given a Tiled Display Topology (TDT) data block, retrieve the total number of - * vertical tiles in the tiled display. The TDT block is part of an Extended - * Display Identification Data (EDID) extension block of type DisplayID. - * - * @param Tdt is a pointer to the TDT data block. - * - * @return The total number of vertical tiles in the tiled display. - * - * @note C-style signature: - * u8 XDptx_GetDispIdTdtVTotal(u8 *Tdt) - * -*******************************************************************************/ -#define XDptx_GetDispIdTdtVTotal(Tdt) \ - (((((Tdt[XDPTX_DISPID_TDT_TOP2] & XDPTX_DISPID_TDT_TOP2_VTOT_H_MASK) \ - >> XDPTX_DISPID_TDT_TOP2_VTOT_H_SHIFT) << 4) | \ - (Tdt[XDPTX_DISPID_TDT_TOP0] & XDPTX_DISPID_TDT_TOP0_VTOT_L_MASK)) + 1) - -/******************************************************************************/ -/** - * Given a Tiled Display Topology (TDT) data block, retrieve the horizontal tile - * location in the tiled display. The TDT block is part of an Extended Display - * Identification Data (EDID) extension block of type DisplayID. - * - * @param Tdt is a pointer to the TDT data block. - * - * @return The horizontal tile location in the tiled display represented by - * the specified TDT. - * - * @note C-style signature: - * u8 XDptx_GetDispIdTdtHLoc(u8 *Tdt) - * -*******************************************************************************/ -#define XDptx_GetDispIdTdtHLoc(Tdt) \ - ((((Tdt[XDPTX_DISPID_TDT_TOP2] & XDPTX_DISPID_TDT_TOP2_HLOC_H_MASK) \ - >> XDPTX_DISPID_TDT_TOP2_HLOC_H_SHIFT) << 4) | \ - ((Tdt[XDPTX_DISPID_TDT_TOP1] & XDPTX_DISPID_TDT_TOP1_HLOC_L_MASK) >> \ - XDPTX_DISPID_TDT_TOP1_HLOC_L_SHIFT)) - -/******************************************************************************/ -/** - * Given a Tiled Display Topology (TDT) data block, retrieve the vertical tile - * location in the tiled display. The TDT block is part of an Extended Display - * Identification Data (EDID) extension block of type DisplayID. - * - * @param Tdt is a pointer to the TDT data block. - * - * @return The vertical tile location in the tiled display represented by - * the specified TDT. - * - * @note C-style signature: - * u8 XDptx_GetDispIdTdtVLoc(u8 *Tdt) - * -*******************************************************************************/ -#define XDptx_GetDispIdTdtVLoc(Tdt) \ - (((Tdt[XDPTX_DISPID_TDT_TOP2] & XDPTX_DISPID_TDT_TOP2_VLOC_H_MASK) << \ - 4) | (Tdt[XDPTX_DISPID_TDT_TOP1] & XDPTX_DISPID_TDT_TOP1_VLOC_L_MASK)) - -/******************************************************************************/ -/** - * Given a Tiled Display Topology (TDT) data block, retrieve the total number of - * tiles in the tiled display. The TDT block is part of an Extended Display - * Identification Data (EDID) extension block of type DisplayID. - * - * @param Tdt is a pointer to the TDT data block. - * - * @return The total number of tiles in the tiled display. - * - * @note C-style signature: - * u8 XDptx_GetDispIdTdtNumTiles(u8 *Tdt) - * -*******************************************************************************/ -#define XDptx_GetDispIdTdtNumTiles(Tdt) \ - (XDptx_GetDispIdTdtHTotal(Tdt) * XDptx_GetDispIdTdtVTotal(Tdt)) - -/******************************************************************************/ -/** - * Given a Tiled Display Topology (TDT) data block, calculate the tiling order - * of the associated tile. The TDT block is part of an Extended Display - * Identification Data (EDID) extension block of type DisplayID. - * The tiling order starts at 0 for x,y coordinate 0,0 and increments as the - * horizontal location increases. Once the last horizontal tile has been - * reached, the next tile in the order is 0,y+1. - * - * @param Tdt is a pointer to the TDT data block. - * - * @return The total number of horizontal tiles in the tiled display. - * - * @note C-style signature: - * u8 XDptx_GetDispIdTdtTileOrder(u8 *Tdt) - * -*******************************************************************************/ -#define XDptx_GetDispIdTdtTileOrder(Tdt) \ - ((XDptx_GetDispIdTdtVLoc(Tdt) * XDptx_GetDispIdTdtHTotal(Tdt)) + \ - XDptx_GetDispIdTdtHLoc(Tdt)) - -#endif /* XDPTX_HW_H_ */ diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdptx_intr.c b/XilinxProcessorIPLib/drivers/dp/src/xdptx_intr.c deleted file mode 100644 index b5efec94..00000000 --- a/XilinxProcessorIPLib/drivers/dp/src/xdptx_intr.c +++ /dev/null @@ -1,180 +0,0 @@ -/******************************************************************************* - * - * Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * Use of the Software is limited solely to applications: - * (a) running on a Xilinx device, or - * (b) that interact with a Xilinx device through a bus or interconnect. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Except as contained in this notice, the name of the Xilinx shall not be used - * in advertising or otherwise to promote the sale, use or other dealings in - * this Software without prior written authorization from Xilinx. - * -*******************************************************************************/ -/******************************************************************************/ -/** - * - * @file xdptx_intr.c - * - * This file contains functions related to XDptx interrupt handling. - * - * @note None. - * - *
- * MODIFICATION HISTORY:
- *
- * Ver   Who  Date     Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0   als  05/17/14 Initial release.
- * 3.0   als  12/16/14 Increased debounce duration for HPD to 0.500ms.
- *                     Added masking of interrupts during servicing.
- * 
- * -*******************************************************************************/ - -/******************************* Include Files ********************************/ - -#include "xdptx.h" - -/**************************** Function Definitions ****************************/ - -/******************************************************************************/ -/** - * This function is the interrupt handler for the XDptx driver. - * - * When an interrupt happens, it first detects what kind of interrupt happened, - * then decides which callback function to invoke. - * - * @param InstancePtr is a pointer to the XDptx instance. - * - * @return None. - * - * @note None. - * -*******************************************************************************/ -void XDptx_HpdInterruptHandler(XDptx *InstancePtr) -{ - u32 IntrStatus; - u8 HpdEventDetected; - u8 HpdPulseDetected; - u32 HpdDuration; - u32 IntrMask; - - /* Verify arguments. */ - Xil_AssertVoid(InstancePtr != NULL); - - /* Determine what kind of interrupt occurred. - * Note: XDPTX_INTERRUPT_STATUS is an RC (read-clear) register. */ - IntrStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_INTERRUPT_STATUS); - IntrStatus &= ~XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_INTERRUPT_MASK); - IntrMask = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_INTERRUPT_MASK); - - HpdEventDetected = IntrStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK; - HpdPulseDetected = IntrStatus & - XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK; - - if (HpdEventDetected) { - /* Mask interrupts while event handling is taking place. API - * will error out in case of a disconnection event anyway. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, - XDPTX_INTERRUPT_MASK, IntrMask | - XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK); - - InstancePtr->HpdEventHandler(InstancePtr->HpdEventCallbackRef); - } - else if (HpdPulseDetected && XDptx_IsConnected(InstancePtr)) { - /* Mask interrupts while event handling is taking place. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, - XDPTX_INTERRUPT_MASK, IntrMask | - XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK); - - /* The source device must debounce the incoming HPD signal by - * sampling the value at an interval greater than 0.500 ms. An - * HPD pulse should be of width 0.5 ms - 1.0 ms. */ - HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - XDPTX_HPD_DURATION); - if (HpdDuration >= 500) { - InstancePtr->HpdPulseHandler( - InstancePtr->HpdPulseCallbackRef); - } - } - - /* Unmask previously masked interrupts once handling is done. */ - XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_INTERRUPT_MASK, - IntrMask); -} - -/******************************************************************************/ -/** - * This function installs a callback function for when a hot-plug-detect event - * interrupt occurs. - * - * @param InstancePtr is a pointer to the XDptx instance. - * @param CallbackFunc is the address to the callback function. - * @param CallbackRef is the user data item that will be passed to the - * callback function when it is invoked. - * - * @return None. - * - * @note None. - * -*******************************************************************************/ -void XDptx_SetHpdEventHandler(XDptx *InstancePtr, - XDptx_HpdEventHandler CallbackFunc, void *CallbackRef) -{ - /* Verify arguments. */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(CallbackFunc != NULL); - Xil_AssertVoid(CallbackRef != NULL); - - InstancePtr->HpdEventHandler = CallbackFunc; - InstancePtr->HpdEventCallbackRef = CallbackRef; -} - -/******************************************************************************/ -/** - * This function installs a callback function for when a hot-plug-detect pulse - * interrupt occurs. - * - * @param InstancePtr is a pointer to the XDptx instance. - * @param CallbackFunc is the address to the callback function. - * @param CallbackRef is the user data item that will be passed to the - * callback function when it is invoked. - * - * @return None. - * - * @note None. - * -*******************************************************************************/ -void XDptx_SetHpdPulseHandler(XDptx *InstancePtr, - XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef) -{ - /* Verify arguments. */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(CallbackFunc != NULL); - Xil_AssertVoid(CallbackRef != NULL); - - InstancePtr->HpdPulseHandler = CallbackFunc; - InstancePtr->HpdPulseCallbackRef = CallbackRef; -} diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdptx_selftest.c b/XilinxProcessorIPLib/drivers/dp/src/xdptx_selftest.c deleted file mode 100644 index 0c56a1b5..00000000 --- a/XilinxProcessorIPLib/drivers/dp/src/xdptx_selftest.c +++ /dev/null @@ -1,213 +0,0 @@ -/******************************************************************************* - * - * Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * Use of the Software is limited solely to applications: - * (a) running on a Xilinx device, or - * (b) that interact with a Xilinx device through a bus or interconnect. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Except as contained in this notice, the name of the Xilinx shall not be used - * in advertising or otherwise to promote the sale, use or other dealings in - * this Software without prior written authorization from Xilinx. - * -*******************************************************************************/ -/******************************************************************************/ -/** - * - * @file xdptx_selftest.c - * - * This file contains a diagnostic self-test function for the XDptx driver. It - * will check many of the DisplayPort TX's register values against the default - * reset values as a sanity-check that the core is ready to be used. - * - * @note None. - * - *
- * MODIFICATION HISTORY:
- *
- * Ver   Who  Date     Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0   als  05/17/14 Initial release.
- * 3.0   als  12/16/14 Stream naming now starts at 1 to follow IP.
- * 
- * -*******************************************************************************/ - -/******************************* Include Files ********************************/ - -#include "xdptx.h" -#include "xstatus.h" - -/**************************** Variable Definitions ****************************/ - -/** - * This table contains the default values for the DisplayPort TX core's general - * usage registers. - */ -u32 ResetValues[53][2] = -{ - {XDPTX_LINK_BW_SET, 0}, - {XDPTX_LANE_COUNT_SET, 0}, - {XDPTX_ENHANCED_FRAME_EN, 0}, - {XDPTX_TRAINING_PATTERN_SET, 0}, - {XDPTX_LINK_QUAL_PATTERN_SET, 0}, - {XDPTX_SCRAMBLING_DISABLE, 0}, - {XDPTX_DOWNSPREAD_CTRL, 0}, - {XDPTX_SOFT_RESET, 0}, - {XDPTX_ENABLE, 0}, - {XDPTX_ENABLE_MAIN_STREAM, 0}, - {XDPTX_ENABLE_SEC_STREAM, 0}, - {XDPTX_FORCE_SCRAMBLER_RESET, 0}, - {XDPTX_TX_MST_CONFIG, 0}, - {XDPTX_AUX_CMD, 0}, - {XDPTX_AUX_WRITE_FIFO, 0}, - {XDPTX_AUX_ADDRESS, 0}, - {XDPTX_AUX_CLK_DIVIDER, 0}, - {XDPTX_TX_USER_FIFO_OVERFLOW, 0}, - {XDPTX_AUX_REPLY_DATA, 0}, - {XDPTX_AUX_REPLY_CODE, 0}, - {XDPTX_AUX_REPLY_COUNT, 0}, - {XDPTX_INTERRUPT_MASK, 0x3F}, - {XDPTX_REPLY_DATA_COUNT, 0}, - {XDPTX_REPLY_STATUS, 0x10}, - {XDPTX_STREAM1, 0}, - {XDPTX_STREAM2, 0}, - {XDPTX_STREAM3, 0}, - {XDPTX_STREAM4, 0}, - {XDPTX_PHY_CONFIG, 0x03}, - {XDPTX_PHY_VOLTAGE_DIFF_LANE_0, 0}, - {XDPTX_PHY_VOLTAGE_DIFF_LANE_1, 0}, - {XDPTX_PHY_VOLTAGE_DIFF_LANE_2, 0}, - {XDPTX_PHY_VOLTAGE_DIFF_LANE_3, 0}, - {XDPTX_PHY_TRANSMIT_PRBS7, 0}, - {XDPTX_PHY_CLOCK_SELECT, 0}, - {XDPTX_TX_PHY_POWER_DOWN, 0}, - {XDPTX_PHY_PRECURSOR_LANE_0, 0}, - {XDPTX_PHY_PRECURSOR_LANE_1, 0}, - {XDPTX_PHY_PRECURSOR_LANE_2, 0}, - {XDPTX_PHY_PRECURSOR_LANE_3, 0}, - {XDPTX_PHY_POSTCURSOR_LANE_0, 0}, - {XDPTX_PHY_POSTCURSOR_LANE_1, 0}, - {XDPTX_PHY_POSTCURSOR_LANE_2, 0}, - {XDPTX_PHY_POSTCURSOR_LANE_3, 0}, - {XDPTX_GT_DRP_COMMAND, 0}, - {XDPTX_GT_DRP_READ_DATA, 0}, - {XDPTX_GT_DRP_CHANNEL_STATUS, 0}, - {XDPTX_TX_AUDIO_CONTROL, 0}, - {XDPTX_TX_AUDIO_CHANNELS, 0}, - {XDPTX_TX_AUDIO_INFO_DATA(1), 0}, - {XDPTX_TX_AUDIO_MAUD, 0}, - {XDPTX_TX_AUDIO_NAUD, 0}, - {XDPTX_TX_AUDIO_EXT_DATA(1), 0} -}; - -/** - * This table contains the default values for the DisplayPort TX core's main - * stream attribute (MSA) registers. - */ -u32 ResetValuesMsa[20][2] = -{ - {XDPTX_MAIN_STREAM_HTOTAL, 0}, - {XDPTX_MAIN_STREAM_VTOTAL, 0}, - {XDPTX_MAIN_STREAM_POLARITY, 0}, - {XDPTX_MAIN_STREAM_HSWIDTH, 0}, - {XDPTX_MAIN_STREAM_VSWIDTH, 0}, - {XDPTX_MAIN_STREAM_HRES, 0}, - {XDPTX_MAIN_STREAM_VRES, 0}, - {XDPTX_MAIN_STREAM_HSTART, 0}, - {XDPTX_MAIN_STREAM_VSTART, 0}, - {XDPTX_MAIN_STREAM_MISC0, 0}, - {XDPTX_MAIN_STREAM_MISC1, 0}, - {XDPTX_M_VID, 0}, - {XDPTX_TU_SIZE, 0}, - {XDPTX_N_VID, 0}, - {XDPTX_USER_PIXEL_WIDTH, 0}, - {XDPTX_USER_DATA_COUNT_PER_LANE, 0}, - {XDPTX_MAIN_STREAM_INTERLACED, 0}, - {XDPTX_MIN_BYTES_PER_TU, 0}, - {XDPTX_FRAC_BYTES_PER_TU, 0}, - {XDPTX_INIT_WAIT, 32} -}; - -/**************************** Function Definitions ****************************/ - -/******************************************************************************/ -/** - * This function runs a self-test on the XDptx driver/device. The sanity test - * checks whether or not all tested registers hold their default reset values. - * - * @param InstancePtr is a pointer to the XDptx instance. - * - * @return - * - XST_SUCCESS if the self-test passed - all tested registers - * hold their default reset values. - * - XST_FAILURE otherwise. - * - * @note None. - * -*******************************************************************************/ -u32 XDptx_SelfTest(XDptx *InstancePtr) -{ - u8 Index; - u8 StreamIndex; - u32 StreamOffset; - u32 Val; - - /* Compare general usage registers with their default values. */ - for (Index = 0; Index < 53; Index++) { - Val = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - ResetValues[Index][0]); - /* Fail if register does not hold default value. */ - if (Val != ResetValues[Index][1]) { - return XST_FAILURE; - } - } - - /* Compare main stream attribute (MSA) registers for all 4 streams with - * their default values. */ - for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) { - /* Determine the MSA register offset for each stream. */ - if (StreamIndex == 0) { - StreamOffset = 0; - } - else if (StreamIndex == 1) { - StreamOffset = XDPTX_STREAM2_MSA_START_OFFSET; - } - else if (StreamIndex == 2) { - StreamOffset = XDPTX_STREAM3_MSA_START_OFFSET; - } - else if (StreamIndex == 3) { - StreamOffset = XDPTX_STREAM4_MSA_START_OFFSET; - } - - for (Index = 0; Index < 20; Index++) { - Val = XDptx_ReadReg(InstancePtr->Config.BaseAddr, - StreamOffset + ResetValuesMsa[Index][0]); - /* Fail if register does not hold default value. */ - if (Val != ResetValuesMsa[Index][1]) { - return XST_FAILURE; - } - } - } - - /* All tested registers hold their default reset values. */ - return XST_SUCCESS; -}