From 1c32d18912447042bc9cae64f288b9d87c2c2696 Mon Sep 17 00:00:00 2001
From: Kedareswara rao Appana <appana.durga.rao@xilinx.com>
Date: Tue, 5 Aug 2014 15:27:39 +0530
Subject: [PATCH] trafgen: Add new version 3.2 and deprecate 3.1

Add new driver trafgen_v3_2 and deprecate trafgen_v3_1.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
---
 .../drivers/trafgen/data/trafgen.mdd          |   43 +
 .../drivers/trafgen/data/trafgen.tcl          |  271 ++++
 .../drivers/trafgen/examples/index.html       |   20 +
 .../examples/xtrafgen_interrupt_example.c     |  667 +++++++++
 .../xtrafgen_master_streaming_example.c       |  319 +++++
 .../examples/xtrafgen_polling_example.c       |  429 ++++++
 .../examples/xtrafgen_static_mode_example.c   |  278 ++++
 .../drivers/trafgen/src/Makefile              |   28 +
 .../drivers/trafgen/src/xtrafgen.c            |  688 ++++++++++
 .../drivers/trafgen/src/xtrafgen.h            | 1199 +++++++++++++++++
 .../drivers/trafgen/src/xtrafgen_g.c          |   70 +
 .../drivers/trafgen/src/xtrafgen_hw.h         |  520 +++++++
 .../drivers/trafgen/src/xtrafgen_sinit.c      |   86 ++
 13 files changed, 4618 insertions(+)
 create mode 100755 XilinxProcessorIPLib/drivers/trafgen/data/trafgen.mdd
 create mode 100755 XilinxProcessorIPLib/drivers/trafgen/data/trafgen.tcl
 create mode 100755 XilinxProcessorIPLib/drivers/trafgen/examples/index.html
 create mode 100755 XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_interrupt_example.c
 create mode 100755 XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_master_streaming_example.c
 create mode 100755 XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_polling_example.c
 create mode 100755 XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_static_mode_example.c
 create mode 100755 XilinxProcessorIPLib/drivers/trafgen/src/Makefile
 create mode 100755 XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.c
 create mode 100755 XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.h
 create mode 100755 XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_g.c
 create mode 100755 XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_hw.h
 create mode 100755 XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_sinit.c

diff --git a/XilinxProcessorIPLib/drivers/trafgen/data/trafgen.mdd b/XilinxProcessorIPLib/drivers/trafgen/data/trafgen.mdd
new file mode 100755
index 00000000..29b8bb08
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/trafgen/data/trafgen.mdd
@@ -0,0 +1,43 @@
+###############################################################################
+#
+# Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+
+OPTION psf_version = 2.1;
+
+BEGIN driver trafgen
+
+  OPTION supported_peripherals = (axi_traffic_gen_v[2-9]_[0-9][0-9]_[a-z] axi_traffic_gen_v[2-9]_[0-9]);
+  OPTION driver_state = ACTIVE;
+  OPTION copyfiles = all;
+    OPTION VERSION = 3.0;
+  OPTION NAME = trafgen;   
+
+END driver
diff --git a/XilinxProcessorIPLib/drivers/trafgen/data/trafgen.tcl b/XilinxProcessorIPLib/drivers/trafgen/data/trafgen.tcl
new file mode 100755
index 00000000..4e23a62c
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/trafgen/data/trafgen.tcl
@@ -0,0 +1,271 @@
+###############################################################################
+#
+# Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+##############################################################################
+#
+#  @file xtrafgen_v2_1_0.tcl
+#
+#
+# <pre>
+# MODIFICATION HISTORY:
+#
+# Ver   Who  Date     Changes
+# ----- ---- -------- -------------------------------------------------------
+# 1.00a srt  01/20/13 First release 
+# 1.01a adk  03/09/13 Updated tcl to differentiate Different Modes in AXI 
+#		      Traffic Genrator.
+# 3.0   adk  12/10/13 Updated as per the New Tcl API's
+#
+# </pre>
+#
+##############################################################################
+
+
+#uses "xillib.tcl"
+
+set periph_config_params_atg 0
+set periph_ninstances_atg    0
+set atg_mode_value	     0
+set atg_mode_value_l2        0
+set axi_mode_value           0
+set baseaddr_value           0
+set highaddr_value           0
+
+proc init_periph_config_struct_atg { deviceid } {
+    global periph_config_params_atg
+    set periph_config_params_atg($deviceid) [list]
+}
+
+proc add_field_to_periph_config_struct_atg { deviceid fieldval } {
+    global periph_config_params_atg
+    lappend periph_config_params_atg($deviceid) $fieldval
+}
+
+proc get_periph_config_struct_fields_atg { deviceid } {
+    global periph_config_params_atg
+    return $periph_config_params_atg($deviceid)
+}
+
+proc xdefine_trafgen_include_file {drv_handle file_name drv_string} {
+	global periph_ninstances
+	
+	    # Open include file
+	    set file_handle [::hsm::utils::open_include_file $file_name]
+	
+	    # Get all peripherals connected to this driver
+	    set periphs [::hsm::utils::get_common_driver_ips $drv_handle]
+	
+	    # Handle NUM_INSTANCES
+	    set periph_ninstances 0
+	    puts $file_handle "/* Definitions for driver [string toupper [get_property NAME $drv_handle]] */"
+	    foreach periph $periphs {
+	    	init_periph_config_struct_atg $periph_ninstances
+	    	incr periph_ninstances 1
+	    }
+	    puts $file_handle "\#define [::hsm::utils::get_driver_param_name $drv_string NUM_INSTANCES] $periph_ninstances"
+	
+	
+	    # Now print all useful parameters for all peripherals
+	    set device_id 0
+	    foreach periph $periphs {
+        	puts $file_handle ""
+        	
+        	xdefine_trafgen_params_instance $file_handle $periph $device_id
+        	
+        	xdefine_trafgen_params_canonical $file_handle $periph $device_id
+        	incr device_id
+            	puts $file_handle "\n"
+           }
+           puts $file_handle "\n/******************************************************************/\n"
+    	   close $file_handle
+}
+
+proc xdfeine_trafgen_params_constants { periph } {
+    global atg_mode_value	     
+    global atg_mode_value_l2        
+    global axi_mode_value           
+    global baseaddr_value           
+    global highaddr_value       
+ 
+    set atg_mode_name [::hsm::utils::get_param_value $periph C_ATG_MODE]
+    set axi4_name [string match -nocase $atg_mode_name "AXI4"]
+    set axi4_lite_name [string match -nocase $atg_mode_name "AXI4-Lite"]
+    set axi4_Stream_name [string match -nocase $atg_mode_name "AXI4-Stream"]
+     if {$axi4_name == 1} {
+	set atg_mode_value 1
+    }
+    if {$axi4_lite_name == 1} {
+	set atg_mode_value 2
+    }
+    if {$axi4_Stream_name == 1} {
+	set atg_mode_value 3
+    }
+    
+    if {[llength $atg_mode_name] == 0} {
+         set atg_mode_value 0
+    }
+    
+    set atg_mode_l2_name [::hsm::utils::get_param_value $periph C_ATG_MODE_L2]
+    set adv_mode_name [string match -nocase $atg_mode_l2_name "Advanced"]
+    set basic_mode_name [string match -nocase $atg_mode_l2_name "Basic"]
+    set static_mode_name [string match -nocase $atg_mode_l2_name "Static"]
+  if {$adv_mode_name == 1} {
+	set atg_mode_value_l2 1
+    }
+    if {$basic_mode_name == 1} {
+	set atg_mode_value_l2 2
+    }
+    if {$static_mode_name == 1} {
+	set atg_mode_value_l2 3
+    }
+    if {[llength $atg_mode_l2_name] == 0} {
+         set atg_mode_value_l2 0
+    }
+    set axi_mode_name [::hsm::utils::get_param_value $periph C_AXIS_MODE]
+    set master_name [string match -nocase $axi_mode_name "Master Only"]
+    set slave_name [string match -nocase $axi_mode_name "Slave Only"]
+    set master_loop_name [string match -nocase $axi_mode_name "Master Loop back"]
+    set slave_loop_name [string match -nocase $axi_mode_name "Slave Loop back"]
+   if {$master_name == 1} {
+	set axi_mode_value 1
+    }
+    if {$slave_name == 1} {
+	set axi_mode_value 2
+    }
+    if {$master_loop_name == 1} {
+	set axi_mode_value 3
+    }
+    if {$slave_loop_name == 1} {
+	set axi_mode_value 4
+    }
+    if {[llength $axi_mode_name] == 0} {
+         set axi_mode_value 0
+    }
+
+    set baseaddr_value [::hsm::utils::get_param_value $periph C_BASEADDR]
+    if {[llength $baseaddr_value] == 0} {
+             set baseaddr_value 0
+    }
+    set highaddr_value [::hsm::utils::get_param_value $periph C_HIGHADDR]
+    if {[llength $highaddr_value] == 0} {
+             set highaddr_value 0
+    }
+}
+
+proc xdefine_trafgen_params_instance {file_handle periph device_id} { 
+    xdfeine_trafgen_params_constants   $periph
+    global atg_mode_value
+    global atg_mode_value_l2
+    global axi_mode_value
+    puts $file_handle "/* Definitions for peripheral [string toupper [get_property NAME $periph]] */"
+    
+    puts $file_handle "\#define [::hsm::utils::get_ip_param_name $periph "DEVICE_ID"] $device_id"
+    puts $file_handle "\#define [::hsm::utils::get_ip_param_name $periph "BASEADDR"] [::hsm::utils::get_param_value $periph C_BASEADDR]"
+    puts $file_handle "\#define [::hsm::utils::get_ip_param_name $periph "HIGHADDR"] [::hsm::utils::get_param_value $periph C_HIGHADDR]"
+    
+    puts $file_handle "\#define [::hsm::utils::get_ip_param_name $periph "C_ATG_MODE"] $atg_mode_value"
+    puts $file_handle "\#define [::hsm::utils::get_ip_param_name $periph "C_ATG_MODE_L2"] $atg_mode_value_l2"
+    puts $file_handle "\#define [::hsm::utils::get_ip_param_name $periph "C_AXIS_MODE"] $axi_mode_value"
+}
+
+proc xdefine_trafgen_params_canonical {file_handle periph device_id} {
+    xdfeine_trafgen_params_constants  $periph 
+    global atg_mode_value	     
+    global atg_mode_value_l2        
+    global axi_mode_value           
+    global baseaddr_value           
+    global highaddr_value
+    puts $file_handle "\n/* Canonical definitions for peripheral [string toupper [get_property NAME $periph]] */"
+    
+    set canonical_tag [string toupper [format "XPAR_XTRAFGEN_%d" $device_id]]
+    
+     # Handle device ID
+    set canonical_name  [format "%s_DEVICE_ID" $canonical_tag]
+    puts $file_handle "\#define $canonical_name $device_id"
+    add_field_to_periph_config_struct_atg $device_id $canonical_name
+    
+    set canonical_name  [format "%s_BASEADDR" $canonical_tag]
+    puts $file_handle "\#define $canonical_name $baseaddr_value"
+    add_field_to_periph_config_struct_atg $device_id $canonical_name
+     
+    set canonical_name  [format "%s_HIGHADDR" $canonical_tag]
+    puts $file_handle "\#define $canonical_name $highaddr_value"
+    
+    set canonical_name  [format "%s_ATG_MODE" $canonical_tag]
+    puts $file_handle "\#define $canonical_name $atg_mode_value"
+    add_field_to_periph_config_struct_atg $device_id $canonical_name
+    
+    set canonical_name  [format "%s_ATG_MODE_L2" $canonical_tag]
+    puts $file_handle "\#define $canonical_name $atg_mode_value_l2"
+    add_field_to_periph_config_struct_atg $device_id $canonical_name
+    
+    set canonical_name  [format "%s_AXIS_MODE" $canonical_tag]
+    puts $file_handle "\#define $canonical_name $axi_mode_value"
+    add_field_to_periph_config_struct_atg $device_id $canonical_name
+}
+
+proc xdefine_trafgen_config_file {file_name drv_string} {
+
+    global periph_ninstances
+
+    set filename [file join "src" $file_name]
+    file delete $filename
+    set config_file [open $filename w]
+    ::hsm::utils::write_c_header $config_file "Driver configuration"
+    puts $config_file "\#include \"xparameters.h\""
+    puts $config_file "\#include \"[string tolower $drv_string].h\""
+    puts $config_file "\n/*"
+    puts $config_file "* The configuration table for devices"
+    puts $config_file "*/\n"
+    puts $config_file [format "%s_Config %s_ConfigTable\[\] =" $drv_string $drv_string]
+    puts $config_file "\{"
+
+    set start_comma ""
+    for {set i 0} {$i < $periph_ninstances} {incr i} {
+
+        puts $config_file [format "%s\t\{" $start_comma]
+        set comma ""
+        foreach field [get_periph_config_struct_fields_atg $i] {
+            puts -nonewline $config_file [format "%s\t\t%s" $comma $field]
+            set comma ",\n"
+        }
+
+        puts -nonewline $config_file "\n\t\}"
+        set start_comma ",\n"
+    }
+    puts $config_file "\n\};\n"
+    close $config_file
+}
+
+proc generate {drv_handle} {
+    xdefine_trafgen_include_file $drv_handle "xparameters.h" "XTrafGen"
+    xdefine_trafgen_config_file  "xtrafgen_g.c" "XTrafGen"
+}
diff --git a/XilinxProcessorIPLib/drivers/trafgen/examples/index.html b/XilinxProcessorIPLib/drivers/trafgen/examples/index.html
new file mode 100755
index 00000000..b023a7c2
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/trafgen/examples/index.html
@@ -0,0 +1,20 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
+<html>
+<head>
+<meta http-equiv="Content-Language" content="en-us">
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<title>Driver example applications</title>
+<link rel="stylesheet" type="text/css" href="../help.css">
+</head>
+<body bgcolor="#FFFFFF">
+<h1> Example Applications for the driver trafgen_v3_1 </h1>
+<HR>
+<ul>
+  <li>xtrafgen_interrupt_example.c <a href="xtrafgen_interrupt_example.c">(source)</a> </li>
+   <li>xtrafgen_master_streaming_example.c <a href="xtrafgen_master_streaming_example.c">(source)</a> </li>
+    <li>xtrafgen_polling_example.c <a href="xtrafgen_polling_example.c">(source)</a> </li>
+     <li>xtrafgen_static_mode_example.c <a href="xtrafgen_static_mode_example.c">(source)</a> </li>
+</ul>
+<p><font face="Times New Roman" color="#800000">Copyright � 1995-2014 Xilinx, Inc. All rights reserved.</font></p>
+</body>
+</html>
diff --git a/XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_interrupt_example.c b/XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_interrupt_example.c
new file mode 100755
index 00000000..b66162a7
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_interrupt_example.c
@@ -0,0 +1,667 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xtrafgen_interrupt_example.c
+ *
+ * This file demonstrates how to use the xtrafgen driver on the Xilinx AXI
+ * Traffic Generator core. The AXI Traffic Generator IP is designed to 
+ * generate AXI4 traffic which can be used to stress different modules/
+ * interconnect connected in the system. It has three internal RAMS: MASTER
+ * RAM, COMMAND RAM, PARAMETER RAM.  MASTER RAM is used to load/store data from 
+ * this memory for write/read transactions.  And the commands to be issued are
+ * loaded into COMMAND and PARAMETER RAMs.
+ *
+ * This example demonstrates by programming known data to Master RAM and
+ * commands to Command and Param RAM. Initiating the master logic will take 
+ * the data from Master RAM (from a location) and generate data for slave 
+ * transactions which will be stored in Master RAM at a different location
+ * specified by commands. The test passes when the master logic interrupt
+ * asserts and verifies for data to be same.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a srt  01/25/13 First release
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+
+/***************************** Include Files *********************************/
+#include "xtrafgen.h"
+#include "xparameters.h"
+#include "xil_exception.h"
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+#include "xuartns550_l.h"       /* to use uartns550 */
+#endif
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+ #include "xintc.h"
+#else
+ #include "xscugic.h"
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define TRAFGEN_DEV_ID	XPAR_XTRAFGEN_0_DEVICE_ID
+
+#ifdef XPAR_V6DDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR	XPAR_V6DDR_0_S_AXI_BASEADDR
+#elif XPAR_S6DDR_0_S0_AXI_BASEADDR
+#define DDR_BASE_ADDR	XPAR_S6DDR_0_S0_AXI_BASEADDR
+#elif XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR	XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#elif XPAR_MIG7SERIES_0_BASEADDR
+#define DDR_BASE_ADDR XPAR_MIG7SERIES_0_BASEADDR
+#endif
+
+#ifndef DDR_BASE_ADDR
+#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
+                        DEFAULT SET TO 0x01000000
+#define MEM_BASE_ADDR	0x01000000
+#else
+#define MEM_BASE_ADDR	(DDR_BASE_ADDR + 0x1000000)
+#endif
+
+#define AXI_ADDRESS		MEM_BASE_ADDR
+#define TEST_LENGTH		0x8
+#define MSTRRAM_INDEX	(TEST_LENGTH) * 4
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+#define ERR_INTR_ID              XPAR_INTC_0_TRAFGEN_0_ERR_OUT_VEC_ID
+#define CMP_INTR_ID              XPAR_INTC_0_TRAFGEN_0_IRQ_OUT_VEC_ID
+#else
+#define ERR_INTR_ID              XPAR_FABRIC_TRAFGEN_0_ERR_OUT_VEC_ID
+#define CMP_INTR_ID              XPAR_FABRIC_TRAFGEN_0_IRQ_OUT_VEC_ID
+#endif
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+#define INTC_DEVICE_ID          XPAR_INTC_0_DEVICE_ID
+#else
+#define INTC_DEVICE_ID          XPAR_SCUGIC_SINGLE_DEVICE_ID
+#endif
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+ #define INTC           XIntc
+ #define INTC_HANDLER   XIntc_InterruptHandler
+#else
+ #define INTC           XScuGic
+ #define INTC_HANDLER   XScuGic_InterruptHandler
+#endif
+
+#undef DEBUG
+
+/************************** Function Prototypes ******************************/
+#ifdef XPAR_UARTNS550_0_BASEADDR
+static void Uart550_Setup(void);
+#endif
+
+int XTrafGenInterruptExample(XTrafGen *InstancePtr, u16 DeviceId);
+void InitDefaultCommands(XTrafGen_Cmd *CmdPtr);
+static void MasterCompleteIntrHandler(void *Callback);
+static void ErrIntrHandler(void *Callback);
+static int SetupIntrSystem(INTC * IntcInstancePtr,
+                           XTrafGen * InstancePtr, u16 CmpIntrId, u16 ErrIntrId);
+static void DisableIntrSystem(INTC * IntcInstancePtr,
+                                        u16 CmpIntrId, u16 ErrIntrId);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Device instance definitions
+ */
+XTrafGen XTrafGenInstance;
+
+/*
+ * Instance of the Interrupt Controller
+ */
+static INTC Intc;
+
+/*
+ * Test Data to write into Master RAM
+ */
+u32 MasterRamData[TEST_LENGTH] = {0x00000000,
+				0x11111111,
+				0x22222222,
+				0x33333333,
+				0x44444444,
+				0x55555555,
+				0x66666666,
+				0x77777777,
+			};
+/*
+ * Data read from Master RAM
+ */
+u32 VerifyRamData[TEST_LENGTH];
+
+/*
+ * Flags interrupt handlers use to notify the application context the events.
+ */
+volatile int Done;
+volatile int Error;
+
+/*****************************************************************************/
+/**
+*
+* Main function
+*
+* This function is the main entry of the traffic generator test. 
+*
+* @param	None
+*
+* @return	- XST_SUCCESS if tests pass
+* 		- XST_FAILURE if fails.
+*
+* @note		None
+*
+******************************************************************************/
+int main()
+{
+	int Status;
+
+	xil_printf("Entering main\n\r");
+
+	Status = XTrafGenInterruptExample(&XTrafGenInstance, TRAFGEN_DEV_ID);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Traffic Generator Interrupt Example Test Failed\n\r");
+		xil_printf("--- Exiting main() ---\n\r");
+		return XST_FAILURE;
+	}
+
+	xil_printf("Traffic Generator Interrupt Example Test passed\n\r");
+	xil_printf("--- Exiting main() ---\n\r");
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function demonstrates the usage Traffic Generator
+* It does the following:
+*       - Set up the output terminal if UART16550 is in the hardware build
+*       - Initialize the AXI Traffic Generator device
+*	- Initialize Master RAM
+*       - Initialize commands and add them to list
+*       - Program internal command and parameter RAMs
+*	- Start Master Logic
+*       - Wait for the master logic to finish
+*       - Check for errors
+*       - Read Master RAM and verify data
+*       - Return test status and exit
+*
+* @param	InstancePtr is a pointer to the instance of the
+*		XTrafGen component.
+* @param	DeviceId is Device ID of the Axi Traffic Generator Device,
+*		typically XPAR_<TRAFGEN_instance>_DEVICE_ID value from
+*		xparameters.h.
+*
+* @return	-XST_SUCCESS to indicate success
+*		-XST_FAILURE to indicate failure
+*
+******************************************************************************/
+int XTrafGenInterruptExample(XTrafGen *InstancePtr, u16 DeviceId)
+{
+
+	XTrafGen_Config *Config;
+	XTrafGen_Cmd Cmd;
+	XTrafGen_Cmd *CmdPtr = &Cmd;
+	u32 MasterRamIndex = 0;
+	int Status = XST_SUCCESS;
+	int Index;
+
+	/* Initial setup for Uart16550 */
+#ifdef XPAR_UARTNS550_0_BASEADDR
+
+	Uart550_Setup();
+
+#endif
+
+	/* Initialize the Device Configuration Interface driver */
+	Config = XTrafGen_LookupConfig(DeviceId);
+	if (!Config) {
+		xil_printf("No config found for %d\r\n", DeviceId);
+		return XST_FAILURE;
+	}
+
+	/*
+	 * This is where the virtual address would be used, this example
+	 * uses physical address.
+	 */
+	Status = XTrafGen_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Initialization failed\n\r");
+		return Status;
+	}
+
+	/* Program Master RAM with Test Data */
+	XTrafGen_AccessMasterRam(InstancePtr, MasterRamIndex,
+			sizeof(MasterRamData), XTG_WRITE, MasterRamData);
+
+	/* Initialize default command fields */
+	InitDefaultCommands(CmdPtr);
+
+	/* Add Valid Command for Write Region */
+	CmdPtr->CRamCmd.Address = AXI_ADDRESS;
+	CmdPtr->CRamCmd.MasterRamIndex = 0x0;
+	CmdPtr->CRamCmd.Length = TEST_LENGTH - 1;
+	CmdPtr->RdWrFlag = XTG_WRITE;
+	CmdPtr->CRamCmd.ValidCmd = 1;
+	CmdPtr->CRamCmd.MyDepend = 0;
+	CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
+						XTG_WRITE) + 1;
+	Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("AddCommand() failed\n\r");
+		return Status;
+	}
+
+	/* Add Valid Command for Read Region */
+	CmdPtr->CRamCmd.Address = AXI_ADDRESS;
+	CmdPtr->CRamCmd.MasterRamIndex = MSTRRAM_INDEX;
+	CmdPtr->CRamCmd.Length = 7;
+	CmdPtr->CRamCmd.Size = 0x2;
+	CmdPtr->RdWrFlag = XTG_READ;
+	CmdPtr->CRamCmd.ValidCmd = 1;
+	CmdPtr->CRamCmd.MyDepend = 0;
+	/* Make this command dependent on Write logic command 1 */
+	CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
+						XTG_WRITE) + 1;
+	Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("AddCommand() failed\n\r");
+		return Status;
+	}
+
+	/* Add second valid command to Write Region  */
+	CmdPtr->CRamCmd.Address = AXI_ADDRESS + MSTRRAM_INDEX;
+	CmdPtr->CRamCmd.MasterRamIndex = MSTRRAM_INDEX;
+	CmdPtr->CRamCmd.Length = 0;
+	CmdPtr->RdWrFlag = XTG_WRITE;
+	CmdPtr->CRamCmd.ValidCmd = 1;
+	CmdPtr->CRamCmd.MyDepend = 0;
+	/* Make this command dependent on Read logic command 1 */
+	CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
+						XTG_READ) + 1;
+	Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("AddCommand() failed\n\r");
+		return Status;
+	}
+
+	/* Add invalid command at the end of Write Queue  */
+	CmdPtr->CRamCmd.Address = AXI_ADDRESS;
+	CmdPtr->CRamCmd.MasterRamIndex = 0x0;
+	CmdPtr->RdWrFlag = XTG_WRITE;
+	CmdPtr->CRamCmd.Size = 0;
+	CmdPtr->CRamCmd.ValidCmd = 0;
+	CmdPtr->CRamCmd.MyDepend = 0;
+	/* Make this command dependent on Read logic command 1 */
+	CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
+						XTG_READ) + 1;;
+	Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("AddCommand() failed\n\r");
+		return Status;
+	}
+
+	/* Add invalid command at the end of Read Queue  */
+	CmdPtr->CRamCmd.MasterRamIndex = 0x0;
+	CmdPtr->RdWrFlag = XTG_READ;
+	CmdPtr->CRamCmd.Length = 0;
+	CmdPtr->CRamCmd.Size = 0x0;
+	CmdPtr->CRamCmd.ValidCmd = 0;
+	/* Make this command dependent on Write logic command 2 */
+	CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
+						XTG_WRITE) + 1;
+	Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("AddCommand() failed\n\r");
+		return Status;
+	}
+
+	/* Display Command list */
+#ifdef DEBUG
+	XTrafGen_PrintCmds(InstancePtr);
+#endif
+
+	/* Program all prepared commands */
+	Status = XTrafGen_WriteCmdsToHw(InstancePtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("WriteCmdsToHw() failed\n\r");
+		return Status;
+	}
+
+	/* Enable Complete Interrupt bit */
+	XTrafGen_EnableMasterCmpInterrupt(InstancePtr);
+
+	/* Set up Interrupt system  */
+	Status = SetupIntrSystem(&Intc, InstancePtr, CMP_INTR_ID, ERR_INTR_ID);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Failed intr setup\r\n");
+		return Status;
+	}
+
+	/* Initialize flags before start transfer test  */
+	Done = 0;
+	Error = 0;
+
+	/* Start Master Logic */
+	XTrafGen_StartMasterLogic(InstancePtr);
+
+	while (!Done && !Error);
+
+	if (Error) {
+		xil_printf("Errors in transfer\r\n");
+		return XST_FAILURE;
+	}
+
+	/* Read Master RAM */
+	XTrafGen_AccessMasterRam(InstancePtr, MSTRRAM_INDEX,
+			sizeof(MasterRamData), XTG_READ, VerifyRamData);
+
+	/* Verify Data */
+	for (Index = 0 ; Index < TEST_LENGTH - 1; Index++) {
+		if (VerifyRamData[Index] != MasterRamData[Index]) {
+			xil_printf("Data Mismatch\n\r");
+			return XST_FAILURE;
+		}
+	}
+
+	DisableIntrSystem(&Intc, CMP_INTR_ID, ERR_INTR_ID);
+	return Status;
+}
+
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+/*****************************************************************************/
+/*
+*
+* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
+*
+* @param	None
+*
+* @return	None
+*
+* @note		None
+*
+******************************************************************************/
+static void Uart550_Setup(void)
+{
+
+	XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
+			XPAR_XUARTNS550_CLOCK_HZ, 9600);
+
+	XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
+			XUN_LCR_8_DATA_BITS);
+}
+#endif
+
+/*****************************************************************************/
+/*
+*
+* Initialize default command fields
+*
+* @param	XTrafGen_Cmd is a pointer to command structure
+*
+* @return	XST_SUCCESS if successful
+*
+* @note		None
+*
+******************************************************************************/
+void InitDefaultCommands(XTrafGen_Cmd *CmdPtr)
+{
+	/* Command RAM default command values */
+	CmdPtr->CRamCmd.LastAddress = 0;
+	CmdPtr->CRamCmd.Prot = 0;
+	CmdPtr->CRamCmd.Id = 0;
+	CmdPtr->CRamCmd.Size = 0x2;
+	CmdPtr->CRamCmd.Burst = 0x1;
+	CmdPtr->CRamCmd.Lock = 0;
+	CmdPtr->CRamCmd.Length = 0;
+	CmdPtr->CRamCmd.MyDepend = 0;
+	CmdPtr->CRamCmd.OtherDepend = 0;
+	CmdPtr->CRamCmd.MasterRamIndex = 0;
+	CmdPtr->CRamCmd.Qos = 0;
+	CmdPtr->CRamCmd.User = 0;
+	CmdPtr->CRamCmd.Cache = 0;
+	CmdPtr->CRamCmd.ExpectedResp = 0x7;
+
+	/* Parameter RAM default command values */
+	CmdPtr->PRamCmd.AddrMode = 0;
+	CmdPtr->PRamCmd.IdMode = 0;
+	CmdPtr->PRamCmd.IntervalMode = 0;
+	CmdPtr->PRamCmd.OpCntl0 = 0;
+	CmdPtr->PRamCmd.OpCntl1 = 0;
+	CmdPtr->PRamCmd.OpCntl2 = 0;
+	CmdPtr->PRamCmd.Opcode = 0;
+}
+
+/*****************************************************************************/
+/*
+*
+* This is the Master Logic Complete Interrupt handler function.
+*
+* This clears the master complete interrupt and set the done flag.
+*
+* @param	Callback is a pointer to Instance of Traffic Generator device.
+*
+* @return	None
+*
+* @note		None
+*
+******************************************************************************/
+static void MasterCompleteIntrHandler(void *Callback)
+{
+	XTrafGen *InstancePtr = (XTrafGen *) Callback;
+
+	XTrafGen_ClearMasterCmpInterrupt(InstancePtr);
+
+	Done = 1;
+}
+
+/*****************************************************************************/
+/*
+*
+* This is the Error Interrupt handler function.
+*
+* This clears the errors and set the error flag.
+*
+* @param	Callback is a pointer to Instance of Traffic Generator device.
+*
+* @return	None
+*
+* @note		None
+*
+******************************************************************************/
+static void ErrIntrHandler(void *Callback)
+{
+	XTrafGen *InstancePtr = (XTrafGen *) Callback;
+	u32 Value;
+
+	Value = XTrafGen_ReadErrors(InstancePtr);
+	if (Value) {
+		XTrafGen_ClearErrors(InstancePtr, Value);
+	}
+		
+	Error = 1;
+}
+
+/*****************************************************************************/
+/*
+*
+* This function setups the interrupt system so interrupts can occur for the
+* Traffic Generator, it assumes INTC component exists in the hardware system.
+*
+* @param	IntcInstancePtr is a pointer to the instance of the INTC.
+* @param	InstancePtr is a pointer to the instance of the Traffic
+*		Generator Device.
+* @param	CmpIntrId is the Master Complete Interrupt ID.
+* @param	ErrIntrId is the Error Interrupt ID.
+*
+* @return
+* 		- XST_SUCCESS if successful,
+* 		- XST_FAILURE if not succesful
+*
+* @note		None.
+*
+******************************************************************************/
+static int SetupIntrSystem(INTC * IntcInstancePtr,
+			XTrafGen * InstancePtr, u16 CmpIntrId, u16 ErrIntrId)
+{
+	int Status;
+
+#ifdef XPAR_INTC_0_DEVICE_ID
+
+	/* Initialize the interrupt controller and connect the ISRs */
+	Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Failed init intc\r\n");
+		return XST_FAILURE;
+	}
+
+	Status = XIntc_Connect(IntcInstancePtr, CmpIntrId,
+			(XInterruptHandler) MasterCompleteIntrHandler, InstancePtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Failed master complete connect intc\r\n");
+		return XST_FAILURE;
+	}
+	
+	Status = XIntc_Connect(IntcInstancePtr, ErrIntrId,
+			(XInterruptHandler) ErrIntrHandler, InstancePtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Failed err connect intc\r\n");
+		return XST_FAILURE;
+	}
+
+	/* Start the interrupt controller */
+	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Failed to start intc\r\n");
+		return XST_FAILURE;
+	}
+
+	XIntc_Enable(IntcInstancePtr, CmpIntrId);
+	XIntc_Enable(IntcInstancePtr, ErrIntrId);
+
+#else
+
+        XScuGic_Config *IntcConfig;
+
+	/*
+	 * Initialize the interrupt controller driver so that it is ready to
+	 * use.
+	 */
+	IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
+	if (NULL == IntcConfig) {
+		return XST_FAILURE;
+	}
+
+	Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
+				IntcConfig->CpuBaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	XScuGic_SetPriorityTriggerType(IntcInstancePtr, CmpIntrId, 0xA0, 0x3);
+
+	XScuGic_SetPriorityTriggerType(IntcInstancePtr, ErrIntrId, 0xA0, 0x3);
+
+	/*
+	 * Connect the device driver handler that will be called when an
+	 * interrupt for the device occurs, the handler defined above performs
+	 * the specific interrupt processing for the device.
+	 */
+	Status = XScuGic_Connect(IntcInstancePtr, CmpIntrId,
+				(Xil_InterruptHandler)MasterCompleteIntrHandler,
+				InstancePtr);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	Status = XScuGic_Connect(IntcInstancePtr, ErrIntrId,
+				(Xil_InterruptHandler)ErrIntrHandler,
+				InstancePtr);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	XScuGic_Enable(IntcInstancePtr, CmpIntrId);
+	XScuGic_Enable(IntcInstancePtr, ErrIntrId);
+#endif
+
+	/* Enable interrupts from the hardware */
+	Xil_ExceptionInit();
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+		(Xil_ExceptionHandler)INTC_HANDLER,
+		(void *)IntcInstancePtr);
+
+	Xil_ExceptionEnable();
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts for Traffic Generator.
+*
+* @param	IntcInstancePtr is the pointer to the INTC component instance
+* @param	CmpIntrId is interrupt ID associated w/ Master logic
+*		compleetion
+* @param	ErrIntrId is interrupt ID associated w/ Master or Slave
+*		errors.
+*
+* @return	None
+*
+* @note		None
+*
+******************************************************************************/
+static void DisableIntrSystem(INTC * IntcInstancePtr,
+				u16 CmpIntrId, u16 ErrIntrId)
+{
+#ifdef XPAR_INTC_0_DEVICE_ID
+	/* Disconnect the interrupts for the Master complete and error */
+	XIntc_Disconnect(IntcInstancePtr, CmpIntrId);
+	XIntc_Disconnect(IntcInstancePtr, ErrIntrId);
+#else
+	XScuGic_Disconnect(IntcInstancePtr, CmpIntrId);
+	XScuGic_Disconnect(IntcInstancePtr, ErrIntrId);
+#endif
+}
diff --git a/XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_master_streaming_example.c b/XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_master_streaming_example.c
new file mode 100755
index 00000000..f1e14380
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_master_streaming_example.c
@@ -0,0 +1,319 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xtrafgen_streamingmaster_example.c
+ *
+ * This file demonstrates how to use the xtrafgen driver on the Xilinx AXI
+ * Traffic Generator core. The AXI Traffic Generator IP is designed to 
+ * generate AXI4 traffic which can be used to stress different modules/
+ * interconnect connected in the system. 
+ *
+ * This example demonstrates how to use Streaming mode in Axi Traffic Genrator
+ * When Configured in Master only mode.In this mode the core genrates Streaming 
+ * Traffic based on the transfer length and transfer count configured.
+ * To test this example hardware Must contain a Streaming FIFO and the 
+ * Connections To Axi TrafficGen needs to made As shown below
+ *                                    ________________
+ *	 ____________       _________|AXI_STR_RXD     |
+ *	|	     |     |         |                |
+ *	|            |_____|         |                |
+ *	|  axi_master|               |________________|
+ *      |____________|                
+ *
+ *       Axi TrafficGen                 Axi Stream FIFO 
+ *
+ *<pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.01a adk  03/09/13 First release
+ * 2.00a adk  16/09/13 Fixed CR:737291
+ * 2.01a adk  15/11/13 Fixed CR:760808
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+
+/***************************** Include Files *********************************/
+#include "xtrafgen.h"
+#include "xparameters.h"
+#include "xil_exception.h"
+#include "xllfifo.h"
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+#include "xuartns550_l.h"       /* to use uartns550 */
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define TRAFGEN_DEV_ID	XPAR_AXI_TRAFFIC_GEN_2_DEVICE_ID
+
+#ifdef XPAR_V6DDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR	XPAR_V6DDR_0_S_AXI_BASEADDR
+#elif XPAR_S6DDR_0_S0_AXI_BASEADDR
+#define DDR_BASE_ADDR	XPAR_S6DDR_0_S0_AXI_BASEADDR
+#elif XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR	XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#elif XPAR_MIG7SERIES_0_BASEADDR
+#define DDR_BASE_ADDR XPAR_MIG_1_BASEADDR
+#endif
+
+#ifndef DDR_BASE_ADDR
+#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
+                        DEFAULT SET TO 0x01000000
+#define MEM_BASE_ADDR	0x01000000
+#else
+#define MEM_BASE_ADDR	(DDR_BASE_ADDR + 0x1000000)
+#endif
+
+#define BURST_LEN	255
+#define STR_FIFO0_ADDR   XPAR_AXI_FIFO_0_BASEADDR
+#undef DEBUG
+
+/************************** Function Prototypes ******************************/
+int XTrafGenStremingModeMasterExample(XTrafGen *InstancePtr, u16 DeviceId);
+#ifdef XPAR_UARTNS550_0_BASEADDR
+static void Uart550_Setup(void);
+#endif
+
+/************************** Variable Definitions *****************************/
+/*
+ * Device instance definitions
+ */
+XTrafGen XTrafGenInstance;
+XLlFifo  XLlFifoInstance;
+
+
+/*****************************************************************************/
+/**
+*
+* Main function
+*
+* This function is the main entry of the traffic generator test. 
+*
+* @param        None
+*
+* @return       - XST_SUCCESS if tests pass
+*               - XST_FAILURE if fails.
+*
+* @note         None.
+*
+******************************************************************************/
+int main()
+{
+	int Status;
+
+	xil_printf("--- Entering main() ---\n\r");
+
+	Status = XTrafGenStremingModeMasterExample(&XTrafGenInstance, 
+				TRAFGEN_DEV_ID);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Traffic Gen Streaming Example Test Failed\n\r");
+		xil_printf("--- Exiting main() ---\n\r");
+		return XST_FAILURE;
+	}
+
+	xil_printf("Traffic Gen Streaming Example Test passed\n\r");
+	xil_printf("--- Exiting main() ---\n\r");
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function demonstrates the usage Traffic Generator
+* It does the following:
+*       - Set up the output terminal if UART16550 is in the hardware build
+*       - Initialize the AXI Traffic Generator device
+*       - Initialize the Streaming FIFO device
+*	- Set the Desired Transfer Count and Transfer Length
+*	- Enable the Traffic Genration on the Core
+*	- Check for the Streaming data on the FIFO 
+*       - Return test status and exit
+*
+* @param	InstancePtr is a pointer to the instance of the
+*		XTrafGen component.
+* @param	DeviceId is Device ID of the Axi Traffic Generator Device,
+*
+*
+* @param	InstancePtr is a pointer to the instance of the
+*			XTrafGen component.
+* @param	DeviceId is Device ID of the Axi Traffic Generator Device,
+*			typically XPAR_<TRAFGEN_instance>_DEVICE_ID value from
+*			xparameters.h.
+*
+* @return	-XST_SUCCESS to indicate success
+*			-XST_FAILURE to indicate failure
+*
+******************************************************************************/
+int XTrafGenStremingModeMasterExample(XTrafGen *InstancePtr, u16 DeviceId)
+{
+
+	XTrafGen_Config *Config;
+	int Status = XST_SUCCESS;
+	u32 Len; 
+	u32 TransferCnt;
+	u32 AtgPacket;
+	u32 FifoOcy;
+	u32 FifoLen;
+	
+        /* Initial setup for Uart16550 */
+#ifdef XPAR_UARTNS550_0_BASEADDR
+
+	Uart550_Setup();
+
+#endif
+
+	/* Initialize the Device Configuration Interface driver */
+	Config = XTrafGen_LookupConfig(DeviceId);
+	if (!Config) {
+		xil_printf("No config found for %d\r\n", DeviceId);
+		return XST_FAILURE;
+	}
+
+	/*
+	 * This is where the virtual address would be used, this example
+	 * uses physical address.
+	 */
+	Status = XTrafGen_CfgInitialize(InstancePtr, Config,
+				Config->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Initialization failed\n\r");
+		return Status;
+	}
+	
+	/* Check for the Streaming Mode */
+	if(InstancePtr->OperatingMode != XTG_MODE_STREAMING) {
+		return XST_FAILURE;
+	}
+	
+	/* Initialize the Fifo Instance */
+	XLlFifo_Initialize(&XLlFifoInstance , STR_FIFO0_ADDR);
+	Status = XLlFifo_Status(&XLlFifoInstance);
+	XLlFifo_IntClear(&XLlFifoInstance,0xffffffff);
+	Status = XLlFifo_Status(&XLlFifoInstance);
+	if(Status != 0x0) {
+		xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
+			    "Expected : 0x0\n\r",
+			    XLlFifo_Status(&XLlFifoInstance));
+		return XST_FAILURE;
+	}
+	
+	/* 
+	 * Set the Required trasaction length 
+	 * and required transaction count
+	 */
+	XTrafGen_ResetStreamingRandomLen(InstancePtr);
+	XTrafGen_SetStreamingTransLen(InstancePtr , 3);
+	XTrafGen_SetStreamingTransCnt(InstancePtr , 2);
+	
+	Len = XTrafGen_GetStreamingTransLen(InstancePtr);
+	TransferCnt = XTrafGen_GetStreamingTransCnt(InstancePtr);
+
+	/* 
+	 * Calculate the ATG data that is sent on the 
+	 * CORE when Streaming is Enabled 
+	 */
+	AtgPacket = (Len +1) * TransferCnt;
+		
+	/* Enable the traffic genration */
+	XTrafGen_StreamEnable(InstancePtr);
+	
+	FifoOcy = XLlFifo_iRxOccupancy(&XLlFifoInstance);
+	if(FifoOcy != AtgPacket) {
+		xil_printf("\n ERROR : Not received complete packets : 0x%x \t"
+			"Expected : 0x%x \n\r",
+			XLlFifo_iRxOccupancy(&XLlFifoInstance), AtgPacket);
+		return XST_FAILURE;
+	}
+	
+	FifoLen = XLlFifo_iRxGetLen(&XLlFifoInstance);
+	if(FifoLen != (AtgPacket*4/TransferCnt)) {
+		xil_printf("\n ERROR : Not received complete bytes : 0x%x \t"
+			"Expected : 0x%x \n\n\r",
+			XLlFifo_iRxGetLen(&XLlFifoInstance),Len);
+		return XST_FAILURE;
+	}
+	while(XLlFifo_iRxGetLen(&XLlFifoInstance)) {
+		xil_printf("Recived packet DATA: 0x%x \n\r",
+				XLlFifo_RxGetWord(&XLlFifoInstance));
+	}
+	
+	if(XLlFifo_iRxOccupancy(&XLlFifoInstance) != 0) {
+		xil_printf("\n ERROR : RDFO is not becoming Empty : 0x%x \t"
+				"Expected : 0x0 \n\n\r",
+				XLlFifo_iRxOccupancy(&XLlFifoInstance));
+		return XST_FAILURE;
+	}
+	
+	if(XLlFifo_iRxGetLen(&XLlFifoInstance) != 0) {
+		xil_printf("\n ERROR : RLR is not becoming Empty : 0x%x \t"
+				"Expected : 0x0 \n\n\r",
+				XLlFifo_iRxGetLen(&XLlFifoInstance));
+		return XST_FAILURE;
+	}
+	
+	return XST_SUCCESS;
+}
+
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+/*****************************************************************************/
+/*
+*
+* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
+*
+* @param        None
+*
+* @return       None
+*
+* @note         None.
+*
+******************************************************************************/
+static void Uart550_Setup(void)
+{
+
+	XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
+			XPAR_XUARTNS550_CLOCK_HZ, 9600);
+
+	XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
+			XUN_LCR_8_DATA_BITS);
+}
+#endif
+
diff --git a/XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_polling_example.c b/XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_polling_example.c
new file mode 100755
index 00000000..d0e286c5
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_polling_example.c
@@ -0,0 +1,429 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xtrafgen_polling_example.c
+ *
+ * This file demonstrates how to use the xtrafgen driver on the Xilinx AXI
+ * Traffic Generator core. The AXI Traffic Generator IP is designed to 
+ * generate AXI4 traffic which can be used to stress different modules/
+ * interconnect connected in the system. It has three internal RAMS: MASTER
+ * RAM, COMMAND RAM, PARAMETER RAM.  MASTER RAM is used to load/store data from 
+ * this memory for write/read transactions.  And the commands to be issued are
+ * loaded into COMMAND and PARAMETER RAMs.
+ *
+ * This example demonstrates by programming known data to Master RAM and
+ * commands to Command and Param RAM. Initiating the master logic will take 
+ * the data from Master RAM (from a location) and generate data for slave 
+ * transactions which will be stored in Master RAM at a different location
+ * specified by commands. The test passes when the master logic completes and  
+ * verifies for data to be same.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a srt  01/25/13 First release
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+
+/***************************** Include Files *********************************/
+#include "xtrafgen.h"
+#include "xparameters.h"
+#include "xil_exception.h"
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+#include "xuartns550_l.h"       /* to use uartns550 */
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define TRAFGEN_DEV_ID	XPAR_XTRAFGEN_0_DEVICE_ID
+
+#ifdef XPAR_V6DDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR	XPAR_V6DDR_0_S_AXI_BASEADDR
+#elif XPAR_S6DDR_0_S0_AXI_BASEADDR
+#define DDR_BASE_ADDR	XPAR_S6DDR_0_S0_AXI_BASEADDR
+#elif XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#define DDR_BASE_ADDR	XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
+#elif XPAR_MIG_7SERIES_1_BASEADDR
+#define DDR_BASE_ADDR XPAR_MIG_7SERIES_1_BASEADDR
+#elif XPAR_MIG7SERIES_0_BASEADDR
+#define DDR_BASE_ADDR XPAR_MIG7SERIES_0_BASEADDR
+#endif
+
+#ifndef DDR_BASE_ADDR
+#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
+                        DEFAULT SET TO 0x01000000
+#define MEM_BASE_ADDR	0x01000000
+#else
+#define MEM_BASE_ADDR	(DDR_BASE_ADDR + 0x1000000)
+#endif
+
+#define AXI_ADDRESS		MEM_BASE_ADDR
+#define TEST_LENGTH		0x8
+#define MSTRRAM_INDEX	(TEST_LENGTH) * 4
+
+#undef DEBUG
+
+/************************** Function Prototypes ******************************/
+int XTrafGenPollingExample(XTrafGen *InstancePtr, u16 DeviceId);
+void InitDefaultCommands(XTrafGen_Cmd *CmdPtr);
+#ifdef XPAR_UARTNS550_0_BASEADDR
+static void Uart550_Setup(void);
+#endif
+
+/************************** Variable Definitions *****************************/
+/*
+ * Device instance definitions
+ */
+XTrafGen XTrafGenInstance;
+
+/*
+ * Test Data to write into Master RAM
+ */
+u32 MasterRamData[TEST_LENGTH] = {0x00000000,
+				0x11111111,
+				0x22222222,
+				0x33333333,
+				0x44444444,
+				0x55555555,
+				0x66666666,
+				0x77777777,
+			};
+/*
+ * Data read from Master RAM
+ */
+u32 VerifyRamData[TEST_LENGTH];
+
+/*****************************************************************************/
+/**
+*
+* Main function
+*
+* This function is the main entry of the traffic generator test. 
+*
+* @param        None
+*
+* @return       - XST_SUCCESS if tests pass
+*               - XST_FAILURE if fails.
+*
+* @note         None.
+*
+******************************************************************************/
+int main()
+{
+	int Status;
+
+	xil_printf("Entering main\n\r");
+
+	Status = XTrafGenPollingExample(&XTrafGenInstance, TRAFGEN_DEV_ID);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Traffic Generator Polling Example Test Failed\n\r");
+		xil_printf("--- Exiting main() ---\n\r");
+		return XST_FAILURE;
+	}
+
+	xil_printf("Traffic Generator Polling Example Test passed\n\r");
+	xil_printf("--- Exiting main() ---\n\r");
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function demonstrates the usage Traffic Generator
+* It does the following:
+*       - Set up the output terminal if UART16550 is in the hardware build
+*       - Initialize the AXI Traffic Generator device
+*	- Initialize Master RAM
+*       - Initialize commands and add them to list
+*       - Program internal command and parameter RAMs
+*	- Start Master Logic
+*       - Wait for the master logic to finish
+*       - Check for errors
+*       - Read Master RAM and verify data
+*       - Return test status and exit
+*
+* @param	InstancePtr is a pointer to the instance of the
+*		XTrafGen component.
+* @param	DeviceId is Device ID of the Axi Traffic Generator Device,
+*
+*
+* @param	InstancePtr is a pointer to the instance of the
+*			XTrafGen component.
+* @param	DeviceId is Device ID of the Axi Traffic Generator Device,
+*			typically XPAR_<TRAFGEN_instance>_DEVICE_ID value from
+*			xparameters.h.
+*
+* @return	-XST_SUCCESS to indicate success
+*			-XST_FAILURE to indicate failure
+*
+******************************************************************************/
+int XTrafGenPollingExample(XTrafGen *InstancePtr, u16 DeviceId)
+{
+
+	XTrafGen_Config *Config;
+	XTrafGen_Cmd Cmd;
+	XTrafGen_Cmd *CmdPtr = &Cmd;
+	u32 MasterRamIndex = 0;
+	u32 Done;
+	u32 Error;
+	int Status = XST_SUCCESS;
+	int Index;
+
+        /* Initial setup for Uart16550 */
+#ifdef XPAR_UARTNS550_0_BASEADDR
+
+	Uart550_Setup();
+
+#endif
+
+	/* Initialize the Device Configuration Interface driver */
+	Config = XTrafGen_LookupConfig(DeviceId);
+	if (!Config) {
+		xil_printf("No config found for %d\r\n", DeviceId);
+		return XST_FAILURE;
+	}
+
+	/*
+	 * This is where the virtual address would be used, this example
+	 * uses physical address.
+	 */
+	Status = XTrafGen_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Initialization failed\n\r");
+		return Status;
+	}
+
+	/* Program Master RAM with Test Data */
+	XTrafGen_AccessMasterRam(InstancePtr, MasterRamIndex,
+			sizeof(MasterRamData), XTG_WRITE, MasterRamData);
+
+	/* Initialize default command fields */
+	InitDefaultCommands(CmdPtr);
+
+	/* Add Valid Command for Write Region */
+	CmdPtr->CRamCmd.Address = AXI_ADDRESS;
+	CmdPtr->CRamCmd.MasterRamIndex = 0x0;
+	CmdPtr->CRamCmd.Length = TEST_LENGTH - 1;
+	CmdPtr->RdWrFlag = XTG_WRITE;
+	CmdPtr->CRamCmd.ValidCmd = 1;
+	CmdPtr->CRamCmd.MyDepend = 0;
+	CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
+						XTG_WRITE) + 1;
+	Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("AddCommand() failed\n\r");
+		return Status;
+	}
+
+	/* Add Valid Command for Read Region */
+	CmdPtr->CRamCmd.Address = AXI_ADDRESS;
+	CmdPtr->CRamCmd.MasterRamIndex = MSTRRAM_INDEX;
+	CmdPtr->CRamCmd.Length = 7;
+	CmdPtr->CRamCmd.Size = 0x2;
+	CmdPtr->RdWrFlag = XTG_READ;
+	CmdPtr->CRamCmd.ValidCmd = 1;
+	CmdPtr->CRamCmd.MyDepend = 0;
+	/* Make this command dependent on Write logic command 1 */
+	CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
+						XTG_WRITE) + 1;
+	Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("AddCommand() failed\n\r");
+		return Status;
+	}
+
+	/* Add second valid command to Write Region  */
+	CmdPtr->CRamCmd.Address = AXI_ADDRESS + MSTRRAM_INDEX;
+	CmdPtr->CRamCmd.MasterRamIndex = MSTRRAM_INDEX;
+	CmdPtr->CRamCmd.Length = 0;
+	CmdPtr->RdWrFlag = XTG_WRITE;
+	CmdPtr->CRamCmd.ValidCmd = 1;
+	CmdPtr->CRamCmd.MyDepend = 0;
+	/* Make this command dependent on Read logic command 1 */
+	CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
+						XTG_READ) + 1;
+	Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("AddCommand() failed\n\r");
+		return Status;
+	}
+
+	/* Add invalid command at the end of Write Queue  */
+	CmdPtr->CRamCmd.Address = AXI_ADDRESS;
+	CmdPtr->CRamCmd.MasterRamIndex = 0x0;
+	CmdPtr->RdWrFlag = XTG_WRITE;
+	CmdPtr->CRamCmd.Size = 0;
+	CmdPtr->CRamCmd.ValidCmd = 0;
+	CmdPtr->CRamCmd.MyDepend = 0;
+	/* Make this command dependent on Read logic command 1 */
+	CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
+						XTG_READ) + 1;;
+	Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("AddCommand() failed\n\r");
+		return Status;
+	}
+
+	/* Add invalid command at the end of Read Queue  */
+	CmdPtr->CRamCmd.MasterRamIndex = 0x0;
+	CmdPtr->RdWrFlag = XTG_READ;
+	CmdPtr->CRamCmd.Length = 0;
+	CmdPtr->CRamCmd.Size = 0x0;
+	CmdPtr->CRamCmd.ValidCmd = 0;
+	/* Make this command dependent on Write logic command 2 */
+	CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
+    						XTG_WRITE) + 1;
+	Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("AddCommand() failed\n\r");
+		return Status;
+	}
+
+	/* Display Command list */
+#ifdef DEBUG
+	XTrafGen_PrintCmds(InstancePtr);
+#endif
+
+	/* Program all prepared commands */
+	Status = XTrafGen_WriteCmdsToHw(InstancePtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("WriteCmdsToHw() failed\n\r");
+		return Status;
+	}
+
+	/* Start Master Logic */
+	XTrafGen_StartMasterLogic(InstancePtr);
+
+	while (1) {
+		Done = XTrafGen_IsMasterLogicDone(InstancePtr);
+		if (Done) {
+			break;
+		}
+
+		Error = XTrafGen_ReadErrors(InstancePtr);
+		if (Error) {
+			XTrafGen_ClearErrors(InstancePtr, Error);
+			return XST_FAILURE;
+		}
+	}
+
+	/* Read Master RAM */
+	XTrafGen_AccessMasterRam(InstancePtr, MSTRRAM_INDEX,
+			sizeof(MasterRamData), XTG_READ, VerifyRamData);
+
+	/* Verify Data */
+	for (Index = 0 ; Index < TEST_LENGTH - 1; Index++) {
+		if (VerifyRamData[Index] != MasterRamData[Index]) {
+			xil_printf("Data Mismatch\n\r");
+			return XST_FAILURE;
+		}
+	}
+
+	return XST_SUCCESS;
+}
+
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+/*****************************************************************************/
+/*
+*
+* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
+*
+* @param        None
+*
+* @return       None
+*
+* @note         None.
+*
+******************************************************************************/
+static void Uart550_Setup(void)
+{
+
+	XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
+			XPAR_XUARTNS550_CLOCK_HZ, 9600);
+
+	XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
+			XUN_LCR_8_DATA_BITS);
+}
+#endif
+
+/*****************************************************************************/
+/*
+*
+* Initialize default command fields
+*
+* @param        XTrafGen_Cmd is a pointer to command structure
+*
+* @return       None.
+*
+* @note         None.
+*
+******************************************************************************/
+void InitDefaultCommands(XTrafGen_Cmd *CmdPtr)
+{
+	/* Command RAM default command values */
+	CmdPtr->CRamCmd.LastAddress = 0;
+	CmdPtr->CRamCmd.Prot = 0;
+	CmdPtr->CRamCmd.Id = 0;
+	CmdPtr->CRamCmd.Size = 0x2;
+	CmdPtr->CRamCmd.Burst = 0x1;
+	CmdPtr->CRamCmd.Lock = 0;
+	CmdPtr->CRamCmd.Length = 0;
+	CmdPtr->CRamCmd.MyDepend = 0;
+	CmdPtr->CRamCmd.OtherDepend = 0;
+	CmdPtr->CRamCmd.MasterRamIndex = 0;
+	CmdPtr->CRamCmd.Qos = 0;
+	CmdPtr->CRamCmd.User = 0;
+	CmdPtr->CRamCmd.Cache = 0;
+	CmdPtr->CRamCmd.ExpectedResp = 0x7;
+
+	/* Parameter RAM default command values */
+	CmdPtr->PRamCmd.AddrMode = 0;
+	CmdPtr->PRamCmd.IdMode = 0;
+	CmdPtr->PRamCmd.IntervalMode = 0;
+	CmdPtr->PRamCmd.OpCntl0 = 0;
+	CmdPtr->PRamCmd.OpCntl1 = 0;
+	CmdPtr->PRamCmd.OpCntl2 = 0;
+	CmdPtr->PRamCmd.Opcode = 0;
+}
+
diff --git a/XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_static_mode_example.c b/XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_static_mode_example.c
new file mode 100755
index 00000000..cdf79ea5
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/trafgen/examples/xtrafgen_static_mode_example.c
@@ -0,0 +1,278 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xtrafgen_static_mode_example.c
+ *
+ * This file demonstrates how to use the xtrafgen driver on the Xilinx AXI
+ * Traffic Generator core. The AXI Traffic Generator IP is designed to 
+ * generate AXI4 traffic which can be used to stress different modules/
+ * interconnect connected in the system.
+ *
+ * This example demonstrates  how to use the Static mode in the Axi Traffic 
+ * Genrator.In Static mode the core continously genrates fixed address and 
+ * fixed INCR type read and write transfers based on the burst length 
+ * configured.
+ * 
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.01a adk  03/09/13 First release
+ * 2.00a adk  16/09/13 Fixed CR:737291
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+
+/***************************** Include Files *********************************/
+#include "xtrafgen.h"
+#include "xparameters.h"
+#include "xil_exception.h"
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+#include "xuartns550_l.h"       /* to use uartns550 */
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define TRAFGEN_DEV_ID	XPAR_XTRAFGEN_0_DEVICE_ID
+#define BURST_LEN	255
+#define MEM_ADDR	XPAR_AXI_BRAM_CTRL_2_S_AXI_BASEADDR
+#define DATA 		0xc0015afe
+
+#undef DEBUG
+
+/************************** Function Prototypes ******************************/
+int XTrafGenStaticModeExample(XTrafGen *InstancePtr, u16 DeviceId);
+#ifdef XPAR_UARTNS550_0_BASEADDR
+static void Uart550_Setup(void);
+#endif
+
+/************************** Variable Definitions *****************************/
+/*
+ * Device instance definitions
+ */
+XTrafGen XTrafGenInstance;
+
+/*****************************************************************************/
+/**
+*
+* Main function
+*
+* This function is the main entry of the traffic generator test. 
+*
+* @param        None
+*
+* @return       - XST_SUCCESS if tests pass
+*               - XST_FAILURE if fails.
+*
+* @note         None.
+*
+******************************************************************************/
+int main()
+{
+	int Status;
+
+	xil_printf("--- Entering main() ---\n\r");
+
+	Status = XTrafGenStaticModeExample(&XTrafGenInstance, TRAFGEN_DEV_ID);
+	if (Status != XST_SUCCESS) {
+		xil_printf("TrafficGen Static mode Example Test Failed\n\r");
+		xil_printf("--- Exiting main() ---\n\r");
+		return XST_FAILURE;
+	}
+
+	xil_printf("TrafficGen Static mode Example Test passed\n\r");
+	xil_printf("--- Exiting main() ---\n\r");
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function demonstrates the usage Traffic Generator
+* It does the following:
+*       - Set up the output terminal if UART16550 is in the hardware build
+*       - Initialize the AXI Traffic Generator device
+*	- Fill's the Target memory with required data
+*	- Enable the Traffic genration
+*	- Disable the Traffic genration
+*       - Return test status and exit
+*
+* @param	InstancePtr is a pointer to the instance of the
+*		XTrafGen component.
+* @param	DeviceId is Device ID of the Axi Traffic Generator Device,
+*
+*
+* @param	InstancePtr is a pointer to the instance of the
+*			XTrafGen component.
+* @param	DeviceId is Device ID of the Axi Traffic Generator Device,
+*			typically XPAR_<TRAFGEN_instance>_DEVICE_ID value from
+*			xparameters.h.
+*
+* @return	-XST_SUCCESS to indicate success
+*		-XST_FAILURE to indicate failure
+*
+******************************************************************************/
+int XTrafGenStaticModeExample(XTrafGen *InstancePtr, u16 DeviceId)
+{
+
+	XTrafGen_Config *Config;
+	int Status = XST_SUCCESS;
+	u32 Count;
+	int *Addr = MEM_ADDR;
+	Count = 0;
+	
+        /* Initial setup for Uart16550 */
+#ifdef XPAR_UARTNS550_0_BASEADDR
+
+	Uart550_Setup();
+
+#endif
+
+	/* Initialize the Device Configuration Interface driver */
+	Config = XTrafGen_LookupConfig(DeviceId);
+	if (!Config) {
+		xil_printf("No config found for %d\r\n", DeviceId);
+		return XST_FAILURE;
+	}
+
+	/*
+	 * This is where the virtual address would be used, this example
+	 * uses physical address.
+	 */
+	Status = XTrafGen_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Initialization failed\n\r");
+		return Status;
+	}
+	
+	/* Check for the Static Mode */
+	if(InstancePtr->OperatingMode != XTG_MODE_STATIC) {
+		return XST_FAILURE;
+	}
+	
+	/* Fill the BRAM with the data */
+	for (Count = 0; Count < (5 * BURST_LEN); Count++) {
+		*(Addr + Count*4) = 0;
+		if(*(Addr + Count*4) != 0x00) {
+			xil_printf("ERROR: Memory Addr 0x%x = 0x%x \t"
+					"Expected = 0x00\n\r"
+					,(Addr+Count*4),(Addr+Count*4));
+			return XST_FAILURE;
+		}
+	}
+	
+	/* Set the Required Burst length */
+	XTrafGen_SetStaticBurstLen(InstancePtr, BURST_LEN);
+	
+	/* Disable the traffic genration */
+	XTrafGen_StaticDisable(InstancePtr);
+	
+	/* Check for the Static control DONE Bit resets */
+	XTrafGen_SetStaticTransferDone(InstancePtr);
+	Status = XTrafGen_IsStaticTransferDone(InstancePtr);
+	if (Status != TRUE) {
+		xil_printf("Static control reset failed failed\n\r");
+		return Status;
+	}
+	
+	/* Enable the traffic genration */
+	XTrafGen_StaticEnable(InstancePtr);
+	
+	/* Disable the traffic genration */
+	XTrafGen_StaticDisable(InstancePtr);
+	
+	/* Wait till data transmission completes */
+	do {
+		Status = XTrafGen_GetStaticTransferDone(InstancePtr);
+	}while(Status != XTG_STREAM_CNTL_TD_MASK);
+
+	
+	/* Check for the data 
+	 * Note:" 0xc0015afe " is the fixed data that has been given by the core
+	 * continuously when ATG is configured in STATIC mode and RUN.
+	 * There is no way to change this DATA in SW.
+	 */
+	for (Count = 0; Count < (BURST_LEN + 1); Count++) {
+		if(*(u32 *)(MEM_ADDR + Count*4) != DATA) {
+			xil_printf("ERROR: Memory Addr 0x%x = 0x%x \t"
+					"Expected = 0xc0015afe\n\r"
+					,(Addr + Count*4),(Addr + Count*4));
+			return XST_FAILURE;
+		}
+	}
+
+	for (Count = (BURST_LEN+1); Count < (BURST_LEN + 4); Count++) {
+		if(*(Addr + Count*4) != 0x00) {
+			xil_printf("ERROR: Memory Addr 0x%x = 0x%x \t"
+					"Expected = 0x00\n\r"
+					,(Addr + Count*4),(Addr + Count*4));
+			return XST_FAILURE;
+		}
+	}
+
+	return XST_SUCCESS;
+}
+
+
+#ifdef XPAR_UARTNS550_0_BASEADDR
+/*****************************************************************************/
+/*
+*
+* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
+*
+* @param        None
+*
+* @return       None
+*
+* @note         None.
+*
+******************************************************************************/
+static void Uart550_Setup(void)
+{
+
+	XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
+			XPAR_XUARTNS550_CLOCK_HZ, 9600);
+
+	XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
+			XUN_LCR_8_DATA_BITS);
+}
+#endif
+
diff --git a/XilinxProcessorIPLib/drivers/trafgen/src/Makefile b/XilinxProcessorIPLib/drivers/trafgen/src/Makefile
new file mode 100755
index 00000000..5c379b70
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/trafgen/src/Makefile
@@ -0,0 +1,28 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=xtrafgen.h xtrafgen_hw.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+
+libs:
+	echo "Compiling trafgen"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	 ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OUTS}
+
diff --git a/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.c b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.c
new file mode 100755
index 00000000..2ed810df
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.c
@@ -0,0 +1,688 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtrafgen.c
+*
+* This file implements AXI Traffic Generator device-wise initialization and 
+* control functions.
+* For more information on the implementation of this driver, see xtrafgen.h.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a srt  01/24/13 First release
+* 1.01a adk  03/09/13 Updated driver to Support Static and Streaming mode.
+* 2.00a adk  16/09/13 Fixed CR:737291
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xtrafgen.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Get Command Info pointer
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       Pointer to the Command Info structure
+*
+* @note         C-style signature:
+*               XTrafGen_CmdInfo *XTrafGen_GetCmdInfo(XTrafGen 
+*				*InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_GetCmdInfo(InstancePtr) \
+                        (&((InstancePtr)->CmdInfo))
+
+/************************** Function Prototypes ******************************/
+static void XTrafGen_PrepCmdWords(XTrafGen *InstancePtr,
+				XTrafGen_Cmd *CmdPtr, u32 *CmdWords);
+static void XTrafGen_PrepParamWord(XTrafGen *InstancePtr,
+                                XTrafGen_Cmd *CmdPtr, u32 *ParamWord);
+static int XTrafGen_ProgramCmdRam(XTrafGen *InstancePtr, u8 RdWrFlag);
+static int XTrafGen_ProgramParamRam(XTrafGen *InstancePtr, u8 RdWrFlag);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+ * This function initializes a AXI Traffic Generator device.  This function 
+ * must be called prior to using a AXI Traffic Generator Device.  Initializing
+ * a engine includes setting up the register base address, setting up the 
+ * instance data, and ensuring the hardware is in a quiescent state.
+ *
+ * @param       InstancePtr is a pointer to the Axi Traffic Generator instance 
+ *              to be worked on.
+ * @param	CfgPtr references the structure holding the hardware
+ *		configuration for the Axi Traffic Generator core to initialize.
+ * @param 	EffectiveAddr is the device base address in the virtual memory
+ *		address	space. The caller is responsible for keeping the
+ *		address mapping from EffectiveAddr to the device physical base
+ *		address unchanged once this function is invoked. Unexpected
+ *		errors may occur if the address mapping changes after this
+ *		function is called. If address translation is not used,
+ *		use Config->BaseAddress for this parameters, passing the
+ *		physical address instead.
+ *
+ * @return
+ *              - XST_SUCCESS for successful initialization
+ *              - XST_INVALID_PARAM if pointer to the configuration structure
+ *              is NULL
+ *
+ *****************************************************************************/
+int XTrafGen_CfgInitialize(XTrafGen * InstancePtr,
+			XTrafGen_Config *Config, u32 EffectiveAddress)
+{
+	u32 ConfigStatus;
+
+	InstancePtr->IsReady = 0;
+
+	if(!Config) {
+		return XST_INVALID_PARAM;
+	}
+
+	/* Setup the instance */
+	memset(InstancePtr, 0, sizeof(XTrafGen));
+	InstancePtr->Config.BaseAddress = EffectiveAddress;
+	InstancePtr->Config.DeviceId = Config->DeviceId;
+		
+	if((Config->BusType == 1) && (Config->Mode == 1 || 
+						Config->ModeType == 2)) {
+	
+		ConfigStatus = XTrafGen_ReadConfigStatus(InstancePtr);
+
+		/* Is it operating in Full Mode */
+		if (ConfigStatus & XTG_CFG_STS_MFULL_MASK) {
+			InstancePtr->OperatingMode = XTG_MODE_FULL;
+		}
+	
+		/* Is it operating in Basic Mode */
+		if (ConfigStatus & XTG_CFG_STS_MBASIC_MASK) {
+			InstancePtr->OperatingMode = XTG_MODE_BASIC;
+		}
+	
+		/* Master Width */
+		InstancePtr->MasterWidth = 
+				(ConfigStatus & XTG_CFG_STS_MWIDTH_MASK) >>
+					XTG_CFG_STS_MWIDTH_SHIFT;
+
+		/* Slave Width */
+		InstancePtr->SlaveWidth = 
+				(ConfigStatus & XTG_CFG_STS_SWIDTH_MASK) >>
+					XTG_CFG_STS_SWIDTH_SHIFT;
+
+		/* Initialize parameters */
+		InstancePtr->CmdInfo.LastWrValidIndex = -1;
+		InstancePtr->CmdInfo.LastRdValidIndex = -1;
+	}
+
+	/* Is it operating in Static Mode */	
+	if((Config->BusType == 1) && (Config->Mode == 3) && 
+			(Config->ModeType == 1 || Config->ModeType == 2)) {
+			InstancePtr->OperatingMode = XTG_MODE_STATIC;
+	}
+	
+	/* Is it operating in Streaming Mode */
+	if((Config->BusType == 3) && (Config->Mode == 1)) {
+			InstancePtr->OperatingMode = XTG_MODE_STREAMING;
+	}
+	
+	/* Is it operating in System-init Mode */
+	if(Config->BusType == 2) {
+			InstancePtr->OperatingMode = XTG_MODE_SYS_INIT;
+	}
+
+	/* Initialization is successful */
+	InstancePtr->IsReady = 1;
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* Add a command to the software list of commands.
+*
+* This function prepares the four Command Words and one Parameter Word from 
+* the Command structure passed from the user application.  It then adds to a 
+* list of commands (maintained in the software). Both CMDRAM and PARAMRAM are 
+* divided into two regions, one for reads and one for writes. Each region can
+* hold 256 commands with each entry containing four Command RAM words and one
+* Parameter RAM word.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param	CmdPtr is a pointer to Command structure.
+*
+* @return       
+*		- XST_SUCCESS if successful
+*		- XST_FAILURE if reached max number of command entries
+*
+*****************************************************************************/
+int XTrafGen_AddCommand(XTrafGen *InstancePtr, XTrafGen_Cmd *CmdPtr)
+{
+	XTrafGen_CmdInfo *CmdInfo;
+	u32 *Index;
+	u32 *CmdWords;
+	u32 *ParamWord;
+
+	/* Verify arguments */
+        Xil_AssertNonvoid(InstancePtr != NULL);
+        Xil_AssertNonvoid(CmdPtr != NULL);
+
+	CmdInfo = XTrafGen_GetCmdInfo(InstancePtr);
+
+	if ((CmdInfo->WrIndexEnd && CmdPtr->RdWrFlag) ||
+		(CmdInfo->RdIndexEnd && !CmdPtr->RdWrFlag)) {
+		return XST_FAILURE;
+	}
+
+	if (CmdPtr->RdWrFlag)
+		Index = &CmdInfo->WrIndex;
+	else
+		Index = &CmdInfo->RdIndex;
+
+	CmdWords = CmdInfo->CmdEntry[CmdPtr->RdWrFlag][*Index].CmdWords;
+	XTrafGen_PrepCmdWords(InstancePtr, CmdPtr, CmdWords);
+
+	ParamWord = &CmdInfo->CmdEntry[CmdPtr->RdWrFlag][*Index].ParamWord;
+	XTrafGen_PrepParamWord(InstancePtr, CmdPtr, ParamWord);
+
+	if (CmdPtr->CRamCmd.ValidCmd) { 
+		if (CmdPtr->RdWrFlag == XTG_WRITE)
+			CmdInfo->LastWrValidIndex = *Index;
+		else
+			CmdInfo->LastRdValidIndex = *Index;
+	}
+
+	if (*Index != MAX_NUM_ENTRIES - 1)
+		(*Index)++;
+	else {
+		if (CmdPtr->RdWrFlag == XTG_WRITE)
+			CmdInfo->WrIndexEnd = 1;
+		else
+			CmdInfo->RdIndexEnd = 1;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Get last Valid Command Index of Write/Read region
+*
+* The last valid command index is used to set 'my_depend' and 'other_depend'
+* fields of the Command RAM (Word 2).
+
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param	RdWrFlag specifies a Read or Write Region 
+*
+* @return       
+*		- Last Valid Command Index
+*
+*****************************************************************************/
+int XTrafGen_GetLastValidIndex(XTrafGen *InstancePtr, u32 RdWrFlag)
+{
+	XTrafGen_CmdInfo *CmdInfo;
+	u32 Index;
+				
+	/* Verify arguments */
+        Xil_AssertNonvoid(InstancePtr != NULL);
+
+	CmdInfo = XTrafGen_GetCmdInfo(InstancePtr);
+
+	if (RdWrFlag == XTG_WRITE)
+		Index = CmdInfo->LastWrValidIndex;
+	else
+		Index = CmdInfo->LastRdValidIndex;
+
+	return Index;
+} 
+
+/*****************************************************************************/
+/**
+* Write Commands to internal Command and Parameter RAMs
+*
+* This function writes all the prepared commands to hardware.
+
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       
+*		- XST_SUCCESS if successful
+*	        - XST_FAILURE if programming internal RAMs failed
+*
+*****************************************************************************/
+int XTrafGen_WriteCmdsToHw(XTrafGen *InstancePtr)
+{
+	u32 Index;
+	u32 Status;
+
+	/* Verify arguments */
+        Xil_AssertNonvoid(InstancePtr != NULL);
+
+	for (Index = 0; Index < NUM_BLOCKS; Index++) {
+		Status = XTrafGen_ProgramCmdRam(InstancePtr, Index);
+		if (Status != XST_SUCCESS) {
+			return XST_FAILURE;
+		}
+					
+		Status = XTrafGen_ProgramParamRam(InstancePtr, Index);
+		if (Status != XST_SUCCESS) {
+			return XST_FAILURE;
+		}
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Erase all Command Entry values
+*
+* This function erases all the 256 entries of both write and read regions with
+* each entry containing four command words and parameter word.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       
+*		- XST_SUCCESS if successful
+*	        - XST_FAILURE if programming internal RAMs failed
+*
+*****************************************************************************/
+int XTrafGen_EraseAllCommands(XTrafGen *InstancePtr)
+{
+	XTrafGen_CmdInfo *CmdInfo;
+	u32 Status;
+	u32 Index;
+
+	/* Verify arguments */
+        Xil_AssertNonvoid(InstancePtr != NULL);
+
+	CmdInfo = XTrafGen_GetCmdInfo(InstancePtr);
+
+	memset(CmdInfo->CmdEntry, 0, sizeof(CmdInfo->CmdEntry));
+
+	CmdInfo->WrIndex = CmdInfo->RdIndex = MAX_NUM_ENTRIES;
+
+	for (Index = 0; Index < NUM_BLOCKS; Index++) {
+		Status = XTrafGen_ProgramCmdRam(InstancePtr, Index);
+		if (Status != XST_SUCCESS) {
+			return XST_FAILURE;
+		}
+					
+		Status = XTrafGen_ProgramParamRam(InstancePtr, Index);
+		if (Status != XST_SUCCESS) {
+			return XST_FAILURE;
+		}
+	}
+
+	CmdInfo->WrIndex = CmdInfo->RdIndex = 0;
+	CmdInfo->WrIndexEnd = CmdInfo->RdIndexEnd = 0;
+	CmdInfo->LastWrValidIndex = CmdInfo->LastRdValidIndex = -1;
+	
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Write or Read Master RAM
+*
+* The MSTRAM has 8 KB of internal RAM used for the following:
+* - Take data from this RAM for write transactions
+* - Store data to this RAM for read transaction
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param	Offset is the offset value in Master RAM.
+* @param	Length is the size of data to write/read.
+* @param	RdWrFlag specifies whether to write or read
+* @param 	Data is the pointer to array which contains data to write or
+*		reads data into.
+* 
+*****************************************************************************/
+void XTrafGen_AccessMasterRam(XTrafGen *InstancePtr, u32 Offset, 
+					int Length, u8 RdWrFlag, u32 *Data)
+{
+	u32 Index = 0;
+		
+	/* Verify arguments */
+        Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((Offset + Length) < XTG_MASTER_RAM_SIZE);
+
+	while (Length > 0) {
+		if (RdWrFlag == XTG_WRITE) {
+			XTrafGen_WriteMasterRam(
+					InstancePtr->Config.BaseAddress, 
+					Offset, Data[Index]);
+		} else {
+			Data[Index] =
+				XTrafGen_ReadMasterRam(
+					InstancePtr->Config.BaseAddress, 
+					Offset);
+		}
+		Length -= 4;
+		Offset += 4;
+		Index++;
+	}
+}
+
+/*****************************************************************************/
+/**
+* Prepares all the four Command RAM Words
+*
+* The CMDRAM is divided into two 4 KB regions, one for reads and one for 
+* writes. Each region of CMDRAM can hold 256 commands each of 128 bits i.e.
+* Four command words each of size 32 bits. This function prepares these
+* command words from the user specified configuration.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param	CmdPtr is a pointer to Command structure.
+* @param	CmdWords is a pointer to an array of four command words.
+*
+*****************************************************************************/
+static void XTrafGen_PrepCmdWords(XTrafGen *InstancePtr,
+				XTrafGen_Cmd *CmdPtr, u32 *CmdWords)
+{
+	XTrafGen_CRamCmd *Cmd;
+
+	/* Verify arguments */
+        Xil_AssertVoid(InstancePtr != NULL);
+        Xil_AssertVoid(CmdPtr != NULL);
+        Xil_AssertVoid(CmdWords != NULL);
+
+	Cmd = &CmdPtr->CRamCmd;
+
+	/* Command Word 0 */
+        CmdWords[0] = Cmd->Address;
+
+	/* Command Word 1 */
+        CmdWords[1] = 0;
+        CmdWords[1] |= ((Cmd->Length & XTG_LEN_MASK) << XTG_LEN_SHIFT);
+        CmdWords[1] |= ((Cmd->Lock & XTG_LOCK_MASK) << XTG_LOCK_SHIFT);
+        CmdWords[1] |= ((Cmd->Burst & XTG_BURST_MASK) << XTG_BURST_SHIFT);
+        CmdWords[1] |= ((Cmd->Size & XTG_SIZE_MASK) << XTG_SIZE_SHIFT);
+        CmdWords[1] |= ((Cmd->Id & XTG_ID_MASK) << XTG_ID_SHIFT);
+        CmdWords[1] |= ((Cmd->Prot & XTG_PROT_MASK) << XTG_PROT_SHIFT);
+        CmdWords[1] |= ((Cmd->LastAddress & XTG_LAST_ADDR_MASK) <<
+					XTG_LAST_ADDR_SHIFT);
+        CmdWords[1] |= ((Cmd->ValidCmd & XTG_VALID_CMD_MASK) <<
+					XTG_VALID_CMD_SHIFT);
+
+	/* Command Word 2 */
+        CmdWords[2] = 0;
+        CmdWords[2] |= ((Cmd->MasterRamIndex & XTG_MSTRAM_INDEX_MASK) <<
+					XTG_MSTRAM_INDEX_SHIFT);
+        CmdWords[2] |= ((Cmd->OtherDepend & XTG_OTHER_DEPEND_MASK) <<
+					XTG_OTHER_DEPEND_SHIFT);
+        CmdWords[2] |= ((Cmd->MyDepend & XTG_MY_DEPEND_MASK) <<
+					XTG_MY_DEPEND_SHIFT);
+
+	/* Command Word 3 */
+        CmdWords[3] = 0;
+        CmdWords[3] |= ((Cmd->Qos & XTG_QOS_MASK) << XTG_QOS_SHIFT);
+        CmdWords[3] |= ((Cmd->User & XTG_USER_MASK) << XTG_USER_SHIFT);
+        CmdWords[3] |= ((Cmd->Cache & XTG_CACHE_MASK) << XTG_CACHE_SHIFT);
+        CmdWords[3] |= ((Cmd->ExpectedResp & XTG_EXPECTED_RESP_MASK) <<
+					XTG_EXPECTED_RESP_SHIFT);
+}
+
+/*****************************************************************************/
+/**
+* Prepares Parameter RAM Word
+*
+* The PARAMRAM extends the command programmability provided through command
+* RAM, by adding extra 32 bits to the decode of each command. This function
+* prepares this 32 bit Parameter RAM word.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param	CmdPtr is a pointer to Command structure.
+* @param	ParamWord is a pointer to an value of Parameter RAM word.
+*
+*****************************************************************************/
+static void XTrafGen_PrepParamWord(XTrafGen *InstancePtr,
+				XTrafGen_Cmd *CmdPtr, u32 *ParamWord)
+{
+	XTrafGen_PRamCmd *Cmd;
+
+	/* Verify arguments */
+        Xil_AssertVoid(InstancePtr != NULL);
+        Xil_AssertVoid(CmdPtr != NULL);
+        Xil_AssertVoid(ParamWord != NULL);
+
+	Cmd = &CmdPtr->PRamCmd;
+
+	*ParamWord = 0;
+	*ParamWord |= (Cmd->Opcode & XTG_PARAM_OP_MASK) << XTG_PARAM_OP_SHIFT;
+	*ParamWord |= (Cmd->AddrMode & XTG_PARAM_ADDRMODE_MASK) <<
+					XTG_PARAM_ADDRMODE_SHIFT;
+	*ParamWord |= (Cmd->IdMode & XTG_PARAM_IDMODE_MASK) <<
+					XTG_PARAM_IDMODE_SHIFT;
+	*ParamWord |= (Cmd->IntervalMode & XTG_PARAM_INTERVALMODE_MASK) <<
+					XTG_PARAM_INTERVALMODE_SHIFT;
+
+	switch (Cmd->Opcode) {
+	case XTG_PARAM_OP_RPT:
+	case XTG_PARAM_OP_DELAY:
+		*ParamWord |=  (Cmd->OpCntl0 & XTG_PARAM_COUNT_MASK) <<
+					XTG_PARAM_COUNT_SHIFT;
+		break;
+
+	case XTG_PARAM_OP_FIXEDRPT:
+    		*ParamWord |=  (Cmd->OpCntl0 & XTG_PARAM_ADDRRANGE_MASK) <<
+					XTG_PARAM_ADDRRANGE_SHIFT;
+    		*ParamWord |=  (Cmd->OpCntl1 & XTG_PARAM_DELAY_MASK) <<
+					XTG_PARAM_DELAY_SHIFT;
+    		*ParamWord |=  (Cmd->OpCntl2 & XTG_PARAM_DELAYRANGE_MASK) <<
+					XTG_PARAM_DELAYRANGE_SHIFT;
+		break;
+
+	case XTG_PARAM_OP_NOP:
+    		*ParamWord = 0;
+		break;
+	}
+}
+
+/*****************************************************************************/
+/**
+* Program Command RAM
+*
+* This function write the list of Command Words prepared by using 
+* *_AddCommand() to Command RAM till the last command entry added.
+
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param	RdWrFlag specifies Read or Write Region 
+*
+* @return       
+*		- XST_SUCCESS if successful
+*		- XST_FAILURE if no valid commands present
+*
+*****************************************************************************/
+static int XTrafGen_ProgramCmdRam(XTrafGen *InstancePtr, u8 RdWrFlag) 
+{
+	XTrafGen_CmdInfo *CmdInfo;
+	u32 *CmdWords;
+	u32 EntryIndex;
+	u32 Index;
+	u32 Offset;
+	u32 CmdWordIndex;
+	int ValidIndex;
+	
+	/* Verify arguments */
+        Xil_AssertNonvoid(InstancePtr != NULL);
+
+	CmdInfo = XTrafGen_GetCmdInfo(InstancePtr);
+
+	if (RdWrFlag == XTG_WRITE) {
+		EntryIndex = CmdInfo->WrIndex;
+		ValidIndex = CmdInfo->LastWrValidIndex;
+		Offset = XTG_CMD_RAM_BLOCK_SIZE;
+	} else {
+		EntryIndex = CmdInfo->RdIndex;
+		ValidIndex = CmdInfo->LastRdValidIndex;
+		Offset = 0;
+	}
+
+	for (Index = 0; Index < EntryIndex; Index++) {
+		if (ValidIndex != -1 ) {
+			CmdWords = CmdInfo->CmdEntry[RdWrFlag][Index].CmdWords;
+			for (CmdWordIndex = 0; CmdWordIndex < 4; CmdWordIndex++) {
+				XTrafGen_WriteCmdRam(
+					InstancePtr->Config.BaseAddress,
+					Offset, CmdWords[CmdWordIndex]);
+				Offset += 4;
+			}
+		} else {
+			return XST_FAILURE;
+		}
+	}
+ 
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Program Parameter RAM
+*
+* This function write the list of Parameter Words prepared by using 
+* *_AddCommand() to Parameter RAM till the last command entry added.
+
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param	RdWrFlag specifies Read or Write Region 
+*
+* @return       
+*		- XST_SUCCESS if successful
+*		- XST_FAILURE if no valid commands present
+*
+*****************************************************************************/
+static int XTrafGen_ProgramParamRam(XTrafGen *InstancePtr, u8 RdWrFlag)
+{
+	XTrafGen_CmdInfo *CmdInfo;
+	u32 *ParamWord;
+	u32 EntryIndex;
+	u32 Index;
+	u32 Offset;
+	int ValidIndex;
+	
+	/* Verify arguments */
+        Xil_AssertNonvoid(InstancePtr != NULL);
+
+	CmdInfo = XTrafGen_GetCmdInfo(InstancePtr);
+
+	if (RdWrFlag == XTG_WRITE) {
+		EntryIndex = CmdInfo->WrIndex;
+		ValidIndex = CmdInfo->LastWrValidIndex;
+		Offset = XTG_PRM_RAM_BLOCK_SIZE;
+	} else {
+		EntryIndex = CmdInfo->RdIndex;
+		ValidIndex = CmdInfo->LastRdValidIndex;
+		Offset = 0;
+	}
+
+	for (Index = 0; Index < EntryIndex; Index++) {
+		if (ValidIndex != -1 ) {
+			ParamWord =
+				&CmdInfo->CmdEntry[RdWrFlag][Index].ParamWord;
+			XTrafGen_WriteParamRam(
+				InstancePtr->Config.BaseAddress,
+				Offset, *ParamWord);
+			Offset += 4;
+		} else {
+			return XST_FAILURE;
+		}
+	}
+
+	return XST_SUCCESS;	
+}
+
+/*****************************************************************************/
+/**
+* Display Command Entry values
+*
+* This function prints all the 256 entries of both write and read regions with
+* each entry containing four command words and parameter word.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+*****************************************************************************/
+void XTrafGen_PrintCmds(XTrafGen *InstancePtr)
+{
+	XTrafGen_CmdInfo *CmdInfo;
+	int Index1;
+	int Index2; 
+
+	/* Verify arguments */
+        Xil_AssertVoid(InstancePtr != NULL);
+
+	CmdInfo = XTrafGen_GetCmdInfo(InstancePtr);
+
+	xil_printf("Commands configured for Write Block: \n\r");
+	for (Index1 = 0; Index1 < MAX_NUM_ENTRIES; Index1++) {
+		xil_printf("Cmd%d:\t", Index1);
+		for (Index2 = 0; Index2 < 4; Index2++) {
+			xil_printf("0x%08x, ",
+				CmdInfo->CmdEntry[1][Index1].CmdWords[Index2]);
+		}
+		xil_printf("0x%08x\n\r", CmdInfo->CmdEntry[1][Index1].ParamWord);
+	}
+			
+	xil_printf("Commands configured for Read Block: \n\r");
+	for (Index1 = 0; Index1 < MAX_NUM_ENTRIES; Index1++) {
+		xil_printf("Cmd%d:\t", Index1);
+		for (Index2 = 0; Index2 < 4; Index2++) {
+			xil_printf("0x%08x, ",
+				CmdInfo->CmdEntry[0][Index1].CmdWords[Index2]);
+		}
+		xil_printf("0x%08x\n\r", CmdInfo->CmdEntry[0][Index1].ParamWord);
+	}
+}
diff --git a/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.h b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.h
new file mode 100755
index 00000000..c24e55d2
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.h
@@ -0,0 +1,1199 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtrafgen.h
+*
+* This file contains the implementation of the AXI Traffic Generator driver.
+* User documentation for the driver functions is contained in this file in the 
+* form of comment blocks at the front of each function.
+*
+* The AXI Traffic Generator IP is designed to generate AXI4 traffic which can 
+* be used to stress different modules/interconnect connected in the system. 
+* Different configurable options allow the user to generate a wide variety of
+* traffic based on their requirements.  The core is broadly separated into a
+* master and slave block, each of which contains the write block and read 
+* block. Other support features are provided by the Control registers and
+* Internal RAMs.
+*
+* The commands to be issued by the AXI traffic generator are loaded in a 
+* 128-bit wide, 512 deep command RAM through AXI Slave interface. After the
+* core is enabled, control logic issues the write/read commands based on the
+* command settings programmed. The core updates the Status registers and
+* asserts interrupts on the completion of issuing programmed commands.
+*
+* The Axi Traffic Genrator has five different modes:
+*
+* - Advanced Mode: Advanced Mode allows full control over the traffic genration
+*   Control registers are provided to you to program the core to genrate 
+*   different AXI4 transactions.
+*
+* - Basic Mode: Basic Mode allows basic AXI4 traffic genration with less 
+*   resource overhead.
+*
+* - Static Mode: Static Mode allows you to genrate a simple AXI4 traffic with 
+*   very less resource and minimum processor intervention.In this Mode the core
+*   continuously genrates fixed address and fixed length INCR type read and 
+*   write transfers.
+*
+* - System Init Mode: System Init Mode is a special Mode where core provides
+*   only AXI4-Lite Master write interface.This mode can be used in a system
+*   without a processor to initialize the system peripherals with preconfigured
+*   values on system reset.
+*
+* - Streaming Mode: In Streaming Mode the core can be configured to generate 
+*   traffic based on the register configuration. 
+*
+* <b>Initialization & Configuration</b>
+*
+* The XTrafGen_Config structure is used by the driver to configure itself.
+* This configuration structure is typically created by the tool-chain based
+* on HW build properties.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+* - XTrafGen_LookupConfig(DeviceId) - Use the devide identifier to find the
+*   static configuration structure defined in xtrafgen_g.c. This is setup
+*   by the tools. For some operating systems the config structure will be
+*   initialized by the software and this call is not needed.
+*
+* - XTrafGen_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*   configuration structure provided by the caller. If running in a system
+*   with address translation, the provided virtual memory base address
+*   replaces the physical address present in the configuration structure.
+*
+* <b>Command Handling</b>
+*
+* AXI Traffic Generator core operates based on the commands programmed into
+* Command and Parameter RAMs. The CMDRAM and PARAMRAM is divided into two
+* regions: write and read. Each region can hold 256 entries.  Once the core
+* is enabled, the internal control logic issues write/read commands. To
+* handle command programming efficiently, we are maintaining a software 
+* list of commands. Following APIs are provided to handle this mechanism:
+*
+* - XTrafGen_AddCommand(): This function prepares the Command Words and 
+*   Parameter Word from the Command structure passed from the user 
+*   application.  It then adds to a software list of commands.
+*
+* - XTrafGen_WriteCmdsToHw(): This function writes the prepared list of 
+*   Command and Parameter Words prepared to CMDRAM and PARAMRAM.
+*
+* - XTrafGen_GetLastValidIndex(): This function gets last Valid Command
+*   Index of Write/Read region. The last valid command index is used to
+*   set 'my_depend' and 'other_depend' fields of the Command RAM. 
+*
+* - XTrafGen_EraseAllCommands(): This function clears the list of commands
+*   maintained in software and also updates the respective RAMs.
+*
+* - XTrafGen_PrintAllCmds(): This function displays the list of commands.  
+*
+* <b>Master RAM Handling</b>
+*
+* AXI Traffic Generator uses MSTRAM to 
+* - Take data from this RAM for write transactions
+* - Store data to this RAM for read transaction
+* User need to call this API to write/read to/from Master RAM,
+*
+* - XTrafGen_AccessMasterRam() - This function programs the Master RAM
+*   with the data which is used in master logic.  The amount of the data
+*   is limited by the size of master RAM.
+*
+* <b>Interrupts</b>
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions:
+* - Master Logic Completion Interrupt
+* - Error Interrupt (For Master and Slave Errors)
+*
+* The application can control which interrupts are enabled using these
+* functions:
+* - XTrafGen_EnableMasterCmpInterrupt()
+* - XTrafGen_MasterErrIntrEnable() 
+* - XTrafGen_SlaveErrIntrEnable()
+*
+* The interrupt system has to be set up and if the interrupts are enabled,
+* Traffic Generator notifies the software either about the completion or an 
+* error in transfer through interrupts.
+*
+* <b> Examples </b>
+*
+* We provided two examples to show how to use the driver API:
+* - One for interrupt mode (xtrafgen_interrupt_example.c)
+* - One for polling mode (xtrafgen_polling_example.c)
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b>RTOS Independence</b>
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied
+* by the layer above this driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a srt  01/24/13 First release
+* 1.01a adk  03/09/13 Updated Driver to Support Streaming and Static Mode
+* 2.00a adk  16/09/13 Fixed CR:737291
+* 2.01a adk  21/10/13 Fixed CR:740522 Updated the MasterRam offset as per latest 
+*		      IP.This driver is valid only for IP(v2.0) onwards. The 
+*		      XTG_MASTER_RAM_OFFSET has been changed from 
+*		      0x10000 to 0xc000.
+* 2.01a adk  15/11/13 Fixed CR:760808 added Macro's for the New bit fields added
+* 		      in the latest tarfgen IP(v2.0).
+* 3.0   adk  12/10/13 Updated as per the New Tcl API's
+* 3.1   adk  28/04/14 Fixed CR:782131 Incorrect mask value for the
+*		      loopenable bit.
+* </pre>
+******************************************************************************/
+
+#ifndef XTRAFGEN_H          /* prevent circular inclusions */
+#define XTRAFGEN_H          /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include <string.h>
+#include "xstatus.h"
+#include "xil_assert.h"
+#include "xtrafgen_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+#define MAX_NUM_ENTRIES	256	/**< Number of command entries per region */	
+#define NUM_BLOCKS	2	/**< Number of Read and write regions */
+
+/* Direction Flags */
+#define XTG_WRITE	1	/**< Write Direction Flag */	 
+#define XTG_READ	0	/**< Read Direction Flag */
+
+/* Operating Mode flags */	
+#define XTG_MODE_FULL		0	/**< Full Mode */
+#define XTG_MODE_BASIC		1	/**< Basic Mode */
+#define XTG_MODE_STATIC		2	/**< Static Mode */
+#define XTG_MODE_STREAMING	3	/**< Streaming Mode */
+#define XTG_MODE_SYS_INIT	4	/**< System Init Mode */
+
+/* Master Width Flags */
+#define XTG_MWIDTH_32	0	/**< Master Width - 32 */
+#define XTG_MWIDTH_64	1	/**< Master Width - 64 */
+	
+/* Slave Width Flags */
+#define XTG_SWIDTH_32	0	/**< Slave Width - 32 */
+#define XTG_SWIDTH_64	1	/**< Slave Width - 64 */
+	
+/* Internal RAM Sizes */
+#define XTG_PRM_RAM_BLOCK_SIZE	0x400	/**< PARAM Block Size (1KB) */	
+#define XTG_CMD_RAM_BLOCK_SIZE	0x1000 	/**< Cmd RAM Block Size (4KB) */
+#define XTG_PARAM_RAM_SIZE	0x800	/**< Parameter RAM (2KB) */
+#define XTG_COMMAND_RAM_SIZE	0x2000	/**< Command RAM (8KB) */
+#define XTG_MASTER_RAM_SIZE	0x2000	/**< Master RAM (8KB) */
+
+/************************** Type Definitions *****************************/
+
+/**
+ *  Command Ram word fields 
+ *
+ */
+typedef struct XTrafGen_CRamCmd
+{
+	u32 Address;		/**< Address Driven to a*_addr line */
+	u32 ValidCmd;		/**< Valid Command */
+	u32 LastAddress;	/**< Last address */
+	u32 Prot;		/**< Driven to a*_prot line */
+	u32 Id;			/**< Driven to a*_id line */
+	u32 Size;		/**< Driven to a*_size line */
+	u32 Burst;		/**< Driven to a*_burst line */
+	u32 Lock;		/** Driven to a*_lock line */	
+	u32 Length;		/**< Driven to a*_len line  */
+	u32 MyDepend;		/**< My depend command no */
+	u32 OtherDepend;	/**< Other depend Command no */
+	u32 MasterRamIndex;	/**< Master Ram Index */
+	u32 Qos;		/**< Driven to a*_qos line */
+	u32 User;		/**< Driven to a*_user line */
+	u32 Cache;		/**< Driven to a*_cache line */
+	u32 ExpectedResp;	/**< Expected response */
+} XTrafGen_CRamCmd;
+
+/**
+ *  Parameter Ram word fields 
+ *
+ */
+typedef struct XTrafGen_PRamCmd
+{
+	u32 OpCntl0;		/**< Control field 0 */ 	
+	u32 OpCntl1;		/**< Control field 1 */
+	u32 OpCntl2;		/**< Control field 2 */
+	u32 AddrMode;		/**< Address mode */
+	u32 IntervalMode;	/**< Interval mode */
+	u32 IdMode;		/**< Id mode */
+	u32 Opcode;		/**< Opcode */
+} XTrafGen_PRamCmd;
+
+/**
+ *  Command structure exposed to user
+ *
+ *  This structure should be updated by user with required
+ *  configuration
+ */ 
+typedef struct XTrafGen_Cmd
+{
+	XTrafGen_CRamCmd CRamCmd; /**< Command RAM struct */ 
+	XTrafGen_PRamCmd PRamCmd; /**< Param RAM struct */ 
+
+	u8 RdWrFlag;		/**< Write/Read region? */ 
+} XTrafGen_Cmd;
+
+/**
+ * Command Entry structure
+ *
+ * This structure denotes each entry of 256 commands.
+ */
+typedef struct XTrafGen_CmdEntry
+{
+	u32 CmdWords[4];	/**< Command Ram words */
+	u32 ParamWord;		/**< Parameter Ram word */
+} XTrafGen_CmdEntry;
+
+/**
+ * The configuration structure for Traffic Generator device
+ *
+ * This structure passes the hardware building information to the driver
+ */
+typedef struct XTrafGen_Config {
+	u16 DeviceId;		/**< Device Id */
+	u32 BaseAddress;	/**< Base Address */
+	u32 BusType;		/**< Atgmode */
+	u32 Mode;		/**< Atgmode_l2 */
+	u32 ModeType;		/**< Axismode */
+} XTrafGen_Config;
+
+/**
+ * Command Information Structure 
+ *
+ * This structure is maintained by the driver 
+ */
+typedef struct XTrafGen_CmdInfo {
+	u32 WrIndex;	/**< Write Region Command Index */
+	u32 RdIndex;	/**< Read Region Command Index */
+	
+	u8 WrIndexEnd;	/**< Write Index End */
+	u8 RdIndexEnd;	/**< Read Index End */
+
+	int LastWrValidIndex;	/**< Write Last Valid Command Index */ 
+	int LastRdValidIndex;	/**< Read Last Valid Command Index */
+
+	XTrafGen_CmdEntry CmdEntry[2][MAX_NUM_ENTRIES];
+				/**< Software array of Commands */
+} XTrafGen_CmdInfo;
+
+/**
+ * The XTrafGen driver instance data. An instance must be allocated for 
+ * each Traffic Generator device in use.
+ */
+typedef struct XTrafGen {
+	XTrafGen_Config Config; /**< Config Structure */
+
+	u8 OperatingMode;	/**< Operating mode */
+	u8 MasterWidth; 	/**< Master Width */
+	u8 SlaveWidth;		/**< Slave Width */
+
+	XTrafGen_CmdInfo CmdInfo; /**< Command Info structure */	
+	
+	int IsReady;	/* Device is initialized and ready */	
+} XTrafGen;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_ReadCoreRevision reads revision of core.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return	Core Revision Value
+*
+* @note         C-style signature:
+*               u8 XTrafGen_ReadCoreRevision(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_ReadCoreRevision(InstancePtr)	\
+	((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_MCNTL_OFFSET) & XTG_MCNTL_REV_MASK) >> \
+		XTG_MCNTL_REV_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_ReadIdWidth reads M_ID_WIDTH.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return	Value of M_ID_WIDTH
+*
+* @note         C-style signature:
+*               u8 XTrafGen_ReadIdWidth(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_ReadIdWidth(InstancePtr)	\
+	((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_MCNTL_OFFSET) & XTG_MCNTL_MSTID_MASK) >>	\
+		XTG_MCNTL_MSTID_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_StartMasterLogic starts traffic generator master logic.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return	None
+*
+* @note         C-style signature:
+*               void XTrafGen_StartMasterLogic(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_StartMasterLogic(InstancePtr)	\
+	XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_MCNTL_OFFSET,	\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+			XTG_MCNTL_OFFSET) | XTG_MCNTL_MSTEN_MASK))
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_IsMasterLogicDone checks for traffic generator master logic
+* completed bit.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return	TRUE if master logic completed.
+*		FALSE if master logic not completed.
+*
+* @note         C-style signature:
+*               u8 XTrafGen_IsMasterLogicDone(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_IsMasterLogicDone(InstancePtr)	\
+	((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_MCNTL_OFFSET) & XTG_MCNTL_MSTEN_MASK) ? \
+		FALSE : TRUE)
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_LoopEnable loops through the command set created using CMDRAM and 
+* PARAMRAM indefinitely in Advanced mode/Basic mode of ATG.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return	None
+*
+* @note         C-style signature:
+*               void XTrafGen_LoopEnable(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_LoopEnable(InstancePtr)	\
+	XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_MCNTL_OFFSET,	\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+			XTG_MCNTL_OFFSET) | XTG_MCNTL_LOOPEN_MASK))
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_LoopDisable Disbales the loop bit in Master control regiset in 
+* Advanced mode/Basic mode of ATG.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return	None
+*
+* @note         C-style signature:
+*               void XTrafGen_LoopDisable(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_LoopDisable(InstancePtr)	\
+	XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_MCNTL_OFFSET,	\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+			XTG_MCNTL_OFFSET) & ~XTG_MCNTL_LOOPEN_MASK))
+			
+/****************************************************************************/
+/**
+*
+* XTrafGen_WriteSlaveControlReg enables control bits of Slave Control
+* Register. This API will write the value passed from the user. 
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param	Value is the Slave Control Register value to set 
+*
+* @return	None
+*
+* @note         C-style signature:
+*               void XTrafGen_WriteSlaveControlReg(XTrafGen *InstancePtr, 
+*						u32 Value)
+*****************************************************************************/
+#define XTrafGen_WriteSlaveControlReg(InstancePtr, Value)	\
+	XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_SCNTL_OFFSET, Value)
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_CheckforMasterComplete checks for master complete.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return      	TRUE if master complete bit is set. 
+*               FALSE if master complete bit is not set.
+*
+* @note         C-style signature:
+*               u8 XTrafGen_CheckforMasterComplete(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_CheckforMasterComplete(InstancePtr)	\
+	((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_ERR_STS_OFFSET) & XTG_ERR_MSTCMP_MASK) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_ReadErrors read master and slave errors.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return	Both Master and Slave error value.
+*
+* @note         C-style signature:
+*               u32 XTrafGen_ReadErrors(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_ReadErrors(InstancePtr)	\
+	(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_ERR_STS_OFFSET) & XTG_ERR_ALL_ERR_MASK)
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_EnableMasterCmpInterrupt enables Master logic complete bit.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_EnableMasterCmpInterrupt(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_EnableMasterCmpInterrupt(InstancePtr)	\
+	XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_ERR_EN_OFFSET,	\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+			XTG_ERR_EN_OFFSET) |	\
+			XTG_ERR_MSTCMP_MASK))
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_ClearMasterCmpInterrupt clear Master logic complete interrupt bit.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               u8 XTrafGen_ClearMasterCmpInterrupt(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_ClearMasterCmpInterrupt(InstancePtr)	\
+	XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_ERR_STS_OFFSET,	\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+			XTG_ERR_STS_OFFSET) |	\
+			XTG_ERR_MSTCMP_MASK))
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_ClearErrors clear errors specified in <i>Mask</i>.
+* The corresponding error for each bit set to 1 in <i>Mask</i>, will be
+* enabled.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param        Mask contains a bit mask of the errors to clear. The mask
+*               can be formed using a set of bit wise or'd values from the
+*               definitions in xtrafgen_hw.h file.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_ClearErrors(XTrafGen *InstancePtr,
+*                                               u32 Mask)
+*
+*****************************************************************************/
+#define XTrafGen_ClearErrors(InstancePtr, Mask)	\
+	XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_ERR_STS_OFFSET,	\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+			XTG_ERR_STS_OFFSET) | Mask))
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_EnableErrors enable errors specified in <i>Mask</i>.  The 
+* corresponding error for each bit set to 1 in <i>Mask</i>, will be
+* enabled.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param        Mask contains a bit mask of the errors to enable. The mask
+*               can be formed using a set of bit wise or'd values from the
+*               definitions in xtrafgen_hw.h file.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_EnableErrors(XTrafGen *InstancePtr,
+*                                               u32 Mask)
+*
+*****************************************************************************/
+#define XTrafGen_EnableErrors(InstancePtr, Mask)	\
+	XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_ERR_EN_OFFSET,	\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+			XTG_ERR_EN_OFFSET) | Mask))
+
+/*****************************************************************************/
+/**
+*
+* XTrafGen_MasterErrIntrEnable enables Global Master error bit.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return	None
+*
+* @note         C-style signature:
+*               void XTrafGen_MasterErrIntrEnable(XTrafGen *InstancePtr)
+*
+******************************************************************************/
+#define XTrafGen_MasterErrIntrEnable(InstancePtr)                     \
+	XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,  \
+		XTG_MSTERR_INTR_OFFSET,	\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XTG_MSTERR_INTR_OFFSET) |	\
+			XTG_MSTERR_INTR_MINTREN_MASK)) 
+
+/*****************************************************************************/
+/**
+*
+* XTrafGen_MasterErrIntrDisable disables Global Master error bit.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return	None
+*
+* @note         C-style signature:
+*               void XTrafGen_MasterErrIntrDisable(XTrafGen *InstancePtr)
+*
+******************************************************************************/
+#define XTrafGen_MasterErrIntrDisable(InstancePtr)                     \
+	XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,  \
+		XTG_MSTERR_INTR_OFFSET,	\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XTG_MSTERR_INTR_OFFSET) &	\
+			~XTG_MSTERR_INTR_MINTREN_MASK)) 
+
+/*****************************************************************************/
+/**
+*
+* XTrafGen_SlaveErrIntrEnable enables Global Slave error bit.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return	None
+*
+* @note         C-style signature:
+*               void XTrafGen_SlaveErrIntrEnable(XTrafGen *InstancePtr)
+*
+******************************************************************************/
+#define XTrafGen_SlaveErrIntrEnable(InstancePtr)                     \
+	XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,  \
+		XTG_SCNTL_OFFSET, \
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XTG_SCNTL_OFFSET) | XTG_SCNTL_ERREN_MASK)) 
+
+/*****************************************************************************/
+/**
+*
+* XTrafGen_SlaveErrIntrDisable disables Global Slave error bit.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return	None
+*
+* @note         C-style signature:
+*               void XTrafGen_SlaveErrIntrDisable(XTrafGen *InstancePtr)
+*
+******************************************************************************/
+#define XTrafGen_SlaveErrIntrDisable(InstancePtr)	\
+	XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,  \
+		XTG_SCNTL_OFFSET, \
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XTG_SCNTL_OFFSET) & 	\
+			~XTG_SCNTL_ERREN_MASK)) 
+
+/*****************************************************************************/
+/**
+*
+* XTrafGen_ReadConfigStatus reads Config status register.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return	Config Status Register value
+*
+* @note         C-style signature:
+*               u32 XTrafGen_ReadConfigStatus(XTrafGen *InstancePtr)
+*
+******************************************************************************/
+#define XTrafGen_ReadConfigStatus(InstancePtr)                     \
+	(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,  \
+	XTG_CFG_STS_OFFSET))
+
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_StaticEnable enable the traffic genration when the core is 
+* configured Static Mode.
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_StaticEnable(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_StaticEnable(InstancePtr)				\
+	(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,		\
+		XTG_STATIC_CNTL_OFFSET,					\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		 XTG_STATIC_CNTL_OFFSET) | XTG_STATIC_CNTL_STEN_MASK)))	
+
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_StaticDisable disables the traffic genration on the Axi TrafGen 
+* when the core is configured in Static Mode
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_StaticDisable(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_StaticDisable(InstancePtr)				\
+	(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,		\
+		XTG_STATIC_CNTL_OFFSET,					\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		 XTG_STATIC_CNTL_OFFSET) & XTG_STATIC_CNTL_RESET_MASK)))
+				
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_StaticVersion returns the version value for the Axi TrafGen
+* When configured in Static Mode
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       Static version value.
+*
+* @note         C-style signature:
+*               u32 XTrafGen_StaticVersion(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_StaticVersion(InstancePtr)				\
+	((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,		\
+		XTG_STATIC_CNTL_OFFSET) & XTG_STATIC_CNTL_VER_MASK) >>  \
+		XTG_STATIC_CNTL_VER_SHIFT )
+				
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_SetStaticBurstLen Configures the Burst Length for AxiTrafGen
+* In Static Mode
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param	Value is the Burst length to set in the Static length register.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_SetStaticBurstLen(XTrafGen *InstancePtr, 
+*						u32 Value)
+*****************************************************************************/
+#define XTrafGen_SetStaticBurstLen(InstancePtr,Value)			\
+	(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_STATIC_LEN_OFFSET,Value))
+
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_GetStaticBurstLen Gets the Burst Length for AxiTrafGen in StaticMode
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       Burst length value.
+*
+* @note         C-style signature:
+*               u32 XTrafGen_GetStaticBurstLen(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_GetStaticBurstLen(InstancePtr)			\
+	(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_STATIC_LEN_OFFSET))
+
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_GetStaticTransferDone gets the state of Transfer done bit 
+* in Control register When the TraficGen is configured in Static Mode.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       Value of the Tranfer Done bit.
+*
+* @note         C-style signature:
+*               u32 XTrafGen_GetStaticTransferDone(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_GetStaticTransferDone(InstancePtr)			\
+	((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+			XTG_STATIC_CNTL_OFFSET)) & XTG_STATIC_CNTL_TD_MASK)
+
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_SetStaticTransferDone sets the Transfer done bit in Control register 
+* When AxiTrafGen is Configured in Static Mode.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_SetStaticTransferDone(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_SetStaticTransferDone(InstancePtr)   			\
+	XTrafGen_WriteReg(InstancePtr->Config.BaseAddress, 	        \
+		XTG_STATIC_CNTL_OFFSET, 				\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_STATIC_CNTL_OFFSET) | XTG_STATIC_CNTL_TD_MASK))
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_IsStaticTransferDone checks for reset value  When Static Traffic genration 
+* Completed by reading Control Register.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return	TRUE if reset Success full
+*		FALSE if failed to reset
+*
+* @note         C-style signature:
+*               u8 XTrafGen_IsStaticTransferDone(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_IsStaticTransferDone(InstancePtr)	\
+	(((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_STATIC_CNTL_OFFSET) & XTG_STATIC_CNTL_TD_MASK) == \
+		XTG_STATIC_CNTL_RESET_MASK) ? \
+		TRUE : FALSE)	
+	
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_StreamEnable enable the traffic genration on the Axi TrafGen 
+* When the core is configured in Streaming Mode
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_StreamEnable(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_StreamEnable(InstancePtr) 				\
+	(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,		\
+		XTG_STREAM_CNTL_OFFSET,					\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_STREAM_CNTL_OFFSET) | XTG_STREAM_CNTL_STEN_MASK)))
+
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_StreamDisable Disable the traffic genration on the Axi TrafGen 
+* When core is configured in Streaming Mode
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_StreamDisable(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_StreamDisable(InstancePtr)			\
+	(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_STREAM_CNTL_OFFSET,				\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_STREAM_CNTL_OFFSET) & XTG_STREAM_CNTL_RESET_MASK)))
+
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_StreamVersion returns the version value for the Axi TrafGen 
+* When configured in  Streaming Mode
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       Streaming Version Value.
+*
+* @note         C-style signature:
+*               u8 XTrafGen_StreamVersion(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_StreamVersion(InstancePtr)		\
+	((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_STREAM_CNTL_OFFSET) & XTG_STREAM_CNTL_VER_MASK) \
+		>> XTG_STREAM_CNTL_VER_SHIFT )
+	
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_SetStreamingTransLen Configures the length of transaction for 
+* AxiTrafGen in Streaming Mode.
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param	Value is the transfer length to set in the transfer length 
+*		Register.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_SetStreamingTransLen(XTrafGen *InstancePtr, 
+*						u32 Value)
+*****************************************************************************/
+#define XTrafGen_SetStreamingTransLen(InstancePtr,Value)		\
+	(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,		\
+		XTG_STREAM_TL_OFFSET,					\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_STREAM_TL_OFFSET) | Value)))
+
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_GetStreamingTransLen Gets the length of transaction for 
+* AxiTrafGen in Streaming Mode
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       Transfer Length value.
+*
+* @note         C-style signature:
+*               u16 XTrafGen_GetStreamingTransLen(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_GetStreamingTransLen(InstancePtr)		\
+	(XTrafGen_ReadReg(InstancePtr->Config.BaseAddress,	\
+		XTG_STREAM_TL_OFFSET)& XTG_STREAM_TL_TLEN_MASK)
+
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_GetStreamingTransCnt Gets the transfer count for AxiTrafGen in 
+* Streaming Mode
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       Transfer Count value.
+*
+* @note         C-style signature:
+*               u16 XTrafGen_GetStreamingTransCnt(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_GetStreamingTransCnt(InstancePtr)		\
+	((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
+		XTG_STREAM_TL_OFFSET ) & XTG_STREAM_TL_TCNT_MASK) \
+		>> XTG_STREAM_TL_TCNT_SHIFT)
+
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_SetStreamingRandomLen Configures the random transaction length 
+* for AxiTrafGen in Streaming Mode.
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param 	Value is the random length that's need to be Configure in the
+*		Streaming Config register.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_SetStreamingRandomLen(XTrafGen *InstancePtr, 
+*						u32 Value)
+*
+*****************************************************************************/
+#define XTrafGen_SetStreamingRandomLen(InstancePtr,Value)		\
+	(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,		\
+		XTG_STREAM_CFG_OFFSET,					\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_STREAM_CFG_OFFSET) | Value)))
+	
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_GetStreamingProgDelay Gets the Programmable Delay for AxiTrafGen in 
+* Streaming Mode.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       Propagation Delay Value
+*
+* @note         C-style signature:
+*               u16 XTrafGen_GetProgDelay(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_GetStreamingProgDelay(InstancePtr)	\
+	((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
+		XTG_STREAM_TL_OFFSET ) \
+		& XTG_STREAM_CFG_PDLY_MASK) >> XTG_STREAM_CFG_PDLY_SHIFT)
+
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_SetStreamingTransCnt Configures the transfer count for 
+* AxiTrafGen in Streaming Mode.
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param	Value is the transfer length that needs to be configured in
+*		Transfer length register.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_SetStreamingTransCnt(XTrafGen *InstancePtr, 
+*						u32 Value)
+*
+*****************************************************************************/
+#define XTrafGen_SetStreamingTransCnt(InstancePtr, Value) \
+	(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_STREAM_TL_OFFSET,	\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		 XTG_STREAM_TL_OFFSET) |((Value << XTG_STREAM_TL_TCNT_SHIFT) \
+		 & XTG_STREAM_TL_TCNT_MASK))))
+		
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_SetStreamingProgDelay Configures the Programmable Delay for 
+* AxiTrafGen in Streaming Mode.
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param	Value is the value that's need to be configure in the Stream
+*		Config Register.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_SetStreamingProgDelay(XTrafGen *InstancePtr, 
+*						u32 Value)
+*
+*****************************************************************************/
+#define XTrafGen_SetStreamingProgDelay(InstancePtr, Value) \
+	(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_STREAM_CFG_OFFSET,  \
+	        (XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
+		 XTG_STREAM_CFG_OFFSET)|(Value << XTG_STREAM_CFG_PDLY_SHIFT)) \
+		 & XTG_STREAM_CFG_PDLY_MASK))
+
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_SetStreamingTdestPort Configures the Value to drive on TDEST port 
+* for Axi TrafGen in Streaming Mode.
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+* @param	Value is the Port value that's need to be set.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_SetStreamingTdestPort(XTrafGen *InstancePtr, 
+*						u8 Value)
+*
+*****************************************************************************/
+#define XTrafGen_SetStreamingTdestPort(InstancePtr, Value) \
+	(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,  \
+		XTG_STREAM_CFG_OFFSET,  \
+	        (XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
+		XTG_STREAM_CFG_OFFSET)|(Value << XTG_STREAM_CFG_TDEST_SHIFT)) \
+		& XTG_STREAM_CFG_TDEST_MASK))
+		
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_SetTransferDone sets the Transfer done bit in Control register 
+* When AxiTrafGen is Configured in  Streaming Mode.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_SetStreamingTransferDone(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_SetStreamingTransferDone(InstancePtr)   \
+	XTrafGen_WriteReg(InstancePtr->Config.BaseAddress,   \
+		XTG_STREAM_CNTL_OFFSET, 			\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
+		XTG_STREAM_CNTL_OFFSET) | XTG_STREAM_CNTL_TD_MASK))
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_IsStreamingTransferDone checks for reset value  When Streaming Traffic 
+* genration is Completed by reading Stream Control Register.
+*
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return	TRUE if reset Success full
+*		FALSE if failed to reset
+*
+* @note         C-style signature:
+*               u8 XTrafGen_IsStreamingTransferDone(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_IsStreamingTransferDone(InstancePtr)	\
+	(((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_STREAM_CNTL_OFFSET) & XTG_STREAM_CNTL_TD_MASK) == \
+		XTG_STREAM_CNTL_RESET_MASK) ? \
+		TRUE : FALSE)	
+		
+/*****************************************************************************/
+/**
+* 
+* XTrafGen_ResetStreamingRandomLen resets the random transaction length 
+* for AxiTrafGen in Streaming Mode.
+* @param        InstancePtr is a pointer to the Axi TrafGen instance to be
+*               worked on.
+*
+* @return       None.
+*
+* @note         C-style signature:
+*               void XTrafGen_ResetStreamingRandomLen(XTrafGen *InstancePtr)
+*
+*****************************************************************************/
+#define XTrafGen_ResetStreamingRandomLen(InstancePtr)		\
+	(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress,		\
+		XTG_STREAM_CFG_OFFSET,					\
+		(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		XTG_STREAM_CFG_OFFSET) & ~XTG_STREAM_CFG_RANDL_MASK)))
+			
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization and control functions in xtrafgen.c
+ */
+int XTrafGen_CfgInitialize(XTrafGen * InstancePtr,
+                             XTrafGen_Config *Config, u32 EffectiveAddress);
+XTrafGen_Config *XTrafGen_LookupConfig(u32 DeviceId);
+int XTrafGen_AddCommand(XTrafGen *InstancePtr, XTrafGen_Cmd *CmdPtr);
+int XTrafGen_GetLastValidIndex(XTrafGen *InstancePtr, u32 RdWrFlag);
+int XTrafGen_WriteCmdsToHw(XTrafGen *InstancePtr);
+void XTrafGen_AccessMasterRam(XTrafGen *InstancePtr, u32 Offset,
+                                     int Length, u8 Write, u32 *Data);
+void XTrafGen_PrintCmds(XTrafGen *InstancePtr);
+int XTrafGen_EraseAllCommands(XTrafGen *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_g.c b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_g.c
new file mode 100755
index 00000000..a8370e61
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_g.c
@@ -0,0 +1,70 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtrafgen_g.c
+*
+* Provide a template for user to define their own hardware settings.
+*
+* If using XPS, this file will be automatically generated.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a srt  01/24/13 First release
+* 1.01a adk  03/09/13 Updated driver to Support Static and Streaming mode.
+* 2.00a adk  16/09/13 Fixed CR:737291
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xtrafgen.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+XTrafGen_Config XTrafGen_ConfigTable[] =
+{
+	{
+		XPAR_XTRAFGEN_0_DEVICE_ID,
+		XPAR_XTRAFGEN_0_BASEADDR,
+		XPAR_XTRAFGEN_0_ATG_MODE,
+		XPAR_XTRAFGEN_0_ATG_MODE_L2,
+		XPAR_XTRAFGEN_0_AXIS_MODE
+	}
+};
diff --git a/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_hw.h b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_hw.h
new file mode 100755
index 00000000..b89be6df
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_hw.h
@@ -0,0 +1,520 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtrafgen_hw.h
+*
+* This header file contains identifiers and macros that can be used to access
+* the Axi Traffic Generator device. The driver APIs/functions are defined in
+* xtrafgen.h.
+*
+* @note
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a srt  1/12/13  First release
+* 1.01a adk  03/09/13 Updated Driver to Support Static and Streaming Mode
+* 2.00a adk  16/09/13 Fixed CR:737291
+* 2.01a adk  21/10/13 Fixed CR:740522 Updated the MasterRam offset as per latest 
+*		      IP.This driver is valid only for IP(v2.0) onwards. The 
+*		      XTG_MASTER_RAM_OFFSET has been changed from 
+*		      0x10000 to 0xc000.
+* 2.01a adk  15/11/13 Fixed CR:760808 Added Mask for the New bit field added
+*		      (XTG_MCNTL_LOOPEN_MASK).
+* 3.1   adk  28/04/14 Fixed CR:782131 Incorrect Mask value for the loopenable
+*		      bit.
+*
+* </pre>
+
+******************************************************************************/
+#ifndef XTRAFGEN_HW_H		/* prevent circular inclusions */
+#define XTRAFGEN_HW_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit.
+ */
+/** @name Device registers
+ *  @{
+ */
+#define XTG_MCNTL_OFFSET	0x00	/**< Master Control */
+#define XTG_SCNTL_OFFSET	0x04	/**< Slave Control */
+#define XTG_ERR_STS_OFFSET	0x08	/**< Error Status  */
+#define XTG_ERR_EN_OFFSET	0x0C	/**< Error Enable */
+#define XTG_MSTERR_INTR_OFFSET	0x10	/**< Master Err Interrupt Enable */
+#define XTG_CFG_STS_OFFSET	0x14	/**< Config Status */
+#define XTG_STREAM_CNTL_OFFSET	0x30	/**< Streaming Control */
+#define XTG_STREAM_CFG_OFFSET	0x34    /**< Streaming Config */
+#define XTG_STREAM_TL_OFFSET	0x38    /**< Streaming Transfer Length */
+ 
+ /** 
+  *  Static Mode Register Descrptions 
+  */
+ #define XTG_STATIC_CNTL_OFFSET	0x60	/**< Static Control */
+ #define XTG_STATIC_LEN_OFFSET	0x64	/**< Static Length */
+
+/*@}*/
+
+/** @name Internal RAM Offsets
+ * @{
+ */
+#define XTG_PARAM_RAM_OFFSET	0x1000	/**< Parameter RAM Offset */
+#define XTG_COMMAND_RAM_OFFSET	0x8000	/**< Command RAM Offset */
+#define XTG_MASTER_RAM_OFFSET	0xC000	/**< Master RAM Offset */
+
+/*@}*/
+
+/** @name Master Control Register bit definitions.
+ *  These bits are associated with the XTG_MCNTL_OFFSET register.
+ * @{
+ */
+#define XTG_MCNTL_REV_MASK	0xFF000000	/**< Core Revision Mask */
+#define XTG_MCNTL_MSTID_MASK	0x00E00000	/**< M_ID_WIDTH Mask */
+#define XTG_MCNTL_MSTEN_MASK	0x00100000	/**< Master Logic Enable
+						Mask */
+#define XTG_MCNTL_LOOPEN_MASK   0x00080000	/**< Loop enable Mask */
+
+#define XTG_MCNTL_REV_SHIFT	24		/**< Core Rev shift */
+#define XTG_MCNTL_MSTID_SHIFT	21		/**< M_ID_WIDTH shift */
+
+/*@}*/
+
+/** @name Slave Control Register bit definitions.
+ *  These bits are associated with the XTG_SCNTL_OFFSET register.
+ * @{
+ */
+#define XTG_SCNTL_BLKRD_MASK	0x00080000	/**< Enable  
+						Block Read */	
+#define XTG_SCNTL_DISEXCL_MASK	0x00040000	/**< Disable  
+						Exclusive Access */	
+#define XTG_SCNTL_WORDR_MASK	0x00020000	/**< Write Response  
+						Order Enable */	
+#define XTG_SCNTL_RORDR_MASK	0x00010000	/**< Read Response  
+						Order Enable */	
+#define XTG_SCNTL_ERREN_MASK	0x00008000	/**< Slv Error 
+						Interrupt Enable */	
+
+/*@}*/
+
+/** @name Error bitmasks
+ *  These bits are shared with the XTG_ERR_STS_OFFSET and 
+ *  XTG_ERR_EN_OFFSET register.
+ * @{
+ */
+#define XTG_ERR_ALL_MSTERR_MASK	0x001F0000	/**< Master
+						Errors Mask */
+#define XTG_ERR_ALL_SLVERR_MASK	0x00000003	/**< Slave
+						Errors Mask */
+#define XTG_ERR_ALL_ERR_MASK	0x001F0003	/**< All
+						Errors Mask */
+
+#define XTG_ERR_MSTCMP_MASK	0x80000000	/**< Master
+						Complete Mask */
+#define XTG_ERR_RIDER_MASK	0x00100000 	/**< Master 
+						Invalid 
+						RVALID Mask */
+#define XTG_ERR_WIDER_MASK	0x00080000	/**< Master
+						Invalid
+						BVALID Mask */
+#define XTG_ERR_WRSPER_MASK	0x00040000	/**< MW
+						Invalid
+						RESP Mask */
+#define XTG_ERR_RERRSP_MASK	0x00020000	/**< MR
+						Invalid
+						RESP Mask */
+#define XTG_ERR_RLENER_MASK	0x00010000	/**< Master
+						Read Length 
+						Mask */
+#define XTG_ERR_SWSTRB_MASK	0x00000002	/**< Slave
+						WSTRB Illegal
+						Mask */
+#define XTG_ERR_SWLENER_MASK	0x00000001	/**< Slave
+						Read Length
+						Mask */
+
+/*@}*/
+
+/*@}*/
+
+/** @name Master Error Interrupt Enable Register bit definitions.
+ *  These bits are associated with the XTG_MSTERR_INTR_OFFSET register.
+ * @{
+ */
+#define XTG_MSTERR_INTR_MINTREN_MASK	0x00008000	/**< Master Err 
+							 Interrupt Enable */
+
+/*@}*/
+
+/** @name Config Status Register bit definitions.
+ *  These bits are associated with the XTG_CFG_STS_OFFSET register.
+ * @{
+ */
+#define XTG_CFG_STS_MWIDTH_SHIFT	28		/**< Master Width Shift */
+#define XTG_CFG_STS_MWIDTH_MASK		0x70000000	/**< Master Width Mask */
+
+#define XTG_CFG_STS_SWIDTH_SHIFT	25		/**< Slave Width Shift */
+#define XTG_CFG_STS_SWIDTH_MASK		0x0E000000	/**< Slave Width Mask */
+
+#define XTG_CFG_STS_MFULL_MASK		0x01000000	/**< Full Mode */
+#define XTG_CFG_STS_MBASIC_MASK		0x00800000	/**< Basic Mode */
+
+/*@}*/
+
+/*@}*/
+/** @name Streaming Control Register bit definitions.
+ *  These bits are associated with the XTG_STR_CFG_OFFSET register.
+ * @{
+ */
+#define XTG_STREAM_CNTL_VER_SHIFT		24		/**< Version Shift */
+#define XTG_STREAM_CNTL_VER_MASK		0xFE000000	/**< Version Mask */
+
+#define XTG_STREAM_CNTL_TD_SHIFT		1		/**< Transfer Done Shift */
+#define XTG_STREAM_CNTL_TD_MASK			0x00000002	/**< Transfer Done Mask */
+ 
+#define XTG_STREAM_CNTL_STEN_MASK		0x00000001	/**< Streaming Enable Mask */
+#define XTG_STREAM_CNTL_RESET_MASK		0x00000000	/**< Streaming Disable Mask */
+/*@}*/
+
+/*@}*/
+/** @name Streaming Config Register bit definitions.
+ *  These bits are associated with the XTG_STR_CFG_OFFSET register.
+ * @{
+ */
+ #define XTG_STREAM_CFG_PDLY_SHIFT		16	 	/**< Programmable Delay Shift */
+ #define XTG_STREAM_CFG_PDLY_MASK		0xFFFF0000	/**< Programmable Delay Mask */
+ 
+ #define XTG_STREAM_CFG_TDEST_SHIFT		8		/**< TDEST PORT Shift */
+ #define XTG_STREAM_CFG_TDEST_MASK		0x0000FF00	/**< TDEST PORT Mask */
+ 
+ #define XTG_STREAM_CFG_RANDLY_SHIFT		1		/**< Random Delay Shift */
+ #define XTG_STREAM_CFG_RANDLY_MASK		0x00000002	/**< Random Delay Mask */
+ 
+ #define XTG_STREAM_CFG_RANDL_MASK		0x00000001	/**< Random Length Mask */
+ /*@}*/
+ 
+ 
+ /*@}*/
+/** @name Streaming Transfer Length Register bit definitions.
+ *  These bits are associated with the XTG_STR_TL_OFFSET register.
+ * @{
+ */
+ #define XTG_STREAM_TL_TCNT_SHIFT		16	 	/**< Transfer Count Shift */
+ #define XTG_STREAM_TL_TCNT_MASK		0xFFFF0000	/**< Transfer Count Mask */
+ 
+ #define XTG_STREAM_TL_TLEN_MASK		0x0000FFFF	/**< Transfer Length Mask */
+ /*@}*/
+ 
+  /*@}*/
+/** @name Static Control Register bit definitions.
+ *  These bits are associated with the XTG_STATIC_CNTL_OFFSET register.
+ * @{
+ */
+#define XTG_STATIC_CNTL_VER_SHIFT		24		/**< Version Shift */
+#define XTG_STATIC_CNTL_VER_MASK		0xFE000000	/**< Version Mask */
+
+#define XTG_STATIC_CNTL_TD_SHIFT		1		/**< Transfer Done Shift */
+#define XTG_STATIC_CNTL_TD_MASK			0x00000002	/**< Transfer Done Mask */
+ 
+#define XTG_STATIC_CNTL_STEN_MASK		0x00000001	/**< Static enable Mask */
+#define XTG_STATIC_CNTL_RESET_MASK		0x00000000	/**< Static Disable Mask */
+ /*@}*/
+ 
+  /*@}*/
+/** @name Static Length Register bit definitions.
+ *  These bits are associated with the XTG_STATIC_LEN_OFFSET register.
+ * @{
+ */
+ #define XTG_STATIC_LEN_BLEN_MASK		0x000000FF	 /**< Burst length Mask */
+ /*@}*/
+
+/** @name Axi Traffic Generator Command Entry field mask/shifts
+ *  @{
+ */
+#define XTG_ADDR_MASK		0xFFFFFFFF	/**< Driven to a*_addr line */
+#define XTG_LEN_MASK		0xFF		/**< Driven to a*_len line  */
+#define XTG_LOCK_MASK		0x1		/**< Driven to a*_lock line */
+#define XTG_BURST_MASK		0x3		/**< Driven to a*_burst line */
+#define XTG_SIZE_MASK		0x7		/**< Driven to a*_size line */
+#define XTG_ID_MASK		0x1F		/**< Driven to a*_id line */
+#define XTG_PROT_MASK		0x7		/**< Driven to a*_prot line */
+#define XTG_LAST_ADDR_MASK	0x7		/**< Last address */
+#define XTG_VALID_CMD_MASK	0x1		/**< Valid Command */	
+#define XTG_MSTRAM_INDEX_MASK	0x1FFF		/**< Master RAM Index */
+#define XTG_OTHER_DEPEND_MASK	0x1FF		/**< Other depend Command no */
+#define XTG_MY_DEPEND_MASK	0x1FF		/**< My depend command no */
+#define XTG_QOS_MASK		0xF		/**< Driven to a*_qos line */
+#define XTG_USER_MASK		0xFF		/**< Driven to a*_user line */
+#define XTG_CACHE_MASK		0xF		/**< Driven to a*_cache line */
+#define XTG_EXPECTED_RESP_MASK	0x7		/**< Expected response */
+
+#define XTG_ADDR_SHIFT		0		/**< Driven to a*_addr line */
+#define XTG_LEN_SHIFT		0		/**< Driven to a*_len line  */
+#define XTG_LOCK_SHIFT		8		/**< Driven to a*_lock line */
+#define XTG_BURST_SHIFT		10		/**< Driven to a*_burst line */
+#define XTG_SIZE_SHIFT		12		/**< Driven to a*_size line */
+#define XTG_ID_SHIFT		15		/**< Driven to a*_id line */
+#define XTG_PROT_SHIFT		21		/**< Driven to a*_prot line */
+#define XTG_LAST_ADDR_SHIFT	28		/**< Last address */
+#define XTG_VALID_CMD_SHIFT	31		/**< Valid Command */
+#define XTG_MSTRAM_INDEX_SHIFT	0		/**< Master RAM Index */
+#define XTG_OTHER_DEPEND_SHIFT	13		/**< Other depend cmd num */
+#define XTG_MY_DEPEND_SHIFT	22		/**< My depend cmd num */
+#define XTG_QOS_SHIFT		16		/**< Driven to a*_qos line */
+#define XTG_USER_SHIFT		5		/**< Driven to a*_user line */
+#define XTG_CACHE_SHIFT		4		/**< Driven to a*_cache line */
+#define XTG_EXPECTED_RESP_SHIFT	0		/**< Expected response */
+
+/*@}*/
+
+
+/** @name Axi Traffic Generator Parameter Entry field mask/shifts
+ *  @{
+ */
+/* Parameter Entry field shift values */
+#define XTG_PARAM_ADDRMODE_SHIFT	24	/**< Address mode */
+#define XTG_PARAM_INTERVALMODE_SHIFT	26	/**< Interval mode */
+#define XTG_PARAM_IDMODE_SHIFT		28	/**< Id mode */
+#define XTG_PARAM_OP_SHIFT		29	/**< Opcode */
+
+/* PARAM RAM Opcode shift values */
+#define XTG_PARAM_COUNT_SHIFT		0	/**< Repeat/Delay count */
+#define XTG_PARAM_DELAYRANGE_SHIFT	0	/**< Delay Range */
+#define XTG_PARAM_DELAY_SHIFT		8	/**< FIXED RPT Delay count */
+#define XTG_PARAM_ADDRRANGE_SHIFT	20	/**< Address Range */
+
+/* Parameter Entry field mask values */
+#define XTG_PARAM_ADDRMODE_MASK		0x3	/**< Address mode */	
+#define XTG_PARAM_INTERVALMODE_MASK	0x3	/**< Interval mode */
+#define XTG_PARAM_IDMODE_MASK		0x1	/**< Id mode */
+#define XTG_PARAM_OP_MASK		0x7	/**< Opcode */
+
+/* PARAM RAM Opcode mask values */
+#define XTG_PARAM_COUNT_MASK		0xFFFFFF/**< Repeat/Delay count */
+#define XTG_PARAM_DELAYRANGE_MASK	0xFF	/**< Delay Range */ 
+#define XTG_PARAM_DELAY_MASK		0xFFF	/**< FIXED RPT Delay count */
+#define XTG_PARAM_ADDRRANGE_MASK	0xF	/**< Address Range */
+
+/* PARAM RAM Opcode values */
+#define XTG_PARAM_OP_NOP		0	/**< NOP mode */
+#define XTG_PARAM_OP_RPT		1	/**< Repeat mode */
+#define XTG_PARAM_OP_DELAY		2 	/**< Delay mode */
+#define XTG_PARAM_OP_FIXEDRPT		3	/**< Fixed Repeat Delay */ 
+
+/* PARAM RAM Address mode values */
+#define XTG_PARAM_OP_ADDRMODE_CONST	0	/**< Constant Addr mode */
+#define XTG_PARAM_OP_ADDRMODE_INCR	1	/**< Increment Addr mode */
+#define XTG_PARAM_OP_ADDRMODE_RAND	2 	/**< Random Addr mode */
+
+/* PARAM RAM Interval mode values */
+#define XTG_PARAMOP_INTERVALMODE_CONST	0	/**< Constant Interval mode */	
+#define XTG_PARAMOP_INTERVALMODE_RAND	1	/**< Random Interval mode */
+
+/*@}*/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_ReadReg returns the value read from the register specified by
+* <i>RegOffset</i>.
+*
+* @param	BaseAddress is the base address of the Axi TrafGen device.
+* @param	RegOffset is the offset of the register to be read.
+*
+* @return	Returns the 32-bit value of the register.
+*
+* @note		C-style signature:
+*		u32 XTrafGen_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XTrafGen_ReadReg(BaseAddress, RegOffset) \
+	(Xil_In32(((BaseAddress) + (RegOffset))))
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_WriteReg, writes <i>Data</i> to the register specified by
+* <i>RegOffset</i>.
+*
+* @param	BaseAddress is the base address of the Axi TrafGen device.
+* @param	RegOffset is the offset of the register to be written.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note
+* 	C-style signature:
+*	void XTrafGen_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data) \
+	Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_ReadParamRam returns the value read from the Parameter RAM
+* specified by <i>Offset</i>.
+*
+* @param	BaseAddress is the base address of the Axi TrafGen device.
+* @param	Offset is the offset of the Parameter RAM to be read.
+*
+* @return	Returns the 32-bit value of the memory location.
+*
+* @note		C-style signature:
+*		u32 XTrafGen_ReadParamRam(u32 BaseAddress, u32 Offset)
+*
+*****************************************************************************/
+#define XTrafGen_ReadParamRam(BaseAddress, Offset)	\
+	(Xil_In32(((BaseAddress) + XTG_PARAM_RAM_OFFSET + (Offset))))
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_WriteParamRam, writes <i>Data</i> to the Parameter RAM 
+* specified by <i>Offset</i>.
+*
+* @param	BaseAddress is the base address of the Axi TrafGen device.
+* @param	Offset is the offset of the location in Parameter RAM
+*		to be written.
+* @param	Data is the 32-bit value to write to the Parameter RAM.
+*
+* @return	None.
+*
+* @note
+* 	C-style signature:
+*	void XTrafGen_WriteParamRam(u32 BaseAddress, u32 Offset, u32 Data)
+*
+*****************************************************************************/
+#define XTrafGen_WriteParamRam(BaseAddress, Offset, Data) \
+	Xil_Out32(((BaseAddress) + XTG_PARAM_RAM_OFFSET + (Offset)), (Data))
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_ReadCmdRam returns the value read from the Command RAM
+* specified by <i>Offset</i>.
+*
+* @param	BaseAddress is the base address of the Axi TrafGen device.
+* @param	Offset is the offset of the Command RAM to be read.
+*
+* @return	Returns the 32-bit value of the memory location.
+*
+* @note		C-style signature:
+*		u32 XTrafGen_ReadCmdRam(u32 BaseAddress, u32 Offset)
+*
+*****************************************************************************/
+#define XTrafGen_ReadCmdRam(BaseAddress, Offset) \
+	(Xil_In32(((BaseAddress) + XTG_COMMAND_RAM_OFFSET + (Offset))))
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_WriteCmdRam, writes <i>Data</i> to the Command RAM specified by
+* <i>Offset</i>.
+*
+* @param	BaseAddress is the base address of the Axi TrafGen device.
+* @param	Offset is the offset of the location in Command RAM
+*		to be written.
+* @param	Data is the 32-bit value to write to the Command RAM.
+*
+* @return	None.
+*
+* @note
+* 	C-style signature:
+*	void XTrafGen_WriteCmdRam(u32 BaseAddress, u32 Offset, u32 Data)
+*
+*****************************************************************************/
+#define XTrafGen_WriteCmdRam(BaseAddress, Offset, Data) \
+	Xil_Out32(((BaseAddress) + XTG_COMMAND_RAM_OFFSET + (Offset)), (Data))
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_ReadMasterRam returns the value read from the Master RAM
+* specified by <i>Offset</i>.
+*
+* @param	BaseAddress is the base address of the Axi TrafGen device.
+* @param	Offset is the offset of the Master RAM to be read.
+*
+* @return	Returns the 32-bit value of the memory location.
+*
+* @note		C-style signature:
+*		u32 XTrafGen_ReadMasterRam(u32 BaseAddress, u32 Offset)
+*
+*****************************************************************************/
+#define XTrafGen_ReadMasterRam(BaseAddress, Offset)	\
+	(Xil_In32(((BaseAddress) + XTG_MASTER_RAM_OFFSET + (Offset))))
+
+/****************************************************************************/
+/**
+*
+* XTrafGen_WriteMasterRam, writes <i>Data</i> to the Master RAM specified
+* by <i>Offset</i>.
+*
+* @param	BaseAddress is the base address of the Axi TrafGen device.
+* @param	Offset is the offset of the location in Master RAM
+*		to be written.
+* @param	Data is the 32-bit value to write to the Master RAM.
+*
+* @return	None.
+*
+* @note
+* 	C-style signature:
+*	void XTrafGen_WriteMasterRam(u32 BaseAddress, u32 Offset, u32 Data)
+*
+*****************************************************************************/
+#define XTrafGen_WriteMasterRam(BaseAddress, Offset, Data) \
+	Xil_Out32(((BaseAddress) + XTG_MASTER_RAM_OFFSET + (Offset)), (Data))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_sinit.c b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_sinit.c
new file mode 100755
index 00000000..eaea7b93
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_sinit.c
@@ -0,0 +1,86 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtrafgen_sinit.c
+*
+* This file contains static initialzation functionality for Axi Traffic
+* Generator driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a srt  01/24/13 First release
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xtrafgen.h"
+
+/*****************************************************************************/
+/**
+ * Look up the hardware configuration for a device instance
+ *
+ * @param	DeviceId is the unique device ID of the device to lookup for
+ *
+ * @return
+ *		The configuration structure for the device. If the device ID is
+ *		not found,a NULL pointer is returned.
+ *
+ * @note	None
+ *
+ ******************************************************************************/
+XTrafGen_Config *XTrafGen_LookupConfig(u32 DeviceId)
+{
+	extern XTrafGen_Config XTrafGen_ConfigTable[];
+	XTrafGen_Config *CfgPtr;
+	u32 Index;
+
+	CfgPtr = NULL;
+
+	for (Index = 0; Index < XPAR_XTRAFGEN_NUM_INSTANCES; Index++) {
+		if (XTrafGen_ConfigTable[Index].DeviceId == DeviceId) {
+
+			CfgPtr = &XTrafGen_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}