From 1ca9de4bfb30225fa83486a63cf21491624c009b Mon Sep 17 00:00:00 2001
From: Subbaraya Sundeep Bhatta <subbaraya.sundeep.bhatta@xilinx.com>
Date: Mon, 18 May 2015 12:47:35 +0530
Subject: [PATCH] xadcps: Add new version 2.2

Added new version 2.2 and deprecated 2.1

Signed-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>
---
 .../drivers/xadcps/data/xadcps.mdd            |   42 +
 .../drivers/xadcps/data/xadcps.tcl            |   51 +
 .../drivers/xadcps/examples/index.html        |   18 +
 .../xadcps/examples/xadcps_intr_example.c     |  446 ++++
 .../examples/xadcps_polled_printf_example.c   |  303 +++
 .../drivers/xadcps/src/Makefile               |   40 +
 .../drivers/xadcps/src/xadcps.c               | 1826 +++++++++++++++++
 .../drivers/xadcps/src/xadcps.h               |  576 ++++++
 .../drivers/xadcps/src/xadcps_g.c             |   82 +
 .../drivers/xadcps/src/xadcps_hw.h            |  499 +++++
 .../drivers/xadcps/src/xadcps_intr.c          |  247 +++
 .../drivers/xadcps/src/xadcps_selftest.c      |  138 ++
 .../drivers/xadcps/src/xadcps_sinit.c         |  100 +
 13 files changed, 4368 insertions(+)
 create mode 100755 XilinxProcessorIPLib/drivers/xadcps/data/xadcps.mdd
 create mode 100755 XilinxProcessorIPLib/drivers/xadcps/data/xadcps.tcl
 create mode 100755 XilinxProcessorIPLib/drivers/xadcps/examples/index.html
 create mode 100644 XilinxProcessorIPLib/drivers/xadcps/examples/xadcps_intr_example.c
 create mode 100644 XilinxProcessorIPLib/drivers/xadcps/examples/xadcps_polled_printf_example.c
 create mode 100644 XilinxProcessorIPLib/drivers/xadcps/src/Makefile
 create mode 100644 XilinxProcessorIPLib/drivers/xadcps/src/xadcps.c
 create mode 100644 XilinxProcessorIPLib/drivers/xadcps/src/xadcps.h
 create mode 100644 XilinxProcessorIPLib/drivers/xadcps/src/xadcps_g.c
 create mode 100644 XilinxProcessorIPLib/drivers/xadcps/src/xadcps_hw.h
 create mode 100644 XilinxProcessorIPLib/drivers/xadcps/src/xadcps_intr.c
 create mode 100644 XilinxProcessorIPLib/drivers/xadcps/src/xadcps_selftest.c
 create mode 100644 XilinxProcessorIPLib/drivers/xadcps/src/xadcps_sinit.c

diff --git a/XilinxProcessorIPLib/drivers/xadcps/data/xadcps.mdd b/XilinxProcessorIPLib/drivers/xadcps/data/xadcps.mdd
new file mode 100755
index 00000000..ea641d31
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/xadcps/data/xadcps.mdd
@@ -0,0 +1,42 @@
+###############################################################################
+#
+# Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+OPTION psf_version = 2.1;
+
+BEGIN driver xadcps
+
+  OPTION supported_peripherals = (ps7_xadc);
+  OPTION driver_state = ACTIVE;
+  OPTION copyfiles = all;
+  OPTION VERSION = 2.2;
+  OPTION NAME = xadcps;
+
+END driver
diff --git a/XilinxProcessorIPLib/drivers/xadcps/data/xadcps.tcl b/XilinxProcessorIPLib/drivers/xadcps/data/xadcps.tcl
new file mode 100755
index 00000000..4b85567a
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/xadcps/data/xadcps.tcl
@@ -0,0 +1,51 @@
+###############################################################################
+#
+# Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+##############################################################################
+#
+# Modification History
+#
+# Ver   Who  Date     Changes
+# ----- ---- -------- -----------------------------------------------
+# 1.02a asa  09/07/13 Created
+#
+##############################################################################
+
+#uses "xillib.tcl"
+
+proc generate {drv_handle} {
+    ::hsi::utils::define_zynq_include_file $drv_handle "xparameters.h" "XAdcPs" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR"
+
+    ::hsi::utils::define_zynq_config_file $drv_handle "xadcps_g.c" "XAdcPs"  "DEVICE_ID" "C_S_AXI_BASEADDR"
+
+    ::hsi::utils::define_zynq_canonical_xpars $drv_handle "xparameters.h" "XAdcPs" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR"
+
+}
diff --git a/XilinxProcessorIPLib/drivers/xadcps/examples/index.html b/XilinxProcessorIPLib/drivers/xadcps/examples/index.html
new file mode 100755
index 00000000..56fe0318
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/xadcps/examples/index.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
+<html>
+<head>
+<meta http-equiv="Content-Language" content="en-us">
+<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+<title>Driver example applications</title>
+<link rel="stylesheet" type="text/css" href="../help.css">
+</head>
+<body bgcolor="#FFFFFF">
+<h1> Example Applications for the driver xadcps_v2_1 </h1>
+<HR>
+<ul>
+  <li>xadcps_intr_example.c <a href="xadcps_intr_example.c">(source)</a> </li>
+  <li>xadcps_polled_printf_example.c <a href="xadcps_polled_printf_example.c">(source)</a> </li>
+</ul>
+<p><font face="Times New Roman" color="#800000">Copyright � 1995-2014 Xilinx, Inc. All rights reserved.</font></p>
+</body>
+</html>
diff --git a/XilinxProcessorIPLib/drivers/xadcps/examples/xadcps_intr_example.c b/XilinxProcessorIPLib/drivers/xadcps/examples/xadcps_intr_example.c
new file mode 100644
index 00000000..fcb8d4f7
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/xadcps/examples/xadcps_intr_example.c
@@ -0,0 +1,446 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps_intr_example.c
+*
+* This file contains a design example using the driver functions of the
+* XADC/ADC driver. This example here shows the usage of the driver/device in
+* interrupt mode to handle on-chip temperature and voltage alarm interrupts.
+*
+*
+* @note
+*
+* This code assumes that no Operating System is being used.
+*
+* The values of the on-chip temperature and the on-chip Vccaux voltage are read
+* from the device and then the alarm thresholds are set in such a manner that
+* the alarms occur.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    01/20/12 First release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xparameters.h"
+#include "xadcps.h"
+#include "xscugic.h"
+#include "xil_exception.h"
+
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#ifndef TESTAPP_GEN
+#define XADC_DEVICE_ID		XPAR_XADCPS_0_DEVICE_ID
+#define INTC_DEVICE_ID		XPAR_SCUGIC_SINGLE_DEVICE_ID
+#define INTR_ID				XPAR_XADCPS_INT_ID
+#define printf				xil_printf
+#endif
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+int XAdcIntrExample(XScuGic *IntcInstancePtr,
+			XAdcPs *XAdcInstPtr,
+			u16 XAdcDeviceId,
+			u16 XAdcIntrId,
+			int *Temp);
+
+static void XAdcInterruptHandler(void *CallBackRef);
+
+static int XAdcSetupInterruptSystem(XScuGic *IntcInstancePtr,
+				      XAdcPs *XAdcPtr,
+				      u16 IntrId );
+
+/************************** Variable Definitions ****************************/
+
+#ifndef TESTAPP_GEN
+static XAdcPs XAdcInst; 	  	/* XADC driver instance */
+static XScuGic InterruptController; 	/* Instance of the GIC driver */
+#endif
+
+/*
+ * Shared variables used to test the callbacks.
+ */
+static volatile  int TemperatureIntr = FALSE; 	/* Temperature alarm intr */
+static volatile  int VccpauxIntr = FALSE;	/* VCCPAUX alarm interrupt */
+
+#ifndef TESTAPP_GEN
+/****************************************************************************/
+/**
+*
+* Main function that invokes the XADC Interrupt example.
+*
+* @param	None.
+*
+* @return
+*		- XST_SUCCESS if the example has completed successfully.
+*		- XST_FAILURE if the example has failed.
+*
+* @note		None.
+*
+*****************************************************************************/
+int main(void)
+{
+
+	int Status;
+	int Temp;
+
+	/*
+	 * Run the XAdc interrupt example, specify the parameters that
+	 * are generated in xparameters.h.
+	 */
+	Status = XAdcIntrExample(&InterruptController,
+				   &XAdcInst,
+				   XADC_DEVICE_ID,
+				   INTR_ID,
+				   &Temp);
+	if (Status != XST_SUCCESS) {
+		printf("Interrupt example Failed\r\n");
+		return XST_FAILURE;
+	}
+	printf("Interrupt example Passed\r\n");
+	return XST_SUCCESS;
+
+}
+#endif /* TESTAPP_GEN */
+
+/****************************************************************************/
+/**
+*
+* This function runs a test on the XADC/ADC device using the
+* driver APIs.
+*
+* The function does the following tasks:
+*	- Initiate the XADC/ADC device driver instance
+*	- Run self-test on the device
+*	- Reset the device
+*	- Set up alarms for on-chip temperature and VCCPAUX
+*	- Set up sequence registers to continuously monitor on-chip temperature
+*	and VCCPAUX
+*	- Setup interrupt system
+*	- Enable interrupts
+*	- Set up configuration registers to start the sequence
+*	- Wait until temperature alarm interrupt or VCCPAUX alarm interrupt
+*	occurs
+*
+* @param	IntcInstancePtr is a pointer to the Interrupt Controller
+*		driver Instance.
+* @param	XAdcInstPtr is a pointer to the XAdcPs driver Instance.
+* @param	XAdcDeviceId is the XPAR_<SYSMON_ADC_instance>_DEVICE_ID value
+*		from xparameters.h.
+* @param	XAdcIntrId is
+*		XPAR_<INTC_instance>_<SYSMON_ADC_instance>_VEC_ID value from
+*		xparameters.h
+* @param	Temp is an output parameter, it is a pointer through which the
+*		current temperature value is returned to the main function.
+*
+* @return
+*		- XST_SUCCESS if the example has completed successfully.
+*		- XST_FAILURE if the example has failed.
+*
+* @note		This function may never return if no interrupt occurs.
+*
+****************************************************************************/
+int XAdcIntrExample(XScuGic *IntcInstancePtr, XAdcPs *XAdcInstPtr,
+			u16 XAdcDeviceId, u16 XAdcIntrId, int *Temp)
+{
+	int Status;
+	XAdcPs_Config *ConfigPtr;
+	u16 TempData;
+	u16 VccpauxData;
+	u32 IntrStatus;
+
+	/*
+	 * Initialize the XAdc driver.
+	 */
+	ConfigPtr = XAdcPs_LookupConfig(XAdcDeviceId);
+	if (ConfigPtr == NULL) {
+		return XST_FAILURE;
+	}
+	XAdcPs_CfgInitialize(XAdcInstPtr, ConfigPtr, ConfigPtr->BaseAddress);
+
+	/*
+	 * Self Test the XADC/ADC device.
+	 */
+	Status = XAdcPs_SelfTest(XAdcInstPtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set XADC in default mode so that alarms are inactive
+	 */
+	XAdcPs_SetSequencerMode(XAdcInstPtr, XADCPS_SEQ_MODE_SAFE);
+
+	/* Disable all alarms */
+	XAdcPs_SetAlarmEnables(XAdcInstPtr,0x0000);
+
+	/*
+	 * Set up Alarm threshold registers for the on-chip temperature and
+	 * VCCPAUX High limit and lower limit so that the alarms occur.
+	 */
+	TempData = XAdcPs_GetAdcData(XAdcInstPtr, XADCPS_CH_TEMP);
+	XAdcPs_SetAlarmThreshold(XAdcInstPtr, XADCPS_ATR_TEMP_UPPER,(TempData-0x07FF));
+	XAdcPs_SetAlarmThreshold(XAdcInstPtr, XADCPS_ATR_TEMP_LOWER,(TempData+0x07FF));
+
+	VccpauxData = XAdcPs_GetAdcData(XAdcInstPtr, XADCPS_CH_VCCPAUX);
+	XAdcPs_SetAlarmThreshold(XAdcInstPtr, XADCPS_ATR_VCCPAUX_UPPER,(VccpauxData-0x07FF));
+	XAdcPs_SetAlarmThreshold(XAdcInstPtr, XADCPS_ATR_VCCPAUX_LOWER,(VccpauxData+0x07FF));
+
+	/*
+	 * Setup the interrupt system.
+	 */
+	Status = XAdcSetupInterruptSystem(IntcInstancePtr,
+					    XAdcInstPtr,
+					    XAdcIntrId);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Clear any bits set in the Interrupt Status Register.
+	 */
+	IntrStatus = XAdcPs_IntrGetStatus(XAdcInstPtr);
+	XAdcPs_IntrClear(XAdcInstPtr, IntrStatus);
+
+
+	/*
+	 * Enable Alarm 0 interrupt for on-chip temperature and Alarm 5
+	 * interrupt for on-chip VCCPAUX.
+	 */
+	XAdcPs_IntrEnable(XAdcInstPtr,
+			(XADCPS_INTX_ALM5_MASK | XADCPS_INTX_ALM0_MASK));
+
+	/*
+	 * Enable Alarm 0 for on-chip temperature and Alarm 5 for on-chip
+	 * VCCPAUX in the Configuration Register 1.
+	 */
+	XAdcPs_SetAlarmEnables(XAdcInstPtr, (XADCPS_CFR1_ALM_VCCPAUX_MASK
+											| XADCPS_CFR1_ALM_TEMP_MASK));
+
+
+	XAdcPs_SetSequencerMode(XAdcInstPtr, XADCPS_SEQ_MODE_INDEPENDENT);
+
+
+	/*
+	 * Wait until an Alarm 0 or Alarm 2 interrupt occurs.
+	 */
+	while (1) {
+		if (TemperatureIntr == TRUE) {
+			/*
+			 * Alarm 0 - Temperature alarm interrupt has occurred.
+			 * The required processing should be put here.
+			 */
+			break;
+		}
+		if (VccpauxIntr == TRUE) {
+					/*
+					 * Alarm 5 - VccPAUX alarm interrupt has occurred.
+					 * The required processing should be put here.
+					 */
+					break;
+		}
+
+	}
+
+
+	/* Set back the ADC in default mode */
+
+	XAdcPs_SetSequencerMode(XAdcInstPtr, XADCPS_SEQ_MODE_SAFE);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is the Interrupt Service Routine for the XADC device.
+* It will be called by the processor whenever an interrupt is asserted
+* by the device.
+*
+* There are 8 different interrupts supported
+*	- Over Temperature
+*	- ALARM 0 to ALARM 7
+*
+* This function only handles ALARM 0 and ALARM 2 interrupts. User of this
+* code may need to modify the code to meet needs of the application.
+*
+* @param	CallBackRef is the callback reference passed from the Interrupt
+*		controller driver, which in our case is a pointer to the
+*		driver instance.
+*
+* @return	None.
+*
+* @note		This function is called within interrupt context.
+*
+******************************************************************************/
+static void XAdcInterruptHandler(void *CallBackRef)
+{
+	u32 IntrStatusValue;
+	XAdcPs *XAdcPtr = (XAdcPs *)CallBackRef;
+
+	/*
+	 * Get the interrupt status from the device and check the value.
+	 */
+
+	IntrStatusValue = XAdcPs_IntrGetStatus(XAdcPtr);
+
+	if (IntrStatusValue & XADCPS_INTX_ALM0_MASK) {
+		/*
+		 * Set Temperature interrupt flag so the code
+		 * in application context can be aware of this interrupt.
+		 */
+		TemperatureIntr = TRUE;
+
+		/* Disable Temperature interrupt */
+		XAdcPs_IntrDisable(XAdcPtr,XADCPS_INTX_ALM0_MASK);
+
+	}
+	if (IntrStatusValue & XADCPS_INTX_ALM5_MASK) {
+			/*
+			 * Set Temperature interrupt flag so the code
+			 * in application context can be aware of this interrupt.
+			 */
+		VccpauxIntr = TRUE;
+
+		/* Disable VccPAUX interrupt */
+		XAdcPs_IntrDisable(XAdcPtr,XADCPS_INTX_ALM5_MASK);
+	}
+
+	/*
+	 * Clear all bits in Interrupt Status Register.
+	 */
+	XAdcPs_IntrClear(XAdcPtr, IntrStatusValue);
+ }
+
+/****************************************************************************/
+/**
+*
+* This function sets up the interrupt system so interrupts can occur for the
+* XADC/ADC.  The function is application-specific since the actual
+* system may or may not have an interrupt controller. The XADC/ADC
+* device could be directly connected to a processor without an interrupt
+* controller. The user should modify this function to fit the application.
+*
+* @param	IntcInstancePtr is a pointer to the Interrupt Controller
+*		driver Instance.
+* @param	XAdcPtr is a pointer to the driver instance for the System
+* 		Monitor device which is going to be connected to the interrupt
+*		controller.
+* @param	IntrId is XPAR_<INTC_instance>_<SYSMON_ADC_instance>_VEC_ID
+*		value from xparameters.h.
+*
+* @return	XST_SUCCESS if successful, or XST_FAILURE.
+*
+* @note		None.
+*
+*
+****************************************************************************/
+static int XAdcSetupInterruptSystem(XScuGic *IntcInstancePtr,
+				      XAdcPs *XAdcPtr,
+				      u16 IntrId )
+{
+
+	int Status;
+	XScuGic_Config *IntcConfig; /* Instance of the interrupt controller */
+
+
+	/*
+	 * Initialize the interrupt controller driver so that it is ready to
+	 * use.
+	 */
+	IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
+	if (NULL == IntcConfig) {
+		return XST_FAILURE;
+	}
+
+	Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
+					IntcConfig->CpuBaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Connect the device driver handler that will be called when an
+	 * interrupt for the device occurs, the handler defined above performs
+	 * the specific interrupt processing for the device.
+	 */
+	Status = XScuGic_Connect(IntcInstancePtr, IntrId,
+				(Xil_InterruptHandler)XAdcInterruptHandler,
+				(void *)XAdcPtr);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	/*
+	 * Enable the interrupt for the XADC device.
+	 */
+	XScuGic_Enable(IntcInstancePtr, IntrId);
+
+	/*
+	 * Initialize the exception table.
+	 */
+	Xil_ExceptionInit();
+
+	/*
+	 * Register the interrupt controller handler with the exception table.
+	 */
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+				(Xil_ExceptionHandler) XScuGic_InterruptHandler,
+				IntcInstancePtr);
+	/*
+	 * Enable exceptions.
+	 */
+	Xil_ExceptionEnable();
+
+
+	return XST_SUCCESS;
+
+}
diff --git a/XilinxProcessorIPLib/drivers/xadcps/examples/xadcps_polled_printf_example.c b/XilinxProcessorIPLib/drivers/xadcps/examples/xadcps_polled_printf_example.c
new file mode 100644
index 00000000..d032d05a
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/xadcps/examples/xadcps_polled_printf_example.c
@@ -0,0 +1,303 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadc_polled_printf_example.c
+*
+* This file contains a design example using the driver functions
+* of the XADC driver. The example here shows the driver/device in polled mode
+* to check the on-chip temperature and voltages.
+*
+* @note
+*
+* This examples also assumes that there is a STDIO device in the system.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI SysMon driver
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xparameters.h"
+#include "xadcps.h"
+#include "xstatus.h"
+#include "stdio.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define XADC_DEVICE_ID 		XPAR_XADCPS_0_DEVICE_ID
+
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+#define printf xil_printf /* Small foot-print printf function */
+
+/************************** Function Prototypes *****************************/
+
+static int XAdcPolledPrintfExample(u16 XAdcDeviceId);
+static int XAdcFractionToInt(float FloatNum);
+
+/************************** Variable Definitions ****************************/
+
+static XAdcPs XAdcInst;      /* XADC driver instance */
+
+/****************************************************************************/
+/**
+*
+* Main function that invokes the polled example in this file.
+*
+* @param	None.
+*
+* @return
+*		- XST_SUCCESS if the example has completed successfully.
+*		- XST_FAILURE if the example has failed.
+*
+* @note		None.
+*
+*****************************************************************************/
+int main(void)
+{
+
+	int Status;
+
+	/*
+	 * Run the polled example, specify the Device ID that is
+	 * generated in xparameters.h.
+	 */
+	Status = XAdcPolledPrintfExample(XADC_DEVICE_ID);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+	return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a test on the XADC/ADC device using the
+* driver APIs.
+* This function does the following tasks:
+*	- Initiate the XADC device driver instance
+*	- Run self-test on the device
+*	- Setup the sequence registers to continuously monitor on-chip
+*	temperature and, VCCPINT, VCCPAUX and VCCPDRO Voltages
+*	- Setup configuration registers to start the sequence
+*	- Read the latest on-chip temperature and, VCCPINT, VCCPAUX and VCCPDRO
+*	  Voltages
+*
+* @param	XAdcDeviceId is the XPAR_<SYSMON_ADC_instance>_DEVICE_ID value
+*		from xparameters.h.
+*
+* @return
+*		- XST_SUCCESS if the example has completed successfully.
+*		- XST_FAILURE if the example has failed.
+*
+* @note   	None
+*
+****************************************************************************/
+int XAdcPolledPrintfExample(u16 XAdcDeviceId)
+{
+	int Status;
+	XAdcPs_Config *ConfigPtr;
+	u32 TempRawData;
+	u32 VccPintRawData;
+	u32 VccPauxRawData;
+	u32 VccPdroRawData;
+	float TempData;
+	float VccPintData;
+	float VccPauxData;
+	float MaxData;
+	float MinData;
+	XAdcPs *XAdcInstPtr = &XAdcInst;
+
+	printf("\r\nEntering the XAdc Polled Example. \r\n");
+
+	/*
+	 * Initialize the XAdc driver.
+	 */
+	ConfigPtr = XAdcPs_LookupConfig(XAdcDeviceId);
+	if (ConfigPtr == NULL) {
+		return XST_FAILURE;
+	}
+	XAdcPs_CfgInitialize(XAdcInstPtr, ConfigPtr,
+				ConfigPtr->BaseAddress);
+
+	/*
+	 * Self Test the XADC/ADC device
+	 */
+	Status = XAdcPs_SelfTest(XAdcInstPtr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Disable the Channel Sequencer before configuring the Sequence
+	 * registers.
+	 */
+	XAdcPs_SetSequencerMode(XAdcInstPtr, XADCPS_SEQ_MODE_SAFE);
+	/*
+	 * Read the on-chip Temperature Data (Current/Maximum/Minimum)
+	 * from the ADC data registers.
+	 */
+	TempRawData = XAdcPs_GetAdcData(XAdcInstPtr, XADCPS_CH_TEMP);
+	TempData = XAdcPs_RawToTemperature(TempRawData);
+	printf("\r\nThe Current Temperature is %0d.%03d Centigrades.\r\n",
+				(int)(TempData), XAdcFractionToInt(TempData));
+
+
+	TempRawData = XAdcPs_GetMinMaxMeasurement(XAdcInstPtr, XADCPS_MAX_TEMP);
+	MaxData = XAdcPs_RawToTemperature(TempRawData);
+	printf("The Maximum Temperature is %0d.%03d Centigrades. \r\n",
+				(int)(MaxData), XAdcFractionToInt(MaxData));
+
+	TempRawData = XAdcPs_GetMinMaxMeasurement(XAdcInstPtr, XADCPS_MIN_TEMP);
+	MinData = XAdcPs_RawToTemperature(TempRawData & 0xFFF0);
+	printf("The Minimum Temperature is %0d.%03d Centigrades. \r\n",
+				(int)(MinData), XAdcFractionToInt(MinData));
+
+	/*
+	 * Read the VccPint Votage Data (Current/Maximum/Minimum) from the
+	 * ADC data registers.
+	 */
+	VccPintRawData = XAdcPs_GetAdcData(XAdcInstPtr, XADCPS_CH_VCCPINT);
+	VccPintData = XAdcPs_RawToVoltage(VccPintRawData);
+	printf("\r\nThe Current VCCPINT is %0d.%03d Volts. \r\n",
+			(int)(VccPintData), XAdcFractionToInt(VccPintData));
+
+	VccPintRawData = XAdcPs_GetMinMaxMeasurement(XAdcInstPtr,
+							XADCPS_MAX_VCCPINT);
+	MaxData = XAdcPs_RawToVoltage(VccPintRawData);
+	printf("The Maximum VCCPINT is %0d.%03d Volts. \r\n",
+			(int)(MaxData), XAdcFractionToInt(MaxData));
+
+	VccPintRawData = XAdcPs_GetMinMaxMeasurement(XAdcInstPtr,
+							XADCPS_MIN_VCCPINT);
+	MinData = XAdcPs_RawToVoltage(VccPintRawData);
+	printf("The Minimum VCCPINT is %0d.%03d Volts. \r\n",
+			(int)(MinData), XAdcFractionToInt(MinData));
+
+	/*
+	 * Read the VccPaux Votage Data (Current/Maximum/Minimum) from the
+	 * ADC data registers.
+	 */
+	VccPauxRawData = XAdcPs_GetAdcData(XAdcInstPtr, XADCPS_CH_VCCPAUX);
+	VccPauxData = XAdcPs_RawToVoltage(VccPauxRawData);
+	printf("\r\nThe Current VCCPAUX is %0d.%03d Volts. \r\n",
+			(int)(VccPauxData), XAdcFractionToInt(VccPauxData));
+
+	VccPauxRawData = XAdcPs_GetMinMaxMeasurement(XAdcInstPtr,
+								XADCPS_MAX_VCCPAUX);
+	MaxData = XAdcPs_RawToVoltage(VccPauxRawData);
+	printf("The Maximum VCCPAUX is %0d.%03d Volts. \r\n",
+				(int)(MaxData), XAdcFractionToInt(MaxData));
+
+
+	VccPauxRawData = XAdcPs_GetMinMaxMeasurement(XAdcInstPtr,
+								XADCPS_MIN_VCCPAUX);
+	MinData = XAdcPs_RawToVoltage(VccPauxRawData);
+	printf("The Minimum VCCPAUX is %0d.%03d Volts. \r\n\r\n",
+				(int)(MinData), XAdcFractionToInt(MinData));
+
+
+	/*
+	 * Read the VccPdro Votage Data (Current/Maximum/Minimum) from the
+	 * ADC data registers.
+	 */
+	VccPdroRawData = XAdcPs_GetAdcData(XAdcInstPtr, XADCPS_CH_VCCPDRO);
+	VccPintData = XAdcPs_RawToVoltage(VccPdroRawData);
+	printf("\r\nThe Current VCCPDDRO is %0d.%03d Volts. \r\n",
+			(int)(VccPintData), XAdcFractionToInt(VccPintData));
+
+	VccPdroRawData = XAdcPs_GetMinMaxMeasurement(XAdcInstPtr,
+							XADCPS_MAX_VCCPDRO);
+	MaxData = XAdcPs_RawToVoltage(VccPdroRawData);
+	printf("The Maximum VCCPDDRO is %0d.%03d Volts. \r\n",
+			(int)(MaxData), XAdcFractionToInt(MaxData));
+
+	VccPdroRawData = XAdcPs_GetMinMaxMeasurement(XAdcInstPtr,
+							XADCPS_MIN_VCCPDRO);
+	MinData = XAdcPs_RawToVoltage(VccPdroRawData);
+	printf("The Minimum VCCPDDRO is %0d.%03d Volts. \r\n",
+			(int)(MinData), XAdcFractionToInt(MinData));
+
+
+	printf("Exiting the XAdc Polled Example. \r\n");
+
+	return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/*
+*
+* This function converts the fraction part of the given floating point number
+* (after the decimal point)to an integer.
+*
+* @param	FloatNum is the floating point number.
+*
+* @return	Integer number to a precision of 3 digits.
+*
+* @note
+* This function is used in the printing of floating point data to a STDIO device
+* using the xil_printf function. The xil_printf is a very small foot-print
+* printf function and does not support the printing of floating point numbers.
+*
+*****************************************************************************/
+int XAdcFractionToInt(float FloatNum)
+{
+	float Temp;
+
+	Temp = FloatNum;
+	if (FloatNum < 0) {
+		Temp = -(FloatNum);
+	}
+
+	return( ((int)((Temp -(float)((int)Temp)) * (1000.0f))));
+}
diff --git a/XilinxProcessorIPLib/drivers/xadcps/src/Makefile b/XilinxProcessorIPLib/drivers/xadcps/src/Makefile
new file mode 100644
index 00000000..837ca136
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/xadcps/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xadcps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling xadcps"
+
+xadcps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xadcps_includes
+
+xadcps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/XilinxProcessorIPLib/drivers/xadcps/src/xadcps.c b/XilinxProcessorIPLib/drivers/xadcps/src/xadcps.c
new file mode 100644
index 00000000..b5088747
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/xadcps/src/xadcps.c
@@ -0,0 +1,1826 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.c
+*
+* This file contains the driver API functions that can be used to access
+* the XADC device.
+*
+* Refer to the xadcps.h header file for more information about this driver.
+*
+* @note 	None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+*			to fix CR #693371
+* 2.1   bss    08/05/14	Modified Assert for XAdcPs_SetSingleChParams to fix
+*			CR #807563.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data);
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset);
+
+
+/************************** Variable Definitions ****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes a specific XAdcPs device/instance. This function
+* must be called prior to using the XADC device.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	ConfigPtr points to the XAdcPs device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address is passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*
+* @note		The user needs to first call the XAdcPs_LookupConfig() API
+*		which returns the Configuration structure pointer which is
+*		passed as a parameter to the XAdcPs_CfgInitialize() API.
+*
+******************************************************************************/
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, XAdcPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+
+	u32 RegValue;
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+
+	/*
+	 * Set the values read from the device config and the base address.
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+	/* Write Unlock value to Device Config Unlock register */
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_UNLK_OFFSET, XADCPS_UNLK_VALUE);
+
+	/* Enable the PS access of xadc and set FIFO thresholds */
+
+	RegValue = XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+			XADCPS_CFG_OFFSET);
+
+	RegValue = RegValue | XADCPS_CFG_ENABLE_MASK |
+			XADCPS_CFG_CFIFOTH_MASK | XADCPS_CFG_DFIFOTH_MASK;
+
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+					XADCPS_CFG_OFFSET, RegValue);
+
+	/* Release xadc from reset */
+
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+						XADCPS_MCTL_OFFSET, 0x00);
+
+	/*
+	 * Indicate the instance is now ready to use and
+	 * initialized without error.
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Config Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Data is the 32 bit data to be written to the Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_CFG_OFFSET, Data);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Config Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the Config Register.
+*		Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+*		interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Config Register and return the value.
+	 */
+	return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_CFG_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous Status Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the Miscellaneous
+*		Status Register. Use the XADCPS_MSTS_*_MASK constants defined
+*		in xadcps_hw.h to interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Miscellaneous Status Register and return the value.
+	 */
+	return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MSTS_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Miscellaneous Control register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Data is the 32 bit data to be written to the Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Write to the Miscellaneous control register Register.
+	 */
+	 XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET, Data);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous control register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the Config Register.
+*		Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+*		interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Miscellaneous control register and return the value.
+	 */
+	return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function resets the XADC Hard Macro in the device.
+*
+* @param	InstancePtr is a pointer to the Xxadc instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XAdcPs_Reset(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Generate the reset by Control
+	 * register and release from reset
+	 */
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET, 0x10);
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET, 0x00);
+}
+
+
+/****************************************************************************/
+/**
+*
+* Get the ADC converted data for the specified channel.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Channel is the channel number. Use the XADCPS_CH_* defined in
+*		the file xadcps.h.
+*		The valid channels are
+*		- 0 to 6
+*		- 13 to 31
+*
+* @return	A 16-bit value representing the ADC converted data for the
+*		specified channel. The XADC Monitor/ADC device guarantees
+* 		a 10 bit resolution for the ADC converted data and data is the
+*		10 MSB bits of the 16 data read from the device.
+*
+* @note		The channels 7,8,9 are used for calibration of the device and
+*		hence there is no associated data with this channel.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel)
+{
+
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
+			 ((Channel >= XADCPS_CH_VCCPINT) &&
+			 (Channel <= XADCPS_CH_AUX_MAX)));
+
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+						(XADCPS_TEMP_OFFSET +
+						Channel));
+	return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the calibration coefficient data for the specified
+* parameter.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	CoeffType specifies the calibration coefficient
+*		to be read. Use XADCPS_CALIB_* constants defined in xadcps.h to
+*		specify the calibration coefficient to be read.
+*
+* @return	A 16-bit value representing the calibration coefficient.
+*		The XADC device guarantees a 10 bit resolution for
+*		the ADC converted data and data is the 10 MSB bits of the 16
+*		data read from the device.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType)
+{
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(CoeffType <= XADCPS_CALIB_GAIN_ERROR_COEFF);
+
+	/*
+	 * Read the selected calibration coefficient.
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+					(XADCPS_ADC_A_SUPPLY_CALIB_OFFSET +
+					CoeffType));
+	return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the Minimum/Maximum measurement for one of the
+* specified parameters. Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in
+* xadcps.h to specify the parameters (Temperature, VccInt, VccAux, VBram,
+* VccPInt, VccPAux and VccPDro).
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	MeasurementType specifies the parameter for which the
+*		Minimum/Maximum measurement has to be read.
+*		Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in xadcps.h to
+*		specify the data to be read.
+*
+* @return	A 16-bit value representing the maximum/minimum measurement for
+*		specified parameter.
+*		The XADC device guarantees a 10 bit resolution for
+*		the ADC converted data and data is the 10 MSB bits of the 16
+*		data read from the device.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType)
+{
+	u32 RegData;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((MeasurementType <= XADCPS_MAX_VCCPDRO) ||
+			((MeasurementType >= XADCPS_MIN_VCCPINT) &&
+			(MeasurementType <= XADCPS_MIN_VCCPDRO)))
+
+	/*
+	 * Read and return the specified Minimum/Maximum measurement.
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+					(XADCPS_MAX_TEMP_OFFSET +
+					MeasurementType));
+	return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of samples of averaging that is to be done for
+* all the channels in both the single channel mode and sequence mode of
+* operations.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Average is the number of samples of averaging programmed to the
+*		Configuration Register 0. Use the XADCPS_AVG_* definitions defined
+*		in xadcps.h file :
+*		- XADCPS_AVG_0_SAMPLES for no averaging
+*		- XADCPS_AVG_16_SAMPLES for 16 samples of averaging
+*		- XADCPS_AVG_64_SAMPLES for 64 samples of averaging
+*		- XADCPS_AVG_256_SAMPLES for 256 samples of averaging
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average)
+{
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Average <= XADCPS_AVG_256_SAMPLES);
+
+	/*
+	 * Write the averaging value into the Configuration Register 0.
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					(~XADCPS_CFR0_AVG_VALID_MASK);
+
+	RegData |=  (((u32) Average << XADCPS_CFR0_AVG_SHIFT));
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+					RegData);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the number of samples of averaging configured for all
+* the channels in the Configuration Register 0.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The averaging read from the Configuration Register 0 is
+*		returned. Use the XADCPS_AVG_* bit definitions defined in
+*		xadcps.h file to interpret the returned value :
+*		- XADCPS_AVG_0_SAMPLES means no averaging
+*		- XADCPS_AVG_16_SAMPLES means 16 samples of averaging
+*		- XADCPS_AVG_64_SAMPLES means 64 samples of averaging
+*		- XADCPS_AVG_256_SAMPLES means 256 samples of averaging
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr)
+{
+	u32 Average;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the averaging value from the Configuration Register 0.
+	 */
+	Average = XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_AVG_VALID_MASK;
+
+
+	return ((u8) (Average >> XADCPS_CFR0_AVG_SHIFT));
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the given parameters in the Configuration Register 0 in
+* the single channel mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Channel is the channel number for the singel channel mode.
+*		The valid channels are 0 to 6, 8, and 13 to 31.
+*		If the external Mux is used then this specifies the channel
+*		oonnected to the external Mux. Please read the Device Spec
+*		to know which channels are valid.
+* @param 	IncreaseAcqCycles is a boolean parameter which specifies whether
+*		the Acquisition time for the external channels has to be
+*		increased to 10 ADCCLK cycles (specify TRUE) or remain at the
+*		default 4 ADCCLK cycles (specify FALSE). This parameter is
+*		only valid for the external channels.
+* @param 	IsDifferentialMode is a boolean parameter which specifies
+*		unipolar(specify FALSE) or differential mode (specify TRUE) for
+*		the analog inputs. The 	input mode is only valid for the
+*		external channels.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Configuration Register 0.
+*		- XST_FAILURE if the channel sequencer is enabled or the input
+*		parameters are not valid for the selected channel.
+*
+* @note
+*		- The number of samples for the averaging for all the channels
+*		is set by using the function XAdcPs_SetAvg.
+*		- The calibration of the device is done by doing a ADC
+*		conversion on the calibration channel(channel 8). The input
+*		parameters IncreaseAcqCycles, IsDifferentialMode and
+*		IsEventMode are not valid for this channel
+*
+*
+*****************************************************************************/
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+				u8 Channel,
+				int IncreaseAcqCycles,
+				int IsEventMode,
+				int IsDifferentialMode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
+			(Channel == XADCPS_CH_ADC_CALIB) ||
+			((Channel >= XADCPS_CH_VCCPINT) &&
+			(Channel <= XADCPS_CH_AUX_MAX)));
+	Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
+			(IncreaseAcqCycles == FALSE));
+	Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+	Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
+			(IsDifferentialMode == FALSE));
+
+	/*
+	 * Check if the device is in single channel mode else return failure
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+		XADCPS_SEQ_MODE_SINGCHAN)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Read the Configuration Register 0.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					XADCPS_CFR0_AVG_VALID_MASK;
+
+	/*
+	 * Select the number of acquisition cycles. The acquisition cycles is
+	 * only valid for the external channels.
+	 */
+	if (IncreaseAcqCycles == TRUE) {
+		if (((Channel >= XADCPS_CH_AUX_MIN) &&
+			(Channel <= XADCPS_CH_AUX_MAX)) ||
+			(Channel == XADCPS_CH_VPVN)){
+			RegValue |= XADCPS_CFR0_ACQ_MASK;
+		} else {
+			return XST_FAILURE;
+		}
+
+	}
+
+	/*
+	 * Select the input mode. The input mode is only valid for the
+	 * external channels.
+	 */
+	if (IsDifferentialMode == TRUE) {
+
+		if (((Channel >= XADCPS_CH_AUX_MIN) &&
+			(Channel <= XADCPS_CH_AUX_MAX)) ||
+			(Channel == XADCPS_CH_VPVN)){
+			RegValue |= XADCPS_CFR0_DU_MASK;
+		} else {
+			return XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Select the ADC mode.
+	 */
+	if (IsEventMode == TRUE) {
+		RegValue |= XADCPS_CFR0_EC_MASK;
+	}
+
+	/*
+	 * Write the given values into the Configuration Register 0.
+	 */
+	RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+				RegValue);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the alarm outputs for the specified alarms in the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AlmEnableMask is the bit-mask of the alarm outputs to be enabled
+*		in the Configuration Register 1.
+*		Bit positions of 1 will be enabled. Bit positions of 0 will be
+*		disabled. This mask is formed by OR'ing XADCPS_CFR1_ALM_*_MASK and
+*		XADCPS_CFR1_OT_MASK masks defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		The implementation of the alarm enables in the Configuration
+*		register 1 is such that the alarms for bit positions of 1 will
+*		be disabled and alarms for bit positions of 0 will be enabled.
+*		The alarm outputs specified by the AlmEnableMask are negated
+*		before writing to the Configuration Register 1.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr, XADCPS_CFR1_OFFSET);
+
+	RegValue &= (u32)~XADCPS_CFR1_ALM_ALL_MASK;
+	RegValue |= (~AlmEnableMask & XADCPS_CFR1_ALM_ALL_MASK);
+
+	/*
+	 * Enable/disables the alarm enables for the specified alarm bits in the
+	 * Configuration Register 1.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+				RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of the alarm output enables in the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	This is the bit-mask of the enabled alarm outputs in the
+*		Configuration Register 1. Use the masks XADCPS_CFR1_ALM*_* and
+*		XADCPS_CFR1_OT_MASK defined in xadcps_hw.h to interpret the
+*		returned value.
+*		Bit positions of 1 indicate that the alarm output is enabled.
+*		Bit positions of 0 indicate that the alarm output is disabled.
+*
+*
+* @note		The implementation of the alarm enables in the Configuration
+*		register 1 is such that alarms for the bit positions of 1 will
+*		be disabled and alarms for bit positions of 0 will be enabled.
+*		The enabled alarm outputs returned by this function is the
+*		negated value of the the data read from the Configuration
+*		Register 1.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the status of alarm output enables from the Configuration
+	 * Register 1.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_ALM_ALL_MASK;
+	return (u16) (~RegValue & XADCPS_CFR1_ALM_ALL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified calibration in the Configuration
+* Register 1 :
+*
+* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : Calibration 0 -ADC offset correction
+* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : Calibration 1 -ADC gain and offset
+*						correction
+* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Calibration 2 -Power Supply sensor
+*					offset correction
+* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Calibration 3 -Power Supply sensor
+*						gain and offset correction
+* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Calibration is the Calibration to be applied.
+*		Use XADCPS_CFR1_CAL*_* bits defined in xadcps_hw.h.
+*		Multiple calibrations can be enabled at a time by oring the
+*		XADCPS_CFR1_CAL_ADC_* and XADCPS_CFR1_CAL_PS_* bits.
+*		Calibration can be disabled by specifying
+		XADCPS_CFR1_CAL_DISABLE_MASK;
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(((Calibration >= XADCPS_CFR1_CAL_ADC_OFFSET_MASK) &&
+			(Calibration <= XADCPS_CFR1_CAL_VALID_MASK)) ||
+			(Calibration == XADCPS_CFR1_CAL_DISABLE_MASK));
+
+	/*
+	 * Set the specified calibration in the Configuration Register 1.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR1_OFFSET);
+
+	RegValue &= (~ XADCPS_CFR1_CAL_VALID_MASK);
+	RegValue |= (Calibration & XADCPS_CFR1_CAL_VALID_MASK);
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the value of the calibration enables from the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The value of the calibration enables in the Configuration
+*		Register 1 :
+*		- XADCPS_CFR1_CAL_ADC_OFFSET_MASK : ADC offset correction
+*		- XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : ADC gain and offset
+*				correction
+*		- XADCPS_CFR1_CAL_PS_OFFSET_MASK : Power Supply sensor offset
+*				correction
+*		- XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Power Supply sensor
+*				gain and offset correction
+*		- XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the calibration enables from the Configuration Register 1.
+	 */
+	return (u16) XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_CAL_VALID_MASK;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the specified Channel Sequencer Mode in the Configuration
+* Register 1 :
+*		- Default safe mode (XADCPS_SEQ_MODE_SAFE)
+*		- One pass through sequence (XADCPS_SEQ_MODE_ONEPASS)
+*		- Continuous channel sequencing (XADCPS_SEQ_MODE_CONTINPASS)
+*		- Single Channel/Sequencer off (XADCPS_SEQ_MODE_SINGCHAN)
+*		- Simulataneous sampling mode (XADCPS_SEQ_MODE_SIMUL_SAMPLING)
+*		- Independent mode (XADCPS_SEQ_MODE_INDEPENDENT)
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	SequencerMode is the sequencer mode to be set.
+*		Use XADCPS_SEQ_MODE_* bits defined in xadcps.h.
+* @return	None.
+*
+* @note		Only one of the modes can be enabled at a time. Please
+*		read the Spec of the XADC for further information about the
+*		sequencer modes.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((SequencerMode <= XADCPS_SEQ_MODE_SIMUL_SAMPLING) ||
+			(SequencerMode == XADCPS_SEQ_MODE_INDEPENDENT));
+
+	/*
+	 * Set the specified sequencer mode in the Configuration Register 1.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR1_OFFSET);
+	RegValue &= (~ XADCPS_CFR1_SEQ_VALID_MASK);
+	RegValue |= ((SequencerMode  << XADCPS_CFR1_SEQ_SHIFT) &
+					XADCPS_CFR1_SEQ_VALID_MASK);
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel sequencer mode from the Configuration
+* Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The channel sequencer mode :
+*		- XADCPS_SEQ_MODE_SAFE : Default safe mode
+*		- XADCPS_SEQ_MODE_ONEPASS : One pass through sequence
+*		- XADCPS_SEQ_MODE_CONTINPASS : Continuous channel sequencing
+*		- XADCPS_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
+*		- XADCPS_SEQ_MODE_SIMUL_SAMPLING : Simulataneous sampling mode
+*		- XADCPS_SEQ_MODE_INDEPENDENT : Independent mode
+*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the channel sequencer mode from the Configuration Register 1.
+	 */
+	return ((u8) ((XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_SEQ_VALID_MASK) >>
+			XADCPS_CFR1_SEQ_SHIFT));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the frequency of the ADCCLK by configuring the DCLK to
+* ADCCLK ratio in the Configuration Register #2
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Divisor is clock divisor used to derive ADCCLK from DCLK.
+*		Valid values of the divisor are
+*		 - 0 to 255. Values 0, 1, 2 are all mapped to 2.
+*		Refer to the device specification for more details
+*
+* @return	None.
+*
+* @note		- The ADCCLK is an internal clock used by the ADC and is
+*		  synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+*		  divided by the user selection in the Configuration Register 2.
+*		- There is no Assert on the minimum value of the Divisor.
+*
+*****************************************************************************/
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Write the divisor value into the Configuration Register #2.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+			  Divisor << XADCPS_CFR2_CD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function gets the ADCCLK divisor from the Configuration Register 2.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The divisor read from the Configuration Register 2.
+*
+* @note		The ADCCLK is an internal clock used by the ADC and is
+*		synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+*		divided by the user selection in the Configuration Register 2.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr)
+{
+	u16 Divisor;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the divisor value from the Configuration Register 2.
+	 */
+	Divisor = (u16) XAdcPs_ReadInternalReg(InstancePtr,
+					 XADCPS_CFR2_OFFSET);
+
+	return (u8) (Divisor >> XADCPS_CFR2_CD_SHIFT);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified channels in the ADC Channel Selection
+* Sequencer Registers. The sequencer must be disabled before writing to these
+* regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	ChEnableMask is the bit mask of all the channels to be enabled.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+*		numbers. Bit masks of 1 will be enabled and bit mask of 0 will
+*		be disabled.
+*		The ChEnableMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Selection Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Selection Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Enable the specified channels in the ADC Channel Selection Sequencer
+	 * Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ00_OFFSET,
+				(ChEnableMask & XADCPS_SEQ00_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ01_OFFSET,
+				(ChEnableMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ01_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel enable bits status from the ADC Channel
+* Selection Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Gets the channel enable bits. Use XADCPS_SEQ_CH__* defined in
+*		xadcps_hw.h to interpret the Channel numbers. Bit masks of 1
+*		are the channels that are enabled and bit mask of 0 are
+*		the channels that are disabled.
+*
+* @return	None
+*
+* @note		None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr)
+{
+	u32 RegValEnable;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 *  Read the channel enable bits for all the channels from the ADC
+	 *  Channel Selection Register.
+	 */
+	RegValEnable = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ00_OFFSET) &
+				XADCPS_SEQ00_CH_VALID_MASK;
+	RegValEnable |= (XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ01_OFFSET) &
+				XADCPS_SEQ01_CH_VALID_MASK) <<
+				XADCPS_SEQ_CH_AUX_SHIFT;
+
+
+	return RegValEnable;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the averaging for the specified channels in the ADC
+* Channel Averaging Enable Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AvgEnableChMask is the bit mask of all the channels for which
+*		averaging is to be enabled. Use XADCPS_SEQ_CH__* defined in
+*		xadcps_hw.h to specify the Channel numbers. Averaging will be
+*		enabled for bit masks of 1 and disabled for bit mask of 0.
+*		The AvgEnableChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Averaging Enable Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Averaging Enables Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Enable/disable the averaging for the specified channels in the
+	 * ADC Channel Averaging Enables Sequencer Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ02_OFFSET,
+				(AvgEnableChMask & XADCPS_SEQ02_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ03_OFFSET,
+				(AvgEnableChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ03_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the channels for which the averaging has been enabled
+* in the ADC Channel Averaging Enables Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns 	The status of averaging (enabled/disabled) for all the channels.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		averaging is enabled and bit mask of 0 are the channels for
+*		averaging is disabled
+*
+* @note		None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr)
+{
+	u32 RegValAvg;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the averaging enable status for all the channels from the
+	 * ADC Channel Averaging Enables Sequencer Registers.
+	 */
+	RegValAvg = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ02_OFFSET) & XADCPS_SEQ02_CH_VALID_MASK;
+	RegValAvg |= (XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_SEQ03_OFFSET) & XADCPS_SEQ03_CH_VALID_MASK) <<
+			XADCPS_SEQ_CH_AUX_SHIFT;
+
+	return RegValAvg;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Analog input mode for the specified channels in the ADC
+* Channel Analog-Input Mode Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	InputModeChMask is the bit mask of all the channels for which
+*		the input mode is differential mode. Use XADCPS_SEQ_CH__* defined
+*		in xadcps_hw.h to specify the channel numbers. Differential
+*		input mode will be set for bit masks of 1 and unipolar input
+*		mode for bit masks of 0.
+*		The InputModeChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Analog-Input Mode Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set the input mode for the specified channels in the ADC Channel
+	 * Analog-Input Mode Sequencer Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ04_OFFSET,
+				(InputModeChMask & XADCPS_SEQ04_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ05_OFFSET,
+				(InputModeChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ05_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Analog input mode for all the channels from
+* the ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns 	The input mode for all the channels.
+*		Use XADCPS_SEQ_CH_* defined in xadcps_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		input mode is differential and bit mask of 0 are the channels
+*		for which input mode is unipolar.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr)
+{
+	u32 InputMode;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 *  Get the input mode for all the channels from the ADC Channel
+	 * Analog-Input Mode Sequencer Registers.
+	 */
+	InputMode = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ04_OFFSET) &
+				XADCPS_SEQ04_CH_VALID_MASK;
+	InputMode |= (XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ05_OFFSET) &
+				XADCPS_SEQ05_CH_VALID_MASK) <<
+				XADCPS_SEQ_CH_AUX_SHIFT;
+
+	return InputMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of Acquisition cycles in the ADC Channel
+* Acquisition Time Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AcqCyclesChMask is the bit mask of all the channels for which
+*		the number of acquisition cycles is to be extended.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+*		numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
+*		for bit masks of 1 and will be the default 4 ADCCLK cycles for
+*		bit masks of 0.
+*		The AcqCyclesChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Acquisition Time Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Channel Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+			XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set the Acquisition time for the specified channels in the
+	 * ADC Channel Acquisition Time Sequencer Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ06_OFFSET,
+				(AcqCyclesChMask & XADCPS_SEQ06_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ07_OFFSET,
+				(AcqCyclesChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ07_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of acquisition from the ADC Channel Acquisition
+* Time Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns 	The acquisition time for all the channels.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		acquisition cycles are extended and bit mask of 0 are the
+*		channels for which acquisition cycles are not extended.
+*
+* @note		None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr)
+{
+	u32 RegValAcq;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the Acquisition cycles for the specified channels from the ADC
+	 * Channel Acquisition Time Sequencer Registers.
+	 */
+	RegValAcq = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ06_OFFSET) &
+				XADCPS_SEQ06_CH_VALID_MASK;
+	RegValAcq |= (XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ07_OFFSET) &
+				XADCPS_SEQ07_CH_VALID_MASK) <<
+				XADCPS_SEQ_CH_AUX_SHIFT;
+
+	return RegValAcq;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the contents of the given Alarm Threshold Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AlarmThrReg is the index of an Alarm Threshold Register to
+*		be set. Use XADCPS_ATR_* constants defined in xadcps.h to
+*		specify the index.
+* @param	Value is the 16-bit threshold value to write into the register.
+*
+* @return	None.
+*
+* @note		Use XAdcPs_SetOverTemp() to set the Over Temperature upper
+*		threshold value.
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value)
+{
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+	/*
+	 * Write the value into the specified Alarm Threshold Register.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_ATR_TEMP_UPPER_OFFSET +
+					AlarmThrReg,Value);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of the specified Alarm Threshold Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AlarmThrReg is the index of an Alarm Threshold Register
+*		to be read. Use XADCPS_ATR_* constants defined in 	xadcps_hw.h
+*		to specify the index.
+*
+* @return	A 16-bit value representing the contents of the selected Alarm
+*		Threshold Register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg)
+{
+	u32 RegData;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+	/*
+	 * Read the specified Alarm Threshold Register and return
+	 * the value
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+				(XADCPS_ATR_TEMP_UPPER_OFFSET + AlarmThrReg));
+
+	return (u16) RegData;
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function enables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr)
+{
+	u16 OtUpper;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the OT upper Alarm Threshold Register.
+	 */
+	OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+				   XADCPS_ATR_OT_UPPER_OFFSET);
+	OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+	/*
+	 * Preserve the powerdown value and write OT enable value the into the
+	 * OT Upper Alarm Threshold Register.
+	 */
+	OtUpper |= XADCPS_ATR_OT_UPPER_ENB_VAL;
+	XAdcPs_WriteInternalReg(InstancePtr,
+			  XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr)
+{
+	u16 OtUpper;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the OT Upper Alarm Threshold Register.
+	 */
+	OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+					 XADCPS_ATR_OT_UPPER_OFFSET);
+	OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+			  XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The function enables the Event mode or Continuous mode in the sequencer mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	IsEventMode is a boolean parameter that specifies continuous
+*		sampling (specify FALSE) or event driven sampling mode (specify
+*		TRUE) for the given channel.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+
+	/*
+	 * Read the Configuration Register 0.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					(~XADCPS_CFR0_EC_MASK);
+
+	/*
+	 * Set the ADC mode.
+	 */
+	if (IsEventMode == TRUE) {
+		RegValue |= XADCPS_CFR0_EC_MASK;
+	} else {
+		RegValue &= ~XADCPS_CFR0_EC_MASK;
+	}
+
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+					RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function returns the sampling mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The sampling mode
+*		- 0 specifies continuous sampling
+*		- 1 specifies event driven sampling mode
+*
+* @note		None.
+*
+*****************************************************************************/
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr)
+{
+	u32 Mode;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the sampling mode from the Configuration Register 0.
+	 */
+	Mode = XAdcPs_ReadInternalReg(InstancePtr,
+				   XADCPS_CFR0_OFFSET) &
+				   XADCPS_CFR0_EC_MASK;
+	if (Mode) {
+
+		return 1;
+	}
+
+	return (0);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the External Mux mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param 	MuxMode specifies whether External Mux is used
+*		- FALSE specifies NO external MUX
+*		- TRUE specifies External Mux is used
+* @param	Channel specifies the channel to be used for the
+*		external Mux. Please read the Device Spec for which
+*		channels are valid for which mode.
+*
+* @return	None.
+*
+* @note		There is no Assert in this function for checking the channel
+*		number if the external Mux is used. The user should provide a
+*		valid channel number.
+*
+*****************************************************************************/
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((MuxMode == TRUE) || (MuxMode == FALSE));
+
+	/*
+	 * Read the Configuration Register 0.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					(~XADCPS_CFR0_MUX_MASK);
+	/*
+	 * Select the Mux mode and the channel to be used.
+	 */
+	if (MuxMode == TRUE) {
+		RegValue |= XADCPS_CFR0_MUX_MASK;
+		RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+
+	}
+
+	/*
+	 * Write the mux mode into the Configuration Register 0.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+					RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the Power Down mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param 	Mode specifies the Power Down Mode
+*		- XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+*		ADC B are enabled)
+*		- XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+*		- XADCPS_PD_MODE_XADC specifies the Power Down of
+*		both ADC A and ADC B.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Mode < XADCPS_PD_MODE_XADC);
+
+
+	/*
+	 * Read the Configuration Register 2.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR2_OFFSET) &
+					(~XADCPS_CFR2_PD_MASK);
+	/*
+	 * Select the Power Down mode.
+	 */
+	RegValue |= (Mode << XADCPS_CFR2_PD_SHIFT);
+
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+					RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Power Down mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Mode specifies the Power Down Mode
+*		- XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+*		ADC B are enabled)
+*		- XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+*		- XADCPS_PD_MODE_XADC specifies the Power Down of
+*		both ADC A and ADC B.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Power Down Mode.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR2_OFFSET) &
+					(~XADCPS_CFR2_PD_MASK);
+	/*
+	 * Return the Power Down mode.
+	 */
+	return (RegValue >> XADCPS_CFR2_PD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for writing to XADC Registers using the command FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	RegOffset is the offset of the XADC register to be written.
+* @param	Data is the data to be written.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data)
+{
+	u32 RegData;
+
+	/*
+	 * Write the Data into the FIFO Register.
+	 */
+	RegData = XAdcPs_FormatWriteData(RegOffset, Data, TRUE);
+
+	XAdcPs_WriteFifo(InstancePtr, RegData);
+
+	/* Read the Read FIFO after any write since for each write
+	 * one location of Read FIFO gets updated
+	 */
+	XAdcPs_ReadFifo(InstancePtr);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function is used for reading from the XADC Registers using the Data FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	RegOffset is the offset of the XADC register to be read.
+*
+* @return	Data read from the FIFO
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset)
+{
+
+	u32 RegData;
+
+	RegData = XAdcPs_FormatWriteData(RegOffset, 0x0, FALSE);
+
+	/* Read cmd to FIFO*/
+	XAdcPs_WriteFifo(InstancePtr, RegData);
+
+	/* Do a Dummy read */
+	RegData = XAdcPs_ReadFifo(InstancePtr);
+
+	/* Do a Dummy write to get the actual read */
+	XAdcPs_WriteFifo(InstancePtr, RegData);
+
+	/* Do the Actual read */
+	RegData = XAdcPs_ReadFifo(InstancePtr);
+
+	return RegData;
+
+}
diff --git a/XilinxProcessorIPLib/drivers/xadcps/src/xadcps.h b/XilinxProcessorIPLib/drivers/xadcps/src/xadcps.h
new file mode 100644
index 00000000..427217ab
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/xadcps/src/xadcps.h
@@ -0,0 +1,576 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.h
+*
+* The XAdcPs driver supports the Xilinx XADC/ADC device.
+*
+* The XADC/ADC device has the following features:
+*	- 10-bit, 200-KSPS (kilo samples per second)
+*		Analog-to-Digital Converter (ADC)
+*	- Monitoring of on-chip supply voltages and temperature
+*	- 1 dedicated differential analog-input pair and
+*	  16 auxiliary differential analog-input pairs
+*	- Automatic alarms based on user defined limits for the on-chip
+*	  supply voltages and temperature
+*	- Automatic Channel Sequencer, programmable averaging, programmable
+*	  acquisition time for the external inputs, unipolar or differential
+*	  input selection for the external inputs
+*	- Inbuilt Calibration
+*	- Optional interrupt request generation
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the XADC/ADC device.
+*
+*
+* <b> XADC Channel Sequencer Modes </b>
+*
+* The  XADC Channel Sequencer supports the following operating modes:
+*
+*   - <b> Default </b>: This is the default mode after power up.
+*		In this mode of operation the XADC operates in
+*		a sequence mode, monitoring the on chip sensors:
+*		Temperature, VCCINT, and VCCAUX.
+*   - <b> One pass through sequence </b>: In this mode the XADC
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers for a single pass and then stops.
+*   - <b> Continuous cycling of sequence </b>: In this mode the XADC
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers continuously.
+*   - <b> Single channel mode</b>: In this mode the XADC Channel
+*		Sequencer is disabled and the XADC operates in a
+*		Single Channel Mode.
+*		The XADC can operate either in a Continuous or Event
+*		driven sampling mode in the single channel mode.
+*   - <b> Simultaneous Sampling Mode</b>: In this mode the XADC Channel
+*		Sequencer will automatically sequence through eight fixed pairs
+*		of auxiliary analog input channels for simulataneous conversion.
+*   - <b> Independent ADC mode</b>: In this mode the first ADC (A) is used to
+*		is used to implement a fixed monitoring mode similar to the
+*		default mode but the alarm fucntions ar eenabled.
+*		The second ADC (B) is available to be used with external analog
+*		input channels only.
+*
+* Read the XADC spec for more information about the sequencer modes.
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the XADC/ADC device.
+*
+* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
+* device. The user needs to first call the XAdcPs_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XAdcPs_CfgInitialize() API.
+*
+*
+* <b>Interrupts</b>
+*
+* The XADC/ADC device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* The interrupt mode is available only if hardware is configured to support
+* interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+* <b> Building the driver </b>
+*
+* The XAdcPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <b> Limitations of the driver </b>
+*
+* XADC/ADC device can be accessed through the JTAG port and the PLB
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to care of this situation
+* in the user application code.
+*
+* <br><br>
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+*			in xadcps.c to fix CR #693371
+* 1.03a bss    11/01/13 Modified xadcps_hw.h to use correct Register offsets
+*			CR#749687
+* 2.1   bss    08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
+*			XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
+*			XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
+*			functions.
+*			Modified Assert for XAdcPs_SetSingleChParams in
+*			xadcps.c to fix CR #807563.
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XADCPS_H /* Prevent circular inclusions */
+#define XADCPS_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xadcps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XADCPS_CH_TEMP		0x0  /**< On Chip Temperature */
+#define XADCPS_CH_VCCINT	0x1  /**< VCCINT */
+#define XADCPS_CH_VCCAUX	0x2  /**< VCCAUX */
+#define XADCPS_CH_VPVN		0x3  /**< VP/VN Dedicated analog inputs */
+#define XADCPS_CH_VREFP		0x4  /**< VREFP */
+#define XADCPS_CH_VREFN		0x5  /**< VREFN */
+#define XADCPS_CH_VBRAM		0x6  /**< On-chip VBRAM Data Reg, 7 series */
+#define XADCPS_CH_SUPPLY_CALIB	0x07 /**< Supply Calib Data Reg */
+#define XADCPS_CH_ADC_CALIB	0x08 /**< ADC Offset Channel Reg */
+#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg  */
+#define XADCPS_CH_VCCPINT	0x0D /**< On-chip PS VCCPINT Channel , Zynq */
+#define XADCPS_CH_VCCPAUX	0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
+#define XADCPS_CH_VCCPDRO	0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
+#define XADCPS_CH_AUX_MIN	 16 /**< Channel number for 1st Aux Channel */
+#define XADCPS_CH_AUX_MAX	 31 /**< Channel number for Last Aux channel */
+
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XADCPS_CALIB_SUPPLY_COEFF     0 /**< Supply Offset Calib Coefficient */
+#define XADCPS_CALIB_ADC_COEFF        1 /**< ADC Offset Calib Coefficient */
+#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XADCPS_MAX_TEMP		0 /**< Maximum Temperature Data */
+#define XADCPS_MAX_VCCINT	1 /**< Maximum VCCINT Data */
+#define XADCPS_MAX_VCCAUX	2 /**< Maximum VCCAUX Data */
+#define XADCPS_MAX_VBRAM	3 /**< Maximum VBRAM Data */
+#define XADCPS_MIN_TEMP		4 /**< Minimum Temperature Data */
+#define XADCPS_MIN_VCCINT	5 /**< Minimum VCCINT Data */
+#define XADCPS_MIN_VCCAUX	6 /**< Minimum VCCAUX Data */
+#define XADCPS_MIN_VBRAM	7 /**< Minimum VBRAM Data */
+#define XADCPS_MAX_VCCPINT	8 /**< Maximum VCCPINT Register , Zynq */
+#define XADCPS_MAX_VCCPAUX	9 /**< Maximum VCCPAUX Register , Zynq */
+#define XADCPS_MAX_VCCPDRO	0xA /**< Maximum VCCPDRO Register , Zynq */
+#define XADCPS_MIN_VCCPINT	0xC /**< Minimum VCCPINT Register , Zynq */
+#define XADCPS_MIN_VCCPAUX	0xD /**< Minimum VCCPAUX Register , Zynq */
+#define XADCPS_MIN_VCCPDRO	0xE /**< Minimum VCCPDRO Register , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XADCPS_ATR_TEMP_UPPER	 0 /**< High user Temperature */
+#define XADCPS_ATR_VCCINT_UPPER  1 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_UPPER  2 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_OT_UPPER	 3 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_TEMP_LOWER	 4 /**< Upper Over Temperature limit Reg */
+#define XADCPS_ATR_VCCINT_LOWER	 5 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_LOWER	 6 /**< VCCAUX low voltage limit register  */
+#define XADCPS_ATR_OT_LOWER	 7 /**< Lower Over Temperature limit */
+#define XADCPS_ATR_VBRAM_UPPER_  8 /**< VRBAM Upper Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER	 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XADCPS_AVG_0_SAMPLES	0  /**< No Averaging */
+#define XADCPS_AVG_16_SAMPLES	1  /**< Average 16 samples */
+#define XADCPS_AVG_64_SAMPLES	2  /**< Average 64 samples */
+#define XADCPS_AVG_256_SAMPLES	3  /**< Average 256 samples */
+
+/*@}*/
+
+
+/**
+ * @name Channel Sequencer Modes of operation
+ * @{
+ */
+#define XADCPS_SEQ_MODE_SAFE		0  /**< Default Safe Mode */
+#define XADCPS_SEQ_MODE_ONEPASS		1  /**< Onepass through Sequencer */
+#define XADCPS_SEQ_MODE_CONTINPASS	2  /**< Continuous Cycling Sequencer */
+#define XADCPS_SEQ_MODE_SINGCHAN	3  /**< Single channel -No Sequencing */
+#define XADCPS_SEQ_MODE_SIMUL_SAMPLING	4  /**< Simultaneous sampling */
+#define XADCPS_SEQ_MODE_INDEPENDENT	8  /**< Independent mode */
+
+/*@}*/
+
+
+
+/**
+ * @name Power Down Modes
+ * @{
+ */
+#define XADCPS_PD_MODE_NONE		0  /**< No Power Down  */
+#define XADCPS_PD_MODE_ADCB		1  /**< Power Down ADC B */
+#define XADCPS_PD_MODE_XADC		2  /**< Power Down ADC A and ADC B */
+/*@}*/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XADC/ADC
+ * device.
+ */
+typedef struct {
+	u16  DeviceId;		/**< Unique ID of device */
+	u32  BaseAddress;	/**< Device base address */
+} XAdcPs_Config;
+
+
+/**
+ * The driver's instance data. The user is required to allocate a variable
+ * of this type for every XADC/ADC device in the system. A pointer to
+ * a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XAdcPs_Config Config;	/**< XAdcPs_Config of current device */
+	u32  IsReady;		/**< Device is initialized and ready  */
+
+} XAdcPs;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in Event Sampling mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- TRUE if the device is in Event Sampling Mode.
+*		- FALSE if the device is in Continuous Sampling Mode.
+*
+* @note		C-Style signature:
+*		int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsEventSamplingModeSet(InstancePtr)			\
+	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ?	\
+			TRUE : FALSE))
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in External Mux mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- TRUE if the device is in External Mux Mode.
+*		- FALSE if the device is NOT in External Mux Mode.
+*
+* @note		C-Style signature:
+*		int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsExternalMuxModeSet(InstancePtr)			\
+	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ?	\
+			TRUE : FALSE))
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC Raw Data to Temperature(centigrades).
+*
+* @param	AdcData is the Raw ADC Data from XADC.
+*
+* @return 	The Temperature in centigrades.
+*
+* @note		C-Style signature:
+*		float XAdcPs_RawToTemperature(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToTemperature(AdcData)				\
+	((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC/ADC Raw Data to Voltage(volts).
+*
+* @param	AdcData is the XADC/ADC Raw Data.
+*
+* @return 	The Voltage in volts.
+*
+* @note		C-Style signature:
+*		float XAdcPs_RawToVoltage(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToVoltage(AdcData) 					\
+	((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
+*
+* @param	Temperature is the Temperature in centigrades to be
+*		converted to XADC/ADC Raw Data.
+*
+* @return 	The XADC/ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XAdcPs_TemperatureToRaw(float Temperature);
+*
+*****************************************************************************/
+#define XAdcPs_TemperatureToRaw(Temperature)				\
+	((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to XADC/ADC Raw Data.
+*
+* @param	Voltage is the Voltage in volts to be converted to
+*		XADC/ADC Raw Data.
+*
+* @return 	The XADC/ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XAdcPs_VoltageToRaw(float Voltage);
+*
+*****************************************************************************/
+#define XAdcPs_VoltageToRaw(Voltage)			 		\
+	((int)((Voltage)*65536.0f/3.0f))
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for writing to the XADC Registers using the
+* command FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XAdcPs_WriteFifo(InstancePtr, Data)				\
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,		\
+			  XADCPS_CMDFIFO_OFFSET, Data);
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for reading from the XADC Registers using the
+* data FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Data read from the FIFO
+*
+* @note		C-Style signature:
+*		u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_ReadFifo(InstancePtr)				\
+	XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,	\
+			  XADCPS_RDFIFO_OFFSET);
+
+
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ * Functions in xadcps_sinit.c
+ */
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
+
+/**
+ * Functions in xadcps.c
+ */
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
+				XAdcPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+
+
+u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
+
+u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
+
+void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
+
+void XAdcPs_Reset(XAdcPs *InstancePtr);
+
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
+
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
+
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
+
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+				u8 Channel,
+				int IncreaseAcqCycles,
+				int IsEventMode,
+				int IsDifferentialMode);
+
+
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
+
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
+
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
+
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
+
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_selftest.c
+ */
+int XAdcPs_SelfTest(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_intr.c
+ */
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
+
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
diff --git a/XilinxProcessorIPLib/drivers/xadcps/src/xadcps_g.c b/XilinxProcessorIPLib/drivers/xadcps/src/xadcps_g.c
new file mode 100644
index 00000000..8442dd72
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/xadcps/src/xadcps_g.c
@@ -0,0 +1,82 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_g.c
+*
+* This file contains a configuration table that specifies the configuration
+* of XADC devices in the system when accessing through the Device Config
+* interface in Zynq.
+*
+* See xadcps.h for more information about this driver.
+*
+* @note None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xadcps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Prototypes ******************************/
+
+/**
+ * This table contains configuration information for each XADC Monitor/ADC
+ * device in the system.
+ */
+XAdcPs_Config XAdcPs_ConfigTable[XPAR_XADCPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_XADCPS_0_DEVICE_ID,	/**< Unique ID of device */
+		XPAR_XADCPS_0_BASEADDR		/**< Base address of device */
+	}
+};
diff --git a/XilinxProcessorIPLib/drivers/xadcps/src/xadcps_hw.h b/XilinxProcessorIPLib/drivers/xadcps/src/xadcps_hw.h
new file mode 100644
index 00000000..a4b712bb
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/xadcps/src/xadcps_hw.h
@@ -0,0 +1,499 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps_hw.h
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the XADC device through the Device
+* Config Interface of the Zynq.
+*
+*
+* Refer to the device specification for more information about this driver.
+*
+* @note	 None.
+*
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss    11/01/13 Modified macros to use correct Register offsets
+*			CR#749687
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XADCPS_HW_H /* Prevent circular inclusions */
+#define XADCPS_HW_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**@name Register offsets of XADC in the Device Config
+ *
+ * The following constants provide access to each of the registers of the
+ * XADC device.
+ * @{
+ */
+
+#define XADCPS_CFG_OFFSET	 0x00 /**< Configuration Register */
+#define XADCPS_INT_STS_OFFSET	 0x04 /**< Interrupt Status Register */
+#define XADCPS_INT_MASK_OFFSET	 0x08 /**< Interrupt Mask Register */
+#define XADCPS_MSTS_OFFSET	 0x0C /**< Misc status register */
+#define XADCPS_CMDFIFO_OFFSET	 0x10 /**< Command FIFO Register */
+#define XADCPS_RDFIFO_OFFSET	 0x14 /**< Read FIFO Register */
+#define XADCPS_MCTL_OFFSET	 0x18 /**< Misc control register */
+
+/* @} */
+
+
+
+
+
+/** @name XADC Config Register Bit definitions
+  * @{
+ */
+#define XADCPS_CFG_ENABLE_MASK	 0x80000000 /**< Enable access from PS mask */
+#define XADCPS_CFG_CFIFOTH_MASK  0x00F00000 /**< Command FIFO Threshold mask */
+#define XADCPS_CFG_DFIFOTH_MASK  0x000F0000 /**< Data FIFO Threshold mask */
+#define XADCPS_CFG_WEDGE_MASK	 0x00002000 /**< Write Edge Mask */
+#define XADCPS_CFG_REDGE_MASK	 0x00001000 /**< Read Edge Mask */
+#define XADCPS_CFG_TCKRATE_MASK  0x00000300 /**< Clock freq control */
+#define XADCPS_CFG_IGAP_MASK	 0x0000001F /**< Idle Gap between
+						* successive commands */
+/* @} */
+
+
+/** @name XADC Interrupt Status/Mask Register Bit definitions
+  *
+  * The definitions are same for the Interrupt Status Register and
+  * Interrupt Mask Register. They are defined only once.
+  * @{
+ */
+#define XADCPS_INTX_ALL_MASK   	   0x000003FF /**< Alarm Signals Mask  */
+#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
+#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
+#define XADCPS_INTX_OT_MASK	   0x00000080 /**< Over temperature Alarm Status */
+#define XADCPS_INTX_ALM_ALL_MASK   0x0000007F /**< Alarm Signals Mask  */
+#define XADCPS_INTX_ALM6_MASK	   0x00000040 /**< Alarm 6 Mask  */
+#define XADCPS_INTX_ALM5_MASK	   0x00000020 /**< Alarm 5 Mask  */
+#define XADCPS_INTX_ALM4_MASK	   0x00000010 /**< Alarm 4 Mask  */
+#define XADCPS_INTX_ALM3_MASK	   0x00000008 /**< Alarm 3 Mask  */
+#define XADCPS_INTX_ALM2_MASK	   0x00000004 /**< Alarm 2 Mask  */
+#define XADCPS_INTX_ALM1_MASK	   0x00000002 /**< Alarm 1 Mask  */
+#define XADCPS_INTX_ALM0_MASK	   0x00000001 /**< Alarm 0 Mask  */
+
+/* @} */
+
+
+/** @name XADC Miscellaneous Register Bit definitions
+  * @{
+ */
+#define XADCPS_MSTS_CFIFO_LVL_MASK  0x000F0000 /**< Command FIFO Level mask */
+#define XADCPS_MSTS_DFIFO_LVL_MASK  0x0000F000 /**< Data FIFO Level Mask  */
+#define XADCPS_MSTS_CFIFOF_MASK     0x00000800 /**< Command FIFO Full Mask  */
+#define XADCPS_MSTS_CFIFOE_MASK     0x00000400 /**< Command FIFO Empty Mask  */
+#define XADCPS_MSTS_DFIFOF_MASK     0x00000200 /**< Data FIFO Full Mask  */
+#define XADCPS_MSTS_DFIFOE_MASK     0x00000100 /**< Data FIFO Empty Mask  */
+#define XADCPS_MSTS_OT_MASK	    0x00000080 /**< Over Temperature Mask */
+#define XADCPS_MSTS_ALM_MASK	    0x0000007F /**< Alarms Mask  */
+/* @} */
+
+
+/** @name XADC Miscellaneous Control Register Bit definitions
+  * @{
+ */
+#define XADCPS_MCTL_RESET_MASK      0x00000010 /**< Reset XADC */
+#define XADCPS_MCTL_FLUSH_MASK      0x00000001 /**< Flush the FIFOs */
+/* @} */
+
+
+/**@name Internal Register offsets of the XADC
+ *
+ * The following constants provide access to each of the internal registers of
+ * the XADC device.
+ * @{
+ */
+
+/*
+ * XADC Internal Channel Registers
+ */
+#define XADCPS_TEMP_OFFSET		  0x00 /**< On-chip Temperature Reg */
+#define XADCPS_VCCINT_OFFSET		  0x01 /**< On-chip VCCINT Data Reg */
+#define XADCPS_VCCAUX_OFFSET		  0x02 /**< On-chip VCCAUX Data Reg */
+#define XADCPS_VPVN_OFFSET		  0x03 /**< ADC out of VP/VN	   */
+#define XADCPS_VREFP_OFFSET		  0x04 /**< On-chip VREFP Data Reg */
+#define XADCPS_VREFN_OFFSET		  0x05 /**< On-chip VREFN Data Reg */
+#define XADCPS_VBRAM_OFFSET		  0x06 /**< On-chip VBRAM , 7 Series */
+#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET  0x08 /**< ADC A Supply Offset Reg */
+#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET  0x09 /**< ADC A Offset Data Reg */
+#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg  */
+#define XADCPS_VCCPINT_OFFSET		  0x0D /**< On-chip VCCPINT Reg, Zynq */
+#define XADCPS_VCCPAUX_OFFSET		  0x0E /**< On-chip VCCPAUX Reg, Zynq */
+#define XADCPS_VCCPDRO_OFFSET		  0x0F /**< On-chip VCCPDRO Reg, Zynq */
+
+/*
+ * XADC External Channel Registers
+ */
+#define XADCPS_AUX00_OFFSET	0x10 /**< ADC out of VAUXP0/VAUXN0 */
+#define XADCPS_AUX01_OFFSET	0x11 /**< ADC out of VAUXP1/VAUXN1 */
+#define XADCPS_AUX02_OFFSET	0x12 /**< ADC out of VAUXP2/VAUXN2 */
+#define XADCPS_AUX03_OFFSET	0x13 /**< ADC out of VAUXP3/VAUXN3 */
+#define XADCPS_AUX04_OFFSET	0x14 /**< ADC out of VAUXP4/VAUXN4 */
+#define XADCPS_AUX05_OFFSET	0x15 /**< ADC out of VAUXP5/VAUXN5 */
+#define XADCPS_AUX06_OFFSET	0x16 /**< ADC out of VAUXP6/VAUXN6 */
+#define XADCPS_AUX07_OFFSET	0x17 /**< ADC out of VAUXP7/VAUXN7 */
+#define XADCPS_AUX08_OFFSET	0x18 /**< ADC out of VAUXP8/VAUXN8 */
+#define XADCPS_AUX09_OFFSET	0x19 /**< ADC out of VAUXP9/VAUXN9 */
+#define XADCPS_AUX10_OFFSET	0x1A /**< ADC out of VAUXP10/VAUXN10 */
+#define XADCPS_AUX11_OFFSET	0x1B /**< ADC out of VAUXP11/VAUXN11 */
+#define XADCPS_AUX12_OFFSET	0x1C /**< ADC out of VAUXP12/VAUXN12 */
+#define XADCPS_AUX13_OFFSET	0x1D /**< ADC out of VAUXP13/VAUXN13 */
+#define XADCPS_AUX14_OFFSET	0x1E /**< ADC out of VAUXP14/VAUXN14 */
+#define XADCPS_AUX15_OFFSET	0x1F /**< ADC out of VAUXP15/VAUXN15 */
+
+/*
+ * XADC Registers for Maximum/Minimum data captured for the
+ * on chip Temperature/VCCINT/VCCAUX data.
+ */
+#define XADCPS_MAX_TEMP_OFFSET		0x20 /**< Max Temperature Reg */
+#define XADCPS_MAX_VCCINT_OFFSET	0x21 /**< Max VCCINT Register */
+#define XADCPS_MAX_VCCAUX_OFFSET	0x22 /**< Max VCCAUX Register */
+#define XADCPS_MAX_VCCBRAM_OFFSET	0x23 /**< Max BRAM Register, 7 series */
+#define XADCPS_MIN_TEMP_OFFSET		0x24 /**< Min Temperature Reg */
+#define XADCPS_MIN_VCCINT_OFFSET	0x25 /**< Min VCCINT Register */
+#define XADCPS_MIN_VCCAUX_OFFSET	0x26 /**< Min VCCAUX Register */
+#define XADCPS_MIN_VCCBRAM_OFFSET	0x27 /**< Min BRAM Register, 7 series */
+#define XADCPS_MAX_VCCPINT_OFFSET	0x28 /**< Max VCCPINT Register, Zynq */
+#define XADCPS_MAX_VCCPAUX_OFFSET	0x29 /**< Max VCCPAUX Register, Zynq */
+#define XADCPS_MAX_VCCPDRO_OFFSET	0x2A /**< Max VCCPDRO Register, Zynq */
+#define XADCPS_MIN_VCCPINT_OFFSET	0x2C /**< Min VCCPINT Register, Zynq */
+#define XADCPS_MIN_VCCPAUX_OFFSET	0x2D /**< Min VCCPAUX Register, Zynq */
+#define XADCPS_MIN_VCCPDRO_OFFSET	0x2E /**< Min VCCPDRO Register,Zynq */
+ /* Undefined 0x2F to 0x3E */
+#define XADCPS_FLAG_OFFSET		0x3F /**< Flag Register */
+
+/*
+ * XADC Configuration Registers
+ */
+#define XADCPS_CFR0_OFFSET	0x40	/**< Configuration Register 0 */
+#define XADCPS_CFR1_OFFSET	0x41	/**< Configuration Register 1 */
+#define XADCPS_CFR2_OFFSET	0x42	/**< Configuration Register 2 */
+
+/* Test Registers 0x43 to 0x47 */
+
+/*
+ * XADC Sequence Registers
+ */
+#define XADCPS_SEQ00_OFFSET	0x48 /**< Seq Reg 00 Adc Channel Selection */
+#define XADCPS_SEQ01_OFFSET	0x49 /**< Seq Reg 01 Adc Channel Selection */
+#define XADCPS_SEQ02_OFFSET	0x4A /**< Seq Reg 02 Adc Average Enable */
+#define XADCPS_SEQ03_OFFSET	0x4B /**< Seq Reg 03 Adc Average Enable */
+#define XADCPS_SEQ04_OFFSET	0x4C /**< Seq Reg 04 Adc Input Mode Select */
+#define XADCPS_SEQ05_OFFSET	0x4D /**< Seq Reg 05 Adc Input Mode Select */
+#define XADCPS_SEQ06_OFFSET	0x4E /**< Seq Reg 06 Adc Acquisition Select */
+#define XADCPS_SEQ07_OFFSET	0x4F /**< Seq Reg 07 Adc Acquisition Select */
+
+/*
+ * XADC Alarm Threshold/Limit Registers (ATR)
+ */
+#define XADCPS_ATR_TEMP_UPPER_OFFSET	0x50 /**< Temp Upper Alarm Register */
+#define XADCPS_ATR_VCCINT_UPPER_OFFSET	0x51 /**< VCCINT Upper Alarm Reg */
+#define XADCPS_ATR_VCCAUX_UPPER_OFFSET	0x52 /**< VCCAUX Upper Alarm Reg */
+#define XADCPS_ATR_OT_UPPER_OFFSET	0x53 /**< Over Temp Upper Alarm Reg */
+#define XADCPS_ATR_TEMP_LOWER_OFFSET	0x54 /**< Temp Lower Alarm Register */
+#define XADCPS_ATR_VCCINT_LOWER_OFFSET	0x55 /**< VCCINT Lower Alarm Reg */
+#define XADCPS_ATR_VCCAUX_LOWER_OFFSET	0x56 /**< VCCAUX Lower Alarm Reg */
+#define XADCPS_ATR_OT_LOWER_OFFSET	0x57 /**< Over Temp Lower Alarm Reg */
+#define XADCPS_ATR_VBRAM_UPPER_OFFSET	0x58 /**< VBRAM Upper Alarm, 7 series */
+#define XADCPS_ATR_VCCPINT_UPPER_OFFSET	0x59 /**< VCCPINT Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET	0x5A /**< VCCPAUX Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET	0x5B /**< VCCPDRO Upper Alarm, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER_OFFSET	0x5C /**< VRBAM Lower Alarm, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER_OFFSET	0x5D /**< VCCPINT Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET	0x5E /**< VCCPAUX Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET	0x5F /**< VCCPDRO Lower Alarm, Zynq */
+
+/* Undefined 0x60 to 0x7F */
+
+/*@}*/
+
+
+
+/**
+ * @name Configuration Register 0 (CFR0) mask(s)
+ * @{
+ */
+#define XADCPS_CFR0_CAL_AVG_MASK	0x8000 /**< Averaging enable Mask */
+#define XADCPS_CFR0_AVG_VALID_MASK	0x3000 /**< Averaging bit Mask */
+#define XADCPS_CFR0_AVG1_MASK		0x0000 /**< No Averaging */
+#define XADCPS_CFR0_AVG16_MASK		0x1000 /**< Average 16 samples */
+#define XADCPS_CFR0_AVG64_MASK	 	0x2000 /**< Average 64 samples */
+#define XADCPS_CFR0_AVG256_MASK 	0x3000 /**< Average 256 samples */
+#define XADCPS_CFR0_AVG_SHIFT	 	12     /**< Averaging bits shift */
+#define XADCPS_CFR0_MUX_MASK	 	0x0800 /**< External Mask Enable */
+#define XADCPS_CFR0_DU_MASK	 	0x0400 /**< Bipolar/Unipolar mode */
+#define XADCPS_CFR0_EC_MASK	 	0x0200 /**< Event driven/
+						 *  Continuous mode selection
+						 */
+#define XADCPS_CFR0_ACQ_MASK	 	0x0100 /**< Add acquisition by 6 ADCCLK */
+#define XADCPS_CFR0_CHANNEL_MASK	0x001F /**< Channel number bit Mask */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 1 (CFR1) mask(s)
+ * @{
+ */
+#define XADCPS_CFR1_SEQ_VALID_MASK	  0xF000 /**< Sequence bit Mask */
+#define XADCPS_CFR1_SEQ_SAFEMODE_MASK	  0x0000 /**< Default Safe Mode */
+#define XADCPS_CFR1_SEQ_ONEPASS_MASK	  0x1000 /**< Onepass through Seq */
+#define XADCPS_CFR1_SEQ_CONTINPASS_MASK	     0x2000 /**< Continuous Cycling Seq */
+#define XADCPS_CFR1_SEQ_SINGCHAN_MASK	     0x3000 /**< Single channel - No Seq */
+#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK  0x4000 /**< Simulataneous Sampling Mask */
+#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK  0x8000 /**< Independent Mode */
+#define XADCPS_CFR1_SEQ_SHIFT		  12     /**< Sequence bit shift */
+#define XADCPS_CFR1_ALM_VCCPDRO_MASK	  0x0800 /**< Alm 6 - VCCPDRO, Zynq  */
+#define XADCPS_CFR1_ALM_VCCPAUX_MASK	  0x0400 /**< Alm 5 - VCCPAUX, Zynq */
+#define XADCPS_CFR1_ALM_VCCPINT_MASK	  0x0200 /**< Alm 4 - VCCPINT, Zynq */
+#define XADCPS_CFR1_ALM_VBRAM_MASK	  0x0100 /**< Alm 3 - VBRAM, 7 series */
+#define XADCPS_CFR1_CAL_VALID_MASK	  0x00F0 /**< Valid Calibration Mask */
+#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK  0x0080 /**< Calibration 3 -Power
+							Supply Gain/Offset
+							Enable */
+#define XADCPS_CFR1_CAL_PS_OFFSET_MASK	  0x0040 /**< Calibration 2 -Power
+							Supply Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
+							Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK	 0x0010 /**< Calibration 0 -ADC Offset
+							Enable */
+#define XADCPS_CFR1_CAL_DISABLE_MASK	0x0000 /**< No Calibration */
+#define XADCPS_CFR1_ALM_ALL_MASK	0x0F0F /**< Mask for all alarms */
+#define XADCPS_CFR1_ALM_VCCAUX_MASK	0x0008 /**< Alarm 2 - VCCAUX Enable */
+#define XADCPS_CFR1_ALM_VCCINT_MASK	0x0004 /**< Alarm 1 - VCCINT Enable */
+#define XADCPS_CFR1_ALM_TEMP_MASK	0x0002 /**< Alarm 0 - Temperature */
+#define XADCPS_CFR1_OT_MASK		0x0001 /**< Over Temperature Enable */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 2 (CFR2) mask(s)
+ * @{
+ */
+#define XADCPS_CFR2_CD_VALID_MASK	0xFF00  /**<Clock Divisor bit Mask   */
+#define XADCPS_CFR2_CD_SHIFT		8	/**<Num of shift on division */
+#define XADCPS_CFR2_CD_MIN		8	/**<Minimum value of divisor */
+#define XADCPS_CFR2_CD_MAX		255	/**<Maximum value of divisor */
+
+#define XADCPS_CFR2_CD_MIN		8	/**<Minimum value of divisor */
+#define XADCPS_CFR2_PD_MASK		0x0030	/**<Power Down Mask */
+#define XADCPS_CFR2_PD_XADC_MASK	0x0030	/**<Power Down XADC Mask */
+#define XADCPS_CFR2_PD_ADC1_MASK	0x0020	/**<Power Down ADC1 Mask */
+#define XADCPS_CFR2_PD_SHIFT		4	/**<Power Down Shift */
+/*@}*/
+
+/**
+ * @name Sequence Register (SEQ) Bit Definitions
+ * @{
+ */
+#define XADCPS_SEQ_CH_CALIB	0x00000001 /**< ADC Calibration Channel */
+#define XADCPS_SEQ_CH_VCCPINT	0x00000020 /**< VCCPINT, Zynq Only */
+#define XADCPS_SEQ_CH_VCCPAUX	0x00000040 /**< VCCPAUX, Zynq Only */
+#define XADCPS_SEQ_CH_VCCPDRO	0x00000080 /**< VCCPDRO, Zynq Only */
+#define XADCPS_SEQ_CH_TEMP	0x00000100 /**< On Chip Temperature Channel */
+#define XADCPS_SEQ_CH_VCCINT	0x00000200 /**< VCCINT Channel */
+#define XADCPS_SEQ_CH_VCCAUX	0x00000400 /**< VCCAUX Channel */
+#define XADCPS_SEQ_CH_VPVN	0x00000800 /**< VP/VN analog inputs Channel */
+#define XADCPS_SEQ_CH_VREFP	0x00001000 /**< VREFP Channel */
+#define XADCPS_SEQ_CH_VREFN	0x00002000 /**< VREFN Channel */
+#define XADCPS_SEQ_CH_VBRAM	0x00004000 /**< VBRAM Channel, 7 series */
+#define XADCPS_SEQ_CH_AUX00	0x00010000 /**< 1st Aux Channel */
+#define XADCPS_SEQ_CH_AUX01	0x00020000 /**< 2nd Aux Channel */
+#define XADCPS_SEQ_CH_AUX02	0x00040000 /**< 3rd Aux Channel */
+#define XADCPS_SEQ_CH_AUX03	0x00080000 /**< 4th Aux Channel */
+#define XADCPS_SEQ_CH_AUX04	0x00100000 /**< 5th Aux Channel */
+#define XADCPS_SEQ_CH_AUX05	0x00200000 /**< 6th Aux Channel */
+#define XADCPS_SEQ_CH_AUX06	0x00400000 /**< 7th Aux Channel */
+#define XADCPS_SEQ_CH_AUX07	0x00800000 /**< 8th Aux Channel */
+#define XADCPS_SEQ_CH_AUX08	0x01000000 /**< 9th Aux Channel */
+#define XADCPS_SEQ_CH_AUX09	0x02000000 /**< 10th Aux Channel */
+#define XADCPS_SEQ_CH_AUX10	0x04000000 /**< 11th Aux Channel */
+#define XADCPS_SEQ_CH_AUX11	0x08000000 /**< 12th Aux Channel */
+#define XADCPS_SEQ_CH_AUX12	0x10000000 /**< 13th Aux Channel */
+#define XADCPS_SEQ_CH_AUX13	0x20000000 /**< 14th Aux Channel */
+#define XADCPS_SEQ_CH_AUX14	0x40000000 /**< 15th Aux Channel */
+#define XADCPS_SEQ_CH_AUX15	0x80000000 /**< 16th Aux Channel */
+
+#define XADCPS_SEQ00_CH_VALID_MASK  0x7FE1 /**< Mask for the valid channels */
+#define XADCPS_SEQ01_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
+
+#define XADCPS_SEQ02_CH_VALID_MASK  0x7FE0 /**< Mask for the valid channels */
+#define XADCPS_SEQ03_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
+
+#define XADCPS_SEQ04_CH_VALID_MASK  0x0800 /**< Mask for the valid channels */
+#define XADCPS_SEQ05_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
+
+#define XADCPS_SEQ06_CH_VALID_MASK  0x0800 /**< Mask for the valid channels */
+#define XADCPS_SEQ07_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
+
+
+#define XADCPS_SEQ_CH_AUX_SHIFT	16 /**< Shift for the Aux Channel */
+
+/*@}*/
+
+/**
+ * @name OT Upper Alarm Threshold Register Bit Definitions
+ * @{
+ */
+
+#define XADCPS_ATR_OT_UPPER_ENB_MASK	0x000F /**< Mask for OT enable */
+#define XADCPS_ATR_OT_UPPER_VAL_MASK	0xFFF0 /**< Mask for OT value */
+#define XADCPS_ATR_OT_UPPER_VAL_SHIFT	4      /**< Shift for OT value */
+#define XADCPS_ATR_OT_UPPER_ENB_VAL	0x0003 /**< Value for OT enable */
+#define XADCPS_ATR_OT_UPPER_VAL_MAX	0x0FFF /**< Max OT value */
+
+/*@}*/
+
+
+/**
+ * @name JTAG DRP Bit Definitions
+ * @{
+ */
+#define XADCPS_JTAG_DATA_MASK		0x0000FFFF /**< Mask for the Data */
+#define XADCPS_JTAG_ADDR_MASK		0x03FF0000 /**< Mask for the Addr */
+#define XADCPS_JTAG_ADDR_SHIFT		16	   /**< Shift for the Addr */
+#define XADCPS_JTAG_CMD_MASK		0x3C000000 /**< Mask for the Cmd */
+#define XADCPS_JTAG_CMD_WRITE_MASK	0x08000000 /**< Mask for CMD Write */
+#define XADCPS_JTAG_CMD_READ_MASK	0x04000000 /**< Mask for CMD Read */
+#define XADCPS_JTAG_CMD_SHIFT		26	   /**< Shift for the Cmd */
+
+/*@}*/
+
+/** @name Unlock Register Definitions
+  * @{
+ */
+ #define XADCPS_UNLK_OFFSET	 0x034 /**< Unlock Register */
+ #define XADCPS_UNLK_VALUE	 0x757BDF0D /**< Unlock Value */
+
+ /* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* Read a register of the XADC device. This macro provides register
+* access to all registers using the register offsets defined above.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset is the offset of the register to read.
+*
+* @return	The contents of the register.
+*
+* @note		C-style Signature:
+*		u32 XAdcPs_ReadReg(u32 BaseAddress, u32 RegOffset);
+*
+******************************************************************************/
+#define XAdcPs_ReadReg(BaseAddress, RegOffset) \
+			(Xil_In32((BaseAddress) + (RegOffset)))
+
+/*****************************************************************************/
+/**
+*
+* Write a register of the XADC device. This macro provides
+* register access to all registers using the register offsets defined above.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset is the offset of the register to write.
+* @param	Data is the value to write to the register.
+*
+* @return	None.
+*
+* @note 	C-style Signature:
+*		void XAdcPs_WriteReg(u32 BaseAddress,
+*					u32 RegOffset,u32 Data)
+*
+******************************************************************************/
+#define XAdcPs_WriteReg(BaseAddress, RegOffset, Data) \
+		(Xil_Out32((BaseAddress) + (RegOffset), (Data)))
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Formats the data to be written to the the XADC registers.
+*
+* @param	RegOffset is the offset of the Register
+* @param	Data is the data to be written to the Register if it is
+*		a write.
+* @param	ReadWrite specifies whether it is a Read or a Write.
+*		Use 0 for Read, 1 for Write.
+*
+* @return	None.
+*
+* @note 	C-style Signature:
+*		void XAdcPs_FormatWriteData(u32 RegOffset,
+*					     u16 Data, int ReadWrite)
+*
+******************************************************************************/
+#define XAdcPs_FormatWriteData(RegOffset, Data, ReadWrite) 	    \
+    ((ReadWrite ? XADCPS_JTAG_CMD_WRITE_MASK : XADCPS_JTAG_CMD_READ_MASK ) | \
+     ((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) | 	     \
+     (Data & XADCPS_JTAG_DATA_MASK))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
diff --git a/XilinxProcessorIPLib/drivers/xadcps/src/xadcps_intr.c b/XilinxProcessorIPLib/drivers/xadcps/src/xadcps_intr.c
new file mode 100644
index 00000000..1e3222da
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/xadcps/src/xadcps_intr.c
@@ -0,0 +1,247 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_intr.c
+*
+* This file contains interrupt handling API functions of the XADC
+* device.
+*
+* The device must be configured at hardware build time to support interrupt
+* for all the functions in this file to work.
+*
+* Refer to xadcps.h header file and device specification for more information.
+*
+* @note
+*
+* Calling the interrupt functions without including the interrupt component will
+* result in asserts if asserts are enabled, and will result in a unpredictable
+* behavior if the asserts are not enabled.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified interrupts in the device.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Mask is the bit-mask of the interrupts to be enabled.
+*		Bit positions of 1 will be enabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XADCPS_INTX_* bits defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable the specified interrupts in the IPIER.
+	 */
+	RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XADCPS_INT_MASK_OFFSET);
+	RegValue &= ~(Mask & XADCPS_INTX_ALL_MASK);
+	XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_MASK_OFFSET,
+				RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function disables the specified interrupts in the device.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Mask is the bit-mask of the interrupts to be disabled.
+*		Bit positions of 1 will be disabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XADCPS_INTX_* bits defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Enable the specified interrupts in the IPIER.
+	 */
+	RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XADCPS_INT_MASK_OFFSET);
+	RegValue |= (Mask & XADCPS_INTX_ALL_MASK);
+	XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_MASK_OFFSET,
+				RegValue);
+}
+/****************************************************************************/
+/**
+*
+* This function returns the enabled interrupts read from the Interrupt Mask
+* Register (IPIER). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h to
+* interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the I.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Return the value read from the Interrupt Enable Register.
+	 */
+	return (~ XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_MASK_OFFSET) & XADCPS_INTX_ALL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt status read from Interrupt Status
+* Register(IPISR). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h
+* to interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the IPISR.
+*
+* @note		The device must be configured at hardware build time to include
+*		interrupt component for this function to work.
+*
+*****************************************************************************/
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Return the value read from the Interrupt Status register.
+	 */
+	return XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_STS_OFFSET) & XADCPS_INTX_ALL_MASK;
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified interrupts in the Interrupt Status
+* Register (IPISR).
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Mask is the bit-mask of the interrupts to be cleared.
+*		Bit positions of 1 will be cleared. Bit positions of 0 will not
+* 		change the previous interrupt status. This mask is formed by
+* 		OR'ing XADCPS_IPIXR_* bits which are defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Clear the specified interrupts in the Interrupt Status register.
+	 */
+	RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XADCPS_INT_STS_OFFSET);
+	RegValue &= (Mask & XADCPS_INTX_ALL_MASK);
+	XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, XADCPS_INT_STS_OFFSET,
+			  RegValue);
+
+}
diff --git a/XilinxProcessorIPLib/drivers/xadcps/src/xadcps_selftest.c b/XilinxProcessorIPLib/drivers/xadcps/src/xadcps_selftest.c
new file mode 100644
index 00000000..3964283f
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/xadcps/src/xadcps_selftest.c
@@ -0,0 +1,138 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_selftest.c
+*
+* This file contains a diagnostic self test function for the XAdcPs driver.
+* The self test function does a simple read/write test of the Alarm Threshold
+* Register.
+*
+* See xadcps.h for more information.
+*
+* @note	None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constant defines the test value to be written
+ * to the Alarm Threshold Register
+ */
+#define XADCPS_ATR_TEST_VALUE 		0x55
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. The test
+*	- Resets the device,
+*	- Writes a value into the Alarm Threshold register and reads it back
+*	for comparison.
+*	- Resets the device again.
+*
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- XST_SUCCESS if the value read from the Alarm Threshold
+*		register is the same as the value written.
+*		- XST_FAILURE Otherwise
+*
+* @note		This is a destructive test in that resets of the device are
+*		performed. Refer to the device specification for the
+*		device status after the reset operation.
+*
+******************************************************************************/
+int XAdcPs_SelfTest(XAdcPs *InstancePtr)
+{
+	int Status;
+	u32 RegValue;
+
+	/*
+	 * Assert the argument
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * Reset the device to get it back to its default state
+	 */
+	XAdcPs_Reset(InstancePtr);
+
+	/*
+	 * Write a value into the Alarm Threshold registers, read it back, and
+	 * do the comparison
+	 */
+	XAdcPs_SetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER,
+				  XADCPS_ATR_TEST_VALUE);
+	RegValue = XAdcPs_GetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER);
+
+	if (RegValue == XADCPS_ATR_TEST_VALUE) {
+		Status = XST_SUCCESS;
+	} else {
+		Status = XST_FAILURE;
+	}
+
+	/*
+	 * Reset the device again to its default state.
+	 */
+	XAdcPs_Reset(InstancePtr);
+	/*
+	 * Return the test result.
+	 */
+	return Status;
+}
diff --git a/XilinxProcessorIPLib/drivers/xadcps/src/xadcps_sinit.c b/XilinxProcessorIPLib/drivers/xadcps/src/xadcps_sinit.c
new file mode 100644
index 00000000..2968270b
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/xadcps/src/xadcps_sinit.c
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_sinit.c
+*
+* This file contains the implementation of the XAdcPs driver's static
+* initialization functionality.
+*
+* @note	None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI XADC driver
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xadcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XAdcPs_Config XAdcPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* This function looks up the device configuration based on the unique device ID.
+* The table XAdcPs_ConfigTable contains the configuration info for each device
+* in the system.
+*
+* @param	DeviceId contains the ID of the device for which the
+*		device configuration pointer is to be returned.
+*
+* @return
+*		- A pointer to the configuration found.
+*		- NULL if the specified device ID was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId)
+{
+	XAdcPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index=0; Index < 1; Index++) {
+		if (XAdcPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XAdcPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}