diff --git a/XilinxProcessorIPLib/drivers/v_vscaler/data/v_vscaler.mdd b/XilinxProcessorIPLib/drivers/v_vscaler/data/v_vscaler.mdd new file mode 100644 index 00000000..593326cf --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_vscaler/data/v_vscaler.mdd @@ -0,0 +1,18 @@ +# ============================================================== +# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +# Version: 2015.1 +# Copyright (C) 2015 Xilinx Inc. All rights reserved. +# +# ============================================================== + +OPTION psf_version = 2.1; + +BEGIN driver v_vscaler + + OPTION supported_peripherals = (v_vscaler_v1_0 ); + OPTION driver_state = ACTIVE; + OPTION copyfiles = all; + OPTION name = v_vscaler; + OPTION version = 1.0; + +END driver diff --git a/XilinxProcessorIPLib/drivers/v_vscaler/data/v_vscaler.tcl b/XilinxProcessorIPLib/drivers/v_vscaler/data/v_vscaler.tcl new file mode 100644 index 00000000..e7353411 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_vscaler/data/v_vscaler.tcl @@ -0,0 +1,23 @@ +# ============================================================== +# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +# Version: 2015.1 +# Copyright (C) 2015 Xilinx Inc. All rights reserved. +# +# ============================================================== + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "XV_vscaler" \ + "NUM_INSTANCES" \ + "DEVICE_ID" \ + "C_S_AXI_CTRL_BASEADDR" \ + "C_S_AXI_CTRL_HIGHADDR" + + xdefine_config_file $drv_handle "xv_vscaler_g.c" "XV_vscaler" \ + "DEVICE_ID" \ + "C_S_AXI_CTRL_BASEADDR" + + xdefine_canonical_xpars $drv_handle "xparameters.h" "XV_vscaler" \ + "DEVICE_ID" \ + "C_S_AXI_CTRL_BASEADDR" \ + "C_S_AXI_CTRL_HIGHADDR" +} diff --git a/XilinxProcessorIPLib/drivers/v_vscaler/src/Makefile b/XilinxProcessorIPLib/drivers/v_vscaler/src/Makefile new file mode 100644 index 00000000..e2c2a969 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_vscaler/src/Makefile @@ -0,0 +1,34 @@ +# ============================================================== +# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +# Version: 2015.1 +# Copyright (C) 2015 Xilinx Inc. All rights reserved. +# +# ============================================================== + +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + + +libs: + echo "Compiling v_vscaler" + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS) + make clean + +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OUTS} diff --git a/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler.c b/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler.c new file mode 100644 index 00000000..ac3baf4a --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler.c @@ -0,0 +1,295 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2015.1 +// Copyright (C) 2015 Xilinx Inc. All rights reserved. +// +// ============================================================== + +/***************************** Include Files *********************************/ +#include "xv_vscaler.h" + +/************************** Function Implementation *************************/ +#ifndef __linux__ +int XV_vscaler_CfgInitialize(XV_vscaler *InstancePtr, XV_vscaler_Config *ConfigPtr) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + InstancePtr->Ctrl_BaseAddress = ConfigPtr->Ctrl_BaseAddress; + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + return XST_SUCCESS; +} +#endif + +void XV_vscaler_Start(XV_vscaler *InstancePtr) { + u32 Data; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL) & 0x80; + XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL, Data | 0x01); +} + +u32 XV_vscaler_IsDone(XV_vscaler *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL); + return (Data >> 1) & 0x1; +} + +u32 XV_vscaler_IsIdle(XV_vscaler *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL); + return (Data >> 2) & 0x1; +} + +u32 XV_vscaler_IsReady(XV_vscaler *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL); + // check ap_start to see if the pcore is ready for next input + return !(Data & 0x1); +} + +void XV_vscaler_EnableAutoRestart(XV_vscaler *InstancePtr) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL, 0x80); +} + +void XV_vscaler_DisableAutoRestart(XV_vscaler *InstancePtr) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL, 0); +} + +void XV_vscaler_Set_HwReg_HeightIn(XV_vscaler *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_HEIGHTIN_DATA, Data); +} + +u32 XV_vscaler_Get_HwReg_HeightIn(XV_vscaler *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_HEIGHTIN_DATA); + return Data; +} + +void XV_vscaler_Set_HwReg_Width(XV_vscaler *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_WIDTH_DATA, Data); +} + +u32 XV_vscaler_Get_HwReg_Width(XV_vscaler *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_WIDTH_DATA); + return Data; +} + +void XV_vscaler_Set_HwReg_HeightOut(XV_vscaler *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_HEIGHTOUT_DATA, Data); +} + +u32 XV_vscaler_Get_HwReg_HeightOut(XV_vscaler *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_HEIGHTOUT_DATA); + return Data; +} + +void XV_vscaler_Set_HwReg_LineRate(XV_vscaler *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_LINERATE_DATA, Data); +} + +u32 XV_vscaler_Get_HwReg_LineRate(XV_vscaler *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_HWREG_LINERATE_DATA); + return Data; +} + +u32 XV_vscaler_Get_HwReg_vfltCoeff_BaseAddress(XV_vscaler *InstancePtr) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return (InstancePtr->Ctrl_BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE); +} + +u32 XV_vscaler_Get_HwReg_vfltCoeff_HighAddress(XV_vscaler *InstancePtr) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return (InstancePtr->Ctrl_BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_HIGH); +} + +u32 XV_vscaler_Get_HwReg_vfltCoeff_TotalBytes(XV_vscaler *InstancePtr) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return (XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_HIGH - XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + 1); +} + +u32 XV_vscaler_Get_HwReg_vfltCoeff_BitWidth(XV_vscaler *InstancePtr) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XV_VSCALER_CTRL_WIDTH_HWREG_VFLTCOEFF; +} + +u32 XV_vscaler_Get_HwReg_vfltCoeff_Depth(XV_vscaler *InstancePtr) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XV_VSCALER_CTRL_DEPTH_HWREG_VFLTCOEFF; +} + +u32 XV_vscaler_Write_HwReg_vfltCoeff_Words(XV_vscaler *InstancePtr, int offset, int *data, int length) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr -> IsReady == XIL_COMPONENT_IS_READY); + + int i; + + if ((offset + length)*4 > (XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_HIGH - XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + 1)) + return 0; + + for (i = 0; i < length; i++) { + *(int *)(InstancePtr->Ctrl_BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + (offset + i)*4) = *(data + i); + } + return length; +} + +u32 XV_vscaler_Read_HwReg_vfltCoeff_Words(XV_vscaler *InstancePtr, int offset, int *data, int length) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr -> IsReady == XIL_COMPONENT_IS_READY); + + int i; + + if ((offset + length)*4 > (XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_HIGH - XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + 1)) + return 0; + + for (i = 0; i < length; i++) { + *(data + i) = *(int *)(InstancePtr->Ctrl_BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + (offset + i)*4); + } + return length; +} + +u32 XV_vscaler_Write_HwReg_vfltCoeff_Bytes(XV_vscaler *InstancePtr, int offset, char *data, int length) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr -> IsReady == XIL_COMPONENT_IS_READY); + + int i; + + if ((offset + length) > (XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_HIGH - XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + 1)) + return 0; + + for (i = 0; i < length; i++) { + *(char *)(InstancePtr->Ctrl_BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + offset + i) = *(data + i); + } + return length; +} + +u32 XV_vscaler_Read_HwReg_vfltCoeff_Bytes(XV_vscaler *InstancePtr, int offset, char *data, int length) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr -> IsReady == XIL_COMPONENT_IS_READY); + + int i; + + if ((offset + length) > (XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_HIGH - XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + 1)) + return 0; + + for (i = 0; i < length; i++) { + *(data + i) = *(char *)(InstancePtr->Ctrl_BaseAddress + XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE + offset + i); + } + return length; +} + +void XV_vscaler_InterruptGlobalEnable(XV_vscaler *InstancePtr) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_GIE, 1); +} + +void XV_vscaler_InterruptGlobalDisable(XV_vscaler *InstancePtr) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_GIE, 0); +} + +void XV_vscaler_InterruptEnable(XV_vscaler *InstancePtr, u32 Mask) { + u32 Register; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Register = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_IER); + XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_IER, Register | Mask); +} + +void XV_vscaler_InterruptDisable(XV_vscaler *InstancePtr, u32 Mask) { + u32 Register; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Register = XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_IER); + XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_IER, Register & (~Mask)); +} + +void XV_vscaler_InterruptClear(XV_vscaler *InstancePtr, u32 Mask) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_vscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_ISR, Mask); +} + +u32 XV_vscaler_InterruptGetEnabled(XV_vscaler *InstancePtr) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_IER); +} + +u32 XV_vscaler_InterruptGetStatus(XV_vscaler *InstancePtr) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XV_vscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_ISR); +} diff --git a/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler.h b/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler.h new file mode 100644 index 00000000..72b5b350 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler.h @@ -0,0 +1,120 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2015.1 +// Copyright (C) 2015 Xilinx Inc. All rights reserved. +// +// ============================================================== + +#ifndef XV_VSCALER_H +#define XV_VSCALER_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#ifndef __linux__ +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xil_io.h" +#else +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#endif +#include "xv_vscaler_hw.h" + +/**************************** Type Definitions ******************************/ +#ifdef __linux__ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +#else +typedef struct { + u16 DeviceId; + u32 Ctrl_BaseAddress; +} XV_vscaler_Config; +#endif + +typedef struct { + u32 Ctrl_BaseAddress; + u32 IsReady; +} XV_vscaler; + +/***************** Macros (Inline Functions) Definitions *********************/ +#ifndef __linux__ +#define XV_vscaler_WriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) +#define XV_vscaler_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) +#else +#define XV_vscaler_WriteReg(BaseAddress, RegOffset, Data) \ + *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data) +#define XV_vscaler_ReadReg(BaseAddress, RegOffset) \ + *(volatile u32*)((BaseAddress) + (RegOffset)) + +#define Xil_AssertVoid(expr) assert(expr) +#define Xil_AssertNonvoid(expr) assert(expr) + +#define XST_SUCCESS 0 +#define XST_DEVICE_NOT_FOUND 2 +#define XST_OPEN_DEVICE_FAILED 3 +#define XIL_COMPONENT_IS_READY 1 +#endif + +/************************** Function Prototypes *****************************/ +#ifndef __linux__ +int XV_vscaler_Initialize(XV_vscaler *InstancePtr, u16 DeviceId); +XV_vscaler_Config* XV_vscaler_LookupConfig(u16 DeviceId); +int XV_vscaler_CfgInitialize(XV_vscaler *InstancePtr, XV_vscaler_Config *ConfigPtr); +#else +int XV_vscaler_Initialize(XV_vscaler *InstancePtr, const char* InstanceName); +int XV_vscaler_Release(XV_vscaler *InstancePtr); +#endif + +void XV_vscaler_Start(XV_vscaler *InstancePtr); +u32 XV_vscaler_IsDone(XV_vscaler *InstancePtr); +u32 XV_vscaler_IsIdle(XV_vscaler *InstancePtr); +u32 XV_vscaler_IsReady(XV_vscaler *InstancePtr); +void XV_vscaler_EnableAutoRestart(XV_vscaler *InstancePtr); +void XV_vscaler_DisableAutoRestart(XV_vscaler *InstancePtr); + +void XV_vscaler_Set_HwReg_HeightIn(XV_vscaler *InstancePtr, u32 Data); +u32 XV_vscaler_Get_HwReg_HeightIn(XV_vscaler *InstancePtr); +void XV_vscaler_Set_HwReg_Width(XV_vscaler *InstancePtr, u32 Data); +u32 XV_vscaler_Get_HwReg_Width(XV_vscaler *InstancePtr); +void XV_vscaler_Set_HwReg_HeightOut(XV_vscaler *InstancePtr, u32 Data); +u32 XV_vscaler_Get_HwReg_HeightOut(XV_vscaler *InstancePtr); +void XV_vscaler_Set_HwReg_LineRate(XV_vscaler *InstancePtr, u32 Data); +u32 XV_vscaler_Get_HwReg_LineRate(XV_vscaler *InstancePtr); +u32 XV_vscaler_Get_HwReg_vfltCoeff_BaseAddress(XV_vscaler *InstancePtr); +u32 XV_vscaler_Get_HwReg_vfltCoeff_HighAddress(XV_vscaler *InstancePtr); +u32 XV_vscaler_Get_HwReg_vfltCoeff_TotalBytes(XV_vscaler *InstancePtr); +u32 XV_vscaler_Get_HwReg_vfltCoeff_BitWidth(XV_vscaler *InstancePtr); +u32 XV_vscaler_Get_HwReg_vfltCoeff_Depth(XV_vscaler *InstancePtr); +u32 XV_vscaler_Write_HwReg_vfltCoeff_Words(XV_vscaler *InstancePtr, int offset, int *data, int length); +u32 XV_vscaler_Read_HwReg_vfltCoeff_Words(XV_vscaler *InstancePtr, int offset, int *data, int length); +u32 XV_vscaler_Write_HwReg_vfltCoeff_Bytes(XV_vscaler *InstancePtr, int offset, char *data, int length); +u32 XV_vscaler_Read_HwReg_vfltCoeff_Bytes(XV_vscaler *InstancePtr, int offset, char *data, int length); + +void XV_vscaler_InterruptGlobalEnable(XV_vscaler *InstancePtr); +void XV_vscaler_InterruptGlobalDisable(XV_vscaler *InstancePtr); +void XV_vscaler_InterruptEnable(XV_vscaler *InstancePtr, u32 Mask); +void XV_vscaler_InterruptDisable(XV_vscaler *InstancePtr, u32 Mask); +void XV_vscaler_InterruptClear(XV_vscaler *InstancePtr, u32 Mask); +u32 XV_vscaler_InterruptGetEnabled(XV_vscaler *InstancePtr); +u32 XV_vscaler_InterruptGetStatus(XV_vscaler *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_hw.h b/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_hw.h new file mode 100644 index 00000000..8cbee539 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_hw.h @@ -0,0 +1,63 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2015.1 +// Copyright (C) 2015 Xilinx Inc. All rights reserved. +// +// ============================================================== + +// CTRL +// 0x000 : Control signals +// bit 0 - ap_start (Read/Write/COH) +// bit 1 - ap_done (Read/COR) +// bit 2 - ap_idle (Read) +// bit 3 - ap_ready (Read) +// bit 7 - auto_restart (Read/Write) +// others - reserved +// 0x004 : Global Interrupt Enable Register +// bit 0 - Global Interrupt Enable (Read/Write) +// others - reserved +// 0x008 : IP Interrupt Enable Register (Read/Write) +// bit 0 - Channel 0 (ap_done) +// bit 1 - Channel 1 (ap_ready) +// others - reserved +// 0x00c : IP Interrupt Status Register (Read/TOW) +// bit 0 - Channel 0 (ap_done) +// bit 1 - Channel 1 (ap_ready) +// others - reserved +// 0x010 : Data signal of HwReg_HeightIn +// bit 15~0 - HwReg_HeightIn[15:0] (Read/Write) +// others - reserved +// 0x014 : reserved +// 0x018 : Data signal of HwReg_Width +// bit 15~0 - HwReg_Width[15:0] (Read/Write) +// others - reserved +// 0x01c : reserved +// 0x020 : Data signal of HwReg_HeightOut +// bit 15~0 - HwReg_HeightOut[15:0] (Read/Write) +// others - reserved +// 0x024 : reserved +// 0x028 : Data signal of HwReg_LineRate +// bit 31~0 - HwReg_LineRate[31:0] (Read/Write) +// 0x02c : reserved +// 0x400 ~ +// 0x7ff : Memory 'HwReg_vfltCoeff' (384 * 16b) +// Word n : bit [15: 0] - HwReg_vfltCoeff[2n] +// bit [31:16] - HwReg_vfltCoeff[2n+1] +// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) + +#define XV_VSCALER_CTRL_ADDR_AP_CTRL 0x000 +#define XV_VSCALER_CTRL_ADDR_GIE 0x004 +#define XV_VSCALER_CTRL_ADDR_IER 0x008 +#define XV_VSCALER_CTRL_ADDR_ISR 0x00c +#define XV_VSCALER_CTRL_ADDR_HWREG_HEIGHTIN_DATA 0x010 +#define XV_VSCALER_CTRL_BITS_HWREG_HEIGHTIN_DATA 16 +#define XV_VSCALER_CTRL_ADDR_HWREG_WIDTH_DATA 0x018 +#define XV_VSCALER_CTRL_BITS_HWREG_WIDTH_DATA 16 +#define XV_VSCALER_CTRL_ADDR_HWREG_HEIGHTOUT_DATA 0x020 +#define XV_VSCALER_CTRL_BITS_HWREG_HEIGHTOUT_DATA 16 +#define XV_VSCALER_CTRL_ADDR_HWREG_LINERATE_DATA 0x028 +#define XV_VSCALER_CTRL_BITS_HWREG_LINERATE_DATA 32 +#define XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_BASE 0x400 +#define XV_VSCALER_CTRL_ADDR_HWREG_VFLTCOEFF_HIGH 0x7ff +#define XV_VSCALER_CTRL_WIDTH_HWREG_VFLTCOEFF 16 +#define XV_VSCALER_CTRL_DEPTH_HWREG_VFLTCOEFF 384 diff --git a/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_l2.c b/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_l2.c new file mode 100644 index 00000000..75b03ae2 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_l2.c @@ -0,0 +1,494 @@ +/****************************************************************************** + * + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xv_vscaler_l2.c +* +* The Vertical Scaler Layer-2 Driver. +* The functions in this file provides an abstraction from the register peek/poke +* methodology by implementing most common use-case provided by the sub-core. +* See xv_vscaler_l2.h for a detailed description of the layer-2 driver +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00  rc   05/01/15   Initial Release
+
+* 
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include +#include "xv_vscaler_l2.h" + +/************************** Constant Definitions *****************************/ +#define PI (3.14159265358979) +#define STEP_PRECISION (65536) // 2^16 +#define COEFF_PRECISION (4096) // 2^12 +#define COEFF_QUANT (4096) + +/* Mask definitions for Low and high 16 bits in a 32 bit number */ +#define XMASK_LOW_16BITS (0x0000FFFF) +#define XMASK_HIGH_16BITS (0xFFFF0000) + +/**************************** Type Definitions *******************************/ + +/**************************** Local Global *******************************/ +static float SincCoeffs[XV_VSCALER_MAX_V_PHASES][XV_VSCALER_MAX_V_TAPS]; +static float TempCoeffs[XV_VSCALER_MAX_V_PHASES][XV_VSCALER_MAX_V_TAPS]; +static float WinCoeffs[XV_VSCALER_MAX_V_PHASES][XV_VSCALER_MAX_V_TAPS]; +static float NormCoeffs[XV_VSCALER_MAX_V_PHASES][XV_VSCALER_MAX_V_TAPS]; + +/************************** Function Prototypes ******************************/ +static float hamming( int x, int taps); +static float sinc(float x); +static void XV_VScalerGetCoeff(XV_vscaler *InstancePtr, + XV_vscaler_l2 *pVscL2Data, + u32 HeightIn, + u32 HeightOut); +static void XV_VScalerSetCoeff(XV_vscaler *InstancePtr, + XV_vscaler_l2 *pVscL2Data); + +/*****************************************************************************/ +/** +* This function starts the vertical scaler core +* +* @param InstancePtr is a pointer to the core instance to be worked on. +* +* @return None +* +******************************************************************************/ +void XV_VScalerStart(XV_vscaler *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + XV_vscaler_EnableAutoRestart(InstancePtr); + XV_vscaler_Start(InstancePtr); +} + +/*****************************************************************************/ +/** +* This function stops the vertical scaler core +* +* @param InstancePtr is a pointer to the core instance to be worked on. +* +* @return None +* +******************************************************************************/ +void XV_VScalerStop(XV_vscaler *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + XV_vscaler_DisableAutoRestart(InstancePtr); +} + +/*****************************************************************************/ +/** +* This function applies the hamming filter on specified pixel position +* +* @param x is the pixel coordinate in horizontal direction +* @param taps is the number of taps available to the scaler +* +* @return hamming filter result +* +******************************************************************************/ +static float hamming( int x, int taps) +{ + //0.54 + 0.46 * cos(pi * x / filter_size); 0.54 - 0.46 * cos(2*pi * x / filter_size) + return (float) (0.54 + (0.46*cos((PI*x)/(taps+1)))); +} + +/*****************************************************************************/ +/** +* This function applies the SIN function to specified pixel position +* +* @param x is the pixel coordinate in horizontal direction +* +* @return Sine function result +* +******************************************************************************/ +static float sinc(float x) +{ + if (x==0) + return 1; + + return (float) sin(x*PI)/(float)(x*PI); +} + +/*****************************************************************************/ +/** +* This function loads user defined filter coefficients in the scaler coefficient +* storage +* +* @param InstancePtr is a pointer to the core instance to be worked on. +* @param pVscL2Data is a pointer to the core instance layer 2 data. +* @param VCoeff is the user defined filter coefficients +******************************************************************************/ +void XV_VscalerLoadUsrCoeffients(XV_vscaler *InstancePtr, + XV_vscaler_l2 *pVscL2Data, + const short VCoeff[XV_VSCALER_MAX_V_PHASES][XV_VSCALER_MAX_V_TAPS]) +{ + int i,j,k, pad, offset; + int num_phases = XV_VSCALER_MAX_V_PHASES; + int num_taps = pVscL2Data->EffectiveTaps; + + /* + * Assert validates the input arguments + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(pVscL2Data != NULL); + Xil_AssertVoid((pVscL2Data->EffectiveTaps > 0) && + (pVscL2Data->EffectiveTaps <= XV_VSCALER_MAX_V_TAPS)); + + //determine if coefficient needs padding (effective vs. max taps) + pad = XV_VSCALER_MAX_V_TAPS - num_taps; + offset = ((pad) ? (pad>>1) : 0); + + //Load User defined coefficients into scaler coefficient table + for (i = 0; i < num_phases; i++) + { + for (k=0,j=offset; jcoeff[i][j] = VCoeff[i][k]; + } + } + + if(pad) //effective taps < max_taps + { + for (i = 0; i < num_phases; i++) + { + //pad left + for (j = 0; j < offset; j++) + { + pVscL2Data->coeff[i][j] = 0; + } + //pad right + for (j = (num_taps+offset); j < XV_VSCALER_MAX_V_TAPS; j++) + { + pVscL2Data->coeff[i][j] = 0; + } + } + } +} + +/*****************************************************************************/ +/** +* This function computes the filter coefficients based on scaling ratio and +* stores them into the layer 2 data storage +* +* @param InstancePtr is a pointer to the core instance to be worked on. +* @param pVscL2Data is a pointer to the core instance layer 2 data. +* @param HeightIn is the input frame height +* @param HeightOut is the scaled frame height +* +* @return None +* +******************************************************************************/ +static void XV_VScalerGetCoeff(XV_vscaler *InstancePtr, + XV_vscaler_l2 *pVscL2Data, + u32 HeightIn, + u32 HeightOut) +{ + int num_phases = XV_VSCALER_MAX_V_PHASES; + int num_taps = pVscL2Data->EffectiveTaps; + int center_tap = num_taps/2; + int i,j, pad, offset; + float x, fc; + float sum[XV_VSCALER_MAX_V_PHASES]; + float cos_win[XV_VSCALER_MAX_V_TAPS]; + + /* + * Assert validates the input arguments + */ + Xil_AssertVoid((pVscL2Data->EffectiveTaps > 0) && + (pVscL2Data->EffectiveTaps <= XV_VSCALER_MAX_V_TAPS)); + + if(HeightIn < HeightOut) + { + fc = (float)HeightIn/(float)HeightOut; + } + else + { + fc = (float)HeightOut/(float)HeightIn; + } + + //determine if coefficient needs padding (effective vs. max taps) + pad = XV_VSCALER_MAX_V_TAPS - num_taps; + offset = ((pad) ? (pad>>1) : 0); + + for(i=0; iFilterSel) + { + case XV_VFILT_LANCZOS: + //Window is a sinc function instead of cosine function + // if using lanczos2 or lanczos3 kernel + // lanczos(x) = sinc(x) * sinc(x / filter_size); + + for (i = 0; i < num_phases; i++) + { + for (j = 0; j < num_taps; j++) + { + x = TempCoeffs[i][j]; + WinCoeffs[i][j] = SincCoeffs[i][j] * sinc((fc*x)/num_taps); + } + } + break; + + case XV_VFILT_WINDOWED_SINC: + for (j = 1; j <= num_taps; j++) + { + cos_win[j-1] = hamming(j, num_taps); + } + + for (i = 0; i < num_phases; i++) + { + for (j = 0; j < num_taps; j++) + { + WinCoeffs[i][j] = SincCoeffs[i][j] * cos_win[j]; + } + } + break; + } + + // normalize to unity and quantize + for (i = 0; i < num_phases; i++) + { + sum[i] = 0; + for (j = 0; j < num_taps; j++) + { + sum[i] += WinCoeffs[i][j]; + } + } + + for (i = 0; i < num_phases; i++) + { + for (j = offset; j < num_taps; j++) + { + NormCoeffs[i][j] = WinCoeffs[i][j]/sum[i]; + pVscL2Data->coeff[i][j] = (short) ((NormCoeffs[i][j] * COEFF_QUANT) + 0.5); + } + } + + if(pad) //effective taps < max_taps + { + for (i = 0; i < num_phases; i++) + { + //pad left + for (j = 0; j < offset; j++) + { + pVscL2Data->coeff[i][j] = 0; + } + //pad right + for (j = (num_taps+offset); j < XV_VSCALER_MAX_V_TAPS; j++) + { + pVscL2Data->coeff[i][j] = 0; + } + } + } +} + + +/*****************************************************************************/ +/** +* This function programs the computed filter coefficients and phase data into +* core registers +* +* @param InstancePtr is a pointer to the core instance to be worked on. +* @param VCoeff is the array that holds computed coefficients +* +* @return None +* +* @Note This version of driver does not make use of computed coefficients. +* Pre-computed coefficients are stored in a local table which are used +* to overwrite any computed coefficients before being programmed into +* the core registers. Control flow still computes the coefficients to +* maintain the sw latency for driver version which would eventually use +* computed coefficients +******************************************************************************/ +static void XV_VScalerSetCoeff(XV_vscaler *InstancePtr, + XV_vscaler_l2 *pVscL2Data) +{ + int num_phases = XV_VSCALER_MAX_V_PHASES; + int num_taps = XV_VSCALER_MAX_V_TAPS/2; + int val,i,j; + u32 baseAddr; + + baseAddr = XV_vscaler_Get_HwReg_vfltCoeff_BaseAddress(InstancePtr); + for (i=0; i < num_phases; i++) + { + for(j=0; j < num_taps; j++) + { + val = (pVscL2Data->coeff[i][(j*2)+1] << 16) | (pVscL2Data->coeff[i][j*2] & XMASK_LOW_16BITS); + Xil_Out32(baseAddr+((i*num_taps+j)*4), val); + } + } +} + +/*****************************************************************************/ +/** +* This function configures the scaler core registers with the specified +* configuration parameters of the axi stream +* +* @param InstancePtr is a pointer to the core instance to be worked on. +* @param WidthIn is the input stream width +* @param HeightIn is the input stream height +* @param HeightOut is the output stream height +* +* @return None +* +******************************************************************************/ +void XV_VScalerSetup(XV_vscaler *InstancePtr, + XV_vscaler_l2 *pVscL2Data, + u32 WidthIn, + u32 HeightIn, + u32 HeightOut) +{ + u32 LineRate; + + /* + * Assert validates the input arguments + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(pVscL2Data != NULL); + + if(pVscL2Data->ScalerType == XV_VSCALER_POLYPHASE) + { + if(!pVscL2Data->UseExtCoeff) //No predefined coefficients + { + /* Generate coefficients for vertical scaling ratio */ + XV_VScalerGetCoeff(InstancePtr, + pVscL2Data, + HeightIn, + HeightOut); + } + + /* Program coefficients into the IP register bank */ + XV_VScalerSetCoeff(InstancePtr, pVscL2Data); + } + + LineRate = (u32) ((float)((HeightIn * STEP_PRECISION) + (HeightOut/2))/(float)HeightOut); + + XV_vscaler_Set_HwReg_HeightIn(InstancePtr, HeightIn); + XV_vscaler_Set_HwReg_Width(InstancePtr, WidthIn); + XV_vscaler_Set_HwReg_HeightOut(InstancePtr, HeightOut); + XV_vscaler_Set_HwReg_LineRate(InstancePtr, LineRate); +} + +/*****************************************************************************/ +/** +* +* This function prints V Scaler status on the console +* +* @param InstancePtr is the instance pointer to the core instance. +* +* @return None +* +******************************************************************************/ +void XV_VScalerDbgReportStatus(XV_vscaler *InstancePtr) +{ + XV_vscaler *pVsc = InstancePtr; + u32 done, idle, ready, ctrl; + u32 widthin, heightin, heightout, linerate; + u32 type = 3; //hard-coded to polyphase for now + u32 baseAddr, taps, phases; + int val,i,j; + + /* + * Assert validates the input arguments + */ + Xil_AssertVoid(InstancePtr != NULL); + + xil_printf("\r\n\r\n----->V SCALER IP STATUS<----\r\n"); + done = XV_vscaler_IsDone(pVsc); + idle = XV_vscaler_IsIdle(pVsc); + ready = XV_vscaler_IsReady(pVsc); + ctrl = XV_vscaler_ReadReg(pVsc->Ctrl_BaseAddress, XV_VSCALER_CTRL_ADDR_AP_CTRL); + + + heightin = XV_vscaler_Get_HwReg_HeightIn(pVsc); + widthin = XV_vscaler_Get_HwReg_Width(pVsc); + heightout = XV_vscaler_Get_HwReg_HeightOut(pVsc); +// type = XV_vscaler_GetHwreg_scaletype(pVsc); + linerate = XV_vscaler_Get_HwReg_LineRate(pVsc); + + taps = XV_VSCALER_MAX_V_TAPS/2; + phases = XV_VSCALER_MAX_V_PHASES; + + xil_printf("IsDone: %d\r\n", done); + xil_printf("IsIdle: %d\r\n", idle); + xil_printf("IsReady: %d\r\n", ready); + xil_printf("Ctrl: 0x%x\r\n\r\n", ctrl); + + xil_printf("Input Width: %d\r\n",widthin); + xil_printf("Input Height: %d\r\n",heightin); + xil_printf("Output Height: %d\r\n",heightout); +// xil_printf("Scaler Type: %d\r\n",type); + xil_printf("Line Rate: %d\r\n",linerate); + xil_printf("Num Phases: %d\r\n",phases); + xil_printf("Num Taps: %d\r\n",taps*2); + + if(type == 3) + { + short lsb, msb; + + xil_printf("\r\nCoefficients:"); + + baseAddr = XV_vscaler_Get_HwReg_vfltCoeff_BaseAddress(pVsc); + for(i = 0; i < phases; i++) + { + xil_printf("\r\nPhase %2d: ",i); + for(j=0; j< taps; j++) + { + val = Xil_In32(baseAddr+((i*taps+j)*4)); + + //coefficients are 12-bits + lsb = (short)(val & XMASK_LOW_16BITS); + msb = (short)((val & XMASK_HIGH_16BITS)>>16); + + xil_printf("%5d %5d ", lsb, msb); + } + } + } +} diff --git a/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_l2.h b/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_l2.h new file mode 100644 index 00000000..f7a745fc --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_l2.h @@ -0,0 +1,181 @@ +/****************************************************************************** + * + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xv_vscaler_l2.h +* +* This header file contains layer 2 API's of the verrtical scaler sub-core +* driver.The functions contained herein provides a high level implementation of +* features provided by the IP, abstracting away the register level details from +* the user +* +* V Scaler IP Features +* +* This V-Scaler IP supports following features +* - 3 Channel Scaler +* - Scale vertically to 2K lines at 60Hz +* - up to 16bits color depth +* - 1, 2 or 4 pixel per clock processing +* +* Dependency +* +* This driver makes use of the video enumerations and data types defined in the +* Xilinx Video Common Driver (video_common_vX.x) and as such the common driver +* must be included as dependency to compile this driver + +* Initialization & Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the vscaler core. +* +* Before using the layer-2 API's user must initialize the core by calling +* Layer-1 API XV_vscaler_Initialize(). This function will look for a +* configuration structure for the device and initialize it to defined HW +* settings. After initialization Layer-2 API's can be used to configure +* the core. It is recommended user always make use of Layer-2 API to +* interact with this core. +* Advanced users always have the capability to directly interact with the IP +* core using Layer-1 API's that perform low level register peek/poke. +* +* Interrupts +* +* This driver does not have any interrupts +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Limitations +* +* Current implementation of "computed coefficients" is non-entrant. If multiple +* instances of the core are used in the design, user application has to make sure +* that scale configuration is an atomic operation and cannot be interrupted in +* middle to context switch to a different instance of the core +* However fixed coefficient version of the code (default) is safe to be used with +* multiple instances of the core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00  rc   05/01/15   Initial Release
+
+* 
+* +******************************************************************************/ +#ifndef XV_VSCALER_L2_H /* prevent circular inclusions */ +#define XV_VSCALER_L2_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xvidc.h" +#include "xv_vscaler.h" + +/************************** Constant Definitions *****************************/ + /** @name Hw Configuration + * @{ + * The following constants define the scaler HW configuration + * TODO: + * Below defined Parameters are static configuration of H Scaler IP + * The tool needs to export these parameters to SDK and the driver will + * be populated with these option settings. i.e. these settings could be + * accessible via instance pointer + * + */ + #define XV_VSCALER_MAX_V_TAPS (6) + #define XV_VSCALER_MAX_V_PHASES (64) + +/**************************** Type Definitions *******************************/ +/** + * This typedef contains the Scaler Type + */ +typedef enum +{ + XV_VSCALER_BILINEAR = 0, + XV_VSCALER_BICUBIC, + XV_VSCALER_POLYPHASE +}XV_VSCALER_TYPE; + +/** + * This typedef contains the type of filters available for scaling operation + */ +typedef enum +{ + XV_VFILT_LANCZOS = 0, + XV_VFILT_WINDOWED_SINC +}XV_VFILTER_ID; + + +/** + * V Scaler Layer 2 data. The user is required to allocate a variable + * of this type for every V Scaler device in the system. A pointer to a + * variable of this type is then passed to the driver API functions. + */ +typedef struct +{ + u8 EffectiveTaps; + u8 UseExtCoeff; + XV_VFILTER_ID FilterSel; + XV_VSCALER_TYPE ScalerType; + u8 Gain; + short coeff[XV_VSCALER_MAX_V_PHASES][XV_VSCALER_MAX_V_TAPS]; +}XV_vscaler_l2; + +/************************** Function Prototypes ******************************/ +void XV_VScalerStart(XV_vscaler *InstancePtr); +void XV_VScalerStop(XV_vscaler *InstancePtr); +void XV_VscalerLoadUsrCoeffients(XV_vscaler *InstancePtr, + XV_vscaler_l2 *pVscL2Data, + const short VCoeff[XV_VSCALER_MAX_V_PHASES][XV_VSCALER_MAX_V_TAPS]); +void XV_VScalerSetup(XV_vscaler *InstancePtr, + XV_vscaler_l2 *pVscL2Data, + u32 WidthIn, + u32 HeightIn, + u32 HeightOut); + +void XV_VScalerDbgReportStatus(XV_vscaler *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_linux.c b/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_linux.c new file mode 100644 index 00000000..6ac520f9 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_linux.c @@ -0,0 +1,150 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2015.1 +// Copyright (C) 2015 Xilinx Inc. All rights reserved. +// +// ============================================================== + +#ifdef __linux__ + +/***************************** Include Files *********************************/ +#include "xv_vscaler.h" + +/***************** Macros (Inline Functions) Definitions *********************/ +#define MAX_UIO_PATH_SIZE 256 +#define MAX_UIO_NAME_SIZE 64 +#define MAX_UIO_MAPS 5 +#define UIO_INVALID_ADDR 0 + +/**************************** Type Definitions ******************************/ +typedef struct { + u32 addr; + u32 size; +} XV_vscaler_uio_map; + +typedef struct { + int uio_fd; + int uio_num; + char name[ MAX_UIO_NAME_SIZE ]; + char version[ MAX_UIO_NAME_SIZE ]; + XV_vscaler_uio_map maps[ MAX_UIO_MAPS ]; +} XV_vscaler_uio_info; + +/***************** Variable Definitions **************************************/ +static XV_vscaler_uio_info uio_info; + +/************************** Function Implementation *************************/ +static int line_from_file(char* filename, char* linebuf) { + char* s; + int i; + FILE* fp = fopen(filename, "r"); + if (!fp) return -1; + s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp); + fclose(fp); + if (!s) return -2; + for (i=0; (*s)&&(iuio_num); + return line_from_file(file, info->name); +} + +static int uio_info_read_version(XV_vscaler_uio_info* info) { + char file[ MAX_UIO_PATH_SIZE ]; + sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num); + return line_from_file(file, info->version); +} + +static int uio_info_read_map_addr(XV_vscaler_uio_info* info, int n) { + int ret; + char file[ MAX_UIO_PATH_SIZE ]; + info->maps[n].addr = UIO_INVALID_ADDR; + sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n); + FILE* fp = fopen(file, "r"); + if (!fp) return -1; + ret = fscanf(fp, "0x%x", &info->maps[n].addr); + fclose(fp); + if (ret < 0) return -2; + return 0; +} + +static int uio_info_read_map_size(XV_vscaler_uio_info* info, int n) { + int ret; + char file[ MAX_UIO_PATH_SIZE ]; + sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n); + FILE* fp = fopen(file, "r"); + if (!fp) return -1; + ret = fscanf(fp, "0x%x", &info->maps[n].size); + fclose(fp); + if (ret < 0) return -2; + return 0; +} + +int XV_vscaler_Initialize(XV_vscaler *InstancePtr, const char* InstanceName) { + XV_vscaler_uio_info *InfoPtr = &uio_info; + struct dirent **namelist; + int i, n; + char* s; + char file[ MAX_UIO_PATH_SIZE ]; + char name[ MAX_UIO_NAME_SIZE ]; + int flag = 0; + + assert(InstancePtr != NULL); + + n = scandir("/sys/class/uio", &namelist, 0, alphasort); + if (n < 0) return XST_DEVICE_NOT_FOUND; + for (i = 0; i < n; i++) { + strcpy(file, "/sys/class/uio/"); + strcat(file, namelist[i]->d_name); + strcat(file, "/name"); + if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) { + flag = 1; + s = namelist[i]->d_name; + s += 3; // "uio" + InfoPtr->uio_num = atoi(s); + break; + } + } + if (flag == 0) return XST_DEVICE_NOT_FOUND; + + uio_info_read_name(InfoPtr); + uio_info_read_version(InfoPtr); + for (n = 0; n < MAX_UIO_MAPS; ++n) { + uio_info_read_map_addr(InfoPtr, n); + uio_info_read_map_size(InfoPtr, n); + } + + sprintf(file, "/dev/uio%d", InfoPtr->uio_num); + if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) { + return XST_OPEN_DEVICE_FAILED; + } + + // NOTE: slave interface 'Ctrl' should be mapped to uioX/map0 + InstancePtr->Ctrl_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize()); + assert(InstancePtr->Ctrl_BaseAddress); + + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + return XST_SUCCESS; +} + +int XV_vscaler_Release(XV_vscaler *InstancePtr) { + XV_vscaler_uio_info *InfoPtr = &uio_info; + + assert(InstancePtr != NULL); + assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + munmap((void*)InstancePtr->Ctrl_BaseAddress, InfoPtr->maps[0].size); + + close(InfoPtr->uio_fd); + + return XST_SUCCESS; +} + +#endif diff --git a/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_sinit.c b/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_sinit.c new file mode 100644 index 00000000..ecdc5269 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_vscaler/src/xv_vscaler_sinit.c @@ -0,0 +1,45 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2015.1 +// Copyright (C) 2015 Xilinx Inc. All rights reserved. +// +// ============================================================== + +#ifndef __linux__ + +#include "xstatus.h" +#include "xparameters.h" +#include "xv_vscaler.h" + +extern XV_vscaler_Config XV_vscaler_ConfigTable[]; + +XV_vscaler_Config *XV_vscaler_LookupConfig(u16 DeviceId) { + XV_vscaler_Config *ConfigPtr = NULL; + + int Index; + + for (Index = 0; Index < XPAR_XV_VSCALER_NUM_INSTANCES; Index++) { + if (XV_vscaler_ConfigTable[Index].DeviceId == DeviceId) { + ConfigPtr = &XV_vscaler_ConfigTable[Index]; + break; + } + } + + return ConfigPtr; +} + +int XV_vscaler_Initialize(XV_vscaler *InstancePtr, u16 DeviceId) { + XV_vscaler_Config *ConfigPtr; + + Xil_AssertNonvoid(InstancePtr != NULL); + + ConfigPtr = XV_vscaler_LookupConfig(DeviceId); + if (ConfigPtr == NULL) { + InstancePtr->IsReady = 0; + return (XST_DEVICE_NOT_FOUND); + } + + return XV_vscaler_CfgInitialize(InstancePtr, ConfigPtr); +} + +#endif