diff --git a/XilinxProcessorIPLib/drivers/axicdma/data/axicdma.mdd b/XilinxProcessorIPLib/drivers/axicdma/data/axicdma.mdd
index 955264ab..74aa08a9 100755
--- a/XilinxProcessorIPLib/drivers/axicdma/data/axicdma.mdd
+++ b/XilinxProcessorIPLib/drivers/axicdma/data/axicdma.mdd
@@ -36,7 +36,7 @@ BEGIN driver axicdma
   OPTION supported_peripherals =  (axi_cdma_v[3-9]_[0-9][0-9]_[a-z] axi_cdma_v[3-9]_[0-9]);	
   OPTION driver_state = ACTIVE;
   OPTION copyfiles = all;
-  OPTION VERSION = 3.0;
+  OPTION VERSION = 4.0;
   OPTION NAME = axicdma;
 
 END driver
diff --git a/XilinxProcessorIPLib/drivers/axicdma/data/axicdma.tcl b/XilinxProcessorIPLib/drivers/axicdma/data/axicdma.tcl
index d30a1dec..0f82998b 100755
--- a/XilinxProcessorIPLib/drivers/axicdma/data/axicdma.tcl
+++ b/XilinxProcessorIPLib/drivers/axicdma/data/axicdma.tcl
@@ -31,9 +31,9 @@
 ##############################################################################
 
 proc generate {drv_handle} {
-	::hsi::utils::define_include_file $drv_handle "xparameters.h" "XAxiCdma" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_INCLUDE_DRE" "C_USE_DATAMOVER_LITE" "C_M_AXI_DATA_WIDTH" "C_INCLUDE_SG" "C_M_AXI_MAX_BURST_LEN"
+	::hsi::utils::define_include_file $drv_handle "xparameters.h" "XAxiCdma" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_INCLUDE_DRE" "C_USE_DATAMOVER_LITE" "C_M_AXI_DATA_WIDTH" "C_INCLUDE_SG" "C_M_AXI_MAX_BURST_LEN" "C_ADDR_WIDTH"
 
-	::hsi::utils::define_config_file  $drv_handle "xaxicdma_g.c" "XAxiCdma" "DEVICE_ID" "C_BASEADDR" "C_INCLUDE_DRE" "C_USE_DATAMOVER_LITE" "C_M_AXI_DATA_WIDTH" "C_M_AXI_MAX_BURST_LEN"
+	::hsi::utils::define_config_file  $drv_handle "xaxicdma_g.c" "XAxiCdma" "DEVICE_ID" "C_BASEADDR" "C_INCLUDE_DRE" "C_USE_DATAMOVER_LITE" "C_M_AXI_DATA_WIDTH" "C_M_AXI_MAX_BURST_LEN" "C_ADDR_WIDTH"
 
-	::hsi::utils::define_canonical_xpars $drv_handle "xparameters.h" "AxiCdma" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_INCLUDE_DRE" "C_USE_DATAMOVER_LITE" "C_M_AXI_DATA_WIDTH" "C_INCLUDE_SG" "C_M_AXI_MAX_BURST_LEN"
+	::hsi::utils::define_canonical_xpars $drv_handle "xparameters.h" "AxiCdma" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_INCLUDE_DRE" "C_USE_DATAMOVER_LITE" "C_M_AXI_DATA_WIDTH" "C_INCLUDE_SG" "C_M_AXI_MAX_BURST_LEN" "C_ADDR_WIDTH"
 }
diff --git a/XilinxProcessorIPLib/drivers/axicdma/examples/xaxicdma_example_sg_poll.c b/XilinxProcessorIPLib/drivers/axicdma/examples/xaxicdma_example_sg_poll.c
index 13ac4ac8..15dc481e 100644
--- a/XilinxProcessorIPLib/drivers/axicdma/examples/xaxicdma_example_sg_poll.c
+++ b/XilinxProcessorIPLib/drivers/axicdma/examples/xaxicdma_example_sg_poll.c
@@ -96,6 +96,8 @@ extern void xil_printf(const char *format, ...);
 #define MEMORY_BASE		XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
 #elif XPAR_MIG7SERIES_0_BASEADDR
 #define MEMORY_BASE	XPAR_MIG7SERIES_0_BASEADDR
+#elif XPAR_PSU_DDR_0_S_AXI_BASEADDR
+#define MEMORY_BASE	XPAR_PSU_DDR_0_S_AXI_BASEADDR
 #else
 #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
 			DEFAULT SET TO 0x01000000
@@ -108,9 +110,8 @@ extern void xil_printf(const char *format, ...);
 #define RX_BUFFER_BASE		(MEMORY_BASE + 0x00660000)
 #define RX_BUFFER_HIGH		(MEMORY_BASE + 0x0068FFFF)
 
-
-
 #define MAX_PKT_LEN		128
+#define MARK_UNCACHEABLE	0x701
 
 /* Number of BDs in the transfer example
  * We show how to submit multiple BDs for one transmit.
@@ -358,7 +359,7 @@ static int SetupTransfer(XAxiCdma * InstancePtr)
 	/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
 	 * is enabled
 	 */
-	Xil_DCacheFlushRange((u32)TransmitBufferPtr,
+	Xil_DCacheFlushRange((UINTPTR)TransmitBufferPtr,
 		MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);
 
 	return XST_SUCCESS;
@@ -384,8 +385,8 @@ static int DoTransfer(XAxiCdma * InstancePtr)
 	XAxiCdma_Bd *BdCurPtr;
 	int Status;
 	int Index;
-	u32 SrcBufferAddr;
-	u32 DstBufferAddr;
+	UINTPTR SrcBufferAddr;
+	UINTPTR DstBufferAddr;
 
 	Status = XAxiCdma_BdRingAlloc(InstancePtr,
 		    NUMBER_OF_BDS_TO_TRANSFER, &BdPtr);
@@ -395,8 +396,8 @@ static int DoTransfer(XAxiCdma * InstancePtr)
 		return XST_FAILURE;
 	}
 
-	SrcBufferAddr = (u32)TransmitBufferPtr;
-	DstBufferAddr = (u32)ReceiveBufferPtr;
+	SrcBufferAddr = (UINTPTR)TransmitBufferPtr;
+	DstBufferAddr = (UINTPTR)ReceiveBufferPtr;
 	BdCurPtr = BdPtr;
 
 	/* Set up the BDs
@@ -470,7 +471,7 @@ static int CheckData(u8 *SrcPtr, u8 *DestPtr, int Length)
 	/* Invalidate the DestBuffer before receiving the data, in case the
 	 * Data Cache is enabled
 	 */
-	Xil_DCacheInvalidateRange((u32)DestPtr, Length);
+	Xil_DCacheInvalidateRange((UINTPTR)DestPtr, Length);
 
 	for (Index = 0; Index < Length; Index++) {
 		if ( DestPtr[Index] != SrcPtr[Index]) {
@@ -508,6 +509,10 @@ int XAxiCdma_SgPollExample(u16 DeviceId)
 	SrcPtr = (u8 *)TransmitBufferPtr;
 	DstPtr = (u8 *)ReceiveBufferPtr;
 
+#ifdef __aarch64__
+	Xil_SetTlbAttributes(MEMORY_BASE, MARK_UNCACHEABLE);
+#endif
+
 	/* Initialize the XAxiCdma device.
 	 */
 	CfgPtr = XAxiCdma_LookupConfig(DeviceId);
diff --git a/XilinxProcessorIPLib/drivers/axicdma/examples/xaxicdma_example_simple_poll.c b/XilinxProcessorIPLib/drivers/axicdma/examples/xaxicdma_example_simple_poll.c
index 6474a8cf..9ad998e7 100644
--- a/XilinxProcessorIPLib/drivers/axicdma/examples/xaxicdma_example_simple_poll.c
+++ b/XilinxProcessorIPLib/drivers/axicdma/examples/xaxicdma_example_simple_poll.c
@@ -258,15 +258,15 @@ static int DoSimplePollTransfer(XAxiCdma *InstancePtr, int Length, int Retries)
 	/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
 	 * is enabled
 	 */
-	Xil_DCacheFlushRange((u32)&SrcBuffer, Length);
+	Xil_DCacheFlushRange((UINTPTR)&SrcBuffer, Length);
 
 	/* Try to start the DMA transfer
 	 */
 	while (Retries) {
 		Retries -= 1;
 
-		Status = XAxiCdma_SimpleTransfer(InstancePtr, (u32)SrcBuffer,
-			(u32)DestBuffer, Length, NULL, NULL);
+		Status = XAxiCdma_SimpleTransfer(InstancePtr, (UINTPTR)SrcBuffer,
+			(UINTPTR)DestBuffer, Length, NULL, NULL);
 		if (Status == XST_SUCCESS) {
 			break;
 		}
@@ -341,7 +341,9 @@ static int CheckData(u8 *SrcPtr, u8 *DestPtr, int Length)
 	/* Invalidate the DestBuffer before receiving the data, in case the
 	 * Data Cache is enabled
 	 */
-	Xil_DCacheInvalidateRange((u32)DestPtr, Length);
+#ifndef __aarch64__
+	Xil_DCacheInvalidateRange((UINTPTR)DestPtr, Length);
+#endif
 
 	for (Index = 0; Index < Length; Index++) {
 		if ( DestPtr[Index] != SrcPtr[Index]) {
diff --git a/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma.c b/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma.c
index 0b478fc2..57aceb8d 100644
--- a/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma.c
+++ b/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma.c
@@ -153,7 +153,7 @@ int XAxiCdma_ResetIsDone(XAxiCdma *InstancePtr)
  * @note	None.
  *
  *****************************************************************************/
-int XAxiCdma_CfgInitialize(XAxiCdma *InstancePtr, XAxiCdma_Config *CfgPtr,
+u32 XAxiCdma_CfgInitialize(XAxiCdma *InstancePtr, XAxiCdma_Config *CfgPtr,
 		u32 EffectiveAddr)
 {
 	u32 RegValue;
@@ -167,6 +167,7 @@ int XAxiCdma_CfgInitialize(XAxiCdma *InstancePtr, XAxiCdma_Config *CfgPtr,
 	InstancePtr->HasDRE = CfgPtr->HasDRE;
 	InstancePtr->IsLite = CfgPtr->IsLite;
 	InstancePtr->WordLength = ((unsigned int)CfgPtr->DataWidth) >> 3;
+	InstancePtr->AddrWidth = CfgPtr->AddrWidth;
 
 	/* AXI CDMA supports 32 bits data width and up
 	 */
@@ -419,9 +420,8 @@ int XAxiCdma_SwitchMode(XAxiCdma *InstancePtr, int Mode)
 			/* Update the CDESC register, because the hardware is
 			 * to start from the CDESC
 			 */
-			XAxiCdma_WriteReg(InstancePtr->BaseAddr,
-			    XAXICDMA_CDESC_OFFSET,
-			    (u32)InstancePtr->BdaRestart);
+			XAxiCdma_BdSetCurBdPtr(InstancePtr,
+				(UINTPTR)InstancePtr->BdaRestart);
 
 			return XST_SUCCESS;
 		}
@@ -464,7 +464,7 @@ int XAxiCdma_SwitchMode(XAxiCdma *InstancePtr, int Mode)
  * 		function to be NULL.
  *
  *****************************************************************************/
-int XAxiCdma_SimpleTransfer(XAxiCdma *InstancePtr, u32 SrcAddr, u32 DstAddr,
+u32 XAxiCdma_SimpleTransfer(XAxiCdma *InstancePtr, UINTPTR SrcAddr, UINTPTR DstAddr,
 	int Length, XAxiCdma_CallBackFn SimpleCallBack, void *CallBackRef)
 {
 	u32 WordBits;
@@ -533,9 +533,18 @@ int XAxiCdma_SimpleTransfer(XAxiCdma *InstancePtr, u32 SrcAddr, u32 DstAddr,
 	InstancePtr->SimpleCallBackRef = CallBackRef;
 
 	XAxiCdma_WriteReg(InstancePtr->BaseAddr, XAXICDMA_SRCADDR_OFFSET,
-		SrcAddr);
+			  LOWER_32_BITS(SrcAddr));
+	if (InstancePtr->AddrWidth > 32)
+		XAxiCdma_WriteReg(InstancePtr->BaseAddr,
+				  XAXICDMA_SRCADDR_MSB_OFFSET,
+				  UPPER_32_BITS(SrcAddr));
+
 	XAxiCdma_WriteReg(InstancePtr->BaseAddr, XAXICDMA_DSTADDR_OFFSET,
-		DstAddr);
+			  LOWER_32_BITS(DstAddr));
+	if (InstancePtr->AddrWidth > 32)
+		XAxiCdma_WriteReg(InstancePtr->BaseAddr,
+				  XAXICDMA_DSTADDR_MSB_OFFSET,
+				  UPPER_32_BITS(DstAddr));
 
 	/* Writing to the BTT register starts the transfer
 	 */
@@ -676,12 +685,20 @@ void XAxiCdma_DumpRegisters(XAxiCdma *InstancePtr)
 		XAxiCdma_ReadReg(RegBase, XAXICDMA_SR_OFFSET));
 	xil_printf("Current BD register: %x\r\n",
 		XAxiCdma_ReadReg(RegBase, XAXICDMA_CDESC_OFFSET));
+	xil_printf("Current BD MSB register: %x\r\n",
+		XAxiCdma_ReadReg(RegBase, XAXICDMA_CDESC_MSB_OFFSET));
 	xil_printf("Tail BD register: %x\r\n",
 		XAxiCdma_ReadReg(RegBase, XAXICDMA_TDESC_OFFSET));
+	xil_printf("Tail BD MSB register: %x\r\n",
+			XAxiCdma_ReadReg(RegBase, XAXICDMA_TDESC_MSB_OFFSET));
 	xil_printf("Source Addr register: %x\r\n",
 		XAxiCdma_ReadReg(RegBase, XAXICDMA_SRCADDR_OFFSET));
+	xil_printf("Source Addr MSB register: %x\r\n",
+		XAxiCdma_ReadReg(RegBase, XAXICDMA_SRCADDR_MSB_OFFSET));
 	xil_printf("Destination Addr register: %x\r\n",
 		XAxiCdma_ReadReg(RegBase, XAXICDMA_DSTADDR_OFFSET));
+	xil_printf("Destination Addr MSB register: %x\r\n",
+		XAxiCdma_ReadReg(RegBase, XAXICDMA_DSTADDR_MSB_OFFSET));
 	xil_printf("BTT register: %x\r\n",
 		XAxiCdma_ReadReg(RegBase, XAXICDMA_BTT_OFFSET));
 
diff --git a/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma.h b/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma.h
index 9abad3be..c0d7635c 100644
--- a/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma.h
+++ b/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma.h
@@ -330,6 +330,7 @@
  * 		       Added logic to check if DDR is present in the test app
  *		       tcl file. (CR 700806)
  * 3.0   adk  19/12/13 Updated as per the New Tcl API's
+ * 4.0	 adk  27/07/15 Added support for 64-bit Addressing.
  * </pre>
  *****************************************************************************/
 
@@ -416,11 +417,12 @@ typedef struct {
  */
 typedef struct {
 	u32 DeviceId;             /**< Unique ID of this instance */
-	u32 BaseAddress;          /**< Physical address of this instance */
+	UINTPTR BaseAddress;          /**< Physical address of this instance */
 	int HasDRE;               /**< Whether support unaligned transfers */
 	int IsLite;               /**< Whether hardware build is lite mode */
 	int DataWidth;            /**< Length of a word in bits */
 	int BurstLen;             /**< Burst length */
+	int AddrWidth;		  /**< Address Width */
 }XAxiCdma_Config;
 
 /**
@@ -432,7 +434,7 @@ typedef struct {
  * @{
  */
 typedef struct {
-	u32 BaseAddr;         /**< Virtual base address of the DMA engine */
+	UINTPTR BaseAddr;         /**< Virtual base address of the DMA engine */
 
 	int Initialized;      /**< The driver/engine in working state */
 	int SimpleOnlyBuild;  /**< Whether hardware is simple only build */
@@ -444,9 +446,9 @@ typedef struct {
 	int SGWaiting;        /**< Flag that SG transfers are waiting */
 
 	/* BD ring fields for SG transfer */
-	u32 FirstBdPhysAddr;  /**< Physical address of 1st BD in list */
-	u32 FirstBdAddr;      /**< Virtual address of 1st BD in list */
-	u32 LastBdAddr;       /**< Virtual address of last BD in the list */
+	UINTPTR FirstBdPhysAddr;  /**< Physical address of 1st BD in list */
+	UINTPTR FirstBdAddr;      /**< Virtual address of 1st BD in list */
+	UINTPTR LastBdAddr;       /**< Virtual address of last BD in the list */
 	u32 BdRingTotalLen;   /**< Total size of ring in bytes */
 	u32 BdSeparation;     /**< Distance between adjacent BDs in bytes */
 	XAxiCdma_Bd *FreeBdHead;   /**< First BD in the free group */
@@ -470,6 +472,7 @@ typedef struct {
 	int SgHandlerTail;             /**< Last active sg transfer handler */
 	XAxiCdma_IntrHandlerList Handlers[XAXICDMA_MAXIMUM_MAX_HANDLER];
 	                               /**< List of interrupt handlers */
+	int AddrWidth;		  /**< Address Width */
 
 }XAxiCdma;
 /* @} */
@@ -483,7 +486,10 @@ typedef struct {
  * XCACHE_FLUSH_DCACHE_RANGE and XCACHE_INVALIDATE_DCACHE_RANGE macros are not
  * implemented or they do nothing.
  *****************************************************************************/
-#ifdef __MICROBLAZE__
+#ifdef __aarch64__
+#define XAXICDMA_CACHE_FLUSH(BdPtr)
+#define XAXICDMA_CACHE_INVALIDATE(BdPtr)
+#elif __MICROBLAZE__
 #ifdef XCACHE_FLUSH_DCACHE_RANGE
 #define XAXICDMA_CACHE_FLUSH(BdPtr)               \
       XCACHE_FLUSH_DCACHE_RANGE((BdPtr), XAXICDMA_BD_HW_NUM_BYTES)
@@ -512,7 +518,7 @@ typedef struct {
 
 XAxiCdma_Config *XAxiCdma_LookupConfig(u32 DeviceId);
 
-int XAxiCdma_CfgInitialize(XAxiCdma *InstancePtr, XAxiCdma_Config *CfgPtr,
+u32 XAxiCdma_CfgInitialize(XAxiCdma *InstancePtr, XAxiCdma_Config *CfgPtr,
         u32 EffectiveAddr);
 void XAxiCdma_Reset(XAxiCdma *InstancePtr);
 int XAxiCdma_ResetIsDone(XAxiCdma *InstancePtr);
@@ -525,34 +531,36 @@ void XAxiCdma_IntrEnable(XAxiCdma *InstancePtr, u32 Mask);
 u32 XAxiCdma_IntrGetEnabled(XAxiCdma *InstancePtr);
 void XAxiCdma_IntrDisable(XAxiCdma *InstancePtr, u32 Mask);
 void XAxiCdma_IntrHandler(void *HandlerRef);
-int XAxiCdma_SimpleTransfer(XAxiCdma *InstancePtr, u32 SrcAddr, u32 DstAddr,
+u32 XAxiCdma_SimpleTransfer(XAxiCdma *InstancePtr, UINTPTR SrcAddr, UINTPTR DstAddr,
         int Length, XAxiCdma_CallBackFn SimpleCallBack, void *CallbackRef);
 int XAxiCdma_SelectKeyHole(XAxiCdma *InstancePtr, u32 Direction, u32 Select);
 
 /* BD ring API functions
  */
-int XAxiCdma_BdRingCntCalc(u32 Alignment, u32 Bytes, u32 BuffAddr);
-int XAxiCdma_BdRingMemCalc(u32 Alignment, int NumBd);
-int XAxiCdma_BdRingGetCnt(XAxiCdma *InstancePtr);
-int XAxiCdma_BdRingGetFreeCnt(XAxiCdma *InstancePtr);
+u32 XAxiCdma_BdRingCntCalc(u32 Alignment, u32 Bytes, u32 BuffAddr);
+u32 XAxiCdma_BdRingMemCalc(u32 Alignment, int NumBd);
+u32 XAxiCdma_BdRingGetCnt(XAxiCdma *InstancePtr);
+u32 XAxiCdma_BdRingGetFreeCnt(XAxiCdma *InstancePtr);
 void XAxiCdma_BdRingSnapShotCurrBd(XAxiCdma *InstancePtr);
 XAxiCdma_Bd *XAxiCdma_BdRingGetCurrBd(XAxiCdma *InstancePtr);
 XAxiCdma_Bd *XAxiCdma_BdRingNext(XAxiCdma *InstancePtr, XAxiCdma_Bd *BdPtr);
 XAxiCdma_Bd *XAxiCdma_BdRingPrev(XAxiCdma *InstancePtr, XAxiCdma_Bd *BdPtr);
-int XAxiCdma_BdRingCreate(XAxiCdma *InstancePtr, u32 PhysAddr,
-        u32 VirtAddr, u32 Alignment, int BdCount);
-int XAxiCdma_BdRingClone(XAxiCdma *InstancePtr, XAxiCdma_Bd * TemplateBdPtr);
-int XAxiCdma_BdRingAlloc(XAxiCdma *InstancePtr, int NumBd,
+LONG XAxiCdma_BdRingCreate(XAxiCdma *InstancePtr, UINTPTR PhysAddr,
+        UINTPTR VirtAddr, u32 Alignment, int BdCount);
+LONG XAxiCdma_BdRingClone(XAxiCdma *InstancePtr, XAxiCdma_Bd * TemplateBdPtr);
+LONG XAxiCdma_BdRingAlloc(XAxiCdma *InstancePtr, int NumBd,
 	XAxiCdma_Bd ** BdSetPtr);
-int XAxiCdma_BdRingUnAlloc(XAxiCdma *InstancePtr, int NumBd,
+LONG XAxiCdma_BdRingUnAlloc(XAxiCdma *InstancePtr, int NumBd,
 	XAxiCdma_Bd * BdSetPtr);
-int XAxiCdma_BdRingToHw(XAxiCdma *InstancePtr, int NumBd,
+LONG XAxiCdma_BdRingToHw(XAxiCdma *InstancePtr, int NumBd,
         XAxiCdma_Bd * BdSetPtr, XAxiCdma_CallBackFn CallBack,
         void *CallBackRef);
-int XAxiCdma_BdRingFromHw(XAxiCdma *InstancePtr, int BdLimit,
+u32 XAxiCdma_BdRingFromHw(XAxiCdma *InstancePtr, int BdLimit,
         XAxiCdma_Bd ** BdSetPtr);
-int XAxiCdma_BdRingFree(XAxiCdma *InstancePtr, int NumBd,
+u32 XAxiCdma_BdRingFree(XAxiCdma *InstancePtr, int NumBd,
         XAxiCdma_Bd * BdSetPtr);
+void XAxiCdma_BdSetCurBdPtr(XAxiCdma *InstancePtr, UINTPTR CurBdPtr);
+void XAxiCdma_BdSetTailBdPtr(XAxiCdma *InstancePtr, UINTPTR TailBdPtr);
 
 /* Debug utility function
  */
diff --git a/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_bd.c b/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_bd.c
index f96fa1ee..f8f375d0 100644
--- a/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_bd.c
+++ b/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_bd.c
@@ -51,6 +51,7 @@
 
 /***************************** Include Files *********************************/
 #include "xaxicdma.h"
+#include "xaxicdma_bd.h"
 
 #define XAXICDMA_PAGE_SIZE  0x1000
 
@@ -71,7 +72,7 @@
  *****************************************************************************/
 void XAxiCdma_BdClear(XAxiCdma_Bd* BdPtr)
 {
-	memset((void *)((u32)BdPtr + XAXICDMA_BD_START_CLEAR), 0,
+	memset((void *)((UINTPTR)BdPtr + XAXICDMA_BD_START_CLEAR), 0,
 	    XAXICDMA_BD_TO_CLEAR);
 
 	return;
@@ -92,8 +93,8 @@ void XAxiCdma_BdClear(XAxiCdma_Bd* BdPtr)
 void XAxiCdma_BdClone(XAxiCdma_Bd *BdPtr, XAxiCdma_Bd *TmpBd)
 {
 
-	memcpy((void *)((u32)BdPtr + XAXICDMA_BD_START_CLEAR),
-	    (void *)((u32)TmpBd + XAXICDMA_BD_START_CLEAR),
+	memcpy((void *)((UINTPTR)BdPtr + XAXICDMA_BD_START_CLEAR),
+	    (void *)((UINTPTR)TmpBd + XAXICDMA_BD_START_CLEAR),
 	    XAXICDMA_BD_TO_CLEAR);
 
 	return;
@@ -110,10 +111,17 @@ void XAxiCdma_BdClone(XAxiCdma_Bd *BdPtr, XAxiCdma_Bd *TmpBd)
  * @note	None.
  *
  *****************************************************************************/
-u32 XAxiCdma_BdGetNextPtr(XAxiCdma_Bd* BdPtr)
+LONG XAxiCdma_BdGetNextPtr(XAxiCdma_Bd* BdPtr)
 {
+	u32 addrlen;
+	addrlen = XAxiCdma_BdGetAddrLength(BdPtr);
 
-	return (u32)(XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_NDESC_OFFSET));
+	if (addrlen > 32) {
+		return (u64)((XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_NDESC_OFFSET)) |
+		((uint64_t)(XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_NDESC_MSB_OFFSET)) << 32U));
+	} else {
+		return (u32)(XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_NDESC_OFFSET));
+	}
 }
 
 /*****************************************************************************/
@@ -128,11 +136,16 @@ u32 XAxiCdma_BdGetNextPtr(XAxiCdma_Bd* BdPtr)
  * @note	None.
  *
  *****************************************************************************/
-void XAxiCdma_BdSetNextPtr(XAxiCdma_Bd* BdPtr, u32 NextBdPtr)
+void XAxiCdma_BdSetNextPtr(XAxiCdma_Bd* BdPtr, UINTPTR NextBdPtr)
 {
+	u32 addrlen;
+        addrlen = XAxiCdma_BdGetAddrLength(BdPtr);
 
-	XAxiCdma_BdWrite(BdPtr, XAXICDMA_BD_NDESC_OFFSET, NextBdPtr);
-
+	XAxiCdma_BdWrite(BdPtr, XAXICDMA_BD_NDESC_OFFSET,
+                         (NextBdPtr & XAXICDMA_DESC_LSB_MASK));
+	if (addrlen > 32)
+		XAxiCdma_BdWrite(BdPtr, XAXICDMA_BD_NDESC_MSB_OFFSET,
+				 UPPER_32_BITS(NextBdPtr));
 	return;
 }
 
@@ -193,8 +206,10 @@ void XAxiCdma_BdClearSts(XAxiCdma_Bd* BdPtr)
  * @note	None.
  *
  *****************************************************************************/
-int XAxiCdma_BdSetSrcBufAddr(XAxiCdma_Bd* BdPtr, u32 Addr)
+u32 XAxiCdma_BdSetSrcBufAddr(XAxiCdma_Bd* BdPtr, UINTPTR Addr)
 {
+	u32 addrlen;
+        addrlen = XAxiCdma_BdGetAddrLength(BdPtr);
 
 	if (XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_HASDRE_OFFSET) == 0) {
 
@@ -209,7 +224,10 @@ int XAxiCdma_BdSetSrcBufAddr(XAxiCdma_Bd* BdPtr, u32 Addr)
 		}
 	}
 
-	XAxiCdma_BdWrite(BdPtr, XAXICDMA_BD_BUFSRC_OFFSET, Addr);
+	XAxiCdma_BdWrite(BdPtr, XAXICDMA_BD_BUFSRC_OFFSET, LOWER_32_BITS(Addr));
+	if (addrlen > 32)
+		XAxiCdma_BdWrite(BdPtr, XAXICDMA_BD_BUFSRC_MSB_OFFSET,
+				 UPPER_32_BITS(Addr));
 
 	return XST_SUCCESS;
 }
@@ -225,10 +243,17 @@ int XAxiCdma_BdSetSrcBufAddr(XAxiCdma_Bd* BdPtr, u32 Addr)
  * @note	None.
  *
  *****************************************************************************/
-u32 XAxiCdma_BdGetSrcBufAddr(XAxiCdma_Bd* BdPtr)
+LONG XAxiCdma_BdGetSrcBufAddr(XAxiCdma_Bd* BdPtr)
 {
+	u32 addrlen;
+        addrlen = XAxiCdma_BdGetAddrLength(BdPtr);
 
-	return (u32)(XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_BUFSRC_OFFSET));
+	if (addrlen > 32)
+		return (u64)((XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_BUFSRC_OFFSET)) |
+			((uint64_t)(XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_BUFSRC_MSB_OFFSET))
+				<< 32U));
+	else
+		return (u32)(XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_BUFSRC_OFFSET));
 }
 
 /*****************************************************************************/
@@ -246,8 +271,11 @@ u32 XAxiCdma_BdGetSrcBufAddr(XAxiCdma_Bd* BdPtr)
  * @note	None.
  *
  *****************************************************************************/
-int XAxiCdma_BdSetDstBufAddr(XAxiCdma_Bd* BdPtr, u32 Addr)
+u32 XAxiCdma_BdSetDstBufAddr(XAxiCdma_Bd* BdPtr, UINTPTR Addr)
 {
+	u32 addrlen;
+        addrlen = XAxiCdma_BdGetAddrLength(BdPtr);
+
 	if (XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_HASDRE_OFFSET) == 0) {
 
 		if (Addr &
@@ -260,7 +288,10 @@ int XAxiCdma_BdSetDstBufAddr(XAxiCdma_Bd* BdPtr, u32 Addr)
 		}
 	}
 
-	XAxiCdma_BdWrite(BdPtr, XAXICDMA_BD_BUFDST_OFFSET, Addr);
+	XAxiCdma_BdWrite(BdPtr, XAXICDMA_BD_BUFDST_OFFSET, LOWER_32_BITS(Addr));
+	if (addrlen > 32)
+		XAxiCdma_BdWrite(BdPtr, XAXICDMA_BD_BUFDST_MSB_OFFSET,
+				 UPPER_32_BITS(Addr));
 
 	return XST_SUCCESS;
 }
@@ -276,10 +307,16 @@ int XAxiCdma_BdSetDstBufAddr(XAxiCdma_Bd* BdPtr, u32 Addr)
  * @note	None
  *
  *****************************************************************************/
-u32 XAxiCdma_BdGetDstBufAddr(XAxiCdma_Bd* BdPtr)
+LONG XAxiCdma_BdGetDstBufAddr(XAxiCdma_Bd* BdPtr)
 {
+	u32 addrlen;
+    addrlen = XAxiCdma_BdGetAddrLength(BdPtr);
 
-	return (u32)(XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_BUFDST_OFFSET));
+	if (addrlen > 32)
+		return (u64) (XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_BUFDST_OFFSET) |
+			((uint64_t)(XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_BUFDST_MSB_OFFSET)) << 32U));
+	else
+		return (u32)(XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_BUFDST_OFFSET));
 }
 
 /*****************************************************************************/
@@ -300,7 +337,7 @@ u32 XAxiCdma_BdGetDstBufAddr(XAxiCdma_Bd* BdPtr)
  *		slave error if the hardware is built in lite mode.
  *
  *****************************************************************************/
-int XAxiCdma_BdSetLength(XAxiCdma_Bd* BdPtr, int LenBytes)
+u32 XAxiCdma_BdSetLength(XAxiCdma_Bd* BdPtr, int LenBytes)
 {
 	int MaxLen;
 
@@ -326,7 +363,7 @@ int XAxiCdma_BdSetLength(XAxiCdma_Bd* BdPtr, int LenBytes)
  * @note	None
  *
  *****************************************************************************/
-int XAxiCdma_BdGetLength(XAxiCdma_Bd* BdPtr)
+u32 XAxiCdma_BdGetLength(XAxiCdma_Bd* BdPtr)
 {
 
 	return (u32)(XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_CTRL_LEN_OFFSET));
@@ -344,10 +381,15 @@ int XAxiCdma_BdGetLength(XAxiCdma_Bd* BdPtr)
  * @note	None
  *
  *****************************************************************************/
-void XAxiCdma_BdSetPhysAddr(XAxiCdma_Bd* BdPtr, u32 PhysAddr)
+void XAxiCdma_BdSetPhysAddr(XAxiCdma_Bd* BdPtr, UINTPTR PhysAddr)
 {
+	u32 addrlen;
+    addrlen = XAxiCdma_BdGetAddrLength(BdPtr);
 
 	XAxiCdma_BdWrite(BdPtr, XAXICDMA_BD_PHYS_ADDR_OFFSET, PhysAddr);
+	if (addrlen > 32)
+                XAxiCdma_BdWrite(BdPtr, XAXICDMA_BD_PHYS_ADDR_MSB_OFFSET,
+				 UPPER_32_BITS(PhysAddr));
 
 	return;
 }
@@ -443,10 +485,17 @@ void XAxiCdma_BdSetMaxLen(XAxiCdma_Bd* BdPtr, int MaxLen)
  * @note	None
  *
  *****************************************************************************/
-u32 XAxiCdma_BdGetPhysAddr(XAxiCdma_Bd* BdPtr)
+LONG XAxiCdma_BdGetPhysAddr(XAxiCdma_Bd* BdPtr)
 {
+	 u32 addrlen;
+        addrlen = XAxiCdma_BdGetAddrLength(BdPtr);
 
-	return (u32)(XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_PHYS_ADDR_OFFSET));
+	 if (addrlen > 32)
+             return (u64)((XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_PHYS_ADDR_OFFSET)) |
+                       ((uint64_t)(XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_PHYS_ADDR_MSB_OFFSET))
+                                << 32U));
+        else
+             return (u32)(XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_PHYS_ADDR_OFFSET));
 }
 
 /*****************************************************************************/
@@ -462,7 +511,7 @@ u32 XAxiCdma_BdGetPhysAddr(XAxiCdma_Bd* BdPtr)
  *****************************************************************************/
 void XAxiCdma_DumpBd(XAxiCdma_Bd* BdPtr)
 {
-	xil_printf("\r\nDump BD %x:\r\n", (unsigned int)BdPtr);
+	xil_printf("\r\nDump BD %x:\r\n", (UINTPTR)BdPtr);
 
 	xil_printf("Next BD ptr \t%x\r\n",
 	    (unsigned int)XAxiCdma_BdGetNextPtr(BdPtr));
diff --git a/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_bd.h b/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_bd.h
index 9b6577d6..f161bdc6 100644
--- a/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_bd.h
+++ b/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_bd.h
@@ -71,19 +71,20 @@ extern "C" {
  * inside a BD:
  *
  *  u32 NextBdPtr;
- *  u32 Pad1;  -- This is always 0
+ *  u32 NextBdPtrMsb;
  *  u32 SrcAddr;
- *  u32 Pad2;  -- This is always 0
+ *  u32 SrcAddrMsb;
  *  u32 DstAddr;
- *  u32 Pad3;  -- This is always 0
+ *  u32 DstAddrMsb;
  *  int Length;
  *  u32 Status;
  *  u32 PhysAddr;
  *  u32 IsLite;
  *  u32 HasDRE;
  *  u32 WordLen;
+ *  u32 Addrlen;
  */
-typedef u32 XAxiCdma_Bd[XAXICDMA_BD_NUM_WORDS];
+typedef UINTPTR XAxiCdma_Bd[XAXICDMA_BD_NUM_WORDS];
 
 /**************************** Macros (Inline Functions) Definitions **********/
 
@@ -95,7 +96,7 @@ typedef u32 XAxiCdma_Bd[XAXICDMA_BD_NUM_WORDS];
  *   u32 XAxiCdma_BdRead(XAxiCdma_Bd* BdPtr, int Offset);
  *****************************************************************************/
 #define XAxiCdma_BdRead(BdPtr, Offset)   \
-	*(u32 *)((u32)(BdPtr) + (u32)(Offset))
+	(*(u32 *)((UINTPTR)((void *)(BdPtr)) + (u32)(Offset)))
 
 /*****************************************************************************/
 /* Macros to write to a word in a BD
@@ -105,29 +106,57 @@ typedef u32 XAxiCdma_Bd[XAXICDMA_BD_NUM_WORDS];
  *    u32 XAxiCdma_BdWrite(XAxiCdma_Bd* BdPtr, int Offset, u32 Value )
  *****************************************************************************/
 #define XAxiCdma_BdWrite(BdPtr, Offset, Value)   \
-	*(u32 *)((u32)(BdPtr) + (u32)(Offset)) = (u32)(Value)
+	(*(u32 *)((UINTPTR)(void *)(BdPtr) + (u32)(Offset))) = (u32)(Value)
+
+/*****************************************************************************/
+/* Set the Addrelen field of the BD.
+ *
+ * @param  BdPtr is the BD to operate on
+ * @param  Addrlen is the Address width of the CDMA
+ *
+ * @note
+ * 	C-style signature:
+ *	u32 XAxiCdma_BdSetAddrLen(XAxiCdma_Bd* BdPtr, int AddrLen)
+ *****************************************************************************/
+#define XAxiCdma_BdSetAddrLen(BdPtr, AddrLen)   \
+       XAxiCdma_BdWrite(BdPtr, XAXICDMA_BD_ADDRLEN_OFFSET, AddrLen);
+
+/*****************************************************************************/
+/* Get the BD's Address length
+ *
+ * @param  BdPtr is the BD to operate on
+ *
+ * @return None
+ *
+ * @note
+ *	C-style signature:
+ *	u32 XAxiCdma_BdGetAddrLength(XAxiCdma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiCdma_BdGetAddrLength(BdPtr)   \
+       XAxiCdma_BdRead(BdPtr, XAXICDMA_BD_ADDRLEN_OFFSET);
 
 
 /************************** Function Prototypes ******************************/
 
 void XAxiCdma_BdClear(XAxiCdma_Bd *BdPtr);
 void XAxiCdma_BdClone(XAxiCdma_Bd *BdPtr, XAxiCdma_Bd *TmpBd);
-u32 XAxiCdma_BdGetNextPtr(XAxiCdma_Bd *BdPtr);
-void XAxiCdma_BdSetNextPtr(XAxiCdma_Bd *BdPtr, u32 NextBdPtr);
+LONG XAxiCdma_BdGetNextPtr(XAxiCdma_Bd *BdPtr);
+void XAxiCdma_BdSetNextPtr(XAxiCdma_Bd *BdPtr, UINTPTR NextBdPtr);
 u32 XAxiCdma_BdGetSts(XAxiCdma_Bd *BdPtr);
 void XAxiCdma_BdClearSts(XAxiCdma_Bd *BdPtr);
-int XAxiCdma_BdSetSrcBufAddr(XAxiCdma_Bd *BdPtr, u32 Addr);
-u32 XAxiCdma_BdGetSrcBufAddr(XAxiCdma_Bd *BdPtr);
-int XAxiCdma_BdSetDstBufAddr(XAxiCdma_Bd *BdPtr, u32 Addr);
-u32 XAxiCdma_BdGetDstBufAddr(XAxiCdma_Bd *BdPtr);
-int XAxiCdma_BdSetLength(XAxiCdma_Bd *BdPtr, int LenBytes);
-int XAxiCdma_BdGetLength(XAxiCdma_Bd *BdPtr);
-void XAxiCdma_BdSetPhysAddr(XAxiCdma_Bd *BdPtr, u32 PhysAddr);
+u32 XAxiCdma_BdSetSrcBufAddr(XAxiCdma_Bd *BdPtr, UINTPTR Addr);
+LONG XAxiCdma_BdGetSrcBufAddr(XAxiCdma_Bd *BdPtr);
+u32 XAxiCdma_BdSetDstBufAddr(XAxiCdma_Bd *BdPtr, UINTPTR Addr);
+LONG XAxiCdma_BdGetDstBufAddr(XAxiCdma_Bd *BdPtr);
+u32 XAxiCdma_BdSetLength(XAxiCdma_Bd *BdPtr, int LenBytes);
+u32 XAxiCdma_BdGetLength(XAxiCdma_Bd *BdPtr);
+void XAxiCdma_BdSetPhysAddr(XAxiCdma_Bd *BdPtr, UINTPTR PhysAddr);
 void XAxiCdma_BdSetIsLite(XAxiCdma_Bd *BdPtr, int IsLite);
 void XAxiCdma_BdSetHasDRE(XAxiCdma_Bd *BdPtr, int HasDRE);
 void XAxiCdma_BdSetWordLen(XAxiCdma_Bd *BdPtr, int WordLen);
 void XAxiCdma_BdSetMaxLen(XAxiCdma_Bd *BdPtr, int MaxLen);
-u32 XAxiCdma_BdGetPhysAddr(XAxiCdma_Bd *BdPtr);
+LONG XAxiCdma_BdGetPhysAddr(XAxiCdma_Bd *BdPtr);
 
 void XAxiCdma_DumpBd(XAxiCdma_Bd* BdPtr);
 
diff --git a/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_bdring.c b/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_bdring.c
index de5d63ac..4158d341 100644
--- a/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_bdring.c
+++ b/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_bdring.c
@@ -73,14 +73,14 @@
  *****************************************************************************/
 #define XAXICDMA_RING_SEEKAHEAD(InstancePtr, BdPtr, NumBd)         \
 {                                                                  \
-    u32 Addr = (u32)(BdPtr);                                       \
+    UINTPTR Addr = (UINTPTR)(void *)(BdPtr);                       \
                                                                    \
     Addr += ((InstancePtr)->BdSeparation * (NumBd));               \
     if (Addr > (InstancePtr)->LastBdAddr) {                        \
         Addr -= (InstancePtr)->BdRingTotalLen;                     \
     }                                                              \
                                                                    \
-    (BdPtr) = (XAxiCdma_Bd*)Addr;                                  \
+    (BdPtr) = (XAxiCdma_Bd *)(void *)Addr;                                  \
 }
 
 /******************************************************************************
@@ -100,14 +100,14 @@
  *****************************************************************************/
 #define XAXICDMA_RING_SEEKBACK(InstancePtr, BdPtr, NumBd)        \
 {                                                                \
-    u32 Addr = (u32)(BdPtr);                                     \
+    UINTPTR Addr = (UINTPTR)(void *)(BdPtr);                                     \
                                                                  \
     Addr -= ((InstancePtr)->BdSeparation * (NumBd));             \
     if (Addr < (InstancePtr)->FirstBdAddr) {                     \
         Addr += (InstancePtr)->BdRingTotalLen;                   \
     }                                                            \
                                                                  \
-    (BdPtr) = (XAxiCdma_Bd*)Addr;                                \
+    (BdPtr) = (XAxiCdma_Bd*)(void *)Addr;                                \
 }
 
 /*****************************************************************************/
@@ -129,7 +129,7 @@
  *			it to this function.
  *
  *****************************************************************************/
-int XAxiCdma_BdRingCntCalc(u32 Alignment, u32 Bytes, u32 BdBuffAddr)
+u32 XAxiCdma_BdRingCntCalc(u32 Alignment, u32 Bytes, u32 BdBuffAddr)
 {
 
 	/* The buffer alignment has to be taken account of. An unaligned buffer
@@ -141,7 +141,7 @@ int XAxiCdma_BdRingCntCalc(u32 Alignment, u32 Bytes, u32 BdBuffAddr)
 		return 0;
 	}
 
-	return ((int)(Bytes) / ((sizeof(XAxiCdma_Bd) + (Alignment - 1)) &
+	return ((uint32_t)(Bytes) / ((sizeof(XAxiCdma_Bd) + (Alignment - 1)) &
                ~(Alignment - 1)));
 }
 
@@ -158,12 +158,56 @@ int XAxiCdma_BdRingCntCalc(u32 Alignment, u32 Bytes, u32 BdBuffAddr)
  * @note	None.
  *
  *****************************************************************************/
-int XAxiCdma_BdRingMemCalc(u32 Alignment, int NumBd)
+u32 XAxiCdma_BdRingMemCalc(u32 Alignment, int NumBd)
 {
-	return (int)(((sizeof(XAxiCdma_Bd) + (Alignment - 1)) &
+	return (uint32_t)(((sizeof(XAxiCdma_Bd) + (Alignment - 1)) &
                ~(Alignment - 1)) * NumBd);
 }
 
+/*****************************************************************************/
+/**
+ * This function set the Current BD ptr of a BD
+ *
+ * @param       BdPtr is the pointer to the BD to set the Next BD ptr
+ * @param       CurBdPtr is the valud of Current BD ptr
+ *
+ * @return      None
+ *
+ * @note        None.
+ *
+ *****************************************************************************/
+void XAxiCdma_BdSetCurBdPtr(XAxiCdma *InstancePtr, UINTPTR CurBdPtr)
+{
+	XAxiCdma_WriteReg(InstancePtr->BaseAddr, XAXICDMA_CDESC_OFFSET,
+                          (CurBdPtr & XAXICDMA_DESC_LSB_MASK));
+    if (InstancePtr->AddrWidth > 32)
+         XAxiCdma_WriteReg(InstancePtr->BaseAddr, XAXICDMA_CDESC_MSB_OFFSET,
+			   UPPER_32_BITS(CurBdPtr));
+        return;
+}
+
+/*****************************************************************************/
+/**
+ * This function grabs a copy of the current BD pointer from the hardware.
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ *
+ * @return	The BD pointer in CDESC register
+ *
+ * @note	None.
+ *
+ *****************************************************************************/
+XAxiCdma_Bd *XAxiCdma_BdRingGetCurrBd(XAxiCdma *InstancePtr)
+{
+
+	if (InstancePtr->AddrWidth > 32) {
+		return (XAxiCdma_Bd *)((XAxiCdma_BdRead(InstancePtr->BaseAddr, XAXICDMA_CDESC_OFFSET)) |
+		((uint64_t)(XAxiCdma_BdRead(InstancePtr->BaseAddr, XAXICDMA_CDESC_MSB_OFFSET)) << 32U));
+	} else {
+		return (XAxiCdma_Bd *)(UINTPTR)(XAxiCdma_BdRead(InstancePtr->BaseAddr, XAXICDMA_CDESC_OFFSET));
+	}
+}
+
 /*****************************************************************************/
 /**
  * This function gets the total number of BDs in the BD ring.
@@ -175,9 +219,9 @@ int XAxiCdma_BdRingMemCalc(u32 Alignment, int NumBd)
  * @note	None.
  *
  *****************************************************************************/
-int XAxiCdma_BdRingGetCnt(XAxiCdma *InstancePtr)
+u32 XAxiCdma_BdRingGetCnt(XAxiCdma *InstancePtr)
 {
-	return InstancePtr->AllBdCnt;
+	return (uint32_t)InstancePtr->AllBdCnt;
 }
 
 /*****************************************************************************/
@@ -191,7 +235,7 @@ int XAxiCdma_BdRingGetCnt(XAxiCdma *InstancePtr)
  * @note	None.
  *
  *****************************************************************************/
-int XAxiCdma_BdRingGetFreeCnt(XAxiCdma *InstancePtr)
+u32 XAxiCdma_BdRingGetFreeCnt(XAxiCdma *InstancePtr)
 {
 	return InstancePtr->FreeBdCnt;
 }
@@ -213,9 +257,7 @@ void XAxiCdma_BdRingSnapShotCurrBd(XAxiCdma *InstancePtr)
 {
 	XAxiCdma_Bd *BdPtr;
 
-	BdPtr = (XAxiCdma_Bd *)XAxiCdma_ReadReg(InstancePtr->BaseAddr,
-	    XAXICDMA_CDESC_OFFSET);
-
+	BdPtr =	XAxiCdma_BdRingGetCurrBd(InstancePtr);
 
 	InstancePtr->BdaRestart = XAxiCdma_BdRingNext(InstancePtr, BdPtr);
 
@@ -224,21 +266,27 @@ void XAxiCdma_BdRingSnapShotCurrBd(XAxiCdma *InstancePtr)
 
 /*****************************************************************************/
 /**
- * This function grabs a copy of the current BD pointer from the hardware.
+ * This function set the Tail BD ptr of a BD
  *
- * @param	InstancePtr is the driver instance we are working on
+ * @param       BdPtr is the pointer to the BD to set the Next BD ptr
+ * @param       Tail Bd is the value of Tail BD ptr
  *
- * @return	The BD pointer in CDESC register
+ * @return      None
  *
- * @note	None.
+ * @note        None.
  *
  *****************************************************************************/
-XAxiCdma_Bd *XAxiCdma_BdRingGetCurrBd(XAxiCdma *InstancePtr)
+void XAxiCdma_BdSetTailBdPtr(XAxiCdma *InstancePtr, UINTPTR TailBdPtr)
 {
-	return (XAxiCdma_Bd *)XAxiCdma_ReadReg(InstancePtr->BaseAddr,
-	    XAXICDMA_CDESC_OFFSET);
+    XAxiCdma_WriteReg(InstancePtr->BaseAddr, XAXICDMA_TDESC_OFFSET,
+                      TailBdPtr & XAXICDMA_DESC_LSB_MASK);
+    if (InstancePtr->AddrWidth > 32)
+            XAxiCdma_WriteReg(InstancePtr->BaseAddr, XAXICDMA_TDESC_MSB_OFFSET,
+                              UPPER_32_BITS(TailBdPtr));
+        return;
 }
 
+
 /*****************************************************************************/
 /**
  * This function gets the next BD of the current BD on the BD ring.
@@ -254,31 +302,31 @@ XAxiCdma_Bd *XAxiCdma_BdRingGetCurrBd(XAxiCdma *InstancePtr)
  *****************************************************************************/
 XAxiCdma_Bd *XAxiCdma_BdRingNext(XAxiCdma *InstancePtr, XAxiCdma_Bd *BdPtr)
 {
-	u32 ReturnBd;
+	UINTPTR ReturnBd;
 
 	/* Check whether the BD ptr is valid
 	 * A BD ptr is not valid if:
 	 * - It is outside of the BD memory range
 	 * - It has invalid alignment
 	 */
-	if (((u32)BdPtr > InstancePtr->LastBdAddr)  ||
-	    ((u32)BdPtr < InstancePtr->FirstBdAddr) ||
-		((u32)BdPtr & (InstancePtr->BdSeparation - 1))) {
+	if (((UINTPTR)BdPtr > InstancePtr->LastBdAddr)  ||
+	    ((UINTPTR)BdPtr < InstancePtr->FirstBdAddr) ||
+		((UINTPTR)BdPtr & (InstancePtr->BdSeparation - 1))) {
 
 		xdbg_printf(XDBG_DEBUG_ERROR, "Invalid BdPtr %x: %x/%x/%x\r\n",
-		(unsigned int)BdPtr, (unsigned int)InstancePtr->FirstBdAddr,
-			(unsigned int)InstancePtr->LastBdAddr,
+		(UINTPTR)BdPtr, (UINTPTR)InstancePtr->FirstBdAddr,
+			(UINTPTR)InstancePtr->LastBdAddr,
 			(unsigned int)XAXICDMA_BD_MINIMUM_ALIGNMENT);
 		ReturnBd = 0x0;
 	}
 
 	/* If the current BD is the last BD in the ring, return the first BD
 	 */
-	else if ((u32)BdPtr == InstancePtr->LastBdAddr) {
+	else if ((UINTPTR)BdPtr == InstancePtr->LastBdAddr) {
 		ReturnBd = InstancePtr->FirstBdAddr;
 	}
 	else {
-		ReturnBd = (u32)BdPtr + InstancePtr->BdSeparation;
+		ReturnBd = (UINTPTR)BdPtr + InstancePtr->BdSeparation;
 	}
 
 	 return (XAxiCdma_Bd *)ReturnBd;
@@ -298,31 +346,31 @@ XAxiCdma_Bd *XAxiCdma_BdRingNext(XAxiCdma *InstancePtr, XAxiCdma_Bd *BdPtr)
  *****************************************************************************/
 XAxiCdma_Bd *XAxiCdma_BdRingPrev(XAxiCdma *InstancePtr, XAxiCdma_Bd *BdPtr)
 {
-	u32 ReturnBd;
+	UINTPTR ReturnBd;
 
 	/* Check whether the BD ptr is valid
 	 * A BD ptr is not valid if:
 	 * - It is outside of the BD memory range
 	 * - It has invalid alignment
 	 */
-	if (((u32)BdPtr > InstancePtr->LastBdAddr)  ||
-	    ((u32)BdPtr < InstancePtr->FirstBdAddr) ||
-		((u32)BdPtr & (InstancePtr->BdSeparation - 1))) {
+	if (((UINTPTR)BdPtr > InstancePtr->LastBdAddr)  ||
+	    ((UINTPTR)BdPtr < InstancePtr->FirstBdAddr) ||
+		((UINTPTR)BdPtr & (InstancePtr->BdSeparation - 1))) {
 
 		xdbg_printf(XDBG_DEBUG_ERROR, "Invalid BdPtr %x: %x/%x/%x\r\n",
-			(unsigned int)BdPtr, (unsigned int)InstancePtr->FirstBdAddr,
-			(unsigned int)InstancePtr->LastBdAddr,
+			(UINTPTR)BdPtr, (UINTPTR)InstancePtr->FirstBdAddr,
+			(UINTPTR)InstancePtr->LastBdAddr,
 		    (unsigned int)XAXICDMA_BD_MINIMUM_ALIGNMENT);
 		ReturnBd = 0x0;
 	}
 
 	/* If the current BD is the first BD in the ring, return the last BD
 	 */
-	else if ((u32)BdPtr == InstancePtr->FirstBdAddr) {
+	else if ((UINTPTR)BdPtr == InstancePtr->FirstBdAddr) {
 		ReturnBd = InstancePtr->LastBdAddr;
 	}
 	else {
-		ReturnBd = (u32)BdPtr - InstancePtr->BdSeparation;
+		ReturnBd = (UINTPTR)BdPtr - InstancePtr->BdSeparation;
 	}
 
 	 return (XAxiCdma_Bd *)ReturnBd;
@@ -349,12 +397,12 @@ XAxiCdma_Bd *XAxiCdma_BdRingPrev(XAxiCdma *InstancePtr, XAxiCdma_Bd *BdPtr)
  *		and the VirtAddr are the same.
  *
  *****************************************************************************/
-int XAxiCdma_BdRingCreate(XAxiCdma *InstancePtr, u32 PhysAddr,
-			u32 VirtAddr, u32 Alignment, int BdCount)
+LONG XAxiCdma_BdRingCreate(XAxiCdma *InstancePtr, UINTPTR PhysAddr,
+			UINTPTR VirtAddr, u32 Alignment, int BdCount)
 {
-	u32 BdVirtAddr;
-	u32 BdNxtPhysAddr;
-	u32 BdPhysAddr;
+	UINTPTR BdVirtAddr;
+	UINTPTR BdNxtPhysAddr;
+	UINTPTR BdPhysAddr;
 	int Index;
 
 	if (InstancePtr->SimpleOnlyBuild) {
@@ -438,7 +486,8 @@ int XAxiCdma_BdRingCreate(XAxiCdma *InstancePtr, u32 PhysAddr,
 	BdPhysAddr = PhysAddr;
 
 	for (Index = 1; Index < BdCount; Index++) {
-
+		XAxiCdma_BdSetAddrLen((XAxiCdma_Bd *)BdVirtAddr,
+		    InstancePtr->AddrWidth);
 		XAxiCdma_BdSetNextPtr((XAxiCdma_Bd *)BdVirtAddr, BdNxtPhysAddr);
 		XAxiCdma_BdSetPhysAddr((XAxiCdma_Bd *)BdVirtAddr, BdPhysAddr);
 		XAxiCdma_BdSetIsLite((XAxiCdma_Bd *)BdVirtAddr,
@@ -459,6 +508,8 @@ int XAxiCdma_BdRingCreate(XAxiCdma *InstancePtr, u32 PhysAddr,
 	/* At the end of the ring, link the last BD back to the top,
 	 * and set its fields
 	 */
+	XAxiCdma_BdSetAddrLen((XAxiCdma_Bd *)BdVirtAddr,
+                    InstancePtr->AddrWidth);
 	XAxiCdma_BdSetNextPtr((XAxiCdma_Bd *)BdVirtAddr, PhysAddr);
 	XAxiCdma_BdSetPhysAddr((XAxiCdma_Bd *)BdVirtAddr, BdPhysAddr);
 	XAxiCdma_BdSetIsLite((XAxiCdma_Bd *)BdVirtAddr,
@@ -478,14 +529,14 @@ int XAxiCdma_BdRingCreate(XAxiCdma *InstancePtr, u32 PhysAddr,
 		InstancePtr->FirstBdAddr + InstancePtr->BdSeparation;
 	InstancePtr->AllBdCnt = BdCount;
 	InstancePtr->FreeBdCnt = BdCount;
-	InstancePtr->FreeBdHead = (XAxiCdma_Bd *) VirtAddr;
+	InstancePtr->FreeBdHead = (XAxiCdma_Bd *) (void *)VirtAddr;
 	InstancePtr->PreBdHead = (XAxiCdma_Bd *) VirtAddr;
 	InstancePtr->HwBdHead = (XAxiCdma_Bd *) VirtAddr;
 	InstancePtr->HwBdTail = (XAxiCdma_Bd *) VirtAddr;
 	InstancePtr->PostBdHead = (XAxiCdma_Bd *) VirtAddr;
-	InstancePtr->BdaRestart = (XAxiCdma_Bd *) PhysAddr;
+	InstancePtr->BdaRestart = (XAxiCdma_Bd *) (void *)PhysAddr;
 
-	return XST_SUCCESS;
+	return (XST_SUCCESS);
 }
 
 /*****************************************************************************/
@@ -505,10 +556,10 @@ int XAxiCdma_BdRingCreate(XAxiCdma *InstancePtr, u32 PhysAddr,
  * @note	None.
  *
  *****************************************************************************/
-int XAxiCdma_BdRingClone(XAxiCdma *InstancePtr, XAxiCdma_Bd * TemplateBdPtr)
+LONG XAxiCdma_BdRingClone(XAxiCdma *InstancePtr, XAxiCdma_Bd * TemplateBdPtr)
 {
 	int Index;
-	u32 CurBd;
+	UINTPTR CurBd;
 	XAxiCdma_Bd TmpBd;
 
 	/* Can't do this function if there isn't a ring */
@@ -574,7 +625,7 @@ int XAxiCdma_BdRingClone(XAxiCdma *InstancePtr, XAxiCdma_Bd * TemplateBdPtr)
  * @note	None.
  *
  *****************************************************************************/
-int XAxiCdma_BdRingAlloc(XAxiCdma *InstancePtr, int NumBd,
+LONG XAxiCdma_BdRingAlloc(XAxiCdma *InstancePtr, int NumBd,
    XAxiCdma_Bd ** BdSetPtr)
 {
 	if (NumBd <= 0) {
@@ -615,7 +666,7 @@ int XAxiCdma_BdRingAlloc(XAxiCdma *InstancePtr, int NumBd,
  * @note	None.
  *
  *****************************************************************************/
-int XAxiCdma_BdRingUnAlloc(XAxiCdma *InstancePtr, int NumBd,
+LONG XAxiCdma_BdRingUnAlloc(XAxiCdma *InstancePtr, int NumBd,
 			 XAxiCdma_Bd * BdSetPtr)
 {
 	XAxiCdma_Bd *TmpBd;
@@ -719,7 +770,7 @@ static void StubCallBackFn(void *CallBackRef, u32 IrqMask, int *NumBdPtr)
  * @note	None.
  *
  *****************************************************************************/
-int XAxiCdma_BdRingToHw(XAxiCdma *InstancePtr, int NumBd,
+LONG XAxiCdma_BdRingToHw(XAxiCdma *InstancePtr, int NumBd,
         XAxiCdma_Bd *BdSetPtr, XAxiCdma_CallBackFn CallBackFn,
         void *CallBackRef)
 {
@@ -780,7 +831,7 @@ int XAxiCdma_BdRingToHw(XAxiCdma *InstancePtr, int NumBd,
 		if (XAxiCdma_BdGetLength(CurBdPtr) == 0) {
 
 			xdbg_printf(XDBG_DEBUG_ERROR,
-			    "0 length bd %x\r\n", (unsigned int)CurBdPtr);
+			    "0 length bd %x\r\n", (UINTPTR)CurBdPtr);
 
 			return XST_INVALID_PARAM;
 		}
@@ -788,7 +839,7 @@ int XAxiCdma_BdRingToHw(XAxiCdma *InstancePtr, int NumBd,
 		XAxiCdma_BdClearSts(CurBdPtr);
 
 		/* Flush the current BD so DMA core could see the updates */
-		XAXICDMA_CACHE_FLUSH((unsigned int)CurBdPtr);
+		XAXICDMA_CACHE_FLUSH((UINTPTR)CurBdPtr);
 
 		CurBdPtr = XAxiCdma_BdRingNext(InstancePtr, CurBdPtr);
 	}
@@ -853,8 +904,9 @@ int XAxiCdma_BdRingToHw(XAxiCdma *InstancePtr, int NumBd,
 	/* The hardware is in SG mode, update the tail BD pointer register
 	 * so that hardware will process the transfer
 	 */
-	XAxiCdma_WriteReg(InstancePtr->BaseAddr, XAXICDMA_TDESC_OFFSET,
-	      XAxiCdma_BdGetPhysAddr((XAxiCdma_Bd *)InstancePtr->HwBdTail));
+	XAxiCdma_BdSetTailBdPtr(InstancePtr,
+				XAxiCdma_BdGetPhysAddr((XAxiCdma_Bd *)InstancePtr->HwBdTail));
+
 
 	return XST_SUCCESS;
 }
@@ -872,7 +924,7 @@ int XAxiCdma_BdRingToHw(XAxiCdma *InstancePtr, int NumBd,
  * @note	None.
  *
  *****************************************************************************/
-int XAxiCdma_BdRingFromHw(XAxiCdma *InstancePtr, int BdLimit,
+u32 XAxiCdma_BdRingFromHw(XAxiCdma *InstancePtr, int BdLimit,
 			     XAxiCdma_Bd ** BdSetPtr)
 {
 	XAxiCdma_Bd *CurBdPtr;
@@ -903,7 +955,7 @@ int XAxiCdma_BdRingFromHw(XAxiCdma *InstancePtr, int BdLimit,
 	 */
 	while (BdCount < BdLimit) {
 		/* Read the status */
-		XAXICDMA_CACHE_INVALIDATE((unsigned int)CurBdPtr);
+		XAXICDMA_CACHE_INVALIDATE((UINTPTR)CurBdPtr);
 		BdSts = XAxiCdma_BdGetSts(CurBdPtr);
 
 		/* If the hardware still hasn't processed this BD then we are
@@ -961,7 +1013,7 @@ int XAxiCdma_BdRingFromHw(XAxiCdma *InstancePtr, int BdLimit,
  * @note	None.
  *
  *****************************************************************************/
-int XAxiCdma_BdRingFree(XAxiCdma *InstancePtr, int NumBd,
+u32 XAxiCdma_BdRingFree(XAxiCdma *InstancePtr, int NumBd,
 		      XAxiCdma_Bd * BdSetPtr)
 {
 	if (NumBd < 0) {
@@ -985,8 +1037,8 @@ int XAxiCdma_BdRingFree(XAxiCdma *InstancePtr, int NumBd,
 		xdbg_printf(XDBG_DEBUG_ERROR, "BdRingFree: Error free BDs: "
 		    "post count %d to free %d, PostBdHead %x to free ptr %x\r\n",
 		    InstancePtr->PostBdCnt, NumBd,
-		    (unsigned int)InstancePtr->PostBdHead,
-		    (unsigned int)BdSetPtr);
+		    (UINTPTR)InstancePtr->PostBdHead,
+		    (UINTPTR)BdSetPtr);
 
 		return XST_DMA_SG_LIST_ERROR;
 	}
@@ -1046,8 +1098,9 @@ int XAxiCdma_BdRingStartTransfer(XAxiCdma *InstancePtr)
 	/* Now it is in SG mode, update the tail pointer to start the
 	 * SG transfer
 	 */
-	XAxiCdma_WriteReg(InstancePtr->BaseAddr, XAXICDMA_TDESC_OFFSET,
-		XAxiCdma_BdGetPhysAddr((XAxiCdma_Bd *)InstancePtr->HwBdTail));
+	XAxiCdma_BdSetTailBdPtr(InstancePtr,
+                XAxiCdma_BdGetPhysAddr((XAxiCdma_Bd *)InstancePtr->HwBdTail));
+
 
 	InstancePtr->SGWaiting = 0;
 
diff --git a/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_hw.h b/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_hw.h
index 87d337e2..7b3934ce 100644
--- a/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_hw.h
+++ b/XilinxProcessorIPLib/drivers/axicdma/src/xaxicdma_hw.h
@@ -82,13 +82,40 @@ extern "C" {
  *   Register accesses are 32-bit.
  * @{
  */
-#define XAXICDMA_CR_OFFSET    	0x00000000  /**< Control register */
-#define XAXICDMA_SR_OFFSET    	0x00000004  /**< Status register */
-#define XAXICDMA_CDESC_OFFSET 	0x00000008  /**< Current descriptor pointer */
-#define XAXICDMA_TDESC_OFFSET	0x00000010  /**< Tail descriptor pointer */
-#define XAXICDMA_SRCADDR_OFFSET 0x00000018  /**< Source address register */
-#define XAXICDMA_DSTADDR_OFFSET 0x00000020  /**< Destination address register */
-#define XAXICDMA_BTT_OFFSET     0x00000028  /**< Bytes to transfer */
+#define XAXICDMA_CR_OFFSET	     0x00000000  /**< Control register */
+#define XAXICDMA_SR_OFFSET	     0x00000004  /**< Status register */
+#define XAXICDMA_CDESC_OFFSET        0x00000008  /**< Current descriptor
+						    pointer */
+#define XAXICDMA_CDESC_MSB_OFFSET    0x0000000C /**< Current descriptor pointer */
+#define XAXICDMA_TDESC_OFFSET	     0x00000010  /**< Tail descriptor pointer */
+#define XAXICDMA_TDESC_MSB_OFFSET    0x00000014  /**< Tail descriptor pointer */
+#define XAXICDMA_SRCADDR_OFFSET	     0x00000018  /**< Source address register */
+#define XAXICDMA_SRCADDR_MSB_OFFSET  0x0000001C /**< Source address register */
+#define XAXICDMA_DSTADDR_OFFSET	     0x00000020  /**< Destination address
+						register */
+#define XAXICDMA_DSTADDR_MSB_OFFSET  0x00000024  /**< Destination address
+						register */
+#define XAXICDMA_BTT_OFFSET          0x00000028  /**< Bytes to transfer */
+/*@}*/
+
+/** @name Bitmasks of XAXICDMA_CR_OFFSET register
+ * @{
+ */
+#define XAXICDMA_CR_RESET_MASK		0x00000004 /**< Reset DMA engine */
+#define XAXICDMA_CR_SGMODE_MASK		0x00000008 /**< Scatter gather mode */
+#define XAXICDMA_CR_KHOLE_RD_MASK	0x00000010 /**< Keyhole Read */
+#define XAXICDMA_CR_KHOLE_WR_MASK	0x00000020 /**< Keyhole Write */
+/*@}*/
+
+/** @name Bitmasks of XAXICDMA_SR_OFFSET register
+ * This register reports status of a DMA channel, including
+ * idle state, errors, and interrupts
+ * @{
+ */
+#define XAXICDMA_SR_IDLE_MASK         0x00000002  /**< DMA channel idle */
+#define XAXICDMA_SR_SGINCLD_MASK      0x00000008  /**< Hybrid build */
+#define XAXICDMA_SR_ERR_INTERNAL_MASK 0x00000010  /**< Datamover internal err */
+#define XAXICDMA_BTT_OFFSET       0x00000028  /**< Bytes to transfer */
 /*@}*/
 
 /** @name Bitmasks of XAXICDMA_CR_OFFSET register
@@ -116,6 +143,13 @@ extern "C" {
 #define XAXICDMA_SR_ERR_ALL_MASK      0x00000770  /**< All errors */
 /*@}*/
 
+/** @name Bitmask for descriptor
+ * @{
+ */
+#define XAXICDMA_DESC_LSB_MASK	(0xFFFFFFC0U)	/**< LSB Address mask */
+/*@}*/
+
+
 /** @name Bitmask for interrupts
  * These masks are shared by XAXICDMA_CR_OFFSET register and
  * XAXICDMA_SR_OFFSET register
@@ -156,19 +190,24 @@ extern "C" {
  *  @{
  */
 #define XAXICDMA_BD_NDESC_OFFSET     0x00 /**< Next descriptor pointer */
+#define XAXICDMA_BD_NDESC_MSB_OFFSET     0x04 /**< Next descriptor pointer */
 #define XAXICDMA_BD_BUFSRC_OFFSET    0x08 /**< Buffer source address */
+#define XAXICDMA_BD_BUFSRC_MSB_OFFSET    0x0C /**< Buffer source address */
 #define XAXICDMA_BD_BUFDST_OFFSET    0x10 /**< Buffer destination address */
+#define XAXICDMA_BD_BUFDST_MSB_OFFSET    0x14 /**< Buffer destination address */
 #define XAXICDMA_BD_CTRL_LEN_OFFSET  0x18 /**< Control/buffer length */
 #define XAXICDMA_BD_STS_OFFSET       0x1C /**< Status */
 #define XAXICDMA_BD_PHYS_ADDR_OFFSET 0x20 /**< Physical address of the BD */
-#define XAXICDMA_BD_ISLITE_OFFSET    0x24 /**< Lite mode hardware build? */
-#define XAXICDMA_BD_HASDRE_OFFSET    0x28 /**< Support unaligned transfers? */
-#define XAXICDMA_BD_WORDLEN_OFFSET   0x2C /**< Word length in bytes */
-#define XAXICDMA_BD_MAX_LEN_OFFSET   0x30 /**< Word length in bytes */
+#define XAXICDMA_BD_PHYS_ADDR_MSB_OFFSET 0x24 /**< Physical address of the BD */
+#define XAXICDMA_BD_ISLITE_OFFSET    0x28 /**< Lite mode hardware build? */
+#define XAXICDMA_BD_HASDRE_OFFSET    0x2C /**< Support unaligned transfers? */
+#define XAXICDMA_BD_WORDLEN_OFFSET   0x30 /**< Word length in bytes */
+#define XAXICDMA_BD_MAX_LEN_OFFSET   0x34 /**< Word length in bytes */
+#define XAXICDMA_BD_ADDRLEN_OFFSET   0x38 /**< Word length in bytes */
 
 #define XAXICDMA_BD_START_CLEAR    8   /**< Offset to start clear */
 #define XAXICDMA_BD_TO_CLEAR       24  /**< BD specific bytes to be cleared */
-#define XAXICDMA_BD_NUM_WORDS      16  /**< Total number of words for one BD*/
+#define XAXICDMA_BD_NUM_WORDS      16U  /**< Total number of words for one BD*/
 #define XAXICDMA_BD_HW_NUM_BYTES   32  /**< Number of bytes hw used */
 /*@}*/
 
@@ -213,7 +252,7 @@ extern "C" {
 *
 ******************************************************************************/
 #define XAxiCdma_ReadReg(BaseAddress, RegOffset)             \
-    XAxiCdma_In32((BaseAddress) + (RegOffset))
+    XAxiCdma_In32((BaseAddress) + (u32)(RegOffset))
 
 /*****************************************************************************/
 /**
@@ -232,7 +271,7 @@ extern "C" {
 *
 ******************************************************************************/
 #define XAxiCdma_WriteReg(BaseAddress, RegOffset, Data)          \
-    XAxiCdma_Out32((BaseAddress) + (RegOffset), (Data))
+    XAxiCdma_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
 
 #ifdef __cplusplus
 }