From 1f3de84cd29d047a8e37aa8c21cb644c4f575817 Mon Sep 17 00:00:00 2001 From: Kinjal Pravinbhai Patel Date: Mon, 27 Jul 2015 18:56:16 +0530 Subject: [PATCH] bsp: a53: added memory attribute definition in xil_mmu.h This patch adds various memory attribute definition which can be used along with xil_settlbattributes API to mark certain memory region with required attributes such as cacheable or non-cacheable, inner/outer/non shareable or executable or not etc. Signed-off-by: Kinjal Pravinbhai Patel Acked-by: Anirudha Sarangi --- .../standalone/src/cortexa53/64bit/xil_mmu.h | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/lib/bsp/standalone/src/cortexa53/64bit/xil_mmu.h b/lib/bsp/standalone/src/cortexa53/64bit/xil_mmu.h index d74b3d93..62de3bf3 100644 --- a/lib/bsp/standalone/src/cortexa53/64bit/xil_mmu.h +++ b/lib/bsp/standalone/src/cortexa53/64bit/xil_mmu.h @@ -66,6 +66,32 @@ extern "C" { /************************** Constant Definitions *****************************/ +/* Memory type */ +#define NORM_NONCACHE 0x401UL /* Normal Non-cacheable*/ +#define STRONG_ORDERED 0x409UL /* Strongly ordered (Device-nGnRnE)*/ +#define DEVICE_MEMORY 0x40DUL /* Device memory (Device-nGnRE)*/ +#define RESERVED 0x0UL /* reserved memory*/ + +/* Normal write-through cacheable inner shareable*/ +#define NORM_WT_CACHE 0x711UL + +/* Normal write back cacheable inner-shareable */ +#define NORM_WB_CACHE 0x705UL + +/* + * shareability attribute only applicable to + * normal cacheable memory + */ +#define INNER_SHAREABLE (0x3 << 8)UL +#define OUTER_SHAREABLE (0x2 << 8)UL +#define NON_SHAREABLE (~(0x3 << 8))UL + +/* Execution type */ +#define EXECUTE_NEVER ((0x1 << 53) | (0x1 << 54))UL + +/* Security type */ +#define NON_SECURE (0x1 << 5)UL + /************************** Variable Definitions *****************************/ /************************** Function Prototypes ******************************/