From 1f48a8019c9e01209403f28e796ab8acd4bc99c2 Mon Sep 17 00:00:00 2001 From: Kedareswara rao Appana Date: Fri, 21 Aug 2015 11:10:56 +0530 Subject: [PATCH] axidma: Handle cache flush/invalidate api's properly for a53 In a53 processor the Cache flush api does both fulsh and invalidate of the memory once the dma transfer is done before checking the data we shouldn't invalidate the memory unlike the a9/microblaze case. This patch updates the axidma examples for the same. Signed-off-by: Kedareswara rao Appana Acked-by: Kinjal Pravinbhai Patel --- .../drivers/axidma/examples/xaxidma_example_simple_intr.c | 5 +++++ .../drivers/axidma/examples/xaxidma_example_simple_poll.c | 3 +++ 2 files changed, 8 insertions(+) diff --git a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_intr.c b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_intr.c index 5a42ca63..add3a9a4 100644 --- a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_intr.c +++ b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_intr.c @@ -326,6 +326,9 @@ int main(void) * is enabled */ Xil_DCacheFlushRange((u32)TxBufferPtr, MAX_PKT_LEN); +#ifdef __aarch64__ + Xil_DCacheFlushRange((UINTPTR)RxBufferPtr, MAX_PKT_LEN); +#endif /* Send a packet */ for(Index = 0; Index < Tries; Index ++) { @@ -438,7 +441,9 @@ static int CheckData(int Length, u8 StartValue) /* Invalidate the DestBuffer before receiving the data, in case the * Data Cache is enabled */ +#ifndef __aarch64__ Xil_DCacheInvalidateRange((u32)RxPacket, Length); +#endif for(Index = 0; Index < Length; Index++) { if (RxPacket[Index] != Value) { diff --git a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c index 06eb019b..2f56ab55 100644 --- a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c +++ b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c @@ -277,6 +277,9 @@ int XAxiDma_SimplePollExample(u16 DeviceId) * is enabled */ Xil_DCacheFlushRange((UINTPTR)TxBufferPtr, MAX_PKT_LEN); +#ifdef __aarch64__ + Xil_DCacheFlushRange((UINTPTR)RxBufferPtr, MAX_PKT_LEN); +#endif for(Index = 0; Index < Tries; Index ++) {