From 21b87a69bf2c9ae92c9478ec00ccd290184c96b7 Mon Sep 17 00:00:00 2001 From: Harini Katakam Date: Wed, 18 Mar 2015 19:03:04 +0530 Subject: [PATCH] emacps: Add missing cache flush Add cache flush after TX BD terminate entry for generic tx queue so that it will be reflected. Signed-off-by: Harini Katakam --- .../drivers/emacps/examples/xemacps_example_intr_dma.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/XilinxProcessorIPLib/drivers/emacps/examples/xemacps_example_intr_dma.c b/XilinxProcessorIPLib/drivers/emacps/examples/xemacps_example_intr_dma.c index 64efb0af..141ea74a 100644 --- a/XilinxProcessorIPLib/drivers/emacps/examples/xemacps_example_intr_dma.c +++ b/XilinxProcessorIPLib/drivers/emacps/examples/xemacps_example_intr_dma.c @@ -104,7 +104,8 @@ * 2.1 srt 07/11/14 Implemented 64-bit changes and modified as per * Zynq Ultrascale Mp GEM specification * 3.0 kpc 01/23/14 Removed PEEP board related code -* 3.0 hk 02/20/15 Added support for jumbo frames. +* 3.0 hk 03/18/15 Added support for jumbo frames. +* Add cache flush after BD terminate entries. * * * @@ -488,6 +489,7 @@ LONG EmacPsDmaIntrExample(XScuGic * IntcInstancePtr, XEMACPS_TXBUF_WRAP_MASK)); XEmacPs_Out32((Config->BaseAddress + XEMACPS_TXQBASE_OFFSET), (UINTPTR)&BdTxTerminate); + Xil_DCacheFlushRange((UINTPTR)(&BdTxTerminate), 64); } /*