diff --git a/lib/bsp/standalone/src/changelog.txt b/lib/bsp/standalone/src/changelog.txt index c635baf5..7739b97e 100755 --- a/lib/bsp/standalone/src/changelog.txt +++ b/lib/bsp/standalone/src/changelog.txt @@ -202,4 +202,8 @@ * Modified profile_mcount_mb.S to fix CR#808412. * 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in * cortexa9/iccarm to fix CR#816701 + * 4.2 pkp 09/02/14 modified translation table entries in cortexa9/gcc/translation_table.s, + * armcc/translation_table.s and iccarm/translation_table.s + * to properly defined reserved entries according to address map for + * fixing CR#820146 ******************************************************************************************/ diff --git a/lib/bsp/standalone/src/cortexa9/armcc/translation_table.s b/lib/bsp/standalone/src/cortexa9/armcc/translation_table.s index 6fc849a2..a96630f5 100755 --- a/lib/bsp/standalone/src/cortexa9/armcc/translation_table.s +++ b/lib/bsp/standalone/src/cortexa9/armcc/translation_table.s @@ -45,6 +45,7 @@ ; 1.00a ecm 10/20/09 Initial version ; 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device ; instead of strongly-ordered. +; 4.2 pkp 09/02/14 modified translation table entries according to address map ; ; ; @note @@ -77,7 +78,7 @@ count SETA count+1 ; 0x40000000 - 0x7fffffff (GpAxi0) count SETA 0 WHILE count<0x400 - DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 + DCD sect + 0xc02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 sect SETA sect+0x100000 count SETA count+1 WEND @@ -85,7 +86,7 @@ count SETA count+1 ; 0x80000000 - 0xbfffffff (GpAxi1) count SETA 0 WHILE count<0x400 - DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 + DCD sect + 0xc02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1w sect SETA sect+0x100000 count SETA count+1 WEND @@ -98,44 +99,96 @@ sect SETA sect+0x100000 count SETA count+1 WEND -; 0xe0000000 - 0xefffffff (IOP dev) +; 0xe0000000 - 0xe02fffff (IOP dev) count SETA 0 - WHILE count<0x100 + WHILE count<0x3 DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 sect SETA sect+0x100000 count SETA count+1 WEND -; 0xf0000000 - 0xf7ffffff (reserved) +; 0xe0300000 - 0xe0ffffff (undef/reserved) count SETA 0 - WHILE count<0x80 + WHILE count<0xD DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 sect SETA sect+0x100000 count SETA count+1 WEND -; 0xf8000000 - 0xf9ffffff (APB device regs) +; 0xe1000000 - 0xe1ffffff (NAND) count SETA 0 - WHILE count<0x20 - DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 + WHILE count<0x10 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 sect SETA sect+0x100000 count SETA count+1 WEND -; 0xfa000000 - 0xfbffffff (reserved) +; 0xe2000000 - 0xe3ffffff (NOR) count SETA 0 WHILE count<0x20 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + WEND + + ; 0xe4000000 - 0xe5ffffff (SRAM) + count SETA 0 + WHILE count<0x20 + DCD sect + 0xc0e ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 + sect SETA sect+0x100000 + count SETA count+1 + WEND + +; 0xe6000000 - 0xf7ffffff (reserved) +count SETA 0 + WHILE count<0x120 DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 sect SETA sect+0x100000 count SETA count+1 WEND -; 0xfc000000 - 0xfffffff (OCM/QSPI) +; 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and +; 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of +; 1MB, it is not possible to define separate regions for them + +; 0xf8000000 - 0xf8ffffff (APB device regs) count SETA 0 - WHILE count<0x40 - DCD sect + 0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 + WHILE count<0x10 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 sect SETA sect+0x100000 count SETA count+1 WEND +; 0xf9000000 - 0xfbffffff (reserved) +count SETA 0 + WHILE count<0x30 + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + WEND + +; 0xfc000000 - 0xfdffffff (QSPI) + count SETA 0 + WHILE count<0x20 + DCD sect + 0xc0a ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 + sect SETA sect+0x100000 + count SETA count+1 + WEND + +; 0xfe000000 - 0xffefffff (reserved) +count SETA 0 + WHILE count<0x1F + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + WEND + +; 0xfff00000 to 0xfffb0000 is reserved but due to granual size of +; 1MB, it is not possible to define separate region for it + +; 0xfff00000 to 0xfffb0000 (OCM) +count SETA 0 +DCD sect + 0x4c0e ; S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 +sect SETA sect+0x100000 + END diff --git a/lib/bsp/standalone/src/cortexa9/gcc/translation_table.s b/lib/bsp/standalone/src/cortexa9/gcc/translation_table.s index 07cd4245..69061f00 100755 --- a/lib/bsp/standalone/src/cortexa9/gcc/translation_table.s +++ b/lib/bsp/standalone/src/cortexa9/gcc/translation_table.s @@ -46,6 +46,11 @@ * 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device * instead of strongly-ordered. * 3.07a asa 07/17/2012 Changed the property of the ".mmu_tbl" section. +* 4.2 pkp 09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved +* and 0xe0000000 - 0xe1ffffff is broken down into +* 0xe0000000 - 0xe02fffff (memory mapped devides) +* 0xe0300000 - 0xe0ffffff (reserved) and +* 0xe1000000 - 0xe1ffffff (NAND) * * * @note @@ -86,12 +91,23 @@ MMUTable: .set SECT, SECT+0x100000 .endr -.rept 0x0020 /* 0xe0000000 - 0xe1ffffff (Memory mapped devices) +.rept 0x003 /* 0xe0000000 - 0xe02fffff (Memory mapped devices) * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */ .word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ .set SECT, SECT+0x100000 .endr +.rept 0x0D /* 0xe0300000 - 0xe0ffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0010 /* 0xe1000000 - 0xe1ffffff (NAND) */ +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + .rept 0x0020 /* 0xe2000000 - 0xe3ffffff (NOR) */ .word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ .set SECT, SECT+0x100000 @@ -108,7 +124,12 @@ MMUTable: .set SECT, SECT+0x100000 .endr +/* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and + 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of + 1MB, it is not possible to define separate regions for them */ + .rept 0x0010 /* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */ + .word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ .set SECT, SECT+0x100000 .endr @@ -119,13 +140,23 @@ MMUTable: .set SECT, SECT+0x100000 .endr -.rept 0x003f /* 0xfc000000 - 0xffefffff (Linear QSPI - XIP) */ +.rept 0x0020 /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */ .word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */ .set SECT, SECT+0x100000 .endr - /* 256K OCM when mapped to high address space - * inner-cacheable */ +.rept 0x001F /* 0xfe000000 - 0xffefffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +/* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of + 1MB, it is not possible to define separate region for it + +/* 0xfff00000 - 0xffffffff + 256K OCM when mapped to high address space + inner-cacheable */ .word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */ .set SECT, SECT+0x100000 diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/translation_table.s b/lib/bsp/standalone/src/cortexa9/iccarm/translation_table.s index f100eb8d..8c7da500 100755 --- a/lib/bsp/standalone/src/cortexa9/iccarm/translation_table.s +++ b/lib/bsp/standalone/src/cortexa9/iccarm/translation_table.s @@ -42,8 +42,9 @@ ; Ver Who Date Changes ; ----- ---- -------- --------------------------------------------------- ; 1.00a ecm 10/20/09 Initial version -; 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device +; 3.07a sgd 07/05/12 Configuring device address spaces as shareable device ; instead of strongly-ordered. +; 4.2 pkp 09/02/14 modified translation table entries according to address map ; ; ; @note @@ -75,7 +76,7 @@ count SETA count+1 ; 0x40000000 - 0x7fffffff (GpAxi0) count SETA 0 REPT 0x400 - DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 + DCD sect + 0xc02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 sect SETA sect+0x100000 count SETA count+1 ENDR @@ -83,7 +84,7 @@ count SETA count+1 ; 0x80000000 - 0xbfffffff (GpAxi1) count SETA 0 REPT 0x400 - DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 + DCD sect + 0xc02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 sect SETA sect+0x100000 count SETA count+1 ENDR @@ -96,44 +97,96 @@ sect SETA sect+0x100000 count SETA count+1 ENDR -; 0xe0000000 - 0xefffffff (IOP dev) +; 0xe0000000 - 0xe02fffff (IOP dev) count SETA 0 - REPT 0x100 + REPT 0x3 DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 sect SETA sect+0x100000 count SETA count+1 ENDR -; 0xf0000000 - 0xf7ffffff (reserved) + ; 0xe0300000 - 0xe0ffffff (undef/reserved) + count SETA 0 + REPT 0xD + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 + sect SETA sect+0x100000 + count SETA count+1 + ENDR + +; 0xe1000000 - 0xe1ffffff (NAND) count SETA 0 - REPT 0x80 - DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 + REPT 0x10 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 sect SETA sect+0x100000 count SETA count+1 ENDR -; 0xf8000000 - 0xf9ffffff (APB device regs) +; 0xe2000000 - 0xe3ffffff (NOR) count SETA 0 REPT 0x20 - DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 sect SETA sect+0x100000 count SETA count+1 ENDR -; 0xfa000000 - 0xfbffffff (reserved) +; 0xe4000000 - 0xe5ffffff (SRAM) count SETA 0 REPT 0x20 - DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 + DCD sect + 0xc0e ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 sect SETA sect+0x100000 count SETA count+1 ENDR -; 0xfc000000 - 0xfffffff (OCM/QSPI) +; 0xe6000000 - 0xf7ffffff (reserved) count SETA 0 - REPT 0x40 - DCD sect + 0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 + REPT 0x0120 + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 sect SETA sect+0x100000 count SETA count+1 ENDR +; 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and +; 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of +; 1MB, it is not possible to define separate regions for them + +; 0xf8000000 - 0xf8ffffff (APB device regs) +count SETA 0 + REPT 0x10 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0xf9000000 - 0xfbffffff (reserved) +count SETA 0 + REPT 0x30 + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0xfc000000 - 0xfdffffff (QSPI) +count SETA 0 + REPT 0x20 + DCD sect + 0xc0a ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0xfe000000 - 0xffefffff (reserved) +count SETA 0 + REPT 0x1F + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0xfff00000 to 0xfffb0000 is reserved but due to granual size of +; 1MB, it is not possible to define separate region for it + +; 0xfff00000 to 0xfffb0000 (OCM) + count SETA 0 + DCD sect + 0x4c0e ; S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 + sect SETA sect+0x100000 + END