diff --git a/XilinxProcessorIPLib/drivers/srio/data/srio.mdd b/XilinxProcessorIPLib/drivers/srio/data/srio.mdd
new file mode 100755
index 00000000..13b796fe
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/srio/data/srio.mdd
@@ -0,0 +1,55 @@
+##############################################################################
+#
+# (c) Copyright 2014 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information of Xilinx, Inc.
+# and is protected under U.S. and international copyright and other
+# intellectual property laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any rights to the
+# materials distributed herewith. Except as otherwise provided in a valid
+# license issued to you by Xilinx, and to the maximum extent permitted by
+# applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+# FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+# IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+# MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+# and (2) Xilinx shall not be liable (whether in contract or tort, including
+# negligence, or under any other theory of liability) for any loss or damage
+# of any kind or nature related to, arising under or in connection with these
+# materials, including for any direct, or any indirect, special, incidental,
+# or consequential loss or damage (including loss of data, profits, goodwill,
+# or any type of loss or damage suffered as a result of any action brought by
+# a third party) even if such damage or loss was reasonably foreseeable or
+# Xilinx had been advised of the possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-safe, or for use in
+# any application requiring fail-safe performance, such as life-support or
+# safety devices or systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any other applications
+# that could lead to death, personal injury, or severe property or
+# environmental damage (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and liability of any use of
+# Xilinx products in Critical Applications, subject only to applicable laws
+# and regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+# AT ALL TIMES.
+#
+# MODIFICATION HISTORY:
+# Ver Who Date Changes
+# -------- ------ -------- --------------------------------------------------
+# 1.0 adk 16/04/14 Initial release
+##############################################################################
+OPTION psf_version = 2.1;
+
+BEGIN driver srio
+
+ OPTION supported_peripherals = (srio_gen2);
+ OPTION driver_state = ACTIVE;
+ OPTION copyfiles = all;
+ OPTION VERSION = 1.0;
+ OPTION NAME = srio;
+
+END driver
diff --git a/XilinxProcessorIPLib/drivers/srio/data/srio.tcl b/XilinxProcessorIPLib/drivers/srio/data/srio.tcl
new file mode 100755
index 00000000..0edee13e
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/srio/data/srio.tcl
@@ -0,0 +1,268 @@
+##############################################################################
+#
+# (c) Copyright 2014 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information of Xilinx, Inc.
+# and is protected under U.S. and international copyright and other
+# intellectual property laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any rights to the
+# materials distributed herewith. Except as otherwise provided in a valid
+# license issued to you by Xilinx, and to the maximum extent permitted by
+# applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+# FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+# IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+# MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+# and (2) Xilinx shall not be liable (whether in contract or tort, including
+# negligence, or under any other theory of liability) for any loss or damage
+# of any kind or nature related to, arising under or in connection with these
+# materials, including for any direct, or any indirect, special, incidental,
+# or consequential loss or damage (including loss of data, profits, goodwill,
+# or any type of loss or damage suffered as a result of any action brought by
+# a third party) even if such damage or loss was reasonably foreseeable or
+# Xilinx had been advised of the possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-safe, or for use in
+# any application requiring fail-safe performance, such as life-support or
+# safety devices or systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any other applications
+# that could lead to death, personal injury, or severe property or
+# environmental damage (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and liability of any use of
+# Xilinx products in Critical Applications, subject only to applicable laws
+# and regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+# AT ALL TIMES.
+#
+##############################################################################
+##############################################################################
+#
+# Modification History
+#
+# Ver Who Date Changes
+# ----- ---- -------- -----------------------------------------------
+# 1.0 adk 16/04/14 Initial release
+#
+##############################################################################
+
+#uses "xillib.tcl"
+
+set periph_config_params_srio 0
+set periph_ninstances_srio 0
+
+proc init_periph_config_struct_srio { deviceid } {
+ global periph_config_params_srio
+ set periph_config_params_srio($deviceid) [list]
+}
+
+proc add_field_to_periph_config_struct_srio { deviceid fieldval } {
+ global periph_config_params_srio
+ lappend periph_config_params_srio($deviceid) $fieldval
+}
+
+proc get_periph_config_struct_fields_srio { deviceid } {
+ global periph_config_params_srio
+ return $periph_config_params_srio($deviceid)
+}
+
+proc xdefine_srio_include_file {drv_handle file_name drv_string} {
+ global periph_ninstances
+
+ # Open include file
+ set file_handle [xopen_include_file $file_name]
+
+ # Get all peripherals connected to this driver
+ set periphs [xget_sw_iplist_for_driver $drv_handle]
+
+ # Handle NUM_INSTANCES
+ set periph_ninstances 0
+ puts $file_handle "/* Definitions for driver [string toupper [get_property NAME $drv_handle]] */"
+ foreach periph $periphs {
+ init_periph_config_struct_srio $periph_ninstances
+ incr periph_ninstances 1
+ }
+ puts $file_handle "\#define [xget_dname $drv_string NUM_INSTANCES] $periph_ninstances"
+
+
+ # Now print all useful parameters for all peripherals
+ set device_id 0
+ foreach periph $periphs {
+ puts $file_handle ""
+
+ xdefine_srio_params_instance $file_handle $periph $device_id
+
+ xdefine_srio_params_canonical $file_handle $periph $device_id
+ incr device_id
+ puts $file_handle "\n"
+ }
+ puts $file_handle "\n/******************************************************************/\n"
+ close $file_handle
+}
+
+proc xdefine_srio_params_instance {file_handle periph device_id} {
+ set sriois_memory [get_property CONFIG.C_PE_MEMORY $periph]
+ if {$sriois_memory == 0} {
+ set sriois_memory 0
+ }
+
+ set sriois_processor [get_property CONFIG.C_PE_PROC $periph]
+ if {$sriois_processor == 0} {
+ set sriois_processor 0
+ } else {
+ set sriois_processor 2
+ }
+
+ set sriois_bridge [get_property CONFIG.C_PE_BRIDGE $periph]
+ if {$sriois_bridge == 0} {
+ set sriois_bridge 0
+ } else {
+ set sriois_bridge 3
+ }
+
+ puts $file_handle "/* Definitions for peripheral [string toupper [get_property NAME $periph]] */"
+
+ puts $file_handle "\#define [xget_dname $periph "DEVICE_ID"] $device_id"
+ set value [get_property CONFIG.C_BASEADDR $periph]
+ if {[llength $value] == 0} {
+ set value 0
+ }
+ puts $file_handle "\#define [xget_dname $periph "C_BASEADDR"] $value"
+
+ set value [get_property CONFIG.C_HIGHADDR $periph]
+ if {[llength $value] == 0} {
+ set value 0
+ }
+ puts $file_handle "\#define [xget_dname $periph "C_HIGHADDR"] $value"
+
+ set value [get_property CONFIG.C_DEVICEID_WIDTH $periph]
+ if {[llength $value] == 0} {
+ set value 0
+ }
+ puts $file_handle "\#define [xget_dname $periph "C_DEVICEID_WIDTH"] $value"
+
+ set value [get_property CONFIG.C_IS_HOST $periph]
+ if {[llength $value] == 0} {
+ set value 0
+ }
+ puts $file_handle "\#define [xget_dname $periph "C_IS_HOST"] $value"
+
+ set value [get_property CONFIG.C_TX_DEPTH $periph]
+ if {[llength $value] == 0} {
+ set value 0
+ }
+ puts $file_handle "\#define [xget_dname $periph "C_TX_DEPTH"] $value"
+
+ set value [get_property CONFIG.C_RX_DEPTH $periph]
+ if {[llength $value] == 0} {
+ set value 0
+ }
+ puts $file_handle "\#define [xget_dname $periph "C_RX_DEPTH"] $value"
+
+ set value [get_property CONFIG.C_DISCOVERED $periph]
+ if {[llength $value] == 0} {
+ set value 0
+ }
+ puts $file_handle "\#define [xget_dname $periph "C_DISCOVERED"] $value"
+
+ puts $file_handle "\#define [xget_dname $periph "PE_MEMORY"] $sriois_memory"
+ puts $file_handle "\#define [xget_dname $periph "PE_PROC"] $sriois_processor"
+ puts $file_handle "\#define [xget_dname $periph "PE_BRIDGE"] $sriois_bridge"
+
+}
+
+proc xdefine_srio_params_canonical {file_handle periph device_id} {
+
+ set sriois_memory [get_property CONFIG.C_PE_MEMORY $periph]
+ if {$sriois_memory == 0} {
+ set sriois_memory 0
+ }
+
+ set sriois_processor [get_property CONFIG.C_PE_PROC $periph]
+ if {$sriois_processor == 0} {
+ set sriois_processor 0
+ } else {
+ set sriois_processor 2
+ }
+
+ set sriois_bridge [get_property CONFIG.C_PE_BRIDGE $periph]
+ if {$sriois_bridge == 0} {
+ set sriois_bridge 0
+ } else {
+ set sriois_bridge 3
+ }
+
+ puts $file_handle "\n/* Canonical definitions for peripheral [string toupper [get_property NAME $periph]] */"
+
+ set canonical_tag [string toupper [format "XPAR_SRIO_%d" $device_id]]
+
+ # Handle device ID
+ set canonical_name [format "%s_DEVICE_ID" $canonical_tag]
+ puts $file_handle "\#define $canonical_name $device_id"
+ add_field_to_periph_config_struct_srio $device_id $canonical_name
+
+ set canonical_name [format "%s_BASEADDR" $canonical_tag]
+ set value [get_property CONFIG.C_BASEADDR $periph]
+ if {[llength $value] == 0} {
+ set value 0
+ }
+ puts $file_handle "\#define $canonical_name $value"
+ add_field_to_periph_config_struct_srio $device_id $canonical_name
+
+ set canonical_name [format "%s_PE_MEMORY" $canonical_tag]
+ puts $file_handle "\#define $canonical_name $sriois_memory"
+ add_field_to_periph_config_struct_srio $device_id $canonical_name
+
+ set canonical_name [format "%s_PE_PROC" $canonical_tag]
+ puts $file_handle "\#define $canonical_name $sriois_processor"
+ add_field_to_periph_config_struct_srio $device_id $canonical_name
+
+ set canonical_name [format "%s_PE_BRIDGE" $canonical_tag]
+ puts $file_handle "\#define $canonical_name $sriois_bridge"
+ add_field_to_periph_config_struct_srio $device_id $canonical_name
+
+}
+
+proc xdefine_srio_config_file {file_name drv_string} {
+
+ global periph_ninstances
+
+ set filename [file join "src" $file_name]
+ file delete $filename
+ set config_file [open $filename w]
+ xprint_generated_header $config_file "Driver configuration"
+ puts $config_file "\#include \"xparameters.h\""
+ puts $config_file "\#include \"[string tolower $drv_string].h\""
+ puts $config_file "\n/*"
+ puts $config_file "* The configuration table for devices"
+ puts $config_file "*/\n"
+ puts $config_file [format "%s_Config %s_ConfigTable\[\] =" $drv_string $drv_string]
+ puts $config_file "\{"
+
+ set start_comma ""
+ for {set i 0} {$i < $periph_ninstances} {incr i} {
+
+ puts $config_file [format "%s\t\{" $start_comma]
+ set comma ""
+ foreach field [get_periph_config_struct_fields_srio $i] {
+ puts -nonewline $config_file [format "%s\t\t%s" $comma $field]
+ set comma ",\n"
+ }
+
+ puts -nonewline $config_file "\n\t\}"
+ set start_comma ",\n"
+ }
+ puts $config_file "\n\};\n"
+ close $config_file
+}
+
+proc generate {drv_handle} {
+ xdefine_srio_include_file $drv_handle "xparameters.h" "XSrio"
+ xdefine_srio_config_file "xsrio_g.c" "XSrio"
+}
+
+
+
+
diff --git a/XilinxProcessorIPLib/drivers/srio/examples/index.html b/XilinxProcessorIPLib/drivers/srio/examples/index.html
new file mode 100755
index 00000000..8eb6ec88
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/srio/examples/index.html
@@ -0,0 +1,17 @@
+
+
+
+
+
+Driver example applications
+
+
+
+
+
+
diff --git a/XilinxProcessorIPLib/drivers/srio/examples/xsrio_dma_loopback_example.c b/XilinxProcessorIPLib/drivers/srio/examples/xsrio_dma_loopback_example.c
new file mode 100755
index 00000000..53b4cc80
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/srio/examples/xsrio_dma_loopback_example.c
@@ -0,0 +1,315 @@
+/******************************************************************************
+*
+* (c) Copyright 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xsrio_dma_loopback_example.c
+ *
+ * This file demonstrates how to use xsrio driver on the Xilinx SRIO Gen2 Core.
+ * The SRIO Gen2 comprised of phy, logical and transport and buffer layers.
+ * Using this IP We can generate both messaging and read/write semantics.
+ *
+ * This example demonstartes how to generate SWRITE(Streaming Write)
+ * transactions on the core.
+ *
+ * Inorder to test this example external loopback is required at the boardlevel
+ * Between the SRIO Tx and Rx pins.
+ *
+ * H/W Requirments:
+ * Inorder to test this example at the h/w level the the SRIO Initiator Request
+ * is connected to the AXI DMA MM2S Channel and SRIO Target Request is connected
+ * to the AXI DMA S2MM Channel.
+ *
+ * S/W Flow:
+ * 1) The system consists of two different memories.Processor runs this example
+ * Code in one memory and the SRIO packet is formed in another memory.
+ * 2) The SRIO Packet is framed in the Memory
+ * 3) Configure the AXI DMA MM2S source address and S2MM for Destiantion address
+ * and specify the byte count for both the channels and then start the dma.
+ * 4) Compare the Data.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.0 adk 16/04/14 Initial release
+ *
+ *
+ *
+ * ***************************************************************************
+ */
+
+/***************************** Include Files *********************************/
+#include "xparameters.h"
+#include "xil_printf.h"
+#include "xil_types.h"
+#include "xstatus.h"
+#include "xsrio.h"
+#include "xbram.h"
+#include "xaxidma.h"
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define SRIO_DEVICE_ID XPAR_SRIO_0_DEVICE_ID
+#define MEM_ADDR XPAR_AXI_BRAM_CTRL_1_S_AXI_BASEADDR
+#define DMA_DEV_ID XPAR_AXIDMA_0_DEVICE_ID
+#define DATA_SIZE 256
+
+/******************** Variable Definitions **********************************/
+XSrio Srio; /* Instance of the XSrio */
+XAxiDma AxiDma; /* Instance of the XAxiDma */
+
+/******************** Function Prototypes ************************************/
+int XSrioDmaLoopbackExample(XSrio *InstancePtr, u16 DeviceId);
+
+/*****************************************************************************/
+/**
+*
+* Main function
+*
+* This function is the main entry of the SRIO DMA Loopback test.
+*
+* @param None
+*
+* @return - XST_SUCCESS if tests pass
+* - XST_FAILURE if fails.
+*
+* @note None
+*
+******************************************************************************/
+int main()
+{
+ int Status;
+
+ xil_printf("Entering main\n\r");
+
+ Status = XSrioDmaLoopbackExample(&Srio, SRIO_DEVICE_ID);
+ if (Status != XST_SUCCESS) {
+ xil_printf("SRIO DMA Loopback Test Failed\n\r");
+ xil_printf("--- Exiting main() ---\n\r");
+ return XST_FAILURE;
+ }
+
+ xil_printf("SRIO DMA Loopback Test passed\n\r");
+ xil_printf("--- Exiting main() ---\n\r");
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* XSrioDmaLoopbackExample This function does a minimal test on the XSrio device
+* and driver as a design example. The purpose of this function is to illustrate
+* how to use the XSrio Component.
+*
+* This function does the following:
+* - Initialize the SRIO device
+* - Initialize the DMA engine
+* - Clearing the Memory
+* - Framing the SRIO Packet in the Memory
+* - Configuring the SRIO
+* - Configuring the DMA
+* - Verifying the Data
+*
+* @param InstancePtr is a pointer to the instance of the
+* XSrio driver.
+* @param DeviceId is Device ID of the SRIO Gen2 Device.
+*
+* @return -XST_SUCCESS to indicate success
+* -XST_FAILURE to indicate failure
+*
+******************************************************************************/
+int XSrioDmaLoopbackExample(XSrio *InstancePtr, u16 DeviceId)
+{
+ XSrio_Config *SrioConfig;
+ XAxiDma_Config *DmaConfig;
+ int Status = XST_SUCCESS;
+ int Count = 0;
+
+ /* Initialize the SRIO Device Configuration Interface driver */
+ SrioConfig = XSrio_LookupConfig(DeviceId);
+ if (!SrioConfig) {
+ xil_printf("No SRIO config found for %d\r\n", DeviceId);
+ return XST_FAILURE;
+ }
+
+ /**< This is where the virtual address would be used, this example
+ * uses physical address.
+ */
+ Status = XSrio_CfgInitialize(InstancePtr, SrioConfig,
+ SrioConfig->BaseAddress);
+ if (Status != XST_SUCCESS) {
+ xil_printf("Initialization failed for SRIO\n\r");
+ return Status;
+ }
+
+ /* Check for PE Configuration */
+ Status = XSrio_GetPEType(InstancePtr);
+ if (Status != XSRIO_IS_MEMORY) {
+ xil_printf("SRIO is not configured as the Memory \n\r");
+ return XST_FAILURE;
+ }
+
+ /* Clearing the Memory */
+ for(Count=0; Count<(128*1024); Count += 4) {
+ *(u32 *)(MEM_ADDR + Count) = 0;
+ }
+
+ /**< Check whether Streaming Write Operation is Supported by the
+ * Core or not Since it is a loopback Example Checking at the both
+ * Target and source Operations.
+ */
+ Status = XSrio_IsOperationSupported(InstancePtr, XSRIO_OP_MODE_SWRITE,
+ XSRIO_DIR_TX);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ Status = XSrio_IsOperationSupported(InstancePtr, XSRIO_OP_MODE_SWRITE,
+ XSRIO_DIR_RX);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ /**< Frame the SRIO Write-Stream Packet in the Memory
+ * The Packet-format used here is HELLO Packet format
+ * More details look into pg 3.1 version:73 page(HELLO PACKET FORMAT).
+ */
+ *(u32 *)(MEM_ADDR + 0x00) = 0x50000600; /**< Lower word of the
+ * HELLO Packet
+ */
+ *(u32 *)(MEM_ADDR + 0x04) = 0x08602F74; /**< Upper word of the
+ * HELLO packet
+ */
+ Count = 8;
+
+ while(Count<(DATA_SIZE * 2)) {
+ *(u32 *)(MEM_ADDR + Count) = Count;
+ Count += 4;
+ }
+
+ /* SRIO Configuration */
+ /* Set the Local Configuration Space Base Address */
+ XSrio_SetLCSBA(InstancePtr, 0xFFF);
+ /* Set the Water Mark Level to transfer priority 0 packet */
+ XSrio_SetWaterMark0(InstancePtr, 0x5);
+ /* Set the Water Mark Level to transfer priority 1 packet */
+ XSrio_SetWaterMark1(InstancePtr, 0x4);
+ /* Set the Water Mark Level to transfer priority 2 packet */
+ XSrio_SetWaterMark2(InstancePtr, 0x3);
+ /* Set the Port Response timeout value */
+ XSrio_SetPortRespTimeOutValue(InstancePtr, 0x010203);
+
+ /* DMA Configuration */
+ DmaConfig = XAxiDma_LookupConfig(DMA_DEV_ID);
+ if (!DmaConfig) {
+ xil_printf("No DMA config found for %d\r\n", DMA_DEV_ID);
+ return XST_FAILURE;
+ }
+
+ /* Initialize DMA engine */
+ Status = XAxiDma_CfgInitialize(&AxiDma, DmaConfig);
+ if (Status != XST_SUCCESS) {
+ xil_printf("Initialization failed %d\r\n", Status);
+ return XST_FAILURE;
+ }
+
+ /**< Configure the DMA Tx Side
+ * MEM_ADDR is the address where Tx packet is formed
+ */
+ XAxiDma_WriteReg(DmaConfig->BaseAddr, XAXIDMA_CR_OFFSET,
+ XAXIDMA_CR_RUNSTOP_MASK);
+ XAxiDma_IntrEnable(&AxiDma,XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
+ XAxiDma_WriteReg(DmaConfig->BaseAddr, XAXIDMA_SRCADDR_OFFSET, MEM_ADDR);
+
+ /**< Configure the DMA Rx Side
+ * MEM_ADDR+0x5000 is the address where Rx packet is formed
+ */
+ XAxiDma_WriteReg(DmaConfig->BaseAddr,
+ XAXIDMA_RX_OFFSET+XAXIDMA_CR_OFFSET, XAXIDMA_CR_RUNSTOP_MASK);
+ XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
+ XAxiDma_WriteReg(DmaConfig->BaseAddr,
+ XAXIDMA_RX_OFFSET + XAXIDMA_DESTADDR_OFFSET, MEM_ADDR+0x5000);
+
+
+ for(Count=8; CountBaseAddr, XAXIDMA_BUFFLEN_OFFSET, 256);
+ /* Wait till DMA MM2S Transfer Complete */
+ while(!(XAxiDma_ReadReg(DmaConfig->BaseAddr, XAXIDMA_SR_OFFSET)
+ & 0x1000));
+ XAxiDma_WriteReg(DmaConfig->BaseAddr,
+ XAXIDMA_RX_OFFSET+XAXIDMA_BUFFLEN_OFFSET, 256);
+ /* Wait till S2MM Transfer Complete */
+ while(!( XAxiDma_ReadReg(DmaConfig->BaseAddr,
+ XAXIDMA_RX_OFFSET+XAXIDMA_SR_OFFSET) & 0x1000));
+
+ /* Verifying the Data */
+ for(Count=8; Count
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 adk 16/04/14 Initial release
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xsrio.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Initialize the XSrio instance provided by the caller based on the
+* given Config structure.
+*
+* @param InstancePtr is the XSrio instance to operate on.
+* @param Config is the device configuration structure containing
+* information about a specific SRIO Device.
+* @param EffectiveAddress is the Physical address of the hardware in a
+* Virtual Memory operating system environment.It is the Base
+* Address in a stand alone environment.
+*
+* @return
+* - XST_SUCCESS Initialization was successful.
+*
+* @note None.
+*****************************************************************************/
+int XSrio_CfgInitialize(XSrio *InstancePtr,
+ XSrio_Config *Config, u32 EffectiveAddress)
+{
+ u32 Portwidth;
+
+ InstancePtr->IsReady = 0;
+
+ /* Setup the instance */
+ memset(InstancePtr, 0, sizeof(XSrio));
+ InstancePtr->Config.BaseAddress = EffectiveAddress;
+ InstancePtr->Config.DeviceId = Config->DeviceId;
+
+ /* Initialization is successful */
+ InstancePtr->IsReady = 1;
+
+ /* Configuration of the Device */
+ InstancePtr->Config.IsPEMemory = Config->IsPEMemory;
+ InstancePtr->Config.IsPEProcessor = Config->IsPEProcessor;
+ InstancePtr->Config.IsPEBridge = Config->IsPEBridge;
+
+ /* Port width for the Device */
+ Portwidth = XSrio_ReadReg(InstancePtr->Config.BaseAddress,
+ XSRIO_PORT_N_ERR_STS_CSR_OFFSET + XSRIO_PORT_N_CTL_CSR_OFFSET);
+ InstancePtr->PortWidth = ((Portwidth & XSRIO_PORT_N_CTL_PW_CSR_MASK) >>
+ XSRIO_PORT_N_CTL_PW_CSR_SHIFT);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* XSrio_GetPortStatus will check the status of the port and returns the status
+* of the port to the user
+*
+* @param InstancePtr is the XSrio instance to operate on.
+*
+* @return
+* - XSRIO_PORT_OK Port is initialized with no errors.
+* - XSRIO_PORT_UNINITIALIZED Port is not intilized.
+* No Serial Rapidio link is present.
+* - XSRIO_PORT_HAS_ERRORS Port is initialized but has errors.
+*
+* @note: None.
+*
+****************************************************************************/
+int XSrio_GetPortStatus(XSrio *InstancePtr)
+{
+ u32 Result;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ Result = XSrio_ReadReg(InstancePtr->Config.BaseAddress,
+ XSRIO_PORT_N_ERR_STS_CSR_OFFSET);
+ if(Result & XSRIO_PORT_N_ERR_STS_POK_CSR_MASK)
+ Result = XSRIO_PORT_OK;
+ else if(Result & XSRIO_PORT_N_ERR_STS_PUINT_CSR_MASK)
+ Result = XSRIO_PORT_UNINITIALIZED;
+ else if(Result & XSRIO_PORT_N_ERR_STS_PERR_CSR_MASK)
+ Result = XSRIO_PORT_HAS_ERRORS;
+
+ return Result;
+}
+
+/*****************************************************************************/
+/**
+* XSrio_GetPEType API will check for the Processing Element type and
+* return the type of type of Processing Element
+*
+* @param InstancePtr is the XSrio instance to operate on.
+*
+* @return
+* - XSRIO_IS_MEMORY if the core is configured as a memory
+* - XSRIO_IS_PROCESSOR if the core is configured as a processor
+* - XSRIO_IS_BRIDGE if the core is configured as a bridge.
+*
+* @note: None.
+*
+*****************************************************************************/
+int XSrio_GetPEType(XSrio *InstancePtr)
+{
+ int Result;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ Result = XSrio_ReadReg(InstancePtr->Config.BaseAddress,
+ XSRIO_PEF_CAR_OFFSET);
+ if(Result & XSRIO_PEF_MEMORY_CAR_MASK)
+ Result = XSRIO_IS_MEMORY;
+ else if(Result & XSRIO_PEF_PROCESSOR_CAR_MASK)
+ Result = XSRIO_IS_PROCESSOR;
+ else if(Result & XSRIO_PEF_BRIDGE_CAR_MASK)
+ Result = XSRIO_IS_BRIDGE;
+
+ return Result;
+}
+
+/*****************************************************************************/
+/**
+* XSrio_IsOperationSupported tells whether the operation is supported by the
+* SRIO Gen2 core or not.
+*
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Operation type is the operation type of the SRIO Packet
+* @param Direction type
+*
+* @return
+* - XST_SUCCESS if the operation is supported by the core.
+* - XST_FAILURE if the operation is not supported by the core.
+*
+* @note None.
+*
+*****************************************************************************/
+int XSrio_IsOperationSupported(XSrio *InstancePtr, u8 Operation, u8 Direction)
+{
+ u32 OperationCar;
+ u32 Status = XST_FAILURE;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ if (Direction & XSRIO_DIR_TX) {
+ OperationCar = XSrio_ReadSrcOps(InstancePtr);
+ } else {
+ OperationCar = XSrio_ReadDstOps(InstancePtr);
+ }
+
+ switch (Operation) {
+ case XSRIO_OP_MODE_NREAD:
+ if(OperationCar & XSRIO_SRCDST_OPS_READ_CAR_MASK)
+ Status = XST_SUCCESS;
+ break;
+ case XSRIO_OP_MODE_NWRITE:
+ if(OperationCar & XSRIO_SRCDST_OPS_WRITE_CAR_MASK)
+ Status = XST_SUCCESS;
+ break;
+ case XSRIO_OP_MODE_SWRITE:
+ if(OperationCar & XSRIO_SRCDST_OPS_SWRITE_CAR_MASK)
+ Status = XST_SUCCESS;
+ break;
+ case XSRIO_OP_MODE_NWRITE_R:
+ if(OperationCar & XSRIO_SRCDST_OPS_WRITE_RESPONSE_CAR_MASK)
+ Status = XST_SUCCESS;
+ break;
+ case XSRIO_OP_MODE_DATA_MESSAGE:
+ if(OperationCar & XSRIO_SRCDST_OPS_DATA_MSG_CAR_MASK)
+ Status = XST_SUCCESS;
+ break;
+ case XSRIO_OP_MODE_DOORBELL:
+ if(OperationCar & XSRIO_SRCDST_OPS_DOORBELL_CAR_MASK)
+ Status = XST_SUCCESS;
+ break;
+ case XSRIO_OP_MODE_ATOMIC:
+ if(OperationCar & XSRIO_SRCDST_OPS_ATOMIC_SET_CAR_MASK)
+ Status = XST_SUCCESS;
+ break;
+ default:
+ Status = XST_FAILURE;
+ }
+ return Status;
+}
diff --git a/XilinxProcessorIPLib/drivers/srio/src/xsrio.h b/XilinxProcessorIPLib/drivers/srio/src/xsrio.h
new file mode 100755
index 00000000..f6e9822f
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/srio/src/xsrio.h
@@ -0,0 +1,1684 @@
+/******************************************************************************
+*
+* (c) Copyright 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsrio.h
+*
+* This file contains the implementation of the SRIO Gen2 driver.
+* User documentation for the driver functions is contained in this file in the
+* form of comment blocks at the front of each function.
+
+* The SRIO Gen2 Core supports RapidIO Interconnect Specification rev. 2.2
+* The SRIO Gen2 Endpoint comprises of the phy ,logical and transport and buffer
+* layers. Using the SRIO Gen2 Endpoint Core we can generate I/O transactions
+* Read(NREAD), Write(NWRITE), Read with response (NREAD_R), Stream write(SWRITE)
+* atomic operations(atomic set,clear,test and swap etc...). It also supports
+* Messaging Transactions Message (MESSAGE), Doorbell(DOORBELL)and
+* 8-bit/16-bit device ID's.
+*
+* Initialization & Configuration
+*
+* The XSrio_Config structure is used by the driver to configure itself.
+* This configuration structure is typically created by the tool-chain based
+* on HW build properties.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+* - XSrio_LookupConfig(DeviceId) - Use the device identifier to find the
+* static configuration structure defined in xsrio_g.c. This is setup
+* by the tools. For some operating systems the config structure will be
+* initialized by the software and this call is not needed.
+*
+* - XSrio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the provided virtual memory base address
+* replaces the physical address present in the configuration structure.
+*
+* Interrupts
+* There are no interrupts available for the SRIO Gen2 Core.
+*
+* Examples
+*
+* There is an example provided to show the usage of the APIs
+* - SRIO Dma loopback example (xsrio_dma_loopback_example.c)
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied
+* by the layer above this driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 adk 16/04/14 Initial release.
+*
+*
+******************************************************************************/
+
+#ifndef XSRIO_H /* prevent circular inclusions */
+#define XSRIO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include
+#include "xstatus.h"
+#include "xil_assert.h"
+#include "xsrio_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/* Processing Element SRIO Gen2 PE Features Flags */
+#define XSRIO_IS_MEMORY 1 /**< Core has physically addressable
+ * storage space
+ */
+#define XSRIO_IS_PROCESSOR 2 /**< Core has a local processor that
+ * runs code
+ */
+#define XSRIO_IS_BRIDGE 3 /**< Core can be used as a bridge to
+ * another interface
+ */
+
+/* Processing Element(SRIO Gen2 Core) Operating Mode Flags */
+#define XSRIO_OP_MODE_NREAD 0 /**< Core supports read Operation */
+#define XSRIO_OP_MODE_NWRITE 1 /**< Core supports write Operation */
+#define XSRIO_OP_MODE_SWRITE 2 /**< Core supports streaming-write
+ * Operation
+ */
+#define XSRIO_OP_MODE_NWRITE_R 3 /**< Core supports write with
+ * Response operation
+ */
+#define XSRIO_OP_MODE_DATA_MESSAGE 4 /**< Core supports data message
+ * Operation
+ */
+#define XSRIO_OP_MODE_DOORBELL 5 /**< Core supports doorbell
+ * Operation
+ */
+#define XSRIO_OP_MODE_ATOMIC 6 /**< Core supports atomic
+ * Operation
+ */
+
+/* Processing Element(SRIO Gen2 Core) Port State Flags */
+#define XSRIO_PORT_OK 0 /**< Port is initialized */
+#define XSRIO_PORT_UNINITIALIZED 1 /**< Port is uninitialized */
+#define XSRIO_PORT_HAS_ERRORS 2 /**< Port has errors */
+
+/* Processing Element(SRIO Gen2 Core Direction Flags */
+#define XSRIO_DIR_TX 1 /**< Transmit Direction Flag */
+#define XSRIO_DIR_RX 2 /**< Receive Direction Flag */
+
+/************************** Type Definitions *****************************/
+
+/**
+ * This typedef contains the configuration information for the device.
+ */
+typedef struct XSrio_Config {
+ u16 DeviceId; /**< Device Id */
+ u32 BaseAddress; /**< Base Address */
+ u8 IsPEMemory; /**< Core is configured as Memory */
+ u8 IsPEProcessor; /**< Core is configured as Processor */
+ u8 IsPEBridge; /**< Core is Configured as Bridge */
+} XSrio_Config;
+
+/**
+ * The XSrio driver instance data. An instance must be allocated for
+ * each SRIO device in use.
+ */
+typedef struct XSrio {
+ XSrio_Config Config; /**< Config Structure */
+ int IsReady; /**< Device is initialized and ready */
+ int PortWidth; /**< Serial lane Port width (1x or 2x or 4x) */
+} XSrio;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* XSrio_ReadDeviceVendorID returns the Device Vendor Id of the core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Device Vendor ID of the core.
+*
+* @note C-style signature:
+* u16 XSrio_ReadDeviceVendorID(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_ReadDeviceVendorID(InstancePtr) \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_DEV_ID_CAR_OFFSET) & XSRIO_DEV_ID_VDRID_CAR_MASK)
+
+/****************************************************************************/
+/**
+*
+* XSrio_ReadDeviceID returns the Device Id of the core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Device ID of the core.
+*
+* @note C-style signature:
+* u16 XSrio_ReadDeviceID(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_ReadDeviceID(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_DEV_ID_CAR_OFFSET) & XSRIO_DEV_ID_DEVID_CAR_MASK) >> \
+ XSRIO_DEV_ID_DEVID_CAR_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_ReadAsmVendorID retruns the Assembly Vendor Id of the core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Assembly Vendor ID of the core.
+*
+* @note C-style signature:
+* u16 XSrio_ReadAsmVendorID(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_ReadAsmVendorID(InstancePtr) \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_ASM_ID_CAR_OFFSET) & XSRIO_ASM_ID_ASMVID_CAR_MASK)
+
+/****************************************************************************/
+/**
+*
+* XSrio_ReadAsmID returns the Assembly Id of the SRIO Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Assembly ID of the core.
+*
+* @note C-style signature:
+* u16 XSrio_ReadAsmID(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_ReadAsmID(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_ASM_ID_CAR_OFFSET) & XSRIO_ASM_ID_ASMID_CAR_MASK) >> \
+ XSRIO_ASM_ID_ASMID_CAR_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetExFeaturesPointer gives the pointer to the Phy Register space of
+* the SRIO Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Pointer to the Phy Register space of the core.
+*
+* @note C-style signature:
+* u16 XSrio_GetExFeaturesPointer(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetExFeaturesPointer(InstancePtr) \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_ASM_INFO_CAR_OFFSET) & XSRIO_ASM_INFO_EFP_CAR_MASK)
+
+/****************************************************************************/
+/**
+*
+* XSrio_ReadAsmRevision returns the Assembly Revision value of the core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Assembly revision of the core.
+*
+* @note C-style signature:
+* u16 XSrio_ReadAsmRevision(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_ReadAsmRevision(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_ASM_INFO_CAR_OFFSET) & XSRIO_ASM_INFO_ASR_CAR_MASK) >> \
+ XSRIO_ASM_INFO_ASR_CAR_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_IsLargeSystem checks whether PE(Processing Element) supports a large
+* system (16-bit Device ids)
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return
+* - TRUE If the System Supports 16-bit Devices.
+* - FALSE If the System Supports 8-bit Devices.
+*
+* @note C-style signature:
+* u8 XSrio_IsLargeSystem(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_IsLargeSystem(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PEF_CAR_OFFSET) & XSRIO_PEF_CTS_CAR_MASK) ? \
+ TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XSrio_IsCRFSupported checks whether the PE(Processing Element) supports
+* CRF(Critical Request Flow indicator).
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return
+* - TRUE If the System Supports CRF.
+* - FALSE If the System Wont Support CRF.
+*
+* @note C-style signature:
+* u8 XSrio_IsCRFSupported(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_IsCRFSupported(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PEF_CAR_OFFSET) & XSRIO_PEF_CRF_CAR_MASK) ? \
+ TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XSrio_ReadSrcOps returns the Source Operations CAR Register contents.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Contents of the Source Operations CAR Register.
+*
+* @note C-style signature:
+* u32 XSrio_ReadSrcOps(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_ReadSrcOps(InstancePtr) \
+ XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_SRC_OPS_CAR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* XSrio_ReadDstOps returns the Destination Operations CAR Register contents.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Contents of the Destination Operations CAR Register.
+*
+* @note C-style signature:
+* u32 XSrio_ReadDstOps(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_ReadDstOps(InstancePtr) \
+ XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_DST_OPS_CAR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetLCSBA returns the Local Configuration Space Base Address(LCSBA) of
+* the SRIO Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Contents of Local Configuration Space Base Address Register.
+*
+* @note C-style signature:
+* u32 XSrio_GetLCSBA(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetLCSBA(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_LCS1_BASEADDR_CSR_OFFSET) & \
+ XSRIO_LCS1_BASEADDR_LCSBA_CSR_MASK) >> \
+ XSRIO_LCS1_BASEADDR_LCSBA_CSR_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetLCSBA it sets the Local Configuration Space Base Address of
+* the SRIO Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Value is the Local Configuration Space Base Address that
+* needs to be configured.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetLCSBA(XSrio *InstancePtr, u32 Value)
+*
+*****************************************************************************/
+#define XSrio_SetLCSBA(InstancePtr, Value) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_LCS1_BASEADDR_CSR_OFFSET, \
+ ((Value << XSRIO_LCS1_BASEADDR_LCSBA_CSR_SHIFT) \
+ & XSRIO_LCS1_BASEADDR_LCSBA_CSR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetLargeBaseDeviceID returns the 16-bit Device Id for an endpoint in a
+* Large transport system.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return 16-bit Device Id.
+*
+* @note C-style signature:
+* u16 XSrio_GetLargeBaseDeviceID(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetLargeBaseDeviceID(InstancePtr) \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_BASE_DID_CSR_OFFSET) & \
+ XSRIO_BASE_DID_LBDID_CSR_MASK)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetLargeBaseDeviceID configures the 16-bit Device Id for an endpoint in
+* a Large transport system.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param DeviceId is the Device ID that needs to be configured.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetLargeBaseDeviceID(XSrio *InstancePtr, u16 DeviceId)
+*
+*****************************************************************************/
+#define XSrio_SetLargeBaseDeviceID(InstancePtr, DeviceId) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_BASE_DID_CSR_OFFSET, \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_BASE_DID_CSR_OFFSET) & XSRIO_BASI_DID_BDID_CSR_MASK) | \
+ (DeviceId & XSRIO_BASE_DID_LBDID_CSR_MASK))))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetBaseDeviceID returns the 8-bit Device Id for an endpoint in a small
+* Transport system.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return 8-bit Device Id.
+*
+* @note C-style signature:
+* u8 XSrio_GetBaseDeviceID(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetBaseDeviceID(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_BASE_DID_CSR_OFFSET) & \
+ XSRIO_BASI_DID_BDID_CSR_MASK) >> XSRIO_BASI_DID_BDID_CSR_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetBaseDeviceID configures the 8-bit Device Id for an endpoint in a
+* small transport system.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param DeviceId is the Device ID that needs to be configured.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetBaseDeviceID(XSrio *InstancePtr, u8 DeviceId)
+*
+*****************************************************************************/
+#define XSrio_SetBaseDeviceID(InstancePtr, DeviceId) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_BASE_DID_CSR_OFFSET, \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_BASE_DID_CSR_OFFSET) & XSRIO_BASE_DID_LBDID_CSR_MASK) \
+ |((DeviceId << XSRIO_BASI_DID_BDID_CSR_SHIFT) \
+ & XSRIO_BASI_DID_BDID_CSR_MASK))))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetHostBaseDevID_LockCSR returns the Device Id of the system host.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Device Id of the system host.
+*
+* @note C-style signature:
+* u16 XSrio_GetHostBaseDevID_LockCSR(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetHostBaseDevID_LockCSR(InstancePtr) \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_HOST_DID_LOCK_CSR_OFFSET) & \
+ XSRIO_HOST_DID_LOCK_HBDID_CSR_MASK)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetHostBaseDevID_LockCSR configures the Host Base Device Id of
+* the SRIO gen2 Core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param DeviceId is the Device ID that needs to be configured.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetHostBaseDevID_LockCSR(XSrio *InstancePtr,
+* u16 DeviceId)
+*
+*****************************************************************************/
+#define XSrio_SetHostBaseDevID_LockCSR(InstancePtr, DeviceId) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_HOST_DID_LOCK_CSR_OFFSET, \
+ (DeviceId & XSRIO_HOST_DID_LOCK_HBDID_CSR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetComponentTagCSR returns the Component Tag Value set by the software
+* during initialization.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Component Tag Value.
+*
+* @note C-style signature:
+* u32 XSrio_GetComponentTagCSR(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetComponentTagCSR(InstancePtr) \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_COMPONENT_TAG_CSR_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetComponentTagCSR sets the Component Tag Value for SRIO Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Value is the Component Tag Value to be set.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetComponentTagCSR(XSrio *InstancePtr, u32 Value)
+*
+*****************************************************************************/
+#define XSrio_SetComponentTagCSR(InstancePtr, Value) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_COMPONENT_TAG_CSR_OFFSET, \
+ Value))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetExtFeaturesID returns the Extended Features Id value.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Extended Features ID Value.
+*
+* @note C-style signature:
+* u16 XSrio_GetExtFeaturesID(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetExtFeaturesID(InstancePtr) \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_EFB_HEADER_OFFSET) & \
+ XSRIO_EFB_HEADER_EFID_MASK)
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetSerialExtFeaturesPointer returns the Extended Features Pointer which
+* will point to the next extended features block if one exists.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Extended Features Pointer Address.
+*
+* @note C-style signature:
+* u16 XSrio_GetSerialExtFeaturesPointer(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetSerialExtFeaturesPointer(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_EFB_HEADER_OFFSET) & \
+ XSRIO_EFB_HEADER_EFP_MASK) >> XSRIO_EFB_HEADER_EFP_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetPortLinkTimeOutValue returns the Port Link Timeout value for the
+* SRIO Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Port link Timeout Value.
+*
+* @note C-style signature:
+* u32 XSrio_GetPortLinkTimeOutValue(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetPortLinkTimeOutValue(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_TOUT_CSR_OFFSET) & \
+ XSRIO_PORT_TOUT_TOUTVAL_CSR_MASK) >> \
+ XSRIO_PORT_TOUT_TOUTVAL_CSR_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetPortLinkTimeOutValue sets the Port Link Timeout value for the
+* SRIO Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Value is the Port Link Timeout value to be set.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetPortLinkTimeOutValue(XSrio *InstancePtr,
+* u16 Value)
+*
+*****************************************************************************/
+#define XSrio_SetPortLinkTimeOutValue(InstancePtr, Value) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_TOUT_CSR_OFFSET, \
+ (Value << XSRIO_PORT_TOUT_TOUTVAL_CSR_SHIFT) & \
+ XSRIO_PORT_TOUT_TOUTVAL_CSR_MASK))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetPortRespTimeOutValue returns the Port Response Timeout value for the
+* the SRIO Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Port Response Timeout value.
+*
+* @note C-style signature:
+* u32 XSrio_GetPortRespTimeOutValue(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetPortRespTimeOutValue(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_RSP_TOUT_CSR_OFFSET) & \
+ XSRIO_RSP_TOUT_TOUTVAL_CSR_MASK) >> \
+ XSRIO_RSP_TOUT_TOUTVAL_CSR_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetPortRespTimeOutValue sets the Port Response Timeout value for the
+* The SRIO Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Value is the Port Response Timeout to be set.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetPortRespTimeOutValue(XSrio *InstancePtr,
+* u16 Value)
+*
+*****************************************************************************/
+#define XSrio_SetPortRespTimeOutValue(InstancePtr, Value) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_RSP_TOUT_CSR_OFFSET, \
+ (Value << XSRIO_RSP_TOUT_TOUTVAL_CSR_SHIFT) & \
+ XSRIO_RSP_TOUT_TOUTVAL_CSR_MASK))
+
+/****************************************************************************/
+/**
+*
+* XSrio_IsPEDiscovered checks whether the PE(Processing Element) is discovered
+* or not.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return
+* - TRUE If the PE is Discovered.
+* - FALSE If the PE is not Discovered.
+*
+* @note C-style signature:
+* u8 XSrio_IsPEDiscovered(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_IsPEDiscovered(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_GEN_CTL_CSR_OFFSET) & \
+ XSRIO_GEN_CTL_DISCOVERED_CSR_MASK) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XSrio_Discovered configures the device as Discovered so that it is
+* responsible for system exploration.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_Discovered(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_Discovered(InstancePtr) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_GEN_CTL_CSR_OFFSET, \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_GEN_CTL_CSR_OFFSET) \
+ | XSRIO_GEN_CTL_DISCOVERED_CSR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* XSrio_IsMasterEnabled checks whether PE(Processing Element) is allowed to
+* issue request into the system.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return
+* - TRUE If the Master Enable bit is set.
+* - FALSE If the Master Enable bit is not set.
+*
+* @note C-style signature:
+* u8 XSrio_IsMasterEnabled(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_IsMasterEnabled(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_GEN_CTL_CSR_OFFSET) \
+ & XSRIO_GEN_CTL_MENABLE_CSR_MASK) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XSrio_MasterEnabled configures the device so that it is allowed to issue
+* requests into the system.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_MasterEnabled(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_MasterEnabled(InstancePtr) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_GEN_CTL_CSR_OFFSET, \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_GEN_CTL_CSR_OFFSET) \
+ | XSRIO_GEN_CTL_MENABLE_CSR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* XSrio_IsHost checks whether PE(Processing Element) is responsible for
+* system exploration.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return
+* - TRUE If the Host bit is set.
+* - FALSE If the Host bit is not set.
+*
+* @note C-style signature:
+* u8 XSrio_IsHost(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_IsHost(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_GEN_CTL_CSR_OFFSET) \
+ & XSRIO_GEN_CTL_HOST_CSR_MASK) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XSrio_HostEnabled configures the device to be responsible for system
+* exploration.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_HostEnabled(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_HostEnabled(InstancePtr) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_GEN_CTL_CSR_OFFSET, \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_GEN_CTL_CSR_OFFSET) \
+ | XSRIO_GEN_CTL_HOST_CSR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetCommand returns the command value that is sent on the Link-request
+* Control symbol of the SRIO Gen2 core. This api is available only if the
+* software assisted error recovery option is enabled in the core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Command information of the link-request control symbol.
+*
+* @note C-style signature:
+* u32 XSrio_GetCommand(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetCommand(InstancePtr) \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_MNT_REQ_CSR_OFFSET) & \
+ XSRIO_PORT_N_MNT_REQ_CMD_CSR_MASK)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SendCommand sends the given command in the link-request control symbol
+* of the SRIO Gen2 core. This api is available only if the software assisted
+* error recovery option is selected in the core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Value is the Command to be send.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SendCommand(XSrio *InstancePtr, u8 Value)
+*
+*****************************************************************************/
+#define XSrio_SendCommand(InstancePtr, Value) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_MNT_REQ_CSR_OFFSET, \
+ Value & XSRIO_PORT_N_MNT_REQ_CMD_CSR_MASK))
+
+/****************************************************************************/
+/**
+*
+* XSrio_IsResponseValid checks whether the link response is valid or not in
+* the SRIO Gen2 Core. This api is available only if the software assisted error
+* recovery option is enabled in the core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return
+* - TRUE if the corresponding link request causes a link
+* response.
+* - FALSE if the corresponding link request not causes a link
+* response.
+*
+* @note C-style signature:
+* u8 XSrio_IsResponseValid(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_IsResponseValid(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_MNT_RES_CSR_OFFSET) & \
+ XSRIO_PORT_N_MNT_RES_RVALID_CSR_MASK) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetOutboundAckID returns the value of the next transmitted Ackid of
+* the SRIO Gen2 Core. This api is available only if the software assisted error
+* recovery option is selected core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Outbound Ack ID value.
+*
+* @note C-style signature:
+* u32 XSrio_GetOutboundAckID(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetOutboundAckID(InstancePtr) \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_ACKID_CSR_OFFSET) & \
+ XSRIO_PORT_N_ACKID_OBACKID_CSR_MASK)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetOutboundAckID sets value of the next transmitted Ackid of
+* the SRIO Gen2 Core. This api is available only if the software assisted error
+* Recovery option is selected in the core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Value is the Outbound Ack Id to be set.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetOutboundAckID(XSrio *InstancePtr, u8 Value)
+*
+*****************************************************************************/
+#define XSrio_SetOutboundAckID(InstancePtr, Value) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_ACKID_CSR_OFFSET, \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_ACKID_CSR_OFFSET) & \
+ XSRIO_PORT_N_ACKID_RESET_OBACKID_CSR_MASK) \
+ | (Value & XSRIO_PORT_N_ACKID_OBACKID_CSR_MASK))))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetInboundAckID returns the expected Ackid of the next received packet
+* of the SRIO Gen2 core. This api is available only if the software assisted
+* error recovery option is selected in the core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Inbound Ack ID value.
+*
+* @note C-style signature:
+* u32 XSrio_GetInboundAckID(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetInboundAckID(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_ACKID_CSR_OFFSET) & \
+ XSRIO_PORT_N_ACKID_IBACKID_CSR_MASK) >> \
+ XSRIO_PORT_N_ACKID_IBACKID_CSR_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetInboundAckID sets the value of the next transmitted Ackid of
+* the SRIO Gen2 core. This api is available only if the software assisted error
+* recovery option is selected in the core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Value is the InBound Ack Id to be set.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetInboundAckID(XSrio *InstancePtr,
+* u8 Value)
+* This api won't work if you call the XSrio_ClrOutStandingAckIDs
+* before calling this api.
+*
+*****************************************************************************/
+#define XSrio_SetInboundAckID(InstancePtr, Value) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_ACKID_CSR_OFFSET, \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_ACKID_CSR_OFFSET) & \
+ XSRIO_PORT_N_ACKID_RESET_IBACKID_CSR_MASK) \
+ | ((Value << XSRIO_PORT_N_ACKID_IBACKID_CSR_SHIFT) & \
+ XSRIO_PORT_N_ACKID_IBACKID_CSR_MASK))))
+
+/****************************************************************************/
+/**
+*
+* XSrio_ClrOutStandingAckIDs clears all outstanding unacknowledged
+* received packets of the SRIO Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_ClrOutStandingAckIDs(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_ClrOutStandingAckIDs(InstancePtr) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_ACKID_CSR_OFFSET, \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_ACKID_CSR_OFFSET) \
+ | XSRIO_PORT_N_ACKID_CLSACKID_CSR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* XSrio_IsEnumerationBoundary checks whether the enumeration boundary is
+* available or not for the SRIO Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return
+* - TRUE if the EnumerationBoundary Enabled.
+* - FALSE if the EnumerationBoundary is not Enabled.
+*
+* @note C-style signature:
+* u8 XSrio_IsEnumerationBoundary(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_IsEnumerationBoundary(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_CTL_CSR_OFFSET) & \
+ XSRIO_PORT_N_CTL_ENUMB_CSR_MASK) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XSrio_ClrEnumerationBoundary clears the enumeration boundary of the
+* SRIO Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_ClrEnumerationBoundary(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_ClrEnumerationBoundary(InstancePtr) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_CTL_CSR_OFFSET, \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_CTL_CSR_OFFSET) \
+ | XSRIO_PORT_N_CTL_ENUMB_CSR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetPortwidthOverride it gives the port width override value of the
+* SRIO Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Port Width Override Value.
+*
+* @note C-style signature:
+* u8 XSrio_GetPortwidthOverride(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetPortwidthOverride(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_CTL_CSR_OFFSET) & \
+ XSRIO_PORT_N_CTL_PWO_CSR_MASK) >> XSRIO_PORT_N_CTL_PWO_CSR_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetPortwidthOverride it sets the port width override value of the SRIO
+* Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Value is the port width override value needs to be set.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetPortwidthOverride(XSrio *InstancePtr, u8 Value)
+*
+*****************************************************************************/
+#define XSrio_SetPortwidthOverride(InstancePtr, Value) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_CTL_CSR_OFFSET, \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_CTL_CSR_OFFSET) & \
+ XSRIO_PORT_N_CTL_RESET_PWO_CSR_MASK) | \
+ ((Value << XSRIO_PORT_N_CTL_PWO_CSR_SHIFT) \
+ & XSRIO_PORT_N_CTL_PWO_CSR_MASK))))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetSerialLaneExtFeaturesPointer it gives the exteneded features pointer
+* For the serial lane which will point to the next extended features block
+* If one exists.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Extended Features Pointer Address.
+*
+* @note C-style signature:
+* u16 XSrio_GetSerialLaneExtFeaturesPointer(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetSerialLaneExtFeaturesPointer(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_EFB_LPSL_OFFSET + XSRIO_SL_HEADER_OFFSET) & \
+ XSRIO_SL_HEADER_EFP_MASK) >> XSRIO_SL_HEADER_EFP_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_ClrDecodingErrors it will clears the 8B/10B decoding errors and return
+* Result.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Lanenum is the Serial Lane-number(0,1,2,3).
+*
+* @return None
+*
+*
+* @note C-style signature:
+* int XSrio_ClrDecodingErrors(XSrio *InstancePtr, u8 Lanenum)
+*
+*****************************************************************************/
+#define XSrio_ClrDecodingErrors(InstancePtr, Lanenum) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_EFB_LPSL_OFFSET + XSRIO_SLS0_CSR_OFFSET(Lanenum)) & \
+ XSRIO_SLS0_CSR_DECODING_ERRORS_MASK) \
+ >> XSRIO_SLS0_CSR_DECODING_ERRORS_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetWaterMark0 it gives the water mark0 buffer space value which will be
+* Use by the link partner to send a priority 0 packet.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Water Mark buffer space value.
+*
+* @note C-style signature:
+* u8 XSrio_GetWaterMark0(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetWaterMark0(InstancePtr) \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_WCSR_OFFSET) & \
+ XSRIO_IMP_WCSR_WM0_MASK)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetWaterMark0 sets water mark0 buffer space value which will be used
+* By the link partner to send a priority 0 packet.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Value to set for a priority 0 packet.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetWaterMark0(XSrio *InstancePtr, u8 Value)
+*
+*****************************************************************************/
+#define XSrio_SetWaterMark0(InstancePtr, Value) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_WCSR_OFFSET, \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_WCSR_OFFSET) & XSRIO_IMP_WCSR_RESET_WM0_MASK) | \
+ (Value & XSRIO_IMP_WCSR_WM0_MASK))))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetWaterMark1 returns the water mark1 buffer space value which will be
+* Use by the link partner to send a priority 1 packet.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Water Mark buffer space value.
+*
+* @note C-style signature:
+* u8 XSrio_GetWaterMark1(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetWaterMark1(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_WCSR_OFFSET ) & \
+ XSRIO_IMP_WCSR_WM1_MASK) >> XSRIO_IMP_WCSR_WM1_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetWaterMark1 sets the water mark1 buffer space value which will be
+* Use by the link partner to send a priority 1 packet.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Value to set for a priority 1 packet.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetWaterMark1(XSrio *InstancePtr, u8 Value)
+*
+*****************************************************************************/
+#define XSrio_SetWaterMark1(InstancePtr, Value) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_WCSR_OFFSET, \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_WCSR_OFFSET) & XSRIO_IMP_WCSR_RESET_WM1_MASK) |\
+ ((Value << XSRIO_IMP_WCSR_WM1_SHIFT) \
+ & XSRIO_IMP_WCSR_WM1_MASK))))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetWaterMark2 returns the water mark2 buffer space value which will be
+* Use by the link partner to send a priority 2 packet.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Water Mark buffer space value..
+*
+* @note C-style signature:
+* u8 XSrio_GetWaterMark2(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetWaterMark2(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_WCSR_OFFSET ) & \
+ XSRIO_IMP_WCSR_WM2_MASK) >> XSRIO_IMP_WCSR_WM2_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetWaterMark2 sets the water mark2 buffer space value which will be
+* Use by the link partner to send a priority 2 packet.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Value to set for a priority 2 packet.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetWaterMark2(XSrio *InstancePtr, u8 Value)
+*
+*****************************************************************************/
+#define XSrio_SetWaterMark2(InstancePtr, Value) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_WCSR_OFFSET, \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_WCSR_OFFSET) & XSRIO_IMP_WCSR_RESET_WM2_MASK) | \
+ ((Value << XSRIO_IMP_WCSR_WM2_SHIFT) \
+ & XSRIO_IMP_WCSR_WM2_MASK))))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetRxSize returns the number of maximum-size packets the rx buffer
+* holded.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Rx buffer size.
+*
+* @note C-style signature:
+* u8 XSrio_GetRxSize(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetRxSize(InstancePtr) \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_BCSR_OFFSET ) & \
+ XSRIO_IMP_BCSR_RXSIZE_MASK)
+
+/****************************************************************************/
+/**
+*
+* XSrio_ForceRxFlowControl forces the Tx flow control enabled core to use
+* Rx flow control.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_ForceRxFlowControl(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_ForceRxFlowControl(InstancePtr) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_BCSR_OFFSET, \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_BCSR_OFFSET) | \
+ XSRIO_IMP_BCSR_FRX_FLOW_CNTL_MASK)))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetTxSize returns the number of maximum-size packets the tx buffer
+* holds.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Tx buffer size.
+*
+* @note C-style signature:
+* u8 XSrio_GetTxSize(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetTxSize(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_BCSR_OFFSET ) & \
+ XSRIO_IMP_BCSR_TXSIZE_MASK) >> XSRIO_IMP_BCSR_TXSIZE_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_CheckforTxReqreorder checks whether the transmit buffer has been
+* configured to allow reordering of requests.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return
+* - TRUE If the Tx Request reorder is enabled in the core.
+* - FALSE If the Tx Request reorder is not enabled in the core.
+*
+* @note C-style signature:
+* u8 XSrio_CheckforTxReqreorder(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_CheckforTxReqreorder(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_BCSR_OFFSET) & \
+ XSRIO_IMP_BCSR_TXREQ_REORDER_MASK) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XSrio_IsTxFlowControl checks whether the BUF is currently operating in
+* Tx flow control mode or not.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return
+* - TRUE If the Tx Flow Control is enabled in the core.
+* - FALSE If the Tx Flow Control is not enabled in the core.
+*
+* @note C-style signature:
+* u8 XSrio_IsTxFlowControl(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_IsTxFlowControl(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_BCSR_OFFSET) & \
+ XSRIO_IMP_BCSR_TX_FLOW_CNTL_MASK) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XSrio_RequestDestinationID gets the destination id value which will be
+* used for outgoing maintenance requests.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Destination ID value of the outgoing maintenance request.
+*
+* @note C-style signature:
+* u8 XSrio_RequestDestinationID(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetDestinationID(InstancePtr) \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_MRIR_OFFSET ) & \
+ XSRIO_IMP_MRIR_REQ_DESTID_MASK)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetDestinationID sets Device Id which will be used for
+* Outgoing maintenance requests.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Value is the Device Id value.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetDestinationID(XSrio *InstancePtr, u8 Value)
+*
+*****************************************************************************/
+#define XSrio_SetDestinationID(InstancePtr, Value) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_MRIR_OFFSET, \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_MRIR_OFFSET) & XSRIO_IMP_MRIR_RST_REQ_DESTID_MASK) | \
+ (Value & XSRIO_IMP_MRIR_REQ_DESTID_MASK))))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetCRF checks whethere the CRF is enabled in the core or not which will
+* be used for outgoing maintenance requests.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return CRF Value used for outgoing maintenance requests.
+*
+* @note C-style signature:
+* u8 XSrio_RequestCRF(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetCRF(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_MRIR_OFFSET) & \
+ XSRIO_IMP_MRIR_REQ_CRF_MASK) >> XSRIO_IMP_MRIR_REQ_CRF_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetCRF sets CRF value that is used for outgoing maintenance requests.
+* This api will work only when the CRF support is enabled in the core
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetCRF(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_SetCRF(InstancePtr) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_MRIR_OFFSET, \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_MRIR_OFFSET) | \
+ XSRIO_IMP_MRIR_REQ_CRF_MASK)))
+
+/****************************************************************************/
+/**
+*
+* XSrio_RequestPriority priority used for outgoing maintenance requests.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Priority value.
+*
+* @note C-style signature:
+* u8 XSrio_RequestPriority(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetPriority(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_MRIR_OFFSET ) & \
+ XSRIO_IMP_MRIR_REQ_PRIO_MASK) >> XSRIO_IMP_MRIR_REQ_PRIO_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetPriority sets the Priority which will be used for
+* outgoing maintenance requests.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Value is the Priority value which will used for outgoing
+* maintenance requests.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetPriority(XSrio *InstancePtr, u8 Value)
+*
+*****************************************************************************/
+#define XSrio_SetPriority(InstancePtr, Value) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_MRIR_OFFSET, \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_MRIR_OFFSET) & XSRIO_IMP_MRIR_RST_REQ_PRIO_MASK) | \
+ ((Value << XSRIO_IMP_MRIR_REQ_PRIO_SHIFT)& \
+ XSRIO_IMP_MRIR_REQ_PRIO_MASK))))
+
+/****************************************************************************/
+/**
+*
+* XSrio_RequestTID gives the transfer id value which will be used for the
+* next outgoing maintenance request. This value will increment after each
+* request is sent.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return Transfer ID value.
+*
+* @note C-style signature:
+* u8 XSrio_RequestTID(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_RequestTID(InstancePtr) \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_MRIR_OFFSET ) & \
+ XSRIO_IMP_MRIR_REQ_TID_MASK) >> XSRIO_IMP_MRIR_REQ_TID_SHIFT)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetTID sets the transfer id which will be used for the next outgoing
+* maintenance request.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Value is the transfer id value which of the next outgoing
+* maintenance request.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetTID(XSrio *InstancePtr, u8 Value)
+*
+*****************************************************************************/
+#define XSrio_SetTID(InstancePtr, Value) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_MRIR_OFFSET, \
+ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_IMP_MRIR_OFFSET) & XSRIO_IMP_MRIR_REQ_RST_TID_MASK) | \
+ ((Value << XSRIO_IMP_MRIR_REQ_TID_SHIFT)& \
+ XSRIO_IMP_MRIR_REQ_TID_MASK))))
+
+/****************************************************************************/
+/**
+*
+* XSrio_ClrPortError clears the Port Error specified by the Mask.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Mask is the mask for the Port Error to be cleared.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_ClrPortError(XSrio *InstancePtrm, u32 Mask)
+*
+*****************************************************************************/
+#define XSrio_ClrPortError(InstancePtr, Mask) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_ERR_STS_CSR_OFFSET, \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_ERR_STS_CSR_OFFSET) \
+ | (Mask & XSRIO_PORT_N_ERR_STS_ERR_ALL_CSR_MASK))))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetPortErrorStatus returns the mask for the port errors currently
+* enabled in the SRIO Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return The bit mask for the port errors that are currently enabled.
+*
+* @note C-style signature:
+* u32 XSrio_GetPortErrorStatus(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetPortErrorStatus(InstancePtr) \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_ERR_STS_CSR_OFFSET) & \
+ XSRIO_PORT_N_ERR_STS_ERR_ALL_CSR_MASK)
+
+/****************************************************************************/
+/**
+*
+* XSrio_SetPortControlStatus Configures specific port specified by the Mask.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+* @param Mask is the mask for the port that needs to be enabled.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XSrio_SetPortControlStatus(XSrio *InstancePtrm, u32 Mask)
+*
+*****************************************************************************/
+#define XSrio_SetPortControlStatus(InstancePtr, Mask) \
+ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_CTL_CSR_OFFSET, \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_CTL_CSR_OFFSET) \
+ | (Mask & XSRIO_PORT_N_CTRL_CSR_STATUS_ALL_MASK))))
+
+/****************************************************************************/
+/**
+*
+* XSrio_GetPortControlStatus returns the status of the port that is currently
+* enabled in the SRIO Gen2 core.
+*
+* @param InstancePtr is a pointer to the SRIO Gen2 instance to be
+* worked on.
+*
+* @return The bit mask for the ports that are currently enabled.
+*
+* @note C-style signature:
+* u32 XSrio_GetPortControlStatus(XSrio *InstancePtr)
+*
+*****************************************************************************/
+#define XSrio_GetPortControlStatus(InstancePtr) \
+ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XSRIO_PORT_N_CTL_CSR_OFFSET) & \
+ XSRIO_PORT_N_CTRL_CSR_STATUS_ALL_MASK)
+
+/*************************** Function Prototypes ******************************/
+/**
+ * Initialization and Control functions in xsrio.c
+ */
+int XSrio_CfgInitialize(XSrio * InstancePtr,
+ XSrio_Config *Config, u32 EffectiveAddress);
+XSrio_Config *XSrio_LookupConfig(u32 DeviceId);
+int XSrio_GetPortStatus(XSrio *InstancePtr);
+int XSrio_GetPEType(XSrio *InstancePtr);
+int XSrio_IsOperationSupported(XSrio * InstancePtr, u8 Operation, u8 Direction);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/XilinxProcessorIPLib/drivers/srio/src/xsrio_g.c b/XilinxProcessorIPLib/drivers/srio/src/xsrio_g.c
new file mode 100755
index 00000000..54032ff3
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/srio/src/xsrio_g.c
@@ -0,0 +1,77 @@
+/******************************************************************************
+*
+* (c) Copyright 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsrio_g.c
+*
+* This file contains a configuration table that specifies the configuration of
+* SRIO devices in the system. Each SRIO device in the system should have an entry
+* in the table.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 adk 16/04/14 Initial release
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xsrio.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+XSrio_Config XSrio_ConfigTable[] =
+{
+ {
+ XPAR_SRIO_0_DEVICE_ID,
+ XPAR_SRIO_0_BASEADDR,
+ XPAR_SRIO_0_PE_MEMORY,
+ XPAR_SRIO_0_PE_PROC,
+ XPAR_SRIO_0_PE_BRIDGE
+ }
+};
diff --git a/XilinxProcessorIPLib/drivers/srio/src/xsrio_hw.h b/XilinxProcessorIPLib/drivers/srio/src/xsrio_hw.h
new file mode 100755
index 00000000..6f28e97f
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/srio/src/xsrio_hw.h
@@ -0,0 +1,678 @@
+/******************************************************************************
+*
+* (c) Copyright 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/**
+*
+* @file xsrio_hw.h
+*
+* This header file contains identifiers and macros that can be used to access
+* the Axi srio gen2 device. The driver APIs/functions are defined in
+* xsrio.h.
+*
+* @note
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.0 adk 16/04/14 Initial release.
+*
+******************************************************************************/
+
+#ifndef XSRIO_HW_H /* prevent circular inclusions */
+#define XSRIO_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/*
+ * Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit.
+ */
+/** @name Device registers
+ * @{
+ */
+
+/**
+ * Capability Address Register Space 0x00-0x3C Resisters
+ */
+#define XSRIO_DEV_ID_CAR_OFFSET 0x00 /**< Device Identity CAR */
+#define XSRIO_DEV_INFO_CAR_OFFSET 0x04 /**< Device Information CAR */
+#define XSRIO_ASM_ID_CAR_OFFSET 0x08 /**< Assembly Identity CAR */
+#define XSRIO_ASM_INFO_CAR_OFFSET 0x0C /**< Assembly Information CAR */
+#define XSRIO_PEF_CAR_OFFSET 0x10 /**< Processing Element
+ * Features CAR
+ */
+#define XSRIO_SWP_INFO_CAR_OFFSET 0x14 /**< Switch Port Information CAR */
+#define XSRIO_SRC_OPS_CAR_OFFSET 0x18 /**< Source operations CAR */
+#define XSRIO_DST_OPS_CAR_OFFSET 0x1c /**< Destination operations CAR */
+
+/**
+ * Command and Status Register Space 0x040-0xFC Registers
+ */
+#define XSRIO_PELL_CTRL_CSR_OFFSET 0x4c /**< PE Logical layer
+ * Control CSR
+ */
+#define XSRIO_LCS0_BASEADDR_CSR_OFFSET 0x58 /**< Local Configuration
+ * Space 0 Base Address CSR
+ */
+#define XSRIO_LCS1_BASEADDR_CSR_OFFSET 0x5c /**< Local Configuration
+ * Space 1 Base Address CSR
+ */
+#define XSRIO_BASE_DID_CSR_OFFSET 0x60 /**< Base Device ID CSR */
+#define XSRIO_HOST_DID_LOCK_CSR_OFFSET 0x68 /**< Host Base Device ID
+ * Lock CSR
+ */
+#define XSRIO_COMPONENT_TAG_CSR_OFFSET 0x6c /**< Component Tag CSR */
+
+/**
+ * Extended Feature Register Space 0x0100-0xFFFC Registers
+ */
+#define XSRIO_EFB_HEADER_OFFSET 0x100 /**< Extended features LP Serial
+ * Register Block Header
+ */
+#define XSRIO_PORT_TOUT_CSR_OFFSET 0x120 /**< Port Link Timeout CSR */
+#define XSRIO_RSP_TOUT_CSR_OFFSET 0x124 /**< Port Response Timeout CSR */
+#define XSRIO_GEN_CTL_CSR_OFFSET 0x13c /**< General Control CSR */
+#define XSRIO_PORT_N_MNT_REQ_CSR_OFFSET 0x140 /**< Port n Link Maintenance
+ * Request CSR
+ */
+#define XSRIO_PORT_N_MNT_RES_CSR_OFFSET 0X144 /**< Port n Maintenance
+ * Response CSR
+ */
+#define XSRIO_PORT_N_ACKID_CSR_OFFSET 0x148 /**< Port n Local Ack ID CSR */
+#define XSRIO_PORT_N_ERR_STS_CSR_OFFSET 0x158 /**< Port n Error and
+ * Status CSR
+ */
+#define XSRIO_PORT_N_CTL_CSR_OFFSET 0x15c /**< Port n Control CSR */
+#define XSRIO_EFB_LPSL_OFFSET 0x0400 /**< LP-Serial Lane Extended
+ * Features offset
+ */
+#define XSRIO_SL_HEADER_OFFSET 0x00 /**< Serial Lane Block Header */
+#define XSRIO_SLS0_CSR_OFFSET(x) (0x10 + x*0x20)
+ /**< Serial Lane N
+ * Status 0 CSR
+ */
+#define XSRIO_SLS1_CSR_OFFSET(x) (0x14 + x*0x20)
+ /**< Serial Lane N
+ * Status 1 CSR
+ */
+/**
+ * Implementation Defined Space 0x010000 - 0xFFFFFC Registers
+ */
+#define XSRIO_IMP_WCSR_OFFSET 0x10000 /**< Water Mark CSR */
+#define XSRIO_IMP_BCSR_OFFSET 0x10004 /**< Buffer Control CSR */
+#define XSRIO_IMP_MRIR_OFFSET 0x10100 /**< Maintenace Request
+ * Information Register
+ */
+
+/*@}*/
+
+/** @name Device Identity CAR bit definitions.
+ * These bits are associated with the XSRIO_DEV_ID_CAR_OFFSET register.
+ * @{
+ */
+#define XSRIO_DEV_ID_DEVID_CAR_MASK 0xFFFF0000 /**< Device ID Mask */
+#define XSRIO_DEV_ID_VDRID_CAR_MASK 0x0000FFFF /**< Device Vendor ID Mask */
+
+#define XSRIO_DEV_ID_DEVID_CAR_SHIFT 16 /**< Device ID shift */
+/*@}*/
+
+/** @name Device Inforamtion CAR bit definitions.
+ * These bits are associated with the XSRIO_DEV_INFO_CAR_OFFSET register.
+ * @{
+ */
+#define XSRIO_DEV_INFO_PATCH_CAR_MASK 0x0000000F /**< Patch Mask */
+#define XSRIO_DEV_INFO_MINREV_CAR_MASK 0x000000F0 /**< Minor Revision Mask */
+#define XSRIO_DEV_INFO_MAJREV_CAR_MASK 0x00000F00 /**< Major Revision Mask */
+#define XSRIO_DEV_INFO_DREV_CAR_MASK 0x000F0000 /**< Device Revision
+ * Lable Mask
+ */
+/*@}*/
+
+/** @name Assembly Identity CAR bit definitions.
+ * These bits are associated with the XSRIO_ASM_ID_CAR_OFFSET register.
+ * @{
+ */
+#define XSRIO_ASM_ID_ASMID_CAR_MASK 0xFFFF0000 /**< Assembly ID Mask */
+#define XSRIO_ASM_ID_ASMVID_CAR_MASK 0x0000FFFF /**< Assembly Vendor ID Mask */
+
+#define XSRIO_ASM_ID_ASMID_CAR_SHIFT 16 /**< Assembly ID Shift */
+/*@}*/
+
+/** @name Assembly Device Information CAR bit definitions.
+ * These bits are associated with the XSRIO_ASM_INFO_CAR_OFFSET register.
+ * @{
+ */
+#define XSRIO_ASM_INFO_ASR_CAR_MASK 0xFFFF0000 /**< Assembly Revision Mask */
+#define XSRIO_ASM_INFO_EFP_CAR_MASK 0x0000FFFF /**< Extended Features
+ * Pointer Mask
+ */
+
+#define XSRIO_ASM_INFO_ASR_CAR_SHIFT 16 /**< Assembly Revision Shift */
+/*@}*/
+
+/** @name Processing Element Features CAR bit definitions.
+ * These bits are associated with the XSRIO_PEF_CAR_OFFSET register.
+ * @{
+ */
+#define XSRIO_PEF_EAS_CAR_MASK 0x00000007 /**< Extended Addressing
+ * Support Mask
+ */
+#define XSRIO_PEF_EF_CAR_MASK 0x00000008 /**< Extended Features Mask */
+#define XSRIO_PEF_CTS_CAR_MASK 0x00000010 /**< Common Transport Large
+ * System support Mask
+ */
+#define XSRIO_PEF_CRF_CAR_MASK 0x00000020 /**< CRF Support Mask */
+#define XSRIO_PEF_MPORT_CAR_MASK 0x08000000 /**< Multi Port Mask */
+#define XSRIO_PEF_SWITCH_CAR_MASK 0x10000000 /**< Switch Mask */
+#define XSRIO_PEF_PROCESSOR_CAR_MASK 0x20000000 /**< Processor Mask */
+#define XSRIO_PEF_MEMORY_CAR_MASK 0x40000000 /**< Memory Mask */
+#define XSRIO_PEF_BRIDGE_CAR_MASK 0x80000000 /**< Bridge Mask */
+/*@}*/
+
+/** @name Source Operations CAR bit definitions.
+ * These bits are associated with the XSRIO_SRC_OPS_CAR_OFFSET
+ * register and XSRIO_DST_OPS_CAR register.
+ * @{
+ */
+#define XSRIO_SRCDST_OPS_PORT_WRITE_CAR_MASK 0x00000004 /**< Port write
+ * operation Mask
+ */
+#define XSRIO_SRCDST_OPS_ATOMIC_SWP_CAR_MASK 0x00000008 /**< Atomic Swap
+ * Mask
+ */
+#define XSRIO_SRCDST_OPS_ATOMIC_CLR_CAR_MASK 0x00000010 /**< Atomic Clear
+ * Mask
+ */
+#define XSRIO_SRCDST_OPS_ATOMIC_SET_CAR_MASK 0x00000020 /**< Atomic Set
+ * Mask
+ */
+#define XSRIO_SRCDST_OPS_ATOMIC_DCR_CAR_MASK 0x00000040 /**< Atomic
+ * Decrement Mask
+ */
+#define XSRIO_SRCDST_OPS_ATOMIC_INCR_CAR_MASK 0x00000080 /**< Atomic
+ * Increment Mask
+ */
+#define XSRIO_SRCDST_OPS_ATOMIC_TSWP_CAR_MASK 0x00000100 /**< Atomic test
+ * and swap Mask
+ */
+#define XSRIO_SRCDST_OPS_ATIOMIC_CSWP_CAR_MASK 0x00000200 /**< Atomic compare
+ * and Swap Mask
+ */
+#define XSRIO_SRCDST_OPS_DOORBELL_CAR_MASK 0x00000400 /**< Doorbell Mask */
+#define XSRIO_SRCDST_OPS_DATA_MSG_CAR_MASK 0x00000800 /**< Data Message
+ * Mask
+ */
+#define XSRIO_SRCDST_OPS_WRITE_RESPONSE_CAR_MASK 0x00001000 /**< Write with
+ * Response Mask
+ */
+#define XSRIO_SRCDST_OPS_SWRITE_CAR_MASK 0x00002000 /**< Streaming
+ * Write Mask
+ */
+#define XSRIO_SRCDST_OPS_WRITE_CAR_MASK 0x00004000 /**< Write Mask */
+#define XSRIO_SRCDST_OPS_READ_CAR_MASK 0x00008000 /**< Read Mask */
+/*@}*/
+
+/** @name PE Logical layer Control CSR bit definitions.
+ * These bits are associated with the XSRIO_PELL_CTRL_CSR_OFFSET register.
+ * @{
+ */
+#define XSRIO_PELL_CTRL_EAC_CSR_MASK 0x00000007 /**< Extended Addressing
+ * Control Mask
+ */
+/*@}*/
+
+/** @name Local Configuration Space Base Address 1 CSR bit definitions.
+ * These bits are associated with the XSRIO_LCS1_BASEADDR_CSR_OFFSET register.
+ * @{
+ */
+#define XSRIO_LCS1_BASEADDR_LCSBA_CSR_MASK 0x7FE00000 /**< LCSBA Mask */
+#define XSRIO_LCS1_BASEADDR_LCSBA_CSR_SHIFT 21 /**< LCSBA Shift */
+/*@}*/
+
+/** @name Base Device ID CSR bit definitions.
+ * These bits are associated with the XSRIO_BASE_DID_CSR_OFFSET register.
+ * @{
+ */
+#define XSRIO_BASE_DID_LBDID_CSR_MASK 0x0000FFFF /**< Large Base Device ID
+ * Mask(16-bit device ID)
+ */
+#define XSRIO_BASI_DID_BDID_CSR_MASK 0x00FF0000 /**< Base Device ID
+ * Mask(8-bit device ID)
+ */
+#define XSRIO_BASI_DID_BDID_CSR_SHIFT 16 /**< Base Device ID Shift */
+/*@}*/
+
+/** @name Host Base Device ID CSR bit definitions.
+ * These bits are associated with the XSRIO_HOST_DID_LOCK_CSR_OFFSET register.
+ * @{
+ */
+#define XSRIO_HOST_DID_LOCK_HBDID_CSR_MASK 0x0000FFFF /**< Host Base
+ * Device ID Mask
+ */
+/*@}*/
+
+/** @name LP - Serial Register Block header bit definitions.
+ * These bits are associated with the XSRIO_EFB_HEADER_OFFSET register.
+ * @{
+ */
+#define XSRIO_EFB_HEADER_EFID_MASK 0x0000FFFF /**< Extended Features ID
+ * Mask
+ */
+#define XSRIO_EFB_HEADER_EFP_MASK 0xFFFF0000 /**< Extended Features
+ * Pointer Mask
+ */
+#define XSRIO_EFB_HEADER_EFP_SHIFT 16 /**< Extended Features
+ * Pointer Shift
+ */
+/*@}*/
+
+/** @name Port Link timeout value CSR bit definitions.
+ * These bits are associated with the XSRIO_PORT_TOUT_CSR_OFFSET register.
+ * @{
+ */
+#define XSRIO_PORT_TOUT_TOUTVAL_CSR_MASK 0xFFFFFF00 /**< Timeout Value Mask */
+#define XSRIO_PORT_TOUT_TOUTVAL_CSR_SHIFT 8 /**< Timeout Value Shift */
+/*@}*/
+
+/** @name Port response timeout value CSR bit definitions.
+ * These bits are associated with the XSRIO_RSP_TOUT_CSR_OFFSET register.
+ * @{
+ */
+#define XSRIO_RSP_TOUT_TOUTVAL_CSR_MASK 0xFFFFFF00 /**< Response Timeout
+ * Value Mask
+ */
+#define XSRIO_RSP_TOUT_TOUTVAL_CSR_SHIFT 8 /**< Response Timeout Shift */
+/*@}*/
+
+/** @name Port General Control CSR bit definitions.
+ * These bits are associated with the XSRIO_GEN_CTL_CSR_OFFSET register.
+ * @{
+ */
+#define XSRIO_GEN_CTL_DISCOVERED_CSR_MASK 0x20000000 /**< Discovered Mask */
+#define XSRIO_GEN_CTL_MENABLE_CSR_MASK 0x40000000 /**< Master Enable Mask */
+#define XSRIO_GEN_CTL_HOST_CSR_MASK 0x80000000 /**< Host Mask */
+
+/*@}*/
+
+/** @name Port n maintenance request CSR bit definitions.
+ * These bits are associated with the XSRIO_PORT_N_MNT_REQ_CSR_OFFSET register.
+ * @{
+ */
+#define XSRIO_PORT_N_MNT_REQ_CMD_CSR_MASK 0x00000007 /**< Command Mask */
+/*@}*/
+
+/** @name Port n maintenance response CSR bit definitions.
+ * These bits are associated with the XSRIO_PORT_N_MNT_RES_CSR_OFFSET register.
+ * @{
+ */
+#define XSRIO_PORT_N_MNT_RES_LS_CSR_MASK 0x0000001F /**< link status Mask */
+#define XSRIO_PORT_N_MNT_RES_ACKS_CSR_MASK 0x000007E0 /**< Ack ID status
+ * Mask
+ */
+#define XSRIO_PORT_N_MNT_RES_RVALID_CSR_MASK 0x80000000 /**< Response Valid
+ * Mask
+ */
+/*@}*/
+
+/** @name Port n local ack ID CSR bit definitions.
+ * These bits are associated with the XSRIO_PORT_N_ACKID_CSR_OFFSET register.
+ * @{
+ */
+#define XSRIO_PORT_N_ACKID_OBACKID_CSR_MASK 0x0000003F /**< Out bound
+ * ACK ID Mask
+ */
+#define XSRIO_PORT_N_ACKID_OSACKID_CSR_MASK 0x00003F00 /**< Out Standing
+ * ACK ID Mask
+ */
+#define XSRIO_PORT_N_ACKID_IBACKID_CSR_MASK 0x3F000000 /**< In bound
+ * ACK ID Mask
+ */
+#define XSRIO_PORT_N_ACKID_CLSACKID_CSR_MASK 0x80000000 /**< Clear
+ * Outstanding
+ * ACK ID Mask
+ */
+#define XSRIO_PORT_N_ACKID_RESET_OBACKID_CSR_MASK 0xFFFFFFC0 /**< Out bound ACK
+ * ID Reset Mask
+ */
+#define XSRIO_PORT_N_ACKID_RESET_IBACKID_CSR_MASK 0xC0FFFFFF /**< In bound ACK
+ * ID Reset Mask
+ */
+#define XSRIO_PORT_N_ACKID_IBACKID_CSR_SHIFT 24 /**< In bound
+ * ACK ID shift
+ */
+/*@}*/
+
+/** @name Port n Error and Status CSR bit definitions.
+ * These bits are associated with the XSRIO_PORT_N_ERR_STS_CSR_OFFSET register.
+ * @{
+ */
+#define XSRIO_PORT_N_ERR_STS_PUINT_CSR_MASK 0x00000001 /**< Port
+ * un-initialized Mask
+ */
+#define XSRIO_PORT_N_ERR_STS_POK_CSR_MASK 0x00000002 /**< Port Ok Mask */
+#define XSRIO_PORT_N_ERR_STS_PERR_CSR_MASK 0x00000004 /**< Port Error Mask */
+#define XSRIO_PORT_N_ERR_STS_IERRS_CSR_MASK 0x00000100 /**< Input Error
+ * stopped Mask
+ */
+#define XSRIO_PORT_N_ERR_STS_IERRE_CSR_MASK 0x00000200 /**< Input Error
+ * encountered Mask
+ */
+#define XSRIO_PORT_N_ERR_STS_IRTS_CSR_MASK 0x00000400 /**< Input Retry
+ * Stopped Mask
+ */
+#define XSRIO_PORT_N_ERR_STS_OERRS_CSR_MASK 0x00010000 /**< Output error
+ * Stopped Mask
+ */
+#define XSRIO_PORT_N_ERR_STS_OERRE_CSR_MASK 0x00020000 /**< Output error
+ * encountered Mask
+ */
+#define XSRIO_PORT_N_ERR_STS_ORTS_CSR_MASK 0x00040000 /**< Output Retry
+ * Stopped Mask
+ */
+#define XSRIO_PORT_N_ERR_STS_OR_CSR_MASK 0x00080000 /**< Output
+ * Retried Mask
+ */
+#define XSRIO_PORT_N_ERR_STS_ORE_CSR_MASK 0x00100000 /**< Output Retry
+ * Encountered Mask
+ */
+#define XSRIO_PORT_N_ERR_STS_FLOWCNTL_CSR_MASK 0x08000000 /**< Flow Control
+ * Mode Mask
+ */
+#define XSRIO_PORT_N_ERR_STS_IDL_SEQ_CSR_MASK 0x20000000 /**< Idle sequence
+ * Mask
+ */
+#define XSRIO_PORT_N_ERR_STS_IDL_SEQE_CSR_MASK 0x40000000 /**< Idle sequence 2
+ * Enable Mask
+ */
+#define XSRIO_PORT_N_ERR_STS_IDL_SEQS_CSR_MASK 0x80000000 /**< Idle sequence 2
+ * support Mask
+ */
+#define XSRIO_PORT_N_ERR_STS_ERR_ALL_CSR_MASK 0x001FFF07 /**< Port Errors Mask */
+/*@}*/
+
+/** @name Port n Control CSR bit definitions.
+ * These bits are associated with the XSRIO_PORT_N_CTL_CSR_OFFSET register.
+ * @{
+ */
+#define XSRIO_PORT_N_CTL_PTYPE_CSR_MASK 0x00000001 /**< Port Type Mask */
+#define XSRIO_PORT_N_CTL_EPWDS_CSR_MASK 0x00003000 /**< Extended Port
+ * Width Support Mask
+ */
+#define XSRIO_PORT_N_CTL_EPWOR_CSR_MASK 0x0000C000 /**< Extended Port
+ * Width Override Mask
+ */
+#define XSRIO_PORT_N_CTL_ENUMB_CSR_MASK 0x00020000 /**< Enumeration
+ * Boundary Mask
+ */
+#define XSRIO_PORT_N_CTL_MCENT_CSR_MASK 0x00080000 /**< Multi-cast Event
+ * Participant Mask
+ */
+#define XSRIO_PORT_N_CTL_ERRD_CSR_MASK 0x00100000 /**< Error Checking
+ * Disable Mask
+ */
+#define XSRIO_PORT_N_CTL_IPE_CSR_MASK 0x00200000 /**< Input port
+ * enable Mask
+ */
+#define XSRIO_PORT_N_CTL_OPE_CSR_MASK 0x00400000 /**< Output port
+ * enable Mask
+ */
+#define XSRIO_PORT_N_CTL_PD_CSR_MASK 0x00800000 /**< Output port
+ * disable Mask
+ */
+#define XSRIO_PORT_N_CTL_PWO_CSR_MASK 0x07000000 /**< Port width
+ * Override Mask
+ */
+#define XSRIO_PORT_N_CTL_RESET_PWO_CSR_MASK 0xF8FFFFFF /**< Port wdith
+ * Override Reset Mask
+ */
+#define XSRIO_PORT_N_CTL_IPW_CSR_MASK 0x38000000 /**< Initialized
+ * Port width Mask
+ */
+#define XSRIO_PORT_N_CTL_PW_CSR_MASK 0xc0000000 /**< Port width Mask */
+#define XSRIO_PORT_N_CTRL_CSR_STATUS_ALL_MASK 0x00F00000 /**< Port Status All
+ * Mask
+ */
+
+#define XSRIO_PORT_N_CTL_PWO_CSR_SHIFT 24 /**< Port width
+ * Override Shift
+ */
+#define XSRIO_PORT_N_CTL_PW_CSR_SHIFT 30 /**< Port width
+ * Shift
+ */
+/*@}*/
+
+/** @name LP -Serial Lane Register Block Header bit definitions.
+ * These bits are associated with the XSRIO_SL_HEADER_OFFSET register.
+ * @{
+ */
+#define XSRIO_SL_HEADER_EFID_MASK 0x0000FFFF /**< Extended
+ * Features ID Mask
+ */
+#define XSRIO_SL_HEADER_EFP_MASK 0xFFFF0000 /**< Extended Features
+ * Pointer Mask
+ */
+#define XSRIO_SL_HEADER_EFP_SHIFT 16 /**< Extended Features
+ * Pointer Shift
+ */
+/*@}*/
+
+/** @name LP -Seral Lane n Status 0 CSRS bit definitions.
+ * These bits are associated with the XSRIO_SLS0_CSR(x) register.
+ * @{
+ */
+#define XSRIO_SLS0_CSR_PORT_NUM_MASK 0xFF000000 /**< Port Number Mask */
+#define XSRIO_SLS0_CSR_LANE_NUM_MASK 0x00F00000 /**< Lane Number Mask */
+#define XSRIO_SLS0_CSR_TRANSMIT_TYPE_MASK 0x00080000 /**< Transmitter
+ * Type Mask
+ */
+#define XSRIO_SLS0_CSR_TRANSMIT_MODE_MASK 0x00040000 /**< Transmitter
+ * Mode Mask
+ */
+#define XSRIO_SLS0_CSR_RCV_INPUT_INV_MASK 0x00008000 /**< Receiver Input
+ * Inverted Mask
+ */
+#define XSRIO_SLS0_CSR_RCV_TRAINED_MASK 0x00004000 /**< Receiver
+ * Trained Mask
+ */
+#define XSRIO_SLS0_CSR_RCVLANE_SYNC_MASK 0x00002000 /**< Receive Lane
+ * Sync Mask
+ */
+#define XSRIO_SLS0_CSR_RCVLANE_RDY_MASK 0x00001000 /**< Receive Lane
+ * Ready Mask
+ */
+#define XSRIO_SLS0_CSR_DECODING_ERRORS_MASK 0x00000F00 /**< 8B/10B Decoding
+ * errors Mask
+ */
+#define XSRIO_SLS0_CSR_LANESYNC_CHAN_MASK 0x00000080 /**< lane_sync state
+ * change Mask
+ */
+#define XSRIO_SLS0_CSR_RCVTRAINED_CHAN_MASK 0x00000040 /**< rcvr_train state
+ * changed Mask
+ */
+#define XSRIO_SLS0_CSR_STAT1_IMP_MASK 0x00000008 /**< Status 1 CSR
+ * Implemented Mask
+ */
+#define XSRIO_SLS0_CSR_DECODING_ERRORS_SHIFT 8
+/*@}*/
+
+/** @name LP -Seral Lane n Status 1 CSRS bit definitions.
+ * These bits are associated with the XSRIO_SLS1_CSR(x) register.
+ * @{
+ */
+
+#define XSRIO_SLS1_CSR_SCRDSCR_EN_MASK 0x00008000 /**< Connected port
+ * Scrambling/Descrambling
+ * Enabled Mask
+ */
+#define XSRIO_SLS1_CSR_CPTEIS_MASK 0x00030000 /**< Connected port transmit
+ * Emphasis Tap(+1) Status
+ * Mask
+ */
+#define XSRIO_SLS1_CSR_CPTEDS_MASK 0x000C0000 /**< Connected port transmit
+ * Emphasis Tap(-1) Status
+ * Mask
+ */
+#define XSRIO_SLS1_CSR_LANENUM_MASK 0x00F00000 /**< Lane number within
+ * connected port
+ */
+#define XSRIO_SLS1_CSR_RXPORT_WIDTH_MASK 0x07000000 /**< Receive port width
+ * Mask
+ */
+#define XSRIO_SLS1_CSR_CPLR_TRAINED_MASK 0x08000000 /**< Connected port lane
+ * Receiver trained Mask
+ */
+#define XSRIO_SLS1_CSR_IMPDEFINED_MASK 0x10000000 /**< Implementation defined
+ * Mask
+ */
+#define XSRIO_SLS1_CSR_VALCHANGED_MASK 0x20000000 /**< Values Changed Mask */
+#define XSRIO_SLS1_CSR_IDLE2_INFO_MASK 0x40000000 /**< IDLE2 Information
+ * Current Mask
+ */
+#define XSRIO_SLS1_CSR_IDLE2_REC_MASK 0x80000000 /**< IDLE2 Received Mask */
+/*@}*/
+
+/** @name Water Mark CSRS bit definitions.
+ * These bits are associated with the XSRIO_IMP_WCSR_OFFSET register.
+ * @{
+ */
+
+#define XSRIO_IMP_WCSR_WM2_MASK 0x003F0000 /**< Water Mark 2 Mask */
+#define XSRIO_IMP_WCSR_WM1_MASK 0x00003F00 /**< Water Mark 1 Mask */
+#define XSRIO_IMP_WCSR_WM0_MASK 0x0000003F /**< Water Mark 0 Mask */
+#define XSRIO_IMP_WCSR_RESET_WM0_MASK 0xFFFFFFC0 /**< Water Mark 0 ResetMask */
+#define XSRIO_IMP_WCSR_RESET_WM1_MASK 0xFFFFC0FF /**< Water Mark 1 ResetMask */
+#define XSRIO_IMP_WCSR_RESET_WM2_MASK 0xFFC0FFFF /**< Water Mark 2 ResetMask */
+
+#define XSRIO_IMP_WCSR_WM1_SHIFT 8 /**< Water Mark 1 Shift */
+#define XSRIO_IMP_WCSR_WM2_SHIFT 16 /**< Water Mark 2 Shift */
+/*@}*/
+
+/** @name Buffer Control CSRS bit definitions.
+ * These bits are associated with the XSRIO_IMP_BCSR_OFFSET register.
+ * @{
+ */
+#define XSRIO_IMP_BCSR_RXFLOW_CNTLONLY_MASK 0x80000000 /**< Rx Flow Control
+ * Only Mask
+ */
+#define XSRIO_IMP_BCSR_UNIFIED_CLK_MASK 0x40000000 /**< Buffer Control
+ * Mask
+ */
+#define XSRIO_IMP_BCSR_TX_FLOW_CNTL_MASK 0x20000000 /**< Tx Flow
+ * Control Mask
+ */
+#define XSRIO_IMP_BCSR_TXREQ_REORDER_MASK 0x10000000 /**< Tx Request
+ * Reorder Mask */
+#define XSRIO_IMP_BCSR_TXSIZE_MASK 0x07FF0000 /**< Tx size Mask */
+#define XSRIO_IMP_BCSR_FRX_FLOW_CNTL_MASK 0x00008000 /**< Force Rx flow
+ * Control Mask
+ */
+#define XSRIO_IMP_BCSR_RXSIZE_MASK 0x000000FF /**< Rx size Mask */
+#define XSRIO_IMP_BCSR_TXSIZE_SHIFT 16 /**< Tx size shift */
+/*@}*/
+
+/** @name Maintenance Request Information Register bit definitions.
+ * These bits are associated with the XSRIO_IMP_MRIR_OFFSET register.
+ * @{
+ */
+#define XSRIO_IMP_MRIR_REQ_TID_MASK 0xFF000000 /**< Request TID Mask */
+#define XSRIO_IMP_MRIR_REQ_PRIO_MASK 0x00060000 /**< Request Priority Mask */
+#define XSRIO_IMP_MRIR_REQ_CRF_MASK 0x00010000 /**< Request CRF Mask */
+#define XSRIO_IMP_MRIR_REQ_DESTID_MASK 0x0000FFFF /**< Request Destination
+ * ID Mask
+ */
+#define XSRIO_IMP_MRIR_RST_REQ_DESTID_MASK 0xFFFF0000
+#define XSRIO_IMP_MRIR_RST_REQ_PRIO_MASK 0xFFF9FFFF
+#define XSRIO_IMP_MRIR_REQ_RST_TID_MASK 0x00FFFFFF
+#define XSRIO_IMP_MRIR_REQ_PRIO_SHIFT 17
+#define XSRIO_IMP_MRIR_REQ_CRF_SHIFT 16
+#define XSRIO_IMP_MRIR_REQ_TID_SHIFT 24
+
+/*@}*/
+
+/****************** Macros (Inline Functions) Definitions ********************/
+/*****************************************************************************/
+/**
+* Macro to read register.
+*
+* @param BaseAddress is the base address of the SRIO
+* @param RegOffset is the register offset.
+*
+* @return Value of the register.
+*
+* @note C-style signature:
+* u32 XSrio_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+******************************************************************************/
+#define XSrio_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+
+/*****************************************************************************/
+/**
+* Macro to write register.
+*
+* @param BaseAddress is the base address of the SRIO.
+* @param RegOffset is the register offset.
+* @param Data is the data to write.
+*
+* @return None
+*
+* @note C-style signature:
+* void XSRIO_WriteReg(u32 BaseAddress, u32 RegOffset,
+* u32 Data)
+*
+******************************************************************************/
+#define XSrio_WriteReg(BaseAddress, RegOffset, Data) \
+ Xil_Out32((BaseAddress) + (RegOffset), (Data))
+/*************************** Variable Definitions ****************************/
+
+/*************************** Function Prototypes *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+
diff --git a/XilinxProcessorIPLib/drivers/srio/src/xsrio_sinit.c b/XilinxProcessorIPLib/drivers/srio/src/xsrio_sinit.c
new file mode 100755
index 00000000..92296b4e
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/srio/src/xsrio_sinit.c
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+* (c) Copyright 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsrio_sinit.c
+*
+* This file contains static Initialization functionality for Xilinx SRIO Gen2
+* Core driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 adk 16/04/14 Initial release.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xsrio.h"
+
+/*****************************************************************************/
+/**
+ * Looks up the device configuration based on the unique device ID. The table
+ * XSrio_ConfigTable contains the configuration info for each device in the
+ * system.
+ *
+ * @param DeviceId is the unique device ID of the device to lookup for
+ *
+ * @return
+ * The configuration structure for the device. If the device ID is
+ * not found,a NULL pointer is returned.
+ *
+ * @note None
+ *
+ ******************************************************************************/
+XSrio_Config *XSrio_LookupConfig(u32 DeviceId)
+{
+ extern XSrio_Config XSrio_ConfigTable[];
+ XSrio_Config *CfgPtr;
+ u32 Index;
+
+ CfgPtr = NULL;
+
+ for (Index = 0; Index < XPAR_XSRIO_NUM_INSTANCES; Index++) {
+ if (XSrio_ConfigTable[Index].DeviceId == DeviceId) {
+
+ CfgPtr = &XSrio_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}