diff --git a/XilinxProcessorIPLib/drivers/scugic/src/xscugic.c b/XilinxProcessorIPLib/drivers/scugic/src/xscugic.c index f6c5b0c4..8763d9b4 100755 --- a/XilinxProcessorIPLib/drivers/scugic/src/xscugic.c +++ b/XilinxProcessorIPLib/drivers/scugic/src/xscugic.c @@ -75,11 +75,10 @@ ******************************************************************************/ /***************************** Include Files *********************************/ -#include "xparameters.h" #include "xil_types.h" #include "xil_assert.h" #include "xscugic.h" - +#include "xparameters.h" /************************** Constant Definitions *****************************/ @@ -98,7 +97,7 @@ static void StubHandler(void *CallBackRef); /*****************************************************************************/ /** * -* DistInit initializes the distributor of the GIC. The +* DistributorInit initializes the distributor of the GIC. The * initialization entails: * * - Write the trigger mode, priority and target CPU @@ -113,9 +112,10 @@ static void StubHandler(void *CallBackRef); * @note None. * ******************************************************************************/ -static void DistInit(XScuGic *InstancePtr, u32 CpuID) +static void DistributorInit(XScuGic *InstancePtr, u32 CpuID) { u32 Int_Id; + u32 LocalCpuID = CpuID; #if USE_AMP==1 #warning "Building GIC for AMP" @@ -127,8 +127,8 @@ static void DistInit(XScuGic *InstancePtr, u32 CpuID) */ return; #endif - - XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0UL); + Xil_AssertVoid(InstancePtr != NULL); + XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U); /* * Set the security domains in the int_security registers for @@ -145,19 +145,19 @@ static void DistInit(XScuGic *InstancePtr, u32 CpuID) * 1. The trigger mode in the int_config register * Only write to the SPI interrupts, so start at 32 */ - for (Int_Id = 32; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id+=16) { + for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+16U) { /* * Each INT_ID uses two bits, or 16 INT_ID per register * Set them all to be level sensitive, active HIGH. */ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), - 0UL); + 0U); } -#define DEFAULT_PRIORITY 0xa0a0a0a0UL - for (Int_Id = 0; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id+=4) { +#define DEFAULT_PRIORITY 0xa0a0a0a0U + for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+4U) { /* * 2. The priority using int the priority_level register * The priority_level and spi_target registers use one byte per @@ -169,27 +169,27 @@ static void DistInit(XScuGic *InstancePtr, u32 CpuID) DEFAULT_PRIORITY); } - for (Int_Id = 32; Int_IdConfig = ConfigPtr; - for (Int_Id = 0; Int_IdConfig->HandlerTable[Int_Id].Handler == 0)) { + if ((InstancePtr->Config->HandlerTable[Int_Id].Handler == NULL)) { InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler; } @@ -304,8 +304,8 @@ int XScuGic_CfgInitialize(XScuGic *InstancePtr, InstancePtr; } - DistInit(InstancePtr, Cpu_Id); - CPUInit(InstancePtr); + DistributorInit(InstancePtr, Cpu_Id); + CPUInitialize(InstancePtr); InstancePtr->IsReady = XIL_COMPONENT_IS_READY; } @@ -338,7 +338,7 @@ int XScuGic_CfgInitialize(XScuGic *InstancePtr, * that was previously connected. * ****************************************************************************/ -int XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, +s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, Xil_InterruptHandler Handler, void *CallBackRef) { /* @@ -390,15 +390,15 @@ void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id) * The Int_Id is used to create the appropriate mask for the * desired bit position. Int_Id currently limited to 0 - 31 */ - Mask = 0x00000001 << (Int_Id % 32); + Mask = 0x00000001U << (Int_Id % 32U); /* * Disable the interrupt such that it won't occur while disconnecting * the handler, only disable the specified interrupt id without modifying * the other interrupt ids */ - XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DISABLE_OFFSET + - ((Int_Id / 32) * 4), Mask); + XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET + + ((Int_Id / 32U) * 4U), Mask); /* * Disconnect the handler and connect a stub, the callback reference @@ -440,14 +440,14 @@ void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id) * The Int_Id is used to create the appropriate mask for the * desired bit position. Int_Id currently limited to 0 - 31 */ - Mask = 0x00000001 << (Int_Id % 32); + Mask = 0x00000001U << (Int_Id % 32U); /* * Enable the selected interrupt source by setting the * corresponding bit in the Enable Set register. */ - XScuGic_DistWriteReg(InstancePtr, XSCUGIC_ENABLE_SET_OFFSET + - ((Int_Id / 32) * 4), Mask); + XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET + + ((Int_Id / 32U) * 4U), Mask); } /*****************************************************************************/ @@ -482,14 +482,14 @@ void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id) * The Int_Id is used to create the appropriate mask for the * desired bit position. Int_Id currently limited to 0 - 31 */ - Mask = 0x00000001 << (Int_Id % 32); + Mask = 0x00000001U << (Int_Id % 32U); /* * Disable the selected interrupt source by setting the * corresponding bit in the IDR. */ - XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DISABLE_OFFSET + - ((Int_Id / 32) * 4), Mask); + XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET + + ((Int_Id / 32U) * 4U), Mask); } /*****************************************************************************/ @@ -513,7 +513,7 @@ void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id) * @note None. * ******************************************************************************/ -int XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id) +s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id) { u32 Mask; @@ -522,8 +522,8 @@ int XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id) */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Int_Id <= 15) ; - Xil_AssertNonvoid(Cpu_Id <= 255) ; + Xil_AssertNonvoid(Int_Id <= 15U) ; + Xil_AssertNonvoid(Cpu_Id <= 255U) ; /* @@ -531,7 +531,7 @@ int XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id) * desired interrupt. Int_Id currently limited to 0 - 15 * Use the target list for the Cpu ID. */ - Mask = ((Cpu_Id << 16) | Int_Id) & + Mask = ((Cpu_Id << 16U) | Int_Id) & (XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK); /* @@ -567,7 +567,7 @@ static void StubHandler(void *CallBackRef) { /* * Indicate another unhandled interrupt for stats */ - ((XScuGic *)CallBackRef)->UnhandledInterrupts++; + ((XScuGic *)((void *)CallBackRef))->UnhandledInterrupts++; } /****************************************************************************/ @@ -599,12 +599,14 @@ void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, u8 Priority, u8 Trigger) { u32 RegValue; + u8 LocalPriority; + LocalPriority = Priority; Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); - Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK); - Xil_AssertVoid(Priority <= XSCUGIC_MAX_INTR_PRIO_VAL); + Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK); + Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL); /* * Determine the register to write to using the Int_Id. @@ -618,13 +620,13 @@ void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc. * The lower order 3 bits are masked before putting it in the register. */ - Priority = Priority & XSCUGIC_INTR_PRIO_MASK; + LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK; /* * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4)*8)); - RegValue |= Priority << ((Int_Id%4)*8); + RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U)); + RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U); /* * Write the value back to the register. @@ -642,8 +644,8 @@ void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16)*2)); - RegValue |= Trigger << ((Int_Id%16)*2); + RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U)); + RegValue |= (u32)Trigger << ((Int_Id%16U)*2U); /* * Write the value back to the register. @@ -690,8 +692,8 @@ void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue = RegValue >> ((Int_Id%4)*8); - *Priority = RegValue & XSCUGIC_PRIORITY_MASK; + RegValue = RegValue >> ((Int_Id%4U)*8U); + *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK); /* * Determine the register to read to using the Int_Id. @@ -703,8 +705,8 @@ void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue = RegValue >> ((Int_Id%16)*2); + RegValue = RegValue >> ((Int_Id%16U)*2U); - *Trigger = RegValue & XSCUGIC_INT_CFG_MASK; + *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK); } diff --git a/XilinxProcessorIPLib/drivers/scugic/src/xscugic.h b/XilinxProcessorIPLib/drivers/scugic/src/xscugic.h index faec7b02..70880b48 100755 --- a/XilinxProcessorIPLib/drivers/scugic/src/xscugic.h +++ b/XilinxProcessorIPLib/drivers/scugic/src/xscugic.h @@ -211,7 +211,7 @@ typedef struct *****************************************************************************/ #define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \ (XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \ - ((u32)Data))) + ((u32)(Data)))) /****************************************************************************/ /** @@ -249,7 +249,7 @@ typedef struct *****************************************************************************/ #define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \ (XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \ - ((u32)Data))) + ((u32)(Data)))) /****************************************************************************/ /** @@ -275,17 +275,17 @@ typedef struct * Required functions in xscugic.c */ -int XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, +s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, Xil_InterruptHandler Handler, void *CallBackRef); void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id); void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id); void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id); -int XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr, +s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr, u32 EffectiveAddr); -int XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id); +s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id); void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, u8 *Priority, u8 *Trigger); @@ -305,7 +305,7 @@ void XScuGic_InterruptHandler(XScuGic *InstancePtr); /* * Self-test functions in xscugic_selftest.c */ -int XScuGic_SelfTest(XScuGic *InstancePtr); +s32 XScuGic_SelfTest(XScuGic *InstancePtr); #ifdef __cplusplus } diff --git a/XilinxProcessorIPLib/drivers/scugic/src/xscugic_g.c b/XilinxProcessorIPLib/drivers/scugic/src/xscugic_g.c index 1f821b03..caf3f3db 100755 --- a/XilinxProcessorIPLib/drivers/scugic/src/xscugic_g.c +++ b/XilinxProcessorIPLib/drivers/scugic/src/xscugic_g.c @@ -85,8 +85,8 @@ XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] = { { - XPAR_SCUGIC_0_DEVICE_ID, /* Unique ID of device */ - XPAR_SCUGIC_0_CPU_BASEADDR, /* CPU Interface base address */ - XPAR_SCUGIC_0_DIST_BASEADDR /* Distributor base address */ + (u16)XPAR_SCUGIC_0_DEVICE_ID, /* Unique ID of device */ + (u32)XPAR_SCUGIC_0_CPU_BASEADDR, /* CPU Interface base address */ + (u32)XPAR_SCUGIC_0_DIST_BASEADDR /* Distributor base address */ } }; diff --git a/XilinxProcessorIPLib/drivers/scugic/src/xscugic_hw.c b/XilinxProcessorIPLib/drivers/scugic/src/xscugic_hw.c index 028cd222..d681846b 100755 --- a/XilinxProcessorIPLib/drivers/scugic/src/xscugic_hw.c +++ b/XilinxProcessorIPLib/drivers/scugic/src/xscugic_hw.c @@ -67,10 +67,10 @@ /***************************** Include Files *********************************/ -#include "xparameters.h" #include "xil_types.h" #include "xil_assert.h" #include "xscugic.h" +#include "xparameters.h" /************************** Constant Definitions *****************************/ @@ -82,11 +82,11 @@ static void DistInit(XScuGic_Config *Config, u32 CpuID); static void CPUInit(XScuGic_Config *Config); -static XScuGic_Config *LookupConfigByBaseAddress(u32 BaseAddress); +static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress); /************************** Variable Definitions *****************************/ -extern XScuGic_Config XScuGic_ConfigTable[]; +extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES]; /*****************************************************************************/ /** @@ -109,6 +109,7 @@ extern XScuGic_Config XScuGic_ConfigTable[]; static void DistInit(XScuGic_Config *Config, u32 CpuID) { u32 Int_Id; + u32 LocalCpuID = CpuID; #if USE_AMP==1 #warning "Building GIC for AMP" @@ -121,7 +122,7 @@ static void DistInit(XScuGic_Config *Config, u32 CpuID) return; #endif - XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0UL); + XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U); /* * Set the security domains in the int_security registers for non-secure @@ -138,18 +139,18 @@ static void DistInit(XScuGic_Config *Config, u32 CpuID) * 1. The trigger mode in the int_config register * Only write to the SPI interrupts, so start at 32 */ - for (Int_Id = 32; Int_IdDistBaseAddress, - XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0UL); + XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U); } -#define DEFAULT_PRIORITY 0xa0a0a0a0UL - for (Int_Id = 0; Int_IdDistBaseAddress, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), CpuID); + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), LocalCpuID); } - for (Int_Id = 0; Int_IdDistBaseAddress, - XSCUGIC_ENABLE_DISABLE_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, + XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, Int_Id), - 0xFFFFFFFFUL); + 0xFFFFFFFFU); } @@ -213,7 +214,7 @@ static void CPUInit(XScuGic_Config *Config) * register */ XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET, - 0xF0); + 0xF0U); /* * If the CPU operates in both security domains, set parameters in the @@ -233,7 +234,7 @@ static void CPUInit(XScuGic_Config *Config) * interrupts Only enable the IRQ output unless secure interrupts * are needed. */ - XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07); + XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U); } @@ -267,10 +268,10 @@ static void CPUInit(XScuGic_Config *Config) * None. * ******************************************************************************/ -int XScuGic_DeviceInitialize(u32 DeviceId) +s32 XScuGic_DeviceInitialize(u32 DeviceId) { XScuGic_Config *Config; - u8 Cpu_Id = XPAR_CPU_ID + 1; + u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1; Config = &XScuGic_ConfigTable[(u32 )DeviceId]; @@ -304,20 +305,21 @@ int XScuGic_DeviceInitialize(u32 DeviceId) void XScuGic_DeviceInterruptHandler(void *DeviceId) { - u32 IntID; + u32 InterruptID; + u32 IntIDFull; XScuGic_VectorTableEntry *TablePtr; XScuGic_Config *CfgPtr; - CfgPtr = &XScuGic_ConfigTable[(u32 )DeviceId]; + CfgPtr = &XScuGic_ConfigTable[(INTPTR )DeviceId]; /* * Read the int_ack register to identify the highest priority * interrupt ID and make sure it is valid. Reading Int_Ack will * clear the interrupt in the GIC. */ - IntID = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, XSCUGIC_INT_ACK_OFFSET) - & XSCUGIC_ACK_INTID_MASK; - if(XSCUGIC_MAX_NUM_INTR_INPUTS < IntID){ + IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, XSCUGIC_INT_ACK_OFFSET); + InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK; + if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){ goto IntrExit; } @@ -339,15 +341,17 @@ void XScuGic_DeviceInterruptHandler(void *DeviceId) * Execute the ISR. Jump into the Interrupt service routine based on * the IRQSource. A software trigger is cleared by the ACK. */ - TablePtr = &(CfgPtr->HandlerTable[IntID]); - TablePtr->Handler(TablePtr->CallBackRef); + TablePtr = &(CfgPtr->HandlerTable[InterruptID]); + if(TablePtr != NULL) { + TablePtr->Handler(TablePtr->CallBackRef); + } IntrExit: /* * Write to the EOI register, we are all done here. * Let this function return, the boot code will restore the stack. */ - XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntID); + XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull); /* * Return from the interrupt. Change security domains could happen @@ -379,15 +383,19 @@ IntrExit: * Note that this function has no effect if the input base address is invalid. * ******************************************************************************/ -void XScuGic_RegisterHandler(u32 BaseAddress, int InterruptId, - Xil_InterruptHandler Handler, void *CallBackRef) +void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID, + Xil_InterruptHandler IntrHandler, void *CallBackRef) { XScuGic_Config *CfgPtr; - CfgPtr = LookupConfigByBaseAddress(BaseAddress); - if (CfgPtr != NULL) { - CfgPtr->HandlerTable[InterruptId].Handler = Handler; - CfgPtr->HandlerTable[InterruptId].CallBackRef = CallBackRef; + + if(CfgPtr != NULL) { + if( IntrHandler != NULL) { + CfgPtr->HandlerTable[InterruptID].Handler = IntrHandler; + } + if( CallBackRef != NULL) { + CfgPtr->HandlerTable[InterruptID].CallBackRef = CallBackRef; + } } } @@ -409,9 +417,9 @@ void XScuGic_RegisterHandler(u32 BaseAddress, int InterruptId, static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress) { XScuGic_Config *CfgPtr = NULL; - int Index; + u32 Index; - for (Index = 0; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) { + for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) { if (XScuGic_ConfigTable[Index].CpuBaseAddress == CpuBaseAddress) { CfgPtr = &XScuGic_ConfigTable[Index]; @@ -419,7 +427,7 @@ static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress) } } - return CfgPtr; + return (XScuGic_Config *)CfgPtr; } /****************************************************************************/ @@ -452,10 +460,11 @@ void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, u8 Priority, u8 Trigger) { u32 RegValue; + u8 LocalPriority = Priority; Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK); - Xil_AssertVoid(Priority <= XSCUGIC_MAX_INTR_PRIO_VAL); + Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL); /* * Determine the register to write to using the Int_Id. @@ -469,13 +478,13 @@ void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc. * The lower order 3 bits are masked before putting it in the register. */ - Priority = Priority & XSCUGIC_INTR_PRIO_MASK; + LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK; /* * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4)*8)); - RegValue |= Priority << ((Int_Id%4)*8); + RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U)); + RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U); /* * Write the value back to the register. @@ -492,8 +501,8 @@ void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16)*2)); - RegValue |= Trigger << ((Int_Id%16)*2); + RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U)); + RegValue |= (u32)Trigger << ((Int_Id%16U)*2U); /* * Write the value back to the register. @@ -538,8 +547,8 @@ void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue = RegValue >> ((Int_Id%4)*8); - *Priority = RegValue & XSCUGIC_PRIORITY_MASK; + RegValue = RegValue >> ((Int_Id%4U)*8U); + *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK); /* * Determine the register to read to using the Int_Id. @@ -551,8 +560,8 @@ void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, * Shift and Mask the correct bits for the priority and trigger in the * register */ - RegValue = RegValue >> ((Int_Id%16)*2); + RegValue = RegValue >> ((Int_Id%16U)*2U); - *Trigger = RegValue & XSCUGIC_INT_CFG_MASK; + *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK); } diff --git a/XilinxProcessorIPLib/drivers/scugic/src/xscugic_hw.h b/XilinxProcessorIPLib/drivers/scugic/src/xscugic_hw.h index fd3520f7..ecab3fca 100755 --- a/XilinxProcessorIPLib/drivers/scugic/src/xscugic_hw.h +++ b/XilinxProcessorIPLib/drivers/scugic/src/xscugic_hw.h @@ -91,16 +91,16 @@ extern "C" { * The maximum number of interrupts supported by the hardware. */ #ifdef __ARM_NEON__ -#define XSCUGIC_MAX_NUM_INTR_INPUTS 95 /* Maximum number of interrupt defined by Zynq */ +#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */ #else -#define XSCUGIC_MAX_NUM_INTR_INPUTS 150 /* Maximum number of interrupt defined by Zynq Ultrascale Mp */ +#define XSCUGIC_MAX_NUM_INTR_INPUTS 150U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */ #endif /* * The maximum priority value that can be used in the GIC. */ -#define XSCUGIC_MAX_INTR_PRIO_VAL 248 -#define XSCUGIC_INTR_PRIO_MASK 0xF8 +#define XSCUGIC_MAX_INTR_PRIO_VAL 248U +#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U /** @name Distributor Interface Register Map * @@ -109,62 +109,62 @@ extern "C" { * device. * @{ */ -#define XSCUGIC_DIST_EN_OFFSET 0x00000000 /**< Distributor Enable - Register */ -#define XSCUGIC_IC_TYPE_OFFSET 0x00000004 /**< Interrupt Controller - Type Register */ -#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008 /**< Implementor ID +#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable Register */ -#define XSCUGIC_SECURITY_OFFSET 0x00000080 /**< Interrupt Security - Register */ -#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100 /**< Enable Set +#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller + Type Register */ +#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID Register */ -#define XSCUGIC_DISABLE_OFFSET 0x00000180 /**< Enable Clear Register */ -#define XSCUGIC_PENDING_SET_OFFSET 0x00000200 /**< Pending Set +#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security Register */ -#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280 /**< Pending Clear +#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set Register */ -#define XSCUGIC_ACTIVE_OFFSET 0x00000300 /**< Active Status Register */ -#define XSCUGIC_PRIORITY_OFFSET 0x00000400 /**< Priority Level Register */ -#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800 /**< SPI Target +#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */ +#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set + Register */ +#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear + Register */ +#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */ +#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */ +#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target Register 0x800-0x8FB */ -#define XSCUGIC_INT_CFG_OFFSET 0x00000C00 /**< Interrupt Configuration - Register 0xC00-0xCFC */ -#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00 /**< PPI Status Register */ -#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04 /**< SPI Status Register +#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration + Register 0xC00-0xCFC */ +#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */ +#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register 0xd04-0xd7C */ -#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80 /**< AHB Configuration +#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration Register */ -#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00 /**< Software Triggered +#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered Interrupt Register */ -#define XSCUGIC_PERPHID_OFFSET 0x00000FD0 /**< Peripheral ID Reg */ -#define XSCUGIC_PCELLID_OFFSET 0x00000FF0 /**< Pcell ID Register */ +#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */ +#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */ /* @} */ /** @name Distributor Enable Register * Controls if the distributor response to external interrupt inputs. * @{ */ -#define XSCUGIC_EN_INT_MASK 0x00000001 /**< Interrupt In Enable */ +#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */ /* @} */ /** @name Interrupt Controller Type Register * @{ */ -#define XSCUGIC_LSPI_MASK 0x0000F800 /**< Number of Lockable +#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable Shared Peripheral Interrupts*/ -#define XSCUGIC_DOMAIN_MASK 0x00000400 /**< Number os Security domains*/ -#define XSCUGIC_CPU_NUM_MASK 0x000000E0 /**< Number of CPU Interfaces */ -#define XSCUGIC_NUM_INT_MASK 0x0000001F /**< Number of Interrupt IDs */ +#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/ +#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */ +#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */ /* @} */ /** @name Implementor ID Register * Implementor and revision information. * @{ */ -#define XSCUGIC_REV_MASK 0x00FFF000 /**< Revision Number */ -#define XSCUGIC_IMPL_MASK 0x00000FFF /**< Implementor */ +#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */ +#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */ /* @} */ /** @name Interrupt Security Registers @@ -175,7 +175,7 @@ extern "C" { * There are up to 32 of these registers staring at location 0x084. * @{ */ -#define XSCUGIC_INT_NS_MASK 0x00000001 /**< Each bit corresponds to an +#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an INT_ID */ /* @} */ @@ -189,7 +189,7 @@ extern "C" { * There are up to 32 of these registers staring at location 0x104. * @{ */ -#define XSCUGIC_INT_EN_MASK 0x00000001 /**< Each bit corresponds to an +#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an INT_ID */ /* @} */ @@ -203,7 +203,7 @@ extern "C" { * There are up to 32 of these registers staring at location 0x184. * @{ */ -#define XSCUGIC_INT_CLR_MASK 0x00000001 /**< Each bit corresponds to an +#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an INT_ID */ /* @} */ @@ -217,7 +217,7 @@ extern "C" { * There are up to 32 of these registers staring at location 0x204. * @{ */ -#define XSCUGIC_PEND_SET_MASK 0x00000001 /**< Each bit corresponds to an +#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an INT_ID */ /* @} */ @@ -231,7 +231,7 @@ extern "C" { * There are up to 32 of these registers staring at location 0x284. * @{ */ -#define XSCUGIC_PEND_CLR_MASK 0x00000001 /**< Each bit corresponds to an +#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an INT_ID */ /* @} */ @@ -244,7 +244,7 @@ extern "C" { * There are up to 32 of these registers staring at location 0x380. * @{ */ -#define XSCUGIC_ACTIVE_MASK 0x00000001 /**< Each bit corresponds to an +#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an INT_ID */ /* @} */ @@ -258,9 +258,9 @@ extern "C" { * There are up to 255 of these registers staring at location 0x420. * @{ */ -#define XSCUGIC_PRIORITY_MASK 0x000000FF /**< Each Byte corresponds to an +#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an INT_ID */ -#define XSCUGIC_PRIORITY_MAX 0x000000FF /**< Highest value of a priority +#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority actually the lowest priority*/ /* @} */ @@ -276,14 +276,14 @@ extern "C" { * for complete documentation. * @{ */ -#define XSCUGIC_SPI_CPU7_MASK 0x00000080 /**< CPU 7 Mask*/ -#define XSCUGIC_SPI_CPU6_MASK 0x00000040 /**< CPU 6 Mask*/ -#define XSCUGIC_SPI_CPU5_MASK 0x00000020 /**< CPU 5 Mask*/ -#define XSCUGIC_SPI_CPU4_MASK 0x00000010 /**< CPU 4 Mask*/ -#define XSCUGIC_SPI_CPU3_MASK 0x00000008 /**< CPU 3 Mask*/ -#define XSCUGIC_SPI_CPU2_MASK 0x00000003 /**< CPU 2 Mask*/ -#define XSCUGIC_SPI_CPU1_MASK 0x00000002 /**< CPU 1 Mask*/ -#define XSCUGIC_SPI_CPU0_MASK 0x00000001 /**< CPU 0 Mask*/ +#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/ +#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/ +#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/ +#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/ +#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/ +#define XSCUGIC_SPI_CPU2_MASK 0x00000003U /**< CPU 2 Mask*/ +#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/ +#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/ /* @} */ /** @name Interrupt Configuration Register 0xC00-0xCFC @@ -303,7 +303,7 @@ extern "C" { * There are up to 255 of these registers staring at location 0xC08. * @{ */ -#define XSCUGIC_INT_CFG_MASK 0x00000003 /**< */ +#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */ /* @} */ /** @name PPI Status Register @@ -313,22 +313,22 @@ extern "C" { * This register is aliased for each CPU interface. * @{ */ -#define XSCUGIC_PPI_C15_MASK 0x00008000 /**< PPI Status */ -#define XSCUGIC_PPI_C14_MASK 0x00004000 /**< PPI Status */ -#define XSCUGIC_PPI_C13_MASK 0x00002000 /**< PPI Status */ -#define XSCUGIC_PPI_C12_MASK 0x00001000 /**< PPI Status */ -#define XSCUGIC_PPI_C11_MASK 0x00000800 /**< PPI Status */ -#define XSCUGIC_PPI_C10_MASK 0x00000400 /**< PPI Status */ -#define XSCUGIC_PPI_C09_MASK 0x00000200 /**< PPI Status */ -#define XSCUGIC_PPI_C08_MASK 0x00000100 /**< PPI Status */ -#define XSCUGIC_PPI_C07_MASK 0x00000080 /**< PPI Status */ -#define XSCUGIC_PPI_C06_MASK 0x00000040 /**< PPI Status */ -#define XSCUGIC_PPI_C05_MASK 0x00000020 /**< PPI Status */ -#define XSCUGIC_PPI_C04_MASK 0x00000010 /**< PPI Status */ -#define XSCUGIC_PPI_C03_MASK 0x00000008 /**< PPI Status */ -#define XSCUGIC_PPI_C02_MASK 0x00000004 /**< PPI Status */ -#define XSCUGIC_PPI_C01_MASK 0x00000002 /**< PPI Status */ -#define XSCUGIC_PPI_C00_MASK 0x00000001 /**< PPI Status */ +#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */ +#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */ +#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */ +#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */ +#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */ +#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */ +#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */ +#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */ +#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */ +#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */ +#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */ +#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */ +#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */ +#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */ +#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */ +#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */ /* @} */ /** @name SPI Status Register 0xd04-0xd7C @@ -337,7 +337,7 @@ extern "C" { * configured. * @{ */ -#define XSCUGIC_SPI_N_MASK 0x00000001 /**< Each bit corresponds to an SPI +#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI input */ /* @} */ @@ -346,11 +346,11 @@ extern "C" { * of the GIC to be set. * @{ */ -#define XSCUGIC_AHB_END_MASK 0x00000004 /**< 0-GIC uses little Endian, +#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian, 1-GIC uses Big Endian */ -#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002 /**< 0-Uses CFGBIGEND control, +#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control, 1-use the AHB_END bit */ -#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001 /**< State of CFGBIGEND */ +#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */ /* @} */ @@ -358,15 +358,15 @@ extern "C" { * Controls issueing of software interrupts. * @{ */ -#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000 -#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000 /**< Target List filter +#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U +#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter b00-Use the target List b01-All CPUs except requester b10-To Requester b11-reserved */ -#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000 /**< CPU Target list */ -#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000 /**< 0= Use a secure interrupt */ -#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000F /**< Set to the INTID +#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */ +#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */ +#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID signaled to the CPU*/ /* @} */ @@ -376,16 +376,16 @@ extern "C" { * interrupt controller, some registers may be reserved in the hardware device. * @{ */ -#define XSCUGIC_CONTROL_OFFSET 0x00000000 /**< CPU Interface Control - Register */ -#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004 /**< Priority Mask Reg */ -#define XSCUGIC_BIN_PT_OFFSET 0x00000008 /**< Binary Point Register */ -#define XSCUGIC_INT_ACK_OFFSET 0x0000000C /**< Interrupt ACK Reg */ -#define XSCUGIC_EOI_OFFSET 0x00000010 /**< End of Interrupt Reg */ -#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014 /**< Running Priority Reg */ -#define XSCUGIC_HI_PEND_OFFSET 0x00000018 /**< Highest Pending Interrupt +#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control Register */ -#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001C /**< Aliased non-Secure +#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */ +#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */ +#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */ +#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */ +#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */ +#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt + Register */ +#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure Binary Point Register */ /**< 0x00000020 to 0x00000FBC are reserved and should not be read or written @@ -399,16 +399,16 @@ extern "C" { * mode. * @{ */ -#define XSCUGIC_CNTR_SBPR_MASK 0x00000010 /**< Secure Binary Pointer, +#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer, 0=separate registers, 1=both use bin_pt_s */ -#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008 /**< Use nFIQ_C for secure +#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure interrupts, 0= use IRQ for both, 1=Use FIQ for secure, IRQ for non*/ -#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004 /**< Ack control for secure or non secure */ -#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002 /**< Non Secure enable */ -#define XSCUGIC_CNTR_EN_S_MASK 0x00000001 /**< Secure enable, 0=Disabled, 1=Enabled */ +#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */ +#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */ +#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */ /* @} */ /** @name Priority Mask Register @@ -417,7 +417,7 @@ extern "C" { * lower than the level of the register. * @{ */ -#define XSCUGIC_PRIORITY_MASK 0x000000FF /**< All interrupts */ +/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */ /* @} */ /** @name Binary Point Register @@ -425,7 +425,7 @@ extern "C" { * @{ */ -#define XSCUGIC_BIN_PT_MASK 0x00000007 /**< Binary point mask value +#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value Value Secure Non-secure b000 0xFE 0xFF b001 0xFC 0xFE @@ -443,8 +443,8 @@ extern "C" { * Identifies the current Pending interrupt, and the CPU ID for software * interrupts. */ -#define XSCUGIC_ACK_INTID_MASK 0x000003FF /**< Interrupt ID */ -#define XSCUGIC_CPUID_MASK 0x00000C00 /**< CPU ID */ +#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */ +#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */ /* @} */ /** @name End of Interrupt Register @@ -452,7 +452,7 @@ extern "C" { * Allows the CPU to signal the GIC when it completes an interrupt service * routine. */ -#define XSCUGIC_EOI_INTID_MASK 0x000003FF /**< Interrupt ID */ +#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */ /* @} */ @@ -461,15 +461,15 @@ extern "C" { * Identifies the interrupt priority level of the highest priority active * interrupt. */ -#define XSCUGIC_RUN_PRIORITY_MASK 0x00000FF /**< Interrupt Priority */ +#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */ /* @} */ /* * Highest Pending Interrupt register definitions * Identifies the interrupt priority of the highest priority pending interupt */ -#define XSCUGIC_PEND_INTID_MASK 0x000003FF /**< Pending Interrupt ID */ -#define XSCUGIC_CPUID_MASK 0x00000C00 /**< CPU ID */ +#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */ +/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */ /* @} */ /***************** Macros (Inline Functions) Definitions *********************/ @@ -487,7 +487,7 @@ extern "C" { * *****************************************************************************/ #define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \ - (XSCUGIC_INT_CFG_OFFSET + ((InterruptID/16) * 4)) + ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U)) /****************************************************************************/ /** @@ -502,7 +502,7 @@ extern "C" { * *****************************************************************************/ #define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \ - (XSCUGIC_PRIORITY_OFFSET + ((InterruptID/4) * 4)) + ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U)) /****************************************************************************/ /** @@ -517,7 +517,7 @@ extern "C" { * *****************************************************************************/ #define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \ - (XSCUGIC_SPI_TARGET_OFFSET + ((InterruptID/4) * 4)) + ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U)) /****************************************************************************/ /** @@ -532,8 +532,8 @@ extern "C" { * @note * *****************************************************************************/ -#define XSCUGIC_ENABLE_DISABLE_OFFSET_CALC(Register, InterruptID) \ - (Register + ((InterruptID/32) * 4)) +#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \ + ((Register) + (((InterruptID)/32U) * 4U)) /****************************************************************************/ /** @@ -571,7 +571,7 @@ extern "C" { * *****************************************************************************/ #define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \ - (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)Data))) + (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data)))) /****************************************************************************/ @@ -587,13 +587,13 @@ extern "C" { * @return None. * * @note C-style signature: -* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id); +* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id) * *****************************************************************************/ #define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \ XScuGic_WriteReg((DistBaseAddress), \ - XSCUGIC_ENABLE_SET_OFFSET + ((Int_Id / 32) * 4), \ - (1 << (Int_Id % 32))) + XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \ + (0x00000001U << ((Int_Id) % 32U))) /****************************************************************************/ /** @@ -609,20 +609,20 @@ extern "C" { * @return None. * * @note C-style signature: -* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id); +* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id) * *****************************************************************************/ #define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \ XScuGic_WriteReg((DistBaseAddress), \ - XSCUGIC_DISABLE_OFFSET + ((Int_Id / 32) * 4), \ - (1 << (Int_Id % 32))) + XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \ + (0x00000001U << ((Int_Id) % 32U))) /************************** Function Prototypes ******************************/ void XScuGic_DeviceInterruptHandler(void *DeviceId); -int XScuGic_DeviceInitialize(u32 DeviceId); -void XScuGic_RegisterHandler(u32 BaseAddress, int InterruptId, +s32 XScuGic_DeviceInitialize(u32 DeviceId); +void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID, Xil_InterruptHandler Handler, void *CallBackRef); void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, u8 Priority, u8 Trigger); diff --git a/XilinxProcessorIPLib/drivers/scugic/src/xscugic_intr.c b/XilinxProcessorIPLib/drivers/scugic/src/xscugic_intr.c index 0d2ebc29..55443957 100755 --- a/XilinxProcessorIPLib/drivers/scugic/src/xscugic_intr.c +++ b/XilinxProcessorIPLib/drivers/scugic/src/xscugic_intr.c @@ -113,7 +113,7 @@ void XScuGic_InterruptHandler(XScuGic *InstancePtr) { - u32 IntID; + u32 InterruptID; u32 IntIDFull; XScuGic_VectorTableEntry *TablePtr; @@ -127,9 +127,9 @@ void XScuGic_InterruptHandler(XScuGic *InstancePtr) * in the GIC. */ IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET); - IntID = IntIDFull & XSCUGIC_ACK_INTID_MASK; + InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK; - if(XSCUGIC_MAX_NUM_INTR_INPUTS < IntID){ + if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){ goto IntrExit; } @@ -151,8 +151,10 @@ void XScuGic_InterruptHandler(XScuGic *InstancePtr) * Execute the ISR. Jump into the Interrupt service routine based on the * IRQSource. A software trigger is cleared by the ACK. */ - TablePtr = &(InstancePtr->Config->HandlerTable[IntID]); + TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]); + if(TablePtr != NULL) { TablePtr->Handler(TablePtr->CallBackRef); + } IntrExit: /* diff --git a/XilinxProcessorIPLib/drivers/scugic/src/xscugic_selftest.c b/XilinxProcessorIPLib/drivers/scugic/src/xscugic_selftest.c index 49d438b8..1616cf8a 100755 --- a/XilinxProcessorIPLib/drivers/scugic/src/xscugic_selftest.c +++ b/XilinxProcessorIPLib/drivers/scugic/src/xscugic_selftest.c @@ -54,7 +54,7 @@ /************************** Constant Definitions *****************************/ -#define XSCUGIC_PCELL_ID 0xB105F00D +#define XSCUGIC_PCELL_ID 0xB105F00DU /**************************** Type Definitions *******************************/ @@ -82,10 +82,11 @@ * @note None. * ******************************************************************************/ -int XScuGic_SelfTest(XScuGic *InstancePtr) +s32 XScuGic_SelfTest(XScuGic *InstancePtr) { - u32 RegValue1 =0; - int Index; + u32 RegValue1 = 0U; + u32 Index; + s32 Status; /* * Assert the arguments @@ -96,15 +97,16 @@ int XScuGic_SelfTest(XScuGic *InstancePtr) /* * Read the ID registers. */ - for(Index=0; Index<=3; Index++) { + for(Index=0U; Index<=3U; Index++) { RegValue1 |= XScuGic_DistReadReg(InstancePtr, - (XSCUGIC_PCELLID_OFFSET + (Index * 4))) << (Index * 8); + ((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) << (Index * 8U); } if(XSCUGIC_PCELL_ID != RegValue1){ - return XST_FAILURE; + Status = XST_FAILURE; + } else { + Status = XST_SUCCESS; } - - return XST_SUCCESS; + return Status; } diff --git a/XilinxProcessorIPLib/drivers/scugic/src/xscugic_sinit.c b/XilinxProcessorIPLib/drivers/scugic/src/xscugic_sinit.c index eeff4688..a976727e 100755 --- a/XilinxProcessorIPLib/drivers/scugic/src/xscugic_sinit.c +++ b/XilinxProcessorIPLib/drivers/scugic/src/xscugic_sinit.c @@ -65,7 +65,7 @@ /************************** Variable Definitions *****************************/ -extern XScuGic_Config XScuGic_ConfigTable[]; +extern XScuGic_Config XScuGic_ConfigTable[XPAR_SCUGIC_NUM_INSTANCES]; /************************** Function Prototypes ******************************/ @@ -86,15 +86,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId) { XScuGic_Config *CfgPtr = NULL; - int Index; + u32 Index; - for (Index=0; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) { + for (Index=0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) { if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) { CfgPtr = &XScuGic_ConfigTable[Index]; break; } } - return CfgPtr; + return (XScuGic_Config *)CfgPtr; }