From 25909c614842a0af34ef0d9de778463e5a586a30 Mon Sep 17 00:00:00 2001 From: Kedareswara rao Appana Date: Fri, 15 May 2015 14:06:30 +0530 Subject: [PATCH] llfifo: Update Register offsets in AXI4 data path as per latest IP version This patch updates the register offsets in the AXI4 data path as per latest IP version(v4.1). The addresses are changed to accommodate increased data width. With old address map and increased data width user had to generate AXI4 unaligned transactions. Therefore, the address map was changed for ease of use in the IP. Signed-off-by: Kedareswara rao Appana --- XilinxProcessorIPLib/drivers/llfifo/src/xllfifo.c | 15 +++++++++++---- XilinxProcessorIPLib/drivers/llfifo/src/xllfifo.h | 2 ++ .../drivers/llfifo/src/xllfifo_hw.h | 2 ++ 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo.c b/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo.c index ff8107cd..d76b704f 100644 --- a/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo.c +++ b/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo.c @@ -405,7 +405,11 @@ int XLlFifo_CfgInitialize(XLlFifo *InstancePtr, *****************************************************************************/ u32 XLlFifo_RxGetWord(XLlFifo *InstancePtr) { - return XLlFifo_ReadReg((InstancePtr)->Axi4BaseAddress, + if (InstancePtr->Datainterface) + return XLlFifo_ReadReg((InstancePtr)->Axi4BaseAddress, + XLLF_AXI4_RDFD_OFFSET); + else + return XLlFifo_ReadReg((InstancePtr)->Axi4BaseAddress, XLLF_RDFD_OFFSET); } @@ -426,9 +430,12 @@ u32 XLlFifo_RxGetWord(XLlFifo *InstancePtr) *****************************************************************************/ void XLlFifo_TxPutWord(XLlFifo *InstancePtr, u32 Word) { - - XLlFifo_WriteReg((InstancePtr)->Axi4BaseAddress, - XLLF_TDFD_OFFSET, (Word)); + if (InstancePtr->Datainterface) + XLlFifo_WriteReg((InstancePtr)->Axi4BaseAddress, + XLLF_AXI4_TDFD_OFFSET, (Word)); + else + XLlFifo_WriteReg((InstancePtr)->Axi4BaseAddress, + XLLF_TDFD_OFFSET, (Word)); } diff --git a/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo.h b/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo.h index db742c9b..08b8219c 100644 --- a/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo.h +++ b/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo.h @@ -162,6 +162,8 @@ * XLlFifo_Initialize is still used to make the driver * backward compatible. * 4.0 adk 19/12/13 Updated as per the New Tcl API's + * 5.0 adk 15/05/15 Updated the register offsets in the AXI4 data path + * as per latest IP version(v4.1)(CR:860254). * * * diff --git a/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_hw.h b/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_hw.h index bb7fa206..0c453bdf 100644 --- a/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_hw.h +++ b/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_hw.h @@ -83,11 +83,13 @@ extern "C" { #define XLLF_TDFR_OFFSET 0x00000008 /**< Transmit Reset */ #define XLLF_TDFV_OFFSET 0x0000000c /**< Transmit Vacancy */ #define XLLF_TDFD_OFFSET 0x00000010 /**< Transmit Data */ +#define XLLF_AXI4_TDFD_OFFSET 0x00000000 /**< Axi4 Transmit Data */ #define XLLF_TLF_OFFSET 0x00000014 /**< Transmit Length */ #define XLLF_RDFR_OFFSET 0x00000018 /**< Receive Reset */ #define XLLF_RDFO_OFFSET 0x0000001c /**< Receive Occupancy */ #define XLLF_RDFD_OFFSET 0x00000020 /**< Receive Data */ +#define XLLF_AXI4_RDFD_OFFSET 0x00001000 /**< Axi4 Receive Data */ #define XLLF_RLF_OFFSET 0x00000024 /**< Receive Length */ #define XLLF_LLR_OFFSET 0x00000028 /**< Local Link Reset */ #define XLLF_TDR_OFFSET 0x0000002C /**< Transmit Destination */