diff --git a/XilinxProcessorIPLib/drivers/qspips/src/xqspips.c b/XilinxProcessorIPLib/drivers/qspips/src/xqspips.c index 23edc9d4..b2606345 100755 --- a/XilinxProcessorIPLib/drivers/qspips/src/xqspips.c +++ b/XilinxProcessorIPLib/drivers/qspips/src/xqspips.c @@ -93,6 +93,8 @@ * Added RX threshold reset(1) after transfer in polled and * interrupt transfers. Made changes to make sure threshold * change is done only when no transfer is in progress. +* 3.1 hk 06/19/14 When writng configuration register, set/reset +* required bits leaving reserved bits untouched. CR# 796813. * * * @@ -257,6 +259,8 @@ int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *ConfigPtr, ******************************************************************************/ void XQspiPs_Reset(XQspiPs *InstancePtr) { + u32 ConfigReg; + Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -266,11 +270,13 @@ void XQspiPs_Reset(XQspiPs *InstancePtr) XQspiPs_Abort(InstancePtr); /* - * Reset any values that are not reset by the hardware reset such that - * the software state matches the hardware device + * Write default value to configuration register. + * Do not modify reserved bits. */ + ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, + XQSPIPS_CR_OFFSET); XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, - XQSPIPS_CR_RESET_STATE); + ConfigReg | XQSPIPS_CR_RESET_STATE); } /*****************************************************************************/ diff --git a/XilinxProcessorIPLib/drivers/qspips/src/xqspips.h b/XilinxProcessorIPLib/drivers/qspips/src/xqspips.h index 2b662839..e2409228 100755 --- a/XilinxProcessorIPLib/drivers/qspips/src/xqspips.h +++ b/XilinxProcessorIPLib/drivers/qspips/src/xqspips.h @@ -263,6 +263,8 @@ * change is done only when no transfer is in progress. * Updated linear init API for parallel and stacked modes. * CR#737760. +* 3.1 hk 06/19/14 When writng configuration register, set/reset +* required bits leaving reserved bits untouched. CR# 796813. * * * diff --git a/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.c b/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.c index 3403670e..ef0b9f28 100755 --- a/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.c +++ b/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.c @@ -42,6 +42,8 @@ * Ver Who Date Changes * ----- --- -------- ----------------------------------------------- * 2.03a hk 09/17/13 First release +* 3.1 hk 06/19/14 When writng configuration register, set/reset +* required bits leaving reserved bits untouched. CR# 796813. * * * @@ -137,9 +139,9 @@ void XQspiPs_ResetHw(u32 BaseAddress) /* * Write default value to configuration register */ + ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET); XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, - XQSPIPS_CR_RESET_STATE); - + ConfigReg | XQSPIPS_CR_RESET_STATE); /* * De-select linear mode diff --git a/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.h b/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.h index 46b2da55..2246c40a 100755 --- a/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.h +++ b/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.h @@ -55,6 +55,9 @@ * 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and * linear mode initialization for boot. Added related * constant definitions. +* 3.1 hk 06/19/14 Changed definition of XQSPIPS_CR_RESET_STATE to set/reset +* required bits leaving reserved bits untouched. CR# 796813. +* * * * @@ -131,11 +134,22 @@ extern "C" { #define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */ +#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */ + /* Deselect the Slave select line and set the transfer size to 32 at reset */ -#define XQSPIPS_CR_RESET_STATE (XQSPIPS_CR_IFMODE_MASK | \ +#define XQSPIPS_CR_RESET_STATE ((XQSPIPS_CR_IFMODE_MASK | \ XQSPIPS_CR_SSCTRL_MASK | \ XQSPIPS_CR_DATA_SZ_MASK | \ - XQSPIPS_CR_MSTREN_MASK) + XQSPIPS_CR_MSTREN_MASK | \ + XQSPIPS_CR_SSFORCE_MASK | \ + XQSPIPS_CR_HOLD_B_MASK) & \ + (~(XQSPIPS_CR_CPOL_MASK | \ + XQSPIPS_CR_CPHA_MASK | \ + XQSPIPS_CR_PRESC_MASK | \ + XQSPIPS_CR_MANSTRTEN_MASK | \ + XQSPIPS_CR_MANSTRT_MASK | \ + XQSPIPS_CR_ENDIAN_MASK | \ + XQSPIPS_CR_REF_CLK_MASK))) /* @} */ diff --git a/XilinxProcessorIPLib/drivers/qspips/src/xqspips_selftest.c b/XilinxProcessorIPLib/drivers/qspips/src/xqspips_selftest.c index 862da729..244724bc 100755 --- a/XilinxProcessorIPLib/drivers/qspips/src/xqspips_selftest.c +++ b/XilinxProcessorIPLib/drivers/qspips/src/xqspips_selftest.c @@ -44,6 +44,8 @@ * ----- --- -------- ----------------------------------------------- * 1.00 sdm 11/25/10 First release * 2.01a sg 02/03/13 Delay Register test is added with DelayNss parameter. +* 3.1 hk 06/19/14 Remove checks for CR and ISR register values as they are +* reset in the previous step. * * * @@ -99,21 +101,6 @@ int XQspiPs_SelfTest(XQspiPs *InstancePtr) */ XQspiPs_Reset(InstancePtr); - /* - * All the QSPI registers should be in their default state right now. - */ - Register = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - if (Register != XQSPIPS_CR_RESET_STATE) { - return XST_REGISTER_ERROR; - } - - Register = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_SR_OFFSET); - if (Register != XQSPIPS_ISR_RESET_STATE) { - return XST_REGISTER_ERROR; - } - DelayTestNss = 0x5A; DelayTestBtwn = 0xA5; DelayTestAfter = 0xAA;