diff --git a/XilinxProcessorIPLib/drivers/dptxss/data/dptxss.mdd b/XilinxProcessorIPLib/drivers/dptxss/data/dptxss.mdd
new file mode 100644
index 00000000..face2905
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/data/dptxss.mdd
@@ -0,0 +1,41 @@
+##############################################################################
+#
+# Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"),to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+###############################################################################
+
+OPTION psf_version = 2.1;
+
+BEGIN driver dptxss
+ OPTION supported_peripherals = (dp_tx_subsystem);
+ OPTION driver_state = ACTIVE;
+ OPTION depends = (dual_splitter_v1_0);
+ OPTION copyfiles = all;
+ OPTION VERSION = 1.0;
+ OPTION NAME = dptxss;
+END driver
diff --git a/XilinxProcessorIPLib/drivers/dptxss/data/dptxss.tcl b/XilinxProcessorIPLib/drivers/dptxss/data/dptxss.tcl
new file mode 100644
index 00000000..b3d31772
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/data/dptxss.tcl
@@ -0,0 +1,205 @@
+##############################################################################
+#
+# Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"),to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+###############################################################################
+
+proc generate {drv_handle} {
+ ::hsi::utils::define_include_file $drv_handle "xparameters.h" "XDpTxSs" "NUM_INSTANCES" "C_BASEADDR" "C_HIGHADDR" "DEVICE_ID" "AUDIO_ENABLE" "BITS_PER_COLOR" "HDCP_ENABLE" "LANE_COUNT" "MODE" "NUM_STREAMS" "SIM_MODE"
+ hier_ip_define_config_file $drv_handle "xdptxss_g.c" "XDpTxSs" "DEVICE_ID" "C_BASEADDR" "AUDIO_ENABLE" "BITS_PER_COLOR" "HDCP_ENABLE" "LANE_COUNT" "MODE" "NUM_STREAMS"
+ ::hsi::utils::define_canonical_xpars $drv_handle "xparameters.h" "DpTxSs" "C_BASEADDR" "C_HIGHADDR" "DEVICE_ID" "AUDIO_ENABLE" "BITS_PER_COLOR" "HDCP_ENABLE" "LANE_COUNT" "MODE" "NUM_STREAMS" "SIM_MODE"
+}
+
+# This procedure creates parameters XPAR_* of each sub-cores in xdptxss_g.c file.
+# to align with subsystem config structure. Basically, subsystem is hierarchical IP (HIP),
+# includes configuration parameters of each sub-cores along with its configuration
+# parameters.
+proc hier_ip_define_config_file {drv_handle file_name drv_string args} {
+ set args [::hsi::utils::get_exact_arg_list $args]
+ set brace 0
+ set num_vtc 0
+ array set sub_core_params {}
+
+ set sub_core_params(displayport) "BASEADDR S_AXI_ACLK LANE_COUNT LINK_RATE MAX_BITS_PER_COLOR QUAD_PIXEL_ENABLE DUAL_PIXEL_ENABLE YCRCB_ENABLE YONLY_ENABLE GT_DATAWIDTH SECONDARY_SUPPORT AUDIO_CHANNELS MST_ENABLE NUMBER_OF_MST_STREAMS PROTOCOL_SELECTION FLOW_DIRECTION"
+ set sub_core_params(v_tc) "BASEADDR"
+ set sub_core_params(v_dual_splitter) "BASEADDR ACTIVE_COLS ACTIVE_ROWS MAX_SEGMENTS AXIS_VIDEO_MAX_TDATA_WIDTH AXIS_VIDEO_MAX_ITDATASMPLS_PER_CLK AXIS_VIDEO_MAX_OTDATASMPLS_PER_CLK MAX_OVRLAP MAX_SMPL_WIDTH HAS_AXI4_LITE HAS_IRQ"
+
+ set filename [file join "src" $file_name]
+ set config_file [open $filename w]
+ ::hsi::utils::write_c_header $config_file "Driver configuration"
+ puts $config_file "#include \"xparameters.h\""
+ puts $config_file "#include \"[string tolower $drv_string].h\""
+ puts $config_file "\n/*"
+ puts $config_file "* The configuration table for devices"
+ puts $config_file "*/\n"
+
+ set periphs_g [::hsi::utils::get_common_driver_ips $drv_handle]
+
+ foreach periph_g $periphs_g {
+ ::hsi::current_hw_instance $periph_g;
+
+ set child_cells_g [::hsi::get_cells]
+
+ foreach child_cell_g $child_cells_g {
+ set child_cell_vlnv [::common::get_property VLNV $child_cell_g]
+ set vlnv_arr [split $child_cell_vlnv :]
+ lassign $vlnv_arr ip_vendor ip_library ip_name ip_version
+
+ set child_cell_name_g [common::get_property NAME $child_cell_g]
+ set ip_type_g [common::get_property IP_TYPE $child_cell_g]
+ set final_child_cell_instance_name_present_g XPAR_${child_cell_name_g}_PRESENT
+
+ if { [string compare -nocase "BUS" $ip_type_g] != 0 } {
+ set interfaces [hsi::get_intf_pins -of_objects $child_cell_g]
+ set is_slave 0
+
+ foreach interface $interfaces {
+ set intf_type [common::get_property TYPE $interface]
+
+ if { [string compare -nocase "SLAVE" $intf_type] == 0 } {
+ set is_slave 1
+ }
+ }
+ if { $is_slave != 0 } {
+ puts -nonewline $config_file "#define [string toupper $final_child_cell_instance_name_present_g] \t1\n"
+ if {$ip_name == "v_tc"} {
+ incr num_vtc
+ }
+ }
+ }
+ }
+ puts $config_file "\n"
+
+ ::hsi::current_hw_instance
+ }
+
+ puts $config_file [format "%s_Config %s_ConfigTable\[\] =" $drv_string $drv_string]
+ puts $config_file "\{"
+ set periphs [::hsi::utils::get_common_driver_ips $drv_handle]
+ set start_comma ""
+ foreach periph $periphs {
+ puts $config_file [format "%s\t\{" $start_comma]
+ set comma ""
+ foreach arg $args {
+ if {[string compare -nocase "DEVICE_ID" $arg] == 0} {
+ puts -nonewline $config_file [format "%s\t\t%s,\n" $comma [::hsi::utils::get_ip_param_name $periph $arg]]
+ continue
+ }
+ puts -nonewline $config_file [format "%s\t\t%s" $comma [::hsi::utils::get_ip_param_name $periph $arg]]
+ set comma ",\n"
+ }
+
+ ::hsi::current_hw_instance $periph
+ set child_cells [::hsi::get_cells]
+ puts $config_file ",\n"
+
+ foreach child_cell $child_cells {
+ set child_cell_vlnv [::common::get_property VLNV $child_cell]
+ set vlnv_arr [split $child_cell_vlnv :]
+
+ lassign $vlnv_arr ip_vendor ip_library ip_name ip_version
+
+ set ip_type [common::get_property IP_TYPE $child_cell]
+ set child_cell_name [common::get_property NAME $child_cell]
+ set final_child_cell_instance_name XPAR_${child_cell_name}_DEVICE_ID
+ set final_child_cell_instance_name_present XPAR_${child_cell_name}_PRESENT
+
+ if { [string compare -nocase "BUS" $ip_type] != 0 } {
+ set interfaces [hsi::get_intf_pins -of_objects $child_cell]
+ set is_slave 0
+ foreach interface $interfaces {
+ set intf_type [common::get_property TYPE $interface]
+ if { [string compare -nocase "SLAVE" $intf_type] == 0 } {
+ set is_slave 1
+ }
+ }
+
+ if { $is_slave != 0 } {
+ if {$ip_name == "v_tc"} {
+ if { $brace == 0 } {
+ puts $config_file "\t\t\{"
+ }
+ incr brace
+
+ puts $config_file "\t\t\t\{"
+ puts -nonewline $config_file [format "\t\t\t\t%s" [string toupper $final_child_cell_instance_name_present]]
+ puts $config_file ","
+ puts $config_file "\t\t\t\t\{"
+ puts -nonewline $config_file [format "\t\t\t\t\t%s" [string toupper $final_child_cell_instance_name]]
+
+ set params_str $sub_core_params($ip_name)
+ set params_arr [split $params_str " " ]
+
+ foreach param $params_arr {
+ set final_child_cell_param_name XPAR_${child_cell_name}_$param
+ puts $config_file ","
+ puts -nonewline $config_file [format "\t\t\t\t\t%s" [string toupper $final_child_cell_param_name]]
+ }
+ if { $brace == $num_vtc} {
+ puts $config_file "\n\t\t\t\t\}"
+ puts $config_file "\t\t\t\}"
+ puts $config_file "\t\t\}"
+ } else {
+ puts $config_file "\n\t\t\t\t\}"
+ puts $config_file "\t\t\t\},"
+ }
+ } else {
+ set comma ",\n"
+
+ puts $config_file "\t\t\{"
+ puts -nonewline $config_file [format "\t\t\t%s" [string toupper $final_child_cell_instance_name_present]]
+ puts $config_file ","
+ puts $config_file "\t\t\t\{"
+ puts -nonewline $config_file [format "\t\t\t\t%s" [string toupper $final_child_cell_instance_name]]
+
+ set params_str $sub_core_params($ip_name)
+ set params_arr [split $params_str " " ]
+
+ foreach param $params_arr {
+ set final_child_cell_param_name XPAR_${child_cell_name}_$param
+ puts $config_file ","
+ puts -nonewline $config_file [format "\t\t\t\t%s" [string toupper $final_child_cell_param_name]]
+ }
+ puts $config_file "\n\t\t\t\}"
+ puts $config_file "\t\t\},"
+ }
+ }
+ }
+ }
+
+ ::hsi::current_hw_instance
+
+ puts -nonewline $config_file "\t\}"
+ set start_comma ",\n"
+ }
+
+ puts $config_file "\n\};"
+ puts $config_file "\n";
+
+ close $config_file
+}
diff --git a/XilinxProcessorIPLib/drivers/dptxss/src/Makefile b/XilinxProcessorIPLib/drivers/dptxss/src/Makefile
new file mode 100644
index 00000000..ac6a65cf
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=-Wall -Wextra
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+INCLUDEFILES=*.h ./vtc/*.h ./dualsplitter/*.h ./dp/*.h
+LIBSOURCES=*.c ./vtc/*.c ./dualsplitter/*.c ./dp/*.c
+
+OBJECTS = $(addsuffix .o, $(basename ./vtc/xss_vtc.c ./dualsplitter/xss_dualsplitter.c ./dp/xss_dptx.c $(wildcard *.c)))
+
+libs: banner xdptxss_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling DisplayPort Transmitter Subsystem"
+
+xdptxss_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xdptxss_includes
+
+xdptxss_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/XilinxProcessorIPLib/drivers/dptxss/src/dp/xss_dptx.c b/XilinxProcessorIPLib/drivers/dptxss/src/dp/xss_dptx.c
new file mode 100644
index 00000000..c830e4c4
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/src/dp/xss_dptx.c
@@ -0,0 +1,1028 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xss_dptx.c
+*
+* This file contains a minimal set of functions for the DisplayPort core
+* to configure in TX mode of operation.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ---- --- -------- --------------------------------------------------
+* 1.00 sha 01/29/15 Initial release.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xss_dptx.h"
+#include "xvidc.h"
+#include "xvidc_edid.h"
+#include "xdebug.h"
+#include "string.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+static u32 Dp_GetTopology(XDp *InstancePtr);
+static u32 Dp_CheckBandwidth(XDp *InstancePtr, u8 Bpc,
+ XVidC_VideoMode VidMode);
+static XVidC_VideoMode Dp_GetPreferredVm(u8 *EdidPtr);
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function configures DisplayPort sub-core with preferred resolution
+* read from sink or user set resolution, bits per color in SST/MST mode.
+* In MST mode, if sinks are more than two, it re-orders the sinks if belongs
+* to same tiled display topology. It trains the link and allocates stream
+* payloads for single stream (SST) or multi-stream transport mode (MST).
+* In MST mode, discovers the topology and finds the actual number of sinks to
+* which associates streams.
+*
+* @param InstancePtr is a pointer to the XDp instance.
+* @param TransportMode specifies whether multiple/single steam to be
+* sent over the main link.
+* - TransportMode = 1 (for Multi-Stream Transport)
+* - TransportMode = 0 (for Single Stream Transport)
+* @param Bpc is the new number of bits per color to use.
+* @param VidMode is one of the enumerated standard video modes
+* defined in xvidc.h file.
+*
+* @return
+* - XST_SUCCESS DisplayPort configured successfully.
+* - XST_FAILURE if DisplayPort configuration failed.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XSs_DpTxStart(XDp *InstancePtr, u8 TransportMode, u8 Bpc,
+ XVidC_VideoMode VidMode)
+{
+ u32 Status;
+ u8 StreamIndex;
+ u8 NumOfStreams;
+ u8 Edid[128];
+ XDp_TxTopologyNode *Sink1;
+
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid((TransportMode == XSS_DPTX_MST) ||
+ (TransportMode == XSS_DPTX_SST));
+ Xil_AssertNonvoid((Bpc == XVIDC_BPC_8) || (Bpc == XVIDC_BPC_10) ||
+ (Bpc == XVIDC_BPC_12) || (Bpc == XVIDC_BPC_16));
+ Xil_AssertNonvoid((VidMode < XVIDC_VM_NUM_SUPPORTED) ||
+ (VidMode == XVIDC_VM_USE_EDID_PREFERRED));
+
+ /* Check for MST / SST mode */
+ if (TransportMode) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"\n\rSS INFO:Starting "
+ "MST config.\n\r");
+ /* Enable MST mode in both the RX and TX. */
+ Status = XDp_TxMstEnable(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ /* If the immediate downstream RX device is an MST
+ * monitor and the DisplayPort Configuration Data
+ * (DPCD) does not indicate MST capability, it is
+ * likely that the MST or DisplayPort v1.2 option must
+ * be selected from the monitor's option menu.
+ * Likewise, the DisplayPort TX core must be configured
+ * to support MST mode. */
+ if (Status == XST_DEVICE_NOT_FOUND) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:MST:"
+ "No connection exists. Verify cable "
+ "and/or monitor.\n\r");
+ }
+ else {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:MST:"
+ "Verify DisplayPort MST capabilities "
+ "in the TX and/or RX device MST "
+ "status is %ld\n\r", Status);
+ }
+
+ return XST_FAILURE;
+ }
+
+ /* Set AUX and sideband delays in microseconds */
+ InstancePtr->TxInstance.AuxDelayUs = 30000;
+ InstancePtr->TxInstance.SbMsgDelayUs = 30000;
+
+ /* Enable downshifting during link training */
+ XDp_TxEnableTrainAdaptive(InstancePtr, 1);
+
+ /* Enable redriver on DP output path */
+ XDp_TxSetHasRedriverInPath(InstancePtr, 1);
+
+ /* Disable main stream to force sending of IDLE patterns. */
+ XDp_TxDisableMainLink(InstancePtr);
+
+ /* Start link training with user set link rate and lane
+ * count. Training is required to discover topology so that
+ * prefer erred timing can be known.
+ */
+ Status = XSs_DpTxStartLink(InstancePtr, FALSE);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:Re- "
+ "training with maximum RX capabilities\n\r");
+
+ /* Train link with maximum RX capabilities */
+ Status = XSs_DpTxStartLink(InstancePtr, TRUE);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:MST:"
+ "Verify cable and/or monitor.\n\r");
+ return Status;
+ }
+ }
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:Discovering "
+ "topology.\n\r");
+
+ /* Get list of sinks */
+ Status = Dp_GetTopology(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ return Status;
+ }
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:Topology "
+ "discovery done, # of sinks found = %d.\n\r",
+ InstancePtr->TxInstance.Topology.SinkTotal);
+
+ /* Total number of streams equal to number of sinks found */
+ NumOfStreams = InstancePtr->TxInstance.Topology.SinkTotal;
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:Reading (MST) Sink "
+ "EDID...\n\r");
+
+ /* Read EDID of first sink */
+ Sink1 = InstancePtr->TxInstance.Topology.SinkList[0];
+ XDp_TxGetRemoteEdid(InstancePtr, Sink1->LinkCountTotal,
+ Sink1->RelativeAddress, Edid);
+
+ /* Check video mode for EDID preferred video mode */
+ if (VidMode == XVIDC_VM_USE_EDID_PREFERRED) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:Using "
+ "preferred EDID resolution.\n\r");
+
+ /* Get preferred video mode from EDID */
+ VidMode = Dp_GetPreferredVm(Edid);
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:VM "
+ "from EDID:%s\n\r",
+ XVidC_GetVideoModeStr(VidMode));
+
+ /* Check whether Video mode exist in VTM table */
+ if (XVIDC_VM_NOT_SUPPORTED == VidMode) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:"
+ "Preferred video mode not present in "
+ "VMT. Update video timing table.\n\r"
+ "Setting to 640x480 video mode\n\r");
+ VidMode = XVIDC_VM_640x480_60_P;
+ }
+
+ if ((InstancePtr->TxInstance.Topology.SinkTotal ==
+ 4) && (VidMode == XVIDC_VM_UHD2_60_P)) {
+ VidMode = XVIDC_VM_1080_60_P;
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:"
+ "MST:Re-ordering sinks if belongs to "
+ "same TDT...\n\r");
+
+ /* Order the sink belong to same TDT */
+ XDp_TxTopologySortSinksByTiling(InstancePtr);
+ }
+ else if ((InstancePtr->TxInstance.Topology.SinkTotal ==
+ 2) && (VidMode <= XVIDC_VM_UHD2_60_P)){
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:"
+ "MST:Re-ordering sinks if belongs to "
+ "same TDT...\n\r");
+
+ /* Order the sink belong to same TDT */
+ XDp_TxTopologySortSinksByTiling(InstancePtr);
+ }
+ }
+ else {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:Using "
+ "user set resolution.\n\r");
+
+ /* Check whether VidMode ID is supported */
+ Status = XVidC_EdidIsVideoTimingSupported(Edid,
+ (XVidC_VideoTimingMode *)XVidC_GetVideoModeData(
+ VidMode));
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:"
+ "MST:%s is not supported.\n\rSetting to "
+ "640x480 resolution."
+ "\n\r", XVidC_GetVideoModeStr(VidMode));
+ VidMode = XVIDC_VM_640x480_60_P;
+ }
+
+ if ((InstancePtr->TxInstance.Topology.SinkTotal ==
+ 4) && (VidMode == XVIDC_VM_UHD2_60_P)){
+ VidMode = XVIDC_VM_1080_60_P;
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:"
+ "Re-ordering sinks if belongs to same "
+ "TDT...\n\r");
+
+ /* Order sinks belongs to the same TDT */
+ XDp_TxTopologySortSinksByTiling(InstancePtr);
+ }
+ else if ((InstancePtr->TxInstance.Topology.SinkTotal ==
+ 2) && (VidMode <= XVIDC_VM_UHD2_60_P)){
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:"
+ "Re-ordering sinks if belongs to same "
+ "TDT...\n\r");
+
+ /* Order sinks belongs to the same TDT */
+ XDp_TxTopologySortSinksByTiling(InstancePtr);
+ }
+ }
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:calculating "
+ "payload...\n\r");
+
+ /* Check link and video bandwidth */
+ Status = Dp_CheckBandwidth(InstancePtr, Bpc, VidMode);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:Link is "
+ "over-subscribed for selected resolution, "
+ "bpc, lane count and link rate value."
+ "\n\rRe-training with maximum RX capabilities."
+ "\n\r");
+
+ /* Check for link training need and run training
+ * sequence.
+ */
+ Status = XSs_DpTxStartLink(InstancePtr, TRUE);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:"
+ "Re-training with max after payload "
+ "failed.\n\r");
+ return Status;
+ }
+ }
+
+ /* Enable each stream(s) */
+ for (StreamIndex = 0; StreamIndex < NumOfStreams;
+ StreamIndex++) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:"
+ "Enabling stream #%d\n", XDP_TX_STREAM_ID1 +
+ StreamIndex);
+ XDp_TxMstCfgStreamEnable(InstancePtr,
+ XDP_TX_STREAM_ID1 + StreamIndex);
+ XDp_TxSetStreamSelectFromSinkList(InstancePtr,
+ XDP_TX_STREAM_ID1 + StreamIndex, StreamIndex);
+ }
+
+ /* Disable stream(s) */
+ for (StreamIndex = NumOfStreams; StreamIndex < 4;
+ StreamIndex++) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:"
+ "Disabling stream #%d\n", XDP_TX_STREAM_ID1 +
+ StreamIndex);
+ XDp_TxMstCfgStreamDisable(InstancePtr,
+ XDP_TX_STREAM_ID1 + StreamIndex);
+ }
+
+ /* Stream setup */
+ for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) {
+ if (XDp_TxMstStreamIsEnabled(InstancePtr,
+ XDP_TX_STREAM_ID1 + StreamIndex)) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:"
+ "Stream #%d... ",XDP_TX_STREAM_ID1 +
+ StreamIndex);
+
+ /* Set bits per color for each stream */
+ XDp_TxCfgMsaSetBpc(InstancePtr,
+ XDP_TX_STREAM_ID1 + StreamIndex, Bpc);
+
+ /* Enable sync clock mode for each stream */
+ XDp_TxCfgMsaEnSynchClkMode(InstancePtr,
+ XDP_TX_STREAM_ID1 + StreamIndex, 1);
+
+ /* Use standard video mode to calculate MSA */
+ XDp_TxCfgMsaUseStandardVideoMode(InstancePtr,
+ XDP_TX_STREAM_ID1 + StreamIndex,
+ VidMode);
+
+ /* Set user pixel width if video mode is
+ * UHD2
+ */
+ if ((InstancePtr->TxInstance.MsaConfig[
+ StreamIndex].Vtm.VmId ==
+ XVIDC_VM_UHD2_60_P) &&
+ (InstancePtr->TxInstance.MsaConfig[
+ StreamIndex].OverrideUserPixelWidth ==
+ 0)) {
+ InstancePtr->TxInstance.MsaConfig[
+ StreamIndex].UserPixelWidth =
+ 4;
+ }
+
+ /* Apply to hardware */
+ XDp_TxSetVideoMode(InstancePtr,
+ XDP_TX_STREAM_ID1 + StreamIndex);
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"configured."
+ "\n\r");
+ }
+ }
+
+ Status = XDp_TxCheckLinkStatus(InstancePtr,
+ InstancePtr->TxInstance.LinkConfig.LaneCount);
+ if (Status == XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST: Link "
+ "is up after streams are configured!\n\r\n\r");
+ }
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:Allocating "
+ "payload...\n\r");
+
+ /* Clear virtual channel payload ID table in TX and all
+ * downstream RX devices
+ */
+ Status = XDp_TxClearPayloadVcIdTable(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:MST:"
+ "Clearing virtual channel payload "
+ "failed.\n\r");
+ return XST_DATA_LOST;
+ }
+
+ /* Allocate payloads. */
+ Status = XDp_TxAllocatePayloadStreams(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:MST:"
+ "Allocation failed. Check link "
+ "over-subscription and bring down "
+ "resolution or BPC.\n\r");
+ return XST_DATA_LOST;
+ }
+
+ Status = XDp_TxCheckLinkStatus(InstancePtr,
+ InstancePtr->TxInstance.LinkConfig.LaneCount);
+ if (Status == XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:Link "
+ "is up after allocate payload!\n\r\n\r");
+ }
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:Config done!"
+ "\n\r\n\r");
+ }
+ /* SST */
+ else {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"\n\rSS INFO:Starting "
+ "SST config.\n\r");
+
+ /* Reset MST mode in both the RX and TX */
+ Status = XDp_TxMstDisable(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ InstancePtr->TxInstance.MstEnable = 0;
+ }
+
+ /* set AUX and sideband delays in microseconds */
+ InstancePtr->TxInstance.AuxDelayUs = 0;
+ InstancePtr->TxInstance.SbMsgDelayUs = 0;
+
+ /* Enable downshifting during link training */
+ XDp_TxEnableTrainAdaptive(InstancePtr, 1);
+
+ /* Enable redriver on DP output path */
+ XDp_TxSetHasRedriverInPath(InstancePtr, 1);
+
+ /* Disable main stream to force sending of IDLE patterns. */
+ XDp_TxDisableMainLink(InstancePtr);
+
+ /* Start link training with user set link rate and lane
+ * count.
+ */
+ Status = XSs_DpTxStartLink(InstancePtr, FALSE);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:SST:"
+ "Re-training with maximum RX capabilities."
+ "\n\r");
+
+ /* Train link with maximum RX capabilities */
+ Status = XSs_DpTxStartLink(InstancePtr, TRUE);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:SST:"
+ "Verify cable and/or monitor.\n\r");
+ return Status;
+ }
+ }
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"Reading (SST) Sink EDID..."
+ "\n\r");
+
+ /* Get EDID */
+ XDp_TxGetEdid(InstancePtr, Edid);
+
+ if (VidMode == XVIDC_VM_USE_EDID_PREFERRED) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:SST:Using "
+ "preferred EDID resolution.\n\r");
+
+ /* Get preferred video mode from EDID */
+ VidMode = Dp_GetPreferredVm(Edid);
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:SST: VM "
+ "from EDID:%s\n\r",
+ XVidC_GetVideoModeStr(VidMode));
+
+ /* Check whether Video mode exist in VTM table */
+ if (XVIDC_VM_NOT_SUPPORTED == VidMode) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"EDID "
+ "preferred video mode not present. "
+ "Update video timing table.\n\r"
+ "Setting to 640x480 video mode\n\r");
+ VidMode = XVIDC_VM_640x480_60_P;
+ }
+ }
+ else {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:SST:Using "
+ "user set resolution.\n\r");
+
+ /* Check whether VidMode ID is supported */
+ Status = XVidC_EdidIsVideoTimingSupported(Edid,
+ (XVidC_VideoTimingMode *)XVidC_GetVideoModeData(
+ VidMode));
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:SST:"
+ "%s is not supported.\n\rSetting to "
+ "640x480 resolution.\n\r",
+ XVidC_GetVideoModeStr(VidMode));
+ VidMode = XVIDC_VM_640x480_60_P;
+ }
+ }
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:SST:calculating "
+ "payload...\n\r");
+
+ /* Check link and video bandwidth */
+ Status = Dp_CheckBandwidth(InstancePtr, Bpc, VidMode);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:SST:Link is "
+ "over-subscribed for selected resolution, "
+ "bpc, lane count and link rate value.\n\r"
+ "Re-training with maximum RX capabilities."
+ "\n\r");
+
+ /* Check for link training need and run training
+ * sequence.
+ */
+ Status = XSs_DpTxStartLink(InstancePtr, TRUE);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:SST:"
+ "Re-training failed with max "
+ "capabilities after payload "
+ "failure.\n\r");
+ return Status;
+ }
+ }
+
+ /* Reset MSA values */
+ XDp_TxClearMsaValues(InstancePtr, XDP_TX_STREAM_ID1);
+ XDp_TxClearMsaValues(InstancePtr, XDP_TX_STREAM_ID2);
+ XDp_TxClearMsaValues(InstancePtr, XDP_TX_STREAM_ID3);
+ XDp_TxClearMsaValues(InstancePtr, XDP_TX_STREAM_ID4);
+
+ InstancePtr->TxInstance.MsaConfig[0].DynamicRange = 0;
+ InstancePtr->TxInstance.MsaConfig[0].YCbCrColorimetry = 0;
+
+ /* Enable sync clock mode */
+ XDp_TxCfgMsaEnSynchClkMode(InstancePtr,
+ XDP_TX_STREAM_ID1, 1);
+
+ /* Set user provided BPC to stream 1 */
+ XDp_TxCfgMsaSetBpc(InstancePtr, XDP_TX_STREAM_ID1, Bpc);
+
+ /* Set user standard video mode for stream 1 to populate
+ * MSA values
+ */
+ XDp_TxCfgMsaUseStandardVideoMode(InstancePtr,
+ XDP_TX_STREAM_ID1, VidMode);
+
+ /* Set user pixel width if video mode is UHD2 */
+ if ((InstancePtr->TxInstance.MsaConfig[0].Vtm.VmId ==
+ XVIDC_VM_UHD2_60_P) &&
+ (InstancePtr->TxInstance.MsaConfig[
+ 0].OverrideUserPixelWidth == 0)) {
+ InstancePtr->TxInstance.MsaConfig[
+ 0].UserPixelWidth = 4;
+ }
+
+ /* Set video mode */
+ XDp_TxSetVideoMode(InstancePtr, XDP_TX_STREAM_ID1);
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:SST: Config done!"
+ "\n\r\n\r");
+
+ /* Reset the transmitter. */
+ XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_SOFT_RESET,
+ XDP_TX_SOFT_RESET_VIDEO_STREAM_ALL_MASK);
+ XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_SOFT_RESET,
+ 0x0);
+ }
+
+ /* Enable the main link. */
+ XDp_TxEnableMainLink(InstancePtr);
+
+ Status = XDp_TxCheckLinkStatus(InstancePtr,
+ InstancePtr->TxInstance.LinkConfig.LaneCount);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:Link "
+ "is DOWN after main link enabled!\n\r\n\r");
+ }
+ else if (Status == XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:Link "
+ "is UP after main link enabled!\n\r\n\r");
+ }
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:Enabled main link!"
+ "\n\r\n\r");
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function checks if the link needs training and runs the training
+* sequence if training is required based on the flags, indicates to use maximum
+* RX capabilities or user specified link rate, lane count during training.
+*
+* @param InstancePtr is a pointer to the XDp instance.
+* @param TrainMaxCap is a flag indicates whether maximum capabilities
+* to be used during link training.
+* - TRUE - Use maximum RX capabilities.
+* - FALSE - Use custom capabilities.
+*
+* @return
+* - XST_SUCCESS the if main link was successfully established.
+* - XST_FAILURE otherwise.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XSs_DpTxStartLink(XDp *InstancePtr, u8 TrainMaxCap)
+{
+ u32 Status;
+ u32 IntrMask;
+ u8 LinkRate;
+ u8 LaneCount;
+
+ /* Read interrupts */
+ IntrMask = XDp_ReadReg(InstancePtr->Config.BaseAddr,
+ XDP_TX_INTERRUPT_MASK);
+
+ /* Disable HPD pulse interrupts during link training. */
+ XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_INTERRUPT_MASK,
+ IntrMask | XDP_TX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK);
+
+ /* Obtain the capabilities of the RX device by reading the monitor's
+ * DPCD.
+ */
+ Status = XDp_TxGetRxCapabilities(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ XDp_WriteReg(InstancePtr->Config.BaseAddr,
+ XDP_TX_INTERRUPT_MASK, IntrMask);
+ return XST_FAILURE;
+ }
+
+ /* Enable clock spreading for both DP TX and RX device */
+ XDp_TxSetDownspread(InstancePtr, 1);
+
+ /* Enable enhanced framing symbol sequence */
+ XDp_TxSetEnhancedFrameMode(InstancePtr, 1);
+
+ /* Configure link with max values of link rate and lane count
+ * for the first time from next onwards configure it with the
+ * user set values.
+ */
+ if (TrainMaxCap) {
+ /* Configure the main link based on the maximum common
+ * capabilities of the DisplayPort TX core and the
+ * receiver device.
+ */
+ Status = XDp_TxCfgMainLinkMax(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:RX device "
+ "not connected.\n\r");
+ XDp_WriteReg(InstancePtr->Config.BaseAddr,
+ XDP_TX_INTERRUPT_MASK, IntrMask);
+ return XST_FAILURE;
+ }
+ }
+
+ LinkRate = InstancePtr->TxInstance.LinkConfig.LinkRate;
+ LaneCount = InstancePtr->TxInstance.LinkConfig.LaneCount;
+
+ /* Establish link after training process */
+ Status = XDp_TxEstablishLink(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:Training failed."
+ "\n\r");
+ XDp_WriteReg(InstancePtr->Config.BaseAddr,
+ XDP_TX_INTERRUPT_MASK, IntrMask);
+
+ return XST_FAILURE;
+ }
+
+ /* Check whether link rate downshifted */
+ if (LinkRate != InstancePtr->TxInstance.LinkConfig.LinkRate) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS Warning! Link rate is "
+ "downshifted.\n\r");
+ }
+
+ /* Check whether lane count downshifted */
+ if (LaneCount != InstancePtr->TxInstance.LinkConfig.LaneCount) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS Warning! Lane count is "
+ "downshifted.\n\r");
+ }
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:Training passed at link rate:"
+ "0x%02x lane count:%d.\n\r",
+ InstancePtr->TxInstance.LinkConfig.LinkRate,
+ InstancePtr->TxInstance.LinkConfig.LaneCount);
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:VS:%d (TX:%ld) PE:%d (TX:%ld)"
+ "\n\r", InstancePtr->TxInstance.LinkConfig.VsLevel,
+ XDp_ReadReg(InstancePtr->Config.BaseAddr,
+ XDP_TX_PHY_VOLTAGE_DIFF_LANE_0),
+ InstancePtr->TxInstance.LinkConfig.PeLevel,
+ XDp_ReadReg(InstancePtr->Config.BaseAddr,
+ XDP_TX_PHY_POSTCURSOR_LANE_0));
+
+ /* Enable HPD interrupts after link training. */
+ XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_INTERRUPT_MASK,
+ IntrMask);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function calculates the video bandwidth and link bandwidth in single
+* stream and millstream mode. It checks whether the link bandwidth is not
+* over-subscribed for video bandwidth.
+*
+* @param InstancePtr is a pointer to the XDp instance.
+* @param Bpc is the new number of bits per color to use.
+* @param VidMode is one of the enumerated standard video modes
+* defined in xvidc.h file.
+*
+* @return
+* - XST_SUCCESS if link bandwidth is not over-subscribed.
+* - XST_FAILURE otherwise.
+*
+* @note Check that the stream allocation will succeed based on
+* capabilities. Don't go through training and allocation sequence
+* if the pre-calculations indicate that it will fail
+*
+******************************************************************************/
+static u32 Dp_CheckBandwidth(XDp *InstancePtr, u8 Bpc, XVidC_VideoMode VidMode)
+{
+ u32 MstCapable;
+ u32 LinkBw = (InstancePtr->TxInstance.LinkConfig.LaneCount *
+ InstancePtr->TxInstance.LinkConfig.LinkRate * 27);
+ u8 BitsPerPixel = 3 * Bpc;
+
+ /* Check for maximum link rate supported */
+ if (InstancePtr->TxInstance.LinkConfig.MaxLinkRate <
+ InstancePtr->TxInstance.LinkConfig.LinkRate) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS:INFO:Requested link rate "
+ "exceeds maximum capabilities.\n\rMaximum link "
+ "rate = ");
+
+ /* Report maximum link rate supported */
+ switch (InstancePtr->TxInstance.LinkConfig.MaxLinkRate) {
+ case XDP_TX_LINK_BW_SET_540GBPS:
+ xdbg_printf(XDBG_DEBUG_GENERAL,"5.40 Gbps."
+ "\n\r");
+ break;
+
+ case XDP_TX_LINK_BW_SET_270GBPS:
+ xdbg_printf(XDBG_DEBUG_GENERAL,"2.70 Gbps."
+ "\n\r");
+ break;
+
+ case XDP_TX_LINK_BW_SET_162GBPS:
+ xdbg_printf(XDBG_DEBUG_GENERAL,"1.62 Gbps."
+ "\n\r");
+ break;
+ }
+
+ return XST_FAILURE;
+ }
+ else if (InstancePtr->TxInstance.LinkConfig.MaxLaneCount <
+ InstancePtr->TxInstance.LinkConfig.LaneCount) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:Requested lane count "
+ "exceeds maximum capabilities.\n\tMaximum lane count "
+ "= %d.\n\r",
+ InstancePtr->TxInstance.LinkConfig.MaxLaneCount);
+ return XST_BUFFER_TOO_SMALL;
+ }
+
+ /* Check MST mode */
+ MstCapable = XDp_TxMstCapable(InstancePtr);
+
+ /* This check is done so that this function check can be called from
+ * anywhere and it will precaculate the required total timeslots based
+ * on the number of sinks and MSA values.
+ * This works because if the example will always run in MST mode if
+ * the monitor is capable of it, otherwise in SST mode.
+ */
+ if ((MstCapable != XST_SUCCESS) ||
+ (InstancePtr->TxInstance.MstEnable == 0)) {
+ u32 TransferUnitSize = 64;
+ u32 VideoBw = (XVidC_GetPixelClockHzByVmId(VidMode) / 1000) *
+ BitsPerPixel / 8;
+ u32 AvgBytesPerTU = (VideoBw * TransferUnitSize) / LinkBw;
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS:INFO:Checking link "
+ "bandwidth validity for SST.\n\r");
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: Link bandwidth = "
+ "%ld Kbps and video bandwidth = %ld Kbps\n\r",
+ (LinkBw * 1000), VideoBw);
+
+ if (AvgBytesPerTU > (TransferUnitSize * 1000)) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:SST link is "
+ "over-subscribed.\n\r");
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:Link "
+ "bandwidth = %ld Kbps and video bandwidth = "
+ "%ld Kbps\n\r", (LinkBw * 1000), VideoBw);
+
+ return XST_BUFFER_TOO_SMALL;
+ }
+ }
+ else if ((MstCapable == XST_SUCCESS) &&
+ (InstancePtr->TxInstance.MstEnable == 1)) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:Checking link "
+ "bandwidth validity for MST\n\r");
+
+ u8 StreamIndex;
+ u32 TimeSlots;
+ u32 TotalTimeSlots = 0;
+ double PeakPixelBw;
+ double Average_StreamSymbolTimeSlotsPerMTP;
+ double Target_Average_StreamSymbolTimeSlotsPerMTP;
+ double MaximumTarget_Average_StreamSymbolTimeSlotsPerMTP;
+ u32 TsInt;
+ u32 TsFrac;
+ u16 Pbn;
+
+ PeakPixelBw = ((double)XVidC_GetPixelClockHzByVmId(VidMode) /
+ 1000000) * ((double)BitsPerPixel / 8);
+
+ Pbn = 1.006 * PeakPixelBw * ((double)64 / 54);
+
+ if ((double)(1.006 * PeakPixelBw * ((double)64 / 54)) >
+ ((double)Pbn)) {
+ Pbn++;
+ }
+
+ Average_StreamSymbolTimeSlotsPerMTP = (64.0 * PeakPixelBw /
+ LinkBw);
+ MaximumTarget_Average_StreamSymbolTimeSlotsPerMTP = (54.0 *
+ ((double)Pbn / LinkBw));
+
+ Target_Average_StreamSymbolTimeSlotsPerMTP =
+ (u32)Average_StreamSymbolTimeSlotsPerMTP;
+ Target_Average_StreamSymbolTimeSlotsPerMTP += ((1.0 / 8.0) *
+ (u32)(8.0 *
+ (MaximumTarget_Average_StreamSymbolTimeSlotsPerMTP -
+ Target_Average_StreamSymbolTimeSlotsPerMTP)));
+
+ TsInt = Target_Average_StreamSymbolTimeSlotsPerMTP;
+ TsFrac = (((double)Target_Average_StreamSymbolTimeSlotsPerMTP *
+ 1000) - (TsInt * 1000));
+
+ TimeSlots = TsInt;
+ if (TsFrac != 0) {
+ TimeSlots++;
+ }
+ if ((InstancePtr->Config.PayloadDataWidth == 4) &&
+ (TimeSlots % 4) != 0) {
+ TimeSlots += (4 - (TimeSlots % 4));
+ }
+ else if ((TimeSlots % 2) != 0) {
+ TimeSlots++;
+ }
+
+ /* Add up all the timeslots. */
+ for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) {
+ if (XDp_TxMstStreamIsEnabled(InstancePtr,
+ StreamIndex + 1)) {
+ TotalTimeSlots += TimeSlots;
+ }
+ }
+
+ if (TotalTimeSlots > 63) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: MST "
+ "link over-subscribed.\n\rTotal time slots "
+ "required: %ld for %ld streams.\n\rOnly 63 "
+ "time slots are available.\n\r",
+ TotalTimeSlots, TotalTimeSlots / TimeSlots);
+
+ return XST_FAILURE;
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function discovers the topology and finds the actual number of sinks.
+* It enables streams corresponding to each sink found during topology
+* discovery.
+*
+* @param InstancePtr is a pointer to the XDp instance.
+*
+* @return
+* - XST_SUCCESS if topology discovered successfully.
+* - XST_FAILURE if topology discovery failed.
+*
+* @note None.
+*
+******************************************************************************/
+static u32 Dp_GetTopology(XDp *InstancePtr)
+{
+ u32 Status;
+ u8 NumStreams;
+
+ /* Clear node and sink */
+ InstancePtr->TxInstance.Topology.NodeTotal = 0;
+ InstancePtr->TxInstance.Topology.SinkTotal = 0;
+
+ /* Discover topology and find total sinks */
+ Status = XDp_TxDiscoverTopology(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:MST:Topology failed:"
+ "%ld.\n\r", Status);
+ return XST_FAILURE;
+ }
+
+ /* Total number of streams equivalent to number of sinks found */
+ NumStreams = InstancePtr->TxInstance.Topology.SinkTotal;
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:No of streams based on "
+ "topology discovery is = %d\n\r", NumStreams);
+
+ if (NumStreams > InstancePtr->Config.NumMstStreams) {
+ NumStreams = InstancePtr->Config.NumMstStreams;
+ }
+
+ Status = XDp_TxCheckLinkStatus(InstancePtr,
+ InstancePtr->TxInstance.LinkConfig.LaneCount);
+ if (Status == XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:MST:Link "
+ "is up after topology discovery!\n\r\n\r");
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function retrieves preferred timing mode information from the EDID
+* to identify video mode or resolution.
+*
+* @param EdidPtr is the supplied base EDID to retrieve timing values.
+*
+* @return Id of a supported video mode.
+*
+* @note None.
+*
+******************************************************************************/
+static XVidC_VideoMode Dp_GetPreferredVm(u8 *EdidPtr)
+{
+ u8 *Ptm;
+ u16 HBlank;
+ u16 VBlank;
+ u32 PixelClockHz;
+ XVidC_FrameRate FrameRate;
+ XVidC_VideoTiming Timing;
+ XVidC_VideoMode VmId;
+
+ (void)memset((void *)&Timing, 0, sizeof(XVidC_VideoTiming));
+
+ Ptm = &EdidPtr[XDP_EDID_PTM];
+
+ HBlank = ((Ptm[XDP_EDID_DTD_HRES_HBLANK_U4] &
+ XDP_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) |
+ Ptm[XDP_EDID_DTD_HBLANK_LSB];
+
+ VBlank = ((Ptm[XDP_EDID_DTD_VRES_VBLANK_U4] &
+ XDP_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) |
+ Ptm[XDP_EDID_DTD_VBLANK_LSB];
+
+ Timing.HActive = (((Ptm[XDP_EDID_DTD_HRES_HBLANK_U4] &
+ XDP_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >>
+ XDP_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
+ Ptm[XDP_EDID_DTD_HRES_LSB];
+
+ Timing.VActive = (((Ptm[XDP_EDID_DTD_VRES_VBLANK_U4] &
+ XDP_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >>
+ XDP_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
+ Ptm[XDP_EDID_DTD_VRES_LSB];
+
+ PixelClockHz = (((Ptm[XDP_EDID_DTD_PIXEL_CLK_KHZ_MSB] <<
+ 8) | Ptm[XDP_EDID_DTD_PIXEL_CLK_KHZ_LSB]) * 10) * 1000;
+
+ Timing.HFrontPorch = (((Ptm[XDP_EDID_DTD_XFPORCH_XSPW_U2] &
+ XDP_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK) >>
+ XDP_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT) << 8) |
+ Ptm[XDP_EDID_DTD_HFPORCH_LSB];
+
+ Timing.HSyncWidth = (((Ptm[XDP_EDID_DTD_XFPORCH_XSPW_U2] &
+ XDP_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK) >>
+ XDP_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT) << 8) |
+ Ptm[XDP_EDID_DTD_HSPW_LSB];
+
+ Timing.F0PVFrontPorch = (((Ptm[XDP_EDID_DTD_XFPORCH_XSPW_U2] &
+ XDP_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK) >>
+ XDP_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT) << 8) |
+ ((Ptm[XDP_EDID_DTD_VFPORCH_VSPW_L4] &
+ XDP_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK) >>
+ XDP_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT);
+
+ Timing.F0PVSyncWidth = ((Ptm[XDP_EDID_DTD_XFPORCH_XSPW_U2] &
+ XDP_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK) << 8) |
+ (Ptm[XDP_EDID_DTD_VFPORCH_VSPW_L4] &
+ XDP_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK);
+
+ /* Compute video mode timing values. */
+ Timing.HBackPorch = HBlank - (Timing.HFrontPorch + Timing.HSyncWidth);
+ Timing.F0PVBackPorch = VBlank - (Timing.F0PVFrontPorch +
+ Timing.F0PVSyncWidth);
+ Timing.HTotal = (Timing.HSyncWidth + Timing.HFrontPorch +
+ Timing.HActive + Timing.HBackPorch);
+ Timing.F0PVTotal = (Timing.F0PVSyncWidth + Timing.F0PVFrontPorch +
+ Timing.VActive + Timing.F0PVBackPorch);
+ FrameRate = PixelClockHz / (Timing.HTotal * Timing.F0PVTotal);
+
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:"
+ "HAct:%d, VAct:%d, FR:%d\n\r", Timing.HActive,
+ Timing.VActive, FrameRate);
+
+ /* Few monitors returns 59 HZ. Hence, setting to 60. */
+ if (FrameRate == 59) {
+ FrameRate = 60;
+ }
+
+ /* Get video mode ID */
+ VmId = XVidC_GetVideoModeId(Timing.HActive, Timing.VActive,
+ FrameRate, XVidC_EdidIsDtdPtmInterlaced(EdidPtr));
+
+ return VmId;
+}
diff --git a/XilinxProcessorIPLib/drivers/dptxss/src/dp/xss_dptx.h b/XilinxProcessorIPLib/drivers/dptxss/src/dp/xss_dptx.h
new file mode 100644
index 00000000..f741f149
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/src/dp/xss_dptx.h
@@ -0,0 +1,85 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xss_dptx.h
+*
+* This is the header file for Xilinx DisplayPort Transmitter Subsystem
+* sub-core, is DisplayPort in TX mode of operation.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ---- --- -------- --------------------------------------------------
+* 1.00 sha 01/29/15 Initial release.
+*
+*
+******************************************************************************/
+#ifndef XSS_DPTX_H_
+#define XSS_DPTX_H_ /**< Prevent circular inclusions
+ * by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xdp.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XSS_DPTX_MST 1 /**< Multi-Stream Transport */
+#define XSS_DPTX_SST 0 /**< Single Stream Transport */
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+u32 XSs_DpTxStart(XDp *InstancePtr, u8 TransportMode, u8 Bpc,
+ XVidC_VideoMode VidMode);
+u32 XSs_DpTxStartLink(XDp *InstancePtr, u8 TrainMaxCap);
+
+/************************** Variable Declarations ****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro */
diff --git a/XilinxProcessorIPLib/drivers/dptxss/src/dualsplitter/xss_dualsplitter.c b/XilinxProcessorIPLib/drivers/dptxss/src/dualsplitter/xss_dualsplitter.c
new file mode 100644
index 00000000..80d9d0a7
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/src/dualsplitter/xss_dualsplitter.c
@@ -0,0 +1,143 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xss_dualsplitter.c
+*
+* This file contains a minimal set of functions for the Dual Splitter core
+* to configure.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ---- --- -------- --------------------------------------------------
+* 1.00 sha 01/29/15 Initial release.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xss_dualsplitter.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+/*****************************************************************************/
+/**
+*
+* This function configures dual splitter with required parameters based on
+* number of streams.
+*
+* @param InstancePtr is a pointer to the XDualSplitter core instance.
+* @param VertSplit specifies a TURE/FALSE flag to indicate whether the
+* core need to program in split mode or bypass mode respectively.
+* @param MsaConfig is a pointer to main stream attributes structure
+* that will be used to extract timing values.
+*
+* @return
+* - XST_SUCCESS if Dual Splitter configured successfully.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XSs_DsSetup(XDualSplitter *InstancePtr, u8 VertSplit,
+ XDp_TxMainStreamAttributes *MsaConfig)
+{
+ u8 ISamples;
+ u8 OSamples;
+ u8 ImgSegments;
+ u8 Overlap;
+ u16 Height;
+ u16 Width;
+ u32 UserPixelWidth;
+ XVidC_VideoMode VmId;
+
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(MsaConfig != NULL);
+ Xil_AssertNonvoid((VertSplit == TRUE) || (VertSplit == FALSE));
+
+ UserPixelWidth = MsaConfig->UserPixelWidth;
+ VmId = MsaConfig->Vtm.VmId;
+ Height = MsaConfig->Vtm.Timing.VActive;
+
+ /* Dual Splitter register update enable */
+ XDualSplitter_RegUpdateEnable(InstancePtr);
+
+ /* Required parameters based on vertical split mode and 4k2k@60p */
+ if ((VertSplit) && (VmId == XVIDC_VM_UHD2_60_P)) {
+ ImgSegments = 0x2;
+ OSamples = 0x4;
+ ISamples = 0x4;
+ Width = MsaConfig->Vtm.Timing.HActive / 2;
+ }
+ else {
+ ImgSegments = 0x1;
+ OSamples = 0x4;
+ ISamples = 0x4;
+ Width = MsaConfig->Vtm.Timing.HActive / UserPixelWidth;
+ }
+
+ /* overlap is common for streams */
+ Overlap = 0x0;
+
+ /* set stream parameters */
+ XDualSplitter_SetImgParam(InstancePtr, ISamples, OSamples, ImgSegments,
+ Overlap);
+
+ /* Update width x height resolution */
+ XDualSplitter_SetImageSize(InstancePtr, Height, Width);
+
+ /* Enable Dual Splitter */
+ XDualSplitter_Enable(InstancePtr);
+
+ return XST_SUCCESS;
+}
+#endif
diff --git a/XilinxProcessorIPLib/drivers/dptxss/src/dualsplitter/xss_dualsplitter.h b/XilinxProcessorIPLib/drivers/dptxss/src/dualsplitter/xss_dualsplitter.h
new file mode 100644
index 00000000..164d270e
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/src/dualsplitter/xss_dualsplitter.h
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xss_dualsplitter.h
+*
+* This is the header file for Xilinx DisplayPort Transmitter Subsystem
+* sub-core, is Dual Splitter.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ---- --- -------- --------------------------------------------------
+* 1.00 sha 01/29/15 Initial release.
+*
+*
+******************************************************************************/
+#ifndef XSS_DUALSPLITTER_H_
+#define XSS_DUALSPLITTER_H_ /**< Prevent circular inclusions
+ * by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+#include "xdualsplitter.h"
+#endif
+#include "xdp.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+u32 XSs_DsSetup(XDualSplitter *InstancePtr, u8 NumStreams,
+ XDp_TxMainStreamAttributes *MsaConfig);
+#endif
+
+/************************** Variable Declarations ****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro */
diff --git a/XilinxProcessorIPLib/drivers/dptxss/src/vtc/xss_vtc.c b/XilinxProcessorIPLib/drivers/dptxss/src/vtc/xss_vtc.c
new file mode 100644
index 00000000..2e6300b2
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/src/vtc/xss_vtc.c
@@ -0,0 +1,200 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xss_vtc.c
+*
+* This file contains a minimal set of functions for the Video Timing controller
+* core to configure.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ---- --- -------- --------------------------------------------------
+* 1.00 sha 01/29/15 Initial release.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xss_vtc.h"
+#include "string.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function configures Video Timing Controller with video timing
+* parameters from MSA config structure.
+*
+* @param InstancePtr is a pointer to the XVtc instance.
+* @param MsaConfig is a pointer to main stream attributes structure
+* that will be used to extract timing values.
+*
+* @return
+* - XST_SUCCESS if video timing parameters set successfully.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XSs_VtcSetup(XVtc *InstancePtr, XDp_TxMainStreamAttributes *MsaConfig)
+{
+ u32 UserPixelWidth;
+
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(MsaConfig != NULL);
+
+ /* Polarity configuration */
+ XVtc_Polarity Polarity;
+ XVtc_SourceSelect SourceSelect;
+ XVtc_Timing VideoTiming;
+
+ /* user pixel width */
+ UserPixelWidth = MsaConfig->UserPixelWidth;
+
+ /* Disable Generator */
+ XVtc_Reset(InstancePtr);
+ XVtc_DisableGenerator(InstancePtr);
+ XVtc_Disable(InstancePtr);
+
+ /* Set up source select */
+ memset((void *)&SourceSelect, 0, sizeof(SourceSelect));
+
+ /* 1 = Generator registers, 0 = Detector registers */
+ SourceSelect.VChromaSrc = 1;
+ SourceSelect.VActiveSrc = 1;
+ SourceSelect.VBackPorchSrc = 1;
+ SourceSelect.VSyncSrc = 1;
+ SourceSelect.VFrontPorchSrc = 1;
+ SourceSelect.VTotalSrc = 1;
+ SourceSelect.HActiveSrc = 1;
+ SourceSelect.HBackPorchSrc = 1;
+ SourceSelect.HSyncSrc = 1;
+ SourceSelect.HFrontPorchSrc = 1;
+ SourceSelect.HTotalSrc = 1;
+
+ /* Set source */
+ XVtc_SetSource(InstancePtr, &SourceSelect);
+
+ /* Horizontal timing */
+ VideoTiming.HActiveVideo =
+ MsaConfig->Vtm.Timing.HActive / UserPixelWidth;
+ VideoTiming.HFrontPorch =
+ MsaConfig->Vtm.Timing.HFrontPorch / UserPixelWidth;
+ VideoTiming.HSyncWidth =
+ MsaConfig->Vtm.Timing.HSyncWidth / UserPixelWidth;
+ VideoTiming.HBackPorch =
+ MsaConfig->Vtm.Timing.HBackPorch / UserPixelWidth;
+ VideoTiming.HSyncPolarity =
+ MsaConfig->Vtm.Timing.HSyncPolarity;
+
+ /* Vertical timing */
+ VideoTiming.VActiveVideo = MsaConfig->Vtm.Timing.VActive;
+ VideoTiming.V0FrontPorch = MsaConfig->Vtm.Timing.F0PVFrontPorch;
+ VideoTiming.V0SyncWidth = MsaConfig->Vtm.Timing.F0PVSyncWidth;
+ VideoTiming.V0BackPorch = MsaConfig->Vtm.Timing.F0PVBackPorch;
+ VideoTiming.V1FrontPorch = MsaConfig->Vtm.Timing.F1VFrontPorch;
+ VideoTiming.V1SyncWidth = MsaConfig->Vtm.Timing.F1VSyncWidth;
+ VideoTiming.V1BackPorch = MsaConfig->Vtm.Timing.F1VBackPorch;
+ VideoTiming.VSyncPolarity = MsaConfig->Vtm.Timing.VSyncPolarity;
+
+ /* Check for interlaced mode */
+ VideoTiming.Interlaced = XVidC_VideoTimingModes[
+ MsaConfig->Vtm.VmId].Timing.F1VTotal == 0 ? 0: 1;
+
+ /* Set timing */
+ XVtc_SetGeneratorTiming(InstancePtr, &VideoTiming);
+
+ /* Set up Polarity of all outputs */
+ memset((void *)&Polarity, 0, sizeof(XVtc_Polarity));
+ Polarity.ActiveChromaPol = 1;
+ Polarity.ActiveVideoPol = 1;
+
+ if (VideoTiming.Interlaced) {
+ Polarity.FieldIdPol = 1;
+ }
+ else {
+ Polarity.FieldIdPol = 0;
+ }
+
+ Polarity.VBlankPol = VideoTiming.VSyncPolarity;
+ Polarity.VSyncPol = VideoTiming.VSyncPolarity;
+ Polarity.HBlankPol = VideoTiming.HSyncPolarity;
+ Polarity.HSyncPol = VideoTiming.HSyncPolarity;
+
+ /* Set polarity */
+ XVtc_SetPolarity(InstancePtr, &Polarity);
+
+ /* VTC driver does not take care of the setting of the VTC in
+ * interlaced operation. As a work around the register
+ * is set manually */
+ if (VideoTiming.Interlaced) {
+ /* Interlaced mode */
+ XVtc_WriteReg(InstancePtr->Config.BaseAddress,
+ XVTC_GFENC_OFFSET, 0x42);
+ }
+ else {
+ /* Progressive mode */
+ XVtc_WriteReg(InstancePtr->Config.BaseAddress,
+ XVTC_GFENC_OFFSET, 0x2);
+ }
+
+ XVtc_WriteReg(InstancePtr->Config.BaseAddress,
+ XVTC_GPOL_OFFSET, 0x3F);
+
+ /* Enable generator module */
+ XVtc_Enable(InstancePtr);
+ XVtc_EnableGenerator(InstancePtr);
+ XVtc_RegUpdateEnable(InstancePtr);
+
+ return XST_SUCCESS;
+}
diff --git a/XilinxProcessorIPLib/drivers/dptxss/src/vtc/xss_vtc.h b/XilinxProcessorIPLib/drivers/dptxss/src/vtc/xss_vtc.h
new file mode 100644
index 00000000..fd011a1e
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/src/vtc/xss_vtc.h
@@ -0,0 +1,82 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xss_vtc.h
+*
+* This is the header file for Xilinx DisplayPort Transmitter Subsystem
+* sub-core, is Video Timing Controller.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ---- --- -------- --------------------------------------------------
+* 1.00 sha 01/29/15 Initial release.
+*
+*
+******************************************************************************/
+#ifndef XSS_VTC_H_
+#define XSS_VTC_H_ /**< Prevent circular inclusions
+ * by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xvtc.h"
+#include "xdp.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+u32 XSs_VtcSetup(XVtc *InstancePtr, XDp_TxMainStreamAttributes *MsaConfig);
+
+/************************** Variable Declarations ****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro */
diff --git a/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss.c b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss.c
new file mode 100644
index 00000000..4f3c6610
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss.c
@@ -0,0 +1,923 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdptxss.c
+*
+* This is the main file for Xilinx DisplayPort Transmitter Subsystem driver.
+* This file contains a minimal set of functions for the XDpTxSs driver that
+* allow access to all of the DisplayPort Transmitter Subsystem core's
+* functionality. Please see xdptxss.h for more details of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ---- --- -------- --------------------------------------------------
+* 1.00 sha 01/29/15 Initial release.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdptxss.h"
+#include "string.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* Subsystem sub-core's structure includes instances of each sub-cores */
+typedef struct {
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+ XDualSplitter DsInst;
+#endif
+ XDp DpInst;
+ XVtc VtcInst[XDPTXSS_NUM_STREAMS];
+} XDpTxSs_SubCores;
+
+/************************** Function Prototypes ******************************/
+
+static void DpTxSs_GetIncludedSubCores(XDpTxSs *InstancePtr);
+
+/************************** Variable Definitions *****************************/
+
+XDpTxSs_SubCores DpTxSsSubCores;
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function initializes the DisplayPort Transmitter Subsystem core. This
+* function must be called prior to using the core. Initialization of the core
+* includes setting up the instance data and ensuring the hardware is in a
+* quiescent state.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+* @param CfgPtr points to the configuration structure associated with
+* the DisplayPort TX Subsystem core.
+* @param EffectiveAddr is the base address of the device. If address
+* translation is being used, then this parameter must reflect the
+* virtual base address. Otherwise, the physical address should be
+* used.
+*
+* @return
+* - XST_DEVICE_NOT_FOUND if sub-core not found.
+* - XST_FAILURE if sub-core initialization failed.
+* - XST_SUCCESS if XDptxss_CfgInitialize successful.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XDpTxSs_CfgInitialize(XDpTxSs *InstancePtr, XDpTxSs_Config *CfgPtr,
+ u32 EffectiveAddr)
+{
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+ XDualSplitter_Config DualConfig;
+#endif
+ XDp_Config DpConfig;
+ XVtc_Config VtcConfig;
+ u32 Status;
+ u32 Index;
+
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(CfgPtr != NULL);
+ Xil_AssertNonvoid(EffectiveAddr != (u32)0x0);
+
+ /* Setup the instance */
+ (void)memset((void *)InstancePtr, 0, sizeof(XDpTxSs));
+ (void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr,
+ sizeof(XDpTxSs_Config));
+
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+ /* Get included sub cores in the DisplayPort TX Subsystem */
+ DpTxSs_GetIncludedSubCores(InstancePtr);
+
+ /* Check for DisplayPort availability */
+ if (InstancePtr->DpPtr) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: Initializing "
+ "DisplayPort Transmitter IP\n\r");
+
+ /* Assign number of streams to one when MST is not enabled */
+ if (InstancePtr->Config.MstSupport) {
+ InstancePtr->UsrOpt.NumOfStreams =
+ InstancePtr->Config.NumMstStreams;
+ }
+ else {
+ InstancePtr->Config.DpSubCore.DpConfig.NumMstStreams =
+ 1;
+ InstancePtr->UsrOpt.NumOfStreams = 1;
+ InstancePtr->Config.NumMstStreams = 1;
+ }
+
+ /* Calculate absolute base address of DP sub-core */
+ InstancePtr->Config.DpSubCore.DpConfig.BaseAddr +=
+ InstancePtr->Config.BaseAddress;
+ (void)memcpy((void *)&(DpConfig),
+ (const void *)&CfgPtr->DpSubCore.DpConfig,
+ sizeof(XDp_Config));
+
+ /* DisplayPort config initialize */
+ DpConfig.BaseAddr += InstancePtr->Config.BaseAddress;
+ XDp_CfgInitialize(InstancePtr->DpPtr, &DpConfig,
+ DpConfig.BaseAddr);
+ Status = XDp_Initialize(InstancePtr->DpPtr);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: DP TX "
+ "initialization failed!\n\r");
+ return XST_FAILURE;
+ }
+
+ /* Initialize user configurable parameters */
+ InstancePtr->UsrOpt.VmId = XVIDC_VM_USE_EDID_PREFERRED;
+ InstancePtr->UsrOpt.Bpc = InstancePtr->Config.MaxBpc;
+ InstancePtr->UsrOpt.MstSupport =
+ InstancePtr->Config.MstSupport;
+ }
+
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+ /* Check for Dual Splitter availability */
+ if ((InstancePtr->DsPtr != NULL) && (InstancePtr->Config.MstSupport)) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: Initializing Dual "
+ "Splitter IP\n\r");
+
+ /* Calculate absolute base address of Dual Splitter sub-core */
+ InstancePtr->Config.DsSubCore.DsConfig.BaseAddress +=
+ InstancePtr->Config.BaseAddress;
+
+ (void)memcpy((void *)&(DualConfig),
+ (const void *)&CfgPtr->DsSubCore.DsConfig,
+ sizeof(XDualSplitter_Config));
+
+ /* Dual Splitter config initialize */
+ DualConfig.BaseAddress += InstancePtr->Config.BaseAddress;
+ Status = XDualSplitter_CfgInitialize(InstancePtr->DsPtr,
+ &DualConfig, DualConfig.BaseAddress);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: Dual "
+ "Splitter initialization failed \n\r");
+ return XST_FAILURE;
+ }
+ }
+#endif
+
+ /* Initialize VTC equal to number of streams */
+ for (Index = 0; Index < InstancePtr->Config.NumMstStreams; Index++) {
+ if (InstancePtr->VtcPtr[Index]) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: "
+ "Initializing VTC%d IP \n\r", Index);
+
+ /* Calculate absolute base address of VTC sub-core */
+ InstancePtr->Config.VtcSubCore[
+ Index].VtcConfig.BaseAddress +=
+ InstancePtr->Config.BaseAddress;
+
+ (void)memcpy((void *)&(VtcConfig),
+ (const void *)&CfgPtr->VtcSubCore[Index].VtcConfig,
+ sizeof(XVtc_Config));
+
+ /* VTC config initialize */
+ VtcConfig.BaseAddress +=
+ InstancePtr->Config.BaseAddress;
+ Status = XVtc_CfgInitialize(InstancePtr->VtcPtr[Index],
+ &VtcConfig, VtcConfig.BaseAddress);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: "
+ "VTC%d initialization failed!\n\r",
+ Index);
+ return XST_FAILURE;
+ }
+ }
+ }
+
+ /* Reset the hardware and set the flag to indicate the
+ * subsystem is ready
+ */
+ XDpTxSs_Reset(InstancePtr);
+ InstancePtr->IsReady = (u32)XIL_COMPONENT_IS_READY;
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resets the DisplayPort Transmitter Subsystem including all
+* sub-cores.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDpTxSs_Reset(XDpTxSs *InstancePtr)
+{
+ u32 Index;
+
+ /* Verify argument. */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /* Reset the DisplayPort. */
+ XDpTxSs_WriteReg(InstancePtr->Config.DpSubCore.DpConfig.BaseAddr,
+ XDP_TX_SOFT_RESET, XDP_TX_SOFT_RESET_VIDEO_STREAM_ALL_MASK);
+ XDpTxSs_WriteReg(InstancePtr->Config.DpSubCore.DpConfig.BaseAddr,
+ XDP_TX_SOFT_RESET, 0x0);
+
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+ /* Reset Dual Splitter */
+ if (InstancePtr->DsPtr) {
+ XDualSplitter_Reset(InstancePtr->DsPtr);
+ }
+#endif
+
+ for (Index = 0; Index < InstancePtr->Config.NumMstStreams; Index++) {
+ /* Reset VTC's */
+ if (InstancePtr->VtcPtr[Index]) {
+ XVtc_Reset(InstancePtr->VtcPtr[Index]);
+ }
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* This function starts the DisplayPort Transmitter Subsystem including all
+* sub-cores.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return
+* - XST_SUCCESS, if DP TX Subsystem and its included sub-cores
+* configured successfully.
+* - XST_FAILURE, otherwise.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XDpTxSs_Start(XDpTxSs *InstancePtr)
+{
+ u32 Status;
+ u32 Index;
+ u8 SinkTotal;
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+ u8 VertSplit;
+#endif
+
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid((InstancePtr->UsrOpt.MstSupport == 0) ||
+ (InstancePtr->UsrOpt.MstSupport == 1));
+
+ /* Check for downstream device connected */
+ if (!XDp_TxIsConnected(InstancePtr->DpPtr)) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: RX device "
+ "is not connected!\n\r");
+ return XST_FAILURE;
+ }
+
+ /* Check RX device is MST capable */
+ Status = XDp_TxMstCapable(InstancePtr->DpPtr);
+ if ((Status == XST_SUCCESS) && (InstancePtr->Config.MstSupport)) {
+ if (InstancePtr->UsrOpt.MstSupport <
+ InstancePtr->Config.MstSupport) {
+ /* Enable SST mode when RX is MST */
+ InstancePtr->UsrOpt.MstSupport = 0;
+
+ /* set maximum number of streams to one */
+ InstancePtr->UsrOpt.NumOfStreams = 1;
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: Setting "
+ "to SST even though RX device is with MST "
+ "capable!\n\r");
+ }
+ else {
+ /* Enable MST mode */
+ InstancePtr->UsrOpt.MstSupport =
+ InstancePtr->Config.MstSupport;
+
+ /* Restore maximum number of supported streams */
+ InstancePtr->UsrOpt.NumOfStreams =
+ InstancePtr->Config.NumMstStreams;
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: RX device "
+ "is with MST capable!\n\r");
+ }
+ }
+ else {
+ /* Enable SST mode */
+ InstancePtr->UsrOpt.MstSupport = 0;
+
+ /* set maximum number of streams to one */
+ InstancePtr->UsrOpt.NumOfStreams = 1;
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: RX device "
+ "is with SST capable. OR Design supports only SST "
+ "mode.\n\r");
+ }
+
+ /* Start DisplayPort sub-core configuration */
+ Status = XSs_DpTxStart(InstancePtr->DpPtr,
+ InstancePtr->UsrOpt.MstSupport,
+ InstancePtr->UsrOpt.Bpc,
+ InstancePtr->UsrOpt.VmId);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: DP Start failed "
+ "in %s!\n\r",
+ InstancePtr->UsrOpt.MstSupport?"MST":"SST");
+ return Status;
+ }
+
+ /* Align video mode being set in DisplayPort */
+ InstancePtr->UsrOpt.VmId =
+ InstancePtr->DpPtr->TxInstance.MsaConfig[0].Vtm.VmId;
+
+ /* Set number of stream to number of sinks found. Make sure that sink
+ * total does not exceed total number supported streams in by Subsystem
+ * configuration.
+ */
+ if (InstancePtr->UsrOpt.MstSupport) {
+ SinkTotal = InstancePtr->DpPtr->TxInstance.Topology.SinkTotal;
+ InstancePtr->UsrOpt.NumOfStreams =
+ (SinkTotal > InstancePtr->UsrOpt.NumOfStreams)?
+ InstancePtr->UsrOpt.NumOfStreams:SinkTotal;
+ }
+
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+ if (InstancePtr->DsPtr) {
+ /* Check video mode and MST support */
+ if ((InstancePtr->UsrOpt.VmId == XVIDC_VM_UHD2_60_P)
+ && (InstancePtr->UsrOpt.MstSupport)) {
+
+ /* Vertical split mode */
+ VertSplit = (TRUE);
+ }
+ else {
+ /* Bypass mode */
+ VertSplit = (FALSE);
+ }
+
+ /* Setup Dual Splitter in either bypass/vertical split mode */
+ Status = XSs_DsSetup(InstancePtr->DsPtr, VertSplit,
+ &InstancePtr->DpPtr->TxInstance.MsaConfig[0]);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: DS start "
+ "failed!\n\r");
+ return Status;
+ }
+ }
+#endif
+
+ /* Setup VTC */
+ for (Index = 0; Index < InstancePtr->UsrOpt.NumOfStreams; Index++) {
+ if (InstancePtr->VtcPtr[Index]) {
+ Status = XSs_VtcSetup(InstancePtr->VtcPtr[Index],
+ &InstancePtr->DpPtr->TxInstance.MsaConfig[Index]);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: "
+ "VTC%d setup failed!\n\r", Index);
+ return Status;
+ }
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function disables the DisplayPort Transmitter Subsystem sub-cores.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDpTxSs_Stop(XDpTxSs *InstancePtr)
+{
+ u8 Index;
+
+ /* Verify argument. */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ if (InstancePtr->DpPtr) {
+ /* disable main link */
+ XDp_TxDisableMainLink(InstancePtr->DpPtr);
+ }
+
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+ if (InstancePtr->DsPtr) {
+ /* Disable Dual Splitter */
+ XDualSplitter_Disable(InstancePtr->DsPtr);
+ }
+#endif
+
+ for (Index = 0; Index < InstancePtr->Config.NumMstStreams; Index++) {
+ if (InstancePtr->VtcPtr[Index]) {
+ /* Disable all the VTC sub-cores */
+ XVtc_Disable(InstancePtr->VtcPtr[Index]);
+ }
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the bits per color value of the video stream.
+*
+* @param InstancePtr is a pointer to the XDpTxSs instance.
+* @param Bpc is the new number of bits per color that needs to be set.
+* - 8 = XVIDC_BPC_8,
+* - 10 = XVIDC_BPC_10,
+* - 12 = XVIDC_BPC_12,
+* - 16 = XVIDC_BPC_16,
+*
+* @return
+* - XST_SUCCESS, if bits per color set successfully.
+* - XST_FAILURE, if bits per color set failed.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XDpTxSs_SetBpc(XDpTxSs *InstancePtr, u8 Bpc)
+{
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid((Bpc == XVIDC_BPC_8) || (Bpc == XVIDC_BPC_10) ||
+ (Bpc == XVIDC_BPC_12) || (Bpc == XVIDC_BPC_16));
+
+ /* Set bits per color */
+ InstancePtr->UsrOpt.Bpc = Bpc;
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the standard display mode.
+*
+* @param InstancePtr is a pointer to the XDpTxSs instance.
+* @param VidMode is one of the enumerated standard video modes that is
+* used to determine the MSA values to be used.
+*
+* @return
+* - XST_SUCCESS, if video mode set successfully.
+* - XST_FAILURE, if video mode set failed.
+*
+* @note Refer xvidc.h for enumerated standard video modes.
+*
+******************************************************************************/
+u32 XDpTxSs_SetVidMode(XDpTxSs *InstancePtr, XVidC_VideoMode VidMode)
+{
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid((VidMode < XVIDC_VM_NUM_SUPPORTED) ||
+ (VidMode == XVIDC_VM_USE_EDID_PREFERRED));
+
+ if ((VidMode == XVIDC_VM_UHD_60_P) &&
+ (InstancePtr->UsrOpt.MstSupport)) {
+ InstancePtr->UsrOpt.VmId = XVIDC_VM_UHD2_60_P;
+ }
+ else {
+ /* Set video mode */
+ InstancePtr->UsrOpt.VmId = VidMode;
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the data rate to be used by the DisplayPort TX Subsystem
+* core.
+*
+* @param InstancePtr is a pointer to the XDpTxSs instance.
+* @param LinkRate is the rate at which link needs to be driven.
+* - XDPTXSS_LINK_BW_SET_162GBPS = 0x06(for a 1.62 Gbps data rate)
+* - XDPTXSS_LINK_BW_SET_270GBPS = 0x0A(for a 2.70 Gbps data rate)
+* - XDPTXSS_LINK_BW_SET_540GBPS = 0x14(for a 5.40 Gbps data rate)
+*
+* @return
+* - XST_SUCCESS if setting the new lane rate was successful.
+* - XST_FAILURE otherwise.
+*
+* @note Maximum supported link rate is used if given link rate is
+* greater than the maximum supported link rate.
+*
+******************************************************************************/
+u32 XDpTxSs_SetLinkRate(XDpTxSs *InstancePtr, u8 LinkRate)
+{
+ u32 Status;
+
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid((LinkRate == XDPTXSS_LINK_BW_SET_162GBPS) ||
+ (LinkRate == XDPTXSS_LINK_BW_SET_270GBPS) ||
+ (LinkRate == XDPTXSS_LINK_BW_SET_540GBPS));
+
+ /* Check for maximum supported link rate */
+ if (LinkRate > InstancePtr->DpPtr->Config.MaxLinkRate) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS info: This link rate is "
+ "not supported by Source/Sink.\n\rMax Supported link "
+ "rate is 0x%x.\n\rSetting maximum supported link "
+ "rate.\n\r", InstancePtr->DpPtr->Config.MaxLinkRate);
+ LinkRate = InstancePtr->DpPtr->Config.MaxLinkRate;
+ }
+
+ /* Set link rate */
+ Status = XDp_TxSetLinkRate(InstancePtr->DpPtr, LinkRate);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: Setting link rate "
+ "failed.\n\r");
+ Status = XST_FAILURE;
+ }
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the number of lanes to be used by DisplayPort TX Subsystem
+* core.
+*
+* @param InstancePtr is a pointer to the XDpTxSs instance.
+* @param LaneCount is the number of lanes to be used.
+* - 1 = XDPTXSS_LANE_COUNT_SET_1
+* - 2 = XDPTXSS_LANE_COUNT_SET_2
+* - 4 = XDPTXSS_LANE_COUNT_SET_4
+* @return
+* - XST_SUCCESS if setting the new lane count was successful.
+* - XST_FAILURE otherwise.
+*
+* @note Maximum supported lane count is used if given lane count is
+* greater than the maximum supported lane count.
+*
+******************************************************************************/
+u32 XDpTxSs_SetLaneCount(XDpTxSs *InstancePtr, u8 LaneCount)
+{
+ u32 Status;
+
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid((LaneCount == XDPTXSS_LANE_COUNT_SET_1) ||
+ (LaneCount == XDPTXSS_LANE_COUNT_SET_2) ||
+ (LaneCount == XDPTXSS_LANE_COUNT_SET_4));
+
+ /* Check for maximum supported lane count */
+ if (LaneCount > InstancePtr->DpPtr->Config.MaxLaneCount) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS info: This lane count is "
+ "not supported by Source/Sink.\n\rMax Supported lane "
+ "count is 0x%x.\n\rSetting maximum supported lane "
+ "count.\n\r", InstancePtr->DpPtr->Config.MaxLaneCount);
+ LaneCount = InstancePtr->DpPtr->Config.MaxLaneCount;
+ }
+
+ /* Set lane count */
+ Status = XDp_TxSetLaneCount(InstancePtr->DpPtr, LaneCount);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: Setting lane count "
+ "failed.\n\r");
+ Status = XST_FAILURE;
+ }
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets transport mode (SST/MST).
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+* @param Mode specifies the type of transport mode that will be set.
+* - 0 = Single-Stream Transport mode,
+* - 1 = Multi-Stream Transport mode,
+*
+* @return
+* - XST_SUCCESS, if transport mode is set successfully to either
+* MST or SST when RX device is MST and mode is less than or
+* equal to supported mode.
+* - XST_FAILURE, if setting to already set mode or mode is
+* greater than supported mode.
+*
+* @note Transport mode is set to either MST or SST when system is MST
+* and RX device is MST capable.
+*
+******************************************************************************/
+u32 XDpTxSs_SetTransportMode(XDpTxSs *InstancePtr, u8 Mode)
+{
+ u32 Status;
+
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid((Mode == 0x0) || (Mode == 0x1));
+
+ /* Check for MST */
+ if (Mode == InstancePtr->UsrOpt.MstSupport) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO:Subsystem is "
+ "already in %s mode \n\r",Mode?"MST":"SST");
+ Status = XST_FAILURE;
+ }
+ /* Check for mode less than supported mode */
+ else if (Mode <= InstancePtr->Config.MstSupport) {
+ /* Check RX device is MST capable */
+ Status = XDp_TxMstCapable(InstancePtr->DpPtr);
+ if ((Status != XST_SUCCESS) && (Mode >
+ InstancePtr->UsrOpt.MstSupport)) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: RX device "
+ "is SST capable. No change in mode.\n\r");
+ Status = XST_FAILURE;
+ }
+ else if ((Status == XST_SUCCESS) && ((Mode <
+ InstancePtr->UsrOpt.MstSupport) ||
+ (Mode > InstancePtr->UsrOpt.MstSupport))) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO::setting "
+ "Subsystem mode from %s to %s mode \n\r",
+ (InstancePtr->UsrOpt.MstSupport?"MST":"SST"),
+ (Mode?"MST":"SST"));
+
+ InstancePtr->UsrOpt.MstSupport = Mode;
+ Status = XST_SUCCESS;
+ }
+ }
+ /* Everything else */
+ else {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR::Subsystem does not "
+ "support %s \n\r", Mode?"MST":"SST");
+ Status = XST_FAILURE;
+ }
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function retrieves the RX device's capabilities from the RX device's
+* DisplayPort Configuration Data (DPCD).
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return
+* - XST_SUCCESS if the DisplayPort Configuration Data was read
+* successfully.
+* - XST_DEVICE_NOT_FOUND if no RX device is connected.
+* - XST_FAILURE otherwise.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XDpTxSs_GetRxCapabilities(XDpTxSs *InstancePtr)
+{
+ u32 Status;
+
+ /* Verify argument. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Get RX device capabilities */
+ Status = XDp_TxGetRxCapabilities(InstancePtr->DpPtr);
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function retrieves an immediately connected RX device's Extended Display
+* Identification Data (EDID) structure.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+* @param Edid is a pointer to the Edid buffer to save to.
+*
+* @return
+* - XST_SUCCESS if the I2C transactions to read the EDID were
+* successful.
+* - XST_ERROR_COUNT_MAX if the EDID read request timed out.
+* - XST_DEVICE_NOT_FOUND if no RX device is connected.
+* - XST_FAILURE otherwise.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XDpTxSs_GetEdid(XDpTxSs *InstancePtr, u8 *Edid)
+{
+ u32 Status;
+
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Edid != NULL);
+
+ /* Retrieve the EDID */
+ Status = XDp_TxGetEdid(InstancePtr->DpPtr, Edid);
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function retrieves a remote RX device's Extended Display Identification
+* Data (EDID) structure.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+* @param SinkNum is the Sink ID in the sink list within the range
+* [0 to 3].
+* @param Edid is a pointer to the Edid buffer to save to.
+*
+* @return
+* - XST_SUCCESS if the I2C transactions to read the EDID were
+* successful.
+* - XST_ERROR_COUNT_MAX if the EDID read request timed out.
+* - XST_DEVICE_NOT_FOUND if no RX device is connected.
+* - XST_FAILURE otherwise.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XDpTxSs_GetRemoteEdid(XDpTxSs *InstancePtr, u8 SinkNum, u8 *Edid)
+{
+ u32 Status;
+ u8 TotalSink;
+ XDp_TxTopologyNode *Node;
+ TotalSink = InstancePtr->DpPtr->TxInstance.Topology.SinkTotal;
+
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Edid != NULL);
+ Xil_AssertNonvoid(SinkNum < TotalSink);
+
+ Node = InstancePtr->DpPtr->TxInstance.Topology.SinkList[SinkNum];
+
+ /* Retrieve the EDID */
+ Status = XDp_TxGetRemoteEdid(InstancePtr->DpPtr, Node->LinkCountTotal,
+ Node->RelativeAddress, Edid);
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function checks if there is a connected RX device to DisplayPort TX
+* Subsystem.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return
+* - TRUE if there is a connection.
+* - FALSE if there is no connection.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XDpTxSs_IsConnected(XDpTxSs *InstancePtr)
+{
+ u32 Status;
+
+ /* Verify argument.*/
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Check for TX connected */
+ Status = XDp_TxIsConnected(InstancePtr->DpPtr);
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function checks if the receiver's DisplayPort Configuration Data (DPCD)
+* indicates the receiver has achieved and maintained clock recovery, channel
+* equalization, symbol lock, and interlane alignment for all lanes currently in
+* use.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return
+* - XST_SUCCESS if the RX device has maintained clock recovery,
+* channel equalization, symbol lock, and interlane alignment.
+* - XST_DEVICE_NOT_FOUND if no RX device is connected.
+* - XST_FAILURE otherwise.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XDpTxSs_CheckLinkStatus(XDpTxSs *InstancePtr)
+{
+ u32 Status;
+
+ /* Verify argument.*/
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Check the status of link with lane count */
+ Status = XDp_TxCheckLinkStatus(InstancePtr->DpPtr,
+ InstancePtr->DpPtr->TxInstance.LinkConfig.LaneCount);
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function determines whether downstream RX device is MST/SST capable.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return
+* - XST_SUCCESS if the RX device is MST enabled.
+* - XST_FAILURE if the RX device is SST enabled.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XDpTxSs_IsMstCapable(XDpTxSs *InstancePtr)
+{
+ u32 Status;
+
+ /* Verify argument.*/
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Check RX device is MST capable */
+ Status = XDp_TxMstCapable(InstancePtr->DpPtr);
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function reports list of cores included in DisplayPort TX Subsystem.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void DpTxSs_GetIncludedSubCores(XDpTxSs *InstancePtr)
+{
+ u32 Index;
+
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+ /* Assign instance of Dual Splitter core */
+ InstancePtr->DsPtr = ((InstancePtr->Config.DsSubCore.IsPresent)?
+ (&DpTxSsSubCores.DsInst): NULL);
+#endif
+
+ /* Assign instance of DisplayPort core */
+ InstancePtr->DpPtr = ((InstancePtr->Config.DpSubCore.IsPresent)?
+ (&DpTxSsSubCores.DpInst): NULL);
+
+ for (Index = 0; Index < InstancePtr->Config.NumMstStreams; Index++) {
+
+ /* Assign instances of VTC core */
+ InstancePtr->VtcPtr[Index] =
+ ((InstancePtr->Config.VtcSubCore[Index].IsPresent)?
+ (&DpTxSsSubCores.VtcInst[Index]): NULL);
+ }
+}
diff --git a/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss.h b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss.h
new file mode 100644
index 00000000..c00b5490
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss.h
@@ -0,0 +1,280 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdptxss.h
+*
+* This is the main header file for Xilinx DisplayPort Transmitter Subsystem
+* core. It abstracts Subsystem cores and provides high level API's to
+* application developer.
+*
+* Core Features
+*
+* For a full description of DisplayPort Transmitter Subsystem core, please
+* see the hardware specification.
+*
+* Software Initialization & Configuration
+*
+* The application needs to do following steps in order for preparing the
+* DisplayPort Transmitter Subsystem core to be ready.
+*
+* - Call XDpTxSs_LookupConfig using a device ID to find the core
+* configuration.
+* - Call XDpTxSs_CfgInitialize to initialize the device and the driver
+* instance associated with it.
+*
+* Interrupts
+*
+* The DisplayPort TX Subsystem driver provides an interrupt handler
+* XDpTxSs_DpIntrHandler for handling the interrupt from the DisplayPort
+* sub-core. The users of this driver have to register this handler with
+* the interrupt system and provide the callback functions by using
+* XDpTxSs_SetCallBack API.
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The DisplayPort Transmitter Subsystem driver is composed of several source
+* files. This allows the user to build and link only those parts of the driver
+* that are necessary.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ---- --- -------- --------------------------------------------------
+* 1.00 sha 01/29/15 Initial release.
+*
+*
+******************************************************************************/
+#ifndef XDPTXSS_H_
+#define XDPTXSS_H_ /**< Prevent circular inclusions
+ * by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xdptxss_hw.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xvidc.h"
+#include "xdebug.h"
+
+/* Subsystem sub-cores header files */
+#include "xss_dptx.h"
+#include "xss_dualsplitter.h"
+#include "xss_vtc.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+* These constants specify different types of handler and used to differentiate
+* interrupt requests from sub-cores.
+*/
+typedef enum {
+ XDPTXSS_HANDLER_DP_HPD_EVENT = 1, /**< A HPD event interrupt
+ * type for DisplayPort
+ * core */
+ XDPTXSS_HANDLER_DP_HPD_PULSE /**< A HPD pulse interrupt
+ * type for DisplayPort
+ * core */
+} XDpTxSs_HandlerType;
+
+/**
+* User input structure
+*/
+typedef struct {
+ XVidC_VideoMode VmId; /**< Video Mode ID */
+ u8 Bpc; /**< Bits per color */
+ u8 MstSupport; /**< Multi-stream transport (MST) support */
+ u8 NumOfStreams; /**< The total number of MST streams */
+} XDpTxSs_UsrOpt;
+
+/**
+* VTC Sub-core structure.
+*/
+typedef struct {
+ u16 IsPresent; /**< Flag to hold the presence of VTC core. */
+ XVtc_Config VtcConfig; /**< Video Timing Controller (VTC) core
+ * configuration information */
+} XDpTxSs_VtcSubCore;
+
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+/**
+* Dual Splitter Sub-core structure.
+*/
+typedef struct {
+ u16 IsPresent; /**< Flag to hold the presence of Dual
+ * Splitter core. */
+ XDualSplitter_Config DsConfig; /**< Dual Splitter core configuration
+ * information */
+} XDpTxSs_DsSubCore;
+#endif
+
+/**
+* DisplayPort Sub-core structure.
+*/
+typedef struct {
+ u16 IsPresent; /**< Flag to hold the presence of DisplayPort
+ * Transmitter core. */
+ XDp_Config DpConfig; /**< DisplayPort core configuration
+ * information */
+} XDpTxSs_DpSubCore;
+
+/**
+* This typedef contains configuration information for the DisplayPort
+* Transmitter Subsystem core. Each DisplayPort TX Subsystem core should have
+* a configuration structure associated.
+*/
+typedef struct {
+ u16 DeviceId; /**< DeviceId is the unique ID of the
+ * DisplayPort TX Subsystem core */
+ u32 BaseAddress; /**< BaseAddress is the physical base address
+ * of the core's registers */
+ u8 SecondaryChEn; /**< This Subsystem core supports audio packets
+ * being sent by the secondary channel. */
+ u8 MaxBpc; /**< The maximum bits/color supported by this
+ * Subsystem core */
+ u8 HdcpEnable; /**< This Subsystem core supports digital
+ * content protection. */
+ u8 MaxLaneCount; /**< The maximum lane count supported by this
+ * core instance. */
+ u8 MstSupport; /**< Multi-stream transport (MST) mode is
+ * enabled by this core instance. */
+ u8 NumMstStreams; /**< The total number of MST streams supported
+ * by this core instance. */
+ XDpTxSs_DpSubCore DpSubCore; /**< DisplayPort Configuration */
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+ XDpTxSs_DsSubCore DsSubCore; /**< Dual Splitter Configuration */
+#endif
+ XDpTxSs_VtcSubCore VtcSubCore[XDPTXSS_NUM_STREAMS]; /**< VTC
+ * Configura-
+ * tion */
+} XDpTxSs_Config;
+
+/**
+* The DisplayPort TX Subsystem driver instance data. An instance must be
+* allocated for each core in use.
+*/
+typedef struct {
+ XDpTxSs_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Core and the driver instance are
+ * initialized */
+ /* Sub-core instances */
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+ XDualSplitter *DsPtr; /**< Dual Splitter sub-core instance */
+#endif
+ XDp *DpPtr; /**< DisplayPort sub-core instance */
+ XVtc *VtcPtr[XDPTXSS_NUM_STREAMS];/**< Maximum number of VTC sub-core
+ * instances */
+
+ XDpTxSs_UsrOpt UsrOpt; /**< User Options structure */
+} XDpTxSs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**
+* Callback type which represents a custom timer wait handler.
+*/
+#define XDpTxSs_TimerHandler XDp_TimerHandler
+
+/************************** Function Prototypes ******************************/
+
+/* Initialization function in xdptxss_sinit.c */
+XDpTxSs_Config* XDpTxSs_LookupConfig(u16 DeviceId);
+
+/* Initialization and control functions in xaxi4s_switch.c */
+u32 XDpTxSs_CfgInitialize(XDpTxSs *InstancePtr, XDpTxSs_Config *CfgPtr,
+ u32 EffectiveAddr);
+u32 XDpTxSs_Start(XDpTxSs *InstancePtr);
+void XDpTxSs_Stop(XDpTxSs *InstancePtr);
+void XDpTxSs_Reset(XDpTxSs *InstancePtr);
+u32 XDpTxSs_SetBpc(XDpTxSs *InstancePtr, u8 Bpc);
+u32 XDpTxSs_SetVidMode(XDpTxSs *InstancePtr, XVidC_VideoMode VidMode);
+u32 XDpTxSs_SetLinkRate(XDpTxSs *InstancePtr, u8 LinkRate);
+u32 XDpTxSs_SetLaneCount(XDpTxSs *InstancePtr, u8 LaneCount);
+u32 XDpTxSs_SetTransportMode(XDpTxSs *InstancePtr, u8 Mode);
+u32 XDpTxSs_IsConnected(XDpTxSs *InstancePtr);
+u32 XDpTxSs_CheckLinkStatus(XDpTxSs *InstancePtr);
+u32 XDpTxSs_IsMstCapable(XDpTxSs *InstancePtr);
+u32 XDpTxSs_GetRxCapabilities(XDpTxSs *InstancePtr);
+u32 XDpTxSs_GetEdid(XDpTxSs *InstancePtr, u8 *Edid);
+u32 XDpTxSs_GetRemoteEdid(XDpTxSs *InstancePtr, u8 SinkNum, u8 *Edid);
+
+void XDpTxSs_ReportCoreInfo(XDpTxSs *InstancePtr);
+void XDpTxSs_ReportLinkInfo(XDpTxSs *InstancePtr);
+void XDpTxSs_ReportMsaInfo(XDpTxSs *InstancePtr);
+void XDpTxSs_ReportSinkCapInfo(XDpTxSs *InstancePtr);
+void XDpTxSs_ReportSplitterInfo(XDpTxSs *InstancePtr);
+void XDpTxSs_ReportVtcInfo(XDpTxSs *InstancePtr);
+
+/* Self test function in xdptxss_selftest.c */
+u32 XDpTxSs_SelfTest(XDpTxSs *InstancePtr);
+
+/* Interrupt functions in xdptxss_intr.c */
+void XDpTxSs_DpIntrHandler(void *InstancePtr);
+u32 XDpTxSs_SetCallBack(XDpTxSs *InstancePtr, u32 HandlerType,
+ void *CallbackFunc, void *CallbackRef);
+void XDpTxSs_SetUserTimerHandler(XDpTxSs *InstancePtr,
+ XDpTxSs_TimerHandler CallbackFunc, void *CallbackRef);
+
+/************************** Variable Declarations ****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro */
diff --git a/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_dbg.c b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_dbg.c
new file mode 100644
index 00000000..e70c5311
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_dbg.c
@@ -0,0 +1,534 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdptxss_dbg.c
+*
+* This file contains functions to report debug information of DisplayPort TX
+* Subsystem sub-cores.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ---- --- -------- --------------------------------------------------
+* 1.00 sha 01/29/15 Initial release.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdptxss.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function prints the capabilities of the DisplayPort sink.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDpTxSs_ReportSinkCapInfo(XDpTxSs *InstancePtr)
+{
+ /* Verify argument. */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ u8 *Dpcd = InstancePtr->DpPtr->TxInstance.RxConfig.DpcdRxCapsField;
+
+ u8 DpcdRevMajor = (Dpcd[XDP_DPCD_REV] &
+ XDP_DPCD_REV_MJR_MASK) >>
+ XDP_DPCD_REV_MJR_SHIFT;
+ u8 DpcdRevMinor = Dpcd[XDP_DPCD_REV] & XDP_DPCD_REV_MNR_MASK;
+ u8 MaxLinkRate = Dpcd[XDP_DPCD_MAX_LINK_RATE];
+ u8 MaxLaneCount = Dpcd[XDP_DPCD_MAX_LANE_COUNT] &
+ XDP_DPCD_MAX_LANE_COUNT_MASK;
+ u8 Tps3Support = Dpcd[XDP_DPCD_MAX_LANE_COUNT] &
+ XDP_DPCD_TPS3_SUPPORT_MASK;
+ u8 EnhancedFrameSupport = Dpcd[XDP_DPCD_MAX_LANE_COUNT] &
+ XDP_DPCD_ENHANCED_FRAME_SUPPORT_MASK;
+ u8 MaxDownspreadSupport = Dpcd[XDP_DPCD_MAX_DOWNSPREAD] &
+ XDP_DPCD_MAX_DOWNSPREAD_MASK;
+ u8 NoAuxHandshakeRequired = Dpcd[XDP_DPCD_MAX_DOWNSPREAD] &
+ XDP_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK;
+ u8 NumRxPorts = (Dpcd[XDP_DPCD_NORP_PWR_V_CAP] & (0x01)) + 1;
+ u8 PwrDpCap5V = Dpcd[XDP_DPCD_NORP_PWR_V_CAP] & (0x01);
+ u8 PwrDpCap12V = Dpcd[XDP_DPCD_NORP_PWR_V_CAP] & (0x20);
+ u8 PwrDpCap18V = Dpcd[XDP_DPCD_NORP_PWR_V_CAP] & (0x40);
+ u8 DownstreamPortPresent = Dpcd[XDP_DPCD_DOWNSP_PRESENT] & (0x80);
+ u8 DownPortType = (Dpcd[XDP_DPCD_DOWNSP_PRESENT] &
+ XDP_DPCD_DOWNSP_TYPE_MASK) >>
+ XDP_DPCD_DOWNSP_TYPE_SHIFT;
+ u8 FormatConversionBlockPresent = Dpcd[XDP_DPCD_DOWNSP_PRESENT] &
+ XDP_DPCD_DOWNSP_FORMAT_CONV_MASK;
+ u8 DetailedCapInfoAvailable = Dpcd[XDP_DPCD_DOWNSP_PRESENT] &
+ XDP_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK;
+ u8 MainLinkAnsi8b10bCodingSupport = Dpcd[XDP_DPCD_ML_CH_CODING_CAP] &
+ XDP_DPCD_ML_CH_CODING_MASK;
+ u8 DownstreamPortCount = Dpcd[XDP_DPCD_DOWNSP_COUNT_MSA_OUI] &
+ XDP_DPCD_DOWNSP_COUNT_MASK;
+ u8 MsaTimingParIgnored = Dpcd[XDP_DPCD_DOWNSP_COUNT_MSA_OUI] &
+ XDP_DPCD_MSA_TIMING_PAR_IGNORED_MASK;
+ u8 OuiSupported = Dpcd[XDP_DPCD_DOWNSP_COUNT_MSA_OUI] &
+ XDP_DPCD_OUI_SUPPORT_MASK;
+ u8 RxPort0LocalEdidPresent = Dpcd[XDP_DPCD_RX_PORT0_CAP_0] &
+ XDP_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK;
+ u8 RxPort0AssocPrecedePort = Dpcd[XDP_DPCD_RX_PORT0_CAP_0] &
+ XDP_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK;
+ u8 RxPort0BufSizeBpl = (Dpcd[XDP_DPCD_RX_PORT0_CAP_1] + 1) * 32;
+ u8 RxPort1LocalEdidPresent = Dpcd[XDP_DPCD_RX_PORT1_CAP_0] &
+ XDP_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK;
+ u8 RxPort1AssocPrecedePort = Dpcd[XDP_DPCD_RX_PORT1_CAP_0] &
+ XDP_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK;
+ u8 RxPort1BufSizeBpl = (Dpcd[XDP_DPCD_RX_PORT1_CAP_1] + 1) * 32;
+ u8 IicSpeed = Dpcd[XDP_DPCD_I2C_SPEED_CTL_CAP];
+ u8 EdpAltScramblerResetCap = Dpcd[XDP_DPCD_EDP_CFG_CAP] &(0x1);
+ u8 EdpFramingChangeCap = Dpcd[XDP_DPCD_EDP_CFG_CAP] & (0x2);
+ u8 TraingAuxReadInt = Dpcd[XDP_DPCD_TRAIN_AUX_RD_INTERVAL];
+ u8 AdapterForceLoadSenseCap = Dpcd[XDP_DPCD_ADAPTER_CAP] & (0x01);
+ u8 AdapterAltI2CPatternCap = Dpcd[XDP_DPCD_ADAPTER_CAP] & (0x02);
+ u8 FauxCap = Dpcd[XDP_DPCD_FAUX_CAP] & XDP_DPCD_FAUX_CAP_MASK;
+ u8 MstmCap = Dpcd[XDP_DPCD_MSTM_CAP] & XDP_DPCD_MST_CAP_MASK;
+ u8 NumAudioEps = Dpcd[XDP_DPCD_NUM_AUDIO_EPS];
+
+ xil_printf("RX capabilities:\n\r"
+ "\tDPCD rev major (0x00000): %d\n\r"
+ "\tDPCD rev minor (0x00000): %d\n\r"
+ "\tMax link rate (0x00001): %s\n\r"
+ "\tMax lane count (0x00002): %d\n\r"
+ "\tTPS3 supported (0x00002): %s\n\r"
+ "\tEnhanced frame support? (0x00002) %s\n\r"
+ "\tMax downspread support? (0x00003) %s\n\r"
+ "\tNo AUX handshake required? (0x00003)%s\n\r"
+ "\t# of receiver ports (0x00004): %d\n\r"
+ "\tDP power 5v cap? (0x00004) %s\n\r"
+ "\tDP power 12v cap? (0x00004) %s\n\r"
+ "\tDP power 18v cap? (0x00004) %s\n\r"
+ "\tDownstream ports present? (0x00005) %s\n\r"
+ "\tDownstreamport0 type (0x00005): %s\n\r"
+ "\tFormat conversion block present (0x00005): %s\n\r"
+ "\tDetailed cap info available? (0x00005) %s\n\r"
+ "\tMain link ANSI 8b/10b channel coding support? (0x00006) "
+ "%s\n\r"
+ "\tDownstream port count (0x00007): %d\n\r"
+ "\tMSA timing parameters ignored? (0x00007) %s\n\r"
+ "\tOUI supported? (0x00007) %s\n\r"
+ "\tReceive port0 local edid present (0x00008) %s\n\r"
+ "\tReceive port0 associated to preceding port? (0x00008) "
+ "%s\n\r"
+ "\tReceive port0 buffer size (0x00009): %d bytes per lane\n\r"
+ "\tReceive port1 local edid present (0x0000A) %s\n\r"
+ "\tReceive port1 associated to preceding port? (0x0000A) "
+ "%s\n\r"
+ "\tReceive port1 buffer size (0x0000B): %d bytes per lane\n\r"
+ "\tI2C speed (0x0000C): %s\n\r"
+ "\tEDP alt scrambler reset cap? (0x0000D) %s\n\r"
+ "\tEDP framing change cap? (0x0000D) %s\n\r"
+ "\tTraining AUX read interval (0x0000E): %s\n\r"
+ "\tAdapter force load sense cap? (0x0000F) %s\n\r"
+ "\tAdapter alt i2c pattern cap? (0x0000F) %s\n\r"
+ "\tFaux cap? (0x00020) %s\n\r"
+ "\tMSTM cap? (0x00021) %s\n\r"
+ "\t# of audio eps (0x00022) : %d\n\r",
+ DpcdRevMajor,
+ DpcdRevMinor,
+ (MaxLinkRate == XDP_DPCD_LINK_BW_SET_162GBPS) ? "1.62Gbps" :
+ (MaxLinkRate == XDP_DPCD_LINK_BW_SET_270GBPS) ? "2.70Gbps" :
+ (MaxLinkRate == XDP_DPCD_LINK_BW_SET_540GBPS) ? "5.40Gbps" :
+ "Unknown link rate",
+ MaxLaneCount,
+ Tps3Support ? "Y" : "N",
+ EnhancedFrameSupport ? "Y" : "N",
+ MaxDownspreadSupport ? "Y" : "N",
+ NoAuxHandshakeRequired ? "Y" : "N",
+ NumRxPorts,
+ PwrDpCap5V ? "Y" : "N",
+ PwrDpCap12V ? "Y" : "N",
+ PwrDpCap18V ? "Y" : "N",
+ DownstreamPortPresent ? "Y" : "N",
+ (DownPortType == XDP_DPCD_DOWNSP_TYPE_DP) ?
+ "DisplayPort" :
+ (DownPortType == XDP_DPCD_DOWNSP_TYPE_AVGA_ADVII) ?
+ "Analog VGA or analog video over DVI-I" :
+ (DownPortType == XDP_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP) ?
+ "DVI, HDMI, or DP++" :
+ (DownPortType == XDP_DPCD_DOWNSP_TYPE_OTHERS) ?
+ "Others" : "Unknown downstream port type",
+ FormatConversionBlockPresent ? "Y" : "N",
+ DetailedCapInfoAvailable ? "Y" : "N",
+ MainLinkAnsi8b10bCodingSupport ? "Y" : "N",
+ DownstreamPortCount,
+ MsaTimingParIgnored ? "Y" : "N",
+ OuiSupported ? "Y" : "N",
+ RxPort0LocalEdidPresent ? "Y" : "N",
+ RxPort0AssocPrecedePort ? "Y" : "N",
+ RxPort0BufSizeBpl,
+ RxPort1LocalEdidPresent ? "Y" : "N",
+ RxPort1AssocPrecedePort ? "Y" : "N",
+ RxPort1BufSizeBpl,
+ (IicSpeed == XDP_DPCD_I2C_SPEED_CTL_NONE) ? "No control" :
+ (IicSpeed == XDP_DPCD_I2C_SPEED_CTL_1KBIPS) ? "1Kbps" :
+ (IicSpeed == XDP_DPCD_I2C_SPEED_CTL_5KBIPS) ? "5Kbps" :
+ (IicSpeed == XDP_DPCD_I2C_SPEED_CTL_10KBIPS) ? "10Kbps" :
+ (IicSpeed == XDP_DPCD_I2C_SPEED_CTL_100KBIPS) ? "100Kbps" :
+ (IicSpeed == XDP_DPCD_I2C_SPEED_CTL_400KBIPS) ? "400Kbps" :
+ (IicSpeed == XDP_DPCD_I2C_SPEED_CTL_1MBIPS) ? "1Mbps" :
+ "Unknown I2C speed",
+ EdpAltScramblerResetCap ? "Y" : "N",
+ EdpFramingChangeCap ? "Y" : "N",
+ (TraingAuxReadInt == XDP_DPCD_TRAIN_AUX_RD_INT_100_400US) ?
+ "100us for CR, 400us for CE" : (TraingAuxReadInt ==
+ XDP_DPCD_TRAIN_AUX_RD_INT_4MS) ? "4us" :
+ (TraingAuxReadInt == XDP_DPCD_TRAIN_AUX_RD_INT_8MS) ? "8us" :
+ (TraingAuxReadInt == XDP_DPCD_TRAIN_AUX_RD_INT_12MS) ?
+ "12us" : (TraingAuxReadInt ==
+ XDP_DPCD_TRAIN_AUX_RD_INT_16MS) ? "16us" :
+ "Unknown AUX read interval",
+ AdapterForceLoadSenseCap ? "Y" : "N",
+ AdapterAltI2CPatternCap ? "Y" : "N",
+ FauxCap ? "Y" : "N",
+ MstmCap ? "Y" : "N",
+ NumAudioEps
+ );
+
+ xil_printf("\n\r");
+}
+
+/*****************************************************************************/
+/**
+*
+* This function reports list of sub-cores included in DisplayPort TX Subsystem.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDpTxSs_ReportCoreInfo(XDpTxSs *InstancePtr)
+{
+ u32 Index;
+
+ /* Verify argument. */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ xil_printf("\n\rDisplayPort TX Subsystem info:\n\r");
+
+ /* Report all the included cores in the subsystem instance */
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+ if (InstancePtr->DsPtr) {
+ xil_printf("Dual Splitter:Yes\n\r");
+ }
+#endif
+
+ if (InstancePtr->DpPtr) {
+ xil_printf("DisplayPort Transmitter(TX):Yes\n\r");
+ }
+
+ for (Index = 0; Index < InstancePtr->Config.NumMstStreams; Index++) {
+ if (InstancePtr->VtcPtr[Index]) {
+ xil_printf("Video Timing Controller(VTC) %ld: Yes\n\r",
+ Index);
+ }
+ }
+
+ xil_printf("Audio enabled:%s\n\r",
+ InstancePtr->Config.SecondaryChEn? "Yes": "No");
+ xil_printf("Max supported bits per color:%d\n\r",
+ InstancePtr->Config.MaxBpc);
+ xil_printf("HDCP enabled:%s\n\r",
+ InstancePtr->Config.HdcpEnable? "Yes": "No");
+ xil_printf("Max supported lane count:%d\n\r",
+ InstancePtr->Config.MaxLaneCount);
+ xil_printf("Multi-Stream Transport mode:%s\n\r",
+ InstancePtr->Config.MstSupport? "Yes": "No (SST)");
+ xil_printf("Max number of supported streams:%d\n\r",
+ InstancePtr->Config.NumMstStreams);
+ xil_printf("Subsystem is running in: %s\n\r",
+ InstancePtr->UsrOpt.MstSupport?"MST":"SST");
+
+ xil_printf("\n\r");
+}
+
+/*****************************************************************************/
+/**
+*
+* This function prints the current Dual Splitter information.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDpTxSs_ReportSplitterInfo(XDpTxSs *InstancePtr)
+{
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+ u8 ISamples;
+ u8 OSamples;
+ u8 Segments;
+ u8 Overlap;
+ u16 Height;
+ u16 Width;
+#endif
+
+ /* Verify argument. */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+ if (InstancePtr->DsPtr) {
+ xil_printf("Dual Splitter info:\n\r");
+ XDualSplitter_GetImageSize(InstancePtr->DsPtr, &Height,
+ &Width);
+ XDualSplitter_GetImgParam(InstancePtr->DsPtr, &ISamples,
+ &OSamples, &Segments, &Overlap);
+ xil_printf("Input Samples :%d\n\r"
+ "Output Samples:%d\n\r"
+ "Overlap :%d\n\r"
+ "Segments :%d\n\r"
+ "Mode :%s\n\r"
+ "Width x Height:%d x %d", ISamples, OSamples,
+ Overlap, Segments,
+ (Segments == 2)?"Split":"Bypass",
+ Width,Height);
+ }
+#else
+ xil_printf("Dual Splitter is not supported in this design \n\r");
+#endif
+ xil_printf("\n\r");
+}
+
+/*****************************************************************************/
+/**
+*
+* This function prints the current VTC timing information.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDpTxSs_ReportVtcInfo(XDpTxSs *InstancePtr)
+{
+ XVtc_Timing VideoTiming;
+ u32 Index;
+
+ /* Verify argument. */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ for (Index = 0; Index < InstancePtr->UsrOpt.NumOfStreams; Index++) {
+ if (InstancePtr->VtcPtr[Index]) {
+ XVtc_GetGeneratorTiming(InstancePtr->VtcPtr[Index],
+ &VideoTiming);
+
+ xil_printf("VTC%ld timing:\n\r"
+ "\tHActiveVideo : %d\n\r"
+ "\tHFrontPorch : %d\n\r"
+ "\tHSyncWidth : %d\n\r"
+ "\tHBackPorch : %d\n\r"
+ "\tHSyncPolarity: %d\n\r"
+ "\tVActiveVideo : %d\n\r"
+ "\tV0FrontPorch : %d\n\r"
+ "\tV0SyncWidth : %d\n\r"
+ "\tV0BackPorch : %d\n\r"
+ "\tV1FrontPorch : %d\n\r"
+ "\tV1SyncWidth : %d\n\r"
+ "\tV1BackPorch : %d\n\r"
+ "\tVSyncPolarity: %d\n\r"
+ "\tInterlaced : %s\n\n\r\r",Index,
+ VideoTiming.HActiveVideo,
+ VideoTiming.HFrontPorch,
+ VideoTiming.HSyncWidth,
+ VideoTiming.HBackPorch,
+ VideoTiming.HSyncPolarity,
+ VideoTiming.VActiveVideo,
+ VideoTiming.V0FrontPorch,
+ VideoTiming.V0SyncWidth,
+ VideoTiming.V0BackPorch,
+ VideoTiming.V1FrontPorch,
+ VideoTiming.V1SyncWidth,
+ VideoTiming.V1BackPorch,
+ VideoTiming.VSyncPolarity,
+ VideoTiming.Interlaced ? "Yes" : "No (Progressive)");
+ }
+ }
+ xil_printf("\n\r");
+}
+
+/*****************************************************************************/
+/**
+*
+* This function prints the link status, selected resolution, bits per color and
+* link/lane count symbol error.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDpTxSs_ReportLinkInfo(XDpTxSs *InstancePtr)
+{
+ u8 Data[8];
+
+ /* Verify argument. */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /* Read Link rate over through channel */
+ XDp_TxAuxRead(InstancePtr->DpPtr, XDP_DPCD_LINK_BW_SET, 1, &Data);
+ xil_printf("\n\rLINK_BW_SET (0x00100) status in DPCD = %x\n\r",
+ (Data[0] & 0xFF));
+
+ /* Read Lane count through AUX channel */
+ XDp_TxAuxRead(InstancePtr->DpPtr, XDP_DPCD_LANE_COUNT_SET, 1,
+ &Data);
+ xil_printf("LANE_COUNT_SET (0x00101) status in DPCD = %x\n\r",
+ (Data[0] & XDP_DPCD_LANE_COUNT_SET_MASK));
+
+ /* Read Lane status through AUX channel */
+ XDp_TxAuxRead(InstancePtr->DpPtr, XDP_DPCD_STATUS_LANE_0_1, 2,
+ &Data);
+ xil_printf("LANE0_1_STATUS (0x00202) in DPCD = %x\n\r",
+ (Data[0] & 0xFF));
+ xil_printf("LANE2_3_STATUS (0x00203) in DPCD = %x\n\r",
+ (Data[1] & 0xFF));
+
+ /* Read symbol error through AUX channel */
+ XDp_TxAuxRead(InstancePtr->DpPtr,
+ XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_0, 8, &Data);
+ xil_printf("\n\rSYMBOL_ERROR_COUNT_LANE_0 (0x00210 and 0x00211) "
+ "Status = %x%x\n\r",(Data[1] & 0xFF00),(Data[0] & 0xFF));
+ xil_printf("SYMBOL_ERROR_COUNT_LANE_1 (0x00212 and 0x00213) "
+ "Status = %x%x\n\r",(Data[3] & 0xFF00),(Data[2] & 0xFF));
+ xil_printf("SYMBOL_ERROR_COUNT_LANE_2 (0x00214 and 0x00215) "
+ "Status = %x%x\n\r",(Data[5] & 0xFF00),(Data[4] & 0xFF));
+ xil_printf("SYMBOL_ERROR_COUNT_LANE_3 (0x00216 and 0x00217) "
+ "Status = %x%x\n\r",(Data[7] & 0xFF00),(Data[6] & 0xFF));
+
+ xil_printf("\n\rSelected Resolution = %s\n\r",
+ XVidC_GetVideoModeStr(InstancePtr->UsrOpt.VmId));
+ xil_printf("Selected BPC = %d\n\r",InstancePtr->UsrOpt.Bpc);
+
+ xil_printf("\n\r");
+}
+
+/*****************************************************************************/
+/**
+*
+* This function prints the current main stream attributes from the DisplayPort
+* TX core.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDpTxSs_ReportMsaInfo(XDpTxSs *InstancePtr)
+{
+
+ /* Verify argument. */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ XDp_Config *TxConfig = &InstancePtr->DpPtr->Config;
+
+ xil_printf("TX MSA registers:\n\r"
+ "\tClocks, H Total (0x180) : %ld\n\r"
+ "\tClocks, V Total (0x184) : %ld\n\r"
+ "\tPolarity (V / H) (0x188) : %ld\n\r"
+ "\tHSync Width (0x180) : %ld\n\r"
+ "\tVSync Width (0x180) : %ld\n\r"
+ "\tHorz Resolution (0x180) : %ld\n\r"
+ "\tVert Resolution (0x180) : %ld\n\r"
+ "\tHorz Start (0x180) : %ld\n\r"
+ "\tVert Start (0x180) : %ld\n\r"
+ "\tMisc0 (0x180) : 0x%08lX\n\r"
+ "\tMisc1 (0x180) : 0x%08lX\n\r"
+ "\tUser Pixel Width (0x180) : %ld\n\r"
+ "\tM Vid (0x180) : %ld\n\r"
+ "\tN Vid (0x180) : %ld\n\r"
+ "\tTransfer Unit Size (0x180) : %ld\n\r"
+ "\tUser Data Count (0x180) : %ld\n\r"
+ "\tMinimum bytes per TU (0x180) : %ld\n\r"
+ "\tFractional bytes per TU (0x180) : %ld\n\r"
+ "\tInit wait (0x180) : %ld\n\r",
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_HTOTAL),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_VTOTAL),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_POLARITY),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_HSWIDTH),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_VSWIDTH),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_HRES),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_VRES),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_HSTART),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_VSTART),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_MISC0),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_MISC1),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_USER_PIXEL_WIDTH),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_M_VID),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_N_VID),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_TU_SIZE),
+ XDp_ReadReg(TxConfig->BaseAddr,
+ XDP_TX_USER_DATA_COUNT_PER_LANE),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MIN_BYTES_PER_TU),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_FRAC_BYTES_PER_TU),
+ XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_INIT_WAIT)
+ );
+
+ xil_printf("\n\r");
+}
diff --git a/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_g.c b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_g.c
new file mode 100644
index 00000000..21c59365
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_g.c
@@ -0,0 +1,137 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xdptxss.h"
+
+/*
+* The configuration table for devices
+*/
+
+#define XPAR_DP_TX_SUBSYSTEM_0_DP_PRESENT 1
+#define XPAR_DP_TX_SUBSYSTEM_0_VS_PRESENT 1
+#define XPAR_DP_TX_SUBSYSTEM_0_VTC1_PRESENT 1
+#define XPAR_DP_TX_SUBSYSTEM_0_VTC2_PRESENT 1
+#define XPAR_DP_TX_SUBSYSTEM_0_VTC3_PRESENT 1
+#define XPAR_DP_TX_SUBSYSTEM_0_VTC4_PRESENT 1
+
+
+XDpTxSs_Config XDpTxSs_ConfigTable[] =
+{
+ {
+ XPAR_DP_TX_SUBSYSTEM_0_DEVICE_ID,
+ XPAR_DP_TX_SUBSYSTEM_0_BASEADDR,
+ XPAR_DP_TX_SUBSYSTEM_0_AUDIO_ENABLE,
+ XPAR_DP_TX_SUBSYSTEM_0_BITS_PER_COLOR,
+ XPAR_DP_TX_SUBSYSTEM_0_HDCP_ENABLE,
+ XPAR_DP_TX_SUBSYSTEM_0_LANE_COUNT,
+ XPAR_DP_TX_SUBSYSTEM_0_MODE,
+ XPAR_DP_TX_SUBSYSTEM_0_NUM_STREAMS,
+
+ {
+ XPAR_DP_TX_SUBSYSTEM_0_DP_PRESENT,
+ {
+ XPAR_DP_TX_SUBSYSTEM_0_DP_DEVICE_ID,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_BASEADDR,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_S_AXI_ACLK,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_LANE_COUNT,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_LINK_RATE,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_MAX_BITS_PER_COLOR,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_QUAD_PIXEL_ENABLE,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_DUAL_PIXEL_ENABLE,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_YCRCB_ENABLE,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_YONLY_ENABLE,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_GT_DATAWIDTH,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_SECONDARY_SUPPORT,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_AUDIO_CHANNELS,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_MST_ENABLE,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_NUMBER_OF_MST_STREAMS,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_PROTOCOL_SELECTION,
+ XPAR_DP_TX_SUBSYSTEM_0_DP_FLOW_DIRECTION
+ }
+ },
+ {
+ XPAR_DP_TX_SUBSYSTEM_0_VS_PRESENT,
+ {
+ XPAR_DP_TX_SUBSYSTEM_0_VS_DEVICE_ID,
+ XPAR_DP_TX_SUBSYSTEM_0_VS_BASEADDR,
+ XPAR_DP_TX_SUBSYSTEM_0_VS_ACTIVE_COLS,
+ XPAR_DP_TX_SUBSYSTEM_0_VS_ACTIVE_ROWS,
+ XPAR_DP_TX_SUBSYSTEM_0_VS_MAX_SEGMENTS,
+ XPAR_DP_TX_SUBSYSTEM_0_VS_AXIS_VIDEO_MAX_TDATA_WIDTH,
+ XPAR_DP_TX_SUBSYSTEM_0_VS_AXIS_VIDEO_MAX_ITDATASMPLS_PER_CLK,
+ XPAR_DP_TX_SUBSYSTEM_0_VS_AXIS_VIDEO_MAX_OTDATASMPLS_PER_CLK,
+ XPAR_DP_TX_SUBSYSTEM_0_VS_MAX_OVRLAP,
+ XPAR_DP_TX_SUBSYSTEM_0_VS_MAX_SMPL_WIDTH,
+ XPAR_DP_TX_SUBSYSTEM_0_VS_HAS_AXI4_LITE,
+ XPAR_DP_TX_SUBSYSTEM_0_VS_HAS_IRQ
+ }
+ },
+ {
+ {
+ XPAR_DP_TX_SUBSYSTEM_0_VTC1_PRESENT,
+ {
+ XPAR_DP_TX_SUBSYSTEM_0_VTC1_DEVICE_ID,
+ XPAR_DP_TX_SUBSYSTEM_0_VTC1_BASEADDR
+ }
+ },
+ {
+ XPAR_DP_TX_SUBSYSTEM_0_VTC2_PRESENT,
+ {
+ XPAR_DP_TX_SUBSYSTEM_0_VTC2_DEVICE_ID,
+ XPAR_DP_TX_SUBSYSTEM_0_VTC2_BASEADDR
+ }
+ },
+ {
+ XPAR_DP_TX_SUBSYSTEM_0_VTC3_PRESENT,
+ {
+ XPAR_DP_TX_SUBSYSTEM_0_VTC3_DEVICE_ID,
+ XPAR_DP_TX_SUBSYSTEM_0_VTC3_BASEADDR
+ }
+ },
+ {
+ XPAR_DP_TX_SUBSYSTEM_0_VTC4_PRESENT,
+ {
+ XPAR_DP_TX_SUBSYSTEM_0_VTC4_DEVICE_ID,
+ XPAR_DP_TX_SUBSYSTEM_0_VTC4_BASEADDR
+ }
+ }
+ }
+ }
+};
diff --git a/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_hw.h b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_hw.h
new file mode 100644
index 00000000..a0fb66c8
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_hw.h
@@ -0,0 +1,173 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdptxss_hw.h
+*
+* This header file contains identifiers and register-level core functions (or
+* macros) that can be used to access the Xilinx DisplayPort Transmitter
+* Subsystem core.
+*
+* For more information about the operation of this core see the hardware
+* specification and documentation in the higher level driver
+* xdptxss.h file.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ---- --- -------- --------------------------------------------------
+* 1.00 sha 01/29/15 Initial release.
+*
+*
+******************************************************************************/
+#ifndef XDPTXSS_HW_H_
+#define XDPTXSS_HW_H_ /**< Prevent circular inclusions
+ * by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/* 0x000: LINK_BW_SET */
+#define XDPTXSS_LINK_BW_SET_162GBPS XDP_TX_LINK_BW_SET_162GBPS /**< 1.62
+ * Gbps
+ * link
+ * rate. */
+#define XDPTXSS_LINK_BW_SET_270GBPS XDP_TX_LINK_BW_SET_270GBPS /**< 2.70
+ * Gbps
+ * link
+ * rate. */
+#define XDPTXSS_LINK_BW_SET_540GBPS XDP_TX_LINK_BW_SET_540GBPS /**< 5.40
+ * Gbps
+ * link
+ * rate. */
+
+/* 0x001: LANE_COUNT_SET */
+#define XDPTXSS_LANE_COUNT_SET_1 XDP_TX_LANE_COUNT_SET_1 /**< Lane count
+ * of 1. */
+#define XDPTXSS_LANE_COUNT_SET_2 XDP_TX_LANE_COUNT_SET_2 /**< Lane count
+ * of 2. */
+#define XDPTXSS_LANE_COUNT_SET_4 XDP_TX_LANE_COUNT_SET_4 /**< Lane count
+ * of 4. */
+
+/* 0x144: INTERRUPT_MASK */
+#define XDPTXSS_INTERRUPT_MASK XDP_TX_INTERRUPT_MASK /**< Masks the
+ * specified
+ * interrupt
+ * sources */
+#define XDPTXSS_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK \
+ XDP_TX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK /**< Mask HPD
+ * pulse
+ * detected
+ * interrupt
+ */
+#define XDPTXSS_INTERRUPT_MASK_HPD_EVENT_MASK \
+ XDP_TX_INTERRUPT_MASK_HPD_EVENT_MASK /**< Mask HPD event
+ * interrupt. */
+
+#define XDPTXSS_NUM_STREAMS 4 /**< Maximum number of
+ * streams supported */
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/** @name Register access macro definition
+* @{
+*/
+#define XDpTxSs_In32 Xil_In32 /**< Input Operations */
+#define XDpTxSs_Out32 Xil_Out32 /**< Output Operations */
+
+/*****************************************************************************/
+/**
+*
+* This macro reads a value from a DisplayPort Transmitter Subsystem register.
+* A 32 bit read is performed. If the component is implemented in a smaller
+* width, only the least significant data is read from the register. The most
+* significant data will be read as 0.
+*
+* @param BaseAddress is the base address of the XDpTxSs core instance.
+* @param RegOffset is the register offset of the register (defined at
+* the top of this file).
+*
+* @return The 32-bit value of the register.
+*
+* @note C-style signature:
+* u32 XDpTxSs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+******************************************************************************/
+#define XDpTxSs_ReadReg(BaseAddress, RegOffset) \
+ XDpTxSs_In32((BaseAddress) + ((u32)RegOffset))
+
+/*****************************************************************************/
+/**
+*
+* This macro writes a value to a DisplayPort Transmitter Subsystem register.
+* A 32 bit write is performed. If the component is implemented in a smaller
+* width, only the least significant data is written.
+*
+* @param BaseAddress is the base address of the XDpTxSs core instance.
+* @param RegOffset is the register offset of the register (defined at
+* the top of this file) to be written.
+* @param Data is the 32-bit value to write into the register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDpTxSs_WriteReg(u32 BaseAddress, u32 RegOffset,
+* u32 Data)
+*
+******************************************************************************/
+#define XDpTxSs_WriteReg(BaseAddress, RegOffset, Data) \
+ XDpTxSs_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
+/*@}*/
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Declarations ****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
\ No newline at end of file
diff --git a/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_intr.c b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_intr.c
new file mode 100644
index 00000000..7523026d
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_intr.c
@@ -0,0 +1,190 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdptxss_intr.c
+*
+* This file contains interrupt related functions of Xilinx DisplayPort TX
+* Subsystem core. Please see xdptxss.h for more details of the core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ---- --- -------- --------------------------------------------------
+* 1.00 sha 01/29/15 Initial release.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdptxss.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the DisplayPort TX core operating
+* in TX mode.
+*
+* The application is responsible for connecting this function to the interrupt
+* system. Application beyond this driver is also responsible for providing
+* callbacks to handle interrupts and installing the callbacks using
+* XDptxss_SetCallBack() during initialization phase.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance that
+* just interrupted.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDpTxSs_DpIntrHandler(void *InstancePtr)
+{
+ XDpTxSs *XDpTxSsPtr = (XDpTxSs *)InstancePtr;
+
+ /* Verify arguments. */
+ Xil_AssertVoid(XDpTxSsPtr != NULL);
+ Xil_AssertVoid(XDpTxSsPtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* DisplayPort TX interrupt handler */
+ XDp_InterruptHandler(XDpTxSsPtr->DpPtr);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function installs an asynchronous callback function for the given
+* HandlerType:
+*
+*
+* HandlerType Callback Function Type
+* ------------------------------ ---------------------------------------------
+* (XDPTXSS_HANDLER_DP_HPD_EVENT) XDp_TxSetHpdEventHandler
+* (XDPTXSS_HANDLER_DP_HPD_PULSE) XDp_TxSetHpdPulseHandler
+*
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+* @param HandlerType specifies the type of handler.
+* @param CallbackFunc is the address of the callback function.
+* @param CallbackRef is a user data item that will be passed to the
+* callback function when it is invoked.
+*
+* @return
+* - XST_SUCCESS if callback function installed successfully.
+* - XST_INVALID_PARAM when HandlerType is invalid.
+*
+* @note Invoking this function for a handler that already has been
+* installed replaces it with the new handler.
+*
+******************************************************************************/
+u32 XDpTxSs_SetCallBack(XDpTxSs *InstancePtr, u32 HandlerType,
+ void *CallbackFunc, void *CallbackRef)
+{
+ u32 Status;
+
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(HandlerType >= XDPTXSS_HANDLER_DP_HPD_EVENT);
+ Xil_AssertNonvoid(CallbackFunc != NULL);
+ Xil_AssertNonvoid(CallbackRef != NULL);
+
+ /* Assign callback based on handler type */
+ switch (HandlerType) {
+ case XDPTXSS_HANDLER_DP_HPD_EVENT:
+ XDp_TxSetHpdEventHandler(InstancePtr->DpPtr,
+ CallbackFunc, CallbackRef);
+ Status = XST_SUCCESS;
+ break;
+
+ case XDPTXSS_HANDLER_DP_HPD_PULSE:
+ XDp_TxSetHpdPulseHandler(InstancePtr->DpPtr,
+ CallbackFunc, CallbackRef);
+ Status = XST_SUCCESS;
+ break;
+
+ default:
+ Status = XST_INVALID_PARAM;
+ break;
+ }
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function installs a custom delay/sleep function to be used by the
+* DisplayPort TX Subsystem.
+*
+* @param InstancePtr is a pointer to the XDpTxSs instance.
+* @param CallbackFunc is the address to the callback function.
+* @param CallbackRef is the user data item (microseconds to delay) that
+* will be passed to the custom sleep/delay function when it is
+* invoked.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDpTxSs_SetUserTimerHandler(XDpTxSs *InstancePtr,
+ XDpTxSs_TimerHandler CallbackFunc, void *CallbackRef)
+{
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(CallbackFunc != NULL);
+ Xil_AssertVoid(CallbackRef != NULL);
+
+ /* Set custom timer wait handler */
+ XDp_SetUserTimerHandler(InstancePtr->DpPtr, CallbackFunc, CallbackRef);
+}
diff --git a/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_selftest.c b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_selftest.c
new file mode 100644
index 00000000..066b9683
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_selftest.c
@@ -0,0 +1,124 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdptxss_selftest.c
+*
+* This file contains self test function for the DisplayPort Transmitter
+* Subsystem core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ---- --- -------- --------------------------------------------------
+* 1.00 sha 01/29/15 Initial release.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdptxss.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function performs self test on DisplayPort Transmitter Subsystem
+* sub-cores.
+*
+* @param InstancePtr is a pointer to the XDpTxSs core instance.
+*
+* @return
+* - XST_SUCCESS if self test passed.
+* - XST_FAILURE if self test failed.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XDpTxSs_SelfTest(XDpTxSs *InstancePtr)
+{
+ u32 Status;
+ u32 Index;
+
+ /* Verify argument. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ if (InstancePtr->DpPtr) {
+ Status = XDp_SelfTest(InstancePtr->DpPtr);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"ERR::DP Self test "
+ "failed\r\n");
+ }
+ }
+
+#if (XPAR_XDUALSPLITTER_NUM_INSTANCES > 0)
+ if (InstancePtr->DsPtr) {
+ Status = XDualSplitter_SelfTest(InstancePtr->DsPtr);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"ERR::Dual Splitter "
+ "Self test failed\r\n");
+ }
+ }
+#endif
+
+ for (Index = 0; Index < InstancePtr->Config.NumMstStreams; Index++) {
+ if (InstancePtr->VtcPtr[Index]) {
+ Status = XVtc_SelfTest(InstancePtr->VtcPtr[Index]);
+ if (Status != XST_SUCCESS) {
+ xdbg_printf(XDBG_DEBUG_GENERAL,"ERR::VTC%d "
+ "Self test failed\n\r",
+ Index);
+ }
+ }
+ }
+
+ return XST_SUCCESS;
+}
diff --git a/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_sinit.c b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_sinit.c
new file mode 100644
index 00000000..89776651
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/dptxss/src/xdptxss_sinit.c
@@ -0,0 +1,108 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdptxss_sinit.c
+*
+* This file contains static initialization method for Xilinx DisplayPort
+* Transmitter Subsystem core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ---- --- -------- --------------------------------------------------
+* 1.00 sha 01/29/15 Initial release.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdptxss.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function returns a reference to an XDptxss_Config structure based
+* on the core id, DeviceId. The return value will refer to an entry in
+* the device configuration table defined in the xdptxss_g.c file.
+*
+* @param DeviceId is the unique core ID of the XDpTxSs core for
+* the lookup operation.
+*
+* @return XDptxss_LookupConfig returns a reference to a config record
+* in the configuration table (in xdptxss_g.c) corresponding
+* to DeviceId, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XDpTxSs_Config *XDpTxSs_LookupConfig(u16 DeviceId)
+{
+ extern XDpTxSs_Config XDpTxSs_ConfigTable[XPAR_XDPTXSS_NUM_INSTANCES];
+ XDpTxSs_Config *CfgPtr = NULL;
+ u32 Index;
+
+ /* Checking for device id for which instance it is matching */
+ for (Index = (u32)0x0; Index < (u32)XPAR_XDPTXSS_NUM_INSTANCES;
+ Index++) {
+ /* Assigning address of config table if both device ids
+ * are matched
+ */
+ if (XDpTxSs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XDpTxSs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XDpTxSs_Config *)CfgPtr;
+}