From 2ebd71bd569fa58674845a35b6287c1c88c4b8a0 Mon Sep 17 00:00:00 2001 From: Andrei-Liviu Simion Date: Sun, 17 Aug 2014 17:26:37 -0700 Subject: [PATCH] dptx: Exporting additional IP configuration parameters. Signed-off-by: Andrei-Liviu Simion --- .../drivers/dptx/data/dptx.tcl | 6 ++-- XilinxProcessorIPLib/drivers/dptx/src/xdptx.c | 17 +++++++++- XilinxProcessorIPLib/drivers/dptx/src/xdptx.h | 31 +++++++++++++------ 3 files changed, 41 insertions(+), 13 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/dptx/data/dptx.tcl b/XilinxProcessorIPLib/drivers/dptx/data/dptx.tcl index b23e575c..eb02e3da 100644 --- a/XilinxProcessorIPLib/drivers/dptx/data/dptx.tcl +++ b/XilinxProcessorIPLib/drivers/dptx/data/dptx.tcl @@ -30,9 +30,9 @@ ## ##*****************************************************************************/ proc generate {drv_handle} { - xdefine_include_file $drv_handle "xparameters.h" "XDptx" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "S_AXI_ACLK" - xdefine_config_file $drv_handle "xdptx_g.c" "XDptx" "DEVICE_ID" "C_BASEADDR" "S_AXI_ACLK" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" - xdefine_canonical_xpars $drv_handle "xparameters.h" "XDptx" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "S_AXI_ACLK" + xdefine_include_file $drv_handle "xparameters.h" "XDptx" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "C_GT_DATAWIDTH" "C_SECONDARY_SUPPORT" "C_AUDIO_CHANNELS" "C_MST_ENABLE" "C_NUMBER_OF_MST_STREAMS" "C_PROTOCOL_SELECTION" "S_AXI_ACLK" + xdefine_config_file $drv_handle "xdptx_g.c" "XDptx" "DEVICE_ID" "C_BASEADDR" "S_AXI_ACLK" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "C_GT_DATAWIDTH" "C_SECONDARY_SUPPORT" "C_AUDIO_CHANNELS" "C_MST_ENABLE" "C_NUMBER_OF_MST_STREAMS" "C_PROTOCOL_SELECTION" + xdefine_canonical_xpars $drv_handle "xparameters.h" "XDptx" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_LANE_COUNT" "C_LINK_RATE" "C_MAX_BITS_PER_COLOR" "C_QUAD_PIXEL_ENABLE" "C_DUAL_PIXEL_ENABLE" "C_YCRCB_ENABLE" "C_YONLY_ENABLE" "C_GT_DATAWIDTH" "C_SECONDARY_SUPPORT" "C_AUDIO_CHANNELS" "C_MST_ENABLE" "C_NUMBER_OF_MST_STREAMS" "C_PROTOCOL_SELECTION" "S_AXI_ACLK" } # diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c index 0fe4a22c..8b4d4229 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c @@ -247,8 +247,23 @@ void XDptx_CfgInitialize(XDptx *InstancePtr, XDptx_Config *ConfigPtr, InstancePtr->Config.BaseAddr = EffectiveAddr; InstancePtr->Config.SAxiClkHz = ConfigPtr->SAxiClkHz; - InstancePtr->Config.MaxLinkRate = ConfigPtr->MaxLinkRate; InstancePtr->Config.MaxLaneCount = ConfigPtr->MaxLaneCount; + InstancePtr->Config.MaxLinkRate = ConfigPtr->MaxLinkRate; + + InstancePtr->Config.MaxBitsPerColor = ConfigPtr->MaxBitsPerColor; + InstancePtr->Config.QuadPixelEn = ConfigPtr->QuadPixelEn; + InstancePtr->Config.DualPixelEn = ConfigPtr->DualPixelEn; + InstancePtr->Config.YCrCbEn = ConfigPtr->YCrCbEn; + InstancePtr->Config.YOnlyEn = ConfigPtr->YOnlyEn; + InstancePtr->Config.PayloadDataWidth = ConfigPtr->PayloadDataWidth; + + InstancePtr->Config.SecondaryChEn = ConfigPtr->SecondaryChEn; + InstancePtr->Config.NumAudioChs = ConfigPtr->NumAudioChs; + + InstancePtr->Config.MstSupport = ConfigPtr->MstSupport; + InstancePtr->Config.NumMstStreams = ConfigPtr->NumMstStreams; + + InstancePtr->Config.DpProtocol = ConfigPtr->DpProtocol; /* Set the DisplayPort TX's voltage swing and pre-emphasis levels to * their defaults. */ diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h index 9fcf3969..b6a0c0c0 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h @@ -337,23 +337,36 @@ typedef enum { */ typedef struct { u16 DeviceId; /**< Device instance ID. */ - u32 BaseAddr; /**< The base address of the core. */ - u32 SAxiClkHz; /**< The clock frequency of the core's + u32 BaseAddr; /**< The base address of the core instance. */ + u32 SAxiClkHz; /**< The clock frequency of the core instance's S_AXI_ACLK port. */ u8 MaxLaneCount; /**< The maximum lane count supported by this - core's instance. */ + core instance. */ u8 MaxLinkRate; /**< The maximum link rate supported by this - core's instance. */ + core instance. */ u8 MaxBitsPerColor; /**< The maximum bits/color supported by this - core's instance*/ - u8 QuadPixelEn; /**< Quad pixel support by this core's + core instance*/ + u8 QuadPixelEn; /**< Quad pixel support by this core instance. */ - u8 DualPixelEn; /**< Dual pixel support by this core's + u8 DualPixelEn; /**< Dual pixel support by this core instance. */ - u8 YOnlyEn; /**< YOnly format support by this core's + u8 YCrCbEn; /**< YCrCb format support by this core instance. */ - u8 YCrCbEn; /**< YCrCb format support by this core's + u8 YOnlyEn; /**< YOnly format support by this core instance. */ + u8 PayloadDataWidth; /**< The payload data width used by this core + instance. */ + u8 SecondaryChEn; /**< This core instance supports audio packets + being sent by the secondary channel. */ + u8 NumAudioChs; /**< The number of audio channels supported by + this core instance. */ + u8 MstSupport; /**< Multi-stream transport (MST) mode is + enabled by this core instance. */ + u8 NumMstStreams; /**< The total number of MST streams supported + by this core instance. */ + u8 DpProtocol; /**< The DisplayPort protocol version that this + core instance is configured for. + 0 = v1.1a, 1 = v1.2. */ } XDptx_Config; /**