From 2ffa12ed7ce63a845f98b415664427d987b1347b Mon Sep 17 00:00:00 2001 From: Venkata Naga Sai Krishna Kolapalli Date: Mon, 20 Apr 2015 16:29:44 +0530 Subject: [PATCH] gpiops_v3_1 : Convert 3-line comments to 1-liners. Driverwide, scripted change to convert 3-line comments to single line comments. Signed-off-by: Venkata Naga Sai Krishna Kolapalli --- .../gpiops/examples/xgpiops_intr_example.c | 48 +++++-------------- .../gpiops/examples/xgpiops_polled_example.c | 44 +++++------------ .../drivers/gpiops/src/xgpiops.c | 32 ++++--------- .../drivers/gpiops/src/xgpiops.h | 32 ++++--------- .../drivers/gpiops/src/xgpiops_hw.c | 36 ++++---------- .../drivers/gpiops/src/xgpiops_intr.c | 36 ++++---------- .../drivers/gpiops/src/xgpiops_selftest.c | 4 +- 7 files changed, 58 insertions(+), 174 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/gpiops/examples/xgpiops_intr_example.c b/XilinxProcessorIPLib/drivers/gpiops/examples/xgpiops_intr_example.c index 67aa7a10..857a27fa 100644 --- a/XilinxProcessorIPLib/drivers/gpiops/examples/xgpiops_intr_example.c +++ b/XilinxProcessorIPLib/drivers/gpiops/examples/xgpiops_intr_example.c @@ -72,15 +72,11 @@ #define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID #define GPIO_INTERRUPT_ID XPAR_XGPIOPS_0_INTR -/* - * The following constants define the GPIO banks that are used. - */ +/* The following constants define the GPIO banks that are used. */ #define INPUT_BANK XGPIOPS_BANK0 /* Bank 0 of the GPIO Device */ #define OUTPUT_BANK XGPIOPS_BANK1 /* Bank 1 of the GPIO Device */ -/* - * The following constants define the positions of the buttons of the GPIO. - */ +/* The following constants define the positions of the buttons of the GPIO. */ #define GPIO_ALL_BUTTONS 0xFFFF /* @@ -174,18 +170,14 @@ int GpioIntrExample(XScuGic *Intc, XGpioPs *Gpio, u16 DeviceId, u16 GpioIntrId) XGpioPs_Config *ConfigPtr; int Status; - /* - * Initialize the Gpio driver. - */ + /* Initialize the Gpio driver. */ ConfigPtr = XGpioPs_LookupConfig(DeviceId); if (ConfigPtr == NULL) { return XST_FAILURE; } XGpioPs_CfgInitialize(Gpio, ConfigPtr, ConfigPtr->BaseAddr); - /* - * Run a self-test on the GPIO device. - */ + /* Run a self-test on the GPIO device. */ Status = XGpioPs_SelfTest(Gpio); if (Status != XST_SUCCESS) { return XST_FAILURE; @@ -247,24 +239,18 @@ static void IntrHandler(void *CallBackRef, u32 Bank, u32 Status) XGpioPs *Gpio = (XGpioPs *)CallBackRef; static u32 ButtonsChanged; - /* - * Do nothing if the intr is generated for a different bank. - */ + /* Do nothing if the intr is generated for a different bank. */ if (Bank != INPUT_BANK) { return; } ButtonsChanged |= Status; - /* - * Set the LEDs. - */ + /* Set the LEDs. */ XGpioPs_Write(Gpio, OUTPUT_BANK, ButtonsChanged); if (ButtonsChanged == GPIO_EXIT_CONTROL_VALUE) { - /* - * Five buttons are pressed to mark the completion of the test. - */ + /* Five buttons are pressed to mark the completion of the test. */ AllButtonsPressed = TRUE; ButtonsChanged = 0; } @@ -335,32 +321,22 @@ static int SetupInterruptSystem(XScuGic *GicInstancePtr, XGpioPs *Gpio, return Status; } - /* - * Enable falling edge interrupts for all the pins in bank 0. - */ + /* Enable falling edge interrupts for all the pins in bank 0. */ XGpioPs_SetIntrType(Gpio, INPUT_BANK, 0x00, 0x00, 0x00); - /* - * Set the handler for gpio interrupts. - */ + /* Set the handler for gpio interrupts. */ XGpioPs_SetCallbackHandler(Gpio, (void *)Gpio, IntrHandler); - /* - * Enable the GPIO interrupts of Bank 0. - */ + /* Enable the GPIO interrupts of Bank 0. */ XGpioPs_IntrEnable(Gpio, INPUT_BANK, 0xFFFFFFFF); - /* - * Enable the interrupt for the GPIO device. - */ + /* Enable the interrupt for the GPIO device. */ XScuGic_Enable(GicInstancePtr, GpioIntrId); - /* - * Enable interrupts in the Processor. - */ + /* Enable interrupts in the Processor. */ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ); return XST_SUCCESS; diff --git a/XilinxProcessorIPLib/drivers/gpiops/examples/xgpiops_polled_example.c b/XilinxProcessorIPLib/drivers/gpiops/examples/xgpiops_polled_example.c index 58b1d711..76bdc581 100644 --- a/XilinxProcessorIPLib/drivers/gpiops/examples/xgpiops_polled_example.c +++ b/XilinxProcessorIPLib/drivers/gpiops/examples/xgpiops_polled_example.c @@ -91,9 +91,7 @@ */ #define LED_DELAY 10000000 -/* - * Following constant define the Input and Output pins. - */ +/* Following constant define the Input and Output pins. */ #define OUTPUT_PIN 10 /* Pin connected to LED/Output */ #define INPUT_PIN 14 /* Pin connected to Switch/Input */ @@ -173,9 +171,7 @@ int GpioPolledExample(u16 DeviceId, u32 *DataRead) int Status; XGpioPs_Config *ConfigPtr; - /* - * Initialize the GPIO driver. - */ + /* Initialize the GPIO driver. */ ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID); Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr); @@ -183,17 +179,13 @@ int GpioPolledExample(u16 DeviceId, u32 *DataRead) return XST_FAILURE; } - /* - * Run the Output Example. - */ + /* Run the Output Example. */ Status = GpioOutputExample(); if (Status != XST_SUCCESS) { return XST_FAILURE; } - /* - * Run the Input Example. - */ + /* Run the Input Example. */ Status = GpioInputExample(DataRead); if (Status != XST_SUCCESS) { return XST_FAILURE; @@ -228,9 +220,7 @@ static int GpioOutputExample(void) XGpioPs_SetDirectionPin(&Gpio, OUTPUT_PIN, 1); XGpioPs_SetOutputEnablePin(&Gpio, OUTPUT_PIN, 1); - /* - * Set the GPIO output to be low. - */ + /* Set the GPIO output to be low. */ XGpioPs_WritePin(&Gpio, OUTPUT_PIN, 0x0); @@ -238,15 +228,11 @@ static int GpioOutputExample(void) #ifndef __SIM__ - /* - * Wait a small amount of time so the LED is visible. - */ + /* Wait a small amount of time so the LED is visible. */ for (Delay = 0; Delay < LED_DELAY; Delay++); #endif - /* - * Set the GPIO Output to High. - */ + /* Set the GPIO Output to High. */ XGpioPs_WritePin(&Gpio, OUTPUT_PIN, 0x1); /* @@ -260,16 +246,12 @@ static int GpioOutputExample(void) } #ifndef __SIM__ - /* - * Wait a small amount of time so the LED is visible. - */ + /* Wait a small amount of time so the LED is visible. */ for (Delay = 0; Delay < LED_DELAY; Delay++); #endif - /* - * Clear the GPIO Output. - */ + /* Clear the GPIO Output. */ XGpioPs_WritePin(&Gpio, OUTPUT_PIN, 0x0); /* @@ -303,14 +285,10 @@ static int GpioOutputExample(void) static int GpioInputExample(u32 *DataRead) { - /* - * Set the direction for the specified pin to be input. - */ + /* Set the direction for the specified pin to be input. */ XGpioPs_SetDirectionPin(&Gpio, INPUT_PIN, 0x0); - /* - * Read the state of the data so that it can be verified. - */ + /* Read the state of the data so that it can be verified. */ *DataRead = XGpioPs_ReadPin(&Gpio, INPUT_PIN); return XST_SUCCESS; diff --git a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.c b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.c index ac52207a..3b298435 100644 --- a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.c +++ b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.c @@ -145,9 +145,7 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr, XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU); } - /* - * Indicate the component is now ready to use. - */ + /* Indicate the component is now ready to use. */ InstancePtr->IsReady = XIL_COMPONENT_IS_READY; return Status; @@ -204,9 +202,7 @@ u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); - /* - * Get the Bank number and Pin number within the bank. - */ + /* Get the Bank number and Pin number within the bank. */ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, @@ -271,15 +267,11 @@ void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data) Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); - /* - * Get the Bank number and Pin number within the bank. - */ + /* Get the Bank number and Pin number within the bank. */ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); if (PinNumber > 15U) { - /* - * There are only 16 data bits in bit maskable register. - */ + /* There are only 16 data bits in bit maskable register. */ PinNumber -= (u8)16; RegOffset = XGPIOPS_DATA_MSW_OFFSET; } else { @@ -354,9 +346,7 @@ void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction) Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); Xil_AssertVoid(Direction <= (u32)1); - /* - * Get the Bank number and Pin number within the bank. - */ + /* Get the Bank number and Pin number within the bank. */ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, @@ -426,9 +416,7 @@ u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); - /* - * Get the Bank number and Pin number within the bank. - */ + /* Get the Bank number and Pin number within the bank. */ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, @@ -495,9 +483,7 @@ void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable) Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); Xil_AssertVoid(OpEnable <= (u32)1); - /* - * Get the Bank number and Pin number within the bank. - */ + /* Get the Bank number and Pin number within the bank. */ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, @@ -567,9 +553,7 @@ u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); - /* - * Get the Bank number and Pin number within the bank. - */ + /* Get the Bank number and Pin number within the bank. */ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, diff --git a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.h b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.h index d0ac1592..696b9bbc 100644 --- a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.h +++ b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops.h @@ -205,15 +205,11 @@ typedef struct { /************************** Function Prototypes ******************************/ -/* - * Functions in xgpiops.c - */ +/* Functions in xgpiops.c */ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr, u32 EffectiveAddr); -/* - * Bank APIs in xgpiops.c - */ +/* Bank APIs in xgpiops.c */ u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank); void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data); void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction); @@ -222,9 +218,7 @@ void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable); u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank); void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank); -/* - * Pin APIs in xgpiops.c - */ +/* Pin APIs in xgpiops.c */ u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin); void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data); void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction); @@ -232,17 +226,11 @@ u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin); void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable); u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin); -/* - * Diagnostic functions in xgpiops_selftest.c - */ +/* Diagnostic functions in xgpiops_selftest.c */ s32 XGpioPs_SelfTest(XGpioPs *InstancePtr); -/* - * Functions in xgpiops_intr.c - */ -/* - * Bank APIs in xgpiops_intr.c - */ +/* Functions in xgpiops_intr.c */ +/* Bank APIs in xgpiops_intr.c */ void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank); @@ -256,9 +244,7 @@ void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef, XGpioPs_Handler FuncPointer); void XGpioPs_IntrHandler(XGpioPs *InstancePtr); -/* - * Pin APIs in xgpiops_intr.c - */ +/* Pin APIs in xgpiops_intr.c */ void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType); u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin); @@ -268,9 +254,7 @@ u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin); u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin); void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin); -/* - * Functions in xgpiops_sinit.c - */ +/* Functions in xgpiops_sinit.c */ XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId); #ifdef __cplusplus diff --git a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_hw.c b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_hw.c index a116165c..2e499149 100644 --- a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_hw.c +++ b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_hw.c @@ -89,9 +89,7 @@ void XGpioPs_ResetHw(u32 BaseAddress) } else { MaxBanks = (u32)4; } - /* - * Write reset values to all mask data registers - */ + /* Write reset values to all mask data registers */ for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) { XGpioPs_WriteReg(BaseAddress, @@ -101,9 +99,7 @@ void XGpioPs_ResetHw(u32 BaseAddress) ((BankCount * XGPIOPS_DATA_MASK_OFFSET) + XGPIOPS_DATA_MSW_OFFSET), 0x0U); } - /* - * Write reset values to all output data registers - */ + /* Write reset values to all output data registers */ for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) { XGpioPs_WriteReg(BaseAddress, @@ -111,9 +107,7 @@ void XGpioPs_ResetHw(u32 BaseAddress) XGPIOPS_DATA_OFFSET), 0x0U); } - /* - * Reset all registers of all GPIO banks - */ + /* Reset all registers of all GPIO banks */ for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) { XGpioPs_WriteReg(BaseAddress, @@ -142,40 +136,28 @@ void XGpioPs_ResetHw(u32 BaseAddress) XGPIOPS_INTANY_OFFSET), 0x0U); } - /* - * Bank 0 Int type - */ + /* Bank 0 Int type */ XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET, XGPIOPS_INTTYPE_BANK0_RESET); - /* - * Bank 1 Int type - */ + /* Bank 1 Int type */ XGpioPs_WriteReg(BaseAddress, ((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET), XGPIOPS_INTTYPE_BANK1_RESET); - /* - * Bank 2 Int type - */ + /* Bank 2 Int type */ XGpioPs_WriteReg(BaseAddress, (((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), XGPIOPS_INTTYPE_BANK2_RESET); - /* - * Bank 3 Int type - */ + /* Bank 3 Int type */ XGpioPs_WriteReg(BaseAddress, (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), XGPIOPS_INTTYPE_BANK3_RESET); if (Platform == XPLAT_ZYNQ_ULTRA_MP) { - /* - * Bank 4 Int type - */ + /* Bank 4 Int type */ XGpioPs_WriteReg(BaseAddress, (((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), XGPIOPS_INTTYPE_BANK4_RESET); - /* - * Bank 5 Int type - */ + /* Bank 5 Int type */ XGpioPs_WriteReg(BaseAddress, (((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), XGPIOPS_INTTYPE_BANK5_RESET); diff --git a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_intr.c b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_intr.c index 33dd8b23..be0a04ce 100644 --- a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_intr.c +++ b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_intr.c @@ -119,9 +119,7 @@ void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); - /* - * Get the Bank number and Pin number within the bank. - */ + /* Get the Bank number and Pin number within the bank. */ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); IntrReg = ((u32)1 << (u32)PinNumber); @@ -183,9 +181,7 @@ void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); - /* - * Get the Bank number and Pin number within the bank. - */ + /* Get the Bank number and Pin number within the bank. */ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); IntrReg = ((u32)1 << (u32)PinNumber); @@ -252,9 +248,7 @@ u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); - /* - * Get the Bank number and Pin number within the bank. - */ + /* Get the Bank number and Pin number within the bank. */ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, @@ -316,9 +310,7 @@ u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); - /* - * Get the Bank number and Pin number within the bank. - */ + /* Get the Bank number and Pin number within the bank. */ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, @@ -351,9 +343,7 @@ void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask) Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(Bank < InstancePtr->MaxBanks); - /* - * Clear the currently pending interrupts. - */ + /* Clear the currently pending interrupts. */ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTSTS_OFFSET, Mask); @@ -382,14 +372,10 @@ void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); - /* - * Get the Bank number and Pin number within the bank. - */ + /* Get the Bank number and Pin number within the bank. */ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); - /* - * Clear the specified pending interrupts. - */ + /* Clear the specified pending interrupts. */ IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTSTS_OFFSET); @@ -522,9 +508,7 @@ void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType) Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW); - /* - * Get the Bank number and Pin number within the bank. - */ + /* Get the Bank number and Pin number within the bank. */ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, @@ -608,9 +592,7 @@ u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); - /* - * Get the Bank number and Pin number within the bank. - */ + /* Get the Bank number and Pin number within the bank. */ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, diff --git a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_selftest.c b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_selftest.c index 3389187c..be04706a 100644 --- a/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_selftest.c +++ b/XilinxProcessorIPLib/drivers/gpiops/src/xgpiops_selftest.c @@ -94,9 +94,7 @@ s32 XGpioPs_SelfTest(XGpioPs *InstancePtr) Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - /* - * Disable the Interrupts for Bank 0 . - */ + /* Disable the Interrupts for Bank 0 . */ IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0); XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);