diff --git a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.c b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.c index 98e44be9..7ce77eea 100755 --- a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.c +++ b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.c @@ -3846,6 +3846,10 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. MASK_0_LSW = 0xff7f // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU @@ -3914,6 +3918,10 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. MASK_0_LSW = 0xf7ff // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU @@ -3982,6 +3990,10 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. MASK_0_LSW = 0xdfff // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU @@ -4123,6 +4135,38 @@ unsigned long ps7_post_config_3_0[] = { // }; +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + unsigned long ps7_pll_init_data_2_0[] = { // START: top // .. START: SLCR SETTINGS @@ -8093,6 +8137,10 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. MASK_0_LSW = 0xff7f // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU @@ -8161,6 +8209,10 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. MASK_0_LSW = 0xf7ff // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU @@ -8229,6 +8281,10 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. MASK_0_LSW = 0xdfff // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU @@ -8364,6 +8420,38 @@ unsigned long ps7_post_config_2_0[] = { // }; +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + unsigned long ps7_pll_init_data_1_0[] = { // START: top // .. START: SLCR SETTINGS @@ -12267,6 +12355,10 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. MASK_0_LSW = 0xff7f // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU @@ -12335,6 +12427,10 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. MASK_0_LSW = 0xf7ff // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU @@ -12403,6 +12499,10 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. MASK_0_LSW = 0xdfff // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU @@ -12538,6 +12638,38 @@ unsigned long ps7_post_config_1_0[] = { // }; +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + #include "xil_io.h" #define PS7_MASK_POLL_TIME 100000000 @@ -12576,7 +12708,7 @@ void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { int mask_poll(unsigned long add , unsigned long mask ) { - unsigned long *addr = (unsigned long*) add; + volatile unsigned long *addr = (volatile unsigned long*) add; int i = 0; while (!(*addr & mask)) { if (i == PS7_MASK_POLL_TIME) { @@ -12658,6 +12790,14 @@ ps7_config(unsigned long * ps7_config_init) i++; } break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; default: finish = PS7_INIT_CORRUPT; break; @@ -12691,11 +12831,31 @@ ps7_post_config() return PS7_INIT_SUCCESS; } +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + int ps7_init() { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); + int ret; //int pcw_ver = 0; if (si_ver == PCW_SILICON_VERSION_1) { @@ -12724,7 +12884,7 @@ ps7_init() } // MIO init - int ret = ps7_config (ps7_mio_init_data); + ret = ps7_config (ps7_mio_init_data); if (ret != PS7_INIT_SUCCESS) return ret; // PLL init @@ -12748,3 +12908,48 @@ ps7_init() return PS7_INIT_SUCCESS; } + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.h b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.h index 422c1e92..ca664000 100755 --- a/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.h +++ b/lib/sw_apps/zynq_fsbl/misc/zc702/ps7_init.h @@ -73,6 +73,7 @@ extern unsigned long * ps7_peripherals_init_data; #define OPCODE_WRITE 2U #define OPCODE_MASKWRITE 3U #define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U #define NEW_PS7_ERR_CODE 1 /* Encode number of arguments in last nibble */ @@ -81,8 +82,7 @@ extern unsigned long * ps7_peripherals_init_data; #define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val #define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val #define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask - - +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask /* Returns codes of PS7_Init */ #define PS7_INIT_SUCCESS (0) // 0 is success in good old C @@ -103,22 +103,22 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 666666666 -#define DDR_FREQ 533333333 -#define DCI_FREQ 10159000 +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158731 #define QSPI_FREQ 200000000 -#define SMC_FREQ 100000000 +#define SMC_FREQ 10000000 #define ENET0_FREQ 25000000 -#define ENET1_FREQ 125000000 +#define ENET1_FREQ 10000000 #define USB0_FREQ 60000000 #define USB1_FREQ 60000000 #define SDIO_FREQ 50000000 #define UART_FREQ 50000000 -#define SPI_FREQ 166666666 +#define SPI_FREQ 10000000 #define I2C_FREQ 111111115 -#define WDT_FREQ 133333333 +#define WDT_FREQ 111111115 #define TTC_FREQ 50000000 -#define CAN_FREQ 23809500 +#define CAN_FREQ 23809523 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 #define FPGA0_FREQ 50000000 @@ -127,11 +127,24 @@ extern unsigned long * ps7_peripherals_init_data; #define FPGA3_FREQ 50000000 +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + int ps7_config( unsigned long*); int ps7_init(); int ps7_post_config(); +int ps7_debug(); char* getPS7MessageInfo(unsigned key); +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); #ifdef __cplusplus } #endif + diff --git a/lib/sw_apps/zynq_fsbl/misc/zc702/xparameters.h b/lib/sw_apps/zynq_fsbl/misc/zc702/xparameters.h index 2d674a3b..c89b3452 100755 --- a/lib/sw_apps/zynq_fsbl/misc/zc702/xparameters.h +++ b/lib/sw_apps/zynq_fsbl/misc/zc702/xparameters.h @@ -214,29 +214,6 @@ #define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF -/******************************************************************/ - -/* Definitions for driver GPIO */ -#define XPAR_XGPIO_NUM_INSTANCES 1 - -/* Definitions for peripheral AXI_GPIO_1 */ -#define XPAR_AXI_GPIO_1_BASEADDR 0x41200000 -#define XPAR_AXI_GPIO_1_HIGHADDR 0x4120FFFF -#define XPAR_AXI_GPIO_1_DEVICE_ID 0 -#define XPAR_AXI_GPIO_1_INTERRUPT_PRESENT 0 -#define XPAR_AXI_GPIO_1_IS_DUAL 0 - - -/******************************************************************/ - -/* Canonical definitions for peripheral AXI_GPIO_1 */ -#define XPAR_GPIO_0_BASEADDR 0x41200000 -#define XPAR_GPIO_0_HIGHADDR 0x4120FFFF -#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_1_DEVICE_ID -#define XPAR_GPIO_0_INTERRUPT_PRESENT 0 -#define XPAR_GPIO_0_IS_DUAL 0 - - /******************************************************************/ /* Definitions for driver GPIOPS */ diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.c b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.c index fb682656..0ffb692d 100755 --- a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.c +++ b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.c @@ -990,14 +990,14 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. reg_ddrc_dfi_wr_level_en = 0x1 // .. .. ==> 0XF80060B0[26:26] = 0x00000001U // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x0 - // .. .. ==> 0XF80060B0[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x0 - // .. .. ==> 0XF80060B0[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x04FFFFFFU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), // .. .. reg_ddrc_skip_ocd = 0x1 // .. .. ==> 0XF80060B4[9:9] = 0x00000001U // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U @@ -1164,35 +1164,35 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. reg_phy_wrlvl_init_ratio = 0x1e // .. .. ==> 0XF800612C[9:0] = 0x0000001EU // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001EU - // .. .. reg_phy_gatelvl_init_ratio = 0xf2 - // .. .. ==> 0XF800612C[19:10] = 0x000000F2U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF800612C[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81EU), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU), // .. .. reg_phy_wrlvl_init_ratio = 0x25 // .. .. ==> 0XF8006130[9:0] = 0x00000025U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000025U - // .. .. reg_phy_gatelvl_init_ratio = 0xd8 - // .. .. ==> 0XF8006130[19:10] = 0x000000D8U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. reg_phy_gatelvl_init_ratio = 0x10d + // .. .. ==> 0XF8006130[19:10] = 0x0000010DU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00043400U // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036025U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U), // .. .. reg_phy_wrlvl_init_ratio = 0x19 // .. .. ==> 0XF8006134[9:0] = 0x00000019U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000019U - // .. .. reg_phy_gatelvl_init_ratio = 0xde - // .. .. ==> 0XF8006134[19:10] = 0x000000DEU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. reg_phy_gatelvl_init_ratio = 0xf3 + // .. .. ==> 0XF8006134[19:10] = 0x000000F3U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003CC00U // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00037819U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U), // .. .. reg_phy_wrlvl_init_ratio = 0x2a // .. .. ==> 0XF8006138[9:0] = 0x0000002AU // .. .. ==> MASK : 0x000003FFU VAL : 0x0000002AU - // .. .. reg_phy_gatelvl_init_ratio = 0xee - // .. .. ==> 0XF8006138[19:10] = 0x000000EEU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. reg_phy_gatelvl_init_ratio = 0x109 + // .. .. ==> 0XF8006138[19:10] = 0x00000109U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00042400U // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B82AU), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU), // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 // .. .. ==> 0XF8006140[9:0] = 0x00000035U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U @@ -1419,12 +1419,12 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. reg_phy_use_wr_level = 0x1 // .. .. ==> 0XF8006194[14:14] = 0x00000001U // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x0 - // .. .. ==> 0XF8006194[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_rd_data_eye_level = 0x0 - // .. .. ==> 0XF8006194[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U // .. .. reg_phy_dis_calib_rst = 0x0 // .. .. ==> 0XF8006194[17:17] = 0x00000000U // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U @@ -1432,7 +1432,7 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> 0XF8006194[19:18] = 0x00000000U // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x00007C82U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), // .. .. reg_arb_page_addr_mask = 0x0 // .. .. ==> 0XF8006204[31:0] = 0x00000000U // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U @@ -3815,6 +3815,10 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. MASK_0_LSW = 0xff7f // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU @@ -3883,6 +3887,10 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] @@ -3951,6 +3959,10 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] @@ -4092,6 +4104,38 @@ unsigned long ps7_post_config_3_0[] = { // }; +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + unsigned long ps7_pll_init_data_2_0[] = { // START: top // .. START: SLCR SETTINGS @@ -5107,14 +5151,14 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. reg_ddrc_dfi_wr_level_en = 0x1 // .. .. ==> 0XF80060B0[26:26] = 0x00000001U // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x0 - // .. .. ==> 0XF80060B0[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x0 - // .. .. ==> 0XF80060B0[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x04FFFFFFU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), // .. .. reg_ddrc_2t_delay = 0x0 // .. .. ==> 0XF80060B4[8:0] = 0x00000000U // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U @@ -5338,35 +5382,35 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. reg_phy_wrlvl_init_ratio = 0x1e // .. .. ==> 0XF800612C[9:0] = 0x0000001EU // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001EU - // .. .. reg_phy_gatelvl_init_ratio = 0xf2 - // .. .. ==> 0XF800612C[19:10] = 0x000000F2U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF800612C[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81EU), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU), // .. .. reg_phy_wrlvl_init_ratio = 0x25 // .. .. ==> 0XF8006130[9:0] = 0x00000025U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000025U - // .. .. reg_phy_gatelvl_init_ratio = 0xd8 - // .. .. ==> 0XF8006130[19:10] = 0x000000D8U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. reg_phy_gatelvl_init_ratio = 0x10d + // .. .. ==> 0XF8006130[19:10] = 0x0000010DU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00043400U // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036025U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U), // .. .. reg_phy_wrlvl_init_ratio = 0x19 // .. .. ==> 0XF8006134[9:0] = 0x00000019U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000019U - // .. .. reg_phy_gatelvl_init_ratio = 0xde - // .. .. ==> 0XF8006134[19:10] = 0x000000DEU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. reg_phy_gatelvl_init_ratio = 0xf3 + // .. .. ==> 0XF8006134[19:10] = 0x000000F3U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003CC00U // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00037819U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U), // .. .. reg_phy_wrlvl_init_ratio = 0x2a // .. .. ==> 0XF8006138[9:0] = 0x0000002AU // .. .. ==> MASK : 0x000003FFU VAL : 0x0000002AU - // .. .. reg_phy_gatelvl_init_ratio = 0xee - // .. .. ==> 0XF8006138[19:10] = 0x000000EEU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. reg_phy_gatelvl_init_ratio = 0x109 + // .. .. ==> 0XF8006138[19:10] = 0x00000109U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00042400U // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B82AU), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU), // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 // .. .. ==> 0XF8006140[9:0] = 0x00000035U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U @@ -5605,12 +5649,12 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. reg_phy_use_wr_level = 0x1 // .. .. ==> 0XF8006194[14:14] = 0x00000001U // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x0 - // .. .. ==> 0XF8006194[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_rd_data_eye_level = 0x0 - // .. .. ==> 0XF8006194[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U // .. .. reg_phy_dis_calib_rst = 0x0 // .. .. ==> 0XF8006194[17:17] = 0x00000000U // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U @@ -5618,7 +5662,7 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> 0XF8006194[19:18] = 0x00000000U // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x00007C82U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), // .. .. reg_arb_page_addr_mask = 0x0 // .. .. ==> 0XF8006204[31:0] = 0x00000000U // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U @@ -8031,6 +8075,10 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. MASK_0_LSW = 0xff7f // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU @@ -8099,6 +8147,10 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] @@ -8167,6 +8219,10 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] @@ -8302,6 +8358,38 @@ unsigned long ps7_post_config_2_0[] = { // }; +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + unsigned long ps7_pll_init_data_1_0[] = { // START: top // .. START: SLCR SETTINGS @@ -9280,14 +9368,14 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. reg_ddrc_dfi_wr_level_en = 0x1 // .. .. ==> 0XF80060B0[26:26] = 0x00000001U // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x0 - // .. .. ==> 0XF80060B0[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x0 - // .. .. ==> 0XF80060B0[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x04FFFFFFU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), // .. .. reg_ddrc_2t_delay = 0x0 // .. .. ==> 0XF80060B4[8:0] = 0x00000000U // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U @@ -9484,35 +9572,35 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. reg_phy_wrlvl_init_ratio = 0x1e // .. .. ==> 0XF800612C[9:0] = 0x0000001EU // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001EU - // .. .. reg_phy_gatelvl_init_ratio = 0xf2 - // .. .. ==> 0XF800612C[19:10] = 0x000000F2U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF800612C[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81EU), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU), // .. .. reg_phy_wrlvl_init_ratio = 0x25 // .. .. ==> 0XF8006130[9:0] = 0x00000025U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000025U - // .. .. reg_phy_gatelvl_init_ratio = 0xd8 - // .. .. ==> 0XF8006130[19:10] = 0x000000D8U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. reg_phy_gatelvl_init_ratio = 0x10d + // .. .. ==> 0XF8006130[19:10] = 0x0000010DU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00043400U // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036025U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U), // .. .. reg_phy_wrlvl_init_ratio = 0x19 // .. .. ==> 0XF8006134[9:0] = 0x00000019U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000019U - // .. .. reg_phy_gatelvl_init_ratio = 0xde - // .. .. ==> 0XF8006134[19:10] = 0x000000DEU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. reg_phy_gatelvl_init_ratio = 0xf3 + // .. .. ==> 0XF8006134[19:10] = 0x000000F3U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003CC00U // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00037819U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U), // .. .. reg_phy_wrlvl_init_ratio = 0x2a // .. .. ==> 0XF8006138[9:0] = 0x0000002AU // .. .. ==> MASK : 0x000003FFU VAL : 0x0000002AU - // .. .. reg_phy_gatelvl_init_ratio = 0xee - // .. .. ==> 0XF8006138[19:10] = 0x000000EEU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. reg_phy_gatelvl_init_ratio = 0x109 + // .. .. ==> 0XF8006138[19:10] = 0x00000109U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00042400U // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B82AU), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU), // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 // .. .. ==> 0XF8006140[9:0] = 0x00000035U // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U @@ -9751,12 +9839,12 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. reg_phy_use_wr_level = 0x1 // .. .. ==> 0XF8006194[14:14] = 0x00000001U // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x0 - // .. .. ==> 0XF8006194[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_rd_data_eye_level = 0x0 - // .. .. ==> 0XF8006194[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U // .. .. reg_phy_dis_calib_rst = 0x0 // .. .. ==> 0XF8006194[17:17] = 0x00000000U // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U @@ -9764,7 +9852,7 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> 0XF8006194[19:18] = 0x00000000U // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x00007C82U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), // .. .. reg_arb_page_addr_mask = 0x0 // .. .. ==> 0XF8006204[31:0] = 0x00000000U // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U @@ -12174,6 +12262,10 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. MASK_0_LSW = 0xff7f // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU @@ -12242,6 +12334,10 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] @@ -12310,6 +12406,10 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] @@ -12445,6 +12545,38 @@ unsigned long ps7_post_config_1_0[] = { // }; +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + #include "xil_io.h" #define PS7_MASK_POLL_TIME 100000000 @@ -12483,7 +12615,7 @@ void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { int mask_poll(unsigned long add , unsigned long mask ) { - unsigned long *addr = (unsigned long*) add; + volatile unsigned long *addr = (volatile unsigned long*) add; int i = 0; while (!(*addr & mask)) { if (i == PS7_MASK_POLL_TIME) { @@ -12565,6 +12697,14 @@ ps7_config(unsigned long * ps7_config_init) i++; } break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; default: finish = PS7_INIT_CORRUPT; break; @@ -12598,11 +12738,31 @@ ps7_post_config() return PS7_INIT_SUCCESS; } +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + int ps7_init() { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); + int ret; //int pcw_ver = 0; if (si_ver == PCW_SILICON_VERSION_1) { @@ -12631,7 +12791,7 @@ ps7_init() } // MIO init - int ret = ps7_config (ps7_mio_init_data); + ret = ps7_config (ps7_mio_init_data); if (ret != PS7_INIT_SUCCESS) return ret; // PLL init @@ -12655,3 +12815,48 @@ ps7_init() return PS7_INIT_SUCCESS; } + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h index 544c658c..56d67a06 100755 --- a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h +++ b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h @@ -73,6 +73,7 @@ extern unsigned long * ps7_peripherals_init_data; #define OPCODE_WRITE 2U #define OPCODE_MASKWRITE 3U #define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U #define NEW_PS7_ERR_CODE 1 /* Encode number of arguments in last nibble */ @@ -81,8 +82,7 @@ extern unsigned long * ps7_peripherals_init_data; #define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val #define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val #define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask - - +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask /* Returns codes of PS7_Init */ #define PS7_INIT_SUCCESS (0) // 0 is success in good old C @@ -103,22 +103,22 @@ extern unsigned long * ps7_peripherals_init_data; /* Freq of all peripherals */ -#define APU_FREQ 667000000 -#define DDR_FREQ 533333313 -#define DCI_FREQ 10159000 +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158731 #define QSPI_FREQ 200000000 -#define SMC_FREQ 100000000 +#define SMC_FREQ 10000000 #define ENET0_FREQ 25000000 -#define ENET1_FREQ 125000000 +#define ENET1_FREQ 10000000 #define USB0_FREQ 60000000 #define USB1_FREQ 60000000 #define SDIO_FREQ 50000000 #define UART_FREQ 50000000 -#define SPI_FREQ 166666666 +#define SPI_FREQ 10000000 #define I2C_FREQ 111111115 -#define WDT_FREQ 133333333 +#define WDT_FREQ 111111115 #define TTC_FREQ 50000000 -#define CAN_FREQ 100000000 +#define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 #define FPGA0_FREQ 50000000 @@ -127,11 +127,24 @@ extern unsigned long * ps7_peripherals_init_data; #define FPGA3_FREQ 50000000 +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + int ps7_config( unsigned long*); int ps7_init(); int ps7_post_config(); +int ps7_debug(); char* getPS7MessageInfo(unsigned key); +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); #ifdef __cplusplus } #endif + diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/xparameters.h b/lib/sw_apps/zynq_fsbl/misc/zc706/xparameters.h index 5ae1fbdd..7eae9450 100755 --- a/lib/sw_apps/zynq_fsbl/misc/zc706/xparameters.h +++ b/lib/sw_apps/zynq_fsbl/misc/zc706/xparameters.h @@ -193,29 +193,6 @@ #define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF -/******************************************************************/ - -/* Definitions for driver GPIO */ -#define XPAR_XGPIO_NUM_INSTANCES 1 - -/* Definitions for peripheral AXI_GPIO_1 */ -#define XPAR_AXI_GPIO_1_BASEADDR 0x41200000 -#define XPAR_AXI_GPIO_1_HIGHADDR 0x4120FFFF -#define XPAR_AXI_GPIO_1_DEVICE_ID 0 -#define XPAR_AXI_GPIO_1_INTERRUPT_PRESENT 0 -#define XPAR_AXI_GPIO_1_IS_DUAL 0 - - -/******************************************************************/ - -/* Canonical definitions for peripheral AXI_GPIO_1 */ -#define XPAR_GPIO_0_BASEADDR 0x41200000 -#define XPAR_GPIO_0_HIGHADDR 0x4120FFFF -#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_1_DEVICE_ID -#define XPAR_GPIO_0_INTERRUPT_PRESENT 0 -#define XPAR_GPIO_0_IS_DUAL 0 - - /******************************************************************/ /* Definitions for driver GPIOPS */