diff --git a/XilinxProcessorIPLib/drivers/trafgen/data/trafgen.mdd b/XilinxProcessorIPLib/drivers/trafgen/data/trafgen.mdd
index 29b8bb08..6907bab8 100755
--- a/XilinxProcessorIPLib/drivers/trafgen/data/trafgen.mdd
+++ b/XilinxProcessorIPLib/drivers/trafgen/data/trafgen.mdd
@@ -37,7 +37,7 @@ BEGIN driver trafgen
   OPTION supported_peripherals = (axi_traffic_gen_v[2-9]_[0-9][0-9]_[a-z] axi_traffic_gen_v[2-9]_[0-9]);
   OPTION driver_state = ACTIVE;
   OPTION copyfiles = all;
-    OPTION VERSION = 3.0;
+    OPTION VERSION = 3.2;
   OPTION NAME = trafgen;   
 
 END driver
diff --git a/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.c b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.c
index 2ed810df..870cbf98 100755
--- a/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.c
+++ b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.c
@@ -393,7 +393,7 @@ void XTrafGen_AccessMasterRam(XTrafGen *InstancePtr, u32 Offset,
 		
 	/* Verify arguments */
         Xil_AssertVoid(InstancePtr != NULL);
-	Xil_AssertVoid((Offset + Length) < XTG_MASTER_RAM_SIZE);
+	Xil_AssertVoid((Offset + Length) <= XTG_MASTER_RAM_SIZE);
 
 	while (Length > 0) {
 		if (RdWrFlag == XTG_WRITE) {
diff --git a/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.h b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.h
index c24e55d2..09b96d12 100755
--- a/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.h
+++ b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen.h
@@ -176,7 +176,7 @@
 * 1.00a srt  01/24/13 First release
 * 1.01a adk  03/09/13 Updated Driver to Support Streaming and Static Mode
 * 2.00a adk  16/09/13 Fixed CR:737291
-* 2.01a adk  21/10/13 Fixed CR:740522 Updated the MasterRam offset as per latest 
+* 2.01a adk  21/10/13 Fixed CR:740522 Updated the MasterRam offset as per latest
 *		      IP.This driver is valid only for IP(v2.0) onwards. The 
 *		      XTG_MASTER_RAM_OFFSET has been changed from 
 *		      0x10000 to 0xc000.
@@ -185,6 +185,9 @@
 * 3.0   adk  12/10/13 Updated as per the New Tcl API's
 * 3.1   adk  28/04/14 Fixed CR:782131 Incorrect mask value for the
 *		      loopenable bit.
+* 3.2   adk  05/08/14 Fixed CR:798742 The last word of 8KB Master RAM in
+*		      axi traffic generator can't access and CR:799554
+* 		      Some incorrect parameter in axi traffic generator driver.
 * </pre>
 ******************************************************************************/
 
diff --git a/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_hw.h b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_hw.h
index b89be6df..7f901e9e 100755
--- a/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_hw.h
+++ b/XilinxProcessorIPLib/drivers/trafgen/src/xtrafgen_hw.h
@@ -210,7 +210,7 @@ extern "C" {
  * @{
  */
 #define XTG_STREAM_CNTL_VER_SHIFT		24		/**< Version Shift */
-#define XTG_STREAM_CNTL_VER_MASK		0xFE000000	/**< Version Mask */
+#define XTG_STREAM_CNTL_VER_MASK		0xFF000000	/**< Version Mask */
 
 #define XTG_STREAM_CNTL_TD_SHIFT		1		/**< Transfer Done Shift */
 #define XTG_STREAM_CNTL_TD_MASK			0x00000002	/**< Transfer Done Mask */
@@ -254,7 +254,7 @@ extern "C" {
  * @{
  */
 #define XTG_STATIC_CNTL_VER_SHIFT		24		/**< Version Shift */
-#define XTG_STATIC_CNTL_VER_MASK		0xFE000000	/**< Version Mask */
+#define XTG_STATIC_CNTL_VER_MASK		0xFF000000	/**< Version Mask */
 
 #define XTG_STATIC_CNTL_TD_SHIFT		1		/**< Transfer Done Shift */
 #define XTG_STATIC_CNTL_TD_MASK			0x00000002	/**< Transfer Done Mask */
@@ -279,7 +279,7 @@ extern "C" {
 #define XTG_LOCK_MASK		0x1		/**< Driven to a*_lock line */
 #define XTG_BURST_MASK		0x3		/**< Driven to a*_burst line */
 #define XTG_SIZE_MASK		0x7		/**< Driven to a*_size line */
-#define XTG_ID_MASK		0x1F		/**< Driven to a*_id line */
+#define XTG_ID_MASK		0x2F		/**< Driven to a*_id line */
 #define XTG_PROT_MASK		0x7		/**< Driven to a*_prot line */
 #define XTG_LAST_ADDR_MASK	0x7		/**< Last address */
 #define XTG_VALID_CMD_MASK	0x1		/**< Valid Command */	
@@ -304,7 +304,7 @@ extern "C" {
 #define XTG_OTHER_DEPEND_SHIFT	13		/**< Other depend cmd num */
 #define XTG_MY_DEPEND_SHIFT	22		/**< My depend cmd num */
 #define XTG_QOS_SHIFT		16		/**< Driven to a*_qos line */
-#define XTG_USER_SHIFT		5		/**< Driven to a*_user line */
+#define XTG_USER_SHIFT		8		/**< Driven to a*_user line */
 #define XTG_CACHE_SHIFT		4		/**< Driven to a*_cache line */
 #define XTG_EXPECTED_RESP_SHIFT	0		/**< Expected response */