From 3b3bd69fa53b4865281182aa4aada6cce8609e88 Mon Sep 17 00:00:00 2001 From: Venkata Naga Sai Krishna Kolapalli Date: Wed, 10 Dec 2014 16:30:38 +0530 Subject: [PATCH] wdtps : Modified wdtps driver for MISRA-C:2012. This patch modifies wdtps for misrac rules. Signed-off-by: Venkata Naga Sai Krishna Kolapalli --- .../drivers/wdtps/src/xwdtps.c | 82 +++++++++++-------- .../drivers/wdtps/src/xwdtps.h | 12 +-- .../drivers/wdtps/src/xwdtps_g.c | 10 ++- .../drivers/wdtps/src/xwdtps_hw.h | 52 ++++++------ .../drivers/wdtps/src/xwdtps_selftest.c | 64 ++++++++------- .../drivers/wdtps/src/xwdtps_sinit.c | 12 +-- 6 files changed, 128 insertions(+), 104 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps.c b/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps.c index 8c4ef71b..4d0d81a6 100755 --- a/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps.c +++ b/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps.c @@ -89,9 +89,10 @@ * @note None. * ******************************************************************************/ -int XWdtPs_CfgInitialize(XWdtPs *InstancePtr, +s32 XWdtPs_CfgInitialize(XWdtPs *InstancePtr, XWdtPs_Config *ConfigPtr, u32 EffectiveAddress) { + s32 Status; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(ConfigPtr != NULL); @@ -102,27 +103,29 @@ int XWdtPs_CfgInitialize(XWdtPs *InstancePtr, * initializing. */ if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { - return XST_DEVICE_IS_STARTED; + Status = XST_DEVICE_IS_STARTED; + } else { + + /* + * Copy configuration into instance. + */ + InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; + + /* + * Save the base address pointer such that the registers of the block + * can be accessed and indicate it has not been started yet. + */ + InstancePtr->Config.BaseAddress = EffectiveAddress; + InstancePtr->IsStarted = 0U; + + /* + * Indicate the instance is ready to use, successfully initialized. + */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + Status = XST_SUCCESS; } - - /* - * Copy configuration into instance. - */ - InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; - - /* - * Save the base address pointer such that the registers of the block - * can be accessed and indicate it has not been started yet. - */ - InstancePtr->Config.BaseAddress = EffectiveAddress; - InstancePtr->IsStarted = 0; - - /* - * Indicate the instance is ready to use, successfully initialized. - */ - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - - return XST_SUCCESS; + return Status; } /****************************************************************************/ @@ -203,7 +206,7 @@ void XWdtPs_Stop(XWdtPs *InstancePtr) * Disable the Timer field in the register and * Set the access key for the write to be done the register. */ - Register &= ~XWDTPS_ZMR_WDEN_MASK; + Register &= (u32)(~XWDTPS_ZMR_WDEN_MASK); Register |= XWDTPS_ZMR_ZKEY_VAL; /* @@ -212,7 +215,7 @@ void XWdtPs_Stop(XWdtPs *InstancePtr) XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET, Register); - InstancePtr->IsStarted = 0; + InstancePtr->IsStarted = 0U; } @@ -235,7 +238,7 @@ void XWdtPs_Stop(XWdtPs *InstancePtr) ******************************************************************************/ void XWdtPs_EnableOutput(XWdtPs *InstancePtr, u8 Signal) { - u32 Register = 0; + u32 Register; Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -260,6 +263,9 @@ void XWdtPs_EnableOutput(XWdtPs *InstancePtr, u8 Signal) */ Register |= XWDTPS_ZMR_IRQEN_MASK; + } else { + /* Else was made for misra-c compliance */ + ; } /* @@ -293,7 +299,7 @@ void XWdtPs_EnableOutput(XWdtPs *InstancePtr, u8 Signal) ******************************************************************************/ void XWdtPs_DisableOutput(XWdtPs *InstancePtr, u8 Signal) { - u32 Register = 0; + u32 Register; Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -310,14 +316,17 @@ void XWdtPs_DisableOutput(XWdtPs *InstancePtr, u8 Signal) /* * Disable the field in the register. */ - Register &= ~XWDTPS_ZMR_RSTEN_MASK; + Register &= (u32)(~XWDTPS_ZMR_RSTEN_MASK); } else if (Signal == XWDTPS_IRQ_SIGNAL) { /* * Disable the field in the register. */ - Register &= ~XWDTPS_ZMR_IRQEN_MASK; + Register &= (u32)(~XWDTPS_ZMR_IRQEN_MASK); + } else { + /* Else was made for misra-c compliance */ + ; } /* @@ -358,7 +367,7 @@ void XWdtPs_DisableOutput(XWdtPs *InstancePtr, u8 Signal) u32 XWdtPs_GetControlValue(XWdtPs *InstancePtr, u8 Control) { u32 Register; - u32 ReturnValue = 0; + u32 ReturnValue = 0U; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -387,6 +396,9 @@ u32 XWdtPs_GetControlValue(XWdtPs *InstancePtr, u8 Control) * Shift over to the right most positions. */ ReturnValue = Register >> XWDTPS_CCR_CRV_SHIFT; + } else { + /* Else was made for misra-c compliance */ + ; } return ReturnValue; @@ -420,7 +432,8 @@ u32 XWdtPs_GetControlValue(XWdtPs *InstancePtr, u8 Control) ******************************************************************************/ void XWdtPs_SetControlValue(XWdtPs *InstancePtr, u8 Control, u32 Value) { - u32 Register = 0; + u32 Register; + u32 LocalValue = Value; Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -437,21 +450,24 @@ void XWdtPs_SetControlValue(XWdtPs *InstancePtr, u8 Control, u32 Value) /* * Zero the field in the register. */ - Register &= ~XWDTPS_CCR_CLKSEL_MASK; + Register &= (u32)(~XWDTPS_CCR_CLKSEL_MASK); } else if (Control == XWDTPS_COUNTER_RESET) { /* * Zero the field in the register. */ - Register &= ~XWDTPS_CCR_CRV_MASK; + Register &= (u32)(~XWDTPS_CCR_CRV_MASK); /* * Shift Value over to the proper positions. */ - Value = Value << XWDTPS_CCR_CRV_SHIFT; + LocalValue = LocalValue << XWDTPS_CCR_CRV_SHIFT; + } else{ + /* This was made for misrac compliance. */ + ; } - Register |= Value; + Register |= LocalValue; /* * Set the access key so the write takes. diff --git a/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps.h b/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps.h index 17ded27b..8073b9b8 100755 --- a/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps.h +++ b/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps.h @@ -105,15 +105,15 @@ extern "C" { * Choices for output selections for the device, used in * XWdtPs_EnableOutput()/XWdtPs_DisableOutput() functions */ -#define XWDTPS_RESET_SIGNAL 1 /**< Reset signal request */ -#define XWDTPS_IRQ_SIGNAL 2 /**< IRQ signal request */ +#define XWDTPS_RESET_SIGNAL 0x01U /**< Reset signal request */ +#define XWDTPS_IRQ_SIGNAL 0x02U /**< IRQ signal request */ /* * Control value setting flags, used in * XWdtPs_SetControlValues()/XWdtPs_GetControlValues() functions */ -#define XWDTPS_CLK_PRESCALE 1 /**< Clock Prescale request */ -#define XWDTPS_COUNTER_RESET 2 /**< Counter Reset request */ +#define XWDTPS_CLK_PRESCALE 0x01U /**< Clock Prescale request */ +#define XWDTPS_COUNTER_RESET 0x02U /**< Counter Reset request */ /**************************** Type Definitions *******************************/ @@ -189,7 +189,7 @@ XWdtPs_Config *XWdtPs_LookupConfig(u16 DeviceId); /* * Interface functions in xwdtps.c */ -int XWdtPs_CfgInitialize(XWdtPs *InstancePtr, +s32 XWdtPs_CfgInitialize(XWdtPs *InstancePtr, XWdtPs_Config *ConfigPtr, u32 EffectiveAddress); void XWdtPs_Start(XWdtPs *InstancePtr); @@ -207,7 +207,7 @@ void XWdtPs_SetControlValue(XWdtPs *InstancePtr, u8 Control, u32 Value); /* * Self-test function in xwdttb_selftest.c. */ -int XWdtPs_SelfTest(XWdtPs *InstancePtr); +s32 XWdtPs_SelfTest(XWdtPs *InstancePtr); #ifdef __cplusplus diff --git a/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_g.c b/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_g.c index f2ab3579..92b14677 100755 --- a/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_g.c +++ b/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_g.c @@ -49,8 +49,8 @@ /***************************** Include Files *********************************/ -#include "xparameters.h" #include "xwdtps.h" +#include "xparameters.h" /************************** Constant Definitions *****************************/ @@ -72,7 +72,11 @@ */ XWdtPs_Config XWdtPs_ConfigTable[XPAR_XWDTPS_NUM_INSTANCES] = { { - XPAR_XWDTPS_0_DEVICE_ID, - XPAR_XWDTPS_0_BASEADDR + (u16)XPAR_XWDTPS_0_DEVICE_ID, + (u32)XPAR_XWDTPS_0_BASEADDR + }, + { + (u16)XPAR_XWDTPS_1_DEVICE_ID, + (u32)XPAR_XWDTPS_1_BASEADDR } }; diff --git a/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_hw.h b/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_hw.h index 2c18a7de..cbb41d59 100755 --- a/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_hw.h +++ b/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_hw.h @@ -67,10 +67,10 @@ extern "C" { * @{ */ -#define XWDTPS_ZMR_OFFSET 0x0 /**< Zero Mode Register */ -#define XWDTPS_CCR_OFFSET 0x4 /**< Counter Control Register */ -#define XWDTPS_RESTART_OFFSET 0x8 /**< Restart Register */ -#define XWDTPS_SR_OFFSET 0xC /**< Status Register */ +#define XWDTPS_ZMR_OFFSET 0x00000000U /**< Zero Mode Register */ +#define XWDTPS_CCR_OFFSET 0x00000004U /**< Counter Control Register */ +#define XWDTPS_RESTART_OFFSET 0x00000008U /**< Restart Register */ +#define XWDTPS_SR_OFFSET 0x0000000CU /**< Status Register */ /* @} */ @@ -79,18 +79,18 @@ extern "C" { * the access code (0xABC) to allow writes to the register * @{ */ -#define XWDTPS_ZMR_WDEN_MASK 0x00000001 /**< enable the WDT */ -#define XWDTPS_ZMR_RSTEN_MASK 0x00000002 /**< enable the reset output */ -#define XWDTPS_ZMR_IRQEN_MASK 0x00000004 /**< enable the IRQ output */ +#define XWDTPS_ZMR_WDEN_MASK 0x00000001U /**< enable the WDT */ +#define XWDTPS_ZMR_RSTEN_MASK 0x00000002U /**< enable the reset output */ +#define XWDTPS_ZMR_IRQEN_MASK 0x00000004U /**< enable the IRQ output */ -#define XWDTPS_ZMR_RSTLN_MASK 0x00000070 /**< set length of reset pulse */ -#define XWDTPS_ZMR_RSTLN_SHIFT 4 /**< shift for reset pulse */ +#define XWDTPS_ZMR_RSTLN_MASK 0x00000070U /**< set length of reset pulse */ +#define XWDTPS_ZMR_RSTLN_SHIFT 4U /**< shift for reset pulse */ -#define XWDTPS_ZMR_IRQLN_MASK 0x00000180 /**< set length of interrupt pulse */ -#define XWDTPS_ZMR_IRQLN_SHIFT 7 /**< shift for interrupt pulse */ +#define XWDTPS_ZMR_IRQLN_MASK 0x00000180U /**< set length of interrupt pulse */ +#define XWDTPS_ZMR_IRQLN_SHIFT 7U /**< shift for interrupt pulse */ -#define XWDTPS_ZMR_ZKEY_MASK 0x00FFF000 /**< mask for writing access key */ -#define XWDTPS_ZMR_ZKEY_VAL 0x00ABC000 /**< access key, 0xABC << 12 */ +#define XWDTPS_ZMR_ZKEY_MASK 0x00FFF000U /**< mask for writing access key */ +#define XWDTPS_ZMR_ZKEY_VAL 0x00ABC000U /**< access key, 0xABC << 12 */ /* @} */ @@ -101,20 +101,20 @@ extern "C" { * @{ */ -#define XWDTPS_CCR_CLKSEL_MASK 0x00000003 /**< counter clock prescale */ +#define XWDTPS_CCR_CLKSEL_MASK 0x00000003U /**< counter clock prescale */ -#define XWDTPS_CCR_CRV_MASK 0x00003FFC /**< counter reset value */ -#define XWDTPS_CCR_CRV_SHIFT 2 /**< shift for writing value */ +#define XWDTPS_CCR_CRV_MASK 0x00003FFCU /**< counter reset value */ +#define XWDTPS_CCR_CRV_SHIFT 2U /**< shift for writing value */ -#define XWDTPS_CCR_CKEY_MASK 0x03FFC000 /**< mask for writing access key */ -#define XWDTPS_CCR_CKEY_VAL 0x00920000 /**< access key, 0x248 << 14 */ +#define XWDTPS_CCR_CKEY_MASK 0x03FFC000U /**< mask for writing access key */ +#define XWDTPS_CCR_CKEY_VAL 0x00920000U /**< access key, 0x248 << 14 */ /* Bit patterns for Clock prescale divider values */ -#define XWDTPS_CCR_PSCALE_0008 0x00000000 /**< divide clock by 8 */ -#define XWDTPS_CCR_PSCALE_0064 0x00000001 /**< divide clock by 64 */ -#define XWDTPS_CCR_PSCALE_0512 0x00000002 /**< divide clock by 512 */ -#define XWDTPS_CCR_PSCALE_4096 0x00000003 /**< divide clock by 4096 */ +#define XWDTPS_CCR_PSCALE_0008 0x00000000U /**< divide clock by 8 */ +#define XWDTPS_CCR_PSCALE_0064 0x00000001U /**< divide clock by 64 */ +#define XWDTPS_CCR_PSCALE_0512 0x00000002U /**< divide clock by 512 */ +#define XWDTPS_CCR_PSCALE_4096 0x00000003U /**< divide clock by 4096 */ /* @} */ @@ -124,7 +124,7 @@ extern "C" { * @{ */ -#define XWDTPS_RESTART_KEY_VAL 0x00001999 /**< valid key */ +#define XWDTPS_RESTART_KEY_VAL 0x00001999U /**< valid key */ /*@}*/ @@ -132,7 +132,7 @@ extern "C" { * This register indicates timer reached zero count. * @{ */ -#define XWDTPS_SR_WDZ_MASK 0x00000001 /**< time out occurred */ +#define XWDTPS_SR_WDZ_MASK 0x00000001U /**< time out occurred */ /*@}*/ @@ -156,7 +156,7 @@ extern "C" { * *****************************************************************************/ #define XWdtPs_ReadReg(BaseAddress, RegOffset) \ - Xil_In32((BaseAddress) + (RegOffset)) + Xil_In32((BaseAddress) + (u32)(RegOffset)) /****************************************************************************/ /** @@ -174,7 +174,7 @@ extern "C" { * *****************************************************************************/ #define XWdtPs_WriteReg(BaseAddress, RegOffset, Data) \ - Xil_Out32((BaseAddress) + (RegOffset), (Data)) + Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)) /************************** Function Prototypes ******************************/ diff --git a/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_selftest.c b/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_selftest.c index da90bb52..d641b720 100755 --- a/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_selftest.c +++ b/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_selftest.c @@ -86,11 +86,12 @@ * @note None. * ******************************************************************************/ -int XWdtPs_SelfTest(XWdtPs *InstancePtr) +s32 XWdtPs_SelfTest(XWdtPs *InstancePtr) { u32 ZmrOrig; u32 ZmrValue1; u32 ZmrValue2; + s32 Status; /* * Assert to ensure the inputs are valid and the instance has been @@ -109,7 +110,7 @@ int XWdtPs_SelfTest(XWdtPs *InstancePtr) * EX-OR in the length of the interrupt pulse, * do not set the key value. */ - ZmrValue1 = ZmrOrig ^ XWDTPS_ZMR_RSTLN_MASK; + ZmrValue1 = ZmrOrig ^ (u32)XWDTPS_ZMR_RSTLN_MASK; /* @@ -128,39 +129,42 @@ int XWdtPs_SelfTest(XWdtPs *InstancePtr) */ XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET, - (ZmrOrig | XWDTPS_ZMR_ZKEY_VAL)); - return XST_FAILURE; - } + (ZmrOrig | (u32)XWDTPS_ZMR_ZKEY_VAL)); + Status = XST_FAILURE; + } else { - /* - * Try to write to register with key value then read back. - */ - XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET, - (ZmrValue1 | XWDTPS_ZMR_ZKEY_VAL)); - - ZmrValue2 = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress, - XWDTPS_ZMR_OFFSET); - - if (ZmrValue1 != ZmrValue2) { /* - * If the values do not match, the hw failed the test, - * return orig register value. + * Try to write to register with key value then read back. */ - XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, - XWDTPS_ZMR_OFFSET, - ZmrOrig | XWDTPS_ZMR_ZKEY_VAL); - return XST_FAILURE; + XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET, + (ZmrValue1 | XWDTPS_ZMR_ZKEY_VAL)); + ZmrValue2 = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress, + XWDTPS_ZMR_OFFSET); + + if (ZmrValue1 != ZmrValue2) { + /* + * If the values do not match, the hw failed the test, + * return orig register value. + */ + XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, + XWDTPS_ZMR_OFFSET, + ZmrOrig | XWDTPS_ZMR_ZKEY_VAL); + Status = XST_FAILURE; + + } else { + + /* + * The hardware locking feature is functional, return the original value + * and return success. + */ + XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET, + ZmrOrig | XWDTPS_ZMR_ZKEY_VAL); + + Status = XST_SUCCESS; + } } - - /* - * The hardware locking feature is functional, return the original value - * and return success. - */ - XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET, - ZmrOrig | XWDTPS_ZMR_ZKEY_VAL); - - return XST_SUCCESS; + return Status; } diff --git a/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_sinit.c b/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_sinit.c index f92bb662..33885578 100755 --- a/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_sinit.c +++ b/XilinxProcessorIPLib/drivers/wdtps/src/xwdtps_sinit.c @@ -49,8 +49,8 @@ /***************************** Include Files *********************************/ -#include "xparameters.h" #include "xwdtps.h" +#include "xparameters.h" /************************** Constant Definitions *****************************/ @@ -59,6 +59,8 @@ /***************** Macros (Inline Functions) Definitions *********************/ +/*************************** Variable Definitions ****************************/ +extern XWdtPs_Config XWdtPs_ConfigTable[XPAR_XWDTPS_NUM_INSTANCES]; /************************** Function Prototypes ******************************/ @@ -77,16 +79,14 @@ ******************************************************************************/ XWdtPs_Config *XWdtPs_LookupConfig(u16 DeviceId) { - extern XWdtPs_Config XWdtPs_ConfigTable[]; XWdtPs_Config *CfgPtr = NULL; - int Index; + u32 Index; - for (Index = 0; Index < XPAR_XWDTPS_NUM_INSTANCES; Index++) { + for (Index = 0U; Index < (u32)XPAR_XWDTPS_NUM_INSTANCES; Index++) { if (XWdtPs_ConfigTable[Index].DeviceId == DeviceId) { CfgPtr = &XWdtPs_ConfigTable[Index]; break; } } - - return (CfgPtr); + return (XWdtPs_Config *)CfgPtr; }