diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html index 58437d3f..dc390cdb 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html @@ -95,8 +95,7 @@ Here is a list of all class members with links to the classes they belong to: : XDptx_SbMsgLinkAddressReplyDeviceInfo, XDptx_SbMsgLinkAddressReplyPortDetail, XDptx_TopologyNode

- h -

- q -

- v -

+: XDptx_MainStreamAttributes

- y -

- h -

- q -

- v -

+: XDptx_MainStreamAttributes

- y -

-

+

dptx v3_0

-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the Xilinx DisplayPort soft IP core in source (TX) mode. This driver follows the DisplayPort 1.2a specification.

+The Xilinx DisplayPort soft IP supports the following features:

+

+The Xilinx DisplayPort soft IP does not support the following features:

+

+DisplayPort overview

+A DisplayPort link consists of:

+

+Driver description

+The device driver enables higher-level software (e.g., an application) to configure and control a DisplayPort TX soft IP, communicate and control an RX device/sink monitor over the AUX channel, and to initialize and transmit data streams over the main link.

+This driver implements link layer functionality: a Link Policy Maker (LPM) and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification.

+

+Using AUX transactions to read/write from/to the sink's DisplayPort Configuration Data (DPCD) address space, the LPM obtains the link capabilities, obtains link configuration and link and sink status, and configures and controls the link and sink. The main link is trained this way.

+I2C-over-AUX transactions are used to obtain the sink's Extended Display Identification Data (EDID) which give information on the display capabilities of the monitor. The SPM may use this information to determine what available screen resolutions and video timing are possible.

+Device configuration

+The device can be configured in various ways during the FPGA implementation process. Configuration parameters are stored in the xdptx_g.c file which is generated when compiling the board support package (BSP). A table is defined where each entry contains configuration information for the DisplayPort instances present in the system. This information includes parameters that are defined in the driver's data/dptx.tcl file such as the base address of the memory-mapped device and the maximum number of lanes, maximum link rate, and video interface that the DisplayPort instance supports, among others.

+Interrupt processing

+DisplayPort interrupts occur on the HPD signal line when the DisplayPort cable is connected/disconnected or when the RX device sends a pulse. The user hardware design must contain an interrupt controller which the DisplayPort TX instance's interrupt signal is connected to. The user application must enable interrupts in the system and set up the interrupt controller such that the XDptx_HpdInterruptHandler handler will service DisplayPort interrupts. When the XDptx_HpdInterruptHandler function is invoked, the handler will identify what type of DisplayPort interrupt has occurred, and will call either the HPD event handler function or the HPD pulse handler function, depending on whether a an HPD event on an HPD pulse event occurred.

+The DisplayPort TX's XDPTX_INTERRUPT_STATUS register indicates the type of interrupt that has occured, and the XDptx_HpdInterruptHandler will use this information to decide which handler to call. An HPD event is identified if bit XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is identified from the XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit.

+The HPD event handler may be set up by using the XDptx_SetHpdEventHandler function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler function.

+Multi-stream transport (MST) mode

+The driver handles MST mode functionality, including sideband messaging, topology discovery, virtual channel payload ID table management, and directing streams to different sinks.

+MST testing has been done at all possible link rate/lane count/topology/ resolution/color depth combinations with each setting using following values:

+

+Audio

+The driver does not handle audio. For an example as to how to configure and transmit audio, examples/xdptx_audio_example.c illustrates the required sequence. The user will need to configure the audio source connected to the Displayport TX instance and set up the audio info frame as per user requirements.

+Asserts

+Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.

+Limitations

+

+

+

Note:
For a 5.4Gbps link rate, a high performance 7 series FPGA is required with a speed grade of -2 or -3.
+
+ MODIFICATION HISTORY:

+

 Ver   Who  Date     Changes
+ ----- ---- -------- -----------------------------------------------
+ 1.0   als  05/17/14 Initial release.
+       als  08/03/14 Initial MST addition.
+ 2.0   als  09/21/14 Added XDptx_DiscoverTopology function and changed
+                     XDptx_IsConnected from macro to function.
+ 3.0   als  12/16/14 Updated to use common video library.
+                     Added topology reordering functions:
+                         XDptx_TopologySwapSinks,
+                         XDptx_TopologySortSinksByTiling
+                     Added wrapper functions for remote DPCD/I2C read/writes:
+                         XDptx_RemoteDpcdRead, XDptx_RemoteDpcdWrite,
+                         XDptx_RemoteIicRead, XDptx_RemoteIicWrite
+                     Added EDID utility functions:
+                         XDptx_GetRemoteEdid, XDptx_GetEdidBlock,
+                         XDptx_GetRemoteEdidBlock,
+                         XDptx_GetRemoteEdidDispIdExt,
+                         XDptx_GetDispIdDataBlock,
+                         XDptx_GetRemoteTiledDisplayDb
+                     Remove unused arguments from functions:
+                         LinkCountTotal, RelativeAddress from
+                             XDptx_AllocatePayloadVcIdTable
+                         RegStartAddress from XDptx_IicWrite
+
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes-members.html index 4ecff287..abcb414d 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes-members.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes-members.html @@ -27,18 +27,17 @@ ComponentFormatXDptx_MainStreamAttributes DataPerLaneXDptx_MainStreamAttributes DynamicRangeXDptx_MainStreamAttributes - HClkTotalXDptx_MainStreamAttributes HStartXDptx_MainStreamAttributes InitWaitXDptx_MainStreamAttributes Misc0XDptx_MainStreamAttributes Misc1XDptx_MainStreamAttributes NVidXDptx_MainStreamAttributes OverrideUserPixelWidthXDptx_MainStreamAttributes + PixelClockHzXDptx_MainStreamAttributes SynchronousClockModeXDptx_MainStreamAttributes TransferUnitSizeXDptx_MainStreamAttributes UserPixelWidthXDptx_MainStreamAttributes - VClkTotalXDptx_MainStreamAttributes VStartXDptx_MainStreamAttributes - VtmXDptx_MainStreamAttributes + VtmXDptx_MainStreamAttributes YCbCrColorimetryXDptx_MainStreamAttributes Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes.html index e54f0cc4..02fe078e 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___main_stream_attributes.html @@ -29,11 +29,9 @@ This typedef contains the main stream attributes which determine how the video w - + - - - + @@ -144,21 +142,6 @@ Used to translate the number of pixels per line to the native internal 16-bit da The dynamic range currently in use by the video stream.

- -

-
-

Public Attributes

XVid_VideoTimingMode Vtm
XVidC_VideoTimingMode Vtm
u32 HClkTotal
u32 VClkTotal
u32 PixelClockHz
u32 HStart
- - - -
u32 XDptx_MainStreamAttributes::HClkTotal
- -
- -

-Horizontal total time (in pixels). -

-

@@ -249,6 +232,21 @@ N value for the video stream. If set to 1, the value stored for UserPixelWidth will be used as the pixel width.

+ +

+
+ + + + +
u32 XDptx_MainStreamAttributes::PixelClockHz
+
+
+ +

+The pixel clock of the stream (in Hz). +

+

@@ -294,21 +292,6 @@ Size of the transfer unit in the framing logic. In MST mode, this is also the nu The width of the user data input port.

- -

-
- - - - -
u32 XDptx_MainStreamAttributes::VClkTotal
-
-
- -

-Vertical total time (in pixels). -

-

@@ -324,12 +307,12 @@ Vertical total time (in pixels). Vertical blank start (in lines).

- +

- +
XVid_VideoTimingMode XDptx_MainStreamAttributes::Vtm XVidC_VideoTimingMode XDptx_MainStreamAttributes::Vtm
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8h.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8h.html index aac7b4ab..3de66dca 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8h.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx_8h.html @@ -21,78 +21,12 @@
  • File List
  • File Members
    • -

    xdptx.h File Reference

    Detailed Description

    -The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the Xilinx DisplayPort soft IP core in source (TX) mode. This driver follows the DisplayPort 1.2a specification.

    -The Xilinx DisplayPort soft IP supports the following features:

    -

    -The Xilinx DisplayPort soft IP does not support the following features:

    -

    -DisplayPort overview

    -A DisplayPort link consists of:

    -

    -Driver description

    -The device driver enables higher-level software (e.g., an application) to configure and control a DisplayPort TX soft IP, communicate and control an RX device/sink monitor over the AUX channel, and to initialize and transmit data streams over the main link.

    -This driver implements link layer functionality: a Link Policy Maker (LPM) and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification.

    -

    -Using AUX transactions to read/write from/to the sink's DisplayPort Configuration Data (DPCD) address space, the LPM obtains the link capabilities, obtains link configuration and link and sink status, and configures and controls the link and sink. The main link is trained this way.

    -I2C-over-AUX transactions are used to obtain the sink's Extended Display Identification Data (EDID) which give information on the display capabilities of the monitor. The SPM may use this information to determine what available screen resolutions and video timing are possible.

    -Device configuration

    -The device can be configured in various ways during the FPGA implementation process. Configuration parameters are stored in the xdptx_g.c file which is generated when compiling the board support package (BSP). A table is defined where each entry contains configuration information for the DisplayPort instances present in the system. This information includes parameters that are defined in the driver's data/dptx.tcl file such as the base address of the memory-mapped device and the maximum number of lanes, maximum link rate, and video interface that the DisplayPort instance supports, among others.

    -Interrupt processing

    -DisplayPort interrupts occur on the HPD signal line when the DisplayPort cable is connected/disconnected or when the RX device sends a pulse. The user hardware design must contain an interrupt controller which the DisplayPort TX instance's interrupt signal is connected to. The user application must enable interrupts in the system and set up the interrupt controller such that the XDptx_HpdInterruptHandler handler will service DisplayPort interrupts. When the XDptx_HpdInterruptHandler function is invoked, the handler will identify what type of DisplayPort interrupt has occurred, and will call either the HPD event handler function or the HPD pulse handler function, depending on whether a an HPD event on an HPD pulse event occurred.

    -The DisplayPort TX's XDPTX_INTERRUPT_STATUS register indicates the type of interrupt that has occured, and the XDptx_HpdInterruptHandler will use this information to decide which handler to call. An HPD event is identified if bit XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is identified from the XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit.

    -The HPD event handler may be set up by using the XDptx_SetHpdEventHandler function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler function.

    -Multi-stream transport (MST) mode

    -The driver handles MST mode functionality, including sideband messaging, topology discovery, virtual channel payload ID table management, and directing streams to different sinks.

    -MST testing has been done at all possible link rate/lane count/topology/ resolution/color depth combinations with each setting using following values:

    -

    -Audio

    -The driver does not handle audio. For an example as to how to configure and transmit audio, examples/xdptx_audio_example.c illustrates the required sequence. The user will need to configure the audio source connected to the Displayport TX instance and set up the audio info frame as per user requirements.

    -Asserts

    -Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.

    -Limitations

    -

    -

    -

    Note:
    For a 5.4Gbps link rate, a high performance 7 series FPGA is required with a speed grade of -2 or -3.
    -
    - MODIFICATION HISTORY:

    -

     Ver   Who  Date     Changes
- ----- ---- -------- -----------------------------------------------
- 1.0   als  05/17/14 Initial release.
-       als  08/03/14 Initial MST addition.
- 2.0   als  09/21/14 Added XDptx_DiscoverTopology function and changed
-                     XDptx_IsConnected from macro to function.
- 3.0   als  12/16/14 Updated to use common video library.
-                     Added topology reordering functions:
-                         XDptx_TopologySwapSinks,
-                         XDptx_TopologySortSinksByTiling
-                     Added wrapper functions for remote DPCD/I2C read/writes:
-                         XDptx_RemoteDpcdRead, XDptx_RemoteDpcdWrite,
-                         XDptx_RemoteIicRead, XDptx_RemoteIicWrite
-                     Added EDID utility functions:
-                         XDptx_GetRemoteEdid, XDptx_GetEdidBlock,
-                         XDptx_GetRemoteEdidBlock,
-                         XDptx_GetRemoteEdidDispIdExt,
-                         XDptx_GetDispIdDataBlock,
-                         XDptx_GetRemoteTiledDisplayDb
-                     Remove unused arguments from functions:
-                         LinkCountTotal, RelativeAddress from
-                             XDptx_AllocatePayloadVcIdTable
-                         RegStartAddress from XDptx_IicWrite
-
    +

    xdptx.h File Reference

    #include "xdptx_hw.h"
    #include "xil_assert.h"
    #include "xil_types.h"
    -#include "xvid.h"
    +#include "xvidc.h"
    @@ -180,7 +114,7 @@ Asserts are used within all Xilinx drivers to enforce constraints on argument va - + @@ -791,7 +725,7 @@ This function sets the bits per color value of the video stream.

    This function takes a the main stream attributes from MsaConfigCustom and copies them into InstancePtr->MsaConfig. If desired, given a base set of attributes, the rest of the attributes may be derived. The minimal required main stream attributes (MSA) that must be contained in the MsaConfigCustom structure are:

    +
  • Pixel clock (in Hz)
  • Horizontal sync polarity
  • Vertical sync polarity
  • Horizontal sync pulse width
  • Vertical sync pulse width
  • Horizontal resolution
  • Vertical resolution
  • Vertical back porch
  • Vertical front porch
  • Horizontal back porch
  • Horizontal front porch

    • Parameters:

    Classes

    void XDptx_CfgMsaRecalculate (XDptx *InstancePtr, u8 Stream)
    void XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, u8 Stream, XVid_VideoMode VideoMode)
    void XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, u8 Stream, XVidC_VideoMode VideoMode)
    void XDptx_CfgMsaUseEdidPreferredTiming (XDptx *InstancePtr, u8 Stream, u8 *Edid)
    @@ -851,7 +785,7 @@ This function sets the main stream attribute values in the configuration structu

    - +

    @@ -870,7 +804,7 @@ This function sets the main stream attribute values in the configuration structu - + diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html index 5a20c8c7..d2da9347 100755 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html @@ -42,7 +42,7 @@ This file contains the stream policy maker functions for the - + @@ -229,7 +229,7 @@ This function sets the bits per color value of the video stream.

    This function takes a the main stream attributes from MsaConfigCustom and copies them into InstancePtr->MsaConfig. If desired, given a base set of attributes, the rest of the attributes may be derived. The minimal required main stream attributes (MSA) that must be contained in the MsaConfigCustom structure are:

    +
  • Pixel clock (in Hz)
  • Horizontal sync polarity
  • Vertical sync polarity
  • Horizontal sync pulse width
  • Vertical sync pulse width
  • Horizontal resolution
  • Vertical resolution
  • Vertical back porch
  • Vertical front porch
  • Horizontal back porch
  • Horizontal front porch

    • Parameters:
    XVid_VideoMode XVidC_VideoMode  VideoMode 

    Functions

    void XDptx_CfgMsaRecalculate (XDptx *InstancePtr, u8 Stream)
    void XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, u8 Stream, XVid_VideoMode VideoMode)
    void XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, u8 Stream, XVidC_VideoMode VideoMode)
    void XDptx_CfgMsaUseEdidPreferredTiming (XDptx *InstancePtr, u8 Stream, u8 *Edid)
    @@ -289,7 +289,7 @@ This function sets the main stream attribute values in the configuration structu

    - +

    @@ -308,7 +308,7 @@ This function sets the main stream attribute values in the configuration structu - +
    XVid_VideoMode XVidC_VideoMode  VideoMode