diff --git a/lib/bsp/standalone/data/standalone.tcl b/lib/bsp/standalone/data/standalone.tcl index a4cd3c00..2770ee69 100755 --- a/lib/bsp/standalone/data/standalone.tcl +++ b/lib/bsp/standalone/data/standalone.tcl @@ -1,34 +1,45 @@ -############################################################################### +############################################################################## # -# Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +# Copyright (C) 2014 Xilinx, Inc. All rights reserved. # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: +# This file contains confidential and proprietary information of Xilinx, Inc. +# and is protected under U.S. and international copyright and other +# intellectual property laws. # -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. +# DISCLAIMER +# This disclaimer is not a license and does not grant any rights to the +# materials distributed herewith. Except as otherwise provided in a valid +# license issued to you by Xilinx, and to the maximum extent permitted by +# applicable law: +# (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +# XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +# OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +# NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +# and +# (2) Xilinx shall not be liable (whether in contract or tort, including +# negligence, or under any other theory of liability) for any loss or damage of +# any kind or nature related to, arising under or in connection with these +# materials, including for any direct, or any indirect, special, incidental, +# or consequential loss or damage (including loss of data, profits, goodwill, +# or any type of loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was reasonably foreseeable +# or Xilinx had been advised of the possibility of the same. # -# Use of the Software is limited solely to applications: -# (a) running on a Xilinx device, or -# (b) that interact with a Xilinx device through a bus or interconnect. +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail-safe, or for use in +# any application requiring fail-safe performance, such as life-support or +# safety devices or systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any other applications +# that could lead to death, personal injury, or severe property or environmental +# damage (individually and collectively, "Critical Applications"). +# Customer assumes the sole risk and liability of any use of Xilinx products in +# Critical Applications, subject only to applicable laws and regulations +# governing limitations on product liability. # -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -# SOFTWARE. +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +# AT ALL TIMES. # -# Except as contained in this notice, the name of the Xilinx shall not be used -# in advertising or otherwise to promote the sale, use or other dealings in -# this Software without prior written authorization from Xilinx. -# -############################################################################### +############################################################################## # ---------------------------------------------------------------------------- # The following are hardcoded for Zynq. @@ -64,9 +75,12 @@ proc generate {os_handle} { set enable_sw_profile [get_property CONFIG.enable_sw_intrusive_profiling $os_handle] set mb_exceptions false - # proctype should be "microblaze" or ps7_cortexa9 + # proctype should be "microblaze" or pss_cortexa53 or pss_cortexr5 or ps7_cortexa9 set mbsrcdir "./src/microblaze" + set cortexa53srcdir "./src/cortexa53" + set cortexr5srcdir "./src/cortexr5" set cortexa9srcdir "./src/cortexa9" + set procdrv [get_sw_processor] set commonsrcdir "./src/common" foreach entry [glob -nocomplain [file join $commonsrcdir *]] { @@ -76,7 +90,7 @@ proc generate {os_handle} { # Only processor specific file should be copied to specified standalone folder # write a API which needs compiler, switch $proctype { - "microblaze" { + "microblaze" { foreach entry [glob -nocomplain [file join $mbsrcdir *]] { # Copy over only files that are not related to exception handling. All such files have exception in their names file copy -force $entry "./src/" @@ -84,6 +98,38 @@ proc generate {os_handle} { set need_config_file "true" set mb_exceptions [mb_has_exceptions $hw_proc_handle] } + "pss_cortexa53" { + set procdrv [get_sw_processor] + set ccdir "./src/cortexa53/gcc" + foreach entry [glob -nocomplain [file join $cortexa53srcdir *]] { + file copy -force $entry "./src/" + } + foreach entry [glob -nocomplain [file join $ccdir *]] { + file copy -force $entry "./src/" + } + file delete -force "./src/gcc" + + set file_handle [::hsm::utils::open_include_file "xparameters.h"] + puts $file_handle "#include \"xparameters_ps.h\"" + puts $file_handle "" + close $file_handle + } + "pss_cortexr5" { + set procdrv [get_sw_processor] + set ccdir "./src/cortexr5/gcc" + foreach entry [glob -nocomplain [file join $cortexr5srcdir *]] { + file copy -force $entry "./src/" + } + foreach entry [glob -nocomplain [file join $ccdir *]] { + file copy -force $entry "./src/" + } + file delete -force "./src/gcc" + + set file_handle [::hsm::utils::open_include_file "xparameters.h"] + puts $file_handle "#include \"xparameters_ps.h\"" + puts $file_handle "" + close $file_handle + } "ps7_cortexa9" { set procdrv [get_sw_processor] set compiler [get_property CONFIG.compiler $procdrv] @@ -125,6 +171,10 @@ proc generate {os_handle} { if { $proctype == "microblaze" } { puts $makeconfig "LIBSOURCES = *.c *.S" puts $makeconfig "PROFILE_ARCH_OBJS = profile_mcount_mb.o" + } elseif { $proctype == "pss_cortexr5" } { + puts $makeconfig "LIBSOURCES = *.c *.S" + } elseif { $proctype == "pss_cortexa53" } { + puts $makeconfig "LIBSOURCES = *.c *.s *.S" } elseif { $proctype == "ps7_cortexa9" } { if {[string compare -nocase $compiler "armcc"] == 0} { puts $makeconfig "LIBSOURCES = *.c *.s" @@ -144,8 +194,10 @@ proc generate {os_handle} { } close $makeconfig - # Remove microblaze, cortexa9 and common directories... + # Remove microblaze, cortexr5, cortexa53 and common directories... file delete -force $mbsrcdir + file delete -force $cortexr5srcdir + file delete -force $cortexa53srcdir file delete -force $cortexa9srcdir file delete -force $commonsrcdir @@ -528,7 +580,7 @@ proc handle_profile { os_handle proctype } { set proc [get_sw_processor] - if {$proctype == "ps7_cortexa9"} { + if {{$proctype == "pss_cortexa53"} | {$proctype == "pss_cortexr5"} | {$proctype == "ps7_cortexa9"}} { set sw_proc_handle [get_sw_processor] set hw_proc_handle [get_cells [get_property HW_INSTANCE $sw_proc_handle]] set cpu_freq [get_property CONFIG.C_CPU_CLK_FREQ_HZ $hw_proc_handle] @@ -557,7 +609,7 @@ proc handle_profile { os_handle proctype } { puts $config_file "#define SAMPLE_FREQ_HZ 100000" puts $config_file "#define TIMER_CLK_TICKS [expr $cpu_freq / 100000]" - # proctype should be "microblaze" or "ps7_cortexa9" + # proctype should be "microblaze" or "pss_cortexa53" switch $proctype { "microblaze" { # Microblaze Processor. @@ -571,6 +623,37 @@ proc handle_profile { os_handle proctype } { } } + "pss_cortexa53" { + # Cortex A53 Processor. + + puts $config_file "#define PROC_CORTEXA53 1" + set timer_inst [get_property CONFIG.profile_timer $os_handle] + if { [string compare -nocase $timer_inst "none"] == 0 } { + # SCU Timer + puts $config_file "#define ENABLE_SCU_TIMER 1" + puts $config_file "#define ENABLE_SYS_INTR 1" + puts $config_file "#define PROFILE_TIMER_BASEADDR $scutimer_baseaddr" + puts $config_file "#define PROFILE_TIMER_INTR_ID $scutimer_intr" + puts $config_file "#define SCUGIC_CPU_BASEADDR $scugic_cpu_base" + puts $config_file "#define SCUGIC_DIST_BASEADDR $scugic_dist_base" + } + } + "pss_cortexr5" { + # Cortex R5 Processor. + + puts $config_file "#define PROC_CORTEXR5 1" + set timer_inst [get_property CONFIG.profile_timer $os_handle] + if { [string compare -nocase $timer_inst "none"] == 0 } { + # SCU Timer + puts $config_file "#define ENABLE_SCU_TIMER 1" + puts $config_file "#define ENABLE_SYS_INTR 1" + puts $config_file "#define PROFILE_TIMER_BASEADDR $scutimer_baseaddr" + puts $config_file "#define PROFILE_TIMER_INTR_ID $scutimer_intr" + puts $config_file "#define SCUGIC_CPU_BASEADDR $scugic_cpu_base" + puts $config_file "#define SCUGIC_DIST_BASEADDR $scugic_dist_base" + } + } + "ps7_cortexa9" { # Cortex A9 Processor. diff --git a/lib/bsp/standalone/src/changelog.txt b/lib/bsp/standalone/src/changelog.txt index f985a091..a7e517e5 100755 --- a/lib/bsp/standalone/src/changelog.txt +++ b/lib/bsp/standalone/src/changelog.txt @@ -3,210 +3,5 @@ * * Ver Who Date Changes * ----- ---- -------- --------------------------------------------------- - * 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros - * 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs - * 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but - * cacheable regions - * Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK - * generated by the cpu driver, for enabling caches - * 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/ - * write-thru caches - * 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC - * Updated the MMU table to mark OCM in high address space - * as inner cacheable and reserved space as Invalid - * 3.03a sdm 08/20/11 Changes to support FreeRTOS - * Updated the MMU table to mark upper half of the DDR as - * non-cacheable - * Setup supervisor and abort mode stacks - * Do not initialize/enable L2CC in case of AMP - * Initialize UART1 for 9600bps in case of AMP - * 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC - * in case of AMP - * 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event - * counters - * 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include - * xparameters.h file for CR630532 - Xil_DCacheFlush()/ - * Xil_DCacheFlushRange() functions in standalone BSP v3_02a - * for MicroBlaze will invalidate data in the cache instead - * of flushing it for writeback caches - * 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7 - * 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values - * Remove redundant dsb/dmb instructions in cache maintenance - * APIs - * Remove redundant dsb in mcr instruction - * 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable - * 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through - * driver tcl in xparameters.h. Update the gcc/translationtable.s - * for the QSPI complete address range - DT644567 - * Removed profile directory for armcc compiler and changed - * profiling setting to false in standalone_v2_1_0.tcl file - * Deleting boot.S file after preprocessing for armcc compiler - * 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to - * invalidate the caches before enabling back the MMU and - * D cache. - * 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file - * xil_mmu.c. Now we invalidate UTLB, Branch predictor - * array, flush the D-cache before changing the attributes - * in translation table. The user need not call Xil_DisableMMU - * before calling Xil_SetTlbAttributes. - * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART - * sgd initialization is present. Changes for this were done in - * uart.c and xil-crt0.s. - * Made changes in xil_io.c to use volatile pointers. - * Made changes in xil_mmu.c to correct the function - * Xil_SetTlbAttributes. - * Changes are made xil-crt0.s to initialize the static - * C++ constructors. - * Changes are made in boot.s, to fix the TTBR settings, - * correct the L2 Cache Auxiliary register settings, L2 cache - * latency settings. - * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c - * sgd usleep.c to use global timer intstead of CP15. - * Made changes in cortexa9/gcc/translation_table.s to map - * the peripheral devices as shareable device memory. - * Made changes in cortexa9/gcc/xil-crt0.s to initialize - * the global timer. - * Made changes in cortexa9/armcc/boot.S to initialize - * the global timer. - * Made changes in cortexa9/armcc/translation_table.s to - * map the peripheral devices as shareable device memory. - * Made changes in cortexa9/gcc/boot.S to optimize the - * L2 cache settings. Changes the section properties for - * ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S - * and cortexa9/gcc/translation_table.S. - * Made changes in cortexa9/xil_cache.c to change the - * cache invalidation order. - * 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove - * compilation/linking issues for C++ compiler. - * Made changes in mb_interface.h to remove compilation/ - * linking issues for C++ compiler. - * Added macros for swapb and swaph microblaze instructions - * mb_interface.h - * Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c - * for CortexA9. - * 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address - * 3.07a asa 08/31/12 Added xil_printf.h include - * 3.07a sgd 09/18/12 Corrected the L2 cache enable settings - * Corrected L2 cache sequence disable sequence - * 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option - * 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for - * irq/fiq handling. - * Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This - * fixes the CR #692094. - * 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552. - * 3.10a srt 04/18/13 Implemented ARM Erratas. - * Cortex A9 Errata - 742230, 743622, 775420, 794073 - * L2Cache PL310 Errata - 588369, 727915, 759370 - * Please refer to file 'xil_errata.h' for errata - * description. - * 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older - * cache APIs were corresponding to only Layer 1 cache - * memories. New APIs were now added and the existing cache - * related APIs were changed to provide a uniform interface - * to flush/invalidate/enable/disable the complete cache - * system which includes both L1 and L2 caches. The changes - * for these were done in: - * src/microblaze/xil_cache.c and src/microblaze/xil_cache.h - * files. - * Four new files were added for supporting L2 cache. They are: - * microblaze_flush_cache_ext.S-> Flushes L2 cache - * microblaze_flush_cache_ext_range.S -> Flushes a range of - * memory in L2 cache. - * microblaze_invalidate_cache_ext.S-> Invalidates L2 cache - * microblaze_invalidate_cache_ext_range -> Invalidates a - * range of memory in L2 cache. - * These changes are done to implement PR #697214. - * 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to - * fix the CR #706464. L2 cache disabling happens independent - * of L1 data cache disable operation. Changes are done in the - * same file in cache handling APIs to do a L2 cache sync - * (poll reg7_?cache_?sync). This fixes CR #700542. - * 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested - * interrupts for ARM. These are done to fix the CR#699680. - * 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach - * sync operation. This fixes the CR# 716781. - * 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support - * for armcc toolchain. - * Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to - * fix issues related to NEON context saving. The assembly - * routines for IRQ and FIQ handling are modified. - * Deprecated the older BSP (3.10a). - * 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid - * various potential issues. Made changes in the function - * Xil_SetAttributes in file xil_mmu.c. - * 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h - * in src\cortexa9 and src\microblaze folders. - * 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of - * L2 cache sync operation and to fix issues around complete - * L2 cache flush/invalidation by ways. - * 3.12a asa 10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h - * to fix linking issues with armcc/DS-5. Modified the armcc - * makefile to fix issues. - * 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB. - * 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used. - * 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler - * and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and - * src\cortexa9\armcc\) to fix CR#767251 - * 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and - * Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs. - * Few cache lines were missed to invalidate when unaligned address - * invalidation was accommodated in Xil_DCacheInvalidateRange. - * In Xil_L1DCacheInvalidate, while invalidating all L1D cache - * stack memory (which contains return address) was invalidated. So - * stack memory is flushed first and then L1D cache is invalidated. - * This is done to fix CR #763829 - * 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from - * mblaze_nt_types.h file and replace uint32_t with u32 in the - * profile_hist.c to fix the above CR. - * 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a - * instead of libxil.a and added prototypes for - * microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in - * mb_interface.h - * 4.1 hk 04/18/14 Add sleep function. - * 4.1 asa 04/21/14 Fix for CR#764881. Added support for msrset and msrclr. Renamed - * some of the *.s files inMB BSP source to *.S. - * 4.1 asa 04/28/14 Fix for CR#772280. Made changes in file cortexa9/gcc/read.c. - * 4.1 bss 04/29/14 Modified driver tcl to use libxil.a if libgloss.a does not exist - * CR#794205 - * 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and - * common/xil_testcache.c - * Fix for CR#764881. - * 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to - * output the DEBUG logs when -DDEBUG flag is enabled in BSP. - * 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm. - * Also added explanatory notes in cortexa9/xil_cache.c for CR#785243. - * 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and - * cortexa9/armcc/boot.s. Added default exception handlers for data - * abort and prefetch abort using handlers called - * DataAbortHandler and PrefetchAbortHandler respectively in - * cortexa9/xil_exception.c to fix CR#802862. - * 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the - * issue of improper linking of translation_table.s - * 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present - * in tool chain to avoid conflicts into some special cases - * 4.2 pkp 07/21/14 Corrected reset value of event counter in function - * Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275 - * 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function - * containing type def u32 defined in xil_types.g to resolve issue of - * CR#805869 - * 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as - * it is not possible to generate timer in nanosecond due to limited - * cpu frequency - * 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of - * uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s - * and iccarm/boot.s. Also uart.c and smc.c have been removed. Also - * removed function definition of XSmc_NorInit and XSmc_NorInit from - * cortexa9/smc.h - * 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_ - * cache_ext_range declarations in mb_interface.h CR#783821. - * Modified profile_mcount_mb.S to fix CR#808412. - * 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in - * cortexa9/iccarm to fix CR#816701 - * 4.2 pkp 09/02/14 modified translation table entries in cortexa9/gcc/translation_table.s, - * armcc/translation_table.s and iccarm/translation_table.s - * to properly defined reserved entries according to address map for - * fixing CR#820146 - * 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s - * and cortexa9/armcc/translation_table.s to resolve compilation - * error for solving CR#822897 -******************************************************************************************/ + * 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp. + *****************************************************************************************/ diff --git a/lib/bsp/standalone/src/common/xbasic_types.h b/lib/bsp/standalone/src/common/xbasic_types.h old mode 100755 new mode 100644 index 91dc6197..f471b734 --- a/lib/bsp/standalone/src/common/xbasic_types.h +++ b/lib/bsp/standalone/src/common/xbasic_types.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -89,15 +100,15 @@ typedef Xuint8 u8; #endif #ifndef TRUE -# define TRUE 1 +# define TRUE 1U #endif #ifndef FALSE -# define FALSE 0 +# define FALSE 0U #endif #ifndef NULL -#define NULL 0 +#define NULL 0U #endif /* diff --git a/lib/bsp/standalone/src/common/xdebug.h b/lib/bsp/standalone/src/common/xdebug.h old mode 100755 new mode 100644 index 899173cf..0143fdcd --- a/lib/bsp/standalone/src/common/xdebug.h +++ b/lib/bsp/standalone/src/common/xdebug.h @@ -1,6 +1,8 @@ #ifndef XDEBUG #define XDEBUG - + +#undef DEBUG + #if defined(DEBUG) && !defined(NDEBUG) #ifndef XDEBUG_WARNING diff --git a/lib/bsp/standalone/src/common/xenv.h b/lib/bsp/standalone/src/common/xenv.h old mode 100755 new mode 100644 index 1674cfae..9aa9ead6 --- a/lib/bsp/standalone/src/common/xenv.h +++ b/lib/bsp/standalone/src/common/xenv.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ diff --git a/lib/bsp/standalone/src/common/xenv_standalone.h b/lib/bsp/standalone/src/common/xenv_standalone.h old mode 100755 new mode 100644 index ddb83111..46d80d28 --- a/lib/bsp/standalone/src/common/xenv_standalone.h +++ b/lib/bsp/standalone/src/common/xenv_standalone.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -66,6 +77,8 @@ #ifndef XENV_STANDALONE_H #define XENV_STANDALONE_H +#include "xil_types.h" + #ifdef __cplusplus extern "C" { #endif @@ -149,7 +162,7 @@ extern "C" { *****************************************************************************/ #define XENV_MEM_FILL(DestPtr, Data, Bytes) \ - memset((void *) DestPtr, (int) Data, (size_t) Bytes) + memset((void *) DestPtr, (s32) Data, (size_t) Bytes) @@ -163,7 +176,7 @@ extern "C" { * A structure that contains a time stamp used by other time stamp macros * defined below. This structure is processor dependent. */ -typedef int XENV_TIME_STAMP; +typedef s32 XENV_TIME_STAMP; /*****************************************************************************/ /** @@ -278,16 +291,16 @@ typedef int XENV_TIME_STAMP; # define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache() # define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ - microblaze_invalidate_dcache_range((int)(Addr), (int)(Len)) + microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len)) #if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) # define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache() # define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ - microblaze_flush_dcache_range((int)(Addr), (int)(Len)) + microblaze_flush_dcache_range((s32)(Addr), (s32)(Len)) #else # define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache() # define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ - microblaze_invalidate_dcache_range((int)(Addr), (int)(Len)) + microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len)) #endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/ #else @@ -307,7 +320,7 @@ typedef int XENV_TIME_STAMP; # define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache() # define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \ - microblaze_invalidate_icache_range((int)(Addr), (int)(Len)) + microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len)) #else # define XCACHE_ENABLE_ICACHE() @@ -340,10 +353,10 @@ typedef int XENV_TIME_STAMP; #define XCACHE_DISABLE_ICACHE() XCache_DisableICache() #define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ - XCache_InvalidateDCacheRange((unsigned int)(Addr), (unsigned)(Len)) + XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len)) #define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ - XCache_FlushDCacheRange((unsigned int)(Addr), (unsigned)(Len)) + XCache_FlushDCacheRange((u32)(Addr), (u32)(Len)) #define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache() diff --git a/lib/bsp/standalone/src/common/xil_assert.c b/lib/bsp/standalone/src/common/xil_assert.c old mode 100755 new mode 100644 index 728bd970..24337c09 --- a/lib/bsp/standalone/src/common/xil_assert.c +++ b/lib/bsp/standalone/src/common/xil_assert.c @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -64,14 +75,14 @@ * sets this variable such that a driver can evaluate this variable * to determine if an assert occurred. */ -unsigned int Xil_AssertStatus; +u32 Xil_AssertStatus; /** * This variable allows the assert functionality to be changed for testing * such that it does not wait infinitely. Use the debugger to disable the * waiting during testing of asserts. */ -int Xil_AssertWait = TRUE; +/*s32 Xil_AssertWait = 1*/ /* The callback function to be invoked when an assert is taken */ static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL; @@ -93,8 +104,9 @@ static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL; * @note None. * ******************************************************************************/ -void Xil_Assert(const char *File, int Line) +void Xil_Assert(const char8 *File, s32 Line) { + s32 Xil_AssertWait = 1; /* if the callback has been set then invoke it */ if (Xil_AssertCallbackRoutine != 0) { (*Xil_AssertCallbackRoutine)(File, Line); @@ -103,7 +115,7 @@ void Xil_Assert(const char *File, int Line) /* if specified, wait indefinitely such that the assert will show up * in testing */ - while (Xil_AssertWait) { + while (Xil_AssertWait != 0) { } } @@ -141,6 +153,6 @@ void Xil_AssertSetCallback(Xil_AssertCallback Routine) ******************************************************************************/ void XNullHandler(void *NullParameter) { - (void) NullParameter; + (void *) NullParameter; } diff --git a/lib/bsp/standalone/src/common/xil_assert.h b/lib/bsp/standalone/src/common/xil_assert.h old mode 100755 new mode 100644 index 2878ef9e..644f13a6 --- a/lib/bsp/standalone/src/common/xil_assert.h +++ b/lib/bsp/standalone/src/common/xil_assert.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -59,19 +70,19 @@ extern "C" { /************************** Constant Definitions *****************************/ -#define XIL_ASSERT_NONE 0 -#define XIL_ASSERT_OCCURRED 1 +#define XIL_ASSERT_NONE 0U +#define XIL_ASSERT_OCCURRED 1U #define XNULL NULL -extern unsigned int Xil_AssertStatus; -extern void Xil_Assert(const char *, int); +extern u32 Xil_AssertStatus; +extern void Xil_Assert(const char8 *File, s32 Line); void XNullHandler(void *NullParameter); /** * This data type defines a callback to be invoked when an * assert occurs. The callback is invoked only when asserts are enabled */ -typedef void (*Xil_AssertCallback) (const char *File, int Line); +typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line); /***************** Macros (Inline Functions) Definitions *********************/ @@ -83,7 +94,7 @@ typedef void (*Xil_AssertCallback) (const char *File, int Line); * (void). This in conjunction with the Xil_AssertWait boolean can be used to * accomodate tests so that asserts which fail allow execution to continue. * -* @param expression is the expression to evaluate. If it evaluates to +* @param Expression is the expression to evaluate. If it evaluates to * false, the assert occurs. * * @return Returns void unless the Xil_AssertWait variable is true, in which @@ -109,7 +120,7 @@ typedef void (*Xil_AssertCallback) (const char *File, int Line); * conjunction with the Xil_AssertWait boolean can be used to accomodate tests * so that asserts which fail allow execution to continue. * -* @param expression is the expression to evaluate. If it evaluates to false, +* @param Expression is the expression to evaluate. If it evaluates to false, * the assert occurs. * * @return Returns 0 unless the Xil_AssertWait variable is true, in which diff --git a/lib/bsp/standalone/src/common/xil_cache_vxworks.h b/lib/bsp/standalone/src/common/xil_cache_vxworks.h old mode 100755 new mode 100644 index 94f58a5d..2e639c81 --- a/lib/bsp/standalone/src/common/xil_cache_vxworks.h +++ b/lib/bsp/standalone/src/common/xil_cache_vxworks.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ diff --git a/lib/bsp/standalone/src/common/xil_hal.h b/lib/bsp/standalone/src/common/xil_hal.h old mode 100755 new mode 100644 index afa97e88..57d857d1 --- a/lib/bsp/standalone/src/common/xil_hal.h +++ b/lib/bsp/standalone/src/common/xil_hal.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ diff --git a/lib/bsp/standalone/src/common/xil_macroback.h b/lib/bsp/standalone/src/common/xil_macroback.h old mode 100755 new mode 100644 index 58632038..fce9a3da --- a/lib/bsp/standalone/src/common/xil_macroback.h +++ b/lib/bsp/standalone/src/common/xil_macroback.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ diff --git a/lib/bsp/standalone/src/common/xil_testcache.c b/lib/bsp/standalone/src/common/xil_testcache.c old mode 100755 new mode 100644 index 8f2275ff..93659045 --- a/lib/bsp/standalone/src/common/xil_testcache.c +++ b/lib/bsp/standalone/src/common/xil_testcache.c @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -51,19 +62,25 @@ * This file contain functions that all operate on HAL. * ******************************************************************************/ +#ifdef __ARM__ #include "xil_cache.h" #include "xil_testcache.h" +#include "xil_types.h" +#include "xpseudo_asm.h" +#ifdef __aarch64__ +#include "xreg_cortexa53.h" +#else +#include "xreg_cortexr5.h" +#endif -extern void xil_printf(const char *ctrl1, ...); +extern void xil_printf(const char8 *ctrl1, ...); #define DATA_LENGTH 128 -#ifdef __GNUC__ -static u32 Data[DATA_LENGTH] __attribute__ ((aligned(32))); -#elif defined (__ICCARM__) -static u32 Data[DATA_LENGTH]; +#ifdef __aarch64__ +static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64))); #else -static u32 Data[DATA_LENGTH] __attribute__ ((aligned(32))); +static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32))); #endif /** @@ -77,30 +94,35 @@ static u32 Data[DATA_LENGTH] __attribute__ ((aligned(32))); * - 0 is returned for a pass * - -1 is returned for a failure */ -int Xil_TestDCacheRange(void) +s32 Xil_TestDCacheRange(void) { - int Index; - int Status; - - u32 Value; + s32 Index; + s32 Status = 0; + u32 CtrlReg; + INTPTR Value; xil_printf("-- Cache Range Test --\n\r"); - for (Index = 0; Index < DATA_LENGTH; Index++) Data[Index] = 0xA0A00505; xil_printf(" initialize Data done:\r\n"); - Xil_DCacheFlushRange((u32)Data, DATA_LENGTH * sizeof(u32)); + Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); xil_printf(" flush range done\r\n"); - for (Index = 0; Index < DATA_LENGTH; Index++) - Data[Index] = Index + 3; - Xil_DCacheInvalidateRange((u32)Data, DATA_LENGTH * sizeof(u32)); - - xil_printf(" invalidate dcache range done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); Status = 0; @@ -113,15 +135,80 @@ int Xil_TestDCacheRange(void) } } + if (!Status) { + xil_printf(" Flush worked\r\n"); + } + else { + xil_printf("Error: flush dcache range not working\r\n"); + } + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A0C505; + + + + Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = Index + 3; + + Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + xil_printf(" invalidate dcache range done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A0A05; + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + if (Value != 0xA0A0A05) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { xil_printf(" Invalidate worked\r\n"); } else { xil_printf("Error: Invalidate dcache range not working\r\n"); } - xil_printf("-- Cache Range Test Complete --\r\n"); - return Status; } @@ -136,23 +223,66 @@ int Xil_TestDCacheRange(void) * - 0 is returned for a pass * - -1 is returned for a failure */ -int Xil_TestDCacheAll(void) +s32 Xil_TestDCacheAll(void) { - int Index; - int Status; - u32 Value; + s32 Index; + s32 Status; + INTPTR Value; + u32 CtrlReg; xil_printf("-- Cache All Test --\n\r"); - for (Index = 0; Index < DATA_LENGTH; Index++) Data[Index] = 0x50500A0A; - xil_printf(" initialize Data done:\r\n"); Xil_DCacheFlush(); - xil_printf(" flush all done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + + if (Value != 0x50500A0A) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { + xil_printf(" Flush all worked\r\n"); + } + else { + xil_printf("Error: Flush dcache all not working\r\n"); + } + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x505FFA0A; + + Xil_DCacheFlush(); + for (Index = 0; Index < DATA_LENGTH; Index++) Data[Index] = Index + 3; @@ -160,12 +290,35 @@ int Xil_TestDCacheAll(void) Xil_DCacheInvalidate(); xil_printf(" invalidate all done\r\n"); - + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x50CFA0A; + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); Status = 0; for (Index = 0; Index < DATA_LENGTH; Index++) { Value = Data[Index]; - if (Value != 0x50500A0A) { + if (Value != 0x50CFA0A) { Status = -1; xil_printf("Data[%d] = %x\r\n", Index, Value); break; @@ -176,13 +329,12 @@ int Xil_TestDCacheAll(void) xil_printf(" Invalidate all worked\r\n"); } else { - xil_printf("Error: Invalidate dcache all not working\r\n"); + xil_printf("Error: Invalidate dcache all not working\r\n"); } xil_printf("-- DCache all Test Complete --\n\r"); return Status; - } @@ -194,12 +346,12 @@ int Xil_TestDCacheAll(void) * - 0 is returned for a pass * The function will hang if it fails. */ -int Xil_TestICacheRange(void) +s32 Xil_TestICacheRange(void) { - Xil_ICacheInvalidateRange((u32)Xil_TestICacheRange, 1024); - Xil_ICacheInvalidateRange((u32)Xil_TestDCacheRange, 1024); - Xil_ICacheInvalidateRange((u32)Xil_TestDCacheAll, 1024); + Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024); + Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024); + Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024); xil_printf("-- Invalidate icache range done --\r\n"); @@ -214,9 +366,10 @@ int Xil_TestICacheRange(void) * - 0 is returned for a pass * The function will hang if it fails. */ -int Xil_TestICacheAll(void) +s32 Xil_TestICacheAll(void) { Xil_ICacheInvalidate(); xil_printf("-- Invalidate icache all done --\r\n"); return 0; } +#endif diff --git a/lib/bsp/standalone/src/common/xil_testcache.h b/lib/bsp/standalone/src/common/xil_testcache.h old mode 100755 new mode 100644 index 0981bd0e..659d7a03 --- a/lib/bsp/standalone/src/common/xil_testcache.h +++ b/lib/bsp/standalone/src/common/xil_testcache.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -49,10 +60,10 @@ extern "C" { #endif -extern int Xil_TestDCacheRange(void); -extern int Xil_TestDCacheAll(void); -extern int Xil_TestICacheRange(void); -extern int Xil_TestICacheAll(void); +extern s32 Xil_TestDCacheRange(void); +extern s32 Xil_TestDCacheAll(void); +extern s32 Xil_TestICacheRange(void); +extern s32 Xil_TestICacheAll(void); #ifdef __cplusplus } diff --git a/lib/bsp/standalone/src/common/xil_testio.c b/lib/bsp/standalone/src/common/xil_testio.c old mode 100755 new mode 100644 index bc638d07..ad5158ca --- a/lib/bsp/standalone/src/common/xil_testio.c +++ b/lib/bsp/standalone/src/common/xil_testio.c @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -60,19 +71,19 @@ * * Endian swap a 16-bit word. * @param Data is the 16-bit word to be swapped. - * @return The endian swapped valud. + * @return The endian swapped value. * */ static u16 Swap16(u16 Data) { - return ((Data >> 8) & 0x00FF) | ((Data << 8) & 0xFF00); + return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U); } /** * * Endian swap a 32-bit word. * @param Data is the 32-bit word to be swapped. - * @return The endian swapped valud. + * @return The endian swapped value. * */ static u32 Swap32(u32 Data) @@ -83,13 +94,13 @@ static u32 Swap32(u32 Data) u16 Swap16Lo; u16 Swap16Hi; - Hi16 = (u16)((Data >> 16) & 0x0000FFFF); - Lo16 = (u16)(Data & 0x0000FFFF); + Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU); + Lo16 = (u16)(Data & 0x0000FFFFU); Swap16Lo = Swap16(Lo16); Swap16Hi = Swap16(Hi16); - return (((u32)(Swap16Lo)) << 16) | ((u32)Swap16Hi); + return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi); } /*****************************************************************************/ @@ -100,7 +111,7 @@ static u32 Swap32(u32 Data) * values. * * @param Addr is a pointer to the region of memory to be tested. -* @param Len is the length of the block. +* @param Length is the Length of the block. * @param Value is the constant used for writting the memory. * * @return @@ -110,22 +121,23 @@ static u32 Swap32(u32 Data) * *****************************************************************************/ -int Xil_TestIO8(u8 *Addr, int Len, u8 Value) +s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value) { u8 ValueIn; - int Index; + s32 Index; + s32 Status = 0; - for (Index = 0; Index < Len; Index++) { - Xil_Out8((u32)Addr, Value); + for (Index = 0; Index < Length; Index++) { + Xil_Out8((INTPTR)Addr, Value); - ValueIn = Xil_In8((u32)Addr); + ValueIn = Xil_In8((INTPTR)Addr); - if (Value != ValueIn) { - return -1; + if ((Value != ValueIn) && (Status == 0)) { + Status = -1; + break; } } - - return 0; + return Status; } @@ -142,7 +154,7 @@ int Xil_TestIO8(u8 *Addr, int Len, u8 Value) * read-in value before comparing is controlled by the 5th argument. * * @param Addr is a pointer to the region of memory to be tested. -* @param Len is the length of the block. +* @param Length is the Length of the block. * @param Value is the constant used for writting the memory. * @param Kind is the test kind. Acceptable values are: * XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. @@ -155,60 +167,63 @@ int Xil_TestIO8(u8 *Addr, int Len, u8 Value) * *****************************************************************************/ -int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap) +s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap) { - u16 ValueIn; - int Index; + u16 *TempAddr16; + u16 ValueIn = 0U; + s32 Index; + TempAddr16 = Addr; + Xil_AssertNonvoid(TempAddr16 != NULL); - for (Index = 0; Index < Len; Index++) { + for (Index = 0; Index < Length; Index++) { switch (Kind) { case XIL_TESTIO_LE: - Xil_Out16LE((u32)Addr, Value); + Xil_Out16LE((INTPTR)TempAddr16, Value); break; case XIL_TESTIO_BE: - Xil_Out16BE((u32)Addr, Value); + Xil_Out16BE((INTPTR)TempAddr16, Value); break; default: - Xil_Out16((u32)Addr, Value); + Xil_Out16((INTPTR)TempAddr16, Value); break; } - ValueIn = Xil_In16((u32)Addr); + ValueIn = Xil_In16((INTPTR)TempAddr16); - if (Kind && Swap) + if ((Kind != 0) && (Swap != 0)) { ValueIn = Swap16(ValueIn); + } if (Value != ValueIn) { return -1; } /* second round */ - Xil_Out16((u32)Addr, Value); + Xil_Out16((INTPTR)TempAddr16, Value); switch (Kind) { case XIL_TESTIO_LE: - ValueIn = Xil_In16LE((u32)Addr); + ValueIn = Xil_In16LE((INTPTR)TempAddr16); break; case XIL_TESTIO_BE: - ValueIn = Xil_In16BE((u32)Addr); + ValueIn = Xil_In16BE((INTPTR)TempAddr16); break; default: - ValueIn = Xil_In16((u32)Addr); + ValueIn = Xil_In16((INTPTR)TempAddr16); break; } - if (Kind && Swap) + if ((Kind != 0) && (Swap != 0)) { ValueIn = Swap16(ValueIn); + } if (Value != ValueIn) { return -1; } - Addr++; + TempAddr16 += sizeof(u16); } - return 0; - } @@ -225,7 +240,7 @@ int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap) * before comparing is controlled by the 5th argument. * * @param Addr is a pointer to the region of memory to be tested. -* @param Len is the length of the block. +* @param Length is the Length of the block. * @param Value is the constant used for writting the memory. * @param Kind is the test kind. Acceptable values are: * XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. @@ -237,56 +252,61 @@ int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap) * - 0 is returned for a pass * *****************************************************************************/ -int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap) +s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap) { - u32 ValueIn; - int Index; + u32 *TempAddr; + u32 ValueIn = 0U; + s32 Index; + TempAddr = Addr; + Xil_AssertNonvoid(TempAddr != NULL); - for (Index = 0; Index < Len; Index++) { + for (Index = 0; Index < Length; Index++) { switch (Kind) { case XIL_TESTIO_LE: - Xil_Out32LE((u32)Addr, Value); + Xil_Out32LE((INTPTR)TempAddr, Value); break; case XIL_TESTIO_BE: - Xil_Out32BE((u32)Addr, Value); + Xil_Out32BE((INTPTR)TempAddr, Value); break; default: - Xil_Out32((u32)Addr, Value); + Xil_Out32((INTPTR)TempAddr, Value); break; } - ValueIn = Xil_In32((u32)Addr); + ValueIn = Xil_In32((INTPTR)TempAddr); - if (Kind && Swap) + if ((Kind != 0) && (Swap != 0)) { ValueIn = Swap32(ValueIn); + } if (Value != ValueIn) { return -1; } /* second round */ - Xil_Out32((u32)Addr, Value); + Xil_Out32((INTPTR)TempAddr, Value); switch (Kind) { case XIL_TESTIO_LE: - ValueIn = Xil_In32LE((u32)Addr); + ValueIn = Xil_In32LE((INTPTR)TempAddr); break; case XIL_TESTIO_BE: - ValueIn = Xil_In32BE((u32)Addr); + ValueIn = Xil_In32BE((INTPTR)TempAddr); break; default: - ValueIn = Xil_In32((u32)Addr); + ValueIn = Xil_In32((INTPTR)TempAddr); break; } - if (Kind && Swap) + if ((Kind != 0) && (Swap != 0)) { ValueIn = Swap32(ValueIn); + } if (Value != ValueIn) { return -1; } - Addr++; + TempAddr += sizeof(u32); } return 0; } diff --git a/lib/bsp/standalone/src/common/xil_testio.h b/lib/bsp/standalone/src/common/xil_testio.h old mode 100755 new mode 100644 index 738e197f..cd351ec4 --- a/lib/bsp/standalone/src/common/xil_testio.h +++ b/lib/bsp/standalone/src/common/xil_testio.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -80,9 +91,9 @@ extern "C" { /************************** Function Prototypes ******************************/ -extern int Xil_TestIO8(u8 *Addr, int Len, u8 Value); -extern int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap); -extern int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap); +extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value); +extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap); +extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap); #ifdef __cplusplus } diff --git a/lib/bsp/standalone/src/common/xil_testmem.c b/lib/bsp/standalone/src/common/xil_testmem.c old mode 100755 new mode 100644 index 6c31e6f0..19a1c1d8 --- a/lib/bsp/standalone/src/common/xil_testmem.c +++ b/lib/bsp/standalone/src/common/xil_testmem.c @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -92,16 +103,18 @@ static u32 RotateRight(u32 Input, u8 Width); * patterns used not to repeat over the region tested. * *****************************************************************************/ -int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) +s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) { u32 I; - u32 J; + u32 j; u32 Val; u32 FirtVal; - u32 Word; + u32 WordMem32; + s32 Status = 0; - Xil_AssertNonvoid(Words != 0); - Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST); + Xil_AssertNonvoid(Addr != NULL); /* * variable initialization @@ -109,25 +122,14 @@ int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) Val = XIL_TESTMEM_INIT_VALUE; FirtVal = XIL_TESTMEM_INIT_VALUE; - /* - * Select the proper Subtest - */ - switch (Subtest) { - - case XIL_TESTMEM_ALLMEMTESTS: - - /* this case executes all of the Subtests */ - - /* fall through case statement */ - - case XIL_TESTMEM_INCREMENT: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'FirtVal' */ - for (I = 0L; I < Words; I++) { - Addr[I] = Val; + for (I = 0U; I < Words; I++) { + *(Addr+I) = Val; Val++; } @@ -144,104 +146,90 @@ int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) * Val */ - for (I = 0L; I < Words; I++) { - Word = Addr[I]; + for (I = 0U; I < Words; I++) { + WordMem32 = *(Addr+I); - if (Word != Val) { - return -1; + if (WordMem32 != Val) { + Status = -1; + goto End_Label; } Val++; } + } - - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - - - /* end of case 1 */ - - /* fall through case statement */ - - case XIL_TESTMEM_WALKONES: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial * test Patterns for walking ones test */ - for (J = 0L; J < 32; J++) { + for (j = 0U; j < (u32)32; j++) { /* * Generate an initial value for walking ones test * to test for bad data bits */ - Val = 1 << J; + Val = (1U << j); /* * START walking ones test * Write a one to each data bit indifferent locations */ - for (I = 0L; I < 32; I++) { + for (I = 0U; I < (u32)32; I++) { /* write memory location */ - Addr[I] = Val; - Val = (u32) RotateLeft(Val, 32); + *(Addr+I) = Val; + Val = (u32) RotateLeft(Val, 32U); } /* * Restore the reference 'val' to the * initial value */ - Val = 1 << J; + Val = 1U << j; /* Read the values from each location that was * written */ - for (I = 0L; I < 32; I++) { + for (I = 0U; I < (u32)32; I++) { /* read memory location */ - Word = Addr[I]; + WordMem32 = *(Addr+I); - if (Word != Val) { - return -1; + if (WordMem32 != Val) { + Status = -1; + goto End_Label; } - Val = (u32)RotateLeft(Val, 32); + Val = (u32)RotateLeft(Val, 32U); } - } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - - /* end of case 2 */ - /* fall through case statement */ - - case XIL_TESTMEM_WALKZEROS: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible * initial test Patterns for walking zeros test */ - for (J = 0L; J < 32; J++) { + for (j = 0U; j < (u32)32; j++) { /* * Generate an initial value for walking ones test * to test for bad data bits */ - Val = ~(1 << J); + Val = ~(1U << j); /* * START walking zeros test * Write a one to each data bit indifferent locations */ - for (I = 0L; I < 32; I++) { + for (I = 0U; I < (u32)32; I++) { /* write memory location */ - Addr[I] = Val; - Val = ~((u32)RotateLeft(~Val, 32)); + *(Addr+I) = Val; + Val = ~((u32)RotateLeft(~Val, 32U)); } /* @@ -249,35 +237,29 @@ int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) * initial value */ - Val = ~(1 << J); + Val = ~(1U << j); /* Read the values from each location that was * written */ - for (I = 0L; I < 32; I++) { + for (I = 0U; I < (u32)32; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem32 = *(Addr+I); + if (WordMem32 != Val) { + Status = -1; + goto End_Label; } - Val = ~((u32)RotateLeft(~Val, 32)); + Val = ~((u32)RotateLeft(~Val, 32U)); } } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - - /* end of case 3 */ - - /* fall through case statement */ - - case XIL_TESTMEM_INVERSEADDR: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Val = (u32) (~((u32) (&Addr[I]))); - Addr[I] = Val; + Val = (u32) (~((INTPTR) (&Addr[I]))); + *(Addr+I) = Val; } /* @@ -285,31 +267,26 @@ int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) * of tested memory */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* Read the location */ - Word = Addr[I]; - Val = (u32) (~((u32) (&Addr[I]))); + WordMem32 = *(Addr+I); + Val = (u32) (~((INTPTR) (&Addr[I]))); - if ((Word ^ Val) != 0x00000000) { - return -1; + if ((WordMem32 ^ Val) != 0x00000000U) { + Status = -1; + goto End_Label; } } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 4 */ - - /* fall through case statement */ - - case XIL_TESTMEM_FIXEDPATTERN: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing */ - if (Pattern == 0) { - Val = 0xDEADBEEF; + if (Pattern == (u32)0) { + Val = 0xDEADBEEFU; } else { Val = Pattern; @@ -319,9 +296,9 @@ int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) * Fill the memory with fixed Pattern */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Addr[I] = Val; + *(Addr+I) = Val; } /* @@ -330,33 +307,20 @@ int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) * with the fixed Pattern */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem32 = *(Addr+I); + if (WordMem32 != Val) { + Status = -1; + goto End_Label; } } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 5 */ - - /* this break is for the prior fall through case statements */ - - break; - - default: - return -1; - - } /* end of switch */ - - /* Successfully passed memory test ! */ - - return 0; +End_Label: + return Status; } /*****************************************************************************/ @@ -388,16 +352,18 @@ int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) * patterns used not to repeat over the region tested. * *****************************************************************************/ -int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) +s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) { u32 I; - u32 J; + u32 j; u16 Val; u16 FirtVal; - u16 Word; + u16 WordMem16; + s32 Status = 0; - Xil_AssertNonvoid(Words != 0); + Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + Xil_AssertNonvoid(Addr != NULL); /* * variable initialization @@ -409,22 +375,14 @@ int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) * selectthe proper Subtest(s) */ - switch (Subtest) { - - case XIL_TESTMEM_ALLMEMTESTS: - - /* this case executes all of the Subtests */ - - /* fall through case statement */ - - case XIL_TESTMEM_INCREMENT: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'FirtVal' */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Addr[I] = Val; + *(Addr+I) = Val; Val++; } /* @@ -439,145 +397,131 @@ int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) * with the incrementing reference val */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; } Val++; } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } + } - /* end of case 1 */ - /* fall through case statement */ - - case XIL_TESTMEM_WALKONES: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial test * Patterns for walking ones test */ - for (J = 0L; J < 16; J++) { + for (j = 0U; j < (u32)16; j++) { /* * Generate an initial value for walking ones test * to test for bad data bits */ - Val = 1 << J; + Val = (u16)((u32)1 << j); /* * START walking ones test * Write a one to each data bit indifferent locations */ - for (I = 0L; I < 16; I++) { + for (I = 0U; I < (u32)16; I++) { /* write memory location */ - Addr[I] = Val; - Val = (u16)RotateLeft(Val, 16); + *(Addr+I) = Val; + Val = (u16)RotateLeft(Val, 16U); } /* * Restore the reference 'Val' to the * initial value */ - Val = 1 << J; + Val = (u16)((u32)1 << j); /* Read the values from each location that was written */ - for (I = 0L; I < 16; I++) { + for (I = 0U; I < (u32)16; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; } - Val = (u16)RotateLeft(Val, 16); + Val = (u16)RotateLeft(Val, 16U); } - } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 2 */ - /* fall through case statement */ + } - case XIL_TESTMEM_WALKZEROS: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible initial * test Patterns for walking zeros test */ - for (J = 0L; J < 16; J++) { + for (j = 0U; j < (u32)16; j++) { /* * Generate an initial value for walking ones * test to test for bad * data bits */ - Val = ~(1 << J); + Val = ~(1U << j); /* * START walking zeros test * Write a one to each data bit indifferent locations */ - for (I = 0L; I < 16; I++) { + for (I = 0U; I < (u32)16; I++) { /* write memory location */ - Addr[I] = Val; - Val = ~((u16)RotateLeft(~Val, 16)); + *(Addr+I) = Val; + Val = ~((u16)RotateLeft(~Val, 16U)); } /* * Restore the reference 'Val' to the * initial value */ - Val = ~(1 << J); + Val = ~(1U << j); /* Read the values from each location that was written */ - for (I = 0L; I < 16; I++) { + for (I = 0U; I < (u32)16; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; } - Val = ~((u16)RotateLeft(~Val, 16)); + Val = ~((u16)RotateLeft(~Val, 16U)); } } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 3 */ - /* fall through case statement */ + } - case XIL_TESTMEM_INVERSEADDR: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Val = (u16) (~((u32) (&Addr[I]))); - Addr[I] = Val; + Val = (u16) (~((INTPTR)(&Addr[I]))); + *(Addr+I) = Val; } /* * Check every word within the words * of tested memory */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* read memory location */ - Word = Addr[I]; - Val = (u16) (~((u32) (&Addr[I]))); - if ((Word ^ Val) != 0x0000) { - return -1; + WordMem16 = *(Addr+I); + Val = (u16) (~((INTPTR) (&Addr[I]))); + if ((WordMem16 ^ Val) != 0x0000U) { + Status = -1; + goto End_Label; } } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 4 */ - /* fall through case statement */ + } - case XIL_TESTMEM_FIXEDPATTERN: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing */ - if (Pattern == 0) { - Val = 0xDEAD; + if (Pattern == (u16)0) { + Val = 0xDEADU; } else { Val = Pattern; @@ -587,9 +531,9 @@ int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) * Fill the memory with fixed pattern */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Addr[I] = Val; + *(Addr+I) = Val; } /* @@ -598,29 +542,18 @@ int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) * with the fixed pattern */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; } } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 5 */ - /* this break is for the prior fall through case statements */ + } - break; - - default: - return -1; - - } /* end of switch */ - - /* Successfully passed memory test ! */ - - return 0; +End_Label: + return Status; } @@ -653,16 +586,18 @@ int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) * patterns used not to repeat over the region tested. * *****************************************************************************/ -int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) +s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) { u32 I; - u32 J; + u32 j; u8 Val; u8 FirtVal; - u8 Word; + u8 WordMem8; + s32 Status = 0; - Xil_AssertNonvoid(Words != 0); + Xil_AssertNonvoid(Words != (u32)0); Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + Xil_AssertNonvoid(Addr != NULL); /* * variable initialization @@ -674,20 +609,14 @@ int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) * select the proper Subtest(s) */ - switch (Subtest) { - - case XIL_TESTMEM_ALLMEMTESTS: - /* this case executes all of the Subtests */ - /* fall through case statement */ - - case XIL_TESTMEM_INCREMENT: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { /* * Fill the memory with incrementing * values starting from 'FirtVal' */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Addr[I] = Val; + *(Addr+I) = Val; Val++; } /* @@ -702,115 +631,102 @@ int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) * Val */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; } Val++; } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 1 */ - - /* fall through case statement */ - - case XIL_TESTMEM_WALKONES: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { /* * set up to cycle through all possible initial * test Patterns for walking ones test */ - for (J = 0L; J < 8; J++) { + for (j = 0U; j < (u32)8; j++) { /* * Generate an initial value for walking ones test * to test for bad data bits */ - Val = 1 << J; + Val = (u8)((u32)1 << j); /* * START walking ones test * Write a one to each data bit indifferent locations */ - for (I = 0L; I < 8; I++) { + for (I = 0U; I < (u32)8; I++) { /* write memory location */ - Addr[I] = Val; - Val = (u8)RotateLeft(Val, 8); + *(Addr+I) = Val; + Val = (u8)RotateLeft(Val, 8U); } /* * Restore the reference 'Val' to the * initial value */ - Val = 1 << J; + Val = (u8)((u32)1 << j); /* Read the values from each location that was written */ - for (I = 0L; I < 8; I++) { + for (I = 0U; I < (u32)8; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; } - Val = (u8)RotateLeft(Val, 8); + Val = (u8)RotateLeft(Val, 8U); } } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 2 */ - /* fall through case statement */ - - case XIL_TESTMEM_WALKZEROS: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { /* * set up to cycle through all possible initial test * Patterns for walking zeros test */ - for (J = 0L; J < 8; J++) { + for (j = 0U; j < (u32)8; j++) { /* * Generate an initial value for walking ones test to test * for bad data bits */ - Val = ~(1 << J); + Val = ~(1U << j); /* * START walking zeros test * Write a one to each data bit indifferent locations */ - for (I = 0L; I < 8; I++) { + for (I = 0U; I < (u32)8; I++) { /* write memory location */ - Addr[I] = Val; - Val = ~((u8)RotateLeft(~Val, 8)); + *(Addr+I) = Val; + Val = ~((u8)RotateLeft(~Val, 8U)); } /* * Restore the reference 'Val' to the * initial value */ - Val = ~(1 << J); + Val = ~(1U << j); /* Read the values from each location that was written */ - for (I = 0L; I < 8; I++) { + for (I = 0U; I < (u32)8; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; } - Val = ~((u8)RotateLeft(~Val, 8)); + Val = ~((u8)RotateLeft(~Val, 8U)); } } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 3 */ - /* fall through case statement */ - - case XIL_TESTMEM_INVERSEADDR: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { /* Fill the memory with inverse of address */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Val = (u8) (~((u32) (&Addr[I]))); - Addr[I] = Val; + Val = (u8) (~((INTPTR) (&Addr[I]))); + *(Addr+I) = Val; } /* @@ -818,28 +734,25 @@ int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) * of tested memory */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* read memory location */ - Word = Addr[I]; - Val = (u8) (~((u32) (&Addr[I]))); - if ((Word ^ Val) != 0x00) { - return -1; + WordMem8 = *(Addr+I); + Val = (u8) (~((INTPTR) (&Addr[I]))); + if ((WordMem8 ^ Val) != 0x00U) { + Status = -1; + goto End_Label; } } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 4 */ - /* fall through case statement */ + } - case XIL_TESTMEM_FIXEDPATTERN: + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { /* * Generate an initial value for * memory testing */ - if (Pattern == 0) { - Val = 0xA5; + if (Pattern == (u8)0) { + Val = 0xA5U; } else { Val = Pattern; @@ -847,9 +760,9 @@ int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) /* * Fill the memory with fixed Pattern */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* write memory location */ - Addr[I] = Val; + *(Addr+I) = Val; } /* * Check every word within the words @@ -857,32 +770,18 @@ int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) * with the fixed Pattern */ - for (I = 0L; I < Words; I++) { + for (I = 0U; I < Words; I++) { /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; } } + } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - - /* end of case 5 */ - - /* this break is for the prior fall through case statements */ - - break; - - default: - return -1; - - } /* end of switch */ - - /* Successfully passed memory test ! */ - - return 0; +End_Label: + return Status; } @@ -909,27 +808,28 @@ static u32 RotateLeft(u32 Input, u8 Width) u32 ReturnVal; u32 WidthMask; u32 MsbMask; + u32 LocalInput = Input; /* * set up the WidthMask and the MsbMask */ - MsbMask = 1 << (Width - 1); + MsbMask = 1U << (Width - 1U); - WidthMask = (MsbMask << 1) - 1; + WidthMask = (MsbMask << (u32)1) - (u32)1; /* * set the Width of the Input to the correct width */ - Input = Input & WidthMask; + LocalInput = LocalInput & WidthMask; - Msb = Input & MsbMask; + Msb = LocalInput & MsbMask; - ReturnVal = Input << 1; + ReturnVal = LocalInput << 1U; - if (Msb != 0x00000000) { - ReturnVal = ReturnVal | 0x00000001; + if (Msb != 0x00000000U) { + ReturnVal = ReturnVal | (u32)0x00000001; } ReturnVal = ReturnVal & WidthMask; @@ -962,26 +862,26 @@ static u32 RotateRight(u32 Input, u8 Width) u32 ReturnVal; u32 WidthMask; u32 MsbMask; - + u32 LocalInput = Input; /* * set up the WidthMask and the MsbMask */ - MsbMask = 1 << (Width - 1); + MsbMask = 1U << (Width - 1U); - WidthMask = (MsbMask << 1) - 1; + WidthMask = (MsbMask << 1U) - 1U; /* * set the width of the input to the correct width */ - Input = Input & WidthMask; + LocalInput = LocalInput & WidthMask; - ReturnVal = Input >> 1; + ReturnVal = LocalInput >> 1U; - Lsb = Input & 0x00000001; + Lsb = LocalInput & 0x00000001U; - if (Lsb != 0x00000000) { + if (Lsb != 0x00000000U) { ReturnVal = ReturnVal | MsbMask; } diff --git a/lib/bsp/standalone/src/common/xil_testmem.h b/lib/bsp/standalone/src/common/xil_testmem.h old mode 100755 new mode 100644 index b172a7e0..2bdf296f --- a/lib/bsp/standalone/src/common/xil_testmem.h +++ b/lib/bsp/standalone/src/common/xil_testmem.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -127,7 +138,7 @@ extern "C" { /* xutil_memtest defines */ -#define XIL_TESTMEM_INIT_VALUE 1 +#define XIL_TESTMEM_INIT_VALUE 1U /** @name Memory subtests * @{ @@ -135,12 +146,12 @@ extern "C" { /** * See the detailed description of the subtests in the file description. */ -#define XIL_TESTMEM_ALLMEMTESTS 0 -#define XIL_TESTMEM_INCREMENT 1 -#define XIL_TESTMEM_WALKONES 2 -#define XIL_TESTMEM_WALKZEROS 3 -#define XIL_TESTMEM_INVERSEADDR 4 -#define XIL_TESTMEM_FIXEDPATTERN 5 +#define XIL_TESTMEM_ALLMEMTESTS 0x00U +#define XIL_TESTMEM_INCREMENT 0x01U +#define XIL_TESTMEM_WALKONES 0x02U +#define XIL_TESTMEM_WALKZEROS 0x03U +#define XIL_TESTMEM_INVERSEADDR 0x04U +#define XIL_TESTMEM_FIXEDPATTERN 0x05U #define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN /* @} */ @@ -151,9 +162,9 @@ extern "C" { /* xutil_testmem prototypes */ -extern int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest); -extern int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest); -extern int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest); +extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest); +extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest); +extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest); #ifdef __cplusplus } diff --git a/lib/bsp/standalone/src/common/xil_types.h b/lib/bsp/standalone/src/common/xil_types.h old mode 100755 new mode 100644 index a0965a24..046c3e18 --- a/lib/bsp/standalone/src/common/xil_types.h +++ b/lib/bsp/standalone/src/common/xil_types.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -44,7 +55,9 @@ * ----- ---- -------- ------------------------------------------------------- * 1.00a hbm 07/14/09 First release * 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros -* 4.2 srt 07/03/14 Use standard definitions from stdint.h +* 5.00 pkp 05/29/14 Made changes for 64 bit architecture +* srt 07/14/14 Use standard definitions from stdint.h and stddef.h +* Define LONG and ULONG datatypes and mask values * * ******************************************************************************/ @@ -58,19 +71,19 @@ /************************** Constant Definitions *****************************/ #ifndef TRUE -# define TRUE 1 +# define TRUE 1U #endif #ifndef FALSE -# define FALSE 0 +# define FALSE 0U #endif #ifndef NULL -#define NULL 0 +#define NULL 0U #endif -#define XIL_COMPONENT_IS_READY 0x11111111 /**< component has been initialized */ -#define XIL_COMPONENT_IS_STARTED 0x22222222 /**< component has been started */ +#define XIL_COMPONENT_IS_READY 0x11111111U /**< component has been initialized */ +#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< component has been started */ /** @name New types * New simple types. @@ -124,15 +137,27 @@ typedef struct /** * xbasic_types.h does not typedef s* or u64 */ -typedef uint64_t u64; +typedef char char8; typedef int8_t s8; typedef int16_t s16; typedef int32_t s32; typedef int64_t s64; +typedef uint64_t u64; +typedef int sint32; + typedef intptr_t INTPTR; typedef uintptr_t UINTPTR; -typedef ptrdiff_t PTRDIFF; +typedef ptrdiff_t PTRDIFF; + +#if !defined(LONG) || !defined(ULONG) +typedef long LONG; +typedef unsigned long ULONG; +#endif + +#define ULONG64_HI_MASK 0xFFFFFFFF00000000U +#define ULONG64_LO_MASK ~ULONG64_HI_MASK + #else #include #endif @@ -156,15 +181,15 @@ typedef void (*XExceptionHandler) (void *InstancePtr); /************************** Constant Definitions *****************************/ #ifndef TRUE -#define TRUE 1 +#define TRUE 1U #endif #ifndef FALSE -#define FALSE 0 +#define FALSE 0U #endif #ifndef NULL -#define NULL 0 +#define NULL 0U #endif #endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/common/xstatus.h b/lib/bsp/standalone/src/common/xstatus.h old mode 100755 new mode 100644 index 36ca9d19..30aeb98b --- a/lib/bsp/standalone/src/common/xstatus.h +++ b/lib/bsp/standalone/src/common/xstatus.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -416,7 +427,7 @@ extern "C" { /**************************** Type Definitions *******************************/ -typedef int XStatus; +typedef s32 XStatus; /***************** Macros (Inline Functions) Definitions *********************/ diff --git a/lib/bsp/standalone/src/cortexa53/gcc/Makefile b/lib/bsp/standalone/src/cortexa53/gcc/Makefile new file mode 100644 index 00000000..39631fac --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/Makefile @@ -0,0 +1,92 @@ +############################################################################### +# +# Copyright (C) 2014 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information of Xilinx, Inc. +# and is protected under U.S. and international copyright and other +# intellectual property laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any rights to the +# materials distributed herewith. Except as otherwise provided in a valid +# license issued to you by Xilinx, and to the maximum extent permitted by +# applicable law: +# (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +# XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +# OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +# NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +# and +# (2) Xilinx shall not be liable (whether in contract or tort, including +# negligence, or under any other theory of liability) for any loss or damage of +# any kind or nature related to, arising under or in connection with these +# materials, including for any direct, or any indirect, special, incidental, +# or consequential loss or damage (including loss of data, profits, goodwill, +# or any type of loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was reasonably foreseeable +# or Xilinx had been advised of the possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail-safe, or for use in +# any application requiring fail-safe performance, such as life-support or +# safety devices or systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any other applications +# that could lead to death, personal injury, or severe property or environmental +# damage (individually and collectively, "Critical Applications"). +# Customer assumes the sole risk and liability of any use of Xilinx products in +# Critical Applications, subject only to applicable laws and regulations +# governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +# AT ALL TIMES. +# +############################################################################### +include config.make + +AS=aarch64-none-elf-as +CC=aarch64-none-elf-gcc +AR=aarch64-none-elf-ar +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +LIB=libxil.a + +CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS)) +ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS)) + + +#The following flags are required for PEEP. We can remove them later +ECC_FLAGS += -march=armv8-a + + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +INCLUDEFILES=*.h + +libs: $(LIBS) + +standalone_libs: $(LIBSOURCES) + echo "Compiling standalone A53" + $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^ + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + +profile_libs: + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" libs + +.PHONY: include +include: standalone_includes profile_includes + +standalone_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +profile_includes: + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" include + +clean: + rm -rf ${OUTS} + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" clean diff --git a/lib/bsp/standalone/src/cortexa53/gcc/_exit.c b/lib/bsp/standalone/src/cortexa53/gcc/_exit.c new file mode 100644 index 00000000..b769c45b --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/_exit.c @@ -0,0 +1,56 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +/* _exit - Simple implementation. Does not return. +*/ +__attribute__((weak)) void _exit (sint32 status) +{ + (void)status; + while (1) + { + __asm__("wfi"); + } +} diff --git a/lib/bsp/standalone/src/cortexa53/gcc/_open.c b/lib/bsp/standalone/src/cortexa53/gcc/_open.c new file mode 100644 index 00000000..d7ff29ff --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/_open.c @@ -0,0 +1,64 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode); +} +#endif + +/* + * _open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + */ +__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode) +{ + (void *)buf; + (void)flags; + (void)mode; + errno = EIO; + return (-1); +} diff --git a/lib/bsp/standalone/src/cortexa53/gcc/_sbrk.c b/lib/bsp/standalone/src/cortexa53/gcc/_sbrk.c new file mode 100644 index 00000000..f22c79c9 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/_sbrk.c @@ -0,0 +1,81 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +extern u8 _heap_start[]; +extern u8 _heap_end[]; + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) caddr_t _sbrk ( s32 incr ); +} +#endif + +__attribute__((weak)) caddr_t _sbrk ( s32 incr ) +{ + static u8 *heap = NULL; + u8 *prev_heap; + static u8 *HeapEndPtr = (u8 *)&_heap_end; + caddr_t Status; + + if (heap == NULL) { + heap = (u8 *)&_heap_start; + } + prev_heap = heap; + + heap += incr; + + if (heap > HeapEndPtr){ + Status = (caddr_t) -1; + } + else if (prev_heap != NULL) { + Status = (caddr_t) ((void *)prev_heap); + } + else { + Status = (caddr_t) -1; + } + + return Status; +} diff --git a/lib/bsp/standalone/src/cortexa53/gcc/abort.c b/lib/bsp/standalone/src/cortexa53/gcc/abort.c new file mode 100644 index 00000000..06f56828 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/abort.c @@ -0,0 +1,53 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include +#include + +/* + * abort -- go out via exit... + */ +__attribute__((weak)) void abort(void) +{ + _exit(1); +} diff --git a/lib/bsp/standalone/src/cortexa53/gcc/asm_vectors.S b/lib/bsp/standalone/src/cortexa53/gcc/asm_vectors.S new file mode 100644 index 00000000..ef210f5a --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/asm_vectors.S @@ -0,0 +1,219 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file asm_vectors.s +* +* This file contains the initial vector table for the Cortex A53 processor +* Currently NEON registers are not saved on stack if interrupt is taken. +* It will be implemented. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00	pkp	5/21/14 Initial version
+*
+* +* @note +* +* None. +* +******************************************************************************/ + + + +.org 0 +.text + +.globl _boot +.globl _vector_table + +.globl FIQInterrupt +.globl IRQInterrupt +.globl SErrorInterrupt +.globl SynchronousInterrupt + + +.org 0 + +.section .vectors, "a" + +_vector_table: + +.set VBAR, _vector_table +.org VBAR + b _boot +.org (VBAR + 0x200) + b SynchronousInterruptHandler + +.org (VBAR + 0x280) + b IRQInterruptHandler + +.org (VBAR + 0x300) + b FIQInterruptHandler + +.org (VBAR + 0x380) + b SErrorInterruptHandler + + +SynchronousInterruptHandler: + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! + + bl SynchronousInterrupt + + ldp X29,X30, [sp], #0x10 + ldp X18,X19, [sp], #0x10 + ldp X16,X17, [sp], #0x10 + ldp X14,X15, [sp], #0x10 + ldp X12,X13, [sp], #0x10 + ldp X10,X11, [sp], #0x10 + ldp X8,X9, [sp], #0x10 + ldp X6,X7, [sp], #0x10 + ldp X4,X5, [sp], #0x10 + ldp X2,X3, [sp], #0x10 + ldp X0,X1, [sp], #0x10 + + eret + +IRQInterruptHandler: + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! + + bl IRQInterrupt + + ldp X29,X30, [sp], #0x10 + ldp X18,X19, [sp], #0x10 + ldp X16,X17, [sp], #0x10 + ldp X14,X15, [sp], #0x10 + ldp X12,X13, [sp], #0x10 + ldp X10,X11, [sp], #0x10 + ldp X8,X9, [sp], #0x10 + ldp X6,X7, [sp], #0x10 + ldp X4,X5, [sp], #0x10 + ldp X2,X3, [sp], #0x10 + ldp X0,X1, [sp], #0x10 + + eret + +FIQInterruptHandler: + + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! + + bl FIQInterrupt + + ldp X29,X30, [sp], #0x10 + ldp X18,X19, [sp], #0x10 + ldp X16,X17, [sp], #0x10 + ldp X14,X15, [sp], #0x10 + ldp X12,X13, [sp], #0x10 + ldp X10,X11, [sp], #0x10 + ldp X8,X9, [sp], #0x10 + ldp X6,X7, [sp], #0x10 + ldp X4,X5, [sp], #0x10 + ldp X2,X3, [sp], #0x10 + ldp X0,X1, [sp], #0x10 + + eret + +SErrorInterruptHandler: + + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! + + bl SErrorInterrupt + + ldp X29,X30, [sp], #0x10 + ldp X18,X19, [sp], #0x10 + ldp X16,X17, [sp], #0x10 + ldp X14,X15, [sp], #0x10 + ldp X12,X13, [sp], #0x10 + ldp X10,X11, [sp], #0x10 + ldp X8,X9, [sp], #0x10 + ldp X6,X7, [sp], #0x10 + ldp X4,X5, [sp], #0x10 + ldp X2,X3, [sp], #0x10 + ldp X0,X1, [sp], #0x10 + + eret + +.end diff --git a/lib/bsp/standalone/src/cortexa53/gcc/boot.S b/lib/bsp/standalone/src/cortexa53/gcc/boot.S new file mode 100644 index 00000000..50f05051 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/boot.S @@ -0,0 +1,275 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file boot.S +* +* This file contains the initial startup code for the Cortex A53 processor +* Currently the processor starts at EL3 and boot code, startup and main +* code will run on secure EL3. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp	5/21/14 Initial version
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+
+.globl MMUTableL0
+.globl MMUTableL1
+.globl MMUTableL2
+.global _prestart
+.global _boot
+
+.global __el3_stack
+.global __el2_stack
+.global __el1_stack
+.global __el0_stack
+.global _vector_table
+
+
+.set EL3_stack,		__el3_stack
+.set EL2_stack,		__el2_stack
+.set EL1_stack,		__el1_stack
+.set EL0_stack,		__el0_stack
+
+.set TT_S1_FAULT,	0x0
+.set TT_S1_TABLE,	0x3
+
+.set L0Table,	MMUTableL0
+.set L1Table,	MMUTableL1
+.set L2Table,	MMUTableL2
+.set vector_base,	_vector_table
+
+.section .boot,"ax"
+
+
+/* this initializes the various processor modes */
+
+_prestart:
+_boot:
+	mov      x0, #0
+	mov      x1, #0
+	mov      x2, #0
+	mov      x3, #0
+	mov      x4, #0
+	mov      x5, #0
+	mov      x6, #0
+	mov      x7, #0
+	mov      x8, #0
+	mov      x9, #0
+	mov      x10, #0
+	mov      x11, #0
+	mov      x12, #0
+	mov      x13, #0
+	mov      x14, #0
+	mov      x15, #0
+	mov      x16, #0
+	mov      x17, #0
+	mov      x18, #0
+	mov      x19, #0
+	mov      x20, #0
+	mov      x21, #0
+	mov      x22, #0
+	mov      x23, #0
+	mov      x24, #0
+	mov      x25, #0
+	mov      x26, #0
+	mov      x27, #0
+	mov      x28, #0
+	mov      x29, #0
+	mov      x30, #0
+#if 0 //dont put other a53 cpus in wfi
+   //Which core am I
+   // ----------------
+	mrs      x0, MPIDR_EL1
+	and      x0, x0, #0xFF                     //Mask off to leave Aff0
+	cbz      x0, OKToRun                          //If core 0, run the primary init code
+EndlessLoop0:
+	wfi
+	b        EndlessLoop0
+#endif
+OKToRun:
+
+	/*Set vector table base address*/
+	ldr	x1, =vector_base
+	msr	VBAR_EL3,x1
+
+	/*Define stack pointer for current exception level*/
+	ldr	 x2,=EL3_stack
+	mov	 sp,x2
+
+
+	/* Disable trapping of CPTR_EL3 accesses or use of Adv.SIMD/FPU*/
+	mov      x0, #0                 // Clear all trap bits
+	msr      CPTR_EL3, x0
+
+
+	/* Configure SCR_EL3 */
+	mov      w1, #0              	//; Initial value of register is unknown
+	orr      w1, w1, #(1 << 11)  	//; Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1)
+	orr      w1, w1, #(1 << 10)  	//; Set RW bit (EL1 is AArch64, as this is the Secure world)
+	orr      w1, w1, #(1 << 3)   	//; Set EA bit (SError routed to EL3)
+	orr      w1, w1, #(1 << 2)   	//; Set FIQ bit (FIQs routed to EL3)
+	orr      w1, w1, #(1 << 1)   	//; Set IRQ bit (IRQs routed to EL3)
+	msr      SCR_EL3, x1
+
+	/*Enable ECC protection*/
+	mrs	x0, S3_1_C11_C0_2  	// register L2CTLR_EL1
+	orr	x0, x0, #(1<<22)
+	msr	S3_1_C11_C0_2, x0
+
+	/*configure cpu auxiliary control register EL1 */
+	ldr	x0,=0x80CA000 		// L1 Data prefetch control - 5, Enable device split throttle, 2 independent data prefetch streams
+	msr	S3_1_C15_C2_0, x0 	//CPUACTLR_EL1
+
+
+	/*Enable hardware coherency between cores*/
+	mrs      x0, S3_1_c15_c2_1  	//Read EL1 CPU Extended Control Register
+	orr      x0, x0, #(1 << 6)  	//Set the SMPEN bit
+	msr      S3_1_c15_c2_1, x0  	//Write EL1 CPU Extended Control Register
+	isb
+
+	tlbi 	ALLE3
+	ic      IALLU                  	//; Invalidate I cache to PoU
+	bl 	invalidate_dcaches
+	dsb	 sy
+	isb
+
+	ldr      x1, =L0Table 		//; Get address of level 0 for TTBR0_EL1
+	msr      TTBR0_EL3, x1		//; Set TTBR0_EL3 (NOTE: There is no TTBR1 at EL1)
+
+
+	/**********************************************
+	* Set up memory attributes
+	* This equates to:
+	* 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
+	* 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
+	* 2 = b00000000 = Device-nGnRnE
+	**********************************************/
+	ldr      x1, =0x000000000000FF44
+	msr      MAIR_EL3, x1
+
+        /**********************************************
+        * Set up TCR_EL1
+        * ---------------
+        ***************************************************/
+        ldr     x1,=0x80803518  /*40 bit*/
+        msr     TCR_EL3, x1
+        isb
+
+	/* Configure SCTLR_EL3 */
+	mov      x1, #0                //Most of the SCTLR_EL3 bits are unknown at reset
+	orr      x1, x1, #(1 << 12)	//Enable I cache
+	orr      x1, x1, #(1 << 3)	//Enable SP alignment check
+	orr      x1, x1, #(1 << 2)	//Enable caches
+	orr      x1, x1, #(1 << 1)	//Enable alignment
+	orr      x1, x1, #(1 << 0)	//Enable MMU
+	msr      SCTLR_EL3, x1
+	dsb	 sy
+	isb
+
+	bl 	 _startup		//jump to start
+
+loop:	b	loop
+
+
+invalidate_dcaches:
+
+	dmb     ISH
+	mrs     x0, CLIDR_EL1          //; x0 = CLIDR
+	ubfx    w2, w0, #24, #3        //; w2 = CLIDR.LoC
+	cmp     w2, #0                 //; LoC is 0?
+	b.eq    invalidateCaches_end   //; No cleaning required and enable MMU
+	mov     w1, #0                 //; w1 = level iterator
+
+invalidateCaches_flush_level:
+	add     w3, w1, w1, lsl #1     //; w3 = w1 * 3 (right-shift for cache type)
+	lsr     w3, w0, w3             //; w3 = w0 >> w3
+	ubfx    w3, w3, #0, #3         //; w3 = cache type of this level
+	cmp     w3, #2                 //; No cache at this level?
+	b.lt    invalidateCaches_next_level
+
+	lsl     w4, w1, #1
+	msr     CSSELR_EL1, x4         //; Select current cache level in CSSELR
+	isb                            //; ISB required to reflect new CSIDR
+	mrs     x4, CCSIDR_EL1         //; w4 = CSIDR
+
+	ubfx    w3, w4, #0, #3
+	add    	w3, w3, #2             //; w3 = log2(line size)
+	ubfx    w5, w4, #13, #15
+	ubfx    w4, w4, #3, #10        //; w4 = Way number
+	clz     w6, w4                 //; w6 = 32 - log2(number of ways)
+
+invalidateCaches_flush_set:
+	mov     w8, w4                 //; w8 = Way number
+invalidateCaches_flush_way:
+	lsl     w7, w1, #1             //; Fill level field
+	lsl     w9, w5, w3
+	orr     w7, w7, w9             //; Fill index field
+	lsl     w9, w8, w6
+	orr     w7, w7, w9             //; Fill way field
+	dc      CISW, x7               //; Invalidate by set/way to point of coherency
+	subs    w8, w8, #1             //; Decrement way
+	b.ge    invalidateCaches_flush_way
+	subs    w5, w5, #1             //; Descrement set
+	b.ge    invalidateCaches_flush_set
+
+invalidateCaches_next_level:
+	add     w1, w1, #1             //; Next level
+	cmp     w2, w1
+	b.gt    invalidateCaches_flush_level
+
+invalidateCaches_end:
+	ret
+
+.end
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/close.c b/lib/bsp/standalone/src/cortexa53/gcc/close.c
new file mode 100644
index 00000000..1c29fdc9
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/close.c
@@ -0,0 +1,58 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _close(s32 fd);
+}
+#endif
+
+/*
+ * close -- We don't need to do anything, but pretend we did.
+ */
+
+__attribute__((weak)) s32 _close(s32 fd)
+{
+  (void)fd;
+  return (0);
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/errno.c b/lib/bsp/standalone/src/cortexa53/gcc/errno.c
new file mode 100644
index 00000000..fb28cf51
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/errno.c
@@ -0,0 +1,62 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+/* The errno variable is stored in the reentrancy structure.  This
+   function returns its address for use by the macro errno defined in
+   errno.h.  */
+
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 * __errno (void);
+}
+#endif
+
+__attribute__((weak)) sint32 *
+__errno (void)
+{
+  return &_REENT->_errno;
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/fcntl.c b/lib/bsp/standalone/src/cortexa53/gcc/fcntl.c
new file mode 100644
index 00000000..70e5fcfa
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/fcntl.c
@@ -0,0 +1,57 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+/*
+ * fcntl -- Manipulate a file descriptor.
+ *          We don't have a filesystem, so we do nothing.
+ */
+__attribute__((weak)) s32 fcntl (s32 fd, s32 cmd, s32 arg)
+{
+  (void)fd;
+  (void)cmd;
+  (void)arg;
+  return 0;
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/fstat.c b/lib/bsp/standalone/src/cortexa53/gcc/fstat.c
new file mode 100644
index 00000000..44a19c53
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/fstat.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
+}
+#endif
+/*
+ * fstat -- Since we have no file system, we just return an error.
+ */
+__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
+{
+  (void)fd;
+  buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
+
+  return (0);
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/getpid.c b/lib/bsp/standalone/src/cortexa53/gcc/getpid.c
new file mode 100644
index 00000000..10d1c3ae
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/getpid.c
@@ -0,0 +1,62 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include "xil_types.h"
+/*
+ * getpid -- only one process, so just return 1.
+ */
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _getpid(void);
+}
+#endif
+
+__attribute__((weak)) s32 getpid(void)
+{
+  return 1;
+}
+
+__attribute__((weak)) s32 _getpid(void)
+{
+  return 1;
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/initialise_monitor_handles.c b/lib/bsp/standalone/src/cortexa53/gcc/initialise_monitor_handles.c
new file mode 100644
index 00000000..6c53d8a9
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/initialise_monitor_handles.c
@@ -0,0 +1,63 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file initialise_monitor_handles.c
+*
+* Contains blank function to avoid compilation error
+*
+* @note
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 

+******************************************************************************/
+__attribute__((weak)) void initialise_monitor_handles(){
+
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/isatty.c b/lib/bsp/standalone/src/cortexa53/gcc/isatty.c
new file mode 100644
index 00000000..b1be3e11
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/isatty.c
@@ -0,0 +1,67 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 _isatty(sint32 fd);
+}
+#endif
+
+/*
+ * isatty -- returns 1 if connected to a terminal device,
+ *           returns 0 if not. Since we're hooked up to a
+ *           serial port, we'll say yes _AND return a 1.
+ */
+__attribute__((weak)) sint32 isatty(sint32 fd)
+{
+  (void)fd;
+  return (1);
+}
+
+__attribute__((weak)) sint32 _isatty(sint32 fd)
+{
+  (void)fd;
+  return (1);
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/kill.c b/lib/bsp/standalone/src/cortexa53/gcc/kill.c
new file mode 100644
index 00000000..62b303da
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/kill.c
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _kill(s32 pid, s32 sig);
+}
+#endif
+
+/*
+ * kill -- go out via exit...
+ */
+
+__attribute__((weak)) s32 kill(s32 pid, s32 sig)
+{
+  if(pid == 1) {
+    _exit(sig);
+  }
+  return 0;
+}
+
+__attribute__((weak)) s32 _kill(s32 pid, s32 sig)
+{
+  if(pid == 1) {
+    _exit(sig);
+  }
+  return 0;
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/lseek.c b/lib/bsp/standalone/src/cortexa53/gcc/lseek.c
new file mode 100644
index 00000000..4aca2718
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/lseek.c
@@ -0,0 +1,72 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
+}
+#endif
+/*
+ * lseek --  Since a serial port is non-seekable, we return an error.
+ */
+__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
+
+__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/memfun.c b/lib/bsp/standalone/src/cortexa53/gcc/memfun.c
new file mode 100644
index 00000000..eeace2ee
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/memfun.c
@@ -0,0 +1,326 @@
+/******************************************************************************
+*
+* Permission to use, copy, modify, and distribute this software for any
+* purpose without fee is hereby granted, provided that this entire notice is
+* included in all copies of any software which is or includes a copy or
+* modification of this software and in all copies of the supporting
+* documentation for such software.
+*
+* THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR
+* IMPLIED WARRANTY. IN PARTICULAR, NEITHER THE AUTHOR NOR AT&T
+* MAKES ANY REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING
+* THE MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR
+* PURPOSE.
+*
+******************************************************************************/
+/*
+FUNCTION
+	<>---set an area of memory
+
+INDEX
+	memset
+
+ANSI_SYNOPSIS
+	#include 
+	void *memset(void *<[dst]>, int <[c]>, size_t <[length]>);
+
+TRAD_SYNOPSIS
+	#include 
+	void *memset(<[dst]>, <[c]>, <[length]>)
+	void *<[dst]>;
+	int <[c]>;
+	size_t <[length]>;
+
+DESCRIPTION
+	This function converts the argument <[c]> into an unsigned
+	char and fills the first <[length]> characters of the array
+	pointed to by <[dst]> to the value.
+
+RETURNS
+	<> returns the value of <[dst]>.
+
+PORTABILITY
+<> is ANSI C.
+
+    <> requires no supporting OS subroutines.
+
+QUICKREF
+	memset ansi pure
+*/
+
+#include 
+#include <_ansi.h>
+
+#define LBLOCKSIZE (sizeof(long))
+#define UNALIGNED_S(X)   ((long)X & (LBLOCKSIZE - 1))
+#define TOO_SMALL(LEN) ((LEN) < LBLOCKSIZE)
+
+/* Nonzero if either X or Y is not aligned on a "long" boundary.  */
+#define UNALIGNED(X, Y) \
+  (((long)X & (sizeof (long) - 1)) | ((long)Y & (sizeof (long) - 1)))
+
+/* How many bytes are copied each iteration of the 4X unrolled loop.  */
+#define BIGBLOCKSIZE    (sizeof (long) << 2)
+
+/* How many bytes are copied each iteration of the word copy loop.  */
+#define LITTLEBLOCKSIZE (sizeof (long))
+
+
+_PTR
+_DEFUN (memset, (m, c, n),
+	_PTR m _AND
+	int c _AND
+	size_t n)
+{
+  char *s = (char *) m;
+
+#if !defined(PREFER_SIZE_OVER_SPEED) && !defined(__OPTIMIZE_SIZE__)
+  int i;
+  unsigned long buffer;
+  unsigned long *aligned_addr;
+  unsigned int d = c & 0xff;	/* To avoid sign extension, copy C to an
+				   unsigned variable.  */
+
+  while (UNALIGNED_S (s))
+    {
+      if (n--)
+        *s++ = (char) c;
+      else
+        return m;
+    }
+
+  if (!TOO_SMALL (n))
+    {
+      /* If we get this far, we know that n is large and s is word-aligned. */
+      aligned_addr = (unsigned long *) s;
+
+      /* Store D into each char sized location in BUFFER so that
+         we can set large blocks quickly.  */
+      buffer = (d << 8) | d;
+      buffer |= (buffer << 16);
+      for (i = 32; i < LBLOCKSIZE * 8; i <<= 1)
+        buffer = (buffer << i) | buffer;
+
+      /* Unroll the loop.  */
+      while (n >= LBLOCKSIZE*4)
+        {
+          *aligned_addr++ = buffer;
+          *aligned_addr++ = buffer;
+          *aligned_addr++ = buffer;
+          *aligned_addr++ = buffer;
+          n -= 4*LBLOCKSIZE;
+        }
+
+      while (n >= LBLOCKSIZE)
+        {
+          *aligned_addr++ = buffer;
+          n -= LBLOCKSIZE;
+        }
+      /* Pick up the remainder with a bytewise loop.  */
+      s = (char*)aligned_addr;
+    }
+
+#endif /* not PREFER_SIZE_OVER_SPEED */
+
+  while (n--)
+    *s++ = (char) c;
+
+  return m;
+}
+
+/*
+FUNCTION
+	<>---compare two memory areas
+
+INDEX
+	memcmp
+
+ANSI_SYNOPSIS
+	#include 
+	int memcmp(const void *<[s1]>, const void *<[s2]>, size_t <[n]>);
+
+TRAD_SYNOPSIS
+	#include 
+	int memcmp(<[s1]>, <[s2]>, <[n]>)
+	void *<[s1]>;
+	void *<[s2]>;
+	size_t <[n]>;
+
+DESCRIPTION
+	This function compares not more than <[n]> characters of the
+	object pointed to by <[s1]> with the object pointed to by <[s2]>.
+
+
+RETURNS
+	The function returns an integer greater than, equal to or
+	less than zero 	according to whether the object pointed to by
+	<[s1]> is greater than, equal to or less than the object
+	pointed to by <[s2]>.
+
+PORTABILITY
+<> is ANSI C.
+
+<> requires no supporting OS subroutines.
+
+QUICKREF
+	memcmp ansi pure
+*/
+
+
+
+int
+_DEFUN (memcmp, (m1, m2, n),
+	_CONST _PTR m1 _AND
+	_CONST _PTR m2 _AND
+	size_t n)
+{
+#if defined(PREFER_SIZE_OVER_SPEED) || defined(__OPTIMIZE_SIZE__)
+  unsigned char *s1 = (unsigned char *) m1;
+  unsigned char *s2 = (unsigned char *) m2;
+
+  while (n--)
+    {
+      if (*s1 != *s2)
+	{
+	  return *s1 - *s2;
+	}
+      s1++;
+      s2++;
+    }
+  return 0;
+#else
+  unsigned char *s1 = (unsigned char *) m1;
+  unsigned char *s2 = (unsigned char *) m2;
+  unsigned long *a1;
+  unsigned long *a2;
+
+  /* If the size is too small, or either pointer is unaligned,
+     then we punt to the byte compare loop.  Hopefully this will
+     not turn up in inner loops.  */
+  if (!TOO_SMALL(n) && !UNALIGNED(s1,s2))
+    {
+      /* Otherwise, load and compare the blocks of memory one
+         word at a time.*/
+      a1 = (unsigned long*) s1;
+      a2 = (unsigned long*) s2;
+      while (n >= LBLOCKSIZE)
+        {
+			if (*a1 != *a2)
+				break;
+			a1++;
+			a2++;
+			n -= LBLOCKSIZE;
+        }
+      /* check m mod LBLOCKSIZE remaining characters */
+
+      s1 = (unsigned char*)a1;
+      s2 = (unsigned char*)a2;
+    }
+
+  while (n--)
+    {
+		if (*s1 != *s2)
+			return *s1 - *s2;
+		s1++;
+		s2++;
+    }
+
+  return 0;
+#endif /* not PREFER_SIZE_OVER_SPEED */
+}
+
+/*
+FUNCTION
+        <>---copy memory regions
+
+ANSI_SYNOPSIS
+        #include 
+        void* memcpy(void *<[out]>, const void *<[in]>, size_t <[n]>);
+
+TRAD_SYNOPSIS
+        #include 
+        void *memcpy(<[out]>, <[in]>, <[n]>
+        void *<[out]>;
+        void *<[in]>;
+        size_t <[n]>;
+
+DESCRIPTION
+        This function copies <[n]> bytes from the memory region
+        pointed to by <[in]> to the memory region pointed to by
+        <[out]>.
+
+        If the regions overlap, the behavior is undefined.
+
+RETURNS
+        <> returns a pointer to the first byte of the <[out]>
+        region.
+
+PORTABILITY
+<> is ANSI C.
+
+<> requires no supporting OS subroutines.
+
+QUICKREF
+        memcpy ansi pure
+	*/
+
+
+_PTR
+_DEFUN (memcpy, (dst0, src0, len0),
+	_PTR dst0 _AND
+	_CONST _PTR src0 _AND
+	size_t len0)
+{
+#if defined(PREFER_SIZE_OVER_SPEED) || defined(__OPTIMIZE_SIZE__)
+  char *dst = (char *) dst0;
+  char *src = (char *) src0;
+
+  _PTR save = dst0;
+
+  while (len0--)
+    {
+      *dst++ = *src++;
+    }
+
+  return save;
+#else
+  char *dst = dst0;
+  _CONST char *src = src0;
+  long *aligned_dst;
+  _CONST long *aligned_src;
+
+  /* If the size is small, or either SRC or DST is unaligned,
+     then punt into the byte copy loop.  This should be rare.  */
+  if (!TOO_SMALL(len0) && !UNALIGNED (src, dst))
+    {
+      aligned_dst = (long*)dst;
+      aligned_src = (long*)src;
+
+      /* Copy 4X long words at a time if possible.  */
+      while (len0 >= BIGBLOCKSIZE)
+        {
+          *aligned_dst++ = *aligned_src++;
+          *aligned_dst++ = *aligned_src++;
+          *aligned_dst++ = *aligned_src++;
+          *aligned_dst++ = *aligned_src++;
+          len0 -= BIGBLOCKSIZE;
+        }
+
+      /* Copy one long word at a time if possible.  */
+      while (len0 >= LITTLEBLOCKSIZE)
+        {
+          *aligned_dst++ = *aligned_src++;
+          len0 -= LITTLEBLOCKSIZE;
+        }
+
+       /* Pick up any residual with a byte copier.  */
+      dst = (char*)aligned_dst;
+      src = (char*)aligned_src;
+    }
+
+  while (len0--)
+    *dst++ = *src++;
+
+  return dst0;
+#endif /* not PREFER_SIZE_OVER_SPEED */
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/open.c b/lib/bsp/standalone/src/cortexa53/gcc/open.c
new file mode 100644
index 00000000..3056fa97
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/open.c
@@ -0,0 +1,63 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 open(const char8 *buf, s32 flags, s32 mode);
+}
+#endif
+/*
+ * open -- open a file descriptor. We don't have a filesystem, so
+ *         we return an error.
+ */
+__attribute__((weak)) s32 open(const char8 *buf, s32 flags, s32 mode)
+{
+  (void *)buf;
+  (void)flags;
+  (void)mode;
+  errno = EIO;
+  return (-1);
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/read.c b/lib/bsp/standalone/src/cortexa53/gcc/read.c
new file mode 100644
index 00000000..66045a43
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/read.c
@@ -0,0 +1,122 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+/* read.c -- read bytes from a input device.
+ */
+
+#include "xparameters.h"
+#include "xil_printf.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
+}
+#endif
+
+/*
+ * read  -- read bytes from the serial port. Ignore fd, since
+ *          we only have stdin.
+ */
+__attribute__((weak)) s32
+read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    *LocalBuf = inbyte();
+	    if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
+	        break;
+		}
+	}
+	if(LocalBuf != NULL) {
+	LocalBuf -= i;
+	}
+  }
+
+  return (i + 1);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+__attribute__((weak)) s32
+_read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    *LocalBuf = inbyte();
+	    if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
+	        break;
+		}
+	}
+	if(LocalBuf != NULL) {
+	LocalBuf -= i;
+	}
+  }
+
+  return (i + 1);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/sbrk.c b/lib/bsp/standalone/src/cortexa53/gcc/sbrk.c
new file mode 100644
index 00000000..3002b8fd
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/sbrk.c
@@ -0,0 +1,76 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) char8 *sbrk (s32 nbytes);
+}
+#endif
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+extern char8 HeapBase[];
+extern char8 HeapLimit[];
+
+
+
+__attribute__((weak)) char8 *sbrk (s32 nbytes)
+{
+  char8 *base;
+  static char8 *heap_ptr = HeapBase;
+
+  base = heap_ptr;
+  if(heap_ptr != NULL) {
+	heap_ptr += nbytes;
+  }
+
+/*  if (heap_ptr <= ((char8 *)&_heap_end + 1)) */
+  if (heap_ptr <= ((char8 *)&HeapLimit + 1)) {
+    return base;
+  }	else {
+    errno = ENOMEM;
+    return ((char8 *)-1);
+  }
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/translation_table.s b/lib/bsp/standalone/src/cortexa53/gcc/translation_table.s
new file mode 100644
index 00000000..9779b967
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/translation_table.s
@@ -0,0 +1,181 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file translation_table.s
+*
+* This file contains the initialization for the MMU table in RAM
+* needed by the Cortex A53 processor
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  05/21/14 Initial version
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+	.globl  MMUTableL0
+	.globl  MMUTableL1
+	.globl  MMUTableL2
+
+	.set reserved,	0x0 					/* Fault*/
+	.set Memory,	0x405 | (3 << 8) | (0x0)		/* normal writeback write allocate inner shared read write */
+	.set Device,	0x409 | (1 << 53)| (1 << 54) |(0x0)	/* strongly ordered read write non executable*/
+	.section .mmu_tbl0,"a"
+
+MMUTableL0:
+
+.set SECT, MMUTableL1
+.8byte	SECT + 0x3
+.set SECT, MMUTableL1+0x1000
+.8byte	SECT + 0x3
+
+	.section .mmu_tbl1,"a"
+
+MMUTableL1:
+
+.set SECT, MMUTableL2			/*1GB DDR*/
+.8byte	SECT + 0x3
+
+.rept	0x3				/*1GB DDR, 1GB PL, 2GB other devices n memory*/
+.set SECT, SECT + 0x1000
+.8byte	SECT + 0x3
+.endr
+
+.set SECT,0x100000000
+.rept	0xC
+.8byte	SECT + reserved
+.set SECT, SECT + 0x40000000	/*12GB Reserved*/
+.endr
+
+.rept	0x10
+.8byte	SECT + Device
+.set SECT, SECT + 0x40000000	/*8GB PL, 8GB PCIe*/
+
+.endr
+
+.rept	0x20
+.8byte	SECT + Memory
+
+.set SECT, SECT + 0x40000000	/*32GB DDR*/
+.endr
+
+
+.rept	0xC0
+.8byte	SECT + Device
+.set SECT, SECT + 0x40000000	/*192GB PL*/
+.endr
+
+
+.rept	0x100
+.8byte	SECT + Device
+.set SECT, SECT + 0x40000000	/*256GB PL/PCIe*/
+.endr
+
+
+.rept	0x200
+.8byte	SECT + Device
+.set SECT, SECT + 0x40000000	/*512GB PL/DDR*/
+.endr
+
+
+.section .mmu_tbl2,"a"
+
+MMUTableL2:
+
+.set SECT, 0
+
+.rept	0x0400			/*2GB DDR */
+.8byte	SECT + Memory
+.set	SECT, SECT+0x200000
+.endr
+
+.rept	0x0200			/*1GB lower PL*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x0100			/*512MB QSPI*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x080			/*256MB lower PCIe*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x040			/*128MB Reserved*/
+.8byte	SECT + reserved
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x8			/*16MB coresight*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x8			/*16MB RPU low latency port*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+
+.rept	0x022			/*68MB Device*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x8			/*8MB FPS*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+
+.rept	0x4			/*16MB LPS*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+
+.8byte	SECT + Device 		/*2MB PMU/CSU */
+.set	SECT, SECT+0x200000
+.8byte  SECT + Memory		/*2MB OCM/TCM*/
+.end
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/unlink.c b/lib/bsp/standalone/src/cortexa53/gcc/unlink.c
new file mode 100644
index 00000000..b212240e
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/unlink.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 unlink(char8 *path);
+}
+#endif
+/*
+ * unlink -- since we have no file system,
+ *           we just return an error.
+ */
+__attribute__((weak)) s32 unlink(char8 *path)
+{
+  (void *)path;
+  errno = EIO;
+  return (-1);
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/write.c b/lib/bsp/standalone/src/cortexa53/gcc/write.c
new file mode 100644
index 00000000..59a97ad4
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/write.c
@@ -0,0 +1,122 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+/* write.c -- write bytes to an output device.
+ */
+
+#include "xparameters.h"
+#include "xil_printf.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _write (s32 fd, char8* buf, s32 nbytes);
+}
+#endif
+
+/*
+ * write -- write bytes to the serial port. Ignore fd, since
+ *          stdout and stderr are the same. Since we have no filesystem,
+ *          open will only return an error.
+ */
+__attribute__((weak)) s32
+write (s32 fd, char8* buf, s32 nbytes)
+
+{
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+__attribute__((weak)) s32
+_write (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/xil-crt0.S b/lib/bsp/standalone/src/cortexa53/gcc/xil-crt0.S
new file mode 100644
index 00000000..d0c8287c
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/xil-crt0.S
@@ -0,0 +1,132 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil-crt0.S
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00	pkp  05/21/14 Initial version
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+.extern XSmc_NorInit
+.extern XSmc_SramInit
+
+	.file	"xil-crt0.S"
+	.section ".got2","aw"
+	.align	2
+
+	.text
+.Lsbss_start:
+	.long	__sbss_start
+
+.Lsbss_end:
+	.long	__sbss_end
+
+.Lbss_start:
+	.long	__bss_start__
+
+.Lbss_end:
+	.long	__bss_end__
+
+
+
+	.globl	_startup
+_startup:
+
+	mov	x0, #0
+
+	/* clear sbss */
+	ldr 	w1,.Lsbss_start		/* calculate beginning of the SBSS */
+	ldr	w2,.Lsbss_end		/* calculate end of the SBSS */
+	uxtw	x1, w1			/*zero extension to w1 register*/
+	uxtw	x2, w2			/*zero extension to w2 register*/
+
+.Lloop_sbss:
+	cmp	x1,x2
+	bge	.Lenclsbss		/* If no SBSS, no clearing required */
+	str	x0, [x1], #8
+	b	.Lloop_sbss
+
+.Lenclsbss:
+	/* clear bss */
+	ldr	w1,.Lbss_start		/* calculate beginning of the BSS */
+	ldr	w2,.Lbss_end		/* calculate end of the BSS */
+	uxtw	x1, w1			/*zero extension to w1 register*/
+	uxtw	x2, w2			/*zero extension to w2 register*/
+
+.Lloop_bss:
+	cmp	x1,x2
+	bge	.Lenclbss		/* If no BSS, no clearing required */
+	str	x0, [x1], #8
+	b	.Lloop_bss
+
+.Lenclbss:
+
+	bl 	Init_Uart		/* Initialize UART */
+
+
+	/* make sure argc and argv are valid */
+	mov	x0, #0
+	mov	x1, #0
+
+	bl	main			/* Jump to main C code */
+
+
+
+	bl	_exit
+
+.Lexit:	/* should never get here */
+	b .Lexit
+
+.Lstart:
+	.size	_startup,.Lstart-_startup
\ No newline at end of file
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/xpseudo_asm_gcc.h b/lib/bsp/standalone/src/cortexa53/gcc/xpseudo_asm_gcc.h
new file mode 100644
index 00000000..439bd767
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/xpseudo_asm_gcc.h
@@ -0,0 +1,178 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp		 05/21/14 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H  /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H  /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s)	tostring(s)
+#define tostring(s)	#s
+
+/* pseudo assembler instructions */
+#define mfcpsr()	({u32 rval; \
+			   asm volatile("mrs %0,  DAIF" : "=r" (rval));\
+			  rval;\
+			 })
+
+#define mtcpsr(v) asm ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei()	//__asm__ __volatile__("cpsie	i\n")
+#define cpsidi()	//__asm__ __volatile__("cpsid	i\n")
+
+#define cpsief()	//__asm__ __volatile__("cpsie	f\n")
+#define cpsidf()	//__asm__ __volatile__("cpsid	f\n")
+
+
+
+#define mtgpr(rn, v)	/*__asm__ __volatile__(\
+			  "mov r" stringify(rn) ", %0 \n"\
+			  : : "r" (v)\
+			)*/
+
+#define mfgpr(rn)	/*({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mov %0,r" stringify(rn) "\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() asm ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() asm("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() asm("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr)	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "ldr	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#define ldrb(adr)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "ldrb	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#define str(adr, val)	__asm__ __volatile__(\
+			  "str	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+#define strb(adr, val)	__asm__ __volatile__(\
+			  "strb	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+/* Count leading zeroes (clz) */
+#define clz(arg)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "clz	%0,%1"\
+			    : "=r" (rval) : "r" (arg)\
+			  );\
+			  rval;\
+			 })
+#define mtcpdc(reg,val)	asm("dc " #reg ",%0"  : : "r" (val))
+#define mtcpic(reg,val)	asm("ic " #reg ",%0"  : : "r" (val))
+
+#define mtcpicall(reg)	asm("ic " #reg)
+#define mtcptlbi(reg)	asm("tlbi " #reg)
+#define mtcpat(reg,val)	asm("at " #reg ",%0"  : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg)	({u32 rval;\
+			asm("mrs	%0, " #reg : "=r" (rval));\
+			rval;\
+			})
+
+#define mtcp(reg,val)	asm("msr " #reg ",%0"  : : "r" (val))
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/lib/bsp/standalone/src/cortexa53/print.c b/lib/bsp/standalone/src/cortexa53/print.c
new file mode 100644
index 00000000..31d7b198
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/print.c
@@ -0,0 +1,32 @@
+/* print.c -- print a string on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ *
+ */
+
+/*
+ * print -- do a raw print of a string
+ */
+#include "xil_printf.h"
+
+void print(const char8 *ptr)
+{
+#ifdef STDOUT_BASEADDRESS
+  while (*ptr != (char8)0) {
+    outbyte (*ptr);
+	*ptr++;
+  }
+#else
+(void)ptr;
+#endif
+}
diff --git a/lib/bsp/standalone/src/cortexa53/putnum.c b/lib/bsp/standalone/src/cortexa53/putnum.c
new file mode 100644
index 00000000..ec0dc37e
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/putnum.c
@@ -0,0 +1,59 @@
+/* putnum.c -- put a hex number on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+ * putnum -- print a 32 bit number in hex
+ */
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Function Prototypes ******************************/
+extern void print (const char8 *ptr);
+void putnum(u32 num);
+
+void putnum(u32 num)
+{
+  char8  buf[9];
+  u32  cnt;
+  s32 i;
+  char8  *ptr;
+  u32  digit;
+  for(i = 0; i<9; i++) {
+	buf[i] = '0';
+  }
+
+  ptr = buf;
+  for (cnt = 7U ; cnt >= 0U ; cnt--) {
+    digit = ((num >> (cnt * 4U)) & 0x0000000FU);
+
+    if ((digit <= 9U) && (ptr != NULL)) {
+		digit += (u32)'0';
+		*ptr = ((char8) digit);
+		ptr += 1;
+	} else if (ptr != NULL) {
+		digit += ((u32)'a' - (u32)10);
+		*ptr = ((char8)digit);
+		ptr += 1;
+	} else {
+		/*Made for MisraC Compliance*/;
+	}
+  }
+
+  if(ptr != NULL) {
+	  *ptr = (char8) 0;
+  }
+  print (buf);
+}
diff --git a/lib/bsp/standalone/src/cortexa53/sleep.c b/lib/bsp/standalone/src/cortexa53/sleep.c
new file mode 100644
index 00000000..c186c6e9
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/sleep.c
@@ -0,0 +1,95 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************
+*
+* @file sleep.c
+*
+* This function provides a second delay using the Global Timer register in
+* the ARM Cortex A53 MP core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 

+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+
+/*****************************************************************************/
+/*
+*
+* This API is used to provide delays in seconds
+*
+* @param	seconds requested
+*
+* @return	0 always
+*
+* @note		None.
+*
+****************************************************************************/
+s32 sleep(u32 seconds)
+{
+	XTime tEnd, tCur;
+	/*write 50MHz frequency to System Time Stamp Generator Register*/
+	Xil_Out32(0xFF250020U,0x02FAF080U);
+	/*Enable the counter*/
+	Xil_Out32(0xFF260000U,0x00000001U);
+
+	XTime_GetTime(&tCur);
+	tEnd  = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
+	do
+	{
+		XTime_GetTime(&tCur);
+	} while (tCur < tEnd);
+
+	/*Disable the counter*/
+	Xil_Out32(0xFF260000U,0x00000000U);
+	return 0;
+}
diff --git a/lib/bsp/standalone/src/cortexa53/sleep.h b/lib/bsp/standalone/src/cortexa53/sleep.h
new file mode 100644
index 00000000..a74c2a28
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/sleep.h
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+s32 usleep(u32 useconds);
+s32 sleep(u32 seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/lib/bsp/standalone/src/cortexa53/uart.c b/lib/bsp/standalone/src/cortexa53/uart.c
new file mode 100644
index 00000000..37752d7c
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/uart.c
@@ -0,0 +1,173 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file uart.c
+*
+* This file contains APIs for configuring the UART.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/* Register offsets */
+#define UART_CR_OFFSET		0x00000000U
+#define UART_MR_OFFSET		0x00000004U
+#define UART_BAUDGEN_OFFSET	0x00000018U
+#define UART_BAUDDIV_OFFSET	0x00000034U
+
+#define MAX_BAUD_ERROR_RATE	3U	/* max % error allowed */
+#define UART_BAUDRATE	115200U
+#define CSU_VERSION_REG     0xFFCA0044U
+
+void Init_Uart(void);
+
+void Init_Uart(void)
+{
+#ifdef STDOUT_BASEADDRESS
+	u8 IterBAUDDIV;		/* Iterator for available baud divisor values */
+	u32 BRGR_Value;		/* Calculated value for baud rate generator */
+	u32 CalcBaudRate;	/* Calculated baud rate */
+	u32 BaudError;		/* Diff between calculated and requested baud
+				 * rate */
+	u32 Best_BRGR = 0U;	/* Best value for baud rate generator */
+	u8 Best_BAUDDIV = 0U;	/* Best value for baud divisor */
+	u32 Best_Error = 0xFFFFFFFFU;
+	u32 PercentError;
+	u32 InputClk;
+	u32 BaudRate = UART_BAUDRATE;
+
+	/* set CD and BDIV */
+
+#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR)
+	InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ;
+#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR)
+	InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ;
+#else
+	/* STDIO is not set or axi_uart is being used for STDIO */
+	return;
+#endif
+InputClk = 25000000U;
+	/*
+	 * Determine the Baud divider. It can be 4to 254.
+	 * Loop through all possible combinations
+	 */
+	for (IterBAUDDIV = 4U; IterBAUDDIV < 255U; IterBAUDDIV++) {
+
+		/*
+		 * Calculate the value for BRGR register
+		 */
+		BRGR_Value = InputClk / (BaudRate * ((u32)IterBAUDDIV + 1U));
+
+		/*
+		 * Calculate the baud rate from the BRGR value
+		 */
+		CalcBaudRate = InputClk/ (BRGR_Value * ((u32)IterBAUDDIV + 1U));
+
+		/*
+		 * Avoid unsigned integer underflow
+		 */
+		if (BaudRate > CalcBaudRate) {
+			BaudError = BaudRate - CalcBaudRate;
+		} else {
+			BaudError = CalcBaudRate - BaudRate;
+		}
+
+		/*
+		 * Find the calculated baud rate closest to requested baud rate.
+		 */
+		if (Best_Error > BaudError) {
+
+			Best_BRGR = BRGR_Value;
+			Best_BAUDDIV = IterBAUDDIV;
+			Best_Error = BaudError;
+		}
+	}
+
+	/*
+	 * Make sure the best error is not too large.
+	 */
+	PercentError = (Best_Error * 100U) / BaudRate;
+	if (((u32)MAX_BAUD_ERROR_RATE) < PercentError) {
+		return;
+	}
+
+	/* set CD and BDIV */
+	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR);
+	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, (u32)Best_BAUDDIV);
+
+    /*
+     * Veloce specific code
+     */
+    if((Xil_In32(CSU_VERSION_REG) & 0x0000F000U) == 0x00002000U ) {
+	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, 2U);
+	    Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, 4U);
+    }
+
+	/*
+	 * 8 data, 1 stop, 0 parity bits
+	 * sel_clk=uart_clk=APB clock
+	 */
+	Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x00000020U);
+
+	/* enable Tx/Rx and reset Tx/Rx data path */
+	Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x00000017U);
+
+	return;
+#endif
+}
diff --git a/lib/bsp/standalone/src/cortexa53/usleep.c b/lib/bsp/standalone/src/cortexa53/usleep.c
new file mode 100644
index 00000000..08b019ee
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/usleep.c
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file usleep.c
+*
+* This function provides a microsecond delay using the Global Timer register in
+* the ARM Cortex A53 MP core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 

+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexa53.h"
+
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_USECOND  (COUNTS_PER_SECOND/1000000 )
+
+/*****************************************************************************/
+/**
+*
+* This API gives a delay in microseconds
+*
+* @param	useconds requested
+*
+* @return	0 if the delay can be achieved, -1 if the requested delay
+*		is out of range
+*
+* @note		None.
+*
+****************************************************************************/
+s32 usleep(u32 useconds)
+{
+	XTime tEnd, tCur;
+	/*write 50MHz frequency to System Time Stamp Generator Register*/
+	Xil_Out32(0xFF250020U,0x02FAF080U);
+	/*Enable the counter*/
+	Xil_Out32(0xFF260000U,0x00000001U);
+
+	XTime_GetTime(&tCur);
+	tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
+	do
+	{
+		XTime_GetTime(&tCur);
+	} while (tCur < tEnd);
+
+	/*Disable the counter*/
+	Xil_Out32(0xFF260000U,0x00000000U);
+	return 0;
+}
diff --git a/lib/bsp/standalone/src/cortexa53/vectors.c b/lib/bsp/standalone/src/cortexa53/vectors.c
new file mode 100644
index 00000000..a15a7b72
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/vectors.c
@@ -0,0 +1,160 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.c
+*
+* This file contains the C level vectors for the ARM Cortex A53 core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xil_exception.h"
+#include "vectors.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XExc_VectorTableEntry XExc_VectorTable[];
+
+/************************** Function Prototypes ******************************/
+
+
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the FIQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void FIQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_FIQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the IRQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void IRQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_IRQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SynchronousInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_SYNC_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SError Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SErrorInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
+}
diff --git a/lib/bsp/standalone/src/cortexa53/vectors.h b/lib/bsp/standalone/src/cortexa53/vectors.h
new file mode 100644
index 00000000..f0609021
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/vectors.h
@@ -0,0 +1,92 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A53 core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/lib/bsp/standalone/src/cortexa53/xil_cache.c b/lib/bsp/standalone/src/cortexa53/xil_cache.c
new file mode 100644
index 00000000..726cf681
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/xil_cache.c
@@ -0,0 +1,659 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.c
+*
+* Contains required functions for the ARM cache functionality. Cache APIs are
+* yet to be implemented. They are left blank to avoid any compilation error
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xpseudo_asm.h"
+#include "xparameters.h"
+#include "xreg_cortexa53.h"
+#include "xil_exception.h"
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+#define IRQ_FIQ_MASK 0xC0U	/* Mask IRQ and FIQ interrupts in cpsr */
+
+/****************************************************************************
+*
+* Enable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+
+void Xil_DCacheEnable(void)
+{
+	u32 CtrlReg;
+	CtrlReg = mfcp(SCTLR_EL3);
+	/* enable caches only if they are disabled */
+	if((CtrlReg & XREG_CONTROL_DCACHE_BIT) == 0X00000000U){
+
+		/* invalidate the Data cache */
+		Xil_DCacheInvalidate();
+
+		CtrlReg |= XREG_CONTROL_DCACHE_BIT;
+
+		/* enable the Data cache */
+		mtcp(SCTLR_EL3,CtrlReg);
+	}
+}
+
+/****************************************************************************
+*
+* Disable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheDisable(void)
+{
+	u32 CtrlReg;
+	/* clean and invalidate the Data cache */
+	Xil_DCacheFlush();
+	CtrlReg = mfcp(SCTLR_EL3);
+
+	CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+	/* disable the Data cache */
+	mtcp(SCTLR_EL3,CtrlReg);
+}
+
+/****************************************************************************
+*
+* invalidate the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidate(void)
+{
+	register u32 CsidReg, C7Reg;
+	u32 LineSize, NumWays;
+	u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, NumCacheLevel, CacheLevel,CacheLevelIndex;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+
+	/* Number of level of cache*/
+	NumCacheLevel = (mfcp(CLIDR_EL1)>>24U) & 0x00000007U;
+
+	CacheLevel=0U;
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(CSSELR_EL1,CacheLevel);
+	isb();
+
+	CsidReg = mfcp(CCSIDR_EL1);
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x00001FFFU) >> 3U;
+	NumWays += 0X00000001U;
+
+	/*Number of Set*/
+	NumSet = (CsidReg >> 13U) & 0x00007FFFU;
+	NumSet += 0X00000001U;
+
+	WayAdjust = clz(NumWays) - (u32)0x0000001FU;
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Invalidate all the cachelines */
+	for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set | CacheLevel;
+			mtcpdc(ISW,C7Reg);
+			Set += (0x00000001U << LineSize);
+		}
+		Set = 0U;
+		Way += (0x00000001U << WayAdjust);
+	}
+
+	/* Wait for invalidate to complete */
+	dsb();
+
+	/* Select cache level 1 and D cache in CSSR */
+	CacheLevel += (0x00000001U<<1U) ;
+	mtcp(CSSELR_EL1,CacheLevel);
+	isb();
+
+	CsidReg = mfcp(CCSIDR_EL1);
+
+	/* Get the cacheline size, way size, index size from csidr */
+		LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x00001FFFU) >> 3U;
+	NumWays += 0x00000001U;
+
+	/* Number of Sets */
+	NumSet = (CsidReg >> 13U) & 0x00007FFFU;
+	NumSet += 0x00000001U;
+
+	WayAdjust = clz(NumWays) - (u32)0x0000001FU;
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Invalidate all the cachelines */
+	for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set | CacheLevel;
+			mtcpdc(ISW,C7Reg);
+			Set += (0x00000001U << LineSize);
+		}
+		Set = 0U;
+		Way += (0x00000001U << WayAdjust);
+	}
+	/* Wait for invalidate to complete */
+	dsb();
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated.	If the cacheline is modified (dirty), the modified contents
+* are written to system memory before the line is invalidated.
+*
+* @param	Address to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 6 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateLine(INTPTR adr)
+{
+
+	u32 currmask;
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(CSSELR_EL1,0x0);
+	mtcpdc(IVAC,(adr & (~0x3F)));
+	/* Wait for invalidate to complete */
+	dsb();
+	/* Select cache level 1 and D cache in CSSR */
+	mtcp(CSSELR_EL1,0x2);
+	mtcpdc(IVAC,(adr & (~0x3F)));
+	/* Wait for invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate the Data cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated. If the cacheline
+* is modified (dirty), the modified contents are written to system memory
+* before the line is invalidated.
+*
+* @param	Start address of range to be invalidated.
+* @param	Length of range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateRange(INTPTR  adr, u32 len)
+{
+	const u32 cacheline = 64U;
+	u32 end;
+	u32 tempadr = adr;
+	u32 tempend;
+	u32 currmask;
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	if (len != 0U) {
+		end = tempadr + len;
+		tempend = end;
+
+		if ((tempadr & (cacheline-1U)) != 0U) {
+			tempadr &= (~(cacheline - 1U));
+			Xil_DCacheFlushLine(tempadr);
+			tempadr += cacheline;
+		}
+		if ((tempend & (cacheline-1U)) != 0U) {
+			tempend &= (~(cacheline - 1U));
+			Xil_DCacheFlushLine(tempend);
+		}
+
+		while (tempadr < tempend) {
+			/* Select cache level 0 and D cache in CSSR */
+			mtcp(CSSELR_EL1,0x0);
+			/* Invalidate Data cache line */
+			mtcpdc(IVAC,(tempadr & (~0x3F)));
+			/* Wait for invalidate to complete */
+			dsb();
+			/* Select cache level 0 and D cache in CSSR */
+			mtcp(CSSELR_EL1,0x2);
+			/* Invalidate Data cache line */
+			mtcpdc(IVAC,(tempadr & (~0x3F)));
+			/* Wait for invalidate to complete */
+			dsb();
+			tempadr += cacheline;
+		}
+	}
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Flush the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheFlush(void)
+{
+	register u32 CsidReg, C7Reg;
+	u32 LineSize, NumWays;
+	u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, NumCacheLevel, CacheLevel,CacheLevelIndex;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+
+	/* Number of level of cache*/
+	NumCacheLevel = (mfcp(CLIDR_EL1)>>24U) & 0x00000007U;
+
+	CacheLevel = 0U;
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(CSSELR_EL1,CacheLevel);
+	isb();
+
+	CsidReg = mfcp(CCSIDR_EL1);
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x00001FFFU) >> 3U;
+	NumWays += 0x00000001U;
+
+	/*Number of Set*/
+	NumSet = (CsidReg >> 13U) & 0x00007FFFU;
+	NumSet += 0x00000001U;
+
+	WayAdjust = clz(NumWays) - (u32)0x0000001FU;
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Flush all the cachelines */
+	for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set | CacheLevel;
+			mtcpdc(CISW,C7Reg);
+			Set += (0x00000001U << LineSize);
+		}
+		Set = 0U;
+		Way += (0x00000001U << WayAdjust);
+	}
+
+	/* Wait for Flush to complete */
+	dsb();
+
+	/* Select cache level 1 and D cache in CSSR */
+	CacheLevel += (0x00000001U << 1U);
+	mtcp(CSSELR_EL1,CacheLevel);
+	isb();
+
+	CsidReg = mfcp(CCSIDR_EL1);
+
+	/* Get the cacheline size, way size, index size from csidr */
+		LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x00001FFFU) >> 3U;
+	NumWays += 0x00000001U;
+
+	/* Number of Sets */
+	NumSet = (CsidReg >> 13U) & 0x00007FFFU;
+	NumSet += 0x00000001U;
+
+	WayAdjust=clz(NumWays) - (u32)0x0000001FU;
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Flush all the cachelines */
+	for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set | CacheLevel;
+			mtcpdc(CISW,C7Reg);
+			Set += (0x00000001U << LineSize);
+		}
+		Set=0U;
+		Way += (0x00000001U<
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheInvalidateLine(INTPTR adr);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+void Xil_DCacheFlushLine(INTPTR adr);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_ICacheInvalidateLine(INTPTR adr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/lib/bsp/standalone/src/cortexa53/xil_exception.c b/lib/bsp/standalone/src/cortexa53/xil_exception.c
new file mode 100644
index 00000000..a0d6781a
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/xil_exception.c
@@ -0,0 +1,225 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xil_exception.c
+*
+* This file contains low-level driver functions for the Cortex A53 exception
+* Handler.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xpseudo_asm.h"
+#include "xdebug.h"
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+static void Xil_ExceptionNullHandler(void *Data);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Exception vector table to store handlers for each exception vector.
+ */
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_SyncAbortHandler, NULL},
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_SErrorAbortHandler, NULL},
+
+};
+/****************************************************************************/
+/**
+*
+* This function is a stub Handler that is the default Handler that gets called
+* if the application has not setup a Handler for a specific  exception. The
+* function interface has to match the interface specified for a Handler even
+* though none of the arguments are used.
+*
+* @param	Data is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void Xil_ExceptionNullHandler(void *Data)
+{
+	(void *)Data;
+DieLoop: goto DieLoop;
+}
+
+/****************************************************************************/
+/**
+*
+* The function is a common API used to initialize exception handlers across all
+* processors supported. For ARM CortexA53, the exception handlers are being
+* initialized statically and hence this function does not do anything.
+*
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xil_ExceptionInit(void)
+{
+	return;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Id of the exception source and the
+* associated Handler that is to run when the exception is recognized. The
+* argument provided in this call as the Data is used as the argument
+* for the Handler when it is called.
+*
+* @param	exception_id contains the ID of the exception source and should
+*		be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+		See xil_exception_l.h for further information.
+* @param	Handler to the Handler for that exception.
+* @param	Data is a reference to Data that will be passed to the
+*		Handler when it gets called.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRegisterHandler(u32 Exception_id,
+				    Xil_ExceptionHandler Handler,
+				    void *Data)
+{
+	XExc_VectorTable[Exception_id].Handler = Handler;
+	XExc_VectorTable[Exception_id].Data = Data;
+}
+
+/*****************************************************************************/
+/**
+*
+* Removes the Handler for a specific exception Id. The stub Handler is then
+* registered for this exception Id.
+*
+* @param	exception_id contains the ID of the exception source and should
+*		be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+*		See xil_exception_l.h for further information.
+
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRemoveHandler(u32 Exception_id)
+{
+	Xil_ExceptionRegisterHandler(Exception_id,
+				       Xil_ExceptionNullHandler,
+				       NULL);
+}
+/*****************************************************************************/
+/**
+*
+* Default Synchronous abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param        None
+*
+* @return       None.
+*
+* @note         None.
+*
+****************************************************************************/
+
+void Xil_SyncAbortHandler(void *CallBackRef){
+	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+	while(1) {
+		;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Default SError abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param        None
+*
+* @return       None.
+*
+* @note         None.
+*
+****************************************************************************/
+void Xil_SErrorAbortHandler(void *CallBackRef){
+	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+	while(1) {
+		;
+	}
+}
diff --git a/lib/bsp/standalone/src/cortexa53/xil_exception.h b/lib/bsp/standalone/src/cortexa53/xil_exception.h
new file mode 100644
index 00000000..3dad6014
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/xil_exception.h
@@ -0,0 +1,179 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A53 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ	XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ	XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL	(XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST			0U
+#define XIL_EXCEPTION_ID_SYNC_INT		1U
+#define XIL_EXCEPTION_ID_IRQ_INT		2U
+#define XIL_EXCEPTION_ID_FIQ_INT		3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT		4U
+#define XIL_EXCEPTION_ID_LAST			5U
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT	XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Enable Exceptions.
+*
+* @param	Mask for exceptions to be enabled.
+*
+* @return	None.
+*
+* @note		If bit is 0, exception is enabled.
+*		C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+
+#define Xil_ExceptionEnableMask(Mask)	\
+		mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+
+/****************************************************************************/
+/**
+* Enable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+		Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* Disable Exceptions.
+*
+* @param	Mask for exceptions to be enabled.
+*
+* @return	None.
+*
+* @note		If bit is 1, exception is disabled.
+*		C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+
+#define Xil_ExceptionDisableMask(Mask)	\
+		mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+		Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+					 Xil_ExceptionHandler Handler,
+					 void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+
+extern void Xil_ExceptionInit(void);
+
+void Xil_SyncAbortHandler(void *CallBackRef);
+
+void Xil_SErrorAbortHandler(void *CallBackRef);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
diff --git a/lib/bsp/standalone/src/cortexa53/xil_io.c b/lib/bsp/standalone/src/cortexa53/xil_io.c
new file mode 100644
index 00000000..a4c196d7
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/xil_io.c
@@ -0,0 +1,392 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures.  These functions encapsulate Cortex A53 architecture-specific
+* I/O requirements.
+*
+* @note
+*
+* This file contains architecture-dependent code.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 

+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexa53.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for an 8-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u8 Xil_In8(INTPTR Addr)
+{
+	return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 16-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_In16(INTPTR Addr)
+{
+	return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_In32(INTPTR Addr)
+{
+	return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for an 8-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out8(INTPTR Addr, u8 Value)
+{
+	u8 *LocalAddr = (u8 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 16-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out16(INTPTR Addr, u16 Value)
+{
+	u16 *LocalAddr = (u16 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 32-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out32(INTPTR Addr, u32 Value)
+{
+	u32 *LocalAddr = (u32 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 64-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out64(INTPTR Addr, u64 Value)
+{
+	u64 *LocalAddr = (u64 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 64-bit memory location by reading the
+* specified Value to the the specified address.
+*
+* @param	OutAddress contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+u64 Xil_In64(INTPTR Addr)
+{
+	return *(volatile u64 *) Addr;
+}
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 16-bit memory location by reading from the
+* specified address and returning the byte-swapped Value read from that
+* address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The byte-swapped Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_In16BE(INTPTR Addr)
+{
+	u16 temp;
+	u16 result;
+
+	temp = Xil_In16(Addr);
+
+	result = Xil_EndianSwap16(temp);
+
+	return result;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the byte-swapped Value read from that
+* address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The byte-swapped Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_In32BE(INTPTR Addr)
+{
+	u32 temp;
+	u32 result;
+
+	temp = Xil_In32(Addr);
+
+	result = Xil_EndianSwap32(temp);
+
+	return result;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 16-bit memory location by writing the
+* specified Value to the the specified address. The Value is byte-swapped
+* before being written.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out16BE(INTPTR Addr, u16 Value)
+{
+	u16 temp;
+
+	temp = Xil_EndianSwap16(Value);
+
+    Xil_Out16(Addr, temp);
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 32-bit memory location by writing the
+* specified Value to the the specified address. The Value is byte-swapped
+* before being written.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out32BE(INTPTR Addr, u32 Value)
+{
+	u32 temp;
+
+	temp = Xil_EndianSwap32(Value);
+
+    Xil_Out32(Addr, temp);
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 16-bit endian converion.
+*
+* @param	Data contains the value to be converted.
+*
+* @return	converted value.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+	return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 32-bit endian converion.
+*
+* @param	Data contains the value to be converted.
+*
+* @return	converted value.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+	u16 LoWord;
+	u16 HiWord;
+
+	/* get each of the half words from the 32 bit word */
+
+	LoWord = (u16) (Data & 0x0000FFFFU);
+	HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+	/* byte swap each of the 16 bit half words */
+
+	LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+	HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+	/* swap the half words before returning the value */
+
+	return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}
diff --git a/lib/bsp/standalone/src/cortexa53/xil_io.h b/lib/bsp/standalone/src/cortexa53/xil_io.h
new file mode 100644
index 00000000..882add78
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/xil_io.h
@@ -0,0 +1,256 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* This file contains the interface for the general IO component, which
+* encapsulates the Input/Output functions for processors that do not
+* require any special I/O handling.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 

+******************************************************************************/
+
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H           /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "xil_printf.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#if defined __GNUC__
+#  define SYNCHRONIZE_IO	dmb()
+#  define INST_SYNC		isb()
+#  define DATA_SYNC		dsb()
+#else
+#  define SYNCHRONIZE_IO
+#  define INST_SYNC
+#  define DATA_SYNC
+#endif /* __GNUC__ */
+
+/*****************************************************************************/
+/**
+*
+* Perform an big-endian input operation for a 16-bit memory location
+* by reading from the specified address and returning the Value read from
+* that address.
+*
+* @param	Addr contains the address to perform the input operation at.
+*
+* @return	The Value read from the specified input address with the
+*		proper endianness. The return Value has the same endianness
+*		as that of the processor, i.e. if the processor is
+*		little-engian, the return Value is the byte-swapped Value read
+*		from the address.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_In16LE(Addr) Xil_In16((Addr))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian input operation for a 32-bit memory location
+* by reading from the specified address and returning the Value read from
+* that address.
+*
+* @param	Addr contains the address to perform the input operation at.
+*
+* @return	The Value read from the specified input address with the
+*		proper endianness. The return Value has the same endianness
+*		as that of the processor, i.e. if the processor is
+*		little-engian, the return Value is the byte-swapped Value read
+*		from the address.
+*
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_In32LE(Addr) Xil_In32((Addr))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 16-bit memory location
+* by writing the specified Value to the specified address.
+*
+* @param	Addr contains the address to perform the output operation at.
+* @param	Value contains the Value to be output at the specified address.
+*		The Value has the same endianness as that of the processor.
+*		If the processor is little-endian, the byte-swapped Value is
+*		written to the address.
+*
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 32-bit memory location
+* by writing the specified Value to the specified address.
+*
+* @param	Addr contains the address to perform the output operation at.
+* @param	Value contains the Value to be output at the specified address.
+*		The Value has the same endianness as that of the processor.
+*		If the processor is little-endian, the byte-swapped Value is
+*		written to the address.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from host byte order to network byte order.
+*
+* @param	Data the 32-bit number to be converted.
+*
+* @return	The converted 32-bit number in network byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Htonl(Data) Xil_EndianSwap32((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from host byte order to network byte order.
+*
+* @param	Data the 16-bit number to be converted.
+*
+* @return	The converted 16-bit number in network byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Htons(Data) Xil_EndianSwap16((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from network byte order to host byte order.
+*
+* @param	Data the 32-bit number to be converted.
+*
+* @return	The converted 32-bit number in host byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Ntohl(Data) Xil_EndianSwap32((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from network byte order to host byte order.
+*
+* @param	Data the 16-bit number to be converted.
+*
+* @return	The converted 16-bit number in host byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Ntohs(Data) Xil_EndianSwap16((Data))
+
+/************************** Function Prototypes ******************************/
+
+/* The following functions allow the software to be transportable across
+ * processors which may use memory mapped I/O or I/O which is mapped into a
+ * seperate address space.
+ */
+u8 Xil_In8(INTPTR Addr);
+u16 Xil_In16(INTPTR Addr);
+u32 Xil_In32(INTPTR Addr);
+u64 Xil_In64(INTPTR Addr);
+
+void Xil_Out8(INTPTR Addr, u8 Value);
+void Xil_Out16(INTPTR Addr, u16 Value);
+void Xil_Out32(INTPTR Addr, u32 Value);
+void Xil_Out64(INTPTR Addr, u64 Value);
+
+
+u16 Xil_In16BE(INTPTR Addr);
+u32 Xil_In32BE(INTPTR Addr);
+void Xil_Out16BE(INTPTR Addr, u16 Value);
+void Xil_Out32BE(INTPTR Addr, u32 Value);
+
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/lib/bsp/standalone/src/cortexa53/xil_mmu.c b/lib/bsp/standalone/src/cortexa53/xil_mmu.c
new file mode 100644
index 00000000..0b2174ea
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/xil_mmu.c
@@ -0,0 +1,171 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.c
+*
+* This file provides APIs for enabling/disabling MMU and setting the memory
+* attributes for sections, in the MMU translation table.
+* MMU APIs are yet to be implemented. They are left blank to avoid any
+* compilation error
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_mmu.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+extern INTPTR MMUTableL1;
+extern INTPTR MMUTableL2;
+/************************** Function Prototypes ******************************/
+/*****************************************************************************
+*
+* Set the memory attributes for a section, in the translation table.
+*
+* @param	addr is the address for which attributes are to be set.
+* @param	attrib specifies the attributes for that memory region.
+*
+* @return	None.
+*
+* @note		The MMU and D-cache need not be disabled before changing an
+*			translation table attribute.
+*
+******************************************************************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib)
+{
+	INTPTR *ptr;
+	INTPTR section;
+	/* if region is less than 4GB MMUTable level 2 need to be modified */
+	if(Addr<0x100000000){
+	section = Addr / 0x00200000U;
+	ptr = &MMUTableL2 + section;
+	*ptr = (Addr & (~0x001FFFFFU)) | attrib;
+	}
+	/* if region is greater than 4GB MMUTable level 1 need to be modified */
+	else{
+	section = Addr / 0x40000000U;
+	ptr = &MMUTableL1 + section;
+	*ptr = (Addr & (~0x3FFFFFFFU)) | attrib;
+	}
+
+	Xil_DCacheFlush();
+	mtcptlbi(ALLE3);
+
+	dsb(); /* ensure completion of the BP and TLB invalidation */
+    isb(); /* synchronize context on this processor */
+
+}
+
+/*****************************************************************************
+*
+* Invalidate the caches and then enable MMU for Cortex A53 processor.
+*
+* @param	None.
+* @return	None.
+*
+******************************************************************************/
+void Xil_EnableMMU(void)
+{
+	u32 Reg;
+	Xil_DCacheInvalidate();
+	Xil_ICacheInvalidate();
+
+	Reg = mfcp(SCTLR_EL1);
+
+	Reg |= 0x00000001U;
+	/* Enable MMU */
+	mtcp(SCTLR_EL1, Reg);
+
+	dsb(); /* ensure completion of the BP and TLB invalidation */
+    isb(); /* synchronize context on this processor */
+}
+
+/*****************************************************************************
+*
+* Disable MMU for Cortex A53 processors. This function invalidates the TLBs
+* and flushed the D Caches before disabling the MMU and D cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+******************************************************************************/
+void Xil_DisableMMU(void)
+{
+
+	u32 Reg;
+
+	mtcptlbi(ALLE3);
+	Xil_DCacheFlush();
+
+	Reg = mfcp(SCTLR_EL1);
+	Reg &= ~(0x00000001U);
+	/*Disable mmu*/
+	mtcp(SCTLR_EL1, Reg);
+	dsb(); /* ensure completion of the BP and TLB invalidation */
+    isb(); /* synchronize context on this processor */
+}
diff --git a/lib/bsp/standalone/src/cortexa53/xil_mmu.h b/lib/bsp/standalone/src/cortexa53/xil_mmu.h
new file mode 100644
index 00000000..c5a8d0f3
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/xil_mmu.h
@@ -0,0 +1,92 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib);
+void Xil_EnableMMU(void);
+void Xil_DisableMMU(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
diff --git a/lib/bsp/standalone/src/cortexa53/xil_printf.c b/lib/bsp/standalone/src/cortexa53/xil_printf.c
new file mode 100644
index 00000000..cc10c957
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/xil_printf.c
@@ -0,0 +1,329 @@
+/*---------------------------------------------------*/
+/* Modified from :                                   */
+/* Public Domain version of printf                   */
+/* Rud Merriam, Compsult, Inc. Houston, Tx.          */
+/* For Embedded Systems Programming, 1991            */
+/*                                                   */
+/*---------------------------------------------------*/
+#include "xil_printf.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include 
+#include 
+#include 
+
+typedef struct params_s {
+    s32 len;
+    s32 num1;
+    s32 num2;
+    char8 pad_character;
+    s32 do_padding;
+    s32 left_flag;
+} params_t;
+
+static void padding( const s32 l_flag,const params_t *par);
+static void outs(const charptr lp, params_t *par);
+static void outnum( const s32 n, const s32 base, params_t *par);
+static s32 getnum( charptr* linep);
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine puts pad characters into the output  */
+/* buffer.                                           */
+/*                                                   */
+static void padding( const s32 l_flag, const params_t *par)
+{
+    s32 i;
+
+    if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
+		i=(par->len);
+        for (; i<(par->num1); i++) {
+            outbyte( par->pad_character);
+		}
+    }
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a string to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+static void outs(const charptr lp, params_t *par)
+{
+    charptr LocalPtr;
+	LocalPtr = lp;
+    /* pad on left if needed                         */
+	if(LocalPtr != NULL) {
+		par->len = (s32)strlen( LocalPtr);
+	}
+    padding( !(par->left_flag), par);
+
+    /* Move string to the buffer                     */
+    while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
+		(par->num2)--;
+        outbyte(*LocalPtr);
+		LocalPtr += 1;
+}
+
+    /* Pad on right if needed                        */
+    /* CR 439175 - elided next stmt. Seemed bogus.   */
+    /* par->len = strlen( lp)                      */
+    padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a number to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+
+static void outnum( const s32 n, const s32 base, params_t *par)
+{
+    charptr cp;
+    s32 negative;
+	s32 i;
+    char8 outbuf[32];
+    const char8 digits[] = "0123456789ABCDEF";
+    s32 num;
+    for(i = 0; i<32; i++) {
+	outbuf[i] = '0';
+    }
+
+    /* Check if number is negative                   */
+    if ((base == 10) && (n < 0L)) {
+        negative = 1;
+		num =(-(n));
+    }
+    else{
+        num = (n);
+        negative = 0;
+    }
+
+    /* Build number (backwards) in outbuf            */
+    i = 0;
+    do {
+		outbuf[i] = digits[(num % base)];
+		i++;
+		num /= base;
+    } while (num > 0);
+
+    if (negative != 0) {
+		outbuf[i] = '-';
+		i++;
+	}
+
+    outbuf[i] = 0;
+    i--;
+
+    /* Move the converted number to the buffer and   */
+    /* add in the padding where needed.              */
+    par->len = (s32)strlen(outbuf);
+    padding( !(par->left_flag), par);
+    while (&outbuf[i] >= outbuf) {
+	outbyte( outbuf[i] );
+		i--;
+}
+    padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine gets a number from the format        */
+/* string.                                           */
+/*                                                   */
+static s32 getnum( charptr* linep)
+{
+    s32 n;
+    s32 ResultIsDigit = 0;
+    charptr cptr;
+    n = 0;
+    cptr = *linep;
+	if(cptr != NULL){
+		ResultIsDigit = isdigit(((s32)*cptr));
+	}
+    while (ResultIsDigit != 0) {
+		if(cptr != NULL){
+			n = ((n*10) + (((s32)*cptr) - (s32)'0'));
+			cptr += 1;
+			if(cptr != NULL){
+				ResultIsDigit = isdigit(((s32)*cptr));
+			}
+		}
+		ResultIsDigit = isdigit(((s32)*cptr));
+	}
+    *linep = ((charptr )(cptr));
+    return(n);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine operates just like a printf/sprintf  */
+/* routine. It outputs a set of data under the       */
+/* control of a formatting string. Not all of the    */
+/* standard C format control are supported. The ones */
+/* provided are primarily those needed for embedded  */
+/* systems work. Primarily the floating point        */
+/* routines are omitted. Other formats could be      */
+/* added easily by following the examples shown for  */
+/* the supported formats.                            */
+/*                                                   */
+
+/* void esp_printf( const func_ptr f_ptr,
+   const charptr ctrl1, ...) */
+void xil_printf( char8 *ctrl1, ...)
+{
+	s32 Check;
+    s32 long_flag;
+    s32 dot_flag;
+
+    params_t par;
+
+    char8 ch;
+    va_list argp;
+    char8 *ctrl = (char8 *)ctrl1;
+
+    va_start( argp, ctrl1);
+
+    while ((ctrl != NULL) && (*ctrl != (char8)0)) {
+
+        /* move format string chars to buffer until a  */
+        /* format control is found.                    */
+        if (*ctrl != '%') {
+            outbyte(*ctrl);
+			ctrl += 1;
+            continue;
+        }
+
+        /* initialize all the flags for this format.   */
+        dot_flag = 0;
+		long_flag = 0;
+		par.left_flag = 0;
+		par.do_padding = 0;
+        par.pad_character = ' ';
+        par.num2=32767;
+		par.num1=0;
+		par.len=0;
+
+ try_next:
+		if(ctrl != NULL) {
+			ctrl += 1;
+		}
+		if(ctrl != NULL) {
+			ch = *ctrl;
+		}
+		else {
+			ch = *ctrl;
+		}
+
+        if (isdigit((s32)ch) != 0) {
+            if (dot_flag != 0) {
+                par.num2 = getnum(&ctrl);
+			}
+            else {
+                if (ch == '0') {
+                    par.pad_character = '0';
+				}
+				if(ctrl != NULL) {
+			par.num1 = getnum(&ctrl);
+				}
+                par.do_padding = 1;
+            }
+            if(ctrl != NULL) {
+			ctrl -= 1;
+			}
+            goto try_next;
+        }
+
+        switch (tolower((s32)ch)) {
+            case '%':
+                outbyte( '%');
+                Check = 1;
+                break;
+
+            case '-':
+                par.left_flag = 1;
+                Check = 0;
+                break;
+
+            case '.':
+                dot_flag = 1;
+                Check = 0;
+                break;
+
+            case 'l':
+                long_flag = 1;
+                Check = 0;
+                break;
+
+            case 'd':
+                if ((long_flag != 0) || (ch == 'D')) {
+                    outnum( va_arg(argp, s32), 10L, &par);
+                }
+                else {
+                    outnum( va_arg(argp, s32), 10L, &par);
+                }
+				Check = 1;
+                break;
+            case 'x':
+                outnum((s32)va_arg(argp, s32), 16L, &par);
+                Check = 1;
+                break;
+
+            case 's':
+                outs( va_arg( argp, char *), &par);
+                Check = 1;
+                break;
+
+            case 'c':
+                outbyte( va_arg( argp, s32));
+                Check = 1;
+                break;
+
+            case '\\':
+                switch (*ctrl) {
+                    case 'a':
+                        outbyte( ((char8)0x07));
+                        break;
+                    case 'h':
+                        outbyte( ((char8)0x08));
+                        break;
+                    case 'r':
+                        outbyte( ((char8)0x0D));
+                        break;
+                    case 'n':
+                        outbyte( ((char8)0x0D));
+                        outbyte( ((char8)0x0A));
+                        break;
+                    default:
+                        outbyte( *ctrl);
+                        break;
+                }
+                ctrl += 1;
+                Check = 0;
+                break;
+
+            default:
+		Check = 1;
+		break;
+        }
+        if(Check == 1) {
+			if(ctrl != NULL) {
+				ctrl += 1;
+			}
+                continue;
+        }
+        goto try_next;
+    }
+    va_end( argp);
+}
+
+/*---------------------------------------------------*/
diff --git a/lib/bsp/standalone/src/cortexa53/xil_printf.h b/lib/bsp/standalone/src/cortexa53/xil_printf.h
new file mode 100644
index 00000000..6c1e1507
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/xil_printf.h
@@ -0,0 +1,44 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+#include 
+#include "xil_types.h"
+#include "xparameters.h"
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to   */
+/* make xil_printf re-entrant.                        */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/*                                                   */
+
+void xil_printf( char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/lib/bsp/standalone/src/cortexa53/xparameters_ps.h b/lib/bsp/standalone/src/cortexa53/xparameters_ps.h
new file mode 100644
index 00000000..89c170c3
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/xparameters_ps.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A53 core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR		0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR		0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts  */
+#define XPAR_XUARTPS_0_INTR		XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR		XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR		XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR		XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR		XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR		XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_XEMACPS_2_INTR		XPS_GEM2_INT_ID
+#define XPAR_XEMACPS_2_WAKE_INTR	XPS_GEM2_WAKE_INT_ID
+#define XPAR_XEMACPS_3_INTR		XPS_GEM3_INT_ID
+#define XPAR_XEMACPS_3_WAKE_INTR	XPS_GEM3_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR		XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR		XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR		XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR		XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR		XPS_TTC1_2_INT_ID
+#define XPAR_XTTCPS_6_INTR		XPS_TTC2_0_INT_ID
+#define XPAR_XTTCPS_7_INTR		XPS_TTC2_1_INT_ID
+#define XPAR_XTTCPS_8_INTR		XPS_TTC2_2_INT_ID
+#define XPAR_XTTCPS_9_INTR		XPS_TTC3_0_INT_ID
+#define XPAR_XTTCPS_10_INTR		XPS_TTC3_1_INT_ID
+#define XPAR_XTTCPS_11_INTR		XPS_TTC3_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR	XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0	XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1	XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2	XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3	XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4	XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
+#define XPAR_XNANDPS8_0_INTR        XPS_NAND_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR	XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR	XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES	1U
+#define XPAR_XSLCR_0_DEVICE_ID		0U
+#define XPAR_XSLCR_0_BASEADDR		XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES	1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID	0U
+#define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00002000U)
+#define XPAR_SCUGIC_ACK_BEFORE		0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES	1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID	0U
+#define XPAR_GLOBAL_TMR_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR		XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for backwards compatibilty
+ */
+
+#define XPS_PERIPHERAL_BASEADDR		0xE0000000U
+#define XPS_UART0_BASEADDR		0xFF000000U
+#define XPS_UART1_BASEADDR		0xFF010000U
+#define XPS_I2C0_BASEADDR		0xFF020000U
+#define XPS_I2C1_BASEADDR		0xFF030000U
+#define XPS_SPI0_BASEADDR		0xFF040000U
+#define XPS_SPI1_BASEADDR		0xFF050000U
+#define XPS_CAN0_BASEADDR		0xFF060000U
+#define XPS_CAN1_BASEADDR		0xFF070000U
+#define XPS_GPIO_BASEADDR		0xFF0A0000U
+#define XPS_GEM0_BASEADDR		0xFF0B0000U
+#define XPS_GEM1_BASEADDR		0xFF0C0000U
+#define XPS_GEM2_BASEADDR		0xFF0D0000U
+#define XPS_GEM3_BASEADDR		0xFF0E0000U
+#define XPS_QSPI_BASEADDR		0xFF0F0000U
+#define XPS_NAND_BASEADDR		0xFF100000U
+#define XPS_TTC0_BASEADDR		0xFF110000U
+#define XPS_TTC1_BASEADDR		0xFF120000U
+#define XPS_TTC2_BASEADDR		0xFF130000U
+#define XPS_TTC3_BASEADDR		0xFF140000U
+#define XPS_WDT_BASEADDR		0xFF150000U
+#define XPS_SDIO0_BASEADDR		0xFF160000U
+#define XPS_SDIO1_BASEADDR		0xFF170000U
+#define XPS_SYS_CTRL_BASEADDR	0xFF180000U
+/*#define XPAR_XNANDPS8_0_BASEADDR 0xFF100000U */
+
+
+#define XPS_PARPORT_CRTL_BASEADDR 0x0000000U
+#define XPS_IOU_BUS_CFG_BASEADDR	0xE0200000U
+#define XPS_PARPORT0_BASEADDR		0xE2000000U
+#define XPS_PARPORT1_BASEADDR		0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR	0xF0000000U
+#define XPS_DMAC0_NON_SEC_BASEADDR	0xFE507000U
+#define XPS_DMAC0_SEC_BASEADDR		0xFE5F0000U
+#define XPS_DDR_CTRL_BASEADDR		0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR	0xF8007000U
+#define XPS_AFI0_BASEADDR		0xF8008000U
+#define XPS_AFI1_BASEADDR		0xF8009000U
+#define XPS_AFI2_BASEADDR		0xF800A000U
+#define XPS_AFI3_BASEADDR		0xF800B000U
+#define XPS_OCM_BASEADDR		0xF800C000U
+#define XPS_EFUSE_BASEADDR		0xF800D000U
+#define XPS_CORESIGHT_BASEADDR		0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR	0xF8900000U
+#define XPS_SCU_PERIPH_BASE		0xF9000000U
+#define XPS_L2CC_BASEADDR		0xFD3FD000U
+#define XPS_SAM_RAM_BASEADDR		0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR	0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR	0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR	0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR		0xF8000000U
+#define XPS_USB0_BASEADDR		0xE0002000U
+#define XPS_USB1_BASEADDR		0xE0003000U
+
+
+/* Shared Peripheral Interrupts (SPI) */
+
+#define XPS_USB1_INT_ID			76U
+#define XPS_USB0_INT_ID			53U
+
+#define XPS_NAND_INT_ID        (32U + 32U)
+
+#define XPS_FPGA1_INT_ID		62U
+#define XPS_FPGA2_INT_ID		63U
+#define XPS_FPGA3_INT_ID		64U
+#define XPS_FPGA4_INT_ID		65U
+#define XPS_FPGA5_INT_ID		66U
+#define XPS_FPGA6_INT_ID		67U
+#define XPS_FPGA7_INT_ID		68U
+#define XPS_DMA4_INT_ID			72U
+#define XPS_DMA5_INT_ID			73U
+#define XPS_DMA6_INT_ID			74U
+#define XPS_DMA7_INT_ID			75U
+#define XPS_FPGA8_INT_ID		84U
+#define XPS_FPGA9_INT_ID		85U
+#define XPS_FPGA10_INT_ID		86U
+#define XPS_FPGA11_INT_ID		87U
+#define XPS_FPGA12_INT_ID		88U
+#define XPS_FPGA13_INT_ID		89U
+#define XPS_FPGA14_INT_ID		90U
+#define XPS_FPGA15_INT_ID		91U
+
+
+#define XPS_OCMINTR_INT_ID		(28U + 32U)
+#define XPS_QSPI_INT_ID			(33U + 32U)
+#define XPS_GPIO_INT_ID			(34U + 32U)
+#define XPS_WDT_INT_ID			(106U + 32U)
+#define XPS_LP_WDT_INT_ID			(69U + 32U)
+#define XPS_TTC0_0_INT_ID		(53U + 32U)
+#define XPS_TTC0_1_INT_ID		(54U + 32U)
+#define XPS_TTC0_2_INT_ID 		(55U + 32U)
+#define XPS_SDIO0_INT_ID		(65U + 32U)
+#define XPS_I2C0_INT_ID			(35U + 32U)
+#define XPS_SPI0_INT_ID			(37U + 32U)
+#define XPS_UART0_INT_ID		(39U + 32U)
+#define XPS_CAN0_INT_ID			(41U + 32U)
+
+/* FIXME */
+/*#define XPS_FPGA0_INT_ID		100U */
+
+#define XPS_TTC1_0_INT_ID		(56U + 32U)
+#define XPS_TTC1_1_INT_ID		(57U + 32U)
+#define XPS_TTC1_2_INT_ID		(58U + 32U)
+#define XPS_TTC2_0_INT_ID		(59U + 32U)
+#define XPS_TTC2_1_INT_ID		(60U + 32U)
+#define XPS_TTC2_2_INT_ID		(61U + 32U)
+#define XPS_TTC3_0_INT_ID		(62U + 32U)
+#define XPS_TTC3_1_INT_ID		(63U + 32U)
+#define XPS_TTC3_2_INT_ID		(64U + 32U)
+#define XPS_SDIO1_INT_ID		(66U + 32U)
+#define XPS_I2C1_INT_ID			(36U + 32U)
+#define XPS_SPI1_INT_ID			(38U + 32U)
+#define XPS_UART1_INT_ID		(40U + 32U)
+#define XPS_CAN1_INT_ID			(42U + 32U)
+#define XPS_GEM0_INT_ID			(73U + 32U)
+#define XPS_GEM0_WAKE_INT_ID		(74U + 32U)
+#define XPS_GEM1_INT_ID			(75U + 32U)
+#define XPS_GEM1_WAKE_INT_ID		(76U + 32U)
+#define XPS_GEM2_INT_ID			(77U + 32U)
+#define XPS_GEM2_WAKE_INT_ID		(78U + 32U)
+#define XPS_GEM3_INT_ID			(79U + 32U)
+#define XPS_GEM3_WAKE_INT_ID		(80U + 32U)
+
+/* Private Peripheral Interrupts (PPI) */
+/*#define XPS_GLOBAL_TMR_INT_ID		27U	 SCU Global Timer interrupt */
+/*#define XPS_FIQ_INT_ID			28U	 FIQ from FPGA fabric */
+/*#define XPS_SCU_TMR_INT_ID		29U	 SCU Private Timer interrupt */
+/*#define XPS_SCU_WDT_INT_ID		30U	 SCU Private WDT interrupt */
+/*#define XPS_IRQ_INT_ID			31U	 IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR		XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR		XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR		XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR		XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR	XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR	XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_2_INTR	XPS_GEM2_INT_ID
+#define XPAR_PS7_ETHERNET_2_WAKE_INTR	XPS_GEM2_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_3_INTR	XPS_GEM3_INT_ID
+#define XPAR_PS7_ETHERNET_3_WAKE_INTR	XPS_GEM3_WAKE_INT_ID
+
+#define XPAR_PS7_QSPI_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR		XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR	XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR		XPS_SYSMON_INT_ID
+
+#define XPAR_XADCPS_NUM_INSTANCES 1U
+#define XPAR_XADCPS_0_DEVICE_ID   0U
+#define XPAR_XADCPS_0_BASEADDR	  (0xF8007000U)
+#define XPAR_XADCPS_INT_ID		XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ		XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ		XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ		XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ		XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ		XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ		XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ		XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ		XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ		XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ		XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ		XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID		0U
+#define XPAR_SCUWDT_DEVICE_ID		0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/lib/bsp/standalone/src/cortexa53/xpseudo_asm.h b/lib/bsp/standalone/src/cortexa53/xpseudo_asm.h
new file mode 100644
index 00000000..c401345d
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/xpseudo_asm.h
@@ -0,0 +1,68 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* This header file contains macros for using inline assembler code.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H
+#define XPSEUDO_ASM_H
+#include "xreg_cortexa53.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
+
+#endif /* XPSEUDO_ASM_H */
diff --git a/lib/bsp/standalone/src/cortexa53/xreg_cortexa53.h b/lib/bsp/standalone/src/cortexa53/xreg_cortexa53.h
new file mode 100644
index 00000000..70319c30
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/xreg_cortexa53.h
@@ -0,0 +1,226 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa53.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+* All of the ARM Cortex A53 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+******************************************************************************/
+#ifndef XREG_CORTEXA53_H
+#define XREG_CORTEXA53_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/* GPRs */
+#define XREG_GPR0				r0
+#define XREG_GPR1				r1
+#define XREG_GPR2				r2
+#define XREG_GPR3				r3
+#define XREG_GPR4				r4
+#define XREG_GPR5				r5
+#define XREG_GPR6				r6
+#define XREG_GPR7				r7
+#define XREG_GPR8				r8
+#define XREG_GPR9				r9
+#define XREG_GPR10				r10
+#define XREG_GPR11				r11
+#define XREG_GPR12				r12
+#define XREG_GPR13				r13
+#define XREG_GPR14				r14
+#define XREG_GPR15				r15
+#define XREG_CPSR				cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0				0
+#define XREG_CP1				1
+#define XREG_CP2				2
+#define XREG_CP3				3
+#define XREG_CP4				4
+#define XREG_CP5				5
+#define XREG_CP6				6
+#define XREG_CP7				7
+#define XREG_CP8				8
+#define XREG_CP9				9
+#define XREG_CP10				10
+#define XREG_CP11				11
+#define XREG_CP12				12
+#define XREG_CP13				13
+#define XREG_CP14				14
+#define XREG_CP15				15
+
+/* Coprocessor control register defines */
+#define XREG_CR0				cr0
+#define XREG_CR1				cr1
+#define XREG_CR2				cr2
+#define XREG_CR3				cr3
+#define XREG_CR4				cr4
+#define XREG_CR5				cr5
+#define XREG_CR6				cr6
+#define XREG_CR7				cr7
+#define XREG_CR8				cr8
+#define XREG_CR9				cr9
+#define XREG_CR10				cr10
+#define XREG_CR11				cr11
+#define XREG_CR12				cr12
+#define XREG_CR13				cr13
+#define XREG_CR14				cr14
+#define XREG_CR15				cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE			0x20
+#define XREG_CPSR_MODE_BITS			0x1F
+#define XREG_CPSR_SYSTEM_MODE			0x1F
+#define XREG_CPSR_UNDEFINED_MODE		0x1B
+#define XREG_CPSR_DATA_ABORT_MODE		0x17
+#define XREG_CPSR_SVC_MODE			0x13
+#define XREG_CPSR_IRQ_MODE			0x12
+#define XREG_CPSR_FIQ_MODE			0x11
+#define XREG_CPSR_USER_MODE			0x10
+
+#define XREG_CPSR_IRQ_ENABLE			0x80
+#define XREG_CPSR_FIQ_ENABLE			0x40
+
+#define XREG_CPSR_N_BIT				0x80000000U
+#define XREG_CPSR_Z_BIT				0x40000000U
+#define XREG_CPSR_C_BIT				0x20000000U
+#define XREG_CPSR_V_BIT				0x10000000U
+
+
+
+/* MPE register definitions */
+#define XREG_FPSID				c0
+#define XREG_FPSCR				c1
+#define XREG_MVFR1				c6
+#define XREG_MVFR0				c7
+#define XREG_FPEXC				c8
+#define XREG_FPINST				c9
+#define XREG_FPINST2				c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT	(24U)
+#define XREG_FPSID_IMPLEMENTER_MASK	(0x000000FFU << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE		(0X00000001U<<23U)
+#define XREG_FPSID_ARCH_BIT		(16U)
+#define XREG_FPSID_ARCH_MASK		(0x0000000FU  << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT		(8U)
+#define XREG_FPSID_PART_MASK		(0x000000FFU << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT		(4U)
+#define XREG_FPSID_VARIANT_MASK		(0x0000000FU  << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT		(0U)
+#define XREG_FPSID_REV_MASK		(0x0000000FU  << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT		(0X00000001U << 31U)
+#define XREG_FPSCR_Z_BIT		(0X00000001U << 30U)
+#define XREG_FPSCR_C_BIT		(0X00000001U << 29U)
+#define XREG_FPSCR_V_BIT		(0X00000001U << 28U)
+#define XREG_FPSCR_QC			(0X00000001U << 27U)
+#define XREG_FPSCR_AHP			(0X00000001U << 26U)
+#define XREG_FPSCR_DEFAULT_NAN		(0X00000001U << 25U)
+#define XREG_FPSCR_FLUSHTOZERO		(0X00000001U << 24U)
+#define XREG_FPSCR_ROUND_NEAREST	(0X00000000U << 22U)
+#define XREG_FPSCR_ROUND_PLUSINF	(0X00000001U << 22U)
+#define XREG_FPSCR_ROUND_MINUSINF	(0X00000002U << 22U)
+#define XREG_FPSCR_ROUND_TOZERO		(0X00000003U << 22U)
+#define XREG_FPSCR_RMODE_BIT		(22U)
+#define XREG_FPSCR_RMODE_MASK		(0X00000003U << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT		(20U)
+#define XREG_FPSCR_STRIDE_MASK		(0X00000003U << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT		(16U)
+#define XREG_FPSCR_LENGTH_MASK		(0X00000007U << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC			(0X00000001U << 7U)
+#define XREG_FPSCR_IXC			(0X00000001U << 4U)
+#define XREG_FPSCR_UFC			(0X00000001U << 3U)
+#define XREG_FPSCR_OFC			(0X00000001U << 2U)
+#define XREG_FPSCR_DZC			(0X00000001U << 1U)
+#define XREG_FPSCR_IOC			(0X00000001U << 0U)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT		(28U)
+#define XREG_MVFR0_RMODE_MASK		(0x0000000FU << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT	(24U)
+#define XREG_MVFR0_SHORT_VEC_MASK	(0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT		(20U)
+#define XREG_MVFR0_SQRT_MASK		(0x0000000FU << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT		(16U)
+#define XREG_MVFR0_DIVIDE_MASK		(0x0000000FU << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT	(0X00000012U)
+#define XREG_MVFR0_EXEC_TRAP_MASK	(0X0000000FU << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT		(8U)
+#define XREG_MVFR0_DP_MASK		(0x0000000FU << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT		(4U)
+#define XREG_MVFR0_SP_MASK		(0x0000000FU << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT		(0U)
+#define XREG_MVFR0_A_SIMD_MASK		(0x0000000FU << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX			(0X00000001U << 31U)
+#define XREG_FPEXC_EN			(0X00000001U << 30U)
+#define XREG_FPEXC_DEX			(0X00000001U << 29U)
+
+
+#define XREG_CONTROL_DCACHE_BIT	(0X00000001U<<2U)
+#define XREG_CONTROL_ICACHE_BIT	(0X00000001U<<12U)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA53_H */
diff --git a/lib/bsp/standalone/src/cortexa53/xstatus.h b/lib/bsp/standalone/src/cortexa53/xstatus.h
new file mode 100644
index 00000000..2737c63d
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/xstatus.h
@@ -0,0 +1,441 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* This file contains Xilinx software status codes.  Status codes have their
+* own data type called int.  These codes are used throughout the Xilinx
+* device drivers.
+*
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/* an error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/* an error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/* a DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/* the device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/* a FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/* the buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/* there was no data available */
+#define XST_REGISTER_ERROR              14L	/* a register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/* an invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/* the device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/* a loopback test failed */
+#define XST_NO_CALLBACK                 18L	/* a callback has not yet been
+						   registered */
+#define XST_NO_FEATURE                  19L	/* device is not configured with
+						   the requested feature */
+#define XST_NOT_INTERRUPT               20L	/* device is not configured for
+						   interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/* device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/* the error counters of a device
+						   have maxed out */
+#define XST_IS_STARTED                  23L	/* used when part of device is
+						   already started i.e.
+						   sub channel */
+#define XST_IS_STOPPED                  24L	/* used when part of device is
+						   already stopped i.e.
+						   sub channel */
+#define XST_DATA_LOST                   26L	/* driver defined error */
+#define XST_RECV_ERROR                  27L	/* generic receive error */
+#define XST_SEND_ERROR                  28L	/* generic transmit error */
+#define XST_NOT_ENABLED                 29L	/* a requested service is not
+						   available because it has not
+						   been enabled */
+
+/***************** Utility Component statuses 401 - 500  *********************/
+
+#define XST_MEMTEST_FAILED              401L	/* memory test failed */
+
+
+/***************** Common Components statuses 501 - 1000 *********************/
+
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/* not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/* not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/* self test, a register value
+						   was invalid after reset */
+#define XST_PFIFO_ERROR                 504L	/* generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK              505L	/* packet FIFO is reporting
+						 * empty and full simultaneously
+						 */
+
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/* self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/* self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/* scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/* scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/* scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/* all the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/* the scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/* no buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/* the packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/* the scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/* no scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/* the buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/* the buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+#define XST_DMA_SG_LIST_ERROR           526L	/* general purpose list access
+						   error */
+#define XST_DMA_BD_ERROR                527L	/* general buffer descriptor
+						   error */
+
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/* an invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/* the value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/* a write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/* the device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/* the device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/* a write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/* the IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/* IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/* The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/* The device interrupt ID register
+						   did not indicate the expected
+						   value */
+#define XST_IPIF_ERROR                  541L	/* generic ipif error */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/* Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/* Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/* MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/* An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/* Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/* Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/* Excess deferral or late
+						 * collision on polled send */
+
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/* self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/* bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/* mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/* A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/* Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/* Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/* 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/* Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/* Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/* Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/* The device isn't a slave    */
+
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/* the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/* Flash is erasing or programming
+						 */
+#define XST_FLASH_READY               1127L	/* Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/* Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes
+						 */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/* Flash is in suspended erase state
+						 */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/* Flash is in suspended write state
+						 */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/* Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/* Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/* Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/* Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/* Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/* Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/* Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/* Failed to query the device */
+
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/* master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/* data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/* slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/* device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/* no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/* more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/* operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/* device is configured as slave-only
+						 */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/* slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE          1160	/* device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/* device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR       1162	/* unrecognised command - qspi only */
+
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/* the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/* an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/* bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/* the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/* self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/* interrupt already in use */
+
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/* self test failed */
+
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/* No MPU lock has been granted */
+
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR			1400
+#define XST_FR_TX_BUSY			1401
+#define XST_FR_BUF_LOCKED		1402
+#define XST_FR_NO_BUF			1403
+
+/****************** USB constants 1410 - 1420  *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED	1410
+#define XST_USB_BUF_ALIGN_ERROR		1411
+#define XST_USB_NO_DESC_AVAILABLE	1412
+#define XST_USB_BUF_TOO_BIG		1413
+#define XST_USB_NO_BUF			1414
+
+/****************** HWICAP constants 1421 - 1429  *****************************/
+
+#define XST_HWICAP_WRITE_DONE		1421
+
+
+/****************** AXI VDMA constants 1430 - 1440  *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR		1430
+
+/*********************** NAND Flash statuses 1441 - 1459  *********************/
+
+#define XST_NAND_BUSY			1441L	/* Flash is erasing or
+						 * programming
+						 */
+#define XST_NAND_READY			1442L	/* Flash is ready for commands
+						 */
+#define XST_NAND_ERROR			1443L	/* Flash had detected an
+						 * internal error.
+						 */
+#define XST_NAND_PART_NOT_SUPPORTED	1444L	/* Flash type not supported by
+						 * driver
+						 */
+#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/* Operation not supported
+						 */
+#define XST_NAND_TIMEOUT_ERROR		1446L	/* Programming or erase
+						 * operation aborted due to a
+						 * timeout
+						 */
+#define XST_NAND_ADDRESS_ERROR		1447L	/* Accessed flash outside its
+						 * addressible range
+						 */
+#define XST_NAND_ALIGNMENT_ERROR	1448L	/* Write alignment error
+						 */
+#define XST_NAND_PARAM_PAGE_ERROR	1449L	/* Failed to read parameter
+						 * page of the device
+						 */
+#define XST_NAND_CACHE_ERROR		1450L	/* Flash page buffer error
+						 */
+
+#define XST_NAND_WRITE_PROTECTED	1451L	/* Flash is write protected
+						 */
+
+/**************************** Type Definitions *******************************/
+
+typedef int XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/lib/bsp/standalone/src/cortexa53/xtime_l.c b/lib/bsp/standalone/src/cortexa53/xtime_l.c
new file mode 100644
index 00000000..0f9a75cc
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/xtime_l.c
@@ -0,0 +1,111 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.c
+*
+* This file contains low level functions to get/set time from the Global Timer
+* register in the ARM Cortex A53 MP core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 

+*
+* @note		None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************
+*
+* Set the time in the Global Timer Counter Register.
+*
+* @param	Value to be written to the Global Timer Counter Register.
+*
+* @return	None.
+*
+* @note		In multiprocessor environment reference time will reset/lost for
+*		all processors, when this function called by any one processor.
+*
+****************************************************************************/
+void XTime_SetTime(XTime Xtime_Global)
+{
+/*As the generic timer of A53 runs constantly time can not be set as desired
+so the API is left unimplemented*/
+}
+
+/****************************************************************************
+*
+* Get the time from the Global Timer Counter Register.
+*
+* @param	Pointer to the location to be updated with the time.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XTime_GetTime(XTime *Xtime_Global)
+{
+	*Xtime_Global = mfcp(CNTPCT_EL0);
+}
diff --git a/lib/bsp/standalone/src/cortexa53/xtime_l.h b/lib/bsp/standalone/src/cortexa53/xtime_l.h
new file mode 100644
index 00000000..bb81c6ba
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/xtime_l.h
@@ -0,0 +1,92 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information  of Xilinx, Inc.
+* and is protected under U.S. and  international copyright and other
+* intellectual property  laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any  rights to the
+* materials distributed herewith. Except as  otherwise provided in a valid
+* license issued to you by  Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND  WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES  AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort,  including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature  related to, arising under or in connection with these
+* materials, including for any direct, or any indirect,  special, incidental,
+* or consequential loss or damage  (including loss of data, profits, goodwill,
+* or any type of  loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was  reasonably foreseeable
+* or Xilinx had been advised of the  possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe  performance, such as life-support or
+* safety devices or  systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any  other applications
+* that could lead to death, personal  injury, or severe property or environmental
+* damage  (individually and collectively, "Critical  Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical  Applications, subject only to applicable laws and  regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 5.00 	pkp	   05/29/14 First release
+* 

+*
+* @note		None.
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+typedef u64 XTime;
+
+/************************** Constant Definitions *****************************/
+
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_SECOND          0x007A1200U
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
diff --git a/lib/bsp/standalone/src/cortexa9/armcc/ARM_argv_veneer.c b/lib/bsp/standalone/src/cortexa9/armcc/ARM_argv_veneer.c
old mode 100755
new mode 100644
diff --git a/lib/bsp/standalone/src/cortexa9/armcc/Makefile b/lib/bsp/standalone/src/cortexa9/armcc/Makefile
old mode 100755
new mode 100644
index b41825b6..edc0a08c
--- a/lib/bsp/standalone/src/cortexa9/armcc/Makefile
+++ b/lib/bsp/standalone/src/cortexa9/armcc/Makefile
@@ -67,15 +67,15 @@ OBJECTS = $(OBJS)
 libs: boot_libs banner $(LIBS)
 
 boot_libs:
-ifeq ($(findstring boot.S,$(wildcard *.S)),boot.S) 
+ifeq ($(findstring boot.S,$(wildcard *.S)),boot.S)
 	${COMPILER} $(INCLUDES) -E -o boot_post.s boot.S
 endif
 	${AS} --cpu=Cortex-A9 --fpu=VFPv3_FP16 -o boot_post.o boot_post.s
-	rm -f boot.S 
+	rm -f boot.S
 
 $(AOBJS1): $(ASOURCES1)
 	${AS} --cpu=Cortex-A9 --fpu=VFPv3_FP16 -o $@ $<
-	
+
 $(AOBJS2): $(ASOURCES2)
 	${AS} --cpu=Cortex-A9 --fpu=VFPv3_FP16 -o $@ $<
 
diff --git a/lib/bsp/standalone/src/cortexa9/armcc/_sys_close.c b/lib/bsp/standalone/src/cortexa9/armcc/_sys_close.c
old mode 100755
new mode 100644
index 975aedf5..f78348c9
--- a/lib/bsp/standalone/src/cortexa9/armcc/_sys_close.c
+++ b/lib/bsp/standalone/src/cortexa9/armcc/_sys_close.c
@@ -1,6 +1,6 @@
-
-// Stuv for close() sys-call
-__weak int _sys_close(int fh)
+#include "xil_types.h"
+/* Stuv for close() sys-call */
+__weak s32 _sys_close(s32 fh)
 {
    return -1;
 }
diff --git a/lib/bsp/standalone/src/cortexa9/armcc/_sys_exit.c b/lib/bsp/standalone/src/cortexa9/armcc/_sys_exit.c
old mode 100755
new mode 100644
index b1235b81..245e5d38
--- a/lib/bsp/standalone/src/cortexa9/armcc/_sys_exit.c
+++ b/lib/bsp/standalone/src/cortexa9/armcc/_sys_exit.c
@@ -1,6 +1,8 @@
-
-// Stuv for exit() sys-call
-__weak void _sys_exit(int rc)
+#include "xil_types.h"
+/* Stuv for exit() sys-call */
+__weak void _sys_exit(s32 rc)
 {
-   while(1);
+   while(1) {
+		;
+	}
 }
diff --git a/lib/bsp/standalone/src/cortexa9/armcc/_sys_iserror.c b/lib/bsp/standalone/src/cortexa9/armcc/_sys_iserror.c
old mode 100755
new mode 100644
index c6fbb978..0bba57f3
--- a/lib/bsp/standalone/src/cortexa9/armcc/_sys_iserror.c
+++ b/lib/bsp/standalone/src/cortexa9/armcc/_sys_iserror.c
@@ -1,9 +1,10 @@
-
-// Stub for iserror() function
-__weak int _sys_iserror(int status)
+#include "xil_types.h"
+/* Stub for iserror() function */
+__weak s32 _sys_iserror(s32 status)
 {
-   if(status<0)
+   if(status<0) {
       return 1;
+	}
 
    return 0;
 }
diff --git a/lib/bsp/standalone/src/cortexa9/armcc/_sys_istty.c b/lib/bsp/standalone/src/cortexa9/armcc/_sys_istty.c
old mode 100755
new mode 100644
index e2fa4834..f41ad0a8
--- a/lib/bsp/standalone/src/cortexa9/armcc/_sys_istty.c
+++ b/lib/bsp/standalone/src/cortexa9/armcc/_sys_istty.c
@@ -1,7 +1,7 @@
-
-// Stub for istty sys-call
-__weak int _sys_istty(unsigned int* f)
-{ 
+#include "xil_types.h"
+/* Stub for istty sys-call */
+__weak s32 _sys_istty(u32* f)
+{
    /* cannot read/write files */
    return 1;
 }
diff --git a/lib/bsp/standalone/src/cortexa9/armcc/_sys_open.c b/lib/bsp/standalone/src/cortexa9/armcc/_sys_open.c
old mode 100755
new mode 100644
index 9845f1aa..851798ac
--- a/lib/bsp/standalone/src/cortexa9/armcc/_sys_open.c
+++ b/lib/bsp/standalone/src/cortexa9/armcc/_sys_open.c
@@ -1,6 +1,6 @@
-
-// Stub for open sys-call
-__weak int _sys_open(const char* name, int openmode)
+#include "xil_types.h"
+/* Stub for open sys-call */
+__weak s32 _sys_open(const char8* name, s32 openmode)
 {
    return 0;
 }
diff --git a/lib/bsp/standalone/src/cortexa9/armcc/_sys_read.c b/lib/bsp/standalone/src/cortexa9/armcc/_sys_read.c
old mode 100755
new mode 100644
index c1a5292e..6c36bb97
--- a/lib/bsp/standalone/src/cortexa9/armcc/_sys_read.c
+++ b/lib/bsp/standalone/src/cortexa9/armcc/_sys_read.c
@@ -1,7 +1,7 @@
-
-// Stub for read() sys-call
-__weak int _sys_read(unsigned int fh, unsigned char *buf, unsigned int len, int mode)
+#include "xil_types.h"
+/* Stub for read() sys-call */
+__weak s32 _sys_read(u32 fh, u8 *buf, u32 len, s32 mode)
 {
-   // Return the number of character NOT read
+   /* Return the number of character NOT read */
    return len;
 }
diff --git a/lib/bsp/standalone/src/cortexa9/armcc/_sys_write.c b/lib/bsp/standalone/src/cortexa9/armcc/_sys_write.c
old mode 100755
new mode 100644
index 33e28622..4297c0e9
--- a/lib/bsp/standalone/src/cortexa9/armcc/_sys_write.c
+++ b/lib/bsp/standalone/src/cortexa9/armcc/_sys_write.c
@@ -1,15 +1,18 @@
+#include "xil_types.h"
 #include "xparameters.h"
 
-__weak int _sys_write(unsigned int fh, const unsigned char *buf, unsigned int len, int mode)
+__weak s32 _sys_write(u32 fh, const u8 *buf, u32 len, s32 mode)
 {
 #ifdef STDOUT_BASEADDRESS
-  unsigned int volatile *uart_base = (unsigned int *)STDOUT_BASEADDRESS;
-  int i;
+  u32 volatile *uart_base = (u32 *)STDOUT_BASEADDRESS;
+  s32 i;
 
   for (i =0; i < len;i++) {
     /* wait if TNFUL */
-    while (*(uart_base + 11) & (1 << 14)) ;
-    *(uart_base + 12) = buf[i];
+    while (*(uart_base + 11U) & (1U << 14U)) {
+		;
+	}
+    *(uart_base + 12U) = buf[i];
   }
 #endif
   return 0;
diff --git a/lib/bsp/standalone/src/cortexa9/armcc/asm_vectors.s b/lib/bsp/standalone/src/cortexa9/armcc/asm_vectors.s
old mode 100755
new mode 100644
index 30c6fae1..681a23af
--- a/lib/bsp/standalone/src/cortexa9/armcc/asm_vectors.s
+++ b/lib/bsp/standalone/src/cortexa9/armcc/asm_vectors.s
@@ -1,4 +1,3 @@
-;* $Id: asm_vectors.s,v 1.1.4.1 2011/10/24 09:35:17 sadanan Exp $
 ;******************************************************************************
 ;
 ; Copyright (C) 2009 - 2014 Xilinx, Inc.  All rights reserved.
@@ -43,8 +42,8 @@
 ; ----- ------- -------- ---------------------------------------------------
 ; 1.00a ecm/sdm 10/20/09 Initial version
 ; 3.11a asa	9/17/13	 Added support for neon.
-; 4.00  pkp	01/22/14 Modified return addresses for interrupt 
-;			 handlers 
+; 4.00  pkp	01/22/14 Modified return addresses for interrupt
+;			 handlers
 ;
; ; @note @@ -79,8 +78,8 @@ _vector_table B FIQHandler -IRQHandler ; IRQ vector handler - +IRQHandler ; IRQ vector handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code vpush {d0-d7} vpush {d16-d31} @@ -95,12 +94,12 @@ IRQHandler ; IRQ vector handler vmsr FPSCR, r1 vpop {d16-d31} vpop {d0-d7} - ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code - subs pc, lr, #4 ; adjust return + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #4 ; adjust return -FIQHandler ; FIQ vector handler - stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code +FIQHandler ; FIQ vector handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code vpush {d0-d7} vpush {d16-d31} vmrs r1, FPSCR @@ -108,48 +107,48 @@ FIQHandler ; FIQ vector handler vmrs r1, FPEXC push {r1} FIQLoop - bl FIQInterrupt ; FIQ vector + bl FIQInterrupt ; FIQ vector pop {r1} vmsr FPEXC, r1 pop {r1} vmsr FPSCR, r1 vpop {d16-d31} vpop {d0-d7} - ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code - subs pc, lr, #4 ; adjust return + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #4 ; adjust return -Undefined ; Undefined handler - stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code - ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code - b _prestart +Undefined ; Undefined handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + b _prestart movs pc, lr -SVCHandler ; SWI handler - stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code - tst r0, #0x20 ; check the T bit - ldrneh r0, [lr,#-2] ; Thumb mode - bicne r0, r0, #0xff00 ; Thumb mode - ldreq r0, [lr,#-4] ; ARM mode - biceq r0, r0, #0xff000000 ; ARM mode - bl SWInterrupt ; SWInterrupt: call C function here - ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code - movs pc, lr ; adjust return +SVCHandler ; SWI handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + tst r0, #0x20 ; check the T bit + ldrneh r0, [lr,#-2] ; Thumb mode + bicne r0, r0, #0xff00 ; Thumb mode + ldreq r0, [lr,#-4] ; ARM mode + biceq r0, r0, #0xff000000 ; ARM mode + bl SWInterrupt ; SWInterrupt: call C function here + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + movs pc, lr ; adjust return -DataAbortHandler ; Data Abort handler - stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code - bl DataAbortInterrupt ;DataAbortInterrupt :call C function here - ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code - subs pc, lr, #8 ; adjust return +DataAbortHandler ; Data Abort handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + bl DataAbortInterrupt ;DataAbortInterrupt :call C function here + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #8 ; adjust return -PrefetchAbortHandler ; Prefetch Abort handler - stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code - bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here - ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code - subs pc, lr, #4 ; adjust return +PrefetchAbortHandler ; Prefetch Abort handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #4 ; adjust return END diff --git a/lib/bsp/standalone/src/cortexa9/armcc/boot.S b/lib/bsp/standalone/src/cortexa9/armcc/boot.S old mode 100755 new mode 100644 index 79d2016d..932977b8 --- a/lib/bsp/standalone/src/cortexa9/armcc/boot.S +++ b/lib/bsp/standalone/src/cortexa9/armcc/boot.S @@ -1,4 +1,3 @@ -;* $Id: boot.S,v 1.1.4.1 2011/10/24 09:35:18 sadanan Exp $ ;****************************************************************************** ; ; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. @@ -43,7 +42,7 @@ ; ----- ------- -------- --------------------------------------------------- ; 1.00a ecm/sdm 10/20/09 Initial version ; 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values -; 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control +; 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control ; register settings. ; 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary ; register settings. @@ -100,27 +99,27 @@ SLCRlockKey EQU 0x767B /* SLCR lock key */ SLCRUnlockKey EQU 0xDF0D /* SLCR unlock key */ SLCRL2cRamConfig EQU 0x00020202 /* SLCR L2C ram configuration */ -CRValMmuCac EQU 2_01000000000101 ; Enable IDC, and MMU -CRValHiVectorAddr EQU 2_10000000000000 ; Set the Vector address to high, 0xFFFF0000 +CRValMmuCac EQU 2_01000000000101 ; Enable IDC, and MMU +CRValHiVectorAddr EQU 2_10000000000000 ; Set the Vector address to high, 0xFFFF0000 -L2CCAuxControl EQU 0x72360000 ; Enable all prefetching, Way Size (16 KB) and High Priority for SO and Dev Reads Enable -L2CCControl EQU 0x01 ; Enable L2CC -L2CCTAGLatency EQU 0x0111 ; 7 Cycles of latency for TAG RAM -L2CCDataLatency EQU 0x0121 ; 7 Cycles of latency for DATA RAM +L2CCAuxControl EQU 0x72360000 ; Enable all prefetching, Way Size (16 KB) and High Priority for SO and Dev Reads Enable +L2CCControl EQU 0x01 ; Enable L2CC +L2CCTAGLatency EQU 0x0111 ; 7 Cycles of latency for TAG RAM +L2CCDataLatency EQU 0x0121 ; 7 Cycles of latency for DATA RAM -FPEXC_EN EQU 0x40000000 ; FPU enable bit, (1 << 30) +FPEXC_EN EQU 0x40000000 ; FPU enable bit, (1 << 30) AREA |.boot|, CODE PRESERVE8 -; this initializes the various processor modes +; this initializes the various processor modes _prestart _boot #if XPAR_CPU_ID==0 -; only allow cp0 through +; only allow cp0 through mrc p15,0,r1,c0,c0,5 and r1, r1, #0xf cmp r1, #0 @@ -130,7 +129,7 @@ EndlessLoop0 b EndlessLoop0 #elif XPAR_CPU_ID==1 -; only allow cp1 through +; only allow cp1 through mrc p15,0,r1,c0,c0,5 and r1, r1, #0xf cmp r1, #1 @@ -142,24 +141,24 @@ EndlessLoop1 OKToRun mrc p15, 0, r0, c0, c0, 0 /* Get the revision */ - and r5, r0, #0x00f00000 + and r5, r0, #0x00f00000 and r6, r0, #0x0000000f orr r6, r6, r5, lsr #20-4 - + #ifdef CONFIG_ARM_ERRATA_742230 cmp r6, #0x22 /* only present up to r2p2 */ mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */ orrle r10, r10, #1 << 4 /* set bit #4 */ mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */ #endif - + #ifdef CONFIG_ARM_ERRATA_743622 teq r5, #0x00200000 /* only present in r2p* */ mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */ orreq r10, r10, #1 << 6 /* set bit #6 */ mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */ #endif - + /* set VBAR to the _vector_table address in scatter file */ ldr r0, =_vector_table mcr p15, 0, r0, c12, c0, 0 @@ -175,18 +174,18 @@ OKToRun ldr r6, =0xffff str r6, [r7] - ; Write to ACTLR + ; Write to ACTLR mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR orr r0, r0, #(0x01 << 6) ; SMP bit - orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast + orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast mcr p15, 0,r0, c1, c0, 1 ; Write ACTLR -; Invalidate caches and TLBs - mov r0,#0 ; r0 = 0 - mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs - mcr p15, 0, r0, c7, c5, 0 ; invalidate icache - mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array - bl invalidate_dcache ; invalidate dcache +; Invalidate caches and TLBs + mov r0,#0 ; r0 = 0 + mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs + mcr p15, 0, r0, c7, c5, 0 ; invalidate icache + mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array + bl invalidate_dcache ; invalidate dcache ; Invalidate L2c Cache ; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) @@ -216,21 +215,21 @@ OKToRun ldr r0,=L2CCSync ; need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET ; Load L2CC base address base + sync register ; poll for completion -Sync +Sync ldr r1, [r0] cmp r1, #0 bne Sync ldr r0,=L2CCIntRaw ; clear pending interrupts ldr r1,[r0] - ldr r0,=L2CCIntClear + ldr r0,=L2CCIntClear str r1,[r0] #endif - ; Disable MMU, if enabled - mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1 - bic r0, r0, #0x1 ; clear bit 0 - mcr p15, 0, r0, c1, c0, 0 ; write value back + ; Disable MMU, if enabled + mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1 + bic r0, r0, #0x1 ; clear bit 0 + mcr p15, 0, r0, c1, c0, 0 ; write value back #ifdef SHAREABLE_DDR ; Mark the entire DDR memory as shareable @@ -259,12 +258,12 @@ mmu_loop: bge mmu_loop ; loop till 512MB is covered #endif - mrs r0, cpsr ; get the current PSR - mvn r1, #0x1f ; set up the irq stack pointer + mrs r0, cpsr ; get the current PSR + mvn r1, #0x1f ; set up the irq stack pointer and r2, r1, r0 - orr r2, r2, #0x12 ; IRQ mode + orr r2, r2, #0x12 ; IRQ mode msr apsr, r2 ; was cpsr, apsr is considered synonym - ldr r13,=|Image$$IRQ_STACK$$ZI$$Limit| ; IRQ stack pointer + ldr r13,=|Image$$IRQ_STACK$$ZI$$Limit| ; IRQ stack pointer mrs r0, cpsr ; get the current PSR mvn r1, #0x1f ; set up the supervisor stack pointer @@ -280,43 +279,43 @@ mmu_loop: msr apsr, r2 ; was cpsr, apsr is considered synonym ldr r13,=|Image$$ABORT_STACK$$ZI$$Limit| ; Abort stack pointer - mrs r0, cpsr ; get the current PSR - mvn r1, #0x1f ; set up the system stack pointer + mrs r0, cpsr ; get the current PSR + mvn r1, #0x1f ; set up the system stack pointer and r2, r1, r0 - orr r2, r2, #0x1f ; SYS mode + orr r2, r2, #0x1f ; SYS mode msr apsr, r2 ; was cpsr, apsr is considered synonym - ldr r13,=|Image$$ARM_LIB_STACK$$ZI$$Limit| ; SYS stack pointer + ldr r13,=|Image$$ARM_LIB_STACK$$ZI$$Limit| ; SYS stack pointer - ; enable MMU and cache + ; enable MMU and cache + + ldr r0,=MMUTable ; Load MMU translation table base + orr r0, r0, #0x5B ; Outer-cacheable, WB + mcr p15, 0, r0, c2, c0, 0 ; TTB0 - ldr r0,=MMUTable ; Load MMU translation table base - orr r0, r0, #0x5B ; Outer-cacheable, WB - mcr p15, 0, r0, c2, c0, 0 ; TTB0 - mvn r0,#0 mcr p15,0,r0,c3,c0,0 ; Enable mmu, icahce and dcache ldr r0,=CRValMmuCac - mcr p15,0,r0,c1,c0,0 ; Enable cache and MMU - dsb ; dsb allow the MMU to start up - isb ; isb flush prefetch buffer + mcr p15,0,r0,c1,c0,0 ; Enable cache and MMU + dsb ; dsb allow the MMU to start up + isb ; isb flush prefetch buffer ; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) #if USE_AMP!=1 ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */ ldr r1,=SLCRUnlockKey /* set unlock key */ str r1, [r0] /* Unlock SLCR */ - + ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */ ldr r1,=SLCRL2cRamConfig /* set the configuration value */ str r1, [r0] /* store the L2c Ram Control Register */ - + ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */ ldr r1,=SLCRlockKey /* set lock key */ str r1, [r0] /* lock SLCR */ - + ldr r0,=L2CCCrtl ; Load L2CC base address base + control register ldr r1,[r0] ; read the register mov r2, #L2CCControl ; set the enable bit @@ -325,28 +324,28 @@ mmu_loop: #endif mov r0, r0 - mrc p15, 0, r1, c1, c0, 2 ; read cp access control register (CACR) into r1 - orr r1, r1, #(0xf << 20) ; enable full access for p10 & p11 - mcr p15, 0, r1, c1, c0, 2 ; write back into CACR + mrc p15, 0, r1, c1, c0, 2 ; read cp access control register (CACR) into r1 + orr r1, r1, #(0xf << 20) ; enable full access for p10 & p11 + mcr p15, 0, r1, c1, c0, 2 ; write back into CACR - ; enable vfp - fmrx r1, FPEXC ; read the exception register - orr r1,r1, #FPEXC_EN ; set VFP enable bit, leave the others in orig state - fmxr FPEXC, r1 ; write back the exception register + ; enable vfp + fmrx r1, FPEXC ; read the exception register + orr r1,r1, #FPEXC_EN ; set VFP enable bit, leave the others in orig state + fmxr FPEXC, r1 ; write back the exception register - mrc p15, 0, r0, c1, c0, 0 ; flow prediction enable + mrc p15, 0, r0, c1, c0, 0 ; flow prediction enable orr r0, r0, #(0x01 << 11) ; #0x8000 mcr p15,0,r0,c1,c0,0 - mrc p15, 0, r0, c1, c0, 1 ; read Auxiliary Control Register - orr r0, r0, #(0x1 << 2) ; enable Dside prefetch - orr r0, r0, #(0x1 << 1) ; enable L2 prefetch - mcr p15, 0, r0, c1, c0, 1 ; write Auxiliary Control Register - + mrc p15, 0, r0, c1, c0, 1 ; read Auxiliary Control Register + orr r0, r0, #(0x1 << 2) ; enable Dside prefetch + orr r0, r0, #(0x1 << 1) ; enable L2 prefetch + mcr p15, 0, r0, c1, c0, 1 ; write Auxiliary Control Register + mrs r0, cpsr /* get the current PSR */ bic r0, r0, #0x100 /* enable asynchronous abort exception */ msr cpsr_xsf, r0 - + ; Clear cp15 regs with unknown reset values mov r0, #0x0 mcr p15, 0, r0, c5, c0, 0 ; DFSR @@ -358,19 +357,19 @@ mmu_loop: mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO mcr p15, 5, r0, c15, c5, 2 ; Write Lockdown TLB VA -; Reset and start Cycle Counter - mov r2, #0x80000000 ; clear overflow +; Reset and start Cycle Counter + mov r2, #0x80000000 ; clear overflow mcr p15, 0, r2, c9, c12, 3 - mov r2, #0xd ; D, C, E + mov r2, #0xd ; D, C, E mcr p15, 0, r2, c9, c12, 0 - mov r2, #0x80000000 ; enable cycle counter + mov r2, #0x80000000 ; enable cycle counter mcr p15, 0, r2, c9, c12, 1 ; Reset and start Global Timer mov r0, #0x0 mov r1, #0x0 bl XTime_SetTime - + #ifdef PROFILING /* defined in Makefile */ /* Setup profiling stuff */ bl _profile_init @@ -379,10 +378,10 @@ mmu_loop: ; make sure argc and argv are valid mov r0, #0 mov r1, #0 - b __main ; jump to C startup code - and r0, r0, r0 ; no op - -Ldone b Ldone ; Paranoia: we should never get here + b __main ; jump to C startup code + and r0, r0, r0 ; no op + +Ldone b Ldone ; Paranoia: we should never get here ; ************************************************************************* @@ -393,47 +392,47 @@ Ldone b Ldone ; Paranoia: we should never get here ; * the whole D-cache. Need to invalidate each line. ; * ; ************************************************************************* - + invalidate_dcache - mrc p15, 1, r0, c0, c0, 1 ; read CLIDR + mrc p15, 1, r0, c0, c0, 1 ; read CLIDR ands r3, r0, #0x7000000 - mov r3, r3, lsr #23 ; cache level value (naturally aligned) + mov r3, r3, lsr #23 ; cache level value (naturally aligned) beq finished - mov r10, #0 ; start with level 0 + mov r10, #0 ; start with level 0 loop1 - add r2, r10, r10, lsr #1 ; work out 3xcachelevel - mov r1, r0, lsr r2 ; bottom 3 bits are the Cache type for this level - and r1, r1, #7 ; get those 3 bits alone + add r2, r10, r10, lsr #1 ; work out 3xcachelevel + mov r1, r0, lsr r2 ; bottom 3 bits are the Cache type for this level + and r1, r1, #7 ; get those 3 bits alone cmp r1, #2 - blt skip ; no cache or only instruction cache at this level - mcr p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register - isb ; isb to sync the change to the CacheSizeID reg - mrc p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register - and r2, r1, #7 ; extract the line length field - add r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + blt skip ; no cache or only instruction cache at this level + mcr p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + isb ; isb to sync the change to the CacheSizeID reg + mrc p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + and r2, r1, #7 ; extract the line length field + add r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 ; r4 is the max number on the way size (right aligned) - clz r5, r4 ; r5 is the bit position of the way size increment + ands r4, r4, r1, lsr #3 ; r4 is the max number on the way size (right aligned) + clz r5, r4 ; r5 is the bit position of the way size increment ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 ; r7 is the max number of the index size (right aligned) + ands r7, r7, r1, lsr #13 ; r7 is the max number of the index size (right aligned) loop2 - mov r9, r4 ; r9 working copy of the max way size (right aligned) + mov r9, r4 ; r9 working copy of the max way size (right aligned) loop3 - orr r11, r10, r9, lsl r5 ; factor in the way number and cache number into r11 - orr r11, r11, r7, lsl r2 ; factor in the index number - mcr p15, 0, r11, c7, c6, 2 ; invalidate by set/way - subs r9, r9, #1 ; decrement the way number + orr r11, r10, r9, lsl r5 ; factor in the way number and cache number into r11 + orr r11, r11, r7, lsl r2 ; factor in the index number + mcr p15, 0, r11, c7, c6, 2 ; invalidate by set/way + subs r9, r9, #1 ; decrement the way number bge loop3 - subs r7, r7, #1 ; decrement the index + subs r7, r7, #1 ; decrement the index bge loop2 skip - add r10, r10, #2 ; increment the cache number + add r10, r10, #2 ; increment the cache number cmp r3, r10 bgt loop1 finished - mov r10, #0 ; swith back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr + mov r10, #0 ; swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr isb bx lr diff --git a/lib/bsp/standalone/src/cortexa9/armcc/translation_table.s b/lib/bsp/standalone/src/cortexa9/armcc/translation_table.s old mode 100755 new mode 100644 index 2c50673e..45c8967a --- a/lib/bsp/standalone/src/cortexa9/armcc/translation_table.s +++ b/lib/bsp/standalone/src/cortexa9/armcc/translation_table.s @@ -1,4 +1,3 @@ -;* $Id: translation_table.s,v 1.1.4.1 2011/10/24 09:35:18 sadanan Exp $ ;****************************************************************************** ; ; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. @@ -68,11 +67,11 @@ MMUTable GBLA count GBLA sect -; 0x00000000 - 0x3ffffff (DDR Cacheable) +; 0x00000000 - 0x3ffffff (DDR Cacheable) count SETA 0 sect SETA 0 WHILE count<0x400 - DCD sect + 0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 + DCD sect + 0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 sect SETA sect+0x100000 count SETA count+1 WEND @@ -96,7 +95,7 @@ count SETA count+1 ; 0xc0000000 - 0xdfffffff (undef) count SETA 0 WHILE count<0x200 - DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 sect SETA sect+0x100000 count SETA count+1 WEND @@ -104,7 +103,7 @@ count SETA count+1 ; 0xe0000000 - 0xe02fffff (IOP dev) count SETA 0 WHILE count<0x3 - DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 sect SETA sect+0x100000 count SETA count+1 WEND @@ -112,7 +111,7 @@ count SETA count+1 ; 0xe0300000 - 0xe0ffffff (undef/reserved) count SETA 0 WHILE count<0xD - DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 sect SETA sect+0x100000 count SETA count+1 WEND @@ -144,7 +143,7 @@ count SETA count+1 ; 0xe6000000 - 0xf7ffffff (reserved) count SETA 0 WHILE count<0x120 - DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 sect SETA sect+0x100000 count SETA count+1 WEND diff --git a/lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.c b/lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.c old mode 100755 new mode 100644 index 09b586df..75ffbe07 --- a/lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.c +++ b/lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.c @@ -109,38 +109,38 @@ __asm void dmb(void) } /* Memory Operations */ -__asm unsigned int ldr(unsigned int adr) +__asm u32 ldr(u32 adr) { ldr r0, [r0] bx lr } -__asm unsigned int ldrb(unsigned int adr) +__asm u32 ldrb(u32 adr) { ldrb r0, [r0] bx lr } -__asm void str(unsigned int adr, unsigned int val) +__asm void str(u32 adr, u32 val) { str r1, [r0] bx lr } -__asm void strb(unsigned int adr, unsigned int val) +__asm void strb(u32 adr, u32 val) { strb r1, [r0] bx lr } /* Count leading zeroes (clz) */ -__asm unsigned int clz(unsigned int arg) +__asm u32 clz(u32 arg) { clz r0, r0 bx lr } -__asm unsigned int mfcpsr(void) +__asm u32 mfcpsr(void) { mrs r0, cpsr bx lr diff --git a/lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.h b/lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.h old mode 100755 new mode 100644 index 13eb5e30..a7e414e8 --- a/lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.h +++ b/lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.h @@ -51,7 +51,7 @@ #define XPSEUDO_ASM_RVCT_H /* by using protection macros */ /***************************** Include Files ********************************/ - +#include "xil_types.h" #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ @@ -67,7 +67,7 @@ extern "C" { #define tostring(s) #s -#define mtcpsr(v) { volatile register unsigned int Reg __asm("cpsr");\ +#define mtcpsr(v) { volatile register u32 Reg __asm("cpsr");\ Reg = v; } /* general purpose register read/write */ @@ -76,7 +76,7 @@ extern "C" { val = Reg; \ val;})*/ -#define mtgpr(rn, v) { volatile register unsigned int Reg __asm("r" stringify(rn));\ +#define mtgpr(rn, v) { volatile register u32 Reg __asm("r" stringify(rn));\ Reg = v; } /* CP15 operations */ @@ -84,7 +84,7 @@ extern "C" { val = register unsigned int Reg __asm(rn); \ val;})*/ -#define mtcp(rn, v) { volatile register unsigned int Reg __asm(rn); \ +#define mtcp(rn, v) { volatile register u32 Reg __asm(rn); \ Reg = v; } /************************** Variable Definitions ****************************/ @@ -111,17 +111,17 @@ __asm void dsb(void); __asm void dmb(void); /* Memory Operations */ -__asm unsigned int ldr(unsigned int adr); +__asm u32 ldr(u32 adr); -__asm unsigned int ldrb(unsigned int adr); +__asm u32 ldrb(u32 adr); -__asm void str(unsigned int adr, unsigned int val); +__asm void str(u32 adr, u32 val); -__asm void strb(unsigned int adr, unsigned int val); +__asm void strb(u32 adr, u32 val); /* Count leading zeroes (clz) */ -__asm unsigned int clz(unsigned int arg); -__asm unsigned int mfcpsr(void); +__asm u32 clz(u32 arg); +__asm u32 mfcpsr(void); #ifdef __cplusplus } diff --git a/lib/bsp/standalone/src/cortexa9/gcc/Makefile b/lib/bsp/standalone/src/cortexa9/gcc/Makefile old mode 100755 new mode 100644 index ea3b9e25..21b166f6 --- a/lib/bsp/standalone/src/cortexa9/gcc/Makefile +++ b/lib/bsp/standalone/src/cortexa9/gcc/Makefile @@ -67,7 +67,7 @@ libs: $(LIBS) standalone_libs: $(LIBSOURCES) echo "Compiling standalone" $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^ - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} profile_libs: $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" libs @@ -84,4 +84,3 @@ profile_includes: clean: rm -rf ${OUTS} $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" clean - diff --git a/lib/bsp/standalone/src/cortexa9/gcc/_exit.c b/lib/bsp/standalone/src/cortexa9/gcc/_exit.c old mode 100755 new mode 100644 index 8f75400b..5fe94ab5 --- a/lib/bsp/standalone/src/cortexa9/gcc/_exit.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/_exit.c @@ -31,11 +31,14 @@ ******************************************************************************/ #include +#include "xil_types.h" /* _exit - Simple implementation. Does not return. */ -__attribute__((weak)) void _exit (int status) +__attribute__((weak)) void _exit (sint32 status) { (void)status; - while (1); + while (1) { + ; + } } diff --git a/lib/bsp/standalone/src/cortexa9/gcc/_open.c b/lib/bsp/standalone/src/cortexa9/gcc/_open.c old mode 100755 new mode 100644 index 1006ce55..7a283809 --- a/lib/bsp/standalone/src/cortexa9/gcc/_open.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/_open.c @@ -31,10 +31,11 @@ ******************************************************************************/ #include +#include "xil_types.h" #ifdef __cplusplus extern "C" { - __attribute__((weak)) int _open(const char *buf, int flags, int mode); + __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode); } #endif @@ -42,9 +43,9 @@ extern "C" { * _open -- open a file descriptor. We don't have a filesystem, so * we return an error. */ -__attribute__((weak)) int _open(const char *buf, int flags, int mode) +__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode) { - (void)buf; + (void *)buf; (void)flags; (void)mode; errno = EIO; diff --git a/lib/bsp/standalone/src/cortexa9/gcc/_sbrk.c b/lib/bsp/standalone/src/cortexa9/gcc/_sbrk.c old mode 100755 new mode 100644 index 4a08ee7c..87fc89c4 --- a/lib/bsp/standalone/src/cortexa9/gcc/_sbrk.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/_sbrk.c @@ -31,31 +31,41 @@ ******************************************************************************/ #include +#include "xil_types.h" -extern int _heap_start; -extern int _heap_end; +extern u8 _heap_start[]; +extern u8 _heap_end[]; #ifdef __cplusplus extern "C" { - __attribute__((weak)) caddr_t _sbrk ( int incr ); + __attribute__((weak)) caddr_t _sbrk ( s32 incr ); } #endif -__attribute__((weak)) caddr_t _sbrk ( int incr ) +__attribute__((weak)) caddr_t _sbrk ( s32 incr ) { - static unsigned char *heap = NULL; - unsigned char *prev_heap; + static u8 *heap = NULL; + u8 *prev_heap; + static u8 *HeapEndPtr = (u8 *)&_heap_end; + caddr_t Status; if (heap == NULL) { - heap = (unsigned char *)&_heap_start; + heap = (u8 *)&_heap_start; } prev_heap = heap; heap += incr; - if ((unsigned)heap > (unsigned)&_heap_end){ - return (caddr_t) -1; + if (heap > HeapEndPtr){ + Status = (caddr_t) -1; } - return (caddr_t) prev_heap; + else if (prev_heap != NULL) { + Status = (caddr_t) ((void *)prev_heap); + } + else { + Status = (caddr_t) -1; + } + + return Status; } diff --git a/lib/bsp/standalone/src/cortexa9/gcc/abort.c b/lib/bsp/standalone/src/cortexa9/gcc/abort.c old mode 100755 new mode 100644 diff --git a/lib/bsp/standalone/src/cortexa9/gcc/asm_vectors.S b/lib/bsp/standalone/src/cortexa9/gcc/asm_vectors.S old mode 100755 new mode 100644 index 532b2222..9db6f766 --- a/lib/bsp/standalone/src/cortexa9/gcc/asm_vectors.S +++ b/lib/bsp/standalone/src/cortexa9/gcc/asm_vectors.S @@ -44,7 +44,7 @@ * 3.05a sdm 02/02/12 Save lr when profiling is enabled * 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file * 'xil_errata.h' for errata description -* 4.00a pkp 22/01/14 Modified return addresses for interrupt +* 4.00a pkp 22/01/14 Modified return addresses for interrupt * handlers (DataAbortHandler and SVCHandler) * to fix CR#767251 * @@ -86,7 +86,7 @@ _vector_table: IRQHandler: /* IRQ vector handler */ - + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/ #ifdef __ARM_NEON__ vpush {d0-d7} @@ -104,7 +104,7 @@ IRQHandler: /* IRQ vector handler */ #endif bl IRQInterrupt /* IRQ vector */ - + #ifdef __ARM_NEON__ pop {r1} vmsr FPEXC, r1 @@ -114,7 +114,7 @@ IRQHandler: /* IRQ vector handler */ vpop {d0-d7} #endif ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ - + subs pc, lr, #4 /* adjust return */ @@ -150,7 +150,7 @@ Undefined: /* Undefined handler */ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ - b _prestart + b _prestart movs pc, lr diff --git a/lib/bsp/standalone/src/cortexa9/gcc/boot.S b/lib/bsp/standalone/src/cortexa9/gcc/boot.S old mode 100755 new mode 100644 index 58fd9b89..498ff69d --- a/lib/bsp/standalone/src/cortexa9/gcc/boot.S +++ b/lib/bsp/standalone/src/cortexa9/gcc/boot.S @@ -41,16 +41,16 @@ * Ver Who Date Changes * ----- ------- -------- --------------------------------------------------- * 1.00a ecm/sdm 10/20/09 Initial version -* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control +* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control * register settings. * 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary * register settings. * 3.07a asa 07/16/12 Modified the L2 Cache controller settings to improve * performance. Changed the property of the ".boot" * section. -* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control +* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control * Register settings -* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a +* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a * value of 0x00020202. Fix for CR 697094 (SI#687034). * 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file * 'xil_errata.h' for errata description @@ -99,13 +99,13 @@ /* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */ .if SIM_MODE == 1 .set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */ -.else +.else .set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */ .endif .set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */ -.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable, +.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable, Event monitor bus enable and Way Size (64 KB) */ .set L2CCControl, 0x01 /* Enable L2CC */ .set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */ @@ -158,7 +158,7 @@ EndlessLoop1: OKToRun: mrc p15, 0, r0, c0, c0, 0 /* Get the revision */ - and r5, r0, #0x00f00000 + and r5, r0, #0x00f00000 and r6, r0, #0x0000000f orr r6, r6, r5, lsr #20-4 @@ -183,7 +183,7 @@ OKToRun: /*set scu enable bit in scu*/ ldr r7, =0xf8f00000 ldr r0, [r7] - orr r0, r0, #0x1 + orr r0, r0, #0x1 str r0, [r7] /*invalidate scu*/ @@ -194,7 +194,7 @@ OKToRun: /* Write to ACTLR */ mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/ orr r0, r0, #(0x01 << 6) /* set SMP bit */ - orr r0, r0, #(0x01 ) /* */ + orr r0, r0, #(0x01 ) /* */ mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ /* Invalidate caches and TLBs */ @@ -238,7 +238,7 @@ Sync: ldr r1, [r0] ldr r0,=L2CCIntRaw /* clear pending interrupts */ ldr r1,[r0] - ldr r0,=L2CCIntClear + ldr r0,=L2CCIntClear str r1,[r0] #endif @@ -321,8 +321,8 @@ mmu_loop: ldr r0,=TblBase /* Load MMU translation table base */ orr r0, r0, #0x5B /* Outer-cacheable, WB */ mcr 15, 0, r0, c2, c0, 0 /* TTB0 */ - - + + mvn r0,#0 /* Load MMU domains -- all ones=manager */ mcr p15,0,r0,c3,c0,0 @@ -340,11 +340,11 @@ mmu_loop: ldr r1,=SLCRUnlockKey /* set unlock key */ str r1, [r0] /* Unlock SLCR */ - ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */ + ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */ ldr r1,=SLCRL2cRamConfig /* set the configuration value */ str r1, [r0] /* store the L2c Ram Control Register */ - ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */ + ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */ ldr r1,=SLCRlockKey /* set lock key */ str r1, [r0] /* lock SLCR */ @@ -366,7 +366,7 @@ mmu_loop: fmxr FPEXC, r1 /* write back the exception register */ mrc p15,0,r0,c1,c0,0 /* flow prediction enable */ - orr r0, r0, #(0x01 << 11) /* #0x8000 */ + orr r0, r0, #(0x01 << 11) /* #0x8000 */ mcr p15,0,r0,c1,c0,0 mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */ @@ -377,11 +377,11 @@ mmu_loop: mrs r0, cpsr /* get the current PSR */ bic r0, r0, #0x100 /* enable asynchronous abort exception */ msr cpsr_xsf, r0 - - + + b _start /* jump to C startup code */ and r0, r0, r0 /* no op */ - + .Ldone: b .Ldone /* Paranoia: we should never get here */ @@ -441,5 +441,3 @@ finished: bx lr .end - - diff --git a/lib/bsp/standalone/src/cortexa9/gcc/close.c b/lib/bsp/standalone/src/cortexa9/gcc/close.c old mode 100755 new mode 100644 index f18b9cdb..96bfd847 --- a/lib/bsp/standalone/src/cortexa9/gcc/close.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/close.c @@ -29,9 +29,10 @@ * this Software without prior written authorization from Xilinx. * ******************************************************************************/ +#include "xil_types.h" #ifdef __cplusplus extern "C" { - __attribute__((weak)) int _close(int fd); + __attribute__((weak)) s32 _close(s32 fd); } #endif @@ -39,7 +40,7 @@ extern "C" { * close -- We don't need to do anything, but pretend we did. */ -__attribute__((weak)) int _close(int fd) +__attribute__((weak)) s32 _close(s32 fd) { (void)fd; return (0); diff --git a/lib/bsp/standalone/src/cortexa9/gcc/cpu_init.S b/lib/bsp/standalone/src/cortexa9/gcc/cpu_init.S old mode 100755 new mode 100644 index 08694f79..f051171a --- a/lib/bsp/standalone/src/cortexa9/gcc/cpu_init.S +++ b/lib/bsp/standalone/src/cortexa9/gcc/cpu_init.S @@ -52,7 +52,7 @@ .text .global __cpu_init - .align 2 + .align 2 __cpu_init: /* Clear cp15 regs with unknown reset values */ diff --git a/lib/bsp/standalone/src/cortexa9/gcc/errno.c b/lib/bsp/standalone/src/cortexa9/gcc/errno.c old mode 100755 new mode 100644 index 4cd96711..9aa1bdce --- a/lib/bsp/standalone/src/cortexa9/gcc/errno.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/errno.c @@ -36,15 +36,16 @@ #include #include +#include "xil_types.h" #ifdef __cplusplus extern "C" { - __attribute__((weak)) int * __errno (); + __attribute__((weak)) sint32 * __errno (void); } #endif -__attribute__((weak)) int * -__errno () +__attribute__((weak)) sint32 * +__errno (void) { return &_REENT->_errno; } diff --git a/lib/bsp/standalone/src/cortexa9/gcc/fcntl.c b/lib/bsp/standalone/src/cortexa9/gcc/fcntl.c old mode 100755 new mode 100644 index 24d8acad..2e3df9ae --- a/lib/bsp/standalone/src/cortexa9/gcc/fcntl.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/fcntl.c @@ -31,12 +31,13 @@ ******************************************************************************/ #include +#include "xil_types.h" /* * fcntl -- Manipulate a file descriptor. * We don't have a filesystem, so we do nothing. */ -__attribute__((weak)) int fcntl (int fd, int cmd, long arg) +__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg) { (void)fd; (void)cmd; diff --git a/lib/bsp/standalone/src/cortexa9/gcc/fstat.c b/lib/bsp/standalone/src/cortexa9/gcc/fstat.c old mode 100755 new mode 100644 index a9abef9c..23fd37b7 --- a/lib/bsp/standalone/src/cortexa9/gcc/fstat.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/fstat.c @@ -31,16 +31,17 @@ ******************************************************************************/ #include +#include "xil_types.h" #ifdef __cplusplus extern "C" { - __attribute__((weak)) int _fstat(int fd, struct stat *buf); + __attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf); } #endif /* * fstat -- Since we have no file system, we just return an error. */ -__attribute__((weak)) int _fstat(int fd, struct stat *buf) +__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf) { (void)fd; buf->st_mode = S_IFCHR; /* Always pretend to be a tty */ diff --git a/lib/bsp/standalone/src/cortexa9/gcc/getpid.c b/lib/bsp/standalone/src/cortexa9/gcc/getpid.c old mode 100755 new mode 100644 index 64dd40b5..30b06afd --- a/lib/bsp/standalone/src/cortexa9/gcc/getpid.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/getpid.c @@ -30,21 +30,22 @@ * ******************************************************************************/ +#include "xil_types.h" /* * getpid -- only one process, so just return 1. */ #ifdef __cplusplus extern "C" { - __attribute__((weak)) int _getpid(); + __attribute__((weak)) s32 _getpid(void); } #endif -__attribute__((weak)) int getpid() +__attribute__((weak)) s32 getpid(void) { return 1; } -__attribute__((weak)) int _getpid() +__attribute__((weak)) s32 _getpid(void) { return 1; } diff --git a/lib/bsp/standalone/src/cortexa9/gcc/isatty.c b/lib/bsp/standalone/src/cortexa9/gcc/isatty.c old mode 100755 new mode 100644 index 5eaf71fa..9d6460ca --- a/lib/bsp/standalone/src/cortexa9/gcc/isatty.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/isatty.c @@ -30,10 +30,11 @@ * ******************************************************************************/ #include +#include "xil_types.h" #ifdef __cplusplus extern "C" { - __attribute__((weak)) int _isatty(int fd); + __attribute__((weak)) sint32 _isatty(sint32 fd); } #endif @@ -42,13 +43,13 @@ extern "C" { * returns 0 if not. Since we're hooked up to a * serial port, we'll say yes _AND return a 1. */ -__attribute__((weak)) int isatty(int fd) +__attribute__((weak)) sint32 isatty(sint32 fd) { (void)fd; return (1); } -__attribute__((weak)) int _isatty(int fd) +__attribute__((weak)) sint32 _isatty(sint32 fd) { (void)fd; return (1); diff --git a/lib/bsp/standalone/src/cortexa9/gcc/kill.c b/lib/bsp/standalone/src/cortexa9/gcc/kill.c old mode 100755 new mode 100644 index 9000019a..c4d6e052 --- a/lib/bsp/standalone/src/cortexa9/gcc/kill.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/kill.c @@ -31,10 +31,11 @@ ******************************************************************************/ #include #include +#include "xil_types.h" #ifdef __cplusplus extern "C" { - __attribute__((weak)) int _kill(int pid, int sig); + __attribute__((weak)) s32 _kill(s32 pid, s32 sig); } #endif @@ -42,17 +43,19 @@ extern "C" { * kill -- go out via exit... */ -__attribute__((weak)) int kill(int pid, int sig) +__attribute__((weak)) s32 kill(s32 pid, s32 sig) { - if(pid == 1) + if(pid == 1) { _exit(sig); + } return 0; } -__attribute__((weak)) int _kill(int pid, int sig) +__attribute__((weak)) s32 _kill(s32 pid, s32 sig) { - if(pid == 1) + if(pid == 1) { _exit(sig); + } return 0; } diff --git a/lib/bsp/standalone/src/cortexa9/gcc/lseek.c b/lib/bsp/standalone/src/cortexa9/gcc/lseek.c old mode 100755 new mode 100644 index c90c84df..a918133b --- a/lib/bsp/standalone/src/cortexa9/gcc/lseek.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/lseek.c @@ -32,16 +32,17 @@ #include #include +#include "xil_types.h" #ifdef __cplusplus extern "C" { - __attribute__((weak)) off_t _lseek(int fd, off_t offset, int whence); + __attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence); } #endif /* * lseek -- Since a serial port is non-seekable, we return an error. */ -__attribute__((weak)) off_t lseek(int fd, off_t offset, int whence) +__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence) { (void)fd; (void)offset; @@ -50,7 +51,7 @@ __attribute__((weak)) off_t lseek(int fd, off_t offset, int whence) return ((off_t)-1); } -__attribute__((weak)) off_t _lseek(int fd, off_t offset, int whence) +__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence) { (void)fd; (void)offset; diff --git a/lib/bsp/standalone/src/cortexa9/gcc/open.c b/lib/bsp/standalone/src/cortexa9/gcc/open.c old mode 100755 new mode 100644 index 224968d6..2c575186 --- a/lib/bsp/standalone/src/cortexa9/gcc/open.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/open.c @@ -31,19 +31,20 @@ ******************************************************************************/ #include +#include "xil_types.h" #ifdef __cplusplus extern "C" { - __attribute__((weak)) int open(const char *buf, int flags, int mode); + __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode); } #endif /* * open -- open a file descriptor. We don't have a filesystem, so * we return an error. */ -__attribute__((weak)) int open(const char *buf, int flags, int mode) +__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode) { - (void)buf; + (void *)buf; (void)flags; (void)mode; errno = EIO; diff --git a/lib/bsp/standalone/src/cortexa9/gcc/read.c b/lib/bsp/standalone/src/cortexa9/gcc/read.c old mode 100755 new mode 100644 index d4eae693..dc42aaf2 --- a/lib/bsp/standalone/src/cortexa9/gcc/read.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/read.c @@ -33,12 +33,12 @@ /* read.c -- read bytes from a input device. */ -#include "xparameters.h" #include "xil_printf.h" +#include "xparameters.h" #ifdef __cplusplus extern "C" { - __attribute__((weak)) int _read (int fd, char* buf, int nbytes); + __attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes); } #endif @@ -46,23 +46,30 @@ extern "C" { * read -- read bytes from the serial port. Ignore fd, since * we only have stdin. */ -__attribute__((weak)) int -read (int fd, char* buf, int nbytes) +__attribute__((weak)) s32 +read (s32 fd, char8* buf, s32 nbytes) { #ifdef STDIN_BASEADDRESS - int i = 0; + s32 i; + char8* LocalBuf = buf; (void)fd; for (i = 0; i < nbytes; i++) { - *(buf + i) = inbyte(); - if ((*(buf + i) == '\n' || *(buf + i) == '\r')) - { - i++; - break; - } + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + *LocalBuf = inbyte(); + if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) { + break; + } + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } } - return (i); + return (i + 1); #else (void)fd; (void)buf; @@ -71,23 +78,30 @@ read (int fd, char* buf, int nbytes) #endif } -__attribute__((weak)) int -_read (int fd, char* buf, int nbytes) +__attribute__((weak)) s32 +_read (s32 fd, char8* buf, s32 nbytes) { #ifdef STDIN_BASEADDRESS - int i = 0; + s32 i; + char8* LocalBuf = buf; (void)fd; for (i = 0; i < nbytes; i++) { - *(buf + i) = inbyte(); - if ((*(buf + i) == '\n' || *(buf + i) == '\r')) - { - i++; - break; - } + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + *LocalBuf = inbyte(); + if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) { + break; + } + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } } - return (i); + return (i + 1); #else (void)fd; (void)buf; diff --git a/lib/bsp/standalone/src/cortexa9/gcc/sbrk.c b/lib/bsp/standalone/src/cortexa9/gcc/sbrk.c old mode 100755 new mode 100644 index 7193d589..c12b4f01 --- a/lib/bsp/standalone/src/cortexa9/gcc/sbrk.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/sbrk.c @@ -31,37 +31,35 @@ ******************************************************************************/ #include +#include "xil_types.h" #ifdef __cplusplus extern "C" { - __attribute__((weak)) char *sbrk (int nbytes); + __attribute__((weak)) char8 *sbrk (s32 nbytes); } #endif -extern char _heap_start[]; -extern char _heap_end[]; -extern char HeapBase[]; -extern char HeapLimit[]; +extern u8 _heap_start[]; +extern u8 _heap_end[]; +extern char8 HeapBase[]; +extern char8 HeapLimit[]; -static char *heap_ptr; -__attribute__((weak)) char *sbrk (int nbytes) + +__attribute__((weak)) char8 *sbrk (s32 nbytes) { - char *base; - - if (!heap_ptr) - /*heap_ptr = (char *)&_heap_start;*/ - heap_ptr = (char *)&HeapBase; + char8 *base; + static char8 *heap_ptr = HeapBase; base = heap_ptr; - heap_ptr += nbytes; + if(heap_ptr != NULL) { + heap_ptr += nbytes; + } -/* if (heap_ptr <= ((char *)&_heap_end + 1))*/ - if (heap_ptr <= ((char *)&HeapLimit + 1)) +/* if (heap_ptr <= ((char8 *)&_heap_end + 1)) */ + if (heap_ptr <= ((char8 *)&HeapLimit + 1)) { return base; - - else - { + } else { errno = ENOMEM; - return ((char *)-1); + return ((char8 *)-1); } } diff --git a/lib/bsp/standalone/src/cortexa9/gcc/translation_table.s b/lib/bsp/standalone/src/cortexa9/gcc/translation_table.s old mode 100755 new mode 100644 diff --git a/lib/bsp/standalone/src/cortexa9/gcc/unlink.c b/lib/bsp/standalone/src/cortexa9/gcc/unlink.c old mode 100755 new mode 100644 index ab3db626..643052d5 --- a/lib/bsp/standalone/src/cortexa9/gcc/unlink.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/unlink.c @@ -31,19 +31,20 @@ ******************************************************************************/ #include +#include "xil_types.h" #ifdef __cplusplus extern "C" { - __attribute__((weak)) int unlink(char *path); + __attribute__((weak)) sint32 unlink(char8 *path); } #endif /* * unlink -- since we have no file system, * we just return an error. */ -__attribute__((weak)) int unlink(char *path) +__attribute__((weak)) sint32 unlink(char8 *path) { - (void)path; + (void *)path; errno = EIO; return (-1); } diff --git a/lib/bsp/standalone/src/cortexa9/gcc/write.c b/lib/bsp/standalone/src/cortexa9/gcc/write.c old mode 100755 new mode 100644 index 3da52c43..27618c7f --- a/lib/bsp/standalone/src/cortexa9/gcc/write.c +++ b/lib/bsp/standalone/src/cortexa9/gcc/write.c @@ -33,12 +33,12 @@ /* write.c -- write bytes to an output device. */ -#include "xparameters.h" #include "xil_printf.h" +#include "xparameters.h" #ifdef __cplusplus extern "C" { - __attribute__((weak)) int _write (int fd, char* buf, int nbytes); + __attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes); } #endif @@ -47,19 +47,28 @@ extern "C" { * stdout and stderr are the same. Since we have no filesystem, * open will only return an error. */ -__attribute__((weak)) int -write (int fd, char* buf, int nbytes) +__attribute__((weak)) sint32 +write (sint32 fd, char8* buf, sint32 nbytes) { #ifdef STDOUT_BASEADDRESS - int i; + s32 i; + char8* LocalBuf = buf; (void)fd; for (i = 0; i < nbytes; i++) { - if (*(buf + i) == '\n') { - outbyte ('\r'); - } - outbyte (*(buf + i)); + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + if (*LocalBuf == '\n') { + outbyte ('\r'); + } + outbyte (*LocalBuf); + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } } return (nbytes); #else @@ -70,18 +79,27 @@ write (int fd, char* buf, int nbytes) #endif } -__attribute__((weak)) int -_write (int fd, char* buf, int nbytes) +__attribute__((weak)) sint32 +_write (sint32 fd, char8* buf, sint32 nbytes) { #ifdef STDOUT_BASEADDRESS - int i; + s32 i; + char8* LocalBuf = buf; (void)fd; for (i = 0; i < nbytes; i++) { - if (*(buf + i) == '\n') { - outbyte ('\r'); - } - outbyte (*(buf + i)); + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + if (*LocalBuf == '\n') { + outbyte ('\r'); + } + outbyte (*LocalBuf); + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } } return (nbytes); #else diff --git a/lib/bsp/standalone/src/cortexa9/gcc/xil-crt0.S b/lib/bsp/standalone/src/cortexa9/gcc/xil-crt0.S old mode 100755 new mode 100644 index dbf7276a..43998d02 --- a/lib/bsp/standalone/src/cortexa9/gcc/xil-crt0.S +++ b/lib/bsp/standalone/src/cortexa9/gcc/xil-crt0.S @@ -68,19 +68,19 @@ .Lbss_start: .long __bss_start -.Lbss_end: +.Lbss_end: .long __bss_end -.Lstack: +.Lstack: .long __stack - + .globl _start _start: bl __cpu_init /* Initialize the CPU first (BSP provides this) */ mov r0, #0 - + /* clear sbss */ ldr r1,.Lsbss_start /* calculate beginning of the SBSS */ ldr r2,.Lsbss_end /* calculate end of the SBSS */ @@ -91,12 +91,12 @@ _start: str r0, [r1], #4 b .Lloop_sbss -.Lenclsbss: +.Lenclsbss: /* clear bss */ ldr r1,.Lbss_start /* calculate beginning of the BSS */ ldr r2,.Lbss_end /* calculate end of the BSS */ -.Lloop_bss: +.Lloop_bss: cmp r1,r2 bge .Lenclbss /* If no BSS, no clearing required */ str r0, [r1], #4 @@ -117,8 +117,8 @@ _start: bl _profile_init #endif /* PROFILING */ - /* run global constructors */ - bl __libc_init_array + /* run global constructors */ + bl __libc_init_array /* make sure argc and argv are valid */ mov r0, #0 @@ -127,8 +127,8 @@ _start: /* Let her rip */ bl main - /* Cleanup global constructors */ - bl __libc_fini_array + /* Cleanup global constructors */ + bl __libc_fini_array #ifdef PROFILING /* Cleanup profiling stuff */ diff --git a/lib/bsp/standalone/src/cortexa9/gcc/xpseudo_asm_gcc.h b/lib/bsp/standalone/src/cortexa9/gcc/xpseudo_asm_gcc.h old mode 100755 new mode 100644 index 66f774b0..e292e6a0 --- a/lib/bsp/standalone/src/cortexa9/gcc/xpseudo_asm_gcc.h +++ b/lib/bsp/standalone/src/cortexa9/gcc/xpseudo_asm_gcc.h @@ -52,6 +52,7 @@ /***************************** Include Files ********************************/ +#include "xil_types.h" #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ @@ -67,7 +68,7 @@ extern "C" { #define tostring(s) #s /* pseudo assembler instructions */ -#define mfcpsr() ({unsigned int rval; \ +#define mfcpsr() ({u32 rval; \ __asm__ __volatile__(\ "mrs %0, cpsr\n"\ : "=r" (rval)\ @@ -93,7 +94,7 @@ extern "C" { : : "r" (v)\ ) -#define mfgpr(rn) ({unsigned int rval; \ +#define mfgpr(rn) ({u32 rval; \ __asm__ __volatile__(\ "mov %0,r" stringify(rn) "\n"\ : "=r" (rval)\ @@ -114,7 +115,7 @@ extern "C" { /* Memory Operations */ -#define ldr(adr) ({unsigned long rval; \ +#define ldr(adr) ({u32 rval; \ __asm__ __volatile__(\ "ldr %0,[%1]"\ : "=r" (rval) : "r" (adr)\ @@ -122,7 +123,7 @@ extern "C" { rval;\ }) -#define ldrb(adr) ({unsigned char rval; \ +#define ldrb(adr) ({u8 rval; \ __asm__ __volatile__(\ "ldrb %0,[%1]"\ : "=r" (rval) : "r" (adr)\ @@ -141,7 +142,7 @@ extern "C" { ) /* Count leading zeroes (clz) */ -#define clz(arg) ({unsigned char rval; \ +#define clz(arg) ({u8 rval; \ __asm__ __volatile__(\ "clz %0,%1"\ : "=r" (rval) : "r" (arg)\ @@ -155,7 +156,7 @@ extern "C" { : : "r" (v)\ ); -#define mfcp(rn) ({unsigned int rval; \ +#define mfcp(rn) ({u32 rval; \ __asm__ __volatile__(\ "mrc " rn "\n"\ : "=r" (rval)\ diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/Makefile b/lib/bsp/standalone/src/cortexa9/iccarm/Makefile old mode 100755 new mode 100644 diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/abort.c b/lib/bsp/standalone/src/cortexa9/iccarm/abort.c old mode 100755 new mode 100644 diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/asm_vectors.s b/lib/bsp/standalone/src/cortexa9/iccarm/asm_vectors.s old mode 100755 new mode 100644 index 7753f07f..311b002b --- a/lib/bsp/standalone/src/cortexa9/iccarm/asm_vectors.s +++ b/lib/bsp/standalone/src/cortexa9/iccarm/asm_vectors.s @@ -41,8 +41,8 @@ ; Ver Who Date Changes ; ----- ------- -------- --------------------------------------------------- ; 1.00a Initial version -; 4.2 pkp 06/27/14 Modified return addresses for interrupt -; handlers +; 4.2 pkp 06/27/14 Modified return addresses for interrupt +; handlers ; ; ; @note @@ -52,7 +52,7 @@ ;**************************************************************************** MODULE ?asm_vectors - + ;; Forward declaration of sections. SECTION IRQ_STACK:DATA:NOROOT(3) SECTION FIQ_STACK:DATA:NOROOT(3) @@ -60,7 +60,7 @@ SECTION ABT_STACK:DATA:NOROOT(3) SECTION UND_STACK:DATA:NOROOT(3) SECTION CSTACK:DATA:NOROOT(3) - + #include "xparameters.h" ;#include "xtime_l.h" @@ -72,9 +72,9 @@ SECTION .intvec:CODE:NOROOT(2) - + PUBLIC _vector_table - + IMPORT IRQInterrupt IMPORT FIQInterrupt IMPORT SWInterrupt @@ -82,8 +82,8 @@ IMPORT PrefetchAbortInterrupt _vector_table - ARM - + ARM + B __iar_program_start B Undefined B SVCHandler @@ -98,54 +98,54 @@ _vector_table REQUIRE _vector_table ARM -IRQHandler ; IRQ vector handler - +IRQHandler ; IRQ vector handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code bl IRQInterrupt ; IRQ vector - ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code - subs pc, lr, #4 ; adjust return + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #4 ; adjust return -FIQHandler ; FIQ vector handler - stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code +FIQHandler ; FIQ vector handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code FIQLoop - bl FIQInterrupt ; FIQ vector + bl FIQInterrupt ; FIQ vector - ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code - subs pc, lr, #4 ; adjust return + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #4 ; adjust return -Undefined ; Undefined handler - stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code - ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code - b _prestart +Undefined ; Undefined handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + b _prestart movs pc, lr -SVCHandler ; SWI handler - stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code - tst r0, #0x20 ; check the T bit - ldrneh r0, [lr,#-2] ; Thumb mode - bicne r0, r0, #0xff00 ; Thumb mode - ldreq r0, [lr,#-4] ; ARM mode - biceq r0, r0, #0xff000000 ; ARM mode - bl SWInterrupt ; SWInterrupt: call C function here - ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code - movs pc, lr ; adjust return +SVCHandler ; SWI handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + tst r0, #0x20 ; check the T bit + ldrneh r0, [lr,#-2] ; Thumb mode + bicne r0, r0, #0xff00 ; Thumb mode + ldreq r0, [lr,#-4] ; ARM mode + biceq r0, r0, #0xff000000 ; ARM mode + bl SWInterrupt ; SWInterrupt: call C function here + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + movs pc, lr ; adjust return -DataAbortHandler ; Data Abort handler - stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code - bl DataAbortInterrupt ;DataAbortInterrupt :call C function here - ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code - subs pc, lr, #8 ; adjust return +DataAbortHandler ; Data Abort handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + bl DataAbortInterrupt ;DataAbortInterrupt :call C function here + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #8 ; adjust return -PrefetchAbortHandler ; Prefetch Abort handler - stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code - bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here - ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code - subs pc, lr, #4 ; adjust return +PrefetchAbortHandler ; Prefetch Abort handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #4 ; adjust return END diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/boot.s b/lib/bsp/standalone/src/cortexa9/iccarm/boot.s old mode 100755 new mode 100644 index 7c8e98c8..3ac5c8d4 --- a/lib/bsp/standalone/src/cortexa9/iccarm/boot.s +++ b/lib/bsp/standalone/src/cortexa9/iccarm/boot.s @@ -51,7 +51,7 @@ ; ;**************************************************************************** - MODULE ?boot + MODULE ?boot ;; Forward declaration of sections. SECTION IRQ_STACK:DATA:NOROOT(3) SECTION FIQ_STACK:DATA:NOROOT(3) @@ -59,7 +59,7 @@ SECTION ABT_STACK:DATA:NOROOT(3) SECTION UND_STACK:DATA:NOROOT(3) SECTION CSTACK:DATA:NOROOT(3) - + #include "xparameters.h" ;#include "xtime_l.h" @@ -78,7 +78,7 @@ PSS_SLCR_BASE_ADDR EQU 0xF8000000 RESERVED EQU 0x0fffff00 TblBase EQU MMUTable -LRemap EQU 0xFE00000F ; set the base address of the peripheral block as not shared +LRemap EQU 0xFE00000F ; set the base address of the peripheral block as not shared L2CCWay EQU (PSS_L2CC_BASE_ADDR + 0x077C) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET) L2CCSync EQU (PSS_L2CC_BASE_ADDR + 0x0730) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET) L2CCCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0100) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET) @@ -94,36 +94,36 @@ SLCRL2cRamReg EQU (PSS_SLCR_BASE_ADDR + 0xA1C) ;(PSS_SLCR_BASE_ADDR + XPSS_S /* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */ #if SIM_MODE == 1 -CRValMmuCac EQU 00000000000000b ; Disable IDC, and MMU -#else -CRValMmuCac EQU 01000000000101b ; Enable IDC, and MMU +CRValMmuCac EQU 00000000000000b ; Disable IDC, and MMU +#else +CRValMmuCac EQU 01000000000101b ; Enable IDC, and MMU #endif -CRValHiVectorAddr EQU 10000000000000b ; Set the Vector address to high, 0xFFFF0000 +CRValHiVectorAddr EQU 10000000000000b ; Set the Vector address to high, 0xFFFF0000 -L2CCAuxControl EQU 0x72360000 ; Enable all prefetching, Way Size (16 KB) and High Priority for SO and Dev Reads Enable -L2CCControl EQU 0x01 ; Enable L2CC -L2CCTAGLatency EQU 0x0111 ; 7 Cycles of latency for TAG RAM -L2CCDataLatency EQU 0x0121 ; 7 Cycles of latency for DATA RAM +L2CCAuxControl EQU 0x72360000 ; Enable all prefetching, Way Size (16 KB) and High Priority for SO and Dev Reads Enable +L2CCControl EQU 0x01 ; Enable L2CC +L2CCTAGLatency EQU 0x0111 ; 7 Cycles of latency for TAG RAM +L2CCDataLatency EQU 0x0121 ; 7 Cycles of latency for DATA RAM -SLCRlockKey EQU 0x767B ; SLCR lock key -SLCRUnlockKey EQU 0xDF0D ; SLCR unlock key -SLCRL2cRamConfig EQU 0x00020202 ; SLCR L2C ram configuration +SLCRlockKey EQU 0x767B ; SLCR lock key +SLCRUnlockKey EQU 0xDF0D ; SLCR unlock key +SLCRL2cRamConfig EQU 0x00020202 ; SLCR L2C ram configuration vector_base EQU _vector_table -FPEXC_EN EQU 0x40000000 ; FPU enable bit, (1 << 30) - - SECTION .intvec:CODE:NOROOT(2) - +FPEXC_EN EQU 0x40000000 ; FPU enable bit, (1 << 30) -; this initializes the various processor modes + SECTION .intvec:CODE:NOROOT(2) + + +; this initializes the various processor modes _prestart __iar_program_start #if XPAR_CPU_ID==0 -; only allow cp0 through +; only allow cp0 through mrc p15,0,r1,c0,c0,5 and r1, r1, #0xf cmp r1, #0 @@ -133,7 +133,7 @@ EndlessLoop0 b EndlessLoop0 #elif XPAR_CPU_ID==1 -; only allow cp1 through +; only allow cp1 through mrc p15,0,r1,c0,c0,5 and r1, r1, #0xf cmp r1, #1 @@ -144,26 +144,26 @@ EndlessLoop1 #endif OKToRun - mrc p15, 0, r0, c0, c0, 0 ; Get the revision - and r5, r0, #0x00f00000 + mrc p15, 0, r0, c0, c0, 0 ; Get the revision + and r5, r0, #0x00f00000 and r6, r0, #0x0000000f orr r6, r6, r5, lsr #20-4 #ifdef CONFIG_ARM_ERRATA_742230 - cmp r6, #0x22 ; only present up to r2p2 - mrcle p15, 0, r10, c15, c0, 1 ; read diagnostic register - orrle r10, r10, #1 << 4 ; set bit #4 - mcrle p15, 0, r10, c15, c0, 1 ; write diagnostic register + cmp r6, #0x22 ; only present up to r2p2 + mrcle p15, 0, r10, c15, c0, 1 ; read diagnostic register + orrle r10, r10, #1 << 4 ; set bit #4 + mcrle p15, 0, r10, c15, c0, 1 ; write diagnostic register #endif #ifdef CONFIG_ARM_ERRATA_743622 - teq r5, #0x00200000 ; only present in r2p* - mrceq p15, 0, r10, c15, c0, 1 ; read diagnostic register - orreq r10, r10, #1 << 6 ; set bit #6 - mcreq p15, 0, r10, c15, c0, 1 ; write diagnostic register + teq r5, #0x00200000 ; only present in r2p* + mrceq p15, 0, r10, c15, c0, 1 ; read diagnostic register + orreq r10, r10, #1 << 6 ; set bit #6 + mcreq p15, 0, r10, c15, c0, 1 ; write diagnostic register #endif - ; set VBAR to the _vector_table address in linker script + ; set VBAR to the _vector_table address in linker script ldr r0, =vector_base mcr p15, 0, r0, c12, c0, 0 @@ -178,18 +178,18 @@ OKToRun ldr r6, =0xffff str r6, [r7] - ; Write to ACTLR + ; Write to ACTLR mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR orr r0, r0, #(0x01 << 6) ; SMP bit - orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast + orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast mcr p15, 0,r0, c1, c0, 1 ; Write ACTLR -; Invalidate caches and TLBs - mov r0,#0 ; r0 = 0 - mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs - mcr p15, 0, r0, c7, c5, 0 ; invalidate icache - mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array - bl invalidate_dcache ; invalidate dcache +; Invalidate caches and TLBs + mov r0,#0 ; r0 = 0 + mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs + mcr p15, 0, r0, c7, c5, 0 ; invalidate icache + mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array + bl invalidate_dcache ; invalidate dcache ; Invalidate L2c Cache ; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) @@ -219,21 +219,21 @@ OKToRun ldr r0,=L2CCSync ; need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET ; Load L2CC base address base + sync register ; poll for completion -Sync +Sync ldr r1, [r0] cmp r1, #0 bne Sync ldr r0,=L2CCIntRaw ; clear pending interrupts ldr r1,[r0] - ldr r0,=L2CCIntClear + ldr r0,=L2CCIntClear str r1,[r0] #endif - ; Disable MMU, if enabled - mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1 - bic r0, r0, #0x1 ; clear bit 0 - mcr p15, 0, r0, c1, c0, 0 ; write value back + ; Disable MMU, if enabled + mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1 + bic r0, r0, #0x1 ; clear bit 0 + mcr p15, 0, r0, c1, c0, 0 ; write value back #ifdef SHAREABLE_DDR ; Mark the entire DDR memory as shareable @@ -262,10 +262,10 @@ mmu_loop bge mmu_loop ; loop till 512MB is covered #endif - mrs r0, cpsr ; get the current PSR - mvn r1, #0x1f ; set up the irq stack pointer + mrs r0, cpsr ; get the current PSR + mvn r1, #0x1f ; set up the irq stack pointer and r2, r1, r0 - orr r2, r2, #0x12 ; IRQ mode + orr r2, r2, #0x12 ; IRQ mode msr cpsr, r2 ; was cpsr, apsr is considered synonym ldr r13,=SFE(IRQ_STACK) ; IRQ stack pointer @@ -283,55 +283,55 @@ mmu_loop msr cpsr, r2 ; was cpsr, apsr is considered synonym ldr r13,=SFE(ABT_STACK) ; Abort stack pointer - mrs r0, cpsr ; was cpsr, get the current PSR - mvn r1, #0x1f ; set up the FIQ stack pointer + mrs r0, cpsr ; was cpsr, get the current PSR + mvn r1, #0x1f ; set up the FIQ stack pointer and r2, r1, r0 - orr r2, r2, #0x11 ; FIQ mode + orr r2, r2, #0x11 ; FIQ mode msr cpsr, r2 ; was cpsr - ldr r13,=SFE(FIQ_STACK) ; FIQ stack pointer + ldr r13,=SFE(FIQ_STACK) ; FIQ stack pointer - mrs r0, cpsr ; was cpsr, get the current PSR - mvn r1, #0x1f ; set up the Undefine stack pointer + mrs r0, cpsr ; was cpsr, get the current PSR + mvn r1, #0x1f ; set up the Undefine stack pointer and r2, r1, r0 - orr r2, r2, #0x1b ; Undefine mode + orr r2, r2, #0x1b ; Undefine mode msr cpsr, r2 ; was cpsr - ldr r13,=SFE(UND_STACK) ; Undefine stack pointer + ldr r13,=SFE(UND_STACK) ; Undefine stack pointer - mrs r0, cpsr ; was cpsr, get the current PSR - mvn r1, #0x1f ; set up the system stack pointer + mrs r0, cpsr ; was cpsr, get the current PSR + mvn r1, #0x1f ; set up the system stack pointer and r2, r1, r0 - orr r2, r2, #0x1f ; SYS mode + orr r2, r2, #0x1f ; SYS mode msr cpsr, r2 ; was cpsr, apsr is considered synonym ldr r13,=SFE(CSTACK) ; SYS stack pointer - ; enable MMU and cache + ; enable MMU and cache - ldr r0,=TblBase ; Load MMU translation table base - orr r0, r0, #0x5B ; Outer-cacheable, WB - mcr p15, 0, r0, c2, c0, 0 ; TTB0 - - mvn r0,#0 ; Load MMU domains -- all ones=manager + ldr r0,=TblBase ; Load MMU translation table base + orr r0, r0, #0x5B ; Outer-cacheable, WB + mcr p15, 0, r0, c2, c0, 0 ; TTB0 + + mvn r0,#0 ; Load MMU domains -- all ones=manager mcr p15,0,r0,c3,c0,0 ; Enable mmu, icahce and dcache ldr r0,=CRValMmuCac - mcr p15,0,r0,c1,c0,0 ; Enable cache and MMU - dsb ; dsb allow the MMU to start up - isb ; isb flush prefetch buffer + mcr p15,0,r0,c1,c0,0 ; Enable cache and MMU + dsb ; dsb allow the MMU to start up + isb ; isb flush prefetch buffer ; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) #if USE_AMP!=1 - ldr r0,=SLCRUnlockReg ; Load SLCR base address base + unlock register - ldr r1,=SLCRUnlockKey ; set unlock key - str r1, [r0] ; Unlock SLCR + ldr r0,=SLCRUnlockReg ; Load SLCR base address base + unlock register + ldr r1,=SLCRUnlockKey ; set unlock key + str r1, [r0] ; Unlock SLCR - ldr r0,=SLCRL2cRamReg ; Load SLCR base address base + l2c Ram Control register ldr r1,=SLCRL2cRamConfig ; set the configuration value */ - str r1, [r0] ; store the L2c Ram Control Register + ldr r0,=SLCRL2cRamReg ; Load SLCR base address base + l2c Ram Control register ldr r1,=SLCRL2cRamConfig ; set the configuration value */ + str r1, [r0] ; store the L2c Ram Control Register - ldr r0,=SLCRlockReg ; Load SLCR base address base + lock register - ldr r1,=SLCRlockKey ; set lock key - str r1, [r0] ; lock SLCR + ldr r0,=SLCRlockReg ; Load SLCR base address base + lock register + ldr r1,=SLCRlockKey ; set lock key + str r1, [r0] ; lock SLCR ldr r0,=L2CCCrtl ; Load L2CC base address base + control register ldr r1,[r0] ; read the register mov r2, #L2CCControl ; set the enable bit @@ -340,23 +340,23 @@ mmu_loop #endif mov r0, r0 - mrc p15, 0, r1, c1, c0, 2 ; read cp access control register (CACR) into r1 - orr r1, r1, #(0xf << 20) ; enable full access for p10 & p11 - mcr p15, 0, r1, c1, c0, 2 ; write back into CACR + mrc p15, 0, r1, c1, c0, 2 ; read cp access control register (CACR) into r1 + orr r1, r1, #(0xf << 20) ; enable full access for p10 & p11 + mcr p15, 0, r1, c1, c0, 2 ; write back into CACR - ; enable vfp - fmrx r1, FPEXC ; read the exception register - orr r1,r1, #FPEXC_EN ; set VFP enable bit, leave the others in orig state - fmxr FPEXC, r1 ; write back the exception register + ; enable vfp + fmrx r1, FPEXC ; read the exception register + orr r1,r1, #FPEXC_EN ; set VFP enable bit, leave the others in orig state + fmxr FPEXC, r1 ; write back the exception register - mrc p15, 0, r0, c1, c0, 0 ; flow prediction enable + mrc p15, 0, r0, c1, c0, 0 ; flow prediction enable orr r0, r0, #(0x01 << 11) ; #0x8000 mcr p15,0,r0,c1,c0,0 - mrc p15, 0, r0, c1, c0, 1 ; read Auxiliary Control Register - orr r0, r0, #(0x1 << 2) ; enable Dside prefetch - orr r0, r0, #(0x1 << 1) ; enable L2 prefetch - mcr p15, 0, r0, c1, c0, 1 ; write Auxiliary Control Register + mrc p15, 0, r0, c1, c0, 1 ; read Auxiliary Control Register + orr r0, r0, #(0x1 << 2) ; enable Dside prefetch + orr r0, r0, #(0x1 << 1) ; enable L2 prefetch + mcr p15, 0, r0, c1, c0, 1 ; write Auxiliary Control Register ; Initialize the vector table ;bl Xil_ExceptionInit @@ -372,12 +372,12 @@ mmu_loop mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO mcr p15, 5, r0, c15, c5, 2 ; Write Lockdown TLB VA -; Reset and start Cycle Counter - mov r2, #0x80000000 ; clear overflow +; Reset and start Cycle Counter + mov r2, #0x80000000 ; clear overflow mcr p15, 0, r2, c9, c12, 3 - mov r2, #0xd ; D, C, E + mov r2, #0xd ; D, C, E mcr p15, 0, r2, c9, c12, 0 - mov r2, #0x80000000 ; enable cycle counter + mov r2, #0x80000000 ; enable cycle counter mcr p15, 0, r2, c9, c12, 1 ; Reset and start Global Timer @@ -388,11 +388,11 @@ mmu_loop ; make sure argc and argv are valid mov r0, #0 mov r1, #0 - b __cmain ; jump to C startup code - - and r0, r0, r0 ; no op - -Ldone b Ldone ; Paranoia: we should never get here + b __cmain ; jump to C startup code + + and r0, r0, r0 ; no op + +Ldone b Ldone ; Paranoia: we should never get here ; ************************************************************************* @@ -403,47 +403,47 @@ Ldone b Ldone ; Paranoia: we should never get here ; * the whole D-cache. Need to invalidate each line. ; * ; ************************************************************************* - + invalidate_dcache - mrc p15, 1, r0, c0, c0, 1 ; read CLIDR + mrc p15, 1, r0, c0, c0, 1 ; read CLIDR ands r3, r0, #0x7000000 - mov r3, r3, lsr #23 ; cache level value (naturally aligned) + mov r3, r3, lsr #23 ; cache level value (naturally aligned) beq finished - mov r10, #0 ; start with level 0 + mov r10, #0 ; start with level 0 loop1 - add r2, r10, r10, lsr #1 ; work out 3xcachelevel - mov r1, r0, lsr r2 ; bottom 3 bits are the Cache type for this level - and r1, r1, #7 ; get those 3 bits alone + add r2, r10, r10, lsr #1 ; work out 3xcachelevel + mov r1, r0, lsr r2 ; bottom 3 bits are the Cache type for this level + and r1, r1, #7 ; get those 3 bits alone cmp r1, #2 - blt skip ; no cache or only instruction cache at this level - mcr p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register - isb ; isb to sync the change to the CacheSizeID reg - mrc p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register - and r2, r1, #7 ; extract the line length field - add r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + blt skip ; no cache or only instruction cache at this level + mcr p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + isb ; isb to sync the change to the CacheSizeID reg + mrc p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + and r2, r1, #7 ; extract the line length field + add r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 ; r4 is the max number on the way size (right aligned) - clz r5, r4 ; r5 is the bit position of the way size increment + ands r4, r4, r1, lsr #3 ; r4 is the max number on the way size (right aligned) + clz r5, r4 ; r5 is the bit position of the way size increment ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 ; r7 is the max number of the index size (right aligned) + ands r7, r7, r1, lsr #13 ; r7 is the max number of the index size (right aligned) loop2 - mov r9, r4 ; r9 working copy of the max way size (right aligned) + mov r9, r4 ; r9 working copy of the max way size (right aligned) loop3 - orr r11, r10, r9, lsl r5 ; factor in the way number and cache number into r11 - orr r11, r11, r7, lsl r2 ; factor in the index number - mcr p15, 0, r11, c7, c6, 2 ; invalidate by set/way - subs r9, r9, #1 ; decrement the way number + orr r11, r10, r9, lsl r5 ; factor in the way number and cache number into r11 + orr r11, r11, r7, lsl r2 ; factor in the index number + mcr p15, 0, r11, c7, c6, 2 ; invalidate by set/way + subs r9, r9, #1 ; decrement the way number bge loop3 - subs r7, r7, #1 ; decrement the index + subs r7, r7, #1 ; decrement the index bge loop2 skip - add r10, r10, #2 ; increment the cache number + add r10, r10, #2 ; increment the cache number cmp r3, r10 bgt loop1 finished - mov r10, #0 ; swith back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr + mov r10, #0 ; swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr dsb isb diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/clock.c b/lib/bsp/standalone/src/cortexa9/iccarm/clock.c old mode 100755 new mode 100644 index f246da0e..03a4ceeb --- a/lib/bsp/standalone/src/cortexa9/iccarm/clock.c +++ b/lib/bsp/standalone/src/cortexa9/iccarm/clock.c @@ -53,4 +53,3 @@ clock_t (clock)(void) return ((clock_t) -1); } - diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/close.c b/lib/bsp/standalone/src/cortexa9/iccarm/close.c old mode 100755 new mode 100644 index 085db764..a3431bde --- a/lib/bsp/standalone/src/cortexa9/iccarm/close.c +++ b/lib/bsp/standalone/src/cortexa9/iccarm/close.c @@ -31,8 +31,9 @@ ******************************************************************************/ #include +#include "xil_types.h" -int __close(int fd) +sint32 __close(sint32 fd) { (void)fd; return (0); diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/exit.c b/lib/bsp/standalone/src/cortexa9/iccarm/exit.c old mode 100755 new mode 100644 index b6a1cdbd..32da10f9 --- a/lib/bsp/standalone/src/cortexa9/iccarm/exit.c +++ b/lib/bsp/standalone/src/cortexa9/iccarm/exit.c @@ -32,8 +32,11 @@ #include #include +#include "xil_types.h" -void exit(int arg) +void exit(sint32 arg) { - while(1); + while(1) { + ; + } } diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/low_level_init.c b/lib/bsp/standalone/src/cortexa9/iccarm/low_level_init.c old mode 100755 new mode 100644 index 74c724a1..6165df31 --- a/lib/bsp/standalone/src/cortexa9/iccarm/low_level_init.c +++ b/lib/bsp/standalone/src/cortexa9/iccarm/low_level_init.c @@ -46,14 +46,15 @@ * initialized. */ +#include "xil_types.h" #ifdef __cplusplus extern "C" { #endif -int __low_level_init(void); +s32 __low_level_init(void); -int __low_level_init(void) +s32 __low_level_init(void) { /*==================================*/ /* Initialize hardware. */ diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/lseek.c b/lib/bsp/standalone/src/cortexa9/iccarm/lseek.c old mode 100755 new mode 100644 index 2a2eca53..53dbb6e4 --- a/lib/bsp/standalone/src/cortexa9/iccarm/lseek.c +++ b/lib/bsp/standalone/src/cortexa9/iccarm/lseek.c @@ -51,8 +51,10 @@ #include #include +#include "xil_types.h" +sint32 __lseek(sint32 handle, sint32 offset, sint32 whence); -long __lseek(int handle, long offset, int whence) +sint32 __lseek(sint32 handle, sint32 offset, sint32 whence) { return (-1); } diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/open.c b/lib/bsp/standalone/src/cortexa9/iccarm/open.c old mode 100755 new mode 100644 index 497cddbb..bea413b1 --- a/lib/bsp/standalone/src/cortexa9/iccarm/open.c +++ b/lib/bsp/standalone/src/cortexa9/iccarm/open.c @@ -44,11 +44,12 @@ */ #include +#include "xil_types.h" +sint32 __open(const char8 * filename, sint32 mode); -int __open(const char * filename, int mode) +sint32 __open(const char8 * filename, sint32 mode) { return 0; } - diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/read.c b/lib/bsp/standalone/src/cortexa9/iccarm/read.c old mode 100755 new mode 100644 index 876e4d74..67bfc787 --- a/lib/bsp/standalone/src/cortexa9/iccarm/read.c +++ b/lib/bsp/standalone/src/cortexa9/iccarm/read.c @@ -43,12 +43,13 @@ */ #include +#include "xil_types.h" +size_t __read(sint32 handle, u8 * buffer, size_t size); -size_t __read(int handle, unsigned char * buffer, size_t size) +size_t __read(sint32 handle, u8 * buffer, size_t size) { return size; } - diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/remove.c b/lib/bsp/standalone/src/cortexa9/iccarm/remove.c old mode 100755 new mode 100644 index ff42d3be..b891a442 --- a/lib/bsp/standalone/src/cortexa9/iccarm/remove.c +++ b/lib/bsp/standalone/src/cortexa9/iccarm/remove.c @@ -38,11 +38,12 @@ */ #include +#include "xil_types.h" +sint32 remove(const char8 * filename); -int remove(const char * filename) +sint32 remove(const char8 * filename) { return 0; } - diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/translation_table.s b/lib/bsp/standalone/src/cortexa9/iccarm/translation_table.s old mode 100755 new mode 100644 index 8fa0112a..3c3578d6 --- a/lib/bsp/standalone/src/cortexa9/iccarm/translation_table.s +++ b/lib/bsp/standalone/src/cortexa9/iccarm/translation_table.s @@ -66,11 +66,11 @@ MMUTable ; Each entry covers a 1MB section. -; 0x00000000 - 0x3ffffff (DDR Cacheable) +; 0x00000000 - 0x3ffffff (DDR Cacheable) count SETA 0 sect SETA 0 REPT 0x400 - DCD sect + 0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 + DCD sect + 0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 sect SETA sect+0x100000 count SETA count+1 ENDR @@ -94,7 +94,7 @@ count SETA count+1 ; 0xc0000000 - 0xdfffffff (undef) count SETA 0 REPT 0x200 - DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 sect SETA sect+0x100000 count SETA count+1 ENDR @@ -102,7 +102,7 @@ count SETA count+1 ; 0xe0000000 - 0xe02fffff (IOP dev) count SETA 0 REPT 0x3 - DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 sect SETA sect+0x100000 count SETA count+1 ENDR diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/write.c b/lib/bsp/standalone/src/cortexa9/iccarm/write.c old mode 100755 new mode 100644 index 786ccd8d..a8317c99 --- a/lib/bsp/standalone/src/cortexa9/iccarm/write.c +++ b/lib/bsp/standalone/src/cortexa9/iccarm/write.c @@ -46,6 +46,7 @@ */ #include +#include "xil_types.h" #if 0 @@ -55,15 +56,15 @@ * (i.e. flush) when the application terminates. */ -size_t __write(int handle, const unsigned char * buffer, size_t size) +size_t __write(sint32 handle, const u8 * buffer, size_t size) { - unsigned int volatile *uart_base = (unsigned int *)0xE0001000; - int i; + u32 volatile *uart_base = (u32 *)0xE0001000U; + s32 i; for (i =0; i < size;i++) { /* wait if TNFUL */ - while (*(uart_base + 11) & (1 << 14)) ; - *(uart_base + 12) = buffer[i]; + while (*(uart_base + 11U) & (1U << 14U)) ; + *(uart_base + 12U) = buffer[i]; } return 0; } @@ -75,7 +76,7 @@ size_t __write(int handle, const unsigned char * buffer, size_t size) #ifdef __cplusplus extern "C" { - int _write (int fd, char* buf, int nbytes); + sint32 _write (sint32 fd, char8* buf, sint32 nbytes); } #endif @@ -84,12 +85,12 @@ extern "C" { * stdout and stderr are the same. Since we have no filesystem, * open will only return an error. */ -int -write (int fd, char* buf, int nbytes) +sint32 +write (sint32 fd, char8* buf, sint32 nbytes) { #ifdef STDOUT_BASEADDRESS - int i; + s32 i; (void)fd; for (i = 0; i < nbytes; i++) { @@ -108,10 +109,10 @@ write (int fd, char* buf, int nbytes) } size_t -__write (int fd, const unsigned char* buf, size_t nbytes) +__write (sint32 fd, const u8* buf, size_t nbytes) { #ifdef STDOUT_BASEADDRESS - int i; + s32 i; (void)fd; for (i = 0; i < nbytes; i++) { @@ -129,4 +130,3 @@ __write (int fd, const unsigned char* buf, size_t nbytes) #endif } - diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.c b/lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.c old mode 100755 new mode 100644 index 1deaf188..bd471a5f --- a/lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.c +++ b/lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.c @@ -61,9 +61,9 @@ /************************** Function Prototypes *****************************/ /* embedded assembler instructions */ -int mfcpsr (void) +s32 mfcpsr (void) { - int rval; + s32 rval; asm("mrs %0, cpsr" : "=r"(rval)); return rval; } diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.h b/lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.h old mode 100755 new mode 100644 index d8f344da..4c705685 --- a/lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.h +++ b/lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.h @@ -53,6 +53,7 @@ /***************************** Include Files ********************************/ +#include "xil_types.h" #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ @@ -87,7 +88,7 @@ extern "C" { : : "r" (v)\ ) -#define mfgpr(rn) ({unsigned int rval; \ +#define mfgpr(rn) ({u32 rval; \ __asm volatile(\ "mov %0,r" stringify(rn) "\n"\ : "=r" (rval)\ @@ -108,7 +109,7 @@ extern "C" { /* Memory Operations */ -#define ldr(adr) ({unsigned long rval; \ +#define ldr(adr) ({u32 rval; \ __asm volatile(\ "ldr %0,[%1]"\ : "=r" (rval) : "r" (adr)\ @@ -116,7 +117,7 @@ extern "C" { rval;\ }) -#define ldrb(adr) ({unsigned char rval; \ +#define ldrb(adr) ({u8 rval; \ __asm volatile(\ "ldrb %0,[%1]"\ : "=r" (rval) : "r" (adr)\ @@ -135,7 +136,7 @@ extern "C" { ) /* Count leading zeroes (clz) */ -#define clz(arg) ({unsigned char rval; \ +#define clz(arg) ({u8 rval; \ __asm volatile(\ "clz %0,%1"\ : "=r" (rval) : "r" (arg)\ @@ -149,7 +150,7 @@ extern "C" { : : "r" (v)\ ); -/*#define mfcp(rn) ({unsigned int rval; \ +/*#define mfcp(rn) ({u32 rval; \ __asm volatile(\ "mrc " rn "\n"\ : "=r" (rval)\ diff --git a/lib/bsp/standalone/src/cortexa9/print.c b/lib/bsp/standalone/src/cortexa9/print.c old mode 100755 new mode 100644 diff --git a/lib/bsp/standalone/src/cortexa9/putnum.c b/lib/bsp/standalone/src/cortexa9/putnum.c old mode 100755 new mode 100644 index f2af0ae2..33c3a6c4 --- a/lib/bsp/standalone/src/cortexa9/putnum.c +++ b/lib/bsp/standalone/src/cortexa9/putnum.c @@ -1,5 +1,5 @@ /* putnum.c -- put a hex number on the output device. - * + * * Copyright (c) 1995 Cygnus Support * * The authors hereby grant permission to use, copy, modify, distribute, @@ -17,25 +17,43 @@ * putnum -- print a 32 bit number in hex */ -extern void print (char* ); +/***************************** Include Files *********************************/ +#include "xil_types.h" -void putnum(unsigned int num) +/************************** Function Prototypes ******************************/ +extern void print (const char8 *ptr); +void putnum(u32 num); + +void putnum(u32 num) { - char buf[9]; - int cnt; - char *ptr; - int digit; - - ptr = buf; - for (cnt = 7 ; cnt >= 0 ; cnt--) { - digit = (num >> (cnt * 4)) & 0xf; - - if (digit <= 9) - *ptr++ = (char) ('0' + digit); - else - *ptr++ = (char) ('a' - 10 + digit); + char8 buf[9]; + s32 cnt; + s32 i; + char8 *ptr; + u32 digit; + for(i = 0; i<9; i++) { + buf[i] = '0'; } - *ptr = (char) 0; + ptr = buf; + for (cnt = 7 ; cnt >= 0 ; cnt--) { + digit = ((num >> ((u16)cnt * 4U)) & 0xfU); + + if ((digit <= 9U) && (ptr != NULL)) { + digit += (u32)'0'; + *ptr = ((char8) digit); + ptr += 1; + } else if (ptr != NULL) { + digit += ((u32)'a' - (u32)10); + *ptr = ((char8)digit); + ptr += 1; + } else { + /*Made for MisraC Compliance*/; + } + } + + if(ptr != NULL) { + *ptr = (char8) 0; + } print (buf); } diff --git a/lib/bsp/standalone/src/cortexa9/sleep.c b/lib/bsp/standalone/src/cortexa9/sleep.c old mode 100755 new mode 100644 index 344eae28..56f6da4d --- a/lib/bsp/standalone/src/cortexa9/sleep.c +++ b/lib/bsp/standalone/src/cortexa9/sleep.c @@ -64,12 +64,12 @@ * @note None. * ****************************************************************************/ -int sleep(unsigned int seconds) +s32 sleep(u32 seconds) { XTime tEnd, tCur; XTime_GetTime(&tCur); - tEnd = tCur + ((XTime) seconds) * COUNTS_PER_SECOND; + tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND); do { XTime_GetTime(&tCur); diff --git a/lib/bsp/standalone/src/cortexa9/sleep.h b/lib/bsp/standalone/src/cortexa9/sleep.h old mode 100755 new mode 100644 index 337fc571..85bd6c62 --- a/lib/bsp/standalone/src/cortexa9/sleep.h +++ b/lib/bsp/standalone/src/cortexa9/sleep.h @@ -29,6 +29,7 @@ * this Software without prior written authorization from Xilinx. * ******************************************************************************/ +#include "xil_types.h" #ifndef SLEEP_H #define SLEEP_H @@ -37,8 +38,8 @@ extern "C" { #endif -int usleep(unsigned int useconds); -int sleep(unsigned int seconds); +s32 usleep(u32 useconds); +s32 sleep(u32 seconds); #ifdef __cplusplus } diff --git a/lib/bsp/standalone/src/cortexa9/smc.h b/lib/bsp/standalone/src/cortexa9/smc.h old mode 100755 new mode 100644 index fea503bf..d25e73fd --- a/lib/bsp/standalone/src/cortexa9/smc.h +++ b/lib/bsp/standalone/src/cortexa9/smc.h @@ -66,42 +66,42 @@ extern "C" { /************************** Constant Definitions *****************************/ /* Memory controller configuration register offset */ -#define XSMCPSS_MC_STATUS 0x000 /* Controller status reg, RO */ -#define XSMCPSS_MC_INTERFACE_CONFIG 0x004 /* Interface config reg, RO */ -#define XSMCPSS_MC_SET_CONFIG 0x008 /* Set configuration reg, WO */ -#define XSMCPSS_MC_CLR_CONFIG 0x00C /* Clear config reg, WO */ -#define XSMCPSS_MC_DIRECT_CMD 0x010 /* Direct command reg, WO */ -#define XSMCPSS_MC_SET_CYCLES 0x014 /* Set cycles register, WO */ -#define XSMCPSS_MC_SET_OPMODE 0x018 /* Set opmode register, WO */ -#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020 /* Refresh period_0 reg, RW */ -#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024 /* Refresh period_1 reg, RW */ +#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */ +#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */ +#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */ +#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */ +#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */ +#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */ +#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */ +#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */ +#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */ /* Chip select configuration register offset */ -#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100 /* Interface 0 chip 0 config */ -#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120 /* Interface 0 chip 1 config */ -#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140 /* Interface 0 chip 2 config */ -#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160 /* Interface 0 chip 3 config */ -#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180 /* Interface 1 chip 0 config */ -#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0 /* Interface 1 chip 1 config */ -#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0 /* Interface 1 chip 2 config */ -#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0 /* Interface 1 chip 3 config */ +#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */ +#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */ +#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */ +#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */ +#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */ +#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */ +#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */ +#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */ /* User configuration register offset */ -#define XSMCPSS_UC_STATUS_OFFSET 0x200 /* User status reg, RO */ -#define XSMCPSS_UC_CONFIG_OFFSET 0x204 /* User config reg, WO */ +#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */ +#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */ /* Integration test register offset */ -#define XSMCPSS_IT_OFFSET 0xE00 +#define XSMCPSS_IT_OFFSET 0xE00U /* ID configuration register offset */ -#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0 -#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4 -#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8 -#define XSMCPSS_ID_PERIP_3_OFFSET 0xFEC -#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0 -#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4 -#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8 -#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFC +#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U +#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U +#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U +#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU +#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U +#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U +#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U +#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU /************************** Variable Definitions *****************************/ diff --git a/lib/bsp/standalone/src/cortexa9/usleep.c b/lib/bsp/standalone/src/cortexa9/usleep.c old mode 100755 new mode 100644 index a8cddf0c..db9ca675 --- a/lib/bsp/standalone/src/cortexa9/usleep.c +++ b/lib/bsp/standalone/src/cortexa9/usleep.c @@ -55,11 +55,12 @@ #include "sleep.h" #include "xtime_l.h" #include "xparameters.h" +#include "xil_types.h" #include "xpseudo_asm.h" #include "xreg_cortexa9.h" /* Global Timer is always clocked at half of the CPU frequency */ -#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2*1000000)) +#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U)) /*****************************************************************************/ /** @@ -74,12 +75,12 @@ * @note None. * ****************************************************************************/ -int usleep(unsigned int useconds) +s32 usleep(u32 useconds) { XTime tEnd, tCur; XTime_GetTime(&tCur); - tEnd = tCur + ((XTime) useconds) * COUNTS_PER_USECOND; + tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND); do { XTime_GetTime(&tCur); diff --git a/lib/bsp/standalone/src/cortexa9/vectors.c b/lib/bsp/standalone/src/cortexa9/vectors.c old mode 100755 new mode 100644 diff --git a/lib/bsp/standalone/src/cortexa9/vectors.h b/lib/bsp/standalone/src/cortexa9/vectors.h old mode 100755 new mode 100644 diff --git a/lib/bsp/standalone/src/cortexa9/xil_cache.c b/lib/bsp/standalone/src/cortexa9/xil_cache.c old mode 100755 new mode 100644 index b124fc5a..c602607c --- a/lib/bsp/standalone/src/cortexa9/xil_cache.c +++ b/lib/bsp/standalone/src/cortexa9/xil_cache.c @@ -100,11 +100,11 @@ /************************** Variable Definitions *****************************/ -#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */ +#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */ #ifdef __GNUC__ - extern int _stack_end; - extern int _stack; + extern s32 _stack_end; + extern s32 _stack; #endif /**************************************************************************** @@ -149,9 +149,9 @@ static void Xil_L2CacheSync(void) #endif { #ifdef CONFIG_PL310_ERRATA_753970 - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET, 0x0); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET, 0x0U); #else - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U); #endif } @@ -202,7 +202,7 @@ void Xil_DCacheDisable(void) ****************************************************************************/ void Xil_DCacheInvalidate(void) { - unsigned int currmask; + u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); @@ -228,9 +228,9 @@ void Xil_DCacheInvalidate(void) * @note The bottom 4 bits are set to 0, forced by architecture. * ****************************************************************************/ -void Xil_DCacheInvalidateLine(unsigned int adr) +void Xil_DCacheInvalidateLine(u32 adr) { - unsigned int currmask; + u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); @@ -302,46 +302,46 @@ void Xil_DCacheInvalidateLine(unsigned int adr) * @note None. * ****************************************************************************/ -void Xil_DCacheInvalidateRange(unsigned int adr, unsigned len) +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) { - const unsigned cacheline = 32; - unsigned int end; - unsigned int tempadr = adr; - unsigned int tempend; - unsigned int currmask; - volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR + + const u32 cacheline = 32U; + u32 end; + u32 tempadr = adr; + u32 tempend; + u32 currmask; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET); currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0) { + if (len != 0U) { end = tempadr + len; tempend = end; /* Select L1 Data cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); - if (tempadr & (cacheline-1)) { - tempadr &= ~(cacheline - 1); + if ((tempadr & (cacheline-1U)) != 0U) { + tempadr &= (~(cacheline - 1U)); Xil_L1DCacheFlushLine(tempadr); /* Disable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x3); + Xil_L2WriteDebugCtrl(0x3U); Xil_L2CacheFlushLine(tempadr); /* Enable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x0); + Xil_L2WriteDebugCtrl(0x0U); Xil_L2CacheSync(); tempadr += cacheline; } - if (tempend & (cacheline-1)) { - tempend &= ~(cacheline - 1); + if ((tempend & (cacheline-1U)) != 0U) { + tempend &= (~(cacheline - 1U)); Xil_L1DCacheFlushLine(tempend); /* Disable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x3); + Xil_L2WriteDebugCtrl(0x3U); Xil_L2CacheFlushLine(tempend); /* Enable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x0); + Xil_L2WriteDebugCtrl(0x0U); Xil_L2CacheSync(); } @@ -357,7 +357,7 @@ void Xil_DCacheInvalidateRange(unsigned int adr, unsigned len) __asm volatile ("mcr " \ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (tempadr)); #else - { volatile register unsigned int Reg + { volatile register u32 Reg __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC); Reg = tempadr; } #endif @@ -382,7 +382,7 @@ void Xil_DCacheInvalidateRange(unsigned int adr, unsigned len) ****************************************************************************/ void Xil_DCacheFlush(void) { - unsigned int currmask; + u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); @@ -407,21 +407,21 @@ void Xil_DCacheFlush(void) * @note The bottom 4 bits are set to 0, forced by architecture. * ****************************************************************************/ -void Xil_DCacheFlushLine(unsigned int adr) +void Xil_DCacheFlushLine(u32 adr) { - unsigned int currmask; + u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); Xil_L1DCacheFlushLine(adr); /* Disable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x3); + Xil_L2WriteDebugCtrl(0x3U); Xil_L2CacheFlushLine(adr); /* Enable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x0); + Xil_L2WriteDebugCtrl(0x0U); Xil_L2CacheSync(); mtcpsr(currmask); } @@ -441,41 +441,42 @@ void Xil_DCacheFlushLine(unsigned int adr) * @note None. * ****************************************************************************/ -void Xil_DCacheFlushRange(unsigned int adr, unsigned len) +void Xil_DCacheFlushRange(INTPTR adr, u32 len) { - const unsigned cacheline = 32; - unsigned int end; - unsigned int currmask; - volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR + + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET); currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0) { + if (len != 0U) { /* Back the starting address up to the start of a cache line * perform cache operations until adr+len */ - end = adr + len; - adr &= ~(cacheline - 1); + end = LocalAddr + len; + LocalAddr &= ~(cacheline - 1U); - while (adr < end) { + while (LocalAddr < end) { #ifdef __GNUC__ /* Flush L1 Data cache line */ __asm__ __volatile__("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (adr)); + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (LocalAddr)); #elif defined (__ICCARM__) __asm volatile ("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (adr)); + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (LocalAddr)); #else - { volatile register unsigned int Reg + { volatile register u32 Reg __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC); - Reg = adr; } + Reg = LocalAddr; } #endif /* Flush L2 cache line */ - *L2CCOffset = adr; + *L2CCOffset = LocalAddr; dsb(); - adr += cacheline; + LocalAddr += cacheline; } } dsb(); @@ -496,9 +497,9 @@ void Xil_DCacheFlushRange(unsigned int adr, unsigned len) * @note The bottom 4 bits are set to 0, forced by architecture. * ****************************************************************************/ -void Xil_DCacheStoreLine(unsigned int adr) +void Xil_DCacheStoreLine(u32 adr) { - unsigned int currmask; + u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); @@ -555,7 +556,7 @@ void Xil_ICacheDisable(void) ****************************************************************************/ void Xil_ICacheInvalidate(void) { - unsigned int currmask; + u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); @@ -579,9 +580,9 @@ void Xil_ICacheInvalidate(void) * @note The bottom 4 bits are set to 0, forced by architecture. * ****************************************************************************/ -void Xil_ICacheInvalidateLine(unsigned int adr) +void Xil_ICacheInvalidateLine(u32 adr) { - unsigned int currmask; + u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); @@ -606,45 +607,46 @@ void Xil_ICacheInvalidateLine(unsigned int adr) * @note None. * ****************************************************************************/ -void Xil_ICacheInvalidateRange(unsigned int adr, unsigned len) +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) { - const unsigned cacheline = 32; - unsigned int end; - volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR + + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET); - unsigned int currmask; + u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0) { + if (len != 0U) { /* Back the starting address up to the start of a cache line * perform cache operations until adr+len */ - end = adr + len; - adr = adr & ~(cacheline - 1); + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); /* Select cache L0 I-cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); - while (adr < end) { + while (LocalAddr < end) { /* Invalidate L2 cache line */ - *L2CCOffset = adr; + *L2CCOffset = LocalAddr; dsb(); #ifdef __GNUC__ /* Invalidate L1 I-cache line */ __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (adr)); + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (LocalAddr)); #elif defined (__ICCARM__) __asm volatile ("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (adr)); + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (LocalAddr)); #else - { volatile register unsigned int Reg + { volatile register u32 Reg __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU); - Reg = adr; } + Reg = LocalAddr; } #endif - adr += cacheline; + LocalAddr += cacheline; } } @@ -666,7 +668,7 @@ void Xil_ICacheInvalidateRange(unsigned int adr, unsigned len) ****************************************************************************/ void Xil_L1DCacheEnable(void) { - register unsigned int CtrlReg; + register u32 CtrlReg; /* enable caches only if they are disabled */ #ifdef __GNUC__ @@ -674,10 +676,10 @@ void Xil_L1DCacheEnable(void) #elif defined (__ICCARM__) mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); #else - { volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL); + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); CtrlReg = Reg; } #endif - if (CtrlReg & XREG_CP15_CONTROL_C_BIT) { + if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) { return; } @@ -703,7 +705,7 @@ void Xil_L1DCacheEnable(void) ****************************************************************************/ void Xil_L1DCacheDisable(void) { - register unsigned int CtrlReg; + register u32 CtrlReg; /* clean and invalidate the Data cache */ Xil_L1DCacheFlush(); @@ -714,7 +716,7 @@ void Xil_L1DCacheDisable(void) #elif defined (__ICCARM__) mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); #else - { volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL); + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); CtrlReg = Reg; } #endif @@ -738,21 +740,21 @@ void Xil_L1DCacheDisable(void) ****************************************************************************/ void Xil_L1DCacheInvalidate(void) { - register unsigned int CsidReg, C7Reg; - unsigned int CacheSize, LineSize, NumWays; - unsigned int Way, WayIndex, Set, SetIndex, NumSet; - unsigned int currmask; + register u32 CsidReg, C7Reg; + u32 CacheSize, LineSize, NumWays; + u32 Way, WayIndex, Set, SetIndex, NumSet; + u32 currmask; #ifdef __GNUC__ - unsigned int stack_start,stack_end,stack_size; + u32 stack_start,stack_end,stack_size; #endif currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); #ifdef __GNUC__ - stack_end = (unsigned int )&_stack_end; - stack_start = (unsigned int )&_stack; + stack_end = (u32)&_stack_end; + stack_start = (u32)&_stack; stack_size=stack_start-stack_end; /*Flush stack memory to save return address*/ @@ -760,37 +762,37 @@ void Xil_L1DCacheInvalidate(void) #endif /* Select cache level 0 and D cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); #ifdef __GNUC__ CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); #elif defined (__ICCARM__) mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg); #else - { volatile register unsigned int Reg __asm(XREG_CP15_CACHE_SIZE_ID); + { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID); CsidReg = Reg; } #endif /* Determine Cache Size */ - CacheSize = (CsidReg >> 13) & 0x1FF; - CacheSize +=1; - CacheSize *=128; /* to get number of bytes */ + CacheSize = (CsidReg >> 13U) & 0x1FFU; + CacheSize +=1U; + CacheSize *=128U; /* to get number of bytes */ /* Number of Ways */ - NumWays = (CsidReg & 0x3ff) >> 3; - NumWays += 1; + NumWays = (CsidReg & 0x3ffU) >> 3U; + NumWays += 1U; /* Get the cacheline size, way size, index size from csidr */ - LineSize = (CsidReg & 0x07) + 4; + LineSize = (CsidReg & 0x07U) + 4U; NumSet = CacheSize/NumWays; - NumSet /= (1 << LineSize); + NumSet /= (0x00000001U << LineSize); - Way = 0UL; - Set = 0UL; + Way = 0U; + Set = 0U; /* Invalidate all the cachelines */ - for (WayIndex =0; WayIndex < NumWays; WayIndex++) { - for (SetIndex =0; SetIndex < NumSet; SetIndex++) { + for (WayIndex =0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex =0U; SetIndex < NumSet; SetIndex++) { C7Reg = Way | Set; #ifdef __GNUC__ /* Invalidate by Set/Way */ @@ -800,15 +802,15 @@ void Xil_L1DCacheInvalidate(void) __asm volatile ("mcr " \ XREG_CP15_INVAL_DC_LINE_SW :: "r" (C7Reg)); #else - //mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg); - { volatile register unsigned int Reg + /*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */ + { volatile register u32 Reg __asm(XREG_CP15_INVAL_DC_LINE_SW); Reg = C7Reg; } #endif - Set += (1 << LineSize); + Set += (0x00000001U << LineSize); } - Set=0UL; - Way += 0x40000000; + Set=0U; + Way += 0x40000000U; } /* Wait for L1 invalidate to complete */ @@ -831,10 +833,10 @@ void Xil_L1DCacheInvalidate(void) * @note The bottom 5 bits are set to 0, forced by architecture. * ****************************************************************************/ -void Xil_L1DCacheInvalidateLine(unsigned int adr) +void Xil_L1DCacheInvalidateLine(u32 adr) { - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU))); /* Wait for L1 invalidate to complete */ dsb(); @@ -856,38 +858,39 @@ void Xil_L1DCacheInvalidateLine(unsigned int adr) * @note None. * ****************************************************************************/ -void Xil_L1DCacheInvalidateRange(unsigned int adr, unsigned len) +void Xil_L1DCacheInvalidateRange(u32 adr, u32 len) { - const unsigned cacheline = 32; - unsigned int end; - unsigned int currmask; + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0) { + if (len != 0U) { /* Back the starting address up to the start of a cache line * perform cache operations until adr+len */ - end = adr + len; - adr = adr & ~(cacheline - 1); + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); /* Select cache L0 D-cache in CSSR */ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - while (adr < end) { + while (LocalAddr < end) { #ifdef __GNUC__ __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (adr)); + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (LocalAddr)); #elif defined (__ICCARM__) __asm volatile ("mcr " \ - XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (adr)); + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (LocalAddr)); #else - { volatile register unsigned int Reg + { volatile register u32 Reg __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC); - Reg = adr; } + Reg = LocalAddr; } #endif - adr += cacheline; + LocalAddr += cacheline; } } @@ -910,10 +913,11 @@ void Xil_L1DCacheInvalidateRange(unsigned int adr, unsigned len) ****************************************************************************/ void Xil_L1DCacheFlush(void) { - register unsigned int CsidReg, C7Reg; - unsigned int CacheSize, LineSize, NumWays; - unsigned int Way, WayIndex, Set, SetIndex, NumSet; - unsigned int currmask; + register u32 CsidReg, C7Reg; + u32 CacheSize, LineSize, NumWays; + u32 Way; + u32 WayIndex, Set, SetIndex, NumSet; + u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); @@ -926,32 +930,32 @@ void Xil_L1DCacheFlush(void) #elif defined (__ICCARM__) mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg); #else - { volatile register unsigned int Reg __asm(XREG_CP15_CACHE_SIZE_ID); + { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID); CsidReg = Reg; } #endif /* Determine Cache Size */ - CacheSize = (CsidReg >> 13) & 0x1FF; - CacheSize +=1; - CacheSize *=128; /* to get number of bytes */ + CacheSize = (CsidReg >> 13U) & 0x1FFU; + CacheSize +=1U; + CacheSize *=128U; /* to get number of bytes */ /* Number of Ways */ - NumWays = (CsidReg & 0x3ff) >> 3; - NumWays += 1; + NumWays = (CsidReg & 0x3ffU) >> 3U; + NumWays += 1U; /* Get the cacheline size, way size, index size from csidr */ - LineSize = (CsidReg & 0x07) + 4; + LineSize = (CsidReg & 0x07U) + 4U; NumSet = CacheSize/NumWays; - NumSet /= (1 << LineSize); + NumSet /= (0x00000001U << LineSize); - Way = 0UL; - Set = 0UL; + Way = 0U; + Set = 0U; /* Invalidate all the cachelines */ - for (WayIndex =0; WayIndex < NumWays; WayIndex++) { - for (SetIndex =0; SetIndex < NumSet; SetIndex++) { + for (WayIndex =0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex =0U; SetIndex < NumSet; SetIndex++) { C7Reg = Way | Set; /* Flush by Set/Way */ #ifdef __GNUC__ @@ -961,14 +965,14 @@ void Xil_L1DCacheFlush(void) __asm volatile ("mcr " \ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (C7Reg)); #else - { volatile register unsigned int Reg + { volatile register u32 Reg __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW); Reg = C7Reg; } #endif - Set += (1 << LineSize); + Set += (0x00000001U << LineSize); } - Set = 0UL; - Way += 0x40000000; + Set = 0U; + Way += 0x40000000U; } /* Wait for L1 flush to complete */ @@ -991,10 +995,10 @@ void Xil_L1DCacheFlush(void) * @note The bottom 5 bits are set to 0, forced by architecture. * ****************************************************************************/ -void Xil_L1DCacheFlushLine(unsigned int adr) +void Xil_L1DCacheFlushLine(u32 adr) { - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU))); /* Wait for L1 flush to complete */ dsb(); @@ -1015,38 +1019,39 @@ void Xil_L1DCacheFlushLine(unsigned int adr) * @note None. * ****************************************************************************/ -void Xil_L1DCacheFlushRange(unsigned int adr, unsigned len) +void Xil_L1DCacheFlushRange(u32 adr, u32 len) { - const unsigned cacheline = 32; - unsigned int end; - unsigned int currmask; + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0) { + if (len != 0U) { /* Back the starting address up to the start of a cache line * perform cache operations until adr+len */ - end = adr + len; - adr = adr & ~(cacheline - 1); + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); /* Select cache L0 D-cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); - while (adr < end) { + while (LocalAddr < end) { #ifdef __GNUC__ __asm__ __volatile__("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (adr)); + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (LocalAddr)); #elif defined (__ICCARM__) __asm volatile ("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (adr)); + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (LocalAddr)); #else - { volatile register unsigned int Reg + { volatile register u32 Reg __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC); - Reg = adr; } + Reg = LocalAddr; } #endif - adr += cacheline; + LocalAddr += cacheline; } } @@ -1070,10 +1075,10 @@ void Xil_L1DCacheFlushRange(unsigned int adr, unsigned len) * @note The bottom 5 bits are set to 0, forced by architecture. * ****************************************************************************/ -void Xil_L1DCacheStoreLine(unsigned int adr) +void Xil_L1DCacheStoreLine(u32 adr) { - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F))); + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU))); /* Wait for L1 store to complete */ dsb(); @@ -1092,7 +1097,7 @@ void Xil_L1DCacheStoreLine(unsigned int adr) ****************************************************************************/ void Xil_L1ICacheEnable(void) { - register unsigned int CtrlReg; + register u32 CtrlReg; /* enable caches only if they are disabled */ #ifdef __GNUC__ @@ -1100,15 +1105,15 @@ void Xil_L1ICacheEnable(void) #elif defined (__ICCARM__) mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); #else - { volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL); + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); CtrlReg = Reg; } #endif - if (CtrlReg & XREG_CP15_CONTROL_I_BIT) { + if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) { return; } /* invalidate the instruction cache */ - mtcp(XREG_CP15_INVAL_IC_POU, 0); + mtcp(XREG_CP15_INVAL_IC_POU, 0U); /* enable the instruction cache */ CtrlReg |= (XREG_CP15_CONTROL_I_BIT); @@ -1129,12 +1134,12 @@ void Xil_L1ICacheEnable(void) ****************************************************************************/ void Xil_L1ICacheDisable(void) { - register unsigned int CtrlReg; + register u32 CtrlReg; dsb(); /* invalidate the instruction cache */ - mtcp(XREG_CP15_INVAL_IC_POU, 0); + mtcp(XREG_CP15_INVAL_IC_POU, 0U); /* disable the instruction cache */ #ifdef __GNUC__ @@ -1142,7 +1147,7 @@ void Xil_L1ICacheDisable(void) #elif defined (__ICCARM__) mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); #else - { volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL); + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); CtrlReg = Reg; } #endif CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT); @@ -1163,9 +1168,9 @@ void Xil_L1ICacheDisable(void) ****************************************************************************/ void Xil_L1ICacheInvalidate(void) { - mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); /* invalidate the instruction cache */ - mtcp(XREG_CP15_INVAL_IC_POU, 0); + mtcp(XREG_CP15_INVAL_IC_POU, 0U); /* Wait for L1 invalidate to complete */ dsb(); @@ -1184,10 +1189,10 @@ void Xil_L1ICacheInvalidate(void) * @note The bottom 5 bits are set to 0, forced by architecture. * ****************************************************************************/ -void Xil_L1ICacheInvalidateLine(unsigned int adr) +void Xil_L1ICacheInvalidateLine(u32 adr) { - mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); - mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F))); + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); + mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU))); /* Wait for L1 invalidate to complete */ dsb(); @@ -1209,38 +1214,39 @@ void Xil_L1ICacheInvalidateLine(unsigned int adr) * @note None. * ****************************************************************************/ -void Xil_L1ICacheInvalidateRange(unsigned int adr, unsigned len) +void Xil_L1ICacheInvalidateRange(u32 adr, u32 len) { - const unsigned cacheline = 32; - unsigned int end; - unsigned int currmask; + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0) { + if (len != 0U) { /* Back the starting address up to the start of a cache line * perform cache operations until adr+len */ - end = adr + len; - adr = adr & ~(cacheline - 1); + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); /* Select cache L0 I-cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); - while (adr < end) { + while (LocalAddr < end) { #ifdef __GNUC__ __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (adr)); + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (LocalAddr)); #elif defined (__ICCARM__) __asm volatile ("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (adr)); + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (LocalAddr)); #else - { volatile register unsigned int Reg + { volatile register u32 Reg __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU); - Reg = adr; } + Reg = LocalAddr; } #endif - adr += cacheline; + LocalAddr += cacheline; } } @@ -1262,12 +1268,12 @@ void Xil_L1ICacheInvalidateRange(unsigned int adr, unsigned len) ****************************************************************************/ void Xil_L2CacheEnable(void) { - register unsigned int L2CCReg; + register u32 L2CCReg; L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); /* only enable if L2CC is currently disabled */ - if ((L2CCReg & 0x01) == 0) { + if ((L2CCReg & 0x01U) == 0U) { /* set up the way size and latencies */ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET); @@ -1290,7 +1296,7 @@ void Xil_L2CacheEnable(void) L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET, - (L2CCReg | (0x01))); + (L2CCReg | (0x01U))); Xil_L2CacheSync(); /* synchronize the processor */ @@ -1312,19 +1318,19 @@ void Xil_L2CacheEnable(void) ****************************************************************************/ void Xil_L2CacheDisable(void) { - register unsigned int L2CCReg; + register u32 L2CCReg; L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); - if(L2CCReg & 0x1) { + if((L2CCReg & 0x1U) != 0U) { /* Clean and Invalidate L2 Cache */ Xil_L2CacheFlush(); /* Disable the L2CC */ - L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET, - (L2CCReg & (~0x01))); + (L2CCReg & (~0x01U))); /* Wait for the cache operations to complete */ dsb(); @@ -1348,11 +1354,16 @@ void Xil_L2CacheDisable(void) ****************************************************************************/ void Xil_L2CacheInvalidate(void) { + u32 ResultDCache; /* Invalidate the caches */ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET, - 0x0000FFFF); - while((Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)) - & 0x0000FFFF); + 0x0000FFFFU); + ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET) + & 0x0000FFFFU; + while(ResultDCache != (u32)0U) { + ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET) + & 0x0000FFFFU; + } /* Wait for the invalidate to complete */ Xil_L2CacheSync(); @@ -1376,9 +1387,9 @@ void Xil_L2CacheInvalidate(void) * @note The bottom 4 bits are set to 0, forced by architecture. * ****************************************************************************/ -void Xil_L2CacheInvalidateLine(unsigned int adr) +void Xil_L2CacheInvalidateLine(u32 adr) { - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr); /* synchronize the processor */ dsb(); } @@ -1399,35 +1410,36 @@ void Xil_L2CacheInvalidateLine(unsigned int adr) * @note None. * ****************************************************************************/ -void Xil_L2CacheInvalidateRange(unsigned int adr, unsigned len) +void Xil_L2CacheInvalidateRange(u32 adr, u32 len) { - const unsigned cacheline = 32; - unsigned int end; - volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR + + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET); - unsigned int currmask; + u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0) { + if (len != 0U) { /* Back the starting address up to the start of a cache line * perform cache operations until adr+len */ - end = adr + len; - adr = adr & ~(cacheline - 1); + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); /* Disable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x3); + Xil_L2WriteDebugCtrl(0x3U); - while (adr < end) { - *L2CCOffset = adr; - adr += cacheline; + while (LocalAddr < end) { + *L2CCOffset = LocalAddr; + LocalAddr += cacheline; } /* Enable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x0); + Xil_L2WriteDebugCtrl(0x0U); } /* synchronize the processor */ @@ -1452,21 +1464,27 @@ void Xil_L2CacheInvalidateRange(unsigned int adr, unsigned len) ****************************************************************************/ void Xil_L2CacheFlush(void) { + u16 L2CCReg; + u32 ResultL2Cache; /* Flush the caches */ /* Disable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x3); + Xil_L2WriteDebugCtrl(0x3U); Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET, - 0x0000FFFF); + 0x0000FFFFU); + ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET) + & 0x0000FFFFU; - while((Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)) - & 0x0000FFFF); + while(ResultL2Cache != (u32)0U) { + ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET) + & 0x0000FFFFU; + } Xil_L2CacheSync(); /* Enable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x0); + Xil_L2WriteDebugCtrl(0x0U); /* synchronize the processor */ dsb(); @@ -1487,7 +1505,7 @@ void Xil_L2CacheFlush(void) * @note The bottom 4 bits are set to 0, forced by architecture. * ****************************************************************************/ -void Xil_L2CacheFlushLine(unsigned int adr) +void Xil_L2CacheFlushLine(u32 adr) { #ifdef CONFIG_PL310_ERRATA_588369 Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr); @@ -1514,35 +1532,36 @@ void Xil_L2CacheFlushLine(unsigned int adr) * @note None. * ****************************************************************************/ -void Xil_L2CacheFlushRange(unsigned int adr, unsigned len) +void Xil_L2CacheFlushRange(u32 adr, u32 len) { - const unsigned cacheline = 32; - unsigned int end; - volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR + + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET); - unsigned int currmask; + u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0) { + if (len != 0U) { /* Back the starting address up to the start of a cache line * perform cache operations until adr+len */ - end = adr + len; - adr = adr & ~(cacheline - 1); + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); /* Disable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x3); + Xil_L2WriteDebugCtrl(0x3U); - while (adr < end) { - *L2CCOffset = adr; + while (LocalAddr < end) { + *L2CCOffset = LocalAddr; Xil_L2CacheSync(); - adr += cacheline; + LocalAddr += cacheline; } /* Enable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x0); + Xil_L2WriteDebugCtrl(0x0U); } /* synchronize the processor */ dsb(); @@ -1564,7 +1583,7 @@ void Xil_L2CacheFlushRange(unsigned int adr, unsigned len) * @note The bottom 4 bits are set to 0, forced by architecture. * ****************************************************************************/ -void Xil_L2CacheStoreLine(unsigned int adr) +void Xil_L2CacheStoreLine(u32 adr) { Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr); /* synchronize the processor */ diff --git a/lib/bsp/standalone/src/cortexa9/xil_cache.h b/lib/bsp/standalone/src/cortexa9/xil_cache.h old mode 100755 new mode 100644 index 1944eb97..afb7e093 --- a/lib/bsp/standalone/src/cortexa9/xil_cache.h +++ b/lib/bsp/standalone/src/cortexa9/xil_cache.h @@ -59,14 +59,14 @@ extern "C" { void Xil_DCacheEnable(void); void Xil_DCacheDisable(void); void Xil_DCacheInvalidate(void); -void Xil_DCacheInvalidateRange(unsigned int adr, unsigned len); +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len); void Xil_DCacheFlush(void); -void Xil_DCacheFlushRange(unsigned int adr, unsigned len); +void Xil_DCacheFlushRange(INTPTR adr, u32 len); void Xil_ICacheEnable(void); void Xil_ICacheDisable(void); void Xil_ICacheInvalidate(void); -void Xil_ICacheInvalidateRange(unsigned int adr, unsigned len); +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len); #ifdef __cplusplus } diff --git a/lib/bsp/standalone/src/cortexa9/xil_cache_l.h b/lib/bsp/standalone/src/cortexa9/xil_cache_l.h old mode 100755 new mode 100644 index 2f787e00..0b00a62b --- a/lib/bsp/standalone/src/cortexa9/xil_cache_l.h +++ b/lib/bsp/standalone/src/cortexa9/xil_cache_l.h @@ -50,42 +50,43 @@ #ifndef XIL_CACHE_MACH_H #define XIL_CACHE_MACH_H +#include "xil_types.h" #ifdef __cplusplus extern "C" { #endif /************************** Function Prototypes ******************************/ -void Xil_DCacheInvalidateLine(unsigned int adr); -void Xil_DCacheFlushLine(unsigned int adr); -void Xil_DCacheStoreLine(unsigned int adr); -void Xil_ICacheInvalidateLine(unsigned int adr); +void Xil_DCacheInvalidateLine(u32 adr); +void Xil_DCacheFlushLine(u32 adr); +void Xil_DCacheStoreLine(u32 adr); +void Xil_ICacheInvalidateLine(u32 adr); void Xil_L1DCacheEnable(void); void Xil_L1DCacheDisable(void); void Xil_L1DCacheInvalidate(void); -void Xil_L1DCacheInvalidateLine(unsigned int adr); -void Xil_L1DCacheInvalidateRange(unsigned int adr, unsigned len); +void Xil_L1DCacheInvalidateLine(u32 adr); +void Xil_L1DCacheInvalidateRange(u32 adr, u32 len); void Xil_L1DCacheFlush(void); -void Xil_L1DCacheFlushLine(unsigned int adr); -void Xil_L1DCacheFlushRange(unsigned int adr, unsigned len); -void Xil_L1DCacheStoreLine(unsigned int adr); +void Xil_L1DCacheFlushLine(u32 adr); +void Xil_L1DCacheFlushRange(u32 adr, u32 len); +void Xil_L1DCacheStoreLine(u32 adr); void Xil_L1ICacheEnable(void); void Xil_L1ICacheDisable(void); void Xil_L1ICacheInvalidate(void); -void Xil_L1ICacheInvalidateLine(unsigned int adr); -void Xil_L1ICacheInvalidateRange(unsigned int adr, unsigned len); +void Xil_L1ICacheInvalidateLine(u32 adr); +void Xil_L1ICacheInvalidateRange(u32 adr, u32 len); void Xil_L2CacheEnable(void); void Xil_L2CacheDisable(void); void Xil_L2CacheInvalidate(void); -void Xil_L2CacheInvalidateLine(unsigned int adr); -void Xil_L2CacheInvalidateRange(unsigned int adr, unsigned len); +void Xil_L2CacheInvalidateLine(u32 adr); +void Xil_L2CacheInvalidateRange(u32 adr, u32 len); void Xil_L2CacheFlush(void); -void Xil_L2CacheFlushLine(unsigned int adr); -void Xil_L2CacheFlushRange(unsigned int adr, unsigned len); -void Xil_L2CacheStoreLine(unsigned int adr); +void Xil_L2CacheFlushLine(u32 adr); +void Xil_L2CacheFlushRange(u32 adr, u32 len); +void Xil_L2CacheStoreLine(u32 adr); #ifdef __cplusplus } diff --git a/lib/bsp/standalone/src/cortexa9/xil_errata.h b/lib/bsp/standalone/src/cortexa9/xil_errata.h old mode 100755 new mode 100644 diff --git a/lib/bsp/standalone/src/cortexa9/xil_exception.c b/lib/bsp/standalone/src/cortexa9/xil_exception.c old mode 100755 new mode 100644 index 7fa86715..5e813553 --- a/lib/bsp/standalone/src/cortexa9/xil_exception.c +++ b/lib/bsp/standalone/src/cortexa9/xil_exception.c @@ -108,7 +108,7 @@ XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = *****************************************************************************/ static void Xil_ExceptionNullHandler(void *Data) { - (void)Data; + (void *)Data; DieLoop: goto DieLoop; } @@ -154,12 +154,12 @@ void Xil_ExceptionInit(void) * @note None. * ****************************************************************************/ -void Xil_ExceptionRegisterHandler(u32 exception_id, +void Xil_ExceptionRegisterHandler(u32 Exception_id, Xil_ExceptionHandler Handler, void *Data) { - XExc_VectorTable[exception_id].Handler = Handler; - XExc_VectorTable[exception_id].Data = Data; + XExc_VectorTable[Exception_id].Handler = Handler; + XExc_VectorTable[Exception_id].Data = Data; } /*****************************************************************************/ @@ -177,9 +177,9 @@ void Xil_ExceptionRegisterHandler(u32 exception_id, * @note None. * ****************************************************************************/ -void Xil_ExceptionRemoveHandler(u32 exception_id) +void Xil_ExceptionRemoveHandler(u32 Exception_id) { - Xil_ExceptionRegisterHandler(exception_id, + Xil_ExceptionRegisterHandler(Exception_id, Xil_ExceptionNullHandler, NULL); } @@ -206,11 +206,13 @@ void Xil_DataAbortHandler(void *CallBackRef){ #elif defined (__ICCARM__) mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus); #else - { volatile register unsigned int Reg __asm(XREG_CP15_DATA_FAULT_STATUS); + { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS); FaultStatus = Reg; } #endif xdbg_printf(XDBG_DEBUG_ERROR, "Data abort with Data Fault Status Register %x\n",FaultStatus); - while(1); + while(1) { + ; + } } /*****************************************************************************/ @@ -233,9 +235,11 @@ void Xil_PrefetchAbortHandler(void *CallBackRef){ #elif defined (__ICCARM__) mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus); #else - { volatile register unsigned int Reg __asm(XREG_CP15_INST_FAULT_STATUS); + { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS); FaultStatus = Reg; } #endif xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort with Instruction Fault Status Register %x\n",FaultStatus); - while(1); + while(1) { + ; + } } diff --git a/lib/bsp/standalone/src/cortexa9/xil_exception.h b/lib/bsp/standalone/src/cortexa9/xil_exception.h old mode 100755 new mode 100644 index bb70e93e..5c5487fa --- a/lib/bsp/standalone/src/cortexa9/xil_exception.h +++ b/lib/bsp/standalone/src/cortexa9/xil_exception.h @@ -66,15 +66,15 @@ extern "C" { #define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE #define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) -#define XIL_EXCEPTION_ID_FIRST 0 -#define XIL_EXCEPTION_ID_RESET 0 -#define XIL_EXCEPTION_ID_UNDEFINED_INT 1 -#define XIL_EXCEPTION_ID_SWI_INT 2 -#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3 -#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4 -#define XIL_EXCEPTION_ID_IRQ_INT 5 -#define XIL_EXCEPTION_ID_FIQ_INT 6 -#define XIL_EXCEPTION_ID_LAST 6 +#define XIL_EXCEPTION_ID_FIRST 0U +#define XIL_EXCEPTION_ID_RESET 0U +#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U +#define XIL_EXCEPTION_ID_SWI_INT 2U +#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U +#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U +#define XIL_EXCEPTION_ID_IRQ_INT 5U +#define XIL_EXCEPTION_ID_FIQ_INT 6U +#define XIL_EXCEPTION_ID_LAST 6U /* * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. @@ -100,19 +100,21 @@ typedef void (*Xil_InterruptHandler)(void *data); * @return None. * * @note If bit is 0, exception is enabled. -* C-Style signature: void Xil_ExceptionEnableMask(Mask); +* C-Style signature: void Xil_ExceptionEnableMask(Mask) * ******************************************************************************/ #ifdef __GNUC__ #define Xil_ExceptionEnableMask(Mask) \ - mtcpsr(mfcpsr() & ~ (Mask & XIL_EXCEPTION_ALL)) + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) #elif defined (__ICCARM__) #define Xil_ExceptionEnableMask(Mask) \ - mtcpsr(mfcpsr() & ~ (Mask & XIL_EXCEPTION_ALL)) + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) #else #define Xil_ExceptionEnableMask(Mask) \ - { register unsigned int Reg __asm("cpsr"); \ - mtcpsr(Reg & ~ (Mask & XIL_EXCEPTION_ALL)) } + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \ + } #endif /****************************************************************************/ @@ -136,19 +138,21 @@ typedef void (*Xil_InterruptHandler)(void *data); * @return None. * * @note If bit is 1, exception is disabled. -* C-Style signature: Xil_ExceptionDisableMask(Mask); +* C-Style signature: Xil_ExceptionDisableMask(Mask) * ******************************************************************************/ #ifdef __GNUC__ #define Xil_ExceptionDisableMask(Mask) \ - mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL)) + mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL)) #elif defined (__ICCARM__) #define Xil_ExceptionDisableMask(Mask) \ mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL)) #else #define Xil_ExceptionDisableMask(Mask) \ - { register unsigned int Reg __asm("cpsr"); \ - mtcpsr(Reg | (Mask & XIL_EXCEPTION_ALL)) } + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \ + } #endif /****************************************************************************/ @@ -213,11 +217,11 @@ typedef void (*Xil_InterruptHandler)(void *data); /************************** Function Prototypes *****************************/ -extern void Xil_ExceptionRegisterHandler(u32 id, - Xil_ExceptionHandler handler, - void *data); +extern void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data); -extern void Xil_ExceptionRemoveHandler(u32 id); +extern void Xil_ExceptionRemoveHandler(u32 Exception_id); extern void Xil_ExceptionInit(void); extern void Xil_DataAbortHandler(void *CallBackRef); diff --git a/lib/bsp/standalone/src/cortexa9/xil_io.c b/lib/bsp/standalone/src/cortexa9/xil_io.c old mode 100755 new mode 100644 index ead20bb1..d5e8257e --- a/lib/bsp/standalone/src/cortexa9/xil_io.c +++ b/lib/bsp/standalone/src/cortexa9/xil_io.c @@ -84,7 +84,7 @@ * @note None. * ******************************************************************************/ -u8 Xil_In8(u32 Addr) +u8 Xil_In8(INTPTR Addr) { return *(volatile u8 *) Addr; } @@ -103,7 +103,7 @@ u8 Xil_In8(u32 Addr) * @note None. * ******************************************************************************/ -u16 Xil_In16(u32 Addr) +u16 Xil_In16(INTPTR Addr) { return *(volatile u16 *) Addr; } @@ -122,7 +122,7 @@ u16 Xil_In16(u32 Addr) * @note None. * ******************************************************************************/ -u32 Xil_In32(u32 Addr) +u32 Xil_In32(INTPTR Addr) { return *(volatile u32 *) Addr; } @@ -133,7 +133,7 @@ u32 Xil_In32(u32 Addr) * Performs an output operation for an 8-bit memory location by writing the * specified Value to the the specified address. * -* @param OutAddress contains the address to perform the output operation +* @param Addr contains the address to perform the output operation * at. * @param Value contains the Value to be output at the specified address. * @@ -142,9 +142,10 @@ u32 Xil_In32(u32 Addr) * @note None. * ******************************************************************************/ -void Xil_Out8(u32 OutAddress, u8 Value) +void Xil_Out8(INTPTR Addr, u8 Value) { - *(volatile u8 *) OutAddress = Value; + u8 *LocalAddr = (u8 *)Addr; + *LocalAddr = Value; } /*****************************************************************************/ @@ -153,7 +154,7 @@ void Xil_Out8(u32 OutAddress, u8 Value) * Performs an output operation for a 16-bit memory location by writing the * specified Value to the the specified address. * -* @param OutAddress contains the address to perform the output operation +* @param Addr contains the address to perform the output operation * at. * @param Value contains the Value to be output at the specified address. * @@ -162,9 +163,10 @@ void Xil_Out8(u32 OutAddress, u8 Value) * @note None. * ******************************************************************************/ -void Xil_Out16(u32 OutAddress, u16 Value) +void Xil_Out16(INTPTR Addr, u16 Value) { - *(volatile u16 *) OutAddress = Value; + u16 *LocalAddr = (u16 *)Addr; + *LocalAddr = Value; } /*****************************************************************************/ @@ -173,7 +175,7 @@ void Xil_Out16(u32 OutAddress, u16 Value) * Performs an output operation for a 32-bit memory location by writing the * specified Value to the the specified address. * -* @param OutAddress contains the address to perform the output operation +* @param Addr contains the address to perform the output operation * at. * @param Value contains the Value to be output at the specified address. * @@ -182,9 +184,10 @@ void Xil_Out16(u32 OutAddress, u16 Value) * @note None. * ******************************************************************************/ -void Xil_Out32(u32 OutAddress, u32 Value) +void Xil_Out32(INTPTR Addr, u32 Value) { - *(volatile u32 *) OutAddress = Value; + u32 *LocalAddr = (u32 *)Addr; + *LocalAddr = Value; } /*****************************************************************************/ @@ -202,7 +205,7 @@ void Xil_Out32(u32 OutAddress, u32 Value) * @note None. * ******************************************************************************/ -u16 Xil_In16BE(u32 Addr) +u16 Xil_In16BE(INTPTR Addr) { u16 temp; u16 result; @@ -229,7 +232,7 @@ u16 Xil_In16BE(u32 Addr) * @note None. * ******************************************************************************/ -u32 Xil_In32BE(u32 Addr) +u32 Xil_In32BE(INTPTR Addr) { u32 temp; u32 result; @@ -248,7 +251,7 @@ u32 Xil_In32BE(u32 Addr) * specified Value to the the specified address. The Value is byte-swapped * before being written. * -* @param OutAddress contains the address to perform the output operation +* @param Addr contains the address to perform the output operation * at. * @param Value contains the Value to be output at the specified address. * @@ -257,13 +260,13 @@ u32 Xil_In32BE(u32 Addr) * @note None. * ******************************************************************************/ -void Xil_Out16BE(u32 OutAddress, u16 Value) +void Xil_Out16BE(INTPTR Addr, u16 Value) { u16 temp; temp = Xil_EndianSwap16(Value); - Xil_Out16(OutAddress, temp); + Xil_Out16(Addr, temp); } /*****************************************************************************/ @@ -273,7 +276,7 @@ void Xil_Out16BE(u32 OutAddress, u16 Value) * specified Value to the the specified address. The Value is byte-swapped * before being written. * -* @param OutAddress contains the address to perform the output operation +* @param Addr contains the address to perform the output operation * at. * @param Value contains the Value to be output at the specified address. * @@ -282,13 +285,13 @@ void Xil_Out16BE(u32 OutAddress, u16 Value) * @note None. * ******************************************************************************/ -void Xil_Out32BE(u32 OutAddress, u32 Value) +void Xil_Out32BE(INTPTR Addr, u32 Value) { u32 temp; temp = Xil_EndianSwap32(Value); - Xil_Out32(OutAddress, temp); + Xil_Out32(Addr, temp); } /*****************************************************************************/ @@ -305,7 +308,7 @@ void Xil_Out32BE(u32 OutAddress, u32 Value) ******************************************************************************/ u16 Xil_EndianSwap16(u16 Data) { - return (u16) (((Data & 0xFF00) >> 8) | ((Data & 0x00FF) << 8)); + return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U)); } /*****************************************************************************/ @@ -327,15 +330,15 @@ u32 Xil_EndianSwap32(u32 Data) /* get each of the half words from the 32 bit word */ - LoWord = (u16) (Data & 0x0000FFFF); - HiWord = (u16) ((Data & 0xFFFF0000) >> 16); + LoWord = (u16) (Data & 0x0000FFFFU); + HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U); /* byte swap each of the 16 bit half words */ - LoWord = (((LoWord & 0xFF00) >> 8) | ((LoWord & 0x00FF) << 8)); - HiWord = (((HiWord & 0xFF00) >> 8) | ((HiWord & 0x00FF) << 8)); + LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U)); + HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U)); /* swap the half words before returning the value */ - return (u32) ((LoWord << 16) | HiWord); + return ((((u32)LoWord) << (u32)16U) | (u32)HiWord); } diff --git a/lib/bsp/standalone/src/cortexa9/xil_io.h b/lib/bsp/standalone/src/cortexa9/xil_io.h old mode 100755 new mode 100644 index 21f203b3..51588c94 --- a/lib/bsp/standalone/src/cortexa9/xil_io.h +++ b/lib/bsp/standalone/src/cortexa9/xil_io.h @@ -98,7 +98,7 @@ extern "C" { * @note None. * ******************************************************************************/ -#define Xil_In16LE(Addr) Xil_In16(Addr) +#define Xil_In16LE(Addr) Xil_In16((Addr)) /*****************************************************************************/ /** @@ -119,7 +119,7 @@ extern "C" { * @note None. * ******************************************************************************/ -#define Xil_In32LE(Addr) Xil_In32(Addr) +#define Xil_In32LE(Addr) Xil_In32((Addr)) /*****************************************************************************/ /** @@ -139,7 +139,7 @@ extern "C" { * @note None. * ******************************************************************************/ -#define Xil_Out16LE(Addr, Value) Xil_Out16(Addr, Value) +#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value)) /*****************************************************************************/ /** @@ -158,7 +158,7 @@ extern "C" { * @note None. * ******************************************************************************/ -#define Xil_Out32LE(Addr, Value) Xil_Out32(Addr, Value) +#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value)) /*****************************************************************************/ /** @@ -172,7 +172,7 @@ extern "C" { * @note None. * ******************************************************************************/ -#define Xil_Htonl(Data) Xil_EndianSwap32(Data) +#define Xil_Htonl(Data) Xil_EndianSwap32((Data)) /*****************************************************************************/ /** @@ -186,7 +186,7 @@ extern "C" { * @note None. * ******************************************************************************/ -#define Xil_Htons(Data) Xil_EndianSwap16(Data) +#define Xil_Htons(Data) Xil_EndianSwap16((Data)) /*****************************************************************************/ /** @@ -200,7 +200,7 @@ extern "C" { * @note None. * ******************************************************************************/ -#define Xil_Ntohl(Data) Xil_EndianSwap32(Data) +#define Xil_Ntohl(Data) Xil_EndianSwap32((Data)) /*****************************************************************************/ /** @@ -214,7 +214,7 @@ extern "C" { * @note None. * ******************************************************************************/ -#define Xil_Ntohs(Data) Xil_EndianSwap16(Data) +#define Xil_Ntohs(Data) Xil_EndianSwap16((Data)) /************************** Function Prototypes ******************************/ @@ -222,18 +222,19 @@ extern "C" { * processors which may use memory mapped I/O or I/O which is mapped into a * seperate address space. */ -u8 Xil_In8(u32 Addr); -u16 Xil_In16(u32 Addr); -u32 Xil_In32(u32 Addr); +u8 Xil_In8(INTPTR Addr); +u16 Xil_In16(INTPTR Addr); +u32 Xil_In32(INTPTR Addr); -void Xil_Out8(u32 Addr, u8 Value); -void Xil_Out16(u32 Addr, u16 Value); -void Xil_Out32(u32 Addr, u32 Value); +void Xil_Out8(INTPTR Addr, u8 Value); +void Xil_Out16(INTPTR Addr, u16 Value); +void Xil_Out32(INTPTR Addr, u32 Value); -u16 Xil_In16BE(u32 Addr); -u32 Xil_In32BE(u32 Addr); -void Xil_Out16BE(u32 Addr, u16 Value); -void Xil_Out32BE(u32 Addr, u32 Value); + +u16 Xil_In16BE(INTPTR Addr); +u32 Xil_In32BE(INTPTR Addr); +void Xil_Out16BE(INTPTR Addr, u16 Value); +void Xil_Out32BE(INTPTR Addr, u32 Value); u16 Xil_EndianSwap16(u16 Data); u32 Xil_EndianSwap32(u32 Data); diff --git a/lib/bsp/standalone/src/cortexa9/xil_misc_psreset_api.c b/lib/bsp/standalone/src/cortexa9/xil_misc_psreset_api.c old mode 100755 new mode 100644 index 1546da39..151d850c --- a/lib/bsp/standalone/src/cortexa9/xil_misc_psreset_api.c +++ b/lib/bsp/standalone/src/cortexa9/xil_misc_psreset_api.c @@ -76,17 +76,17 @@ * @note None. * ******************************************************************************/ -void XDdr_ResetHw() +void XDdr_ResetHw(void) { u32 RegVal; - /* Unlock the slcr register access lock */ + /* Unlock the slcr register access lock */ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert and deassert the ddr softreset bit */ RegVal = Xil_In32(XDDRC_CTRL_BASEADDR); - RegVal &= ~XDDRPS_CTRL_RESET_MASK; + RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK); Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); - RegVal |= XDDRPS_CTRL_RESET_MASK; + RegVal |= ((u32)XDDRPS_CTRL_RESET_MASK); Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); } @@ -102,7 +102,7 @@ void XDdr_ResetHw() * @note None. * ******************************************************************************/ -void XOcm_Remap() +void XOcm_Remap(void) { u32 RegVal; @@ -110,7 +110,7 @@ void XOcm_Remap() Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Map the ocm region to postbootrom state */ RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR); - RegVal = (RegVal & ~XSLCR_OCM_CFG_HIADDR_MASK) | XSLCR_OCM_CFG_RESETVAL; + RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL; Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal); } @@ -131,11 +131,11 @@ void XSmc_ResetHw(u32 BaseAddress) /* Clear the interuupts */ RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET); - RegVal = RegVal | XSMC_MEMC_CLR_CONFIG_MASK; + RegVal = RegVal | (u32)XSMC_MEMC_CLR_CONFIG_MASK; Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal); /* Clear the idle counter registers */ - Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0); - Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0); + Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U); + Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U); /* Update the ecc registers with reset values */ Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET, XSMC_ECC_MEMCFG1_RESET_VAL); @@ -157,26 +157,26 @@ void XSmc_ResetHw(u32 BaseAddress) * @note None. * ******************************************************************************/ -void XSlcr_MioWriteResetValues() +void XSlcr_MioWriteResetValues(void) { u32 i; /* Unlock the slcr register access lock */ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Update all the MIO registers with reset values */ - for (i=0; i<=1;i++); + for (i=0U; i<=1U;i++) { - Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)), + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), XSLCR_MIO_PIN_00_RESET_VAL); } - for (; i<=8;i++); + for (; i<=8U;i++) { - Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)), + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), XSLCR_MIO_PIN_02_RESET_VAL); } - for (; i<=53 ;i++); + for (; i<=53U ;i++) { - Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)), + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), XSLCR_MIO_PIN_00_RESET_VAL); } @@ -194,7 +194,7 @@ void XSlcr_MioWriteResetValues() * @note None. * ******************************************************************************/ -void XSlcr_PllWriteResetValues() +void XSlcr_PllWriteResetValues(void) { /* Unlock the slcr register access lock */ @@ -224,14 +224,14 @@ void XSlcr_PllWriteResetValues() * @note None. * ******************************************************************************/ -void XSlcr_DisableLevelShifters() +void XSlcr_DisableLevelShifters(void) { u32 RegVal; /* Unlock the slcr register access lock */ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Disable the level shifters */ RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR); - RegVal = RegVal & ~XSLCR_LVL_SHFTR_EN_MASK; + RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK); Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal); } @@ -254,11 +254,11 @@ void XSlcr_OcmReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_OCM_RST_CTRL_VAL; + RegVal = RegVal | ((u32)XSLCR_OCM_RST_CTRL_VAL); Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_OCM_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL); Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); } @@ -280,11 +280,11 @@ void XSlcr_EmacPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_GEM_RST_CTRL_VAL; + RegVal = RegVal | ((u32)XSLCR_GEM_RST_CTRL_VAL); Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_GEM_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_GEM_RST_CTRL_VAL); Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); } @@ -307,11 +307,11 @@ void XSlcr_UsbPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_USB_RST_CTRL_VAL; + RegVal = RegVal | ((u32)XSLCR_USB_RST_CTRL_VAL); Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_USB_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL); Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -333,11 +333,11 @@ void XSlcr_QspiPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_QSPI_RST_CTRL_VAL; + RegVal = RegVal | ((u32)XSLCR_QSPI_RST_CTRL_VAL); Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_QSPI_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL); Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -359,11 +359,11 @@ void XSlcr_SpiPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_SPI_RST_CTRL_VAL; + RegVal = RegVal | ((u32)XSLCR_SPI_RST_CTRL_VAL); Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_SPI_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL); Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -384,11 +384,11 @@ void XSlcr_I2cPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_I2C_RST_CTRL_VAL; + RegVal = RegVal | ((u32)XSLCR_I2C_RST_CTRL_VAL); Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_I2C_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL); Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -410,11 +410,11 @@ void XSlcr_UartPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_UART_RST_CTRL_VAL; + RegVal = RegVal | ((u32)XSLCR_UART_RST_CTRL_VAL); Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_UART_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL); Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -436,11 +436,11 @@ void XSlcr_CanPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_CAN_RST_CTRL_VAL; + RegVal = RegVal | ((u32)XSLCR_CAN_RST_CTRL_VAL); Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_CAN_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL); Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -461,11 +461,11 @@ void XSlcr_SmcPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_SMC_RST_CTRL_VAL; + RegVal = RegVal | ((u32)XSLCR_SMC_RST_CTRL_VAL); Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_SMC_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL); Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -487,11 +487,11 @@ void XSlcr_DmaPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_DMAC_RST_CTRL_VAL; + RegVal = RegVal | ((u32)XSLCR_DMAC_RST_CTRL_VAL); Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_DMAC_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL); Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -513,10 +513,10 @@ void XSlcr_GpioPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_GPIO_RST_CTRL_VAL; + RegVal = RegVal | ((u32)XSLCR_GPIO_RST_CTRL_VAL); Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_GPIO_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL); Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); -} \ No newline at end of file +} diff --git a/lib/bsp/standalone/src/cortexa9/xil_misc_psreset_api.h b/lib/bsp/standalone/src/cortexa9/xil_misc_psreset_api.h old mode 100755 new mode 100644 index 223fb587..46fcc972 --- a/lib/bsp/standalone/src/cortexa9/xil_misc_psreset_api.h +++ b/lib/bsp/standalone/src/cortexa9/xil_misc_psreset_api.h @@ -58,137 +58,137 @@ extern "C" { #include "xil_io.h" /************************** Constant Definitions *****************************/ -#define XDDRC_CTRL_BASEADDR 0xF8006000 -#define XSLCR_BASEADDR 0xF8000000 +#define XDDRC_CTRL_BASEADDR 0xF8006000U +#define XSLCR_BASEADDR 0xF8000000U /**< OCM configuration register */ -#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x910) +#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U) /**< SLCR unlock register */ -#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x8) +#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U) /**< SLCR GEM0 rx clock control register */ -#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x138) +#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U) /**< SLCR GEM1 rx clock control register */ -#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x13C) +#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU) /**< SLCR GEM0 clock control register */ -#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x140) +#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U) /**< SLCR GEM1 clock control register */ -#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x144) +#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U) /**< SLCR SMC clock control register */ -#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x148) +#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U) /**< SLCR GEM reset control register */ -#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214) +#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U) /**< SLCR USB0 clock control register */ -#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x130) +#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U) /**< SLCR USB1 clock control register */ -#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x134) +#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U) /**< SLCR USB1 reset control register */ -#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210) +#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U) /**< SLCR SMC reset control register */ -#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234) +#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U) /**< SLCR Level shifter enable register */ -#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x900) +#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U) /**< SLCR ARM pll control register */ -#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x100) +#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U) /**< SLCR DDR pll control register */ -#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x104) +#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U) /**< SLCR IO pll control register */ -#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x108) +#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U) /**< SLCR ARM pll configuration register */ -#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x110) +#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U) /**< SLCR DDR pll configuration register */ -#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x114) +#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U) /**< SLCR IO pll configuration register */ -#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x118) +#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U) /**< SLCR ARM clock control register */ -#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x120) +#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U) /**< SLCR DDR clock control register */ -#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x124) +#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U) /**< SLCR MIO pin address register */ -#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x700) +#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U) /**< SLCR DMAC reset control address register */ -#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x20C) +#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU) /**< SLCR USB reset control address register */ -#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210) +/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/ /**< SLCR GEM reset control address register */ -#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214) +/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/ /**< SLCR SDIO reset control address register */ -#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x218) +#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U) /**< SLCR SPI reset control address register */ -#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x21C) +#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU) /**< SLCR CAN reset control address register */ -#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x220) +#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U) /**< SLCR I2C reset control address register */ -#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x224) +#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U) /**< SLCR UART reset control address register */ -#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x228) +#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U) /**< SLCR GPIO reset control address register */ -#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x22C) +#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU) /**< SLCR LQSPI reset control address register */ -#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x230) +#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U) /**< SLCR SMC reset control address register */ -#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234) +/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/ /**< SLCR OCM reset control address register */ -#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x238) +#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U) /**< SMC mem controller clear config register */ -#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0C +#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU /**< SMC idlecount configuration register */ -#define XSMC_REFRESH_PERIOD_0_OFFSET 0x20 -#define XSMC_REFRESH_PERIOD_1_OFFSET 0x24 +#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U +#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U /**< SMC ECC configuration register */ -#define XSMC_ECC_MEMCFG1_OFFSET 0x404 +#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U /**< SMC ECC command 1 register */ -#define XSMC_ECC_MEMCMD1_OFFSET 0x404 +#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U /**< SMC ECC command 2 register */ -#define XSMC_ECC_MEMCMD2_OFFSET 0x404 +#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U /**< SLCR unlock code */ -#define XSLCR_UNLOCK_CODE 0x0000DF0D +#define XSLCR_UNLOCK_CODE 0x0000DF0DU /**< SMC mem clear configuration mask */ -#define XSMC_MEMC_CLR_CONFIG_MASK 0x5F +#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU /**< SMC ECC memconfig 1 reset value */ -#define XSMC_ECC_MEMCFG1_RESET_VAL 0x43 +#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U /**< SMC ECC memcommand 1 reset value */ -#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080 +#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U /**< SMC ECC memcommand 2 reset value */ -#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585 +#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U /**< DDR controller reset bit mask */ -#define XDDRPS_CTRL_RESET_MASK 0x1 +#define XDDRPS_CTRL_RESET_MASK 0x00000001U /**< SLCR OCM configuration reset value*/ -#define XSLCR_OCM_CFG_RESETVAL 0x8 +#define XSLCR_OCM_CFG_RESETVAL 0x00000008U /**< SLCR OCM bank selection mask*/ -#define XSLCR_OCM_CFG_HIADDR_MASK 0xF +#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU /**< SLCR level shifter enable mask*/ -#define XSLCR_LVL_SHFTR_EN_MASK 0xF +#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU /**< SLCR PLL register reset values */ -#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008 -#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008 -#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008 -#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0 -#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0 -#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0 -#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400 -#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003 +#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U +#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U /**< SLCR MIO register default values */ -#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601 -#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601 +#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U +#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U /**< SLCR Reset control registers default values */ -#define XSLCR_DMAC_RST_CTRL_VAL 0x1 -#define XSLCR_GEM_RST_CTRL_VAL 0xF3 -#define XSLCR_USB_RST_CTRL_VAL 0x3 -#define XSLCR_I2C_RST_CTRL_VAL 0x3 -#define XSLCR_SPI_RST_CTRL_VAL 0xF -#define XSLCR_UART_RST_CTRL_VAL 0xF -#define XSLCR_QSPI_RST_CTRL_VAL 0x3 -#define XSLCR_GPIO_RST_CTRL_VAL 0x1 -#define XSLCR_SMC_RST_CTRL_VAL 0x3 -#define XSLCR_OCM_RST_CTRL_VAL 0x1 -#define XSLCR_SDIO_RST_CTRL_VAL 0x33 -#define XSLCR_CAN_RST_CTRL_VAL 0x3 +#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U +#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U +#define XSLCR_USB_RST_CTRL_VAL 0x00000003U +#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U +#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU +#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU +#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U +#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U +#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U +#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U +#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U +#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U /**************************** Type Definitions *******************************/ /* the following data type is used to hold a null terminated version string @@ -203,11 +203,11 @@ extern "C" { /* * Performs reset operation to the ddr interface */ -void XDdr_ResetHw(); +void XDdr_ResetHw(void); /* * Map the ocm region to post bootrom state */ -void XOcm_Remap(); +void XOcm_Remap(void); /* * Performs the smc interface reset */ @@ -215,15 +215,15 @@ void XSmc_ResetHw(u32 BaseAddress); /* * updates the MIO registers with reset values */ -void XSlcr_MioWriteResetValues(); +void XSlcr_MioWriteResetValues(void); /* * updates the PLL and clock registers with reset values */ -void XSlcr_PllWriteResetValues(); +void XSlcr_PllWriteResetValues(void); /* * Disables the level shifters */ -void XSlcr_DisableLevelShifters(); +void XSlcr_DisableLevelShifters(void); /* * provides softreset to the GPIO interface */ diff --git a/lib/bsp/standalone/src/cortexa9/xil_mmu.c b/lib/bsp/standalone/src/cortexa9/xil_mmu.c old mode 100755 new mode 100644 index 885db99d..7785e4e2 --- a/lib/bsp/standalone/src/cortexa9/xil_mmu.c +++ b/lib/bsp/standalone/src/cortexa9/xil_mmu.c @@ -88,7 +88,7 @@ extern u32 MMUTable; * Set the memory attributes for a section, in the translation table. Each * section covers 1MB of memory. * -* @param addr is the address for which attributes are to be set. +* @param Addr is the address for which attributes are to be set. * @param attrib specifies the attributes for that memory region. * * @return None. @@ -97,20 +97,23 @@ extern u32 MMUTable; * translation table attribute. * ******************************************************************************/ -void Xil_SetTlbAttributes(u32 addr, u32 attrib) +void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib) { u32 *ptr; u32 section; - section = addr / 0x100000; - ptr = &MMUTable + section; - *ptr = (addr & 0xFFF00000) | attrib; + section = Addr / 0x100000U; + ptr = &MMUTable; + ptr += section; + if(ptr != NULL) { + *ptr = (Addr & 0xFFF00000U) | attrib; + } Xil_DCacheFlush(); - mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0); + mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U); /* Invalidate all branch predictors */ - mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0); + mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U); dsb(); /* ensure completion of the BP and TLB invalidation */ isb(); /* synchronize context on this processor */ @@ -135,10 +138,10 @@ void Xil_EnableMMU(void) #elif defined (__ICCARM__) mfcp(XREG_CP15_SYS_CONTROL, Reg); #else - { volatile register unsigned int Cp15Reg __asm(XREG_CP15_SYS_CONTROL); + { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL); Reg = Cp15Reg; } #endif - Reg |= 0x05; + Reg |= (u32)0x05U; mtcp(XREG_CP15_SYS_CONTROL, Reg); dsb(); @@ -160,8 +163,8 @@ void Xil_DisableMMU(void) { u32 Reg; - mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0); - mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0); + mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U); + mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U); Xil_DCacheFlush(); #ifdef __GNUC__ @@ -169,13 +172,13 @@ void Xil_DisableMMU(void) #elif defined (__ICCARM__) mfcp(XREG_CP15_SYS_CONTROL, Reg); #else - { volatile register unsigned int Cp15Reg __asm(XREG_CP15_SYS_CONTROL); + { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL); Reg = Cp15Reg; } #endif - Reg &= ~0x05; + Reg &= (u32)(~0x05U); #ifdef CONFIG_ARM_ERRATA_794073 /* Disable Branch Prediction */ - Reg &= ~0x800; + Reg &= (u32)(~0x800U); #endif mtcp(XREG_CP15_SYS_CONTROL, Reg); } diff --git a/lib/bsp/standalone/src/cortexa9/xil_mmu.h b/lib/bsp/standalone/src/cortexa9/xil_mmu.h old mode 100755 new mode 100644 index da3a924f..673f2000 --- a/lib/bsp/standalone/src/cortexa9/xil_mmu.h +++ b/lib/bsp/standalone/src/cortexa9/xil_mmu.h @@ -72,7 +72,7 @@ extern "C" { /************************** Function Prototypes ******************************/ -void Xil_SetTlbAttributes(u32 addr, u32 attrib); +void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib); void Xil_EnableMMU(void); void Xil_DisableMMU(void); diff --git a/lib/bsp/standalone/src/cortexa9/xil_printf.c b/lib/bsp/standalone/src/cortexa9/xil_printf.c old mode 100755 new mode 100644 index 7660a8b4..701025b3 --- a/lib/bsp/standalone/src/cortexa9/xil_printf.c +++ b/lib/bsp/standalone/src/cortexa9/xil_printf.c @@ -6,18 +6,24 @@ /* */ /*---------------------------------------------------*/ #include "xil_printf.h" +#include "xil_types.h" +#include "xil_assert.h" #include #include #include +static void padding( const s32 l_flag,const struct params_s *par); +static void outs(const charptr lp, struct params_s *par); +static void outnum( const s32 n, const s32 base, struct params_s *par); +static s32 getnum( charptr* linep); typedef struct params_s { - int len; - int num1; - int num2; - char pad_character; - int do_padding; - int left_flag; + s32 len; + s32 num1; + s32 num2; + char8 pad_character; + s32 do_padding; + s32 left_flag; } params_t; @@ -35,15 +41,17 @@ typedef struct params_s { /* This routine puts pad characters into the output */ /* buffer. */ /* */ -void padding( const int l_flag, params_t *par) +static void padding( const s32 l_flag, const struct params_s *par) { - int i; + s32 i; - if (par->do_padding && l_flag && (par->len < par->num1)) - for (i=par->len; inum1; i++) { + if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) { + i=(par->len); + for (; i<(par->num1); i++) { #ifdef STDOUT_BASEADDRESS outbyte( par->pad_character); #endif + } } } @@ -52,22 +60,28 @@ void padding( const int l_flag, params_t *par) /* This routine moves a string to the output buffer */ /* as directed by the padding and positioning flags. */ /* */ -void outs( charptr lp, params_t *par) +static void outs(const charptr lp, struct params_s *par) { + charptr LocalPtr; + LocalPtr = lp; /* pad on left if needed */ - par->len = strlen( lp); + if(LocalPtr != NULL) { + par->len = (s32)strlen( LocalPtr); + } padding( !(par->left_flag), par); /* Move string to the buffer */ - while (*lp && (par->num2)--) { + while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) { + (par->num2)--; #ifdef STDOUT_BASEADDRESS - outbyte( *lp++); + outbyte(*LocalPtr); + LocalPtr += 1; #endif } /* Pad on right if needed */ /* CR 439175 - elided next stmt. Seemed bogus. */ - /* par->len = strlen( lp); */ + /* par->len = strlen( lp) */ padding( par->left_flag, par); } @@ -77,40 +91,52 @@ void outs( charptr lp, params_t *par) /* as directed by the padding and positioning flags. */ /* */ -void outnum( const long n, const long base, params_t *par) +static void outnum( const s32 n, const s32 base, struct params_s *par) { charptr cp; - int negative; - char outbuf[32]; - const char digits[] = "0123456789ABCDEF"; - unsigned long num; + s32 negative; + s32 i; + char8 outbuf[32]; + const char8 digits[] = "0123456789ABCDEF"; + s32 num; + for(i = 0; i<32; i++) { + outbuf[i] = '0'; + } /* Check if number is negative */ - if (base == 10 && n < 0L) { + if ((base == 10) && (n < 0L)) { negative = 1; - num = -(n); + num =(-(n)); } else{ - num = (n); + num = n; negative = 0; } /* Build number (backwards) in outbuf */ - cp = outbuf; + i = 0; do { - *cp++ = digits[(int)(num % base)]; - } while ((num /= base) > 0); - if (negative) - *cp++ = '-'; - *cp-- = 0; + outbuf[i] = digits[(num % base)]; + i++; + num /= base; + } while (num > 0); + + if (negative != 0) { + outbuf[i] = '-'; + i++; + } + + outbuf[i] = 0; + i--; /* Move the converted number to the buffer and */ /* add in the padding where needed. */ - par->len = strlen(outbuf); + par->len = (s32)strlen(outbuf); padding( !(par->left_flag), par); - while (cp >= outbuf) { + while (&outbuf[i] >= outbuf) { #ifdef STDOUT_BASEADDRESS - outbyte( *cp--); + outbyte( outbuf[i] ); + i--; #endif } padding( par->left_flag, par); @@ -121,16 +147,27 @@ void outnum( const long n, const long base, params_t *par) /* This routine gets a number from the format */ /* string. */ /* */ -int getnum( charptr* linep) +static s32 getnum( charptr* linep) { - int n; - charptr cp; - + s32 n; + s32 ResultIsDigit = 0; + charptr cptr; n = 0; - cp = *linep; - while (isdigit(((int)*cp))) - n = n*10 + ((*cp++) - '0'); - *linep = cp; + cptr = *linep; + if(cptr != NULL){ + ResultIsDigit = isdigit(((s32)*cptr)); + } + while (ResultIsDigit != 0) { + if(cptr != NULL){ + n = ((n*10) + (((s32)*cptr) - (s32)'0')); + cptr += 1; + if(cptr != NULL){ + ResultIsDigit = isdigit(((s32)*cptr)); + } + } + ResultIsDigit = isdigit(((s32)*cptr)); + } + *linep = ((charptr )(cptr)); return(n); } @@ -141,7 +178,7 @@ int getnum( charptr* linep) /* control of a formatting string. Not all of the */ /* standard C format control are supported. The ones */ /* provided are primarily those needed for embedded */ -/* systems work. Primarily the floaing point */ +/* systems work. Primarily the floating point */ /* routines are omitted. Other formats could be */ /* added easily by following the examples shown for */ /* the supported formats. */ @@ -149,116 +186,142 @@ int getnum( charptr* linep) /* void esp_printf( const func_ptr f_ptr, const charptr ctrl1, ...) */ -void xil_printf( const char *ctrl1, ...) +void xil_printf( char8 *ctrl1, ...) { - - int long_flag; - int dot_flag; + s32 Check; + s32 long_flag; + s32 dot_flag; params_t par; - char ch; + char8 ch; va_list argp; - char *ctrl = (char *)ctrl1; + char8 *ctrl = (char8 *)ctrl1; va_start( argp, ctrl1); - for ( ; *ctrl; ctrl++) { + while ((ctrl != NULL) && (*ctrl != (char8)0)) { /* move format string chars to buffer until a */ /* format control is found. */ if (*ctrl != '%') { #ifdef STDOUT_BASEADDRESS outbyte(*ctrl); + ctrl += 1; #endif continue; } /* initialize all the flags for this format. */ - dot_flag = long_flag = par.left_flag = par.do_padding = 0; + dot_flag = 0; + long_flag = 0; + par.left_flag = 0; + par.do_padding = 0; par.pad_character = ' '; par.num2=32767; + par.num1=0; + par.len=0; try_next: - ch = *(++ctrl); + if(ctrl != NULL) { + ctrl += 1; + } + if(ctrl != NULL) { + ch = *ctrl; + } + else { + ch = *ctrl; + } - if (isdigit((int)ch)) { - if (dot_flag) + if (isdigit((s32)ch) != 0) { + if (dot_flag != 0) { par.num2 = getnum(&ctrl); + } else { - if (ch == '0') + if (ch == '0') { par.pad_character = '0'; - - par.num1 = getnum(&ctrl); + } + if(ctrl != NULL) { + par.num1 = getnum(&ctrl); + } par.do_padding = 1; } - ctrl--; + if(ctrl != NULL) { + ctrl -= 1; + } goto try_next; } - switch (tolower((int)ch)) { + switch (tolower((s32)ch)) { case '%': #ifdef STDOUT_BASEADDRESS outbyte( '%'); #endif - continue; + Check = 1; + break; case '-': par.left_flag = 1; + Check = 0; break; case '.': dot_flag = 1; + Check = 0; break; case 'l': long_flag = 1; + Check = 0; break; case 'd': - if (long_flag || ch == 'D') { - outnum( va_arg(argp, long), 10L, &par); - continue; + if ((long_flag != 0) || (ch == 'D')) { + outnum( va_arg(argp, s32), 10L, &par); } else { - outnum( va_arg(argp, int), 10L, &par); - continue; + outnum( va_arg(argp, s32), 10L, &par); } + Check = 1; + break; case 'x': - outnum((long)va_arg(argp, int), 16L, &par); - continue; + outnum((s32)va_arg(argp, s32), 16L, &par); + Check = 1; + break; case 's': outs( va_arg( argp, char *), &par); - continue; + Check = 1; + break; case 'c': #ifdef STDOUT_BASEADDRESS - outbyte( va_arg( argp, int)); + outbyte( va_arg( argp, s32)); #endif - continue; + Check = 1; + break; case '\\': switch (*ctrl) { case 'a': #ifdef STDOUT_BASEADDRESS - outbyte( 0x07); + outbyte( ((char8)0x07)); #endif break; case 'h': #ifdef STDOUT_BASEADDRESS - outbyte( 0x08); + outbyte( ((char8)0x08)); #endif break; case 'r': #ifdef STDOUT_BASEADDRESS - outbyte( 0x0D); + outbyte( ((char8)0x0D)); #endif break; case 'n': #ifdef STDOUT_BASEADDRESS - outbyte( 0x0D); - outbyte( 0x0A); + outbyte( ((char8)0x0D)); + outbyte( ((char8)0x0A)); #endif break; default: @@ -267,10 +330,18 @@ void xil_printf( const char *ctrl1, ...) #endif break; } - ctrl++; + ctrl += 1; + Check = 0; break; default: + Check = 1; + break; + } + if(Check == 1) { + if(ctrl != NULL) { + ctrl += 1; + } continue; } goto try_next; diff --git a/lib/bsp/standalone/src/cortexa9/xil_printf.h b/lib/bsp/standalone/src/cortexa9/xil_printf.h old mode 100755 new mode 100644 index 89a051c2..6c1e1507 --- a/lib/bsp/standalone/src/cortexa9/xil_printf.h +++ b/lib/bsp/standalone/src/cortexa9/xil_printf.h @@ -8,8 +8,8 @@ extern "C" { #include #include #include -#include "xparameters.h" #include "xil_types.h" +#include "xparameters.h" /*----------------------------------------------------*/ /* Use the following parameter passing structure to */ @@ -27,18 +27,15 @@ struct params_s; /* that is unacceptable in most embedded systems. */ /*---------------------------------------------------*/ -typedef char* charptr; -typedef int (*func_ptr)(int c); +typedef char8* charptr; +typedef s32 (*func_ptr)(int c); /* */ -void padding( const int l_flag, struct params_s *par); -void outs( charptr lp, struct params_s *par); -void outnum( const long n, const long base, struct params_s *par); -int getnum( charptr* linep); -void xil_printf( const char *ctrl1, ...); -void print( const char *ptr); -void outbyte (char); -char inbyte(void); + +void xil_printf( char8 *ctrl1, ...); +void print( const char8 *ptr); +extern void outbyte (char8 c); +extern char8 inbyte(void); #ifdef __cplusplus } diff --git a/lib/bsp/standalone/src/cortexa9/xl2cc.h b/lib/bsp/standalone/src/cortexa9/xl2cc.h old mode 100755 new mode 100644 index c31edc1b..fd34f64c --- a/lib/bsp/standalone/src/cortexa9/xl2cc.h +++ b/lib/bsp/standalone/src/cortexa9/xl2cc.h @@ -61,109 +61,109 @@ extern "C" { /************************** Constant Definitions *****************************/ /* L2CC Register Offsets */ -#define XPS_L2CC_ID_OFFSET 0x0000 -#define XPS_L2CC_TYPE_OFFSET 0x0004 -#define XPS_L2CC_CNTRL_OFFSET 0x0100 -#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104 -#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108 -#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010C +#define XPS_L2CC_ID_OFFSET 0x0000U +#define XPS_L2CC_TYPE_OFFSET 0x0004U +#define XPS_L2CC_CNTRL_OFFSET 0x0100U +#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U +#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U +#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU -#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200 -#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204 -#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208 -#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020C -#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210 +#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U +#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U +#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U +#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU +#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U -#define XPS_L2CC_IER_OFFSET 0x0214 /* Interrupt Mask */ -#define XPS_L2CC_IPR_OFFSET 0x0218 /* Masked interrupt status */ -#define XPS_L2CC_ISR_OFFSET 0x021C /* Raw Interrupt Status */ -#define XPS_L2CC_IAR_OFFSET 0x0220 /* Interrupt Clear */ +#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */ +#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */ +#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */ +#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */ -#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730 /* Cache Sync */ -#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740 /* Dummy Register for Cache Sync */ -#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770 /* Cache Invalid by PA */ -#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077C /* Cache Invalid by Way */ -#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0 /* Cache Clean by PA */ -#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8 /* Cache Clean by Index */ -#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BC /* Cache Clean by Way */ -#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0 /* Cache Invalidate and Clean by PA */ -#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8 /* Cache Invalidate and Clean by Index */ -#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FC /* Cache Invalidate and Clean by Way */ +#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */ +#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */ +#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */ +#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */ +#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */ +#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */ +#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */ +#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */ +#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */ +#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900 /* Cache Data Lockdown 0 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904 /* Cache Instruction Lockdown 0 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908 /* Cache Data Lockdown 1 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090C /* Cache Instruction Lockdown 1 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910 /* Cache Data Lockdown 2 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914 /* Cache Instruction Lockdown 2 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918 /* Cache Data Lockdown 3 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091C /* Cache Instruction Lockdown 3 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920 /* Cache Data Lockdown 4 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924 /* Cache Instruction Lockdown 4 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928 /* Cache Data Lockdown 5 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092C /* Cache Instruction Lockdown 5 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930 /* Cache Data Lockdown 6 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934 /* Cache Instruction Lockdown 6 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938 /* Cache Data Lockdown 7 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093C /* Cache Instruction Lockdown 7 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */ -#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950 /* Cache Lockdown Line Enable */ -#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954 /* Cache Unlock All Lines by Way */ +#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */ +#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */ -#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00 /* Start of address filtering */ -#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04 /* Start of address filtering */ +#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */ +#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */ -#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40 /* Debug Control Register */ +#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */ /* XPS_L2CC_CNTRL_OFFSET bit masks */ -#define XPS_L2CC_ENABLE_MASK 0x00000001 /* enables the L2CC */ +#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */ /* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */ -#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000 /* Early BRESP Enable */ -#define XPS_L2CC_AUX_IPFE_MASK 0x20000000 /* Instruction Prefetch Enable */ -#define XPS_L2CC_AUX_DPFE_MASK 0x10000000 /* Data Prefetch Enable */ -#define XPS_L2CC_AUX_NSIC_MASK 0x08000000 /* Non-secure interrupt access control */ -#define XPS_L2CC_AUX_NSLE_MASK 0x04000000 /* Non-secure lockdown enable */ -#define XPS_L2CC_AUX_CRP_MASK 0x02000000 /* Cache replacement policy */ -#define XPS_L2CC_AUX_FWE_MASK 0x01800000 /* Force write allocate */ -#define XPS_L2CC_AUX_SAOE_MASK 0x00400000 /* Shared attribute override enable */ -#define XPS_L2CC_AUX_PE_MASK 0x00200000 /* Parity enable */ -#define XPS_L2CC_AUX_EMBE_MASK 0x00100000 /* Event monitor bus enable */ -#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000 /* Way-size */ -#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000 /* Associativity */ -#define XPS_L2CC_AUX_SAIE_MASK 0x00002000 /* Shared attribute invalidate enable */ -#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000 /* Exclusive cache configuration */ -#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800 /* Store buffer device limitation Enable */ -#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400 /* High Priority for SO and Dev Reads Enable */ -#define XPS_L2CC_AUX_FLZE_MASK 0x00000001 /* Full line of zero enable */ +#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */ +#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */ +#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */ +#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */ +#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */ +#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */ +#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */ +#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */ +#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */ +#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */ +#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */ +#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */ +#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */ +#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */ +#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */ +#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */ +#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */ -#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000 /* Enable all prefetching, */ +#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */ /* Cache replacement policy, Parity enable, */ /* Event monitor bus enable and Way Size (64 KB) */ -#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFF /* */ +#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */ -#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111 /* latency for TAG RAM */ -#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121 /* latency for DATA RAM */ +#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */ +#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */ /* Interrupt bit masks */ -#define XPS_L2CC_IXR_DECERR_MASK 0x00000100 /* DECERR from L3 */ -#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080 /* SLVERR from L3 */ -#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040 /* Error on L2 data RAM (Read) */ -#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020 /* Error on L2 tag RAM (Read) */ -#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010 /* Error on L2 data RAM (Write) */ -#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008 /* Error on L2 tag RAM (Write) */ -#define XPS_L2CC_IXR_PARRD_MASK 0x00000004 /* Parity Error on L2 data RAM (Read) */ -#define XPS_L2CC_IXR_PARRT_MASK 0x00000002 /* Parity Error on L2 tag RAM (Read) */ -#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001 /* Event Counter1/0 Overflow Increment */ +#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */ +#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */ +#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */ +#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */ +#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */ +#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */ +#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */ +#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */ +#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */ /* Address filtering mask and enable bit */ -#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000 /* Address filtering valid bits*/ -#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001 /* Address filtering enable bit*/ +#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/ +#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/ /* Debug control bits */ -#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004 /* Debug SPIDEN bit */ -#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002 /* Debug DWB bit, forces write through */ -#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002 /* Debug DCL bit, disables cache line fill */ +#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */ +#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */ +#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */ #ifdef __cplusplus } diff --git a/lib/bsp/standalone/src/cortexa9/xl2cc_counter.c b/lib/bsp/standalone/src/cortexa9/xl2cc_counter.c old mode 100755 new mode 100644 index bbea0f57..761186ac --- a/lib/bsp/standalone/src/cortexa9/xl2cc_counter.c +++ b/lib/bsp/standalone/src/cortexa9/xl2cc_counter.c @@ -86,14 +86,14 @@ void XL2cc_EventCtrReset(void); * @note None. * *****************************************************************************/ -void XL2cc_EventCtrInit(int Event0, int Event1) +void XL2cc_EventCtrInit(s32 Event0, s32 Event1) { /* Write event code into cnt1 cfg reg */ - *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (Event1 << 2); + *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (((u32)Event1) << 2); /* Write event code into cnt0 cfg reg */ - *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (Event0 << 2); + *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (((u32)Event0) << 2); /* Reset counters */ XL2cc_EventCtrReset(); @@ -113,10 +113,13 @@ void XL2cc_EventCtrInit(int Event0, int Event1) *****************************************************************************/ void XL2cc_EventCtrStart(void) { + u32 *LocalPtr; + LocalPtr = (u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET); XL2cc_EventCtrReset(); /* Enable counter */ - *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 1; + /* *((volatile u32*)((void *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET))) = 1 */ + *LocalPtr = (u32)1; } /****************************************************************************/ @@ -138,7 +141,7 @@ void XL2cc_EventCtrStart(void) void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1) { /* Disable counter */ - *((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0; + *((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0U; /* Save counter values */ *EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET)); @@ -161,5 +164,5 @@ void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1) *****************************************************************************/ void XL2cc_EventCtrReset(void) { - *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6; + *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6U; } diff --git a/lib/bsp/standalone/src/cortexa9/xl2cc_counter.h b/lib/bsp/standalone/src/cortexa9/xl2cc_counter.h old mode 100755 new mode 100644 index 6cc48b4f..28e7d9f9 --- a/lib/bsp/standalone/src/cortexa9/xl2cc_counter.h +++ b/lib/bsp/standalone/src/cortexa9/xl2cc_counter.h @@ -97,7 +97,7 @@ extern "C" { /************************** Function Prototypes *****************************/ -void XL2cc_EventCtrInit(int Event0, int Event1); +void XL2cc_EventCtrInit(s32 Event0, s32 Event1); void XL2cc_EventCtrStart(void); void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1); diff --git a/lib/bsp/standalone/src/cortexa9/xparameters_ps.h b/lib/bsp/standalone/src/cortexa9/xparameters_ps.h old mode 100755 new mode 100644 index caa1020e..22e79de0 --- a/lib/bsp/standalone/src/cortexa9/xparameters_ps.h +++ b/lib/bsp/standalone/src/cortexa9/xparameters_ps.h @@ -67,8 +67,8 @@ extern "C" { */ /* Canonical definitions for DDR MEMORY */ -#define XPAR_DDR_MEM_BASEADDR 0x00000000 -#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFF +#define XPAR_DDR_MEM_BASEADDR 0x00000000U +#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU /* Canonical definitions for Interrupts */ #define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID @@ -121,21 +121,21 @@ extern "C" { /* Canonical definitions for WDT */ /* Canonical definitions for SLCR */ -#define XPAR_XSLCR_NUM_INSTANCES 1 -#define XPAR_XSLCR_0_DEVICE_ID 0 +#define XPAR_XSLCR_NUM_INSTANCES 1U +#define XPAR_XSLCR_0_DEVICE_ID 0U #define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR /* Canonical definitions for SCU GIC */ -#define XPAR_SCUGIC_NUM_INSTANCES 1 -#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0 -#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x0100) -#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x1000) -#define XPAR_SCUGIC_ACK_BEFORE 0 +#define XPAR_SCUGIC_NUM_INSTANCES 1U +#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U +#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U) +#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U) +#define XPAR_SCUGIC_ACK_BEFORE 0U /* Canonical definitions for Global Timer */ -#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1 -#define XPAR_GLOBAL_TMR_DEVICE_ID 0 -#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x200) +#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U +#define XPAR_GLOBAL_TMR_DEVICE_ID 0U +#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U) #define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID @@ -151,121 +151,121 @@ extern "C" { * within the hardblock. These have been put for bacwards compatibilty */ -#define XPS_PERIPHERAL_BASEADDR 0xE0000000 -#define XPS_UART0_BASEADDR 0xE0000000 -#define XPS_UART1_BASEADDR 0xE0001000 -#define XPS_USB0_BASEADDR 0xE0002000 -#define XPS_USB1_BASEADDR 0xE0003000 -#define XPS_I2C0_BASEADDR 0xE0004000 -#define XPS_I2C1_BASEADDR 0xE0005000 -#define XPS_SPI0_BASEADDR 0xE0006000 -#define XPS_SPI1_BASEADDR 0xE0007000 -#define XPS_CAN0_BASEADDR 0xE0008000 -#define XPS_CAN1_BASEADDR 0xE0009000 -#define XPS_GPIO_BASEADDR 0xE000A000 -#define XPS_GEM0_BASEADDR 0xE000B000 -#define XPS_GEM1_BASEADDR 0xE000C000 -#define XPS_QSPI_BASEADDR 0xE000D000 -#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000 -#define XPS_SDIO0_BASEADDR 0xE0100000 -#define XPS_SDIO1_BASEADDR 0xE0101000 -#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000 -#define XPS_NAND_BASEADDR 0xE1000000 -#define XPS_PARPORT0_BASEADDR 0xE2000000 -#define XPS_PARPORT1_BASEADDR 0xE4000000 -#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000 -#define XPS_SYS_CTRL_BASEADDR 0xF8000000 /* AKA SLCR */ -#define XPS_TTC0_BASEADDR 0xF8001000 -#define XPS_TTC1_BASEADDR 0xF8002000 -#define XPS_DMAC0_SEC_BASEADDR 0xF8003000 -#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000 -#define XPS_WDT_BASEADDR 0xF8005000 -#define XPS_DDR_CTRL_BASEADDR 0xF8006000 -#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000 -#define XPS_AFI0_BASEADDR 0xF8008000 -#define XPS_AFI1_BASEADDR 0xF8009000 -#define XPS_AFI2_BASEADDR 0xF800A000 -#define XPS_AFI3_BASEADDR 0xF800B000 -#define XPS_OCM_BASEADDR 0xF800C000 -#define XPS_EFUSE_BASEADDR 0xF800D000 -#define XPS_CORESIGHT_BASEADDR 0xF8800000 -#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000 -#define XPS_SCU_PERIPH_BASE 0xF8F00000 -#define XPS_L2CC_BASEADDR 0xF8F02000 -#define XPS_SAM_RAM_BASEADDR 0xFFFC0000 -#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000 -#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000 -#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000 -#define XPS_PERIPH_APB_BASEADDR 0xF8000000 +#define XPS_PERIPHERAL_BASEADDR 0xE0000000U +#define XPS_UART0_BASEADDR 0xE0000000U +#define XPS_UART1_BASEADDR 0xE0001000U +#define XPS_USB0_BASEADDR 0xE0002000U +#define XPS_USB1_BASEADDR 0xE0003000U +#define XPS_I2C0_BASEADDR 0xE0004000U +#define XPS_I2C1_BASEADDR 0xE0005000U +#define XPS_SPI0_BASEADDR 0xE0006000U +#define XPS_SPI1_BASEADDR 0xE0007000U +#define XPS_CAN0_BASEADDR 0xE0008000U +#define XPS_CAN1_BASEADDR 0xE0009000U +#define XPS_GPIO_BASEADDR 0xE000A000U +#define XPS_GEM0_BASEADDR 0xE000B000U +#define XPS_GEM1_BASEADDR 0xE000C000U +#define XPS_QSPI_BASEADDR 0xE000D000U +#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U +#define XPS_SDIO0_BASEADDR 0xE0100000U +#define XPS_SDIO1_BASEADDR 0xE0101000U +#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U +#define XPS_NAND_BASEADDR 0xE1000000U +#define XPS_PARPORT0_BASEADDR 0xE2000000U +#define XPS_PARPORT1_BASEADDR 0xE4000000U +#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U +#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */ +#define XPS_TTC0_BASEADDR 0xF8001000U +#define XPS_TTC1_BASEADDR 0xF8002000U +#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U +#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U +#define XPS_WDT_BASEADDR 0xF8005000U +#define XPS_DDR_CTRL_BASEADDR 0xF8006000U +#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U +#define XPS_AFI0_BASEADDR 0xF8008000U +#define XPS_AFI1_BASEADDR 0xF8009000U +#define XPS_AFI2_BASEADDR 0xF800A000U +#define XPS_AFI3_BASEADDR 0xF800B000U +#define XPS_OCM_BASEADDR 0xF800C000U +#define XPS_EFUSE_BASEADDR 0xF800D000U +#define XPS_CORESIGHT_BASEADDR 0xF8800000U +#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U +#define XPS_SCU_PERIPH_BASE 0xF8F00000U +#define XPS_L2CC_BASEADDR 0xF8F02000U +#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U +#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U +#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U +#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U +#define XPS_PERIPH_APB_BASEADDR 0xF8000000U /* Shared Peripheral Interrupts (SPI) */ -#define XPS_CORE_PARITY0_INT_ID 32 -#define XPS_CORE_PARITY1_INT_ID 33 -#define XPS_L2CC_INT_ID 34 -#define XPS_OCMINTR_INT_ID 35 -#define XPS_ECC_INT_ID 36 -#define XPS_PMU0_INT_ID 37 -#define XPS_PMU1_INT_ID 38 -#define XPS_SYSMON_INT_ID 39 -#define XPS_DVC_INT_ID 40 -#define XPS_WDT_INT_ID 41 -#define XPS_TTC0_0_INT_ID 42 -#define XPS_TTC0_1_INT_ID 43 -#define XPS_TTC0_2_INT_ID 44 -#define XPS_DMA0_ABORT_INT_ID 45 -#define XPS_DMA0_INT_ID 46 -#define XPS_DMA1_INT_ID 47 -#define XPS_DMA2_INT_ID 48 -#define XPS_DMA3_INT_ID 49 -#define XPS_SMC_INT_ID 50 -#define XPS_QSPI_INT_ID 51 -#define XPS_GPIO_INT_ID 52 -#define XPS_USB0_INT_ID 53 -#define XPS_GEM0_INT_ID 54 -#define XPS_GEM0_WAKE_INT_ID 55 -#define XPS_SDIO0_INT_ID 56 -#define XPS_I2C0_INT_ID 57 -#define XPS_SPI0_INT_ID 58 -#define XPS_UART0_INT_ID 59 -#define XPS_CAN0_INT_ID 60 -#define XPS_FPGA0_INT_ID 61 -#define XPS_FPGA1_INT_ID 62 -#define XPS_FPGA2_INT_ID 63 -#define XPS_FPGA3_INT_ID 64 -#define XPS_FPGA4_INT_ID 65 -#define XPS_FPGA5_INT_ID 66 -#define XPS_FPGA6_INT_ID 67 -#define XPS_FPGA7_INT_ID 68 -#define XPS_TTC1_0_INT_ID 69 -#define XPS_TTC1_1_INT_ID 70 -#define XPS_TTC1_2_INT_ID 71 -#define XPS_DMA4_INT_ID 72 -#define XPS_DMA5_INT_ID 73 -#define XPS_DMA6_INT_ID 74 -#define XPS_DMA7_INT_ID 75 -#define XPS_USB1_INT_ID 76 -#define XPS_GEM1_INT_ID 77 -#define XPS_GEM1_WAKE_INT_ID 78 -#define XPS_SDIO1_INT_ID 79 -#define XPS_I2C1_INT_ID 80 -#define XPS_SPI1_INT_ID 81 -#define XPS_UART1_INT_ID 82 -#define XPS_CAN1_INT_ID 83 -#define XPS_FPGA8_INT_ID 84 -#define XPS_FPGA9_INT_ID 85 -#define XPS_FPGA10_INT_ID 86 -#define XPS_FPGA11_INT_ID 87 -#define XPS_FPGA12_INT_ID 88 -#define XPS_FPGA13_INT_ID 89 -#define XPS_FPGA14_INT_ID 90 -#define XPS_FPGA15_INT_ID 91 +#define XPS_CORE_PARITY0_INT_ID 32U +#define XPS_CORE_PARITY1_INT_ID 33U +#define XPS_L2CC_INT_ID 34U +#define XPS_OCMINTR_INT_ID 35U +#define XPS_ECC_INT_ID 36U +#define XPS_PMU0_INT_ID 37U +#define XPS_PMU1_INT_ID 38U +#define XPS_SYSMON_INT_ID 39U +#define XPS_DVC_INT_ID 40U +#define XPS_WDT_INT_ID 41U +#define XPS_TTC0_0_INT_ID 42U +#define XPS_TTC0_1_INT_ID 43U +#define XPS_TTC0_2_INT_ID 44U +#define XPS_DMA0_ABORT_INT_ID 45U +#define XPS_DMA0_INT_ID 46U +#define XPS_DMA1_INT_ID 47U +#define XPS_DMA2_INT_ID 48U +#define XPS_DMA3_INT_ID 49U +#define XPS_SMC_INT_ID 50U +#define XPS_QSPI_INT_ID 51U +#define XPS_GPIO_INT_ID 52U +#define XPS_USB0_INT_ID 53U +#define XPS_GEM0_INT_ID 54U +#define XPS_GEM0_WAKE_INT_ID 55U +#define XPS_SDIO0_INT_ID 56U +#define XPS_I2C0_INT_ID 57U +#define XPS_SPI0_INT_ID 58U +#define XPS_UART0_INT_ID 59U +#define XPS_CAN0_INT_ID 60U +#define XPS_FPGA0_INT_ID 61U +#define XPS_FPGA1_INT_ID 62U +#define XPS_FPGA2_INT_ID 63U +#define XPS_FPGA3_INT_ID 64U +#define XPS_FPGA4_INT_ID 65U +#define XPS_FPGA5_INT_ID 66U +#define XPS_FPGA6_INT_ID 67U +#define XPS_FPGA7_INT_ID 68U +#define XPS_TTC1_0_INT_ID 69U +#define XPS_TTC1_1_INT_ID 70U +#define XPS_TTC1_2_INT_ID 71U +#define XPS_DMA4_INT_ID 72U +#define XPS_DMA5_INT_ID 73U +#define XPS_DMA6_INT_ID 74U +#define XPS_DMA7_INT_ID 75U +#define XPS_USB1_INT_ID 76U +#define XPS_GEM1_INT_ID 77U +#define XPS_GEM1_WAKE_INT_ID 78U +#define XPS_SDIO1_INT_ID 79U +#define XPS_I2C1_INT_ID 80U +#define XPS_SPI1_INT_ID 81U +#define XPS_UART1_INT_ID 82U +#define XPS_CAN1_INT_ID 83U +#define XPS_FPGA8_INT_ID 84U +#define XPS_FPGA9_INT_ID 85U +#define XPS_FPGA10_INT_ID 86U +#define XPS_FPGA11_INT_ID 87U +#define XPS_FPGA12_INT_ID 88U +#define XPS_FPGA13_INT_ID 89U +#define XPS_FPGA14_INT_ID 90U +#define XPS_FPGA15_INT_ID 91U /* Private Peripheral Interrupts (PPI) */ -#define XPS_GLOBAL_TMR_INT_ID 27 /* SCU Global Timer interrupt */ -#define XPS_FIQ_INT_ID 28 /* FIQ from FPGA fabric */ -#define XPS_SCU_TMR_INT_ID 29 /* SCU Private Timer interrupt */ -#define XPS_SCU_WDT_INT_ID 30 /* SCU Private WDT interrupt */ -#define XPS_IRQ_INT_ID 31 /* IRQ from FPGA fabric */ +#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */ +#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */ +#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */ +#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */ +#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */ /* REDEFINES for TEST APP */ @@ -315,8 +315,8 @@ extern "C" { #define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ #endif -#define XPAR_SCUTIMER_DEVICE_ID 0 -#define XPAR_SCUWDT_DEVICE_ID 0 +#define XPAR_SCUTIMER_DEVICE_ID 0U +#define XPAR_SCUWDT_DEVICE_ID 0U #ifdef __cplusplus diff --git a/lib/bsp/standalone/src/cortexa9/xpm_counter.c b/lib/bsp/standalone/src/cortexa9/xpm_counter.c old mode 100755 new mode 100644 index 25a291c2..6cc88f9a --- a/lib/bsp/standalone/src/cortexa9/xpm_counter.c +++ b/lib/bsp/standalone/src/cortexa9/xpm_counter.c @@ -58,13 +58,103 @@ /**************************** Type Definitions ******************************/ -typedef const u32 PmcrEventCfg[XPM_CTRCOUNT]; +typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT]; /***************** Macros (Inline Functions) Definitions ********************/ /************************** Variable Definitions *****************************/ -static PmcrEventCfg PmcrEvents[] = { +/************************** Function Prototypes ******************************/ + +void Xpm_DisableEventCounters(void); +void Xpm_EnableEventCounters (void); +void Xpm_ResetEventCounters (void); + +/******************************************************************************/ + +/****************************************************************************/ +/** +* +* This function disables the Cortex A9 event counters. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_DisableEventCounters(void) +{ + /* Disable the event counters */ + mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f); +} + +/****************************************************************************/ +/** +* +* This function enables the Cortex A9 event counters. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_EnableEventCounters(void) +{ + /* Enable the event counters */ + mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f); +} + +/****************************************************************************/ +/** +* +* This function resets the Cortex A9 event counters. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_ResetEventCounters(void) +{ + u32 Reg; +#ifdef __GNUC__ + Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); +#else + { register uint32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL); + Reg = C15Reg; } +#endif + Reg |= (1U << 1U); /* reset event counters */ + mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); + +} + +/****************************************************************************/ +/** +* +* This function configures the Cortex A9 event counters controller, with the +* event codes, in a configuration selected by the user and enables the counters. +* +* @param PmcrCfg is configuration value based on which the event counters +* are configured. +* Use XPM_CNTRCFG* values defined in xpm_counter.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_SetEvents(s32 PmcrCfg) +{ + u32 Counter; + static PmcrEventCfg32 PmcrEvents[] = { { XPM_EVENT_SOFTINCR, XPM_EVENT_INSRFETCH_CACHEREFILL, @@ -153,109 +243,18 @@ static PmcrEventCfg PmcrEvents[] = { XPM_EVENT_DATA_CACHEACCESS, XPM_EVENT_DATA_TLBREFILL }, -}; - -/************************** Function Prototypes ******************************/ - -void Xpm_DisableEventCounters(void); -void Xpm_EnableEventCounters (void); -void Xpm_ResetEventCounters (void); - -/******************************************************************************/ - -/****************************************************************************/ -/** -* -* This function disables the Cortex A9 event counters. -* -* @param None. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void Xpm_DisableEventCounters(void) -{ - /* Disable the event counters */ - mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f); -} - -/****************************************************************************/ -/** -* -* This function enables the Cortex A9 event counters. -* -* @param None. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void Xpm_EnableEventCounters(void) -{ - /* Enable the event counters */ - mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f); -} - -/****************************************************************************/ -/** -* -* This function resets the Cortex A9 event counters. -* -* @param None. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void Xpm_ResetEventCounters(void) -{ - u32 Reg; - -#ifdef __GNUC__ - Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); -#else - { register unsigned int C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL); - Reg = C15Reg; } -#endif - Reg |= (1 << 1); /* reset event counters */ - mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); -} - -/****************************************************************************/ -/** -* -* This function configures the Cortex A9 event counters controller, with the -* event codes, in a configuration selected by the user and enables the counters. -* -* @param PmcrCfg is configuration value based on which the event counters -* are configured. -* Use XPM_CNTRCFG* values defined in xpm_counter.h. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void Xpm_SetEvents(int PmcrCfg) -{ - u32 Counter; - const u32 *Ptr = PmcrEvents[PmcrCfg]; + }; + const u32 *ptr = PmcrEvents[PmcrCfg]; Xpm_DisableEventCounters(); - for(Counter = 0; Counter < XPM_CTRCOUNT; Counter++) { + for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) { /* Selecet event counter */ mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); /* Set the event */ - mtcp(XREG_CP15_EVENT_TYPE_SEL, Ptr[Counter]); + mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]); } Xpm_ResetEventCounters(); @@ -282,7 +281,7 @@ void Xpm_GetEventCounters(u32 *PmCtrValue) Xpm_DisableEventCounters(); - for(Counter = 0; Counter < XPM_CTRCOUNT; Counter++) { + for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) { mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); #ifdef __GNUC__ @@ -290,7 +289,7 @@ void Xpm_GetEventCounters(u32 *PmCtrValue) #elif defined (__ICCARM__) mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]); #else - { register unsigned int Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT); + { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT); PmCtrValue[Counter] = Cp15Reg; } #endif } diff --git a/lib/bsp/standalone/src/cortexa9/xpm_counter.h b/lib/bsp/standalone/src/cortexa9/xpm_counter.h old mode 100755 new mode 100644 index 3012428c..19e8ef2c --- a/lib/bsp/standalone/src/cortexa9/xpm_counter.h +++ b/lib/bsp/standalone/src/cortexa9/xpm_counter.h @@ -75,7 +75,7 @@ extern "C" { /************************** Constant Definitions ****************************/ /* Number of performance counters */ -#define XPM_CTRCOUNT 6 +#define XPM_CTRCOUNT 6U /* The following constants define the Cortex-A9 Performance Monitor Events */ @@ -83,40 +83,40 @@ extern "C" { * Software increment. The register is incremented only on writes to the * Software Increment Register */ -#define XPM_EVENT_SOFTINCR 0x00 +#define XPM_EVENT_SOFTINCR 0x00U /* * Instruction fetch that causes a refill at (at least) the lowest level(s) of * instruction or unified cache. Includes the speculative linefills in the * count */ -#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01 +#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U /* * Instruction fetch that causes a TLB refill at (at least) the lowest level of * TLB. Includes the speculative requests in the count */ -#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02 +#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U /* * Data read or write operation that causes a refill at (at least) the lowest * level(s)of data or unified cache. Counts the number of allocations performed * in the Data Cache due to a read or a write */ -#define XPM_EVENT_DATA_CACHEREFILL 0x03 +#define XPM_EVENT_DATA_CACHEREFILL 0x03U /* * Data read or write operation that causes a cache access at (at least) the * lowest level(s) of data or unified cache. This includes speculative reads */ -#define XPM_EVENT_DATA_CACHEACCESS 0x04 +#define XPM_EVENT_DATA_CACHEACCESS 0x04U /* * Data read or write operation that causes a TLB refill at (at least) the * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI, * CP15 Cache operation by MVA and CP15 VA to PA operations */ -#define XPM_EVENT_DATA_TLBREFILL 0x05 +#define XPM_EVENT_DATA_TLBREFILL 0x05U /* * Data read architecturally executed. Counts the number of data read @@ -124,7 +124,7 @@ extern "C" { * speculative and aborted LDR/LDM, as well as the reads due to the SWP * instructions */ -#define XPM_EVENT_DATA_READS 0x06 +#define XPM_EVENT_DATA_READS 0x06U /* * Data write architecturally executed. Counts the number of data write @@ -132,79 +132,79 @@ extern "C" { * speculative and aborted STR/STM, as well as the writes due to the SWP * instructions */ -#define XPM_EVENT_DATA_WRITE 0x07 +#define XPM_EVENT_DATA_WRITE 0x07U /* Exception taken. Counts the number of exceptions architecturally taken.*/ -#define XPM_EVENT_EXCEPTION 0x09 +#define XPM_EVENT_EXCEPTION 0x09U /* Exception return architecturally executed.*/ -#define XPM_EVENT_EXCEPRETURN 0x0A +#define XPM_EVENT_EXCEPRETURN 0x0AU /* * Change to ContextID retired. Counts the number of instructions * architecturally executed writing into the ContextID Register */ -#define XPM_EVENT_CHANGECONTEXT 0x0B +#define XPM_EVENT_CHANGECONTEXT 0x0BU /* * Software change of PC, except by an exception, architecturally executed. * Count the number of PC changes architecturally executed, excluding the PC * changes due to taken exceptions */ -#define XPM_EVENT_SW_CHANGEPC 0x0C +#define XPM_EVENT_SW_CHANGEPC 0x0CU /* * Immediate branch architecturally executed (taken or not taken). This includes * the branches which are flushed due to a previous load/store which aborts * late */ -#define XPM_EVENT_IMMEDBRANCH 0x0D +#define XPM_EVENT_IMMEDBRANCH 0x0DU /* * Unaligned access architecturally executed. Counts the number of aborted * unaligned accessed architecturally executed, and the number of not-aborted * unaligned accesses, including the speculative ones */ -#define XPM_EVENT_UNALIGNEDACCESS 0x0F +#define XPM_EVENT_UNALIGNEDACCESS 0x0FU /* * Branch mispredicted/not predicted. Counts the number of mispredicted or * not-predicted branches executed. This includes the branches which are flushed * due to a previous load/store which aborts late */ -#define XPM_EVENT_BRANCHMISS 0x10 +#define XPM_EVENT_BRANCHMISS 0x10U /* * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This * event is not exported on the PMUEVENT bus */ -#define XPM_EVENT_CLOCKCYCLES 0x11 +#define XPM_EVENT_CLOCKCYCLES 0x11U /* * Branches or other change in program flow that could have been predicted by * the branch prediction resources of the processor. This includes the branches * which are flushed due to a previous load/store which aborts late */ -#define XPM_EVENT_BRANCHPREDICT 0x12 +#define XPM_EVENT_BRANCHPREDICT 0x12U /* * Java bytecode execute. Counts the number of Java bytecodes being decoded, * including speculative ones */ -#define XPM_EVENT_JAVABYTECODE 0x40 +#define XPM_EVENT_JAVABYTECODE 0x40U /* * Software Java bytecode executed. Counts the number of software java bytecodes * being decoded, including speculative ones */ -#define XPM_EVENT_SWJAVABYTECODE 0x41 +#define XPM_EVENT_SWJAVABYTECODE 0x41U /* * Jazelle backward branches executed. Counts the number of Jazelle taken * branches being executed. This includes the branches which are flushed due * to a previous load/store which aborts late */ -#define XPM_EVENT_JAVABACKBRANCH 0x42 +#define XPM_EVENT_JAVABACKBRANCH 0x42U /* * Coherent linefill miss Counts the number of coherent linefill requests @@ -212,7 +212,7 @@ extern "C" { * Cortex-A9 processors, meaning that the request is sent to the external * memory */ -#define XPM_EVENT_COHERLINEMISS 0x50 +#define XPM_EVENT_COHERLINEMISS 0x50U /* * Coherent linefill hit. Counts the number of coherent linefill requests @@ -220,7 +220,7 @@ extern "C" { * processor, meaning that the linefill data is fetched directly from the * relevant Cortex-A9 cache */ -#define XPM_EVENT_COHERLINEHIT 0x51 +#define XPM_EVENT_COHERLINEHIT 0x51U /* * Instruction cache dependent stall cycles. Counts the number of cycles where @@ -228,14 +228,14 @@ extern "C" { * due to the instruction side not being able to provide any and the * instruction cache is currently performing at least one linefill */ -#define XPM_EVENT_INSTRSTALL 0x60 +#define XPM_EVENT_INSTRSTALL 0x60U /* * Data cache dependent stall cycles. Counts the number of cycles where the core * has some instructions that it cannot issue to any pipeline, and the Load * Store unit has at least one pending linefill request, and no pending */ -#define XPM_EVENT_DATASTALL 0x61 +#define XPM_EVENT_DATASTALL 0x61U /* * Main TLB miss stall cycles. Counts the number of cycles where the processor @@ -245,36 +245,36 @@ extern "C" { * provide the necessary data, due to them waiting for the main TLB translation * table walk to complete */ -#define XPM_EVENT_MAINTLBSTALL 0x62 +#define XPM_EVENT_MAINTLBSTALL 0x62U /* * Counts the number of STREX instructions architecturally executed and * passed */ -#define XPM_EVENT_STREXPASS 0x63 +#define XPM_EVENT_STREXPASS 0x63U /* * Counts the number of STREX instructions architecturally executed and * failed */ -#define XPM_EVENT_STREXFAIL 0x64 +#define XPM_EVENT_STREXFAIL 0x64U /* * Data eviction. Counts the number of eviction requests due to a linefill in * the data cache */ -#define XPM_EVENT_DATAEVICT 0x65 +#define XPM_EVENT_DATAEVICT 0x65U /* * Counts the number of cycles where the issue stage does not dispatch any * instruction because it is empty or cannot dispatch any instructions */ -#define XPM_EVENT_NODISPATCH 0x66 +#define XPM_EVENT_NODISPATCH 0x66U /* * Counts the number of cycles where the issue stage is empty */ -#define XPM_EVENT_ISSUEEMPTY 0x67 +#define XPM_EVENT_ISSUEEMPTY 0x67U /* * Counts the number of instructions going through the Register Renaming stage. @@ -288,7 +288,7 @@ extern "C" { * - b01 one instruction renamed * - b10 two instructions renamed */ -#define XPM_EVENT_INSTRRENAME 0x68 +#define XPM_EVENT_INSTRRENAME 0x68U /* * Counts the number of procedure returns whose condition codes do not fail, @@ -307,26 +307,26 @@ extern "C" { * - LDM SP,{...,PC} (writeback not specified) * - LDR PC,[SP,#offset] (wrong addressing mode) */ -#define XPM_EVENT_PREDICTFUNCRET 0x6E +#define XPM_EVENT_PREDICTFUNCRET 0x6EU /* * Counts the number of instructions being executed in the main execution * pipeline of the processor, the multiply pipeline and arithmetic logic unit * pipeline. The counted instructions are still speculative */ -#define XPM_EVENT_MAINEXEC 0x70 +#define XPM_EVENT_MAINEXEC 0x70U /* * Counts the number of instructions being executed in the processor second * execution pipeline (ALU). The counted instructions are still speculative */ -#define XPM_EVENT_SECEXEC 0x71 +#define XPM_EVENT_SECEXEC 0x71U /* * Counts the number of instructions being executed in the Load/Store unit. The * counted instructions are still speculative */ -#define XPM_EVENT_LDRSTR 0x72 +#define XPM_EVENT_LDRSTR 0x72U /* * Counts the number of Floating-point instructions going through the Register @@ -337,7 +337,7 @@ extern "C" { *0b01 one floating-point instruction renamed *0b10 two floating-point instructions renamed */ -#define XPM_EVENT_FLOATRENAME 0x73 +#define XPM_EVENT_FLOATRENAME 0x73U /* * Counts the number of Neon instructions going through the Register Rename @@ -348,113 +348,113 @@ extern "C" { *0b01 one NEON instruction renamed *0b10 two NEON instructions renamed */ -#define XPM_EVENT_NEONRENAME 0x74 +#define XPM_EVENT_NEONRENAME 0x74U /* * Counts the number of cycles where the processor is stalled because PLD slots * are all full */ -#define XPM_EVENT_PLDSTALL 0x80 +#define XPM_EVENT_PLDSTALL 0x80U /* * Counts the number of cycles when the processor is stalled and the data side * is stalled too because it is full and executing writes to the external * memory */ -#define XPM_EVENT_WRITESTALL 0x81 +#define XPM_EVENT_WRITESTALL 0x81U /* * Counts the number of stall cycles due to main TLB misses on requests issued * by the instruction side */ -#define XPM_EVENT_INSTRTLBSTALL 0x82 +#define XPM_EVENT_INSTRTLBSTALL 0x82U /* * Counts the number of stall cycles due to main TLB misses on requests issued * by the data side */ -#define XPM_EVENT_DATATLBSTALL 0x83 +#define XPM_EVENT_DATATLBSTALL 0x83U /* * Counts the number of stall cycles due to micro TLB misses on the instruction * side. This event does not include main TLB miss stall cycles that are already * counted in the corresponding main TLB event */ -#define XPM_EVENT_INSTR_uTLBSTALL 0x84 +#define XPM_EVENT_INSTR_uTLBSTALL 0x84U /* * Counts the number of stall cycles due to micro TLB misses on the data side. * This event does not include main TLB miss stall cycles that are already * counted in the corresponding main TLB event */ -#define XPM_EVENT_DATA_uTLBSTALL 0x85 +#define XPM_EVENT_DATA_uTLBSTALL 0x85U /* * Counts the number of stall cycles because of the execution of a DMB memory * barrier. This includes all DMB instructions being executed, even * speculatively */ -#define XPM_EVENT_DMB_STALL 0x86 +#define XPM_EVENT_DMB_STALL 0x86U /* * Counts the number of cycles during which the integer core clock is enabled */ -#define XPM_EVENT_INT_CLKEN 0x8A +#define XPM_EVENT_INT_CLKEN 0x8AU /* * Counts the number of cycles during which the Data Engine clock is enabled */ -#define XPM_EVENT_DE_CLKEN 0x8B +#define XPM_EVENT_DE_CLKEN 0x8BU /* * Counts the number of ISB instructions architecturally executed */ -#define XPM_EVENT_INSTRISB 0x90 +#define XPM_EVENT_INSTRISB 0x90U /* * Counts the number of DSB instructions architecturally executed */ -#define XPM_EVENT_INSTRDSB 0x91 +#define XPM_EVENT_INSTRDSB 0x91U /* * Counts the number of DMB instructions speculatively executed */ -#define XPM_EVENT_INSTRDMB 0x92 +#define XPM_EVENT_INSTRDMB 0x92U /* * Counts the number of external interrupts executed by the processor */ -#define XPM_EVENT_EXTINT 0x93 +#define XPM_EVENT_EXTINT 0x93U /* * PLE cache line request completed */ -#define XPM_EVENT_PLE_LRC 0xA0 +#define XPM_EVENT_PLE_LRC 0xA0U /* * PLE cache line request skipped */ -#define XPM_EVENT_PLE_LRS 0xA1 +#define XPM_EVENT_PLE_LRS 0xA1U /* * PLE FIFO flush */ -#define XPM_EVENT_PLE_FLUSH 0xA2 +#define XPM_EVENT_PLE_FLUSH 0xA2U /* * PLE request complete */ -#define XPM_EVENT_PLE_CMPL 0xA3 +#define XPM_EVENT_PLE_CMPL 0xA3U /* * PLE FIFO overflow */ -#define XPM_EVENT_PLE_OVFL 0xA4 +#define XPM_EVENT_PLE_OVFL 0xA4U /* * PLE request programmed */ -#define XPM_EVENT_PLE_PROG 0xA5 +#define XPM_EVENT_PLE_PROG 0xA5U /* * The following constants define the configurations for Cortex-A9 Performance @@ -561,7 +561,7 @@ extern "C" { /************************** Function Prototypes *****************************/ /* Interface fuctions to access perfromance counters from abstraction layer */ -void Xpm_SetEvents(int PmcrCfg); +void Xpm_SetEvents(s32 PmcrCfg); void Xpm_GetEventCounters(u32 *PmCtrValue); #ifdef __cplusplus diff --git a/lib/bsp/standalone/src/cortexa9/xpseudo_asm.h b/lib/bsp/standalone/src/cortexa9/xpseudo_asm.h old mode 100755 new mode 100644 index 80feecd0..36151b32 --- a/lib/bsp/standalone/src/cortexa9/xpseudo_asm.h +++ b/lib/bsp/standalone/src/cortexa9/xpseudo_asm.h @@ -46,6 +46,9 @@ * * ******************************************************************************/ +#ifndef XPSEUDO_ASM_H +#define XPSEUDO_ASM_H + #include "xreg_cortexa9.h" #ifdef __GNUC__ #include "xpseudo_asm_gcc.h" @@ -54,3 +57,5 @@ #else #include "xpseudo_asm_rvct.h" #endif + +#endif /* XPSEUDO_ASM_H */ diff --git a/lib/bsp/standalone/src/cortexa9/xreg_cortexa9.h b/lib/bsp/standalone/src/cortexa9/xreg_cortexa9.h old mode 100755 new mode 100644 index dacb3090..b63cc2ce --- a/lib/bsp/standalone/src/cortexa9/xreg_cortexa9.h +++ b/lib/bsp/standalone/src/cortexa9/xreg_cortexa9.h @@ -210,21 +210,21 @@ extern "C" { #endif /* XREG_CP15_CONTROL bit defines */ -#define XREG_CP15_CONTROL_TE_BIT 0x40000000 -#define XREG_CP15_CONTROL_AFE_BIT 0x20000000 -#define XREG_CP15_CONTROL_TRE_BIT 0x10000000 -#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000 -#define XREG_CP15_CONTROL_EE_BIT 0x02000000 -#define XREG_CP15_CONTROL_HA_BIT 0x00020000 -#define XREG_CP15_CONTROL_RR_BIT 0x00004000 -#define XREG_CP15_CONTROL_V_BIT 0x00002000 -#define XREG_CP15_CONTROL_I_BIT 0x00001000 -#define XREG_CP15_CONTROL_Z_BIT 0x00000800 -#define XREG_CP15_CONTROL_SW_BIT 0x00000400 -#define XREG_CP15_CONTROL_B_BIT 0x00000080 -#define XREG_CP15_CONTROL_C_BIT 0x00000004 -#define XREG_CP15_CONTROL_A_BIT 0x00000002 -#define XREG_CP15_CONTROL_M_BIT 0x00000001 +#define XREG_CP15_CONTROL_TE_BIT 0x40000000U +#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U +#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U +#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U +#define XREG_CP15_CONTROL_EE_BIT 0x02000000U +#define XREG_CP15_CONTROL_HA_BIT 0x00020000U +#define XREG_CP15_CONTROL_RR_BIT 0x00004000U +#define XREG_CP15_CONTROL_V_BIT 0x00002000U +#define XREG_CP15_CONTROL_I_BIT 0x00001000U +#define XREG_CP15_CONTROL_Z_BIT 0x00000800U +#define XREG_CP15_CONTROL_SW_BIT 0x00000400U +#define XREG_CP15_CONTROL_B_BIT 0x00000080U +#define XREG_CP15_CONTROL_C_BIT 0x00000004U +#define XREG_CP15_CONTROL_A_BIT 0x00000002U +#define XREG_CP15_CONTROL_M_BIT 0x00000001U #if defined (__GNUC__) || defined (__ICCARM__) /* C2 Register Defines */ diff --git a/lib/bsp/standalone/src/cortexa9/xtime_l.c b/lib/bsp/standalone/src/cortexa9/xtime_l.c old mode 100755 new mode 100644 index 611719bf..8b4401bd --- a/lib/bsp/standalone/src/cortexa9/xtime_l.c +++ b/lib/bsp/standalone/src/cortexa9/xtime_l.c @@ -78,18 +78,18 @@ * all processors, when this function called by any one processor. * ****************************************************************************/ -void XTime_SetTime(XTime Xtime) +void XTime_SetTime(XTime Xtime_Global) { /* Disable Global Timer */ - Xil_Out32(GLOBAL_TMR_BASEADDR + GTIMER_CONTROL_OFFSET, 0x0); + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0); /* Updating Global Timer Counter Register */ - Xil_Out32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime); - Xil_Out32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET, - (u32)(Xtime>>32)); + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global); + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET, + (u32)((u32)(Xtime_Global>>32U))); /* Enable Global Timer */ - Xil_Out32(GLOBAL_TMR_BASEADDR + GTIMER_CONTROL_OFFSET, 0x1); + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1); } /**************************************************************************** @@ -103,7 +103,7 @@ void XTime_SetTime(XTime Xtime) * @note None. * ****************************************************************************/ -void XTime_GetTime(XTime *Xtime) +void XTime_GetTime(XTime *Xtime_Global) { u32 low; u32 high; @@ -115,6 +115,6 @@ void XTime_GetTime(XTime *Xtime) low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET); } while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high); - *Xtime = (((XTime) high) << 32) | (XTime) low; + *Xtime_Global = (((XTime) high) << 32U) | (XTime) low; } diff --git a/lib/bsp/standalone/src/cortexa9/xtime_l.h b/lib/bsp/standalone/src/cortexa9/xtime_l.h old mode 100755 new mode 100644 index 84b7e846..046bd2ad --- a/lib/bsp/standalone/src/cortexa9/xtime_l.h +++ b/lib/bsp/standalone/src/cortexa9/xtime_l.h @@ -56,19 +56,21 @@ extern "C" { #endif /***************************** Include Files *********************************/ + +#include "xil_types.h" #include "xparameters.h" /***************** Macros (Inline Functions) Definitions *********************/ /**************************** Type Definitions *******************************/ -typedef unsigned long long XTime; +typedef u64 XTime; /************************** Constant Definitions *****************************/ #define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR -#define GTIMER_COUNTER_LOWER_OFFSET 0x00 -#define GTIMER_COUNTER_UPPER_OFFSET 0x04 -#define GTIMER_CONTROL_OFFSET 0x08 +#define GTIMER_COUNTER_LOWER_OFFSET 0x00U +#define GTIMER_COUNTER_UPPER_OFFSET 0x04U +#define GTIMER_CONTROL_OFFSET 0x08U /* Global Timer is always clocked at half of the CPU frequency */ @@ -77,8 +79,8 @@ typedef unsigned long long XTime; /************************** Function Prototypes ******************************/ -void XTime_SetTime(XTime Xtime); -void XTime_GetTime(XTime *Xtime); +void XTime_SetTime(XTime Xtime_Global); +void XTime_GetTime(XTime *Xtime_Global); #ifdef __cplusplus } diff --git a/lib/bsp/standalone/src/cortexr5/gcc/Makefile b/lib/bsp/standalone/src/cortexr5/gcc/Makefile new file mode 100644 index 00000000..74f162f8 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/Makefile @@ -0,0 +1,95 @@ +############################################################################### +# +# Copyright (C) 2014 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information of Xilinx, Inc. +# and is protected under U.S. and international copyright and other +# intellectual property laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any rights to the +# materials distributed herewith. Except as otherwise provided in a valid +# license issued to you by Xilinx, and to the maximum extent permitted by +# applicable law: +# (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +# XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +# OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +# NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +# and +# (2) Xilinx shall not be liable (whether in contract or tort, including +# negligence, or under any other theory of liability) for any loss or damage of +# any kind or nature related to, arising under or in connection with these +# materials, including for any direct, or any indirect, special, incidental, +# or consequential loss or damage (including loss of data, profits, goodwill, +# or any type of loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was reasonably foreseeable +# or Xilinx had been advised of the possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail-safe, or for use in +# any application requiring fail-safe performance, such as life-support or +# safety devices or systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any other applications +# that could lead to death, personal injury, or severe property or environmental +# damage (individually and collectively, "Critical Applications"). +# Customer assumes the sole risk and liability of any use of Xilinx products in +# Critical Applications, subject only to applicable laws and regulations +# governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +# AT ALL TIMES. +# +############################################################################### + +include config.make +AS=arm-none-eabi-as +CC=arm-none-eabi-gcc +AR=arm-none-eabi-ar +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +LIB=libxil.a + +CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS)) +ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS)) + +ifeq ($(COMPILER) , arm-eabi-gcc) + ECC_FLAGS = += -nostartfiles +endif + +#The following flags are required for PEEP. We can remove them later +ECC_FLAGS += -mcpu=cortex-r5 \ + -mfloat-abi=soft \ + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +INCLUDEFILES=*.h + +libs: $(LIBS) + +standalone_libs: $(LIBSOURCES) + echo "Compiling standalone" + $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^ + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + +profile_libs: + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" libs + +.PHONY: include +include: standalone_includes profile_includes + +standalone_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +profile_includes: + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" include + +clean: + rm -rf ${OUTS} + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" clean diff --git a/lib/bsp/standalone/src/cortexr5/gcc/_exit.c b/lib/bsp/standalone/src/cortexr5/gcc/_exit.c new file mode 100644 index 00000000..620dd74d --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/_exit.c @@ -0,0 +1,56 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +/* _exit - Simple implementation. Does not return. +*/ +__attribute__((weak)) void _exit (sint32 status) +{ + (void)status; + while (1) + { + __asm__("wfi"); + } +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/_open.c b/lib/bsp/standalone/src/cortexr5/gcc/_open.c new file mode 100644 index 00000000..d7ff29ff --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/_open.c @@ -0,0 +1,64 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode); +} +#endif + +/* + * _open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + */ +__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode) +{ + (void *)buf; + (void)flags; + (void)mode; + errno = EIO; + return (-1); +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/_sbrk.c b/lib/bsp/standalone/src/cortexr5/gcc/_sbrk.c new file mode 100644 index 00000000..f22c79c9 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/_sbrk.c @@ -0,0 +1,81 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +extern u8 _heap_start[]; +extern u8 _heap_end[]; + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) caddr_t _sbrk ( s32 incr ); +} +#endif + +__attribute__((weak)) caddr_t _sbrk ( s32 incr ) +{ + static u8 *heap = NULL; + u8 *prev_heap; + static u8 *HeapEndPtr = (u8 *)&_heap_end; + caddr_t Status; + + if (heap == NULL) { + heap = (u8 *)&_heap_start; + } + prev_heap = heap; + + heap += incr; + + if (heap > HeapEndPtr){ + Status = (caddr_t) -1; + } + else if (prev_heap != NULL) { + Status = (caddr_t) ((void *)prev_heap); + } + else { + Status = (caddr_t) -1; + } + + return Status; +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/abort.c b/lib/bsp/standalone/src/cortexr5/gcc/abort.c new file mode 100644 index 00000000..06f56828 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/abort.c @@ -0,0 +1,53 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include +#include + +/* + * abort -- go out via exit... + */ +__attribute__((weak)) void abort(void) +{ + _exit(1); +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/asm_vectors.S b/lib/bsp/standalone/src/cortexr5/gcc/asm_vectors.S new file mode 100644 index 00000000..8b3e36cb --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/asm_vectors.S @@ -0,0 +1,132 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file asm_vectors.s +* +* This file contains the initial vector table for the Cortex R5 processor +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp	02/10/14 Initial version
+*
+* +* @note +* +* None. +* +******************************************************************************/ +.org 0 +.text + +.globl _boot +.globl _vector_table + +.globl FIQInterrupt +.globl IRQInterrupt +.globl SWInterrupt +.globl DataAbortInterrupt +.globl PrefetchAbortInterrupt + +.globl IRQHandler +.globl prof_pc + +.section .vectors, "a" +_vector_table: + ldr pc,=_boot + ldr pc,=Undefined + ldr pc,=SVCHandler + ldr pc,=PrefetchAbortHandler + ldr pc,=DataAbortHandler + NOP /* Placeholder for address exception vector*/ + ldr pc,=IRQHandler + ldr pc,=FIQHandler + +.text +IRQHandler: /* IRQ vector handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/ + bl IRQInterrupt /* IRQ vector */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + subs pc, lr, #4 /* adjust return */ + +FIQHandler: /* FIQ vector handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ +FIQLoop: + bl FIQInterrupt /* FIQ vector */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + subs pc, lr, #4 /* adjust return */ + +Undefined: /* Undefined handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + b _prestart + movs pc, lr + +SVCHandler: /* SWI handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + tst r0, #0x20 /* check the T bit */ + ldrneh r0, [lr,#-2] /* Thumb mode */ + bicne r0, r0, #0xff00 /* Thumb mode */ + ldreq r0, [lr,#-4] /* ARM mode */ + biceq r0, r0, #0xff000000 /* ARM mode */ + bl SWInterrupt /* SWInterrupt: call C function here */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + movs pc, lr /* adjust return */ + +DataAbortHandler: /* Data Abort handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + subs pc, lr, #8 /* adjust return */ + +PrefetchAbortHandler: /* Prefetch Abort handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + subs pc, lr, #4 /* adjust return */ + + +.end diff --git a/lib/bsp/standalone/src/cortexr5/gcc/boot.S b/lib/bsp/standalone/src/cortexr5/gcc/boot.S new file mode 100644 index 00000000..e78f42c6 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/boot.S @@ -0,0 +1,204 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file boot.S +* +* This file contains the initial startup code for the Cortex R5 processor +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 pkp  02/10/14 Initial version
+*
+* +* @note +* +* None. +* +******************************************************************************/ + +#include "xparameters.h" + + +.global _prestart +.global _boot +.global __stack +.global __irq_stack +.global __supervisor_stack +.global __abort_stack +.global __fiq_stack +.global __undef_stack +.global _vector_table + + +/* Stack Pointer locations for boot code */ +.set Undef_stack, __undef_stack +.set FIQ_stack, __fiq_stack +.set Abort_stack, __abort_stack +.set SPV_stack, __supervisor_stack +.set IRQ_stack, __irq_stack +.set SYS_stack, __stack + +.set vector_base, _vector_table + +.section .boot,"axS" + + +/* this initializes the various processor modes */ + +_prestart: +_boot: + + + +OKToRun: + +/* Disable MPU and caches */ + mrc p15, 0, r0, c1, c0, 0 /* Read CP15 Control Register*/ + bic r0, r0, #0x05 /* Disable MPU (M bit) and data cache (C bit) */ + bic r0, r0, #0x1000 /* Disable instruction cache (I bit) */ + dsb /* Ensure all previous loads/stores have completed */ + mcr p15, 0, r0, c1, c0, 0 /* Write CP15 Control Register */ + isb /* Ensure subsequent insts execute wrt new MPU settings */ + +/* Disable Branch prediction */ + mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR */ + orr r0, r0, #(0x1 << 17) /* Enable RSDIS bit 17 to disable the return stack */ + orr r0, r0, #(0x1 << 16) /* Clear BP bit 15 and set BP bit 16:*/ + bic r0, r0, #(0x1 << 15) /* Branch always not taken and history table updates disabled*/ + mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ + dsb /* Complete all outstanding explicit memory operations*/ + +/* Invalidate caches */ + mov r0,#0 /* r0 = 0 */ + dsb + mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ + mcr p15, 0, r0, c15, c5, 0 /* Invalidate entire data cache*/ + isb + +/*TCM configuration*/ + ldr r0, =0x00000 /* Set ATCM base address*/ + orr r0, r0, #1 /* Enable it*/ + mcr p15, 0, r0, c9, c1, 1 /* Write ATCM Region Register*/ + + ldr r0, =0x20000 /* Set BTCM base address*/ + orr r0, r0, #1 /* Enable it*/ + mcr p15, 0, r0, c9, c1, 0 /* Write BTCM Region Register*/ + +/* Initialize stack pointer for various mode */ + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the irq stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x12 /* IRQ mode */ + msr cpsr, r2 + ldr r13,=IRQ_stack /* IRQ stack pointer */ + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the supervisor stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x13 /* supervisor mode */ + msr cpsr, r2 + ldr r13,=SPV_stack /* Supervisor stack pointer */ + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the Abort stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x17 /* Abort mode */ + msr cpsr, r2 + ldr r13,=Abort_stack /* Abort stack pointer */ + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the FIQ stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x11 /* FIQ mode */ + msr cpsr, r2 + ldr r13,=FIQ_stack /* FIQ stack pointer */ + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the Undefine stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x1b /* Undefine mode */ + msr cpsr, r2 + ldr r13,=Undef_stack /* Undefine stack pointer */ + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the system stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x1F /* SYS mode */ + msr cpsr, r2 + ldr r13,=SYS_stack /* SYS stack pointer */ + + bl Init_MPU /* Initialize MPU */ + +/*set exception vector to LOVEC */ + mrc p15, 0, r0, c1, c0, 0 + mvn r1, #0x2000 + and r0, r0, r1 + mcr p15, 0, r0, c1, c0, 0 + + +/* Enable icahce and dcache */ + mrc p15,0,r1,c1,c0,0 + ldr r0, =0x1004 + orr r1,r1,r0 + mcr p15,0,r1,c1,c0,0 /* Enable cache */ + dsb + isb /* isb flush prefetch buffer */ + +/* Enable Branch prediction */ + mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/ + bic r0, r0, #(0x1 << 17) /* Clear RSDIS bit 17 to enable return stack*/ + bic r0, r0, #(0x1 << 16) /* Clear BP bit 15 and BP bit 16:*/ + bic r0, r0, #(0x1 << 15) /* Normal operation, BP is taken from the global history table.*/ + mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ + + b _startup /* jump to C startup code */ + + +.Ldone: b .Ldone /* Paranoia: we should never get here */ + + +.end diff --git a/lib/bsp/standalone/src/cortexr5/gcc/close.c b/lib/bsp/standalone/src/cortexr5/gcc/close.c new file mode 100644 index 00000000..1c29fdc9 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/close.c @@ -0,0 +1,58 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _close(s32 fd); +} +#endif + +/* + * close -- We don't need to do anything, but pretend we did. + */ + +__attribute__((weak)) s32 _close(s32 fd) +{ + (void)fd; + return (0); +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/cpu_init.S b/lib/bsp/standalone/src/cortexr5/gcc/cpu_init.S new file mode 100644 index 00000000..f5ce7a9d --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/cpu_init.S @@ -0,0 +1,90 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file cpu_init.s +* +* This file contains CPU specific initialization. Invoked from main CRT +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp	02/10/14 Initial version
+*
+*
+* +* @note +* +* None. +* +******************************************************************************/ + + .text + .global __cpu_init + .align 2 +__cpu_init: + +/* Clear cp15 regs with unknown reset values */ + mov r0, #0x0 + mcr p15, 0, r0, c5, c0, 0 /* DFSR */ + mcr p15, 0, r0, c5, c0, 1 /* IFSR */ + mcr p15, 0, r0, c6, c0, 0 /* DFAR */ + mcr p15, 0, r0, c6, c0, 2 /* IFAR */ + mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */ + mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */ + mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */ + + +/* Reset and start Cycle Counter */ + mov r2, #0x80000000 /* clear overflow */ + mcr p15, 0, r2, c9, c12, 3 + mov r2, #0xd /* D, C, E */ + mcr p15, 0, r2, c9, c12, 0 + mov r2, #0x80000000 /* enable cycle counter */ + mcr p15, 0, r2, c9, c12, 1 + + bx lr + +.end diff --git a/lib/bsp/standalone/src/cortexr5/gcc/errno.c b/lib/bsp/standalone/src/cortexr5/gcc/errno.c new file mode 100644 index 00000000..fb28cf51 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/errno.c @@ -0,0 +1,62 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +/* The errno variable is stored in the reentrancy structure. This + function returns its address for use by the macro errno defined in + errno.h. */ + +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) sint32 * __errno (void); +} +#endif + +__attribute__((weak)) sint32 * +__errno (void) +{ + return &_REENT->_errno; +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/fcntl.c b/lib/bsp/standalone/src/cortexr5/gcc/fcntl.c new file mode 100644 index 00000000..70e5fcfa --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/fcntl.c @@ -0,0 +1,57 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +/* + * fcntl -- Manipulate a file descriptor. + * We don't have a filesystem, so we do nothing. + */ +__attribute__((weak)) s32 fcntl (s32 fd, s32 cmd, s32 arg) +{ + (void)fd; + (void)cmd; + (void)arg; + return 0; +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/fstat.c b/lib/bsp/standalone/src/cortexr5/gcc/fstat.c new file mode 100644 index 00000000..44a19c53 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/fstat.c @@ -0,0 +1,61 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf); +} +#endif +/* + * fstat -- Since we have no file system, we just return an error. + */ +__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf) +{ + (void)fd; + buf->st_mode = S_IFCHR; /* Always pretend to be a tty */ + + return (0); +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/getpid.c b/lib/bsp/standalone/src/cortexr5/gcc/getpid.c new file mode 100644 index 00000000..10d1c3ae --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/getpid.c @@ -0,0 +1,62 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include "xil_types.h" +/* + * getpid -- only one process, so just return 1. + */ +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _getpid(void); +} +#endif + +__attribute__((weak)) s32 getpid(void) +{ + return 1; +} + +__attribute__((weak)) s32 _getpid(void) +{ + return 1; +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/isatty.c b/lib/bsp/standalone/src/cortexr5/gcc/isatty.c new file mode 100644 index 00000000..b1be3e11 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/isatty.c @@ -0,0 +1,67 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) sint32 _isatty(sint32 fd); +} +#endif + +/* + * isatty -- returns 1 if connected to a terminal device, + * returns 0 if not. Since we're hooked up to a + * serial port, we'll say yes _AND return a 1. + */ +__attribute__((weak)) sint32 isatty(sint32 fd) +{ + (void)fd; + return (1); +} + +__attribute__((weak)) sint32 _isatty(sint32 fd) +{ + (void)fd; + return (1); +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/kill.c b/lib/bsp/standalone/src/cortexr5/gcc/kill.c new file mode 100644 index 00000000..62b303da --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/kill.c @@ -0,0 +1,71 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _kill(s32 pid, s32 sig); +} +#endif + +/* + * kill -- go out via exit... + */ + +__attribute__((weak)) s32 kill(s32 pid, s32 sig) +{ + if(pid == 1) { + _exit(sig); + } + return 0; +} + +__attribute__((weak)) s32 _kill(s32 pid, s32 sig) +{ + if(pid == 1) { + _exit(sig); + } + return 0; +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/lseek.c b/lib/bsp/standalone/src/cortexr5/gcc/lseek.c new file mode 100644 index 00000000..4aca2718 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/lseek.c @@ -0,0 +1,72 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence); +} +#endif +/* + * lseek -- Since a serial port is non-seekable, we return an error. + */ +__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence) +{ + (void)fd; + (void)offset; + (void)whence; + errno = ESPIPE; + return ((off_t)-1); +} + +__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence) +{ + (void)fd; + (void)offset; + (void)whence; + errno = ESPIPE; + return ((off_t)-1); +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/open.c b/lib/bsp/standalone/src/cortexr5/gcc/open.c new file mode 100644 index 00000000..878f069c --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/open.c @@ -0,0 +1,63 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode); +} +#endif +/* + * open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + */ +__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode) +{ + (void *)buf; + (void)flags; + (void)mode; + errno = EIO; + return (-1); +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/read.c b/lib/bsp/standalone/src/cortexr5/gcc/read.c new file mode 100644 index 00000000..66045a43 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/read.c @@ -0,0 +1,122 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +/* read.c -- read bytes from a input device. + */ + +#include "xparameters.h" +#include "xil_printf.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes); +} +#endif + +/* + * read -- read bytes from the serial port. Ignore fd, since + * we only have stdin. + */ +__attribute__((weak)) s32 +read (s32 fd, char8* buf, s32 nbytes) +{ +#ifdef STDIN_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + *LocalBuf = inbyte(); + if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) { + break; + } + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + + return (i + 1); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} + +__attribute__((weak)) s32 +_read (s32 fd, char8* buf, s32 nbytes) +{ +#ifdef STDIN_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + *LocalBuf = inbyte(); + if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) { + break; + } + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + + return (i + 1); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/sbrk.c b/lib/bsp/standalone/src/cortexr5/gcc/sbrk.c new file mode 100644 index 00000000..3002b8fd --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/sbrk.c @@ -0,0 +1,76 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) char8 *sbrk (s32 nbytes); +} +#endif + +extern u8 _heap_start[]; +extern u8 _heap_end[]; +extern char8 HeapBase[]; +extern char8 HeapLimit[]; + + + +__attribute__((weak)) char8 *sbrk (s32 nbytes) +{ + char8 *base; + static char8 *heap_ptr = HeapBase; + + base = heap_ptr; + if(heap_ptr != NULL) { + heap_ptr += nbytes; + } + +/* if (heap_ptr <= ((char8 *)&_heap_end + 1)) */ + if (heap_ptr <= ((char8 *)&HeapLimit + 1)) { + return base; + } else { + errno = ENOMEM; + return ((char8 *)-1); + } +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/unlink.c b/lib/bsp/standalone/src/cortexr5/gcc/unlink.c new file mode 100644 index 00000000..2a90f359 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/unlink.c @@ -0,0 +1,61 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) sint32 unlink(char8 *path); +} +#endif +/* + * unlink -- since we have no file system, + * we just return an error. + */ +__attribute__((weak)) sint32 unlink(char8 *path) +{ + (void *)path; + errno = EIO; + return (-1); +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/write.c b/lib/bsp/standalone/src/cortexr5/gcc/write.c new file mode 100644 index 00000000..59a97ad4 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/write.c @@ -0,0 +1,122 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +/* write.c -- write bytes to an output device. + */ + +#include "xparameters.h" +#include "xil_printf.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _write (s32 fd, char8* buf, s32 nbytes); +} +#endif + +/* + * write -- write bytes to the serial port. Ignore fd, since + * stdout and stderr are the same. Since we have no filesystem, + * open will only return an error. + */ +__attribute__((weak)) s32 +write (s32 fd, char8* buf, s32 nbytes) + +{ +#ifdef STDOUT_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + if (*LocalBuf == '\n') { + outbyte ('\r'); + } + outbyte (*LocalBuf); + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + return (nbytes); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} + +__attribute__((weak)) s32 +_write (s32 fd, char8* buf, s32 nbytes) +{ +#ifdef STDOUT_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + if (*LocalBuf == '\n') { + outbyte ('\r'); + } + outbyte (*LocalBuf); + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + return (nbytes); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/xil-crt0.S b/lib/bsp/standalone/src/cortexr5/gcc/xil-crt0.S new file mode 100644 index 00000000..fe30ca14 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/xil-crt0.S @@ -0,0 +1,125 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil-crt0.S +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/10/14 First release
+*
+* +* @note +* +* None. +* +******************************************************************************/ + + .file "xil-crt0.S" + .section ".got2","aw" + .align 2 + + .text +.Lsbss_start: + .long __sbss_start + +.Lsbss_end: + .long __sbss_end + +.Lbss_start: + .long __bss_start__ + +.Lbss_end: + .long __bss_end__ + +.Lstack: + .long __stack + + + .globl _startup + +_startup: + bl __cpu_init /* Initialize the CPU first (BSP provides this) */ + + mov r0, #0 + + /* clear sbss */ + ldr r1,.Lsbss_start /* calculate beginning of the SBSS */ + ldr r2,.Lsbss_end /* calculate end of the SBSS */ + +.Lloop_sbss: + cmp r1,r2 + bge .Lenclsbss /* If no SBSS, no clearing required */ + str r0, [r1], #4 + b .Lloop_sbss + +.Lenclsbss: + /* clear bss */ + ldr r1,.Lbss_start /* calculate beginning of the BSS */ + ldr r2,.Lbss_end /* calculate end of the BSS */ + +.Lloop_bss: + cmp r1,r2 + bge .Lenclbss /* If no BSS, no clearing required */ + str r0, [r1], #4 + b .Lloop_bss + +.Lenclbss: + + /* set stack pointer */ + ldr r13,.Lstack /* stack address */ + + bl Init_Uart /* Initialize UART */ + + bl main /* Jump to main C code */ + + bl _exit + +.Lexit: /* should never get here */ + b .Lexit + +.Lstart: + .size _startup,.Lstart-_startup diff --git a/lib/bsp/standalone/src/cortexr5/gcc/xpseudo_asm_gcc.h b/lib/bsp/standalone/src/cortexr5/gcc/xpseudo_asm_gcc.h new file mode 100644 index 00000000..de65c73e --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/xpseudo_asm_gcc.h @@ -0,0 +1,186 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_gcc.h +* +* This header file contains macros for using inline assembler code. It is +* written specifically for the GNU compiler. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+*
+* +******************************************************************************/ + +#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_GCC_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* necessary for pre-processor */ +#define stringify(s) tostring(s) +#define tostring(s) #s + +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval; \ + __asm__ __volatile__(\ + "mrs %0, cpsr\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__(\ + "msr cpsr,%0\n"\ + : : "r" (v)\ + ) + +#define cpsiei() __asm__ __volatile__("cpsie i\n") +#define cpsidi() __asm__ __volatile__("cpsid i\n") + +#define cpsief() __asm__ __volatile__("cpsie f\n") +#define cpsidf() __asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) __asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) + +#define mfgpr(rn) ({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb" : : : "memory") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") + + +/* Memory Operations */ +#define ldr(adr) ({u32 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define ldrb(adr) ({u8 rval; \ + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define str(adr, val) __asm__ __volatile__(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +#define strb(adr, val) __asm__ __volatile__(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +/* Count leading zeroes (clz) */ +#define clz(arg) ({u8 rval; \ + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) + +/* CP15 operations */ +#define mtcp(rn, v) __asm__ __volatile__(\ + "mcr " rn "\n"\ + : : "r" (v)\ + ); + +#define mfcp(rn) ({u32 rval; \ + __asm__ __volatile__(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XPSEUDO_ASM_GCC_H */ diff --git a/lib/bsp/standalone/src/cortexr5/mpu.c b/lib/bsp/standalone/src/cortexr5/mpu.c new file mode 100644 index 00000000..bfe0df4a --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/mpu.c @@ -0,0 +1,130 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file mpu.c +* +* This file contains initial configuration of the MPU. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+*
+* +* @note +* +* None. +* +******************************************************************************/ + +#include "xil_mpu.h" +#include "xil_types.h" +#include "xreg_cortexr5.h" +#include "xparameters.h" + +void Init_MPU(void); + +void Init_MPU(void) +{ + + u32 addr, reg_size, attrib, reg; + s32 reg_num; + + addr = 0xFFFF0000U; + reg_size = REGION_64K; + reg_num = 0; + attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW; + Xil_SetAttribute(addr,reg_size,reg_num, attrib); + + addr = 0xFFFC0000U; + reg_size = REGION_128K; + reg_num = 1; + attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW ; + Xil_SetAttribute(addr,reg_size,reg_num, attrib); + + addr = 0xFFFE0000U; + reg_size = REGION_64K; + reg_num = 2; + attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ; + Xil_SetAttribute(addr,reg_size,reg_num, attrib); + + addr = 0xFD000000U; + reg_size = REGION_4M; + reg_num = 3; + attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(addr,reg_size,reg_num, attrib); + + addr = 0xFEC00000U; + reg_size = REGION_4M; + reg_num = 4; + attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(addr,reg_size,reg_num, attrib); + + + addr = 0xFF000000U; + reg_size = REGION_4M; + reg_num = 5; + attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(addr,reg_size,reg_num, attrib); + + + addr = 0xFF400000U; + reg_size = REGION_4M; + reg_num = 6; + attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(addr,reg_size,reg_num, attrib); + + + addr = 0xFF800000U; + reg_size = REGION_4M; + reg_num = 7; + attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(addr,reg_size,reg_num, attrib); + + Xil_EnableBackgroundRegion(); + Xil_EnableMPU(); + +} diff --git a/lib/bsp/standalone/src/cortexr5/print.c b/lib/bsp/standalone/src/cortexr5/print.c new file mode 100644 index 00000000..31d7b198 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/print.c @@ -0,0 +1,32 @@ +/* print.c -- print a string on the output device. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * + */ + +/* + * print -- do a raw print of a string + */ +#include "xil_printf.h" + +void print(const char8 *ptr) +{ +#ifdef STDOUT_BASEADDRESS + while (*ptr != (char8)0) { + outbyte (*ptr); + *ptr++; + } +#else +(void)ptr; +#endif +} diff --git a/lib/bsp/standalone/src/cortexr5/putnum.c b/lib/bsp/standalone/src/cortexr5/putnum.c new file mode 100644 index 00000000..86d3a74e --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/putnum.c @@ -0,0 +1,59 @@ +/* putnum.c -- put a hex number on the output device. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +/* + * putnum -- print a 32 bit number in hex + */ + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Function Prototypes ******************************/ +extern void print (const char8 *ptr); +void putnum(u32 num); + +void putnum(u32 num) +{ + char8 buf[9]; + u32 cnt; + s32 i; + char8 *ptr; + u32 digit; + for(i = 0; i<9; i++) { + buf[i] = '0'; + } + + ptr = buf; + for (cnt = 7U ; cnt >= 0U ; cnt--) { + digit = (num >> (cnt * 4U)) & 0x0000000fU; + + if ((digit <= 9U) && (ptr != NULL)) { + digit += (u32)'0'; + *ptr = ((char8) digit); + ptr += 1; + } else if (ptr != NULL) { + digit += ((u32)'a' - (u32)10); + *ptr = ((char8)digit); + ptr += 1; + } else { + /*Made for MisraC Compliance*/; + } + } + + if(ptr != NULL) { + *ptr = (char8) 0; + } + print (buf); +} diff --git a/lib/bsp/standalone/src/cortexr5/sleep.c b/lib/bsp/standalone/src/cortexr5/sleep.c new file mode 100644 index 00000000..e65a544c --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/sleep.c @@ -0,0 +1,108 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/***************************************************************************** +* +* @file sleep.c +* +* This function provides a second delay using the Global Timer register in +* the ARM Cortex R5 MP core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 02/20/14 First release
+*
+* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "sleep.h" +#include "xtime_l.h" +#include "xparameters.h" + +/*****************************************************************************/ +/* +* +* This API is used to provide delays in seconds. Maximum value of seconds +* attained with sleep routine is 10995 +* +* @param seconds requested +* +* @return 0 always +* +* @note None. +* +****************************************************************************/ + +s32 sleep(u32 seconds) +{ + + XTime tEnd, tCur; + + /* Disable ttc Timer */ + Xil_Out32(TTC3_BASEADDR + 0x0000000CU,0x00000001U); + /*set prescale value*/ + Xil_Out32(TTC3_BASEADDR + 0x00000000U,0x0000000DU); + /*write interval value to register*/ + Xil_Out32(TTC3_BASEADDR + 0x00000024U,0xFFFFFFFFU); + /*write match value to register*/ + Xil_Out32(TTC3_BASEADDR + 0x00000030U,0xFFFFFFFFU); + /* Enable ttc Timer */ + Xil_Out32(TTC3_BASEADDR + 0x0000000CU,0x0000001AU); + + XTime_GetTime(&tCur); + + tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND); + do + { + XTime_GetTime(&tCur); + + } while (tCur < tEnd); + + /* Disable ttc Timer */ + Xil_Out32(TTC3_BASEADDR + 0x0000000CU, Xil_In32(TTC3_BASEADDR + 0x0000000CU) | 0x00000001U); + + return 0; +} diff --git a/lib/bsp/standalone/src/cortexr5/sleep.h b/lib/bsp/standalone/src/cortexr5/sleep.h new file mode 100644 index 00000000..4200f9d4 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/sleep.h @@ -0,0 +1,60 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +#ifndef SLEEP_H +#define SLEEP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xil_types.h" +#include "xil_io.h" + +s32 usleep(u32 useconds); +s32 sleep(u32 seconds); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/cortexr5/uart.c b/lib/bsp/standalone/src/cortexr5/uart.c new file mode 100644 index 00000000..5d589ad9 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/uart.c @@ -0,0 +1,171 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file uart.c +* +* This file contains APIs for configuring the UART. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+*
+* +* @note +* +* None. +* +******************************************************************************/ + +#include "xil_types.h" +#include "xparameters.h" +#include "xil_assert.h" +#include "xil_io.h" + +/* Register offsets */ +#define UART_CR_OFFSET 0x00000000U +#define UART_MR_OFFSET 0x00000004U +#define UART_BAUDGEN_OFFSET 0x00000018U +#define UART_BAUDDIV_OFFSET 0x00000034U + +#define MAX_BAUD_ERROR_RATE 0x00000003U /* max % error allowed */ +#define UART_BAUDRATE 115200U +#define CSU_VERSION_REG 0xFFCA0044U + +void Init_Uart(void); + +void Init_Uart(void) +{ +#ifdef STDOUT_BASEADDRESS + u8 IterBAUDDIV; /* Iterator for available baud divisor values */ + u32 BRGR_Value; /* Calculated value for baud rate generator */ + u32 CalcBaudRate; /* Calculated baud rate */ + u32 BaudError; /* Diff between calculated and requested baud rate */ + u32 Best_BRGR = 0U; /* Best value for baud rate generator */ + u8 Best_BAUDDIV = 0U; /* Best value for baud divisor */ + u32 Best_Error = 0xFFFFFFFFU; + u32 PercentError; + u32 InputClk; + u32 BaudRate = UART_BAUDRATE; + +#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR) + InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ; +#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR) + InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ; +#else + /* STDIO is not set or axi_uart is being used for STDIO */ + return; +#endif +InputClk = 25000000U; + /* + * Determine the Baud divider. It can be 4to 254. + * Loop through all possible combinations + */ + for (IterBAUDDIV = 4U; IterBAUDDIV < 255U; IterBAUDDIV++) { + + /* + * Calculate the value for BRGR register + */ + BRGR_Value = InputClk / (BaudRate * ((u32)IterBAUDDIV + 0x00000001U)); + + /* + * Calculate the baud rate from the BRGR value + */ + CalcBaudRate = InputClk/ (BRGR_Value * ((u32)IterBAUDDIV + 0x00000001U)); + + /* + * Avoid unsigned integer underflow + */ + if (BaudRate > CalcBaudRate) { + BaudError = BaudRate - CalcBaudRate; + } else { + BaudError = CalcBaudRate - BaudRate; + } + + /* + * Find the calculated baud rate closest to requested baud rate. + */ + if (Best_Error > BaudError) { + + Best_BRGR = BRGR_Value; + Best_BAUDDIV = IterBAUDDIV; + Best_Error = BaudError; + + } + } + + /* + * Make sure the best error is not too large. + */ + PercentError = (Best_Error * 100U) / BaudRate; + if (MAX_BAUD_ERROR_RATE < PercentError) { + return; + } + + /* set CD and BDIV */ + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR); + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, (u32)Best_BAUDDIV); + + /* + * Veloce specific code + */ + if((Xil_In32(CSU_VERSION_REG) & 0x0000F000U) == 0x00002000U ) { + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, 0x00000002U); + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, 0x00000004U); + } + + /* + * 8 data, 1 stop, 0 parity bits + * sel_clk=uart_clk=APB clock + */ + Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x00000020U); + + /* enable Tx/Rx and reset Tx/Rx data path */ + Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x00000017U); + + return; +#endif +} diff --git a/lib/bsp/standalone/src/cortexr5/usleep.c b/lib/bsp/standalone/src/cortexr5/usleep.c new file mode 100644 index 00000000..f8955b6c --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/usleep.c @@ -0,0 +1,112 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file usleep.c +* +* This function provides a microsecond delay using the Global Timer register in +* the ARM Cortex R5 MP core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+*
+* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "sleep.h" +#include "xtime_l.h" +#include "xparameters.h" +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "xreg_cortexr5.h" + +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_USECOND 25U + +/*****************************************************************************/ +/** +* +* This API gives a delay in microseconds +* +* @param useconds requested +* +* @return 0 if the delay can be achieved, -1 if the requested delay +* is out of range +* +* @note None. +* +****************************************************************************/ + +s32 usleep(u32 useconds) +{ + XTime tEnd, tCur; + /*disable ttc timer*/ + Xil_Out32(TTC3_BASEADDR + 0x0000000CU,0x1U); + /*set prescale value*/ + Xil_Out32(TTC3_BASEADDR + 0x00000000U, 0x000001U); + /*write interval value to register*/ + Xil_Out32(TTC3_BASEADDR + 0x00000024U,0xFFFFFFFFU); + /*write match value to register*/ + Xil_Out32(TTC3_BASEADDR + 0x00000030U,0xFFFFFFFFU); + /* Enable ttc Timer */ + Xil_Out32(TTC3_BASEADDR + 0x0000000CU,0x1AU); + + XTime_GetTime(&tCur); + + tEnd = tCur + (((XTime) useconds) * (COUNTS_PER_USECOND)); + do + { + XTime_GetTime(&tCur); + } while (tCur < tEnd); + + /* Disable ttc Timer */ + Xil_Out32(TTC3_BASEADDR + 0x0000000CU, Xil_In32(TTC3_BASEADDR + 0x0000000CU) | 0x00000001U); + + return 0; +} diff --git a/lib/bsp/standalone/src/cortexr5/vectors.c b/lib/bsp/standalone/src/cortexr5/vectors.c new file mode 100644 index 00000000..eafb303b --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/vectors.c @@ -0,0 +1,179 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file vectors.c +* +* This file contains the C level vectors for the ARM Cortex R5 core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+*
+* +* @note +* +* None. +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xil_exception.h" +#include "vectors.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +typedef struct { + Xil_ExceptionHandler Handler; + void *Data; +} XExc_VectorTableEntry; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +extern XExc_VectorTableEntry XExc_VectorTable[]; + +/************************** Function Prototypes ******************************/ + + + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the FIQ interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void FIQInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_FIQ_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the IRQ interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void IRQInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_IRQ_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the SW Interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void SWInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_SWI_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the DataAbort Interrupt called from the +* vectors.s file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void DataAbortInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the PrefetchAbort Interrupt called from the +* vectors.s file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void PrefetchAbortInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data); +} diff --git a/lib/bsp/standalone/src/cortexr5/vectors.h b/lib/bsp/standalone/src/cortexr5/vectors.h new file mode 100644 index 00000000..abc01bb8 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/vectors.h @@ -0,0 +1,92 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file vectors.h +* +* This file contains the C level vector prototypes for the ARM Cortex R5 core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+*
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef VECTORS_H_ +#define VECTORS_H_ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +void FIQInterrupt(void); +void IRQInterrupt(void); +void SWInterrupt(void); +void DataAbortInterrupt(void); +void PrefetchAbortInterrupt(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/lib/bsp/standalone/src/cortexr5/xil_cache.c b/lib/bsp/standalone/src/cortexr5/xil_cache.c new file mode 100644 index 00000000..f585d2da --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_cache.c @@ -0,0 +1,595 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache.c +* +* Contains required functions for the ARM cache functionality. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xil_io.h" +#include "xpseudo_asm.h" +#include "xparameters.h" +#include "xreg_cortexr5.h" +#include "xil_exception.h" + + +/************************** Variable Definitions *****************************/ + +#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */ + + +extern s32 _stack_end; +extern s32 _stack; + +/****************************************************************************/ +/************************** Function Prototypes ******************************/ + +/**************************************************************************** +* +* Enable the Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheEnable(void) +{ + register u32 CtrlReg; + + /* enable caches only if they are disabled */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + + if ((CtrlReg & XREG_CP15_CONTROL_C_BIT)==0x00000000U) { + /* invalidate the Data cache */ + Xil_DCacheInvalidate(); + + /* enable the Data cache */ + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + } +} + +/**************************************************************************** +* +* Disable the Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheDisable(void) +{ + register u32 CtrlReg; + + /* clean and invalidate the Data cache */ + Xil_DCacheFlush(); + + /* disable the Data cache */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/**************************************************************************** +* +* Invalidate the entire Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheInvalidate(void) +{ + u32 currmask; + u32 stack_start,stack_end,stack_size; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + + stack_end = (u32 )&_stack_end; + stack_start = (u32 )&_stack; + stack_size=stack_start-stack_end; + + /*Flush stack memory to save return address*/ + Xil_DCacheFlushRange(stack_end, stack_size); + + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + + /*invalidate all D cache*/ + mtcp(XREG_CP15_INVAL_DC_ALL, 0); + + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Invalidate a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the modified contents +* are lost and are NOT written to system memory before the line is +* invalidated. +* +* @param Address to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheInvalidateLine(INTPTR adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); + + /* Wait for invalidate to complete */ + dsb(); + + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Invalidate the Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the modified contents are lost and are NOT +* written to system memory before the line is invalidated. +* +* @param Start address of range to be invalidated. +* @param Length of range to be invalidated in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) +{ + const u32 cacheline = 32U; + u32 end; + u32 tempadr = adr; + u32 tempend; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + end = tempadr + len; + tempend = end; + /* Select L1 Data cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + + if ((tempadr & (cacheline-1U)) != 0U) { + tempadr &= (~(cacheline - 1U)); + + Xil_DCacheFlushLine(tempadr); + } + if ((tempend & (cacheline-1U)) != 0U) { + tempend &= (~(cacheline - 1U)); + + Xil_DCacheFlushLine(tempend); + } + + while (tempadr < tempend) { + + /* Invalidate Data cache line */ + __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (tempadr)); + + tempadr += cacheline; + } + } + + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Flush the entire Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheFlush(void) +{ + register u32 CsidReg, C7Reg; + u32 CacheSize, LineSize, NumWays; + u32 Way, WayIndex, Set, SetIndex, NumSet; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + /* Select cache level 0 and D cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + + CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); + + /* Determine Cache Size */ + + CacheSize = (CsidReg >> 13U) & 0x000001FFU; + CacheSize += 0x00000001U; + CacheSize *= (u32)128; /* to get number of bytes */ + + /* Number of Ways */ + NumWays = (CsidReg & 0x000003ffU) >> 3U; + NumWays += 0x00000001U; + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x00000007U) + 0x00000004U; + + NumSet = CacheSize/NumWays; + NumSet /= (0x00000001U << LineSize); + + Way = 0U; + Set = 0U; + + /* Invalidate all the cachelines */ + for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set; + /* Flush by Set/Way */ + __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (C7Reg)); + + Set += (0x00000001U << LineSize); + } + Set = 0U; + Way += 0x40000000U; + } + + /* Wait for flush to complete */ + dsb(); + mtcpsr(currmask); + + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Flush a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the entire +* contents of the cacheline are written to system memory before the +* line is invalidated. +* +* @param Address to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheFlushLine(INTPTR adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + + mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); + + /* Wait for flush to complete */ + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* Flush the Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the written to system memory first before the +* before the line is invalidated. +* +* @param Start address of range to be flushed. +* @param Length of range to be flushed in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheFlushRange(INTPTR adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0x00000000U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr &= ~(cacheline - 1U); + + while (LocalAddr < end) { + /* Flush Data cache line */ + __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (LocalAddr)); + + LocalAddr += cacheline; + } + } + dsb(); + mtcpsr(currmask); +} +/**************************************************************************** +* +* Store a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache and the cacheline is modified (dirty), +* the entire contents of the cacheline are written to system memory. +* After the store completes, the cacheline is marked as unmodified +* (not dirty). +* +* @param Address to be stored. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheStoreLine(INTPTR adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F))); + + /* Wait for store to complete */ + dsb(); + isb(); + + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Enable the instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheEnable(void) +{ + register u32 CtrlReg; + + /* enable caches only if they are disabled */ + + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + + if ((CtrlReg & XREG_CP15_CONTROL_I_BIT)==0x00000000U) { + /* invalidate the instruction cache */ + mtcp(XREG_CP15_INVAL_IC_POU, 0); + + /* enable the instruction cache */ + CtrlReg |= (XREG_CP15_CONTROL_I_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + } +} + +/**************************************************************************** +* +* Disable the instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheDisable(void) +{ + register u32 CtrlReg; + + dsb(); + + /* invalidate the instruction cache */ + mtcp(XREG_CP15_INVAL_IC_POU, 0); + + /* disable the instruction cache */ + + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + + CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/**************************************************************************** +* +* Invalidate the entire instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheInvalidate(void) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); + + /* invalidate the instruction cache */ + mtcp(XREG_CP15_INVAL_IC_POU, 0); + + /* Wait for invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Invalidate an instruction cache line. If the instruction specified by the +* parameter adr is cached by the instruction cache, the cacheline containing +* that instruction is invalidated. +* +* @param None. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_ICacheInvalidateLine(INTPTR adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); + mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F))); + + /* Wait for invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Invalidate the instruction cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the modified contents are lost and are NOT +* written to system memory before the line is invalidated. +* +* @param Start address of range to be invalidated. +* @param Length of range to be invalidated in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + if (len != 0x00000000U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + /* Select cache L0 I-cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); + + while (LocalAddr < end) { + + /* Invalidate L1 I-cache line */ + __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (LocalAddr)); + + LocalAddr += cacheline; + } + } + + /* Wait for invalidate to complete */ + dsb(); + mtcpsr(currmask); +} diff --git a/lib/bsp/standalone/src/cortexr5/xil_cache.h b/lib/bsp/standalone/src/cortexr5/xil_cache.h new file mode 100644 index 00000000..2cad1d6a --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_cache.h @@ -0,0 +1,88 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache.h +* +* Contains required functions for the ARM cache functionality +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+*
+* +******************************************************************************/ +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void Xil_DCacheEnable(void); +void Xil_DCacheDisable(void); +void Xil_DCacheInvalidate(void); +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len); +void Xil_DCacheFlush(void); +void Xil_DCacheFlushRange(INTPTR adr, u32 len); +void Xil_DCacheInvalidateLine(INTPTR adr); +void Xil_DCacheFlushLine(INTPTR adr); +void Xil_DCacheStoreLine(INTPTR adr); + +void Xil_ICacheEnable(void); +void Xil_ICacheDisable(void); +void Xil_ICacheInvalidate(void); +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len); +void Xil_ICacheInvalidateLine(INTPTR adr); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/cortexr5/xil_exception.c b/lib/bsp/standalone/src/cortexr5/xil_exception.c new file mode 100644 index 00000000..177cda5e --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_exception.c @@ -0,0 +1,229 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xil_exception.c +* +* This file contains low-level driver functions for the Cortex R5 exception +* Handler. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 02/20/14 First release
+*
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_exception.h" +#include "xpseudo_asm.h" +#include "xdebug.h" +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +typedef struct { + Xil_ExceptionHandler Handler; + void *Data; +} XExc_VectorTableEntry; + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Function Prototypes *****************************/ +static void Xil_ExceptionNullHandler(void *Data); +/************************** Variable Definitions *****************************/ +/* + * Exception vector table to store handlers for each exception vector. + */ +XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = +{ + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_PrefetchAbortHandler, NULL}, + {Xil_DataAbortHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, +}; + +/*****************************************************************************/ + +/****************************************************************************/ +/** +* +* This function is a stub Handler that is the default Handler that gets called +* if the application has not setup a Handler for a specific exception. The +* function interface has to match the interface specified for a Handler even +* though none of the arguments are used. +* +* @param Data is unused by this function. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +static void Xil_ExceptionNullHandler(void *Data) +{ + (void *)Data; +DieLoop: goto DieLoop; +} + +/****************************************************************************/ +/** +* The function is a common API used to initialize exception handlers across all +* processors supported. For ARM CortexR5, the exception handlers are being +* initialized statically and hence this function does not do anything. +* +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xil_ExceptionInit(void) +{ + return; +} + +/*****************************************************************************/ +/** +* +* Makes the connection between the Id of the exception source and the +* associated Handler that is to run when the exception is recognized. The +* argument provided in this call as the Data is used as the argument +* for the Handler when it is called. +* +* @param exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. + See xil_exception_l.h for further information. +* @param Handler to the Handler for that exception. +* @param Data is a reference to Data that will be passed to the +* Handler when it gets called. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data) +{ + XExc_VectorTable[Exception_id].Handler = Handler; + XExc_VectorTable[Exception_id].Data = Data; +} + +/*****************************************************************************/ +/** +* +* Removes the Handler for a specific exception Id. The stub Handler is then +* registered for this exception Id. +* +* @param exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception_l.h for further information. + +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ExceptionRemoveHandler(u32 Exception_id) +{ + Xil_ExceptionRegisterHandler(Exception_id, + Xil_ExceptionNullHandler, + NULL); +} +/*****************************************************************************/ +/** +* +* Default Data abort handler which prints a debug message on console if +* Debug flag is enabled +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ + +void Xil_DataAbortHandler(void *CallBackRef){ + + xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n"); + while(1) { + ; + } +} + +/*****************************************************************************/ +/** +* +* Default Prefetch abort handler which printsa debug message on console if +* Debug flag is enabled +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_PrefetchAbortHandler(void *CallBackRef){ + + xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n"); + while(1) { + ; + } +} diff --git a/lib/bsp/standalone/src/cortexr5/xil_exception.h b/lib/bsp/standalone/src/cortexr5/xil_exception.h new file mode 100644 index 00000000..69134399 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_exception.h @@ -0,0 +1,241 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* This header file contains ARM Cortex R5 specific exception related APIs. +* For exception related functions that can be used across all Xilinx supported +* processors, please use xil_exception.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+*
+* +******************************************************************************/ + +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions ****************************/ + +#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE +#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE +#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) + +#define XIL_EXCEPTION_ID_FIRST 0U +#define XIL_EXCEPTION_ID_RESET 0U +#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U +#define XIL_EXCEPTION_ID_SWI_INT 2U +#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U +#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U +#define XIL_EXCEPTION_ID_IRQ_INT 5U +#define XIL_EXCEPTION_ID_FIQ_INT 6U +#define XIL_EXCEPTION_ID_LAST 6U + +/* + * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. + */ +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT + +/**************************** Type Definitions ******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *data); +typedef void (*Xil_InterruptHandler)(void *data); + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Enable Exceptions. +* +* @param Mask for exceptions to be enabled. +* +* @return None. +* +* @note If bit is 0, exception is enabled. +* C-Style signature: void Xil_ExceptionEnableMask(Mask) +* +******************************************************************************/ +#ifdef __GNUC__ +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionEnableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \ + } +#endif + +/****************************************************************************/ +/** +* Enable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) + +/****************************************************************************/ +/** +* Disable Exceptions. +* +* @param Mask for exceptions to be enabled. +* +* @return None. +* +* @note If bit is 1, exception is disabled. +* C-Style signature: Xil_ExceptionDisableMask(Mask) +* +******************************************************************************/ +#ifdef __GNUC__ +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionDisableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \ + } +#endif + +/****************************************************************************/ +/** +* Disable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionDisable() \ + Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) + +/****************************************************************************/ +/** +* Enable nested interrupts by clearing the I and F bits it CPSR +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I and F +* are 1). To allow nesting of interrupts, this macro should be +* used. It clears the I and F bits by changing the ARM mode to +* system mode. Once these bits are cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I and +* F bits, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("mrs lr, spsr"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); + +/****************************************************************************/ +/** +* Disable the nested interrupts by setting the I and F bits. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ/FIQ mode and +* hence sets back the I and F bits. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x92"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr spsr_cxsf, lr"); + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +extern void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data); + +extern void Xil_ExceptionRemoveHandler(u32 Exception_id); + +extern void Xil_ExceptionInit(void); + +extern void Xil_DataAbortHandler(void *CallBackRef); + +extern void Xil_PrefetchAbortHandler(void *CallBackRef); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_EXCEPTION_H */ diff --git a/lib/bsp/standalone/src/cortexr5/xil_io.c b/lib/bsp/standalone/src/cortexr5/xil_io.c new file mode 100644 index 00000000..b0469d99 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_io.c @@ -0,0 +1,391 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.c +* +* Contains I/O functions for memory-mapped or non-memory-mapped I/O +* architectures. These functions encapsulate Cortex R5 architecture-specific +* I/O requirements. +* +* @note +* +* This file contains architecture-dependent code. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 02/20/14 First release
+*
+******************************************************************************/ + + +/***************************** Include Files *********************************/ +#include "xil_io.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xpseudo_asm.h" +#include "xreg_cortexr5.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* Performs an input operation for an 8-bit memory location by reading from the +* specified address and returning the Value read from that address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u8 Xil_In8(INTPTR Addr) +{ + return *(volatile u8 *) Addr; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 16-bit memory location by reading from the +* specified address and returning the Value read from that address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u16 Xil_In16(INTPTR Addr) +{ + return *(volatile u16 *) Addr; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 32-bit memory location by reading from the +* specified address and returning the Value read from that address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u32 Xil_In32(INTPTR Addr) +{ + return *(volatile u32 *) Addr; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for an 8-bit memory location by writing the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out8(INTPTR Addr, u8 Value) +{ + u8 *LocalAddr = (u8 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 16-bit memory location by writing the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out16(INTPTR Addr, u16 Value) +{ + u16 *LocalAddr = (u16 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 32-bit memory location by writing the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out32(INTPTR Addr, u32 Value) +{ + u32 *LocalAddr = (u32 *)Addr; + *LocalAddr = Value; +} +/*****************************************************************************/ +/** +* +* Performs an output operation for a 64-bit memory location by writing the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out64(INTPTR Addr, u64 Value) +{ + u64 *LocalAddr = (u64 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 64-bit memory location by reading the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +u64 Xil_In64(INTPTR Addr) +{ + return *(volatile u64 *) Addr; +} +/*****************************************************************************/ +/** +* +* Performs an input operation for a 16-bit memory location by reading from the +* specified address and returning the byte-swapped Value read from that +* address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The byte-swapped Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u16 Xil_In16BE(INTPTR Addr) +{ + u16 temp; + u16 result; + + temp = Xil_In16(Addr); + + result = Xil_EndianSwap16(temp); + + return result; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 32-bit memory location by reading from the +* specified address and returning the byte-swapped Value read from that +* address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The byte-swapped Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u32 Xil_In32BE(INTPTR Addr) +{ + u32 temp; + u32 result; + + temp = Xil_In32(Addr); + + result = Xil_EndianSwap32(temp); + + return result; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 16-bit memory location by writing the +* specified Value to the the specified address. The Value is byte-swapped +* before being written. +* +* @param OutAddress contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out16BE(INTPTR Addr, u16 Value) +{ + u16 temp; + + temp = Xil_EndianSwap16(Value); + + Xil_Out16(Addr, temp); +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 32-bit memory location by writing the +* specified Value to the the specified address. The Value is byte-swapped +* before being written. +* +* @param OutAddress contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out32BE(INTPTR Addr, u32 Value) +{ + u32 temp; + + temp = Xil_EndianSwap32(Value); + + Xil_Out32(Addr, temp); +} + +/*****************************************************************************/ +/** +* +* Perform a 16-bit endian converion. +* +* @param Data contains the value to be converted. +* +* @return converted value. +* +* @note None. +* +******************************************************************************/ +u16 Xil_EndianSwap16(u16 Data) +{ + return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U)); +} + +/*****************************************************************************/ +/** +* +* Perform a 32-bit endian converion. +* +* @param Data contains the value to be converted. +* +* @return converted value. +* +* @note None. +* +******************************************************************************/ +u32 Xil_EndianSwap32(u32 Data) +{ + u16 LoWord; + u16 HiWord; + + /* get each of the half words from the 32 bit word */ + + LoWord = (u16) (Data & 0x0000FFFFU); + HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U); + + /* byte swap each of the 16 bit half words */ + + LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U)); + HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U)); + + /* swap the half words before returning the value */ + + return ((((u32)LoWord) << 16U) | (u32)HiWord); +} diff --git a/lib/bsp/standalone/src/cortexr5/xil_io.h b/lib/bsp/standalone/src/cortexr5/xil_io.h new file mode 100644 index 00000000..35428c7d --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_io.h @@ -0,0 +1,255 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.h +* +* This file contains the interface for the general IO component, which +* encapsulates the Input/Output functions for processors that do not +* require any special I/O handling. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 02/20/14 First release
+*
+******************************************************************************/ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "xil_printf.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#if defined __GNUC__ +# define SYNCHRONIZE_IO dmb() +# define INST_SYNC isb() +# define DATA_SYNC dsb() +#else +# define SYNCHRONIZE_IO +# define INST_SYNC +# define DATA_SYNC +#endif /* __GNUC__ */ + +/*****************************************************************************/ +/** +* +* Perform an big-endian input operation for a 16-bit memory location +* by reading from the specified address and returning the Value read from +* that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The Value read from the specified input address with the +* proper endianness. The return Value has the same endianness +* as that of the processor, i.e. if the processor is +* little-engian, the return Value is the byte-swapped Value read +* from the address. +* +* @note None. +* +******************************************************************************/ +#define Xil_In16LE(Addr) Xil_In16((Addr)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian input operation for a 32-bit memory location +* by reading from the specified address and returning the Value read from +* that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The Value read from the specified input address with the +* proper endianness. The return Value has the same endianness +* as that of the processor, i.e. if the processor is +* little-engian, the return Value is the byte-swapped Value read +* from the address. +* +* +* @note None. +* +******************************************************************************/ +#define Xil_In32LE(Addr) Xil_In32((Addr)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian output operation for a 16-bit memory location +* by writing the specified Value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param Value contains the Value to be output at the specified address. +* The Value has the same endianness as that of the processor. +* If the processor is little-endian, the byte-swapped Value is +* written to the address. +* +* +* @return None +* +* @note None. +* +******************************************************************************/ +#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian output operation for a 32-bit memory location +* by writing the specified Value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param Value contains the Value to be output at the specified address. +* The Value has the same endianness as that of the processor. +* If the processor is little-endian, the byte-swapped Value is +* written to the address. +* +* @return None +* +* @note None. +* +******************************************************************************/ +#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value)) + +/*****************************************************************************/ +/** +* +* Convert a 32-bit number from host byte order to network byte order. +* +* @param Data the 32-bit number to be converted. +* +* @return The converted 32-bit number in network byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Htonl(Data) Xil_EndianSwap32((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 16-bit number from host byte order to network byte order. +* +* @param Data the 16-bit number to be converted. +* +* @return The converted 16-bit number in network byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Htons(Data) Xil_EndianSwap16((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 32-bit number from network byte order to host byte order. +* +* @param Data the 32-bit number to be converted. +* +* @return The converted 32-bit number in host byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Ntohl(Data) Xil_EndianSwap32((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 16-bit number from network byte order to host byte order. +* +* @param Data the 16-bit number to be converted. +* +* @return The converted 16-bit number in host byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Ntohs(Data) Xil_EndianSwap16((Data)) + +/************************** Function Prototypes ******************************/ + +/* The following functions allow the software to be transportable across + * processors which may use memory mapped I/O or I/O which is mapped into a + * seperate address space. + */ +u8 Xil_In8(INTPTR Addr); +u16 Xil_In16(INTPTR Addr); +u32 Xil_In32(INTPTR Addr); +u64 Xil_In64(INTPTR Addr); + +void Xil_Out8(INTPTR Addr, u8 Value); +void Xil_Out16(INTPTR Addr, u16 Value); +void Xil_Out32(INTPTR Addr, u32 Value); +void Xil_Out64(INTPTR Addr, u64 Value); + +u16 Xil_In16BE(INTPTR Addr); +u32 Xil_In32BE(INTPTR Addr); +void Xil_Out16BE(INTPTR Addr, u16 Value); +void Xil_Out32BE(INTPTR Addr, u32 Value); + +u16 Xil_EndianSwap16(u16 Data); +u32 Xil_EndianSwap32(u32 Data); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/cortexr5/xil_mpu.c b/lib/bsp/standalone/src/cortexr5/xil_mpu.c new file mode 100644 index 00000000..db77d36f --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_mpu.c @@ -0,0 +1,476 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mmu.c +* +* This file provides APIs for enabling/disabling MMU and setting the memory +* attributes for sections, in the MMU translation table. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+*
+* +* @note +* +* None. +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xpseudo_asm.h" +#include "xil_types.h" +#include "xil_mpu.h" +#include "xil_printf.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/***************************************************************************** +* +* Set the memory attributes for a section of memory with starting address addr +* of the region size defined by reg_size having attributes attrib of region number +* reg_num +* +* @param addr is the address for which attributes are to be set. +* @param attrib specifies the attributes for that memory region. +* @param reg_size specifies the size for that memory region. +* @param reg_num specifies the number for that memory region. +* @return None. +* +* +******************************************************************************/ +void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) +{ + u32 CtrlReg, Alignment_Check=0x1U; + u32 Index; + u32 Local_reg_size = reg_size; + s32 DCacheStatus=0, ICacheStatus=0; + /* disable caches only if they are enabled */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { + DCacheStatus=1; + } + if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { + ICacheStatus=1; + } + if(DCacheStatus != 0) { + Xil_DCacheDisable(); + } + if(ICacheStatus != 0){ + Xil_ICacheDisable(); + } + for (Index=0U; Index<=Local_reg_size;Index++) { + Alignment_Check*=2U; + } + + /*If address is aligned with region size then it is configured*/ + + if((!(addr%Alignment_Check)) != 0x00000000U){ + Local_reg_size = Local_reg_size<<1U; + Local_reg_size |= REGION_EN; + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); + mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */ + mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */ + mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/ + dsb(); /* ensure completion of the BP invalidation */ + isb(); /* synchronize context on this processor */ + } + else { + xil_printf("Address %x is not aligned with region size \n",addr); + } + + /* enable caches only if they are disabled in routine*/ + if(DCacheStatus != 0) { + Xil_DCacheEnable(); + } + if(ICacheStatus != 0) { + Xil_ICacheEnable(); + } +} + +/***************************************************************************** +* +* Enable MPU for Cortex R5 processor. This function invalidates I cache and +* flush the D Caches before enabling the MPU. +* +* +* @param None. +* @return None. +* +******************************************************************************/ +void Xil_EnableMPU(void) +{ + u32 CtrlReg, Reg; + s32 DCacheStatus=0, ICacheStatus=0; + /* enable caches only if they are disabled */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { + DCacheStatus=1; + } + if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { + ICacheStatus=1; + } + + if(DCacheStatus != 0) { + Xil_DCacheDisable(); + } + if(ICacheStatus != 0){ + Xil_ICacheDisable(); + } + Reg = mfcp(XREG_CP15_SYS_CONTROL); + Reg |= 0x00000001U; + dsb(); + mtcp(XREG_CP15_SYS_CONTROL, Reg); + isb(); + /* enable caches only if they are disabled in routine*/ + if(DCacheStatus != 0) { + Xil_DCacheEnable(); + } + if(ICacheStatus != 0) { + Xil_ICacheEnable(); + } +} + +/***************************************************************************** +* +* Disable MPU for Cortex R5 processors. This function invalidates I cache and +* flush the D Caches before disabling the MPU. +* +* @param None. +* +* @return None. +* +******************************************************************************/ +void Xil_DisableMPU(void) +{ + u32 CtrlReg, Reg; + s32 DCacheStatus=0, ICacheStatus=0; + /* enable caches only if they are disabled */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { + DCacheStatus=1; + } + if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { + ICacheStatus=1; + } + + if(DCacheStatus != 0) { + Xil_DCacheDisable(); + } + if(ICacheStatus != 0){ + Xil_ICacheDisable(); + } + + mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0); + Reg = mfcp(XREG_CP15_SYS_CONTROL); + Reg &= ~(0x00000001U); + dsb(); + mtcp(XREG_CP15_SYS_CONTROL, Reg); + isb(); + /* enable caches only if they are disabled in routine*/ + if(DCacheStatus != 0) { + Xil_DCacheEnable(); + } + if(ICacheStatus != 0) { + Xil_ICacheEnable(); + } +} + +/***************************************************************************** +* +* Disable a Region in MPU for Cortex R5 processors. This function invalidates +* I cache and flush the D Caches before disabling the MPU region. +* +* @param reg_num defines region number which is to be disabled. +* +* @return None. +* +******************************************************************************/ + +void Xil_DisableRegion(s32 reg_num) +{ + u32 CtrlReg, Reg; + s32 DCacheStatus=0, ICacheStatus=0; + /* enable caches only if they are disabled */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { + DCacheStatus=1; + } + if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { + ICacheStatus=1; + } + + if(DCacheStatus != 0) { + Xil_DCacheDisable(); + } + if(ICacheStatus != 0){ + Xil_ICacheDisable(); + } + + mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0); + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); + + Reg = mfcp(XREG_CP15_MPU_REG_SIZE_EN); + + Reg &= ~((u32)REGION_EN); + dsb(); + mtcp(XREG_CP15_MPU_REG_SIZE_EN, Reg); + isb(); + /* enable caches only if they are disabled in routine*/ + if(DCacheStatus != 0) { + Xil_DCacheEnable(); + } + if(ICacheStatus != 0) { + Xil_ICacheEnable(); + } +} +/***************************************************************************** +* +* Disable a SubRegion in MPU for Cortex R5 processors. This function invalidates +* I cache and flush the D Caches before disabling +* the MPU subregion. +* +* @param reg_num defines region number in which particular subregion +* is to be disabled. +* @param subreg_num defines the subregion number which is to be disabled. +* @return None. +* +******************************************************************************/ + +void Xil_DisableSubRegion(s32 reg_num, u32 subreg_num) +{ + u32 CtrlReg, Reg; + s32 DCacheStatus=0, ICacheStatus=0; + /* enable caches only if they are disabled */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { + DCacheStatus=1; + } + if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { + ICacheStatus=1; + } + + if(DCacheStatus != 0) { + Xil_DCacheDisable(); + } + if(ICacheStatus != 0){ + Xil_ICacheDisable(); + } + + mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0); + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); + + Reg = mfcp(XREG_CP15_MPU_REG_SIZE_EN); + Reg |= ((0x00000001U< +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------- +* 5.00 pkp 02/10/14 Initial version +* +* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef XIL_MPU_H +#define XIL_MPU_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +#include "xil_types.h" +/***************************** Include Files *********************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib); +void Xil_EnableMPU(void); +void Xil_DisableMPU(void); +void Xil_DisableRegion(s32 reg_num); +void Xil_DisableSubRegion(s32 reg_num, u32 subreg_num); +void Xil_EnableSubRegion(s32 reg_num, u32 subreg_num); +void Xil_EnableBackgroundRegion(void); +void Xil_DisableBackgroundRegion(void); +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_MPU_H */ diff --git a/lib/bsp/standalone/src/cortexr5/xil_printf.c b/lib/bsp/standalone/src/cortexr5/xil_printf.c new file mode 100644 index 00000000..701025b3 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_printf.c @@ -0,0 +1,352 @@ +/*---------------------------------------------------*/ +/* Modified from : */ +/* Public Domain version of printf */ +/* Rud Merriam, Compsult, Inc. Houston, Tx. */ +/* For Embedded Systems Programming, 1991 */ +/* */ +/*---------------------------------------------------*/ +#include "xil_printf.h" +#include "xil_types.h" +#include "xil_assert.h" +#include +#include +#include + +static void padding( const s32 l_flag,const struct params_s *par); +static void outs(const charptr lp, struct params_s *par); +static void outnum( const s32 n, const s32 base, struct params_s *par); +static s32 getnum( charptr* linep); + +typedef struct params_s { + s32 len; + s32 num1; + s32 num2; + char8 pad_character; + s32 do_padding; + s32 left_flag; +} params_t; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + + +/*---------------------------------------------------*/ +/* */ +/* This routine puts pad characters into the output */ +/* buffer. */ +/* */ +static void padding( const s32 l_flag, const struct params_s *par) +{ + s32 i; + + if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) { + i=(par->len); + for (; i<(par->num1); i++) { +#ifdef STDOUT_BASEADDRESS + outbyte( par->pad_character); +#endif + } + } +} + +/*---------------------------------------------------*/ +/* */ +/* This routine moves a string to the output buffer */ +/* as directed by the padding and positioning flags. */ +/* */ +static void outs(const charptr lp, struct params_s *par) +{ + charptr LocalPtr; + LocalPtr = lp; + /* pad on left if needed */ + if(LocalPtr != NULL) { + par->len = (s32)strlen( LocalPtr); + } + padding( !(par->left_flag), par); + + /* Move string to the buffer */ + while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) { + (par->num2)--; +#ifdef STDOUT_BASEADDRESS + outbyte(*LocalPtr); + LocalPtr += 1; +#endif +} + + /* Pad on right if needed */ + /* CR 439175 - elided next stmt. Seemed bogus. */ + /* par->len = strlen( lp) */ + padding( par->left_flag, par); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine moves a number to the output buffer */ +/* as directed by the padding and positioning flags. */ +/* */ + +static void outnum( const s32 n, const s32 base, struct params_s *par) +{ + charptr cp; + s32 negative; + s32 i; + char8 outbuf[32]; + const char8 digits[] = "0123456789ABCDEF"; + s32 num; + for(i = 0; i<32; i++) { + outbuf[i] = '0'; + } + + /* Check if number is negative */ + if ((base == 10) && (n < 0L)) { + negative = 1; + num =(-(n)); + } + else{ + num = n; + negative = 0; + } + + /* Build number (backwards) in outbuf */ + i = 0; + do { + outbuf[i] = digits[(num % base)]; + i++; + num /= base; + } while (num > 0); + + if (negative != 0) { + outbuf[i] = '-'; + i++; + } + + outbuf[i] = 0; + i--; + + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { +#ifdef STDOUT_BASEADDRESS + outbyte( outbuf[i] ); + i--; +#endif +} + padding( par->left_flag, par); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine gets a number from the format */ +/* string. */ +/* */ +static s32 getnum( charptr* linep) +{ + s32 n; + s32 ResultIsDigit = 0; + charptr cptr; + n = 0; + cptr = *linep; + if(cptr != NULL){ + ResultIsDigit = isdigit(((s32)*cptr)); + } + while (ResultIsDigit != 0) { + if(cptr != NULL){ + n = ((n*10) + (((s32)*cptr) - (s32)'0')); + cptr += 1; + if(cptr != NULL){ + ResultIsDigit = isdigit(((s32)*cptr)); + } + } + ResultIsDigit = isdigit(((s32)*cptr)); + } + *linep = ((charptr )(cptr)); + return(n); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine operates just like a printf/sprintf */ +/* routine. It outputs a set of data under the */ +/* control of a formatting string. Not all of the */ +/* standard C format control are supported. The ones */ +/* provided are primarily those needed for embedded */ +/* systems work. Primarily the floating point */ +/* routines are omitted. Other formats could be */ +/* added easily by following the examples shown for */ +/* the supported formats. */ +/* */ + +/* void esp_printf( const func_ptr f_ptr, + const charptr ctrl1, ...) */ +void xil_printf( char8 *ctrl1, ...) +{ + s32 Check; + s32 long_flag; + s32 dot_flag; + + params_t par; + + char8 ch; + va_list argp; + char8 *ctrl = (char8 *)ctrl1; + + va_start( argp, ctrl1); + + while ((ctrl != NULL) && (*ctrl != (char8)0)) { + + /* move format string chars to buffer until a */ + /* format control is found. */ + if (*ctrl != '%') { +#ifdef STDOUT_BASEADDRESS + outbyte(*ctrl); + ctrl += 1; +#endif + continue; + } + + /* initialize all the flags for this format. */ + dot_flag = 0; + long_flag = 0; + par.left_flag = 0; + par.do_padding = 0; + par.pad_character = ' '; + par.num2=32767; + par.num1=0; + par.len=0; + + try_next: + if(ctrl != NULL) { + ctrl += 1; + } + if(ctrl != NULL) { + ch = *ctrl; + } + else { + ch = *ctrl; + } + + if (isdigit((s32)ch) != 0) { + if (dot_flag != 0) { + par.num2 = getnum(&ctrl); + } + else { + if (ch == '0') { + par.pad_character = '0'; + } + if(ctrl != NULL) { + par.num1 = getnum(&ctrl); + } + par.do_padding = 1; + } + if(ctrl != NULL) { + ctrl -= 1; + } + goto try_next; + } + + switch (tolower((s32)ch)) { + case '%': +#ifdef STDOUT_BASEADDRESS + outbyte( '%'); +#endif + Check = 1; + break; + + case '-': + par.left_flag = 1; + Check = 0; + break; + + case '.': + dot_flag = 1; + Check = 0; + break; + + case 'l': + long_flag = 1; + Check = 0; + break; + + case 'd': + if ((long_flag != 0) || (ch == 'D')) { + outnum( va_arg(argp, s32), 10L, &par); + } + else { + outnum( va_arg(argp, s32), 10L, &par); + } + Check = 1; + break; + case 'x': + outnum((s32)va_arg(argp, s32), 16L, &par); + Check = 1; + break; + + case 's': + outs( va_arg( argp, char *), &par); + Check = 1; + break; + + case 'c': +#ifdef STDOUT_BASEADDRESS + outbyte( va_arg( argp, s32)); +#endif + Check = 1; + break; + + case '\\': + switch (*ctrl) { + case 'a': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x07)); +#endif + break; + case 'h': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x08)); +#endif + break; + case 'r': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x0D)); +#endif + break; + case 'n': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x0D)); + outbyte( ((char8)0x0A)); +#endif + break; + default: +#ifdef STDOUT_BASEADDRESS + outbyte( *ctrl); +#endif + break; + } + ctrl += 1; + Check = 0; + break; + + default: + Check = 1; + break; + } + if(Check == 1) { + if(ctrl != NULL) { + ctrl += 1; + } + continue; + } + goto try_next; + } + va_end( argp); +} + +/*---------------------------------------------------*/ diff --git a/lib/bsp/standalone/src/cortexr5/xil_printf.h b/lib/bsp/standalone/src/cortexr5/xil_printf.h new file mode 100644 index 00000000..6c1e1507 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_printf.h @@ -0,0 +1,44 @@ + #ifndef XIL_PRINTF_H + #define XIL_PRINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include "xil_types.h" +#include "xparameters.h" + +/*----------------------------------------------------*/ +/* Use the following parameter passing structure to */ +/* make xil_printf re-entrant. */ +/*----------------------------------------------------*/ + +struct params_s; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + +typedef char8* charptr; +typedef s32 (*func_ptr)(int c); + +/* */ + +void xil_printf( char8 *ctrl1, ...); +void print( const char8 *ptr); +extern void outbyte (char8 c); +extern char8 inbyte(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/cortexr5/xparameters_ps.h b/lib/bsp/standalone/src/cortexr5/xparameters_ps.h new file mode 100644 index 00000000..7875b74d --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xparameters_ps.h @@ -0,0 +1,369 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xparameters_ps.h +* +* This file contains the address definitions for the hard peripherals +* attached to the ARM Cortex R5 core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp  	02/29/14 Initial version
+*
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef XPARAMETERS_PS_H_ +#define XPARAMETERS_PS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* + * This block contains constant declarations for the peripherals + * within the hardblock + */ + +/* Canonical definitions for DDR MEMORY */ +#define XPAR_DDR_MEM_BASEADDR 0x00000000U +#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU + +/* Canonical definitions for Interrupts */ +#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID +#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID +#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID +#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID +#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID +#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID +#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID +#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID +#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID +#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID +#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID +#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID +#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID +#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID +#define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID +#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID +#define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID +#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID +#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID +#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID +#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID +#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID +#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID +#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID +#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID +#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID +#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID +#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID +#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID +#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID +#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID +#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID +#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID + + +#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR +#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR + + + +/* Canonical definitions for DMAC */ + + +/* Canonical definitions for WDT */ + +/* Canonical definitions for SLCR */ +#define XPAR_XSLCR_NUM_INSTANCES 1U +#define XPAR_XSLCR_0_DEVICE_ID 0U +#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR + +/* Canonical definitions for SCU GIC */ +#define XPAR_SCUGIC_NUM_INSTANCES 1U +#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U +#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U) +#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U) +#define XPAR_SCUGIC_ACK_BEFORE 0U + +/* Canonical definitions for Global Timer */ +#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U +#define XPAR_GLOBAL_TMR_DEVICE_ID 0U +#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U) +#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID + + +/* Xilinx Parallel Flash Library (XilFlash) User Settings */ +#define XPAR_AXI_EMC + + +#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ + + +/* + * This block contains constant declarations for the peripherals + * within the hardblock. These have been put for bacwards compatibilty + */ + +#define XPS_PERIPHERAL_BASEADDR 0xE0000000U +#define XPS_UART0_BASEADDR 0xFF000000U +#define XPS_UART1_BASEADDR 0xFF010000U +#define XPS_I2C0_BASEADDR 0xFF020000U +#define XPS_I2C1_BASEADDR 0xFF030000U +#define XPS_SPI0_BASEADDR 0xFF040000U +#define XPS_SPI1_BASEADDR 0xFF050000U +#define XPS_CAN0_BASEADDR 0xFF060000U +#define XPS_CAN1_BASEADDR 0xFF070000U +#define XPS_GPIO_BASEADDR 0xFF0A0000U +#define XPS_GEM0_BASEADDR 0xFF0B0000U +#define XPS_GEM1_BASEADDR 0xFF0C0000U +#define XPS_GEM2_BASEADDR 0xFF0D0000U +#define XPS_GEM3_BASEADDR 0xFF0E0000U +#define XPS_QSPI_BASEADDR 0xFF0F0000U +#define XPS_NAND_BASEADDR 0xFF100000U +#define XPS_TTC0_BASEADDR 0xFF110000U +#define XPS_TTC1_BASEADDR 0xFF120000U +#define XPS_TTC2_BASEADDR 0xFF130000U +#define XPS_TTC3_BASEADDR 0xFF140000U +#define XPS_WDT_BASEADDR 0xFF150000U +#define XPS_SDIO0_BASEADDR 0xFF160000U +#define XPS_SDIO1_BASEADDR 0xFF170000U +#define XPS_SYS_CTRL_BASEADDR 0xFF180000U +/*#define XPAR_XNANDPS8_0_BASEADDR 0xFF100000U */ + + +#define XPS_PARPORT_CRTL_BASEADDR 0x0000000U +#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U +#define XPS_PARPORT0_BASEADDR 0xE2000000U +#define XPS_PARPORT1_BASEADDR 0xE4000000U +#define XPS_QSPI_LINEAR_BASEADDR 0xF0000000U +#define XPS_DMAC0_NON_SEC_BASEADDR 0xFE507000U +#define XPS_DMAC0_SEC_BASEADDR 0xFE5F0000U +#define XPS_DDR_CTRL_BASEADDR 0xF8006000U +#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U +#define XPS_AFI0_BASEADDR 0xF8008000U +#define XPS_AFI1_BASEADDR 0xF8009000U +#define XPS_AFI2_BASEADDR 0xF800A000U +#define XPS_AFI3_BASEADDR 0xF800B000U +#define XPS_OCM_BASEADDR 0xF800C000U +#define XPS_EFUSE_BASEADDR 0xF800D000U +#define XPS_CORESIGHT_BASEADDR 0xF8800000U +#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U +#define XPS_SCU_PERIPH_BASE 0xF9000000U +#define XPS_L2CC_BASEADDR 0xFD3FD000U +#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U +#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U +#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U +#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U +#define XPS_PERIPH_APB_BASEADDR 0xF8000000U +#define XPS_USB0_BASEADDR 0xE0002000U +#define XPS_USB1_BASEADDR 0xE0003000U + + +/* Shared Peripheral Interrupts (SPI) */ +/* Shared Peripheral Interrupts (SPI) */ + +#define XPS_USB1_INT_ID 76U +#define XPS_USB0_INT_ID 53U + +#define XPS_NAND_INT_ID (32U + 32U) + +#define XPS_FPGA1_INT_ID 62U +#define XPS_FPGA2_INT_ID 63U +#define XPS_FPGA3_INT_ID 64U +#define XPS_FPGA4_INT_ID 65U +#define XPS_FPGA5_INT_ID 66U +#define XPS_FPGA6_INT_ID 67U +#define XPS_FPGA7_INT_ID 68U +#define XPS_DMA4_INT_ID 72U +#define XPS_DMA5_INT_ID 73U +#define XPS_DMA6_INT_ID 74U +#define XPS_DMA7_INT_ID 75U +#define XPS_FPGA8_INT_ID 84U +#define XPS_FPGA9_INT_ID 85U +#define XPS_FPGA10_INT_ID 86U +#define XPS_FPGA11_INT_ID 87U +#define XPS_FPGA12_INT_ID 88U +#define XPS_FPGA13_INT_ID 89U +#define XPS_FPGA14_INT_ID 90U +#define XPS_FPGA15_INT_ID 91U + + +#define XPS_OCMINTR_INT_ID (28U + 32U) +#define XPS_QSPI_INT_ID (33U + 32U) +#define XPS_GPIO_INT_ID (34U + 32U) +#define XPS_WDT_INT_ID (106U + 32U) +#define XPS_LP_WDT_INT_ID (69U + 32U) +#define XPS_TTC0_0_INT_ID (53U + 32U) +#define XPS_TTC0_1_INT_ID (54U + 32U) +#define XPS_TTC0_2_INT_ID (55U + 32U) +#define XPS_SDIO0_INT_ID (65U + 32U) +#define XPS_I2C0_INT_ID (35U + 32U) +#define XPS_SPI0_INT_ID (37U + 32U) +#define XPS_UART0_INT_ID (39U + 32U) +#define XPS_CAN0_INT_ID (41U + 32U) + +/* FIXME */ +//#define XPS_FPGA0_INT_ID 100 + +#define XPS_TTC1_0_INT_ID (56U + 32U) +#define XPS_TTC1_1_INT_ID (57U + 32U) +#define XPS_TTC1_2_INT_ID (58U + 32U) +#define XPS_TTC2_0_INT_ID (59U + 32U) +#define XPS_TTC2_1_INT_ID (60U + 32U) +#define XPS_TTC2_2_INT_ID (61U + 32U) +#define XPS_TTC3_0_INT_ID (62U + 32U) +#define XPS_TTC3_1_INT_ID (63U + 32U) +#define XPS_TTC3_2_INT_ID (64U + 32U) +#define XPS_SDIO1_INT_ID (66U + 32U) +#define XPS_I2C1_INT_ID (36U + 32U) +#define XPS_SPI1_INT_ID (38U + 32U) +#define XPS_UART1_INT_ID (40U + 32U) +#define XPS_CAN1_INT_ID (42U + 32U) +#define XPS_GEM0_INT_ID (73U + 32U) +#define XPS_GEM0_WAKE_INT_ID (74U + 32U) +#define XPS_GEM1_INT_ID (75U + 32U) +#define XPS_GEM1_WAKE_INT_ID (76U + 32U) +#define XPS_GEM2_INT_ID (77U + 32U) +#define XPS_GEM2_WAKE_INT_ID (78U + 32U) +#define XPS_GEM3_INT_ID (79U + 32U) +#define XPS_GEM3_WAKE_INT_ID (80U + 32U) + +/* Private Peripheral Interrupts (PPI) */ +/*#define XPS_GLOBAL_TMR_INT_ID 27 SCU Global Timer interrupt */ +/*#define XPS_FIQ_INT_ID 28 FIQ from FPGA fabric */ +/*#define XPS_SCU_TMR_INT_ID 29 SCU Private Timer interrupt */ +/*#define XPS_SCU_WDT_INT_ID 30 SCU Private WDT interrupt */ +/*#define XPS_IRQ_INT_ID 31 IRQ from FPGA fabric */ + + +/* REDEFINES for TEST APP */ +/* Definitions for UART */ +#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID +#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID +#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID +#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID +#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID +#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID +#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID +#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID +#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID +#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID +#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID +#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID +#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID +#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_2_INTR XPS_GEM2_INT_ID +#define XPAR_PS7_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_3_INTR XPS_GEM3_INT_ID +#define XPAR_PS7_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID + +#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID +#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID +#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID +#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID +#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID + +#define XPAR_XADCPS_NUM_INSTANCES 1U +#define XPAR_XADCPS_0_DEVICE_ID 0U +#define XPAR_XADCPS_0_BASEADDR (0xF8007000U) +#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID + +/* For backwards compatibilty */ +#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ +#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ +#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ +#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ +#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ + +#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ + +#ifdef XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ +#endif + +#ifdef XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ +#endif + +#define XPAR_SCUTIMER_DEVICE_ID 0U +#define XPAR_SCUWDT_DEVICE_ID 0U + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/lib/bsp/standalone/src/cortexr5/xpm_counter.c b/lib/bsp/standalone/src/cortexr5/xpm_counter.c new file mode 100644 index 00000000..e2984619 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xpm_counter.c @@ -0,0 +1,303 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpm_counter.c +* +* This file contains APIs for configuring and controlling the Cortex-R5 +* Performance Monitor Events. For more information about the event counters, +* see xpm_counter.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xpm_counter.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT]; + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions *****************************/ + + + +/************************** Function Prototypes ******************************/ + +void Xpm_DisableEventCounters(void); +void Xpm_EnableEventCounters (void); +void Xpm_ResetEventCounters (void); + +/******************************************************************************/ + +/****************************************************************************/ +/** +* +* This function disables the Cortex R5 event counters. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_DisableEventCounters(void) +{ + /* Disable the event counters */ + mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f); +} + +/****************************************************************************/ +/** +* +* This function enables the Cortex R5 event counters. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_EnableEventCounters(void) +{ + /* Enable the event counters */ + mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f); +} + +/****************************************************************************/ +/** +* +* This function resets the Cortex R5 event counters. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_ResetEventCounters(void) +{ + u32 Reg; + +#ifdef __GNUC__ + Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL); +#else + { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL); + Reg = C15Reg; } +#endif + Reg |= (1U << 2U); /* reset event counters */ + mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); +} + +/****************************************************************************/ +/** +* +* This function configures the Cortex R5 event counters controller, with the +* event codes, in a configuration selected by the user and enables the counters. +* +* @param PmcrCfg is configuration value based on which the event counters +* are configured. +* Use XPM_CNTRCFG* values defined in xpm_counter.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_SetEvents(s32 PmcrCfg) +{ + u32 Counter; + static PmcrEventCfg32 PmcrEvents[] = { + { + XPM_EVENT_SOFTINCR, + XPM_EVENT_INSRFETCH_CACHEREFILL, + XPM_EVENT_INSTRFECT_TLBREFILL, + XPM_EVENT_DATA_CACHEREFILL, + XPM_EVENT_DATA_CACHEACCESS, + XPM_EVENT_DATA_TLBREFILL + }, + { + XPM_EVENT_DATA_READS, + XPM_EVENT_DATA_WRITE, + XPM_EVENT_EXCEPTION, + XPM_EVENT_EXCEPRETURN, + XPM_EVENT_CHANGECONTEXT, + XPM_EVENT_SW_CHANGEPC + }, + { + XPM_EVENT_IMMEDBRANCH, + XPM_EVENT_UNALIGNEDACCESS, + XPM_EVENT_BRANCHMISS, + XPM_EVENT_CLOCKCYCLES, + XPM_EVENT_BRANCHPREDICT, + XPM_EVENT_JAVABYTECODE + }, + { + XPM_EVENT_SWJAVABYTECODE, + XPM_EVENT_JAVABACKBRANCH, + XPM_EVENT_COHERLINEMISS, + XPM_EVENT_COHERLINEHIT, + XPM_EVENT_INSTRSTALL, + XPM_EVENT_DATASTALL + }, + { + XPM_EVENT_MAINTLBSTALL, + XPM_EVENT_STREXPASS, + XPM_EVENT_STREXFAIL, + XPM_EVENT_DATAEVICT, + XPM_EVENT_NODISPATCH, + XPM_EVENT_ISSUEEMPTY + }, + { + XPM_EVENT_INSTRRENAME, + XPM_EVENT_PREDICTFUNCRET, + XPM_EVENT_MAINEXEC, + XPM_EVENT_SECEXEC, + XPM_EVENT_LDRSTR, + XPM_EVENT_FLOATRENAME + }, + { + XPM_EVENT_NEONRENAME, + XPM_EVENT_PLDSTALL, + XPM_EVENT_WRITESTALL, + XPM_EVENT_INSTRTLBSTALL, + XPM_EVENT_DATATLBSTALL, + XPM_EVENT_INSTR_uTLBSTALL + }, + { + XPM_EVENT_DATA_uTLBSTALL, + XPM_EVENT_DMB_STALL, + XPM_EVENT_INT_CLKEN, + XPM_EVENT_DE_CLKEN, + XPM_EVENT_INSTRISB, + XPM_EVENT_INSTRDSB + }, + { + XPM_EVENT_INSTRDMB, + XPM_EVENT_EXTINT, + XPM_EVENT_PLE_LRC, + XPM_EVENT_PLE_LRS, + XPM_EVENT_PLE_FLUSH, + XPM_EVENT_PLE_CMPL + }, + { + XPM_EVENT_PLE_OVFL, + XPM_EVENT_PLE_PROG, + XPM_EVENT_PLE_LRC, + XPM_EVENT_PLE_LRS, + XPM_EVENT_PLE_FLUSH, + XPM_EVENT_PLE_CMPL + }, + { + XPM_EVENT_DATASTALL, + XPM_EVENT_INSRFETCH_CACHEREFILL, + XPM_EVENT_INSTRFECT_TLBREFILL, + XPM_EVENT_DATA_CACHEREFILL, + XPM_EVENT_DATA_CACHEACCESS, + XPM_EVENT_DATA_TLBREFILL + }, + }; + const u32 *ptr = PmcrEvents[PmcrCfg]; + + Xpm_DisableEventCounters(); + + for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) { + + /* Selecet event counter */ + mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); + + /* Set the event */ + mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]); + } + + Xpm_ResetEventCounters(); + Xpm_EnableEventCounters(); +} + +/****************************************************************************/ +/** +* +* This function disables the event counters and returns the counter values. +* +* @param PmCtrValue is a pointer to an array of type u32 PmCtrValue[6]. +* It is an output parameter which is used to return the PM +* counter values. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_GetEventCounters(u32 *PmCtrValue) +{ + u32 Counter; + + Xpm_DisableEventCounters(); + + for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) { + + mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); +#ifdef __GNUC__ + PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT); +#else + { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT); + PmCtrValue[Counter] = Cp15Reg; } +#endif + } +} diff --git a/lib/bsp/standalone/src/cortexr5/xpm_counter.h b/lib/bsp/standalone/src/cortexr5/xpm_counter.h new file mode 100644 index 00000000..caa64387 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xpm_counter.h @@ -0,0 +1,582 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpm_counter.h +* +* This header file contains APIs for configuring and controlling the Cortex-R5 +* Performance Monitor Events. +* Cortex-R5 Performance Monitor has 6 event counters which can be used to +* count a variety of events described in Coretx-R5 TRM. This file defines +* configurations, where value configures the event counters to count a +* set of events. +* +* Xpm_SetEvents can be used to set the event counters to count a set of events +* and Xpm_GetEventCounters can be used to read the counter values. +* +* @note +* +* This file doesn't handle the Cortex-R5 cycle counter, as the cycle counter is +* being used for time keeping. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+*
+* +******************************************************************************/ + +#ifndef XPMCOUNTER_H /* prevent circular inclusions */ +#define XPMCOUNTER_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include +#include "xpseudo_asm.h" +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/* Number of performance counters */ +#define XPM_CTRCOUNT 6U + +/* The following constants define the Cortex-R5 Performance Monitor Events */ + +/* + * Software increment. The register is incremented only on writes to the + * Software Increment Register + */ +#define XPM_EVENT_SOFTINCR 0x00U + +/* + * Instruction fetch that causes a refill at (at least) the lowest level(s) of + * instruction or unified cache. Includes the speculative linefills in the + * count + */ +#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U + +/* + * Instruction fetch that causes a TLB refill at (at least) the lowest level of + * TLB. Includes the speculative requests in the count + */ +#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U + +/* + * Data read or write operation that causes a refill at (at least) the lowest + * level(s)of data or unified cache. Counts the number of allocations performed + * in the Data Cache due to a read or a write + */ +#define XPM_EVENT_DATA_CACHEREFILL 0x03U + +/* + * Data read or write operation that causes a cache access at (at least) the + * lowest level(s) of data or unified cache. This includes speculative reads + */ +#define XPM_EVENT_DATA_CACHEACCESS 0x04U + +/* + * Data read or write operation that causes a TLB refill at (at least) the + * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI, + * CP15 Cache operation by MVA and CP15 VA to PA operations + */ +#define XPM_EVENT_DATA_TLBREFILL 0x05U + +/* + * Data read architecturally executed. Counts the number of data read + * instructions accepted by the Load Store Unit. This includes counting the + * speculative and aborted LDR/LDM, as well as the reads due to the SWP + * instructions + */ +#define XPM_EVENT_DATA_READS 0x06U + +/* + * Data write architecturally executed. Counts the number of data write + * instructions accepted by the Load Store Unit. This includes counting the + * speculative and aborted STR/STM, as well as the writes due to the SWP + * instructions + */ +#define XPM_EVENT_DATA_WRITE 0x07U + +/* Exception taken. Counts the number of exceptions architecturally taken.*/ +#define XPM_EVENT_EXCEPTION 0x09U + +/* Exception return architecturally executed.*/ +#define XPM_EVENT_EXCEPRETURN 0x0AU + +/* + * Change to ContextID retired. Counts the number of instructions + * architecturally executed writing into the ContextID Register + */ +#define XPM_EVENT_CHANGECONTEXT 0x0BU + +/* + * Software change of PC, except by an exception, architecturally executed. + * Count the number of PC changes architecturally executed, excluding the PC + * changes due to taken exceptions + */ +#define XPM_EVENT_SW_CHANGEPC 0x0CU + +/* + * Immediate branch architecturally executed (taken or not taken). This includes + * the branches which are flushed due to a previous load/store which aborts + * late + */ +#define XPM_EVENT_IMMEDBRANCH 0x0DU + +/* + * Unaligned access architecturally executed. Counts the number of aborted + * unaligned accessed architecturally executed, and the number of not-aborted + * unaligned accesses, including the speculative ones + */ +#define XPM_EVENT_UNALIGNEDACCESS 0x0FU + +/* + * Branch mispredicted/not predicted. Counts the number of mispredicted or + * not-predicted branches executed. This includes the branches which are flushed + * due to a previous load/store which aborts late + */ +#define XPM_EVENT_BRANCHMISS 0x10U + +/* + * Counts clock cycles when the Cortex-R5 processor is not in WFE/WFI. This + * event is not exported on the PMUEVENT bus + */ +#define XPM_EVENT_CLOCKCYCLES 0x11U + +/* + * Branches or other change in program flow that could have been predicted by + * the branch prediction resources of the processor. This includes the branches + * which are flushed due to a previous load/store which aborts late + */ +#define XPM_EVENT_BRANCHPREDICT 0x12U + +/* + * Java bytecode execute. Counts the number of Java bytecodes being decoded, + * including speculative ones + */ +#define XPM_EVENT_JAVABYTECODE 0x40U + +/* + * Software Java bytecode executed. Counts the number of software java bytecodes + * being decoded, including speculative ones + */ +#define XPM_EVENT_SWJAVABYTECODE 0x41U + +/* + * Jazelle backward branches executed. Counts the number of Jazelle taken + * branches being executed. This includes the branches which are flushed due + * to a previous load/store which aborts late + */ +#define XPM_EVENT_JAVABACKBRANCH 0x42U + +/* + * Coherent linefill miss Counts the number of coherent linefill requests + * performed by the Cortex-R5 processor which also miss in all the other + * Cortex-R5 processors, meaning that the request is sent to the external + * memory + */ +#define XPM_EVENT_COHERLINEMISS 0x50U + +/* + * Coherent linefill hit. Counts the number of coherent linefill requests + * performed by the Cortex-R5 processor which hit in another Cortex-R5 + * processor, meaning that the linefill data is fetched directly from the + * relevant Cortex-R5 cache + */ +#define XPM_EVENT_COHERLINEHIT 0x51U + +/* + * Instruction cache dependent stall cycles. Counts the number of cycles where + * the processor is ready to accept new instructions, but does not receive any + * due to the instruction side not being able to provide any and the + * instruction cache is currently performing at least one linefill + */ +#define XPM_EVENT_INSTRSTALL 0x60U + +/* + * Data cache dependent stall cycles. Counts the number of cycles where the core + * has some instructions that it cannot issue to any pipeline, and the Load + * Store unit has at least one pending linefill request, and no pending + */ +#define XPM_EVENT_DATASTALL 0x61U + +/* + * Main TLB miss stall cycles. Counts the number of cycles where the processor + * is stalled waiting for the completion of translation table walks from the + * main TLB. The processor stalls can be due to the instruction side not being + * able to provide the instructions, or to the data side not being able to + * provide the necessary data, due to them waiting for the main TLB translation + * table walk to complete + */ +#define XPM_EVENT_MAINTLBSTALL 0x62U + +/* + * Counts the number of STREX instructions architecturally executed and + * passed + */ +#define XPM_EVENT_STREXPASS 0x63U + +/* + * Counts the number of STREX instructions architecturally executed and + * failed + */ +#define XPM_EVENT_STREXFAIL 0x64U + +/* + * Data eviction. Counts the number of eviction requests due to a linefill in + * the data cache + */ +#define XPM_EVENT_DATAEVICT 0x65U + +/* + * Counts the number of cycles where the issue stage does not dispatch any + * instruction because it is empty or cannot dispatch any instructions + */ +#define XPM_EVENT_NODISPATCH 0x66U + +/* + * Counts the number of cycles where the issue stage is empty + */ +#define XPM_EVENT_ISSUEEMPTY 0x67U + +/* + * Counts the number of instructions going through the Register Renaming stage. + * This number is an approximate number of the total number of instructions + * speculatively executed, and even more approximate of the total number of + * instructions architecturally executed. The approximation depends mainly on + * the branch misprediction rate. + * The renaming stage can handle two instructions in the same cycle so the event + * is two bits long: + * - b00 no instructions renamed + * - b01 one instruction renamed + * - b10 two instructions renamed + */ +#define XPM_EVENT_INSTRRENAME 0x68U + +/* + * Counts the number of procedure returns whose condition codes do not fail, + * excluding all returns from exception. This count includes procedure returns + * which are flushed due to a previous load/store which aborts late. + * Only the following instructions are reported: + * - BX R14 + * - MOV PC LR + * - POP {..,pc} + * - LDR pc,[sp],#offset + * The following instructions are not reported: + * - LDMIA R9!,{..,PC} (ThumbEE state only) + * - LDR PC,[R9],#offset (ThumbEE state only) + * - BX R0 (Rm != R14) + * - MOV PC,R0 (Rm != R14) + * - LDM SP,{...,PC} (writeback not specified) + * - LDR PC,[SP,#offset] (wrong addressing mode) + */ +#define XPM_EVENT_PREDICTFUNCRET 0x6EU + +/* + * Counts the number of instructions being executed in the main execution + * pipeline of the processor, the multiply pipeline and arithmetic logic unit + * pipeline. The counted instructions are still speculative + */ +#define XPM_EVENT_MAINEXEC 0x70U + +/* + * Counts the number of instructions being executed in the processor second + * execution pipeline (ALU). The counted instructions are still speculative + */ +#define XPM_EVENT_SECEXEC 0x71U + +/* + * Counts the number of instructions being executed in the Load/Store unit. The + * counted instructions are still speculative + */ +#define XPM_EVENT_LDRSTR 0x72U + +/* + * Counts the number of Floating-point instructions going through the Register + * Rename stage. Instructions are still speculative in this stage. + *Two floating-point instructions can be renamed in the same cycle so the event + * is two bitslong: + *0b00 no floating-point instruction renamed + *0b01 one floating-point instruction renamed + *0b10 two floating-point instructions renamed + */ +#define XPM_EVENT_FLOATRENAME 0x73U + +/* + * Counts the number of Neon instructions going through the Register Rename + * stage.Instructions are still speculative in this stage. + * Two NEON instructions can be renamed in the same cycle so the event is two + * bits long: + *0b00 no NEON instruction renamed + *0b01 one NEON instruction renamed + *0b10 two NEON instructions renamed + */ +#define XPM_EVENT_NEONRENAME 0x74U + +/* + * Counts the number of cycles where the processor is stalled because PLD slots + * are all full + */ +#define XPM_EVENT_PLDSTALL 0x80U + +/* + * Counts the number of cycles when the processor is stalled and the data side + * is stalled too because it is full and executing writes to the external + * memory + */ +#define XPM_EVENT_WRITESTALL 0x81U + +/* + * Counts the number of stall cycles due to main TLB misses on requests issued + * by the instruction side + */ +#define XPM_EVENT_INSTRTLBSTALL 0x82U + +/* + * Counts the number of stall cycles due to main TLB misses on requests issued + * by the data side + */ +#define XPM_EVENT_DATATLBSTALL 0x83U + +/* + * Counts the number of stall cycles due to micro TLB misses on the instruction + * side. This event does not include main TLB miss stall cycles that are already + * counted in the corresponding main TLB event + */ +#define XPM_EVENT_INSTR_uTLBSTALL 0x84U + +/* + * Counts the number of stall cycles due to micro TLB misses on the data side. + * This event does not include main TLB miss stall cycles that are already + * counted in the corresponding main TLB event + */ +#define XPM_EVENT_DATA_uTLBSTALL 0x85U + +/* + * Counts the number of stall cycles because of the execution of a DMB memory + * barrier. This includes all DMB instructions being executed, even + * speculatively + */ +#define XPM_EVENT_DMB_STALL 0x86U + +/* + * Counts the number of cycles during which the integer core clock is enabled + */ +#define XPM_EVENT_INT_CLKEN 0x8AU + +/* + * Counts the number of cycles during which the Data Engine clock is enabled + */ +#define XPM_EVENT_DE_CLKEN 0x8BU + +/* + * Counts the number of ISB instructions architecturally executed + */ +#define XPM_EVENT_INSTRISB 0x90U + +/* + * Counts the number of DSB instructions architecturally executed + */ +#define XPM_EVENT_INSTRDSB 0x91U + +/* + * Counts the number of DMB instructions speculatively executed + */ +#define XPM_EVENT_INSTRDMB 0x92U + +/* + * Counts the number of external interrupts executed by the processor + */ +#define XPM_EVENT_EXTINT 0x93U + +/* + * PLE cache line request completed + */ +#define XPM_EVENT_PLE_LRC 0xA0U + +/* + * PLE cache line request skipped + */ +#define XPM_EVENT_PLE_LRS 0xA1U + +/* + * PLE FIFO flush + */ +#define XPM_EVENT_PLE_FLUSH 0xA2U + +/* + * PLE request complete + */ +#define XPM_EVENT_PLE_CMPL 0xA3U + +/* + * PLE FIFO overflow + */ +#define XPM_EVENT_PLE_OVFL 0xA4U + +/* + * PLE request programmed + */ +#define XPM_EVENT_PLE_PROG 0xA5U + +/* + * The following constants define the configurations for Cortex-R5 Performance + * Monitor Events. Each configuration configures the event counters for a set + * of events. + * ----------------------------------------------- + * Config PmCtr0... PmCtr5 + * ----------------------------------------------- + * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR, + * XPM_EVENT_INSRFETCH_CACHEREFILL, + * XPM_EVENT_INSTRFECT_TLBREFILL, + * XPM_EVENT_DATA_CACHEREFILL, + * XPM_EVENT_DATA_CACHEACCESS, + * XPM_EVENT_DATA_TLBREFILL } + * + * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS, + * XPM_EVENT_DATA_WRITE, + * XPM_EVENT_EXCEPTION, + * XPM_EVENT_EXCEPRETURN, + * XPM_EVENT_CHANGECONTEXT, + * XPM_EVENT_SW_CHANGEPC } + * + * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH, + * XPM_EVENT_UNALIGNEDACCESS, + * XPM_EVENT_BRANCHMISS, + * XPM_EVENT_CLOCKCYCLES, + * XPM_EVENT_BRANCHPREDICT, + * XPM_EVENT_JAVABYTECODE } + * + * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE, + * XPM_EVENT_JAVABACKBRANCH, + * XPM_EVENT_COHERLINEMISS, + * XPM_EVENT_COHERLINEHIT, + * XPM_EVENT_INSTRSTALL, + * XPM_EVENT_DATASTALL } + * + * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL, + * XPM_EVENT_STREXPASS, + * XPM_EVENT_STREXFAIL, + * XPM_EVENT_DATAEVICT, + * XPM_EVENT_NODISPATCH, + * XPM_EVENT_ISSUEEMPTY } + * + * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME, + * XPM_EVENT_PREDICTFUNCRET, + * XPM_EVENT_MAINEXEC, + * XPM_EVENT_SECEXEC, + * XPM_EVENT_LDRSTR, + * XPM_EVENT_FLOATRENAME } + * + * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME, + * XPM_EVENT_PLDSTALL, + * XPM_EVENT_WRITESTALL, + * XPM_EVENT_INSTRTLBSTALL, + * XPM_EVENT_DATATLBSTALL, + * XPM_EVENT_INSTR_uTLBSTALL } + * + * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL, + * XPM_EVENT_DMB_STALL, + * XPM_EVENT_INT_CLKEN, + * XPM_EVENT_DE_CLKEN, + * XPM_EVENT_INSTRISB, + * XPM_EVENT_INSTRDSB } + * + * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB, + * XPM_EVENT_EXTINT, + * XPM_EVENT_PLE_LRC, + * XPM_EVENT_PLE_LRS, + * XPM_EVENT_PLE_FLUSH, + * XPM_EVENT_PLE_CMPL } + * + * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL, + * XPM_EVENT_PLE_PROG, + * XPM_EVENT_PLE_LRC, + * XPM_EVENT_PLE_LRS, + * XPM_EVENT_PLE_FLUSH, + * XPM_EVENT_PLE_CMPL } + * + * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL, + * XPM_EVENT_INSRFETCH_CACHEREFILL, + * XPM_EVENT_INSTRFECT_TLBREFILL, + * XPM_EVENT_DATA_CACHEREFILL, + * XPM_EVENT_DATA_CACHEACCESS, + * XPM_EVENT_DATA_TLBREFILL } + */ +#define XPM_CNTRCFG1 0 +#define XPM_CNTRCFG2 1 +#define XPM_CNTRCFG3 2 +#define XPM_CNTRCFG4 3 +#define XPM_CNTRCFG5 4 +#define XPM_CNTRCFG6 5 +#define XPM_CNTRCFG7 6 +#define XPM_CNTRCFG8 7 +#define XPM_CNTRCFG9 8 +#define XPM_CNTRCFG10 9 +#define XPM_CNTRCFG11 10 + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +/* Interface fuctions to access perfromance counters from abstraction layer */ +void Xpm_SetEvents(s32 PmcrCfg); +void Xpm_GetEventCounters(u32 *PmCtrValue); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/cortexr5/xpseudo_asm.h b/lib/bsp/standalone/src/cortexr5/xpseudo_asm.h new file mode 100644 index 00000000..8f0ea67e --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xpseudo_asm.h @@ -0,0 +1,69 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm.h +* +* This header file contains macros for using inline assembler code. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+*
+* +******************************************************************************/ +#ifndef XPSEUDO_ASM_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_H /* by using protection macros */ + +#include "xreg_cortexr5.h" +#ifdef __GNUC__ + #include "xpseudo_asm_gcc.h" +#else + #include "xpseudo_asm_rvct.h" +#endif + +#endif /* XPSEUDO_ASM_H */ diff --git a/lib/bsp/standalone/src/cortexr5/xreg_cortexr5.h b/lib/bsp/standalone/src/cortexr5/xreg_cortexr5.h new file mode 100644 index 00000000..5e50c99a --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xreg_cortexr5.h @@ -0,0 +1,604 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xreg_cortexr5.h +* +* This header file contains definitions for using inline assembler code. It is +* written specifically for the GNU, IAR, ARMCC compiler. +* +* All of the ARM Cortex R5 GPRs, SPRs, and Debug Registers are defined along +* with the positions of the bits within the registers. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+*
+* +******************************************************************************/ +#ifndef XREG_CORTEXR5_H /* prevent circular inclusions */ +#define XREG_CORTEXR5_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* GPRs */ +#define XREG_GPR0 r0 +#define XREG_GPR1 r1 +#define XREG_GPR2 r2 +#define XREG_GPR3 r3 +#define XREG_GPR4 r4 +#define XREG_GPR5 r5 +#define XREG_GPR6 r6 +#define XREG_GPR7 r7 +#define XREG_GPR8 r8 +#define XREG_GPR9 r9 +#define XREG_GPR10 r10 +#define XREG_GPR11 r11 +#define XREG_GPR12 r12 +#define XREG_GPR13 r13 +#define XREG_GPR14 r14 +#define XREG_GPR15 r15 +#define XREG_CPSR cpsr + +/* Coprocessor number defines */ +#define XREG_CP0 0 +#define XREG_CP1 1 +#define XREG_CP2 2 +#define XREG_CP3 3 +#define XREG_CP4 4 +#define XREG_CP5 5 +#define XREG_CP6 6 +#define XREG_CP7 7 +#define XREG_CP8 8 +#define XREG_CP9 9 +#define XREG_CP10 10 +#define XREG_CP11 11 +#define XREG_CP12 12 +#define XREG_CP13 13 +#define XREG_CP14 14 +#define XREG_CP15 15 + +/* Coprocessor control register defines */ +#define XREG_CR0 cr0 +#define XREG_CR1 cr1 +#define XREG_CR2 cr2 +#define XREG_CR3 cr3 +#define XREG_CR4 cr4 +#define XREG_CR5 cr5 +#define XREG_CR6 cr6 +#define XREG_CR7 cr7 +#define XREG_CR8 cr8 +#define XREG_CR9 cr9 +#define XREG_CR10 cr10 +#define XREG_CR11 cr11 +#define XREG_CR12 cr12 +#define XREG_CR13 cr13 +#define XREG_CR14 cr14 +#define XREG_CR15 cr15 + +/* Current Processor Status Register (CPSR) Bits */ +#define XREG_CPSR_THUMB_MODE 0x20U +#define XREG_CPSR_MODE_BITS 0x1FU +#define XREG_CPSR_SYSTEM_MODE 0x1FU +#define XREG_CPSR_UNDEFINED_MODE 0x1BU +#define XREG_CPSR_DATA_ABORT_MODE 0x17U +#define XREG_CPSR_SVC_MODE 0x13U +#define XREG_CPSR_IRQ_MODE 0x12U +#define XREG_CPSR_FIQ_MODE 0x11U +#define XREG_CPSR_USER_MODE 0x10U + +#define XREG_CPSR_IRQ_ENABLE 0x80U +#define XREG_CPSR_FIQ_ENABLE 0x40U + +#define XREG_CPSR_N_BIT 0x80000000U +#define XREG_CPSR_Z_BIT 0x40000000U +#define XREG_CPSR_C_BIT 0x20000000U +#define XREG_CPSR_V_BIT 0x10000000U + +/*MPU region definitions*/ +#define REGION_32B 0x00000004U +#define REGION_64B 0x00000005U +#define REGION_128B 0x00000006U +#define REGION_256B 0x00000007U +#define REGION_512B 0x00000008U +#define REGION_1K 0x00000009U +#define REGION_2K 0x0000000AU +#define REGION_4K 0x0000000BU +#define REGION_8K 0x0000000CU +#define REGION_16K 0x0000000DU +#define REGION_32K 0x0000000EU +#define REGION_64K 0x0000000FU +#define REGION_128K 0x00000010U +#define REGION_256K 0x00000011U +#define REGION_512K 0x00000012U +#define REGION_1M 0x00000013U +#define REGION_2M 0x00000014U +#define REGION_4M 0x00000015U +#define REGION_8M 0x00000016U +#define REGION_16M 0x00000017U +#define REGION_32M 0x00000018U +#define REGION_64M 0x00000019U +#define REGION_128M 0x0000001AU +#define REGION_256M 0x0000001BU +#define REGION_512M 0x0000001CU +#define REGION_1G 0x0000001DU +#define REGION_2G 0x0000001EU +#define REGION_4G 0x0000001FU + +#define REGION_EN 0x00000001U + + + +#define SHAREABLE 0x00000004U /*shareable */ +#define STRONG_ORDERD_SHARED 0x00000000U /*strongly ordered, always shareable*/ + +#define DEVICE_SHARED 0x00000001U /*device, shareable*/ +#define DEVICE_NONSHARED 0x00000010U /*device, non shareable*/ + +#define NORM_NSHARED_WT_NWA 0x00000002U /*Outer and Inner write-through, no write-allocate non-shareable*/ +#define NORM_SHARED_WT_NWA 0x00000006U /*Outer and Inner write-through, no write-allocate shareable*/ + +#define NORM_NSHARED_WB_NWA 0x00000003U /*Outer and Inner write-back, no write-allocate non shareable*/ +#define NORM_SHARED_WB_NWA 0x00000007U /*Outer and Inner write-back, no write-allocate shareable*/ + +#define NORM_NSHARED_NCACHE 0x00000008U /*Outer and Inner Non cacheable non shareable*/ +#define NORM_SHARED_NCACHE 0x0000000CU /*Outer and Inner Non cacheable shareable*/ + +#define NORM_NSHARED_WB_WA 0x0000000BU /*Outer and Inner write-back non shared*/ +#define NORM_SHARED_WB_WA 0x0000000FU /*Outer and Inner write-back shared*/ + +/* inner and outer cache policies can be combined for different combinations */ + +#define NORM_IN_POLICY_NCACHE 0x00000020U /*inner non cacheable*/ +#define NORM_IN_POLICY_WB_WA 0x00000021U /*inner write back write allocate*/ +#define NORM_IN_POLICY_WT_NWA 0x00000022U /*inner write through no write allocate*/ +#define NORM_IN_POLICY_WB_NWA 0x00000023U /*inner write back no write allocate*/ + +#define NORM_OUT_POLICY_NCACHE 0x00000020U /*outer non cacheable*/ +#define NORM_OUT_POLICY_WB_WA 0x00000028U /*outer write back write allocate*/ +#define NORM_OUT_POLICY_WT_NWA 0x00000030U /*outer write through no write allocate*/ +#define NORM_OUT_POLICY_WB_NWA 0x00000038U /*outer write back no write allocate*/ + +#define NO_ACCESS (0x00000000U<<8U) /*No access*/ +#define PRIV_RW_USER_NA (0x00000001U<<8U) /*Privileged access only*/ +#define PRIV_RW_USER_RO (0x00000002U<<8U) /*Writes in User mode generate permission faults*/ +#define PRIV_RW_USER_RW (0x00000003U<<8U) /*Full Access*/ +#define PRIV_RO_USER_NA (0x00000005U<<8U) /*Privileged eead only*/ +#define PRIV_RO_USER_RO (0x00000006U<<8U) /*Privileged/User read-only*/ + +#define EXECUTE_NEVER (0x00000001U<<12U) /* Bit 12*/ + + +/* CP15 defines */ +#if defined (__GNUC__) || defined (__ICCARM__) +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" +#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" +#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" +#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" +#define XREG_CP15_MPU_TYPE "p15, 0, %0, c0, c0, 4" +#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" + +#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" +#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" +#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" +#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" +#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" +#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" +#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" + +#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" +#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" +#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" +#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" +#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" +#define XREG_CP15_INST_FEATURE_5 "p15, 0, %0, c0, c2, 5" + +#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" +#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" +#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" + +#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" +#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" +#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" + + + +#else /* RVCT */ +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0" +#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1" +#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2" +#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3" +#define XREG_CP15_MPU_TYPE "cp15:0:c0:c0:4" +#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5" + +#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0" +#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1" +#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2" +#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4" +#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5" +#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6" +#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7" + +#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0" +#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1" +#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2" +#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3" +#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4" +#define XREG_CP15_INST_FEATURE_5 "cp15:0:c0:c2:5" + +#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0" +#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1" +#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7" + +#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0" +#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1" +#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2" + +#endif + +/* XREG_CP15_CONTROL bit defines */ +#define XREG_CP15_CONTROL_TE_BIT 0x40000000U +#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U +#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U +#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U +#define XREG_CP15_CONTROL_EE_BIT 0x02000000U +#define XREG_CP15_CONTROL_HA_BIT 0x00020000U +#define XREG_CP15_CONTROL_RR_BIT 0x00004000U +#define XREG_CP15_CONTROL_V_BIT 0x00002000U +#define XREG_CP15_CONTROL_I_BIT 0x00001000U +#define XREG_CP15_CONTROL_Z_BIT 0x00000800U +#define XREG_CP15_CONTROL_SW_BIT 0x00000400U +#define XREG_CP15_CONTROL_B_BIT 0x00000080U +#define XREG_CP15_CONTROL_C_BIT 0x00000004U +#define XREG_CP15_CONTROL_A_BIT 0x00000002U +#define XREG_CP15_CONTROL_M_BIT 0x00000001U + +#if defined (__GNUC__) || defined (__ICCARM__) +/* C2 Register Defines */ +/* Not Used */ + +/* C3 Register Defines */ +/* Not Used */ + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" +#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" +#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" + +#define XREG_CP15_MPU_REG_BASEADDR "p15, 0, %0, c6, c1, 0" +#define XREG_CP15_MPU_REG_SIZE_EN "p15, 0, %0, c6, c1, 2" +#define XREG_CP15_MPU_REG_ACCESS_CTRL "p15, 0, %0, c6, c1, 4" + +#define XREG_CP15_MPU_MEMORY_REG_NUMBER "p15, 0, %0, c6, c2, 0" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" + +#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex R5. + */ +#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" +#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "p15, 0, %0, c7, c5, 7" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" +#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" + + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" +#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" + +#define XREG_CP15_INVAL_DC_ALL "p15, 0, %0, c15, c5, 0" +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex R5. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" +#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" + +#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" + +/* C8 Register Defines */ +/* Not Used */ + + +/* C9 Register Defines */ + +#define XREG_CP15_ATCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 1" +#define XREG_CP15_BTCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 0" +#define XREG_CP15_TCM_SELECTION "p15, 0, %0, c9, c2, 0" + +#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" +#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" +#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" +#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" +#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" +#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" +#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" +#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" + +#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" +#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" +#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" + +/* C10 Register Defines */ +/* Not used */ + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +/* Not used */ + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" +#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" +#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" +#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_SEC_AUX_CTRL "p15, 0, %0, c15, c0, 0" + + +#else +/* C2 Register Defines */ +/* Not Used */ + +/* C3 Register Defines */ +/* Not Used */ + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0" +#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0" +#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2" + +#define XREG_CP15_MPU_REG_BASEADDR "cp15:0:c6:c1:0" +#define XREG_CP15_MPU_REG_SIZE_EN "cp15:0:c6:c1:2" +#define XREG_CP15_MPU_REG_ACCESS_CTRL "cp15:0:c6:c1:4" + +#define XREG_CP15_MPU_MEMORY_REG_NUMBER "cp15:0:c6:c2:0" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "cp15:0:c7:c0:4" + +#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex R5. + */ +#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6" +#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "cp15:0:c7:c5:7" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1" +#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1" +#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2" + +#define XREG_CP15_INVAL_DC_ALL "cp15:0:c15:c5:0" + +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex R5. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4" +#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1" + +#define XREG_CP15_NOP2 "cp15:0:c7:c13:1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2" + +/* C8 Register Defines */ +/* Not Used */ + + +/* C9 Register Defines */ +#define XREG_CP15_ATCM_REG_SIZE_ADDR "cp15:0:c9:c1:1" +#define XREG_CP15_BTCM_REG_SIZE_ADDR "cp15:0:c9:c1:0" +#define XREG_CP15_TCM_SELECTION "cp15:0:c9:c2:0" + + +#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0" +#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1" +#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2" +#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3" +#define XREG_CP15_SW_INC "cp15:0:c9:c12:4" +#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0" +#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1" +#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2" + +#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0" +#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1" +#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2" + +/* C10 Register Defines */ +/* Not Used */ + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +/* Not Used */ + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1" +#define USER_RW_THREAD_PID "cp15:0:c13:c0:2" +#define USER_RO_THREAD_PID "cp15:0:c13:c0:3" +#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_SEC_AUX_CTRL "cp15:0:c15:c0:0" + +#endif + + +/* MPE register definitions */ +#define XREG_FPSID c0 +#define XREG_FPSCR c1 +#define XREG_MVFR1 c6 +#define XREG_MVFR0 c7 +#define XREG_FPEXC c8 +#define XREG_FPINST c9 +#define XREG_FPINST2 c10 + +/* FPSID bits */ +#define XREG_FPSID_IMPLEMENTER_BIT (24U) +#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (0X00000001U << 23U) +#define XREG_FPSID_ARCH_BIT (16U) +#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8U) +#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4U) +#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0U) +#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) + +/* FPSCR bits */ +#define XREG_FPSCR_N_BIT (0X00000001U << 31U) +#define XREG_FPSCR_Z_BIT (0X00000001U << 30U) +#define XREG_FPSCR_C_BIT (0X00000001U << 29U) +#define XREG_FPSCR_V_BIT (0X00000001U << 28U) +#define XREG_FPSCR_QC (0X00000001U << 27U) +#define XREG_FPSCR_AHP (0X00000001U << 26U) +#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) +#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) +#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) +#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) +#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) +#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) +#define XREG_FPSCR_RMODE_BIT (22U) +#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20U) +#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16U) +#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (0X00000001U << 7U) +#define XREG_FPSCR_IXC (0X00000001U << 4U) +#define XREG_FPSCR_UFC (0X00000001U << 3U) +#define XREG_FPSCR_OFC (0X00000001U << 2U) +#define XREG_FPSCR_DZC (0X00000001U << 1U) +#define XREG_FPSCR_IOC (0X00000001U << 0U) + +/* MVFR0 bits */ +#define XREG_MVFR0_RMODE_BIT (28U) +#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24U) +#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20U) +#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16U) +#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (12U) +#define XREG_MVFR0_EXEC_TRAP_MASK (0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8U) +#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4U) +#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0U) +#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) + +/* FPEXC bits */ +#define XREG_FPEXC_EX (0X00000001U << 31U) +#define XREG_FPEXC_EN (0X00000001U << 30U) +#define XREG_FPEXC_DEX (0X00000001U << 29U) + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XREG_CORTEXR5_H */ diff --git a/lib/bsp/standalone/src/cortexr5/xstatus.h b/lib/bsp/standalone/src/cortexr5/xstatus.h new file mode 100644 index 00000000..2737c63d --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xstatus.h @@ -0,0 +1,441 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xstatus.h +* +* This file contains Xilinx software status codes. Status codes have their +* own data type called int. These codes are used throughout the Xilinx +* device drivers. +* +******************************************************************************/ + +#ifndef XSTATUS_H /* prevent circular inclusions */ +#define XSTATUS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/*********************** Common statuses 0 - 500 *****************************/ + +#define XST_SUCCESS 0L +#define XST_FAILURE 1L +#define XST_DEVICE_NOT_FOUND 2L +#define XST_DEVICE_BLOCK_NOT_FOUND 3L +#define XST_INVALID_VERSION 4L +#define XST_DEVICE_IS_STARTED 5L +#define XST_DEVICE_IS_STOPPED 6L +#define XST_FIFO_ERROR 7L /* an error occurred during an + operation with a FIFO such as + an underrun or overrun, this + error requires the device to + be reset */ +#define XST_RESET_ERROR 8L /* an error occurred which requires + the device to be reset */ +#define XST_DMA_ERROR 9L /* a DMA error occurred, this error + typically requires the device + using the DMA to be reset */ +#define XST_NOT_POLLED 10L /* the device is not configured for + polled mode operation */ +#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put + the specified data into */ +#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough + to hold the expected data */ +#define XST_NO_DATA 13L /* there was no data available */ +#define XST_REGISTER_ERROR 14L /* a register did not contain the + expected value */ +#define XST_INVALID_PARAM 15L /* an invalid parameter was passed + into the function */ +#define XST_NOT_SGDMA 16L /* the device is not configured for + scatter-gather DMA operation */ +#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ +#define XST_NO_CALLBACK 18L /* a callback has not yet been + registered */ +#define XST_NO_FEATURE 19L /* device is not configured with + the requested feature */ +#define XST_NOT_INTERRUPT 20L /* device is not configured for + interrupt mode operation */ +#define XST_DEVICE_BUSY 21L /* device is busy */ +#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device + have maxed out */ +#define XST_IS_STARTED 23L /* used when part of device is + already started i.e. + sub channel */ +#define XST_IS_STOPPED 24L /* used when part of device is + already stopped i.e. + sub channel */ +#define XST_DATA_LOST 26L /* driver defined error */ +#define XST_RECV_ERROR 27L /* generic receive error */ +#define XST_SEND_ERROR 28L /* generic transmit error */ +#define XST_NOT_ENABLED 29L /* a requested service is not + available because it has not + been enabled */ + +/***************** Utility Component statuses 401 - 500 *********************/ + +#define XST_MEMTEST_FAILED 401L /* memory test failed */ + + +/***************** Common Components statuses 501 - 1000 *********************/ + +/********************* Packet Fifo statuses 501 - 510 ************************/ + +#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ +#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ +#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value + was invalid after reset */ +#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */ +#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting + * empty and full simultaneously + */ + +/************************** DMA statuses 511 - 530 ***************************/ + +#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer + failed */ +#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value + was invalid after reset */ +#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains + no buffer descriptors ready + to be processed */ +#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ +#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ +#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of + the scatter gather list are + being used */ +#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer + descriptor which is to be + copied over in the scatter + list is locked */ +#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been + put into the scatter gather + list to be commited */ +#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold + specified was larger than the + total # of buffer descriptors + in the scatter gather list */ +#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has + already been created */ +#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has + been created */ +#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was + being started was not committed + to the list */ +#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start + has already been used by the + hardware so it can't be reused + */ +#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access + error */ +#define XST_DMA_BD_ERROR 527L /* general buffer descriptor + error */ + +/************************** IPIF statuses 531 - 550 ***************************/ + +#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width + was passed into the function */ +#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at + reset was not valid */ +#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt + status register did not read + back correctly */ +#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status + register did not reset when + acked */ +#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable + register was not updated when + other registers changed */ +#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt + status register did not read + back correctly */ +#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register + did not reset when acked */ +#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was + not updated correctly when other + registers changed */ +#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending + register did not indicate the + expected value */ +#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register + did not indicate the expected + value */ +#define XST_IPIF_ERROR 541L /* generic ipif error */ + +/****************** Device specific statuses 1001 - 4095 *********************/ + +/********************* Ethernet statuses 1001 - 1050 *************************/ + +#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough + * to hold the minimum number of + * buffers or descriptors */ +#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ +#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ +#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ +#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */ +#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */ +#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late + * collision on polled send */ + +/*********************** UART statuses 1051 - 1075 ***************************/ +#define XST_UART + +#define XST_UART_INIT_ERROR 1051L +#define XST_UART_START_ERROR 1052L +#define XST_UART_CONFIG_ERROR 1053L +#define XST_UART_TEST_FAIL 1054L +#define XST_UART_BAUD_ERROR 1055L +#define XST_UART_BAUD_RANGE 1056L + + +/************************ IIC statuses 1076 - 1100 ***************************/ + +#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ +#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ +#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ + /* general call address */ +#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ + /* value after reset not valid */ +#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ + /* value after reset not valid */ +#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ + /* didn't return value written */ +#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ + /* didn't return value written */ +#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ + /* didn't return written value */ +#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ + +/*********************** ATMC statuses 1101 - 1125 ***************************/ + +#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM + controller hit the max value + which requires the statistics + to be cleared */ + +/*********************** Flash statuses 1126 - 1150 **************************/ + +#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming + */ +#define XST_FLASH_READY 1127L /* Flash is ready for commands */ +#define XST_FLASH_ERROR 1128L /* Flash had detected an internal + error. Use XFlash_DeviceControl + to retrieve device specific codes + */ +#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state + */ +#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state + */ +#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by + driver */ +#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ +#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ +#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation + aborted due to a timeout */ +#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its + addressible range */ +#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ +#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from + write/erase function with + XFL_NON_BLOCKING_WRITE/ERASE + option cleared */ +#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ + +/*********************** SPI statuses 1151 - 1175 ****************************/ + +#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ +#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ +#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ +#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ +#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ +#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being + * selected */ +#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ +#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only + */ +#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ +#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */ +#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */ + +#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */ + +/********************** OPB Arbiter statuses 1176 - 1200 *********************/ + +#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either + * one master assigned to two or more + * priorities, or one master not + * assigned to any priority + */ +#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the + * priority levels without first + * suspending the use of priority + * levels + */ +#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but + * bus parking was not enabled + */ +#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed + * priority mode to allow the + * priorities to be changed + */ + +/************************ Intc statuses 1201 - 1225 **************************/ + +#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ +#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ + +/********************** TmrCtr statuses 1226 - 1250 **************************/ + +#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ + +/********************** WdtTb statuses 1251 - 1275 ***************************/ + +#define XST_WDTTB_TIMER_FAILED 1251L + +/********************** PlbArb statuses 1276 - 1300 **************************/ + +#define XST_PLBARB_FAIL_SELFTEST 1276L + +/********************** Plb2Opb statuses 1301 - 1325 *************************/ + +#define XST_PLB2OPB_FAIL_SELFTEST 1301L + +/********************** Opb2Plb statuses 1326 - 1350 *************************/ + +#define XST_OPB2PLB_FAIL_SELFTEST 1326L + +/********************** SysAce statuses 1351 - 1360 **************************/ + +#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ + +/********************** PCI Bridge statuses 1361 - 1375 **********************/ + +#define XST_PCI_INVALID_ADDRESS 1361L + +/********************** FlexRay constants 1400 - 1409 *************************/ + +#define XST_FR_TX_ERROR 1400 +#define XST_FR_TX_BUSY 1401 +#define XST_FR_BUF_LOCKED 1402 +#define XST_FR_NO_BUF 1403 + +/****************** USB constants 1410 - 1420 *******************************/ + +#define XST_USB_ALREADY_CONFIGURED 1410 +#define XST_USB_BUF_ALIGN_ERROR 1411 +#define XST_USB_NO_DESC_AVAILABLE 1412 +#define XST_USB_BUF_TOO_BIG 1413 +#define XST_USB_NO_BUF 1414 + +/****************** HWICAP constants 1421 - 1429 *****************************/ + +#define XST_HWICAP_WRITE_DONE 1421 + + +/****************** AXI VDMA constants 1430 - 1440 *****************************/ + +#define XST_VDMA_MISMATCH_ERROR 1430 + +/*********************** NAND Flash statuses 1441 - 1459 *********************/ + +#define XST_NAND_BUSY 1441L /* Flash is erasing or + * programming + */ +#define XST_NAND_READY 1442L /* Flash is ready for commands + */ +#define XST_NAND_ERROR 1443L /* Flash had detected an + * internal error. + */ +#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by + * driver + */ +#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported + */ +#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase + * operation aborted due to a + * timeout + */ +#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its + * addressible range + */ +#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error + */ +#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter + * page of the device + */ +#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error + */ + +#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected + */ + +/**************************** Type Definitions *******************************/ + +typedef int XStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/cortexr5/xtime_l.c b/lib/bsp/standalone/src/cortexr5/xtime_l.c new file mode 100644 index 00000000..1eb1dc37 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xtime_l.c @@ -0,0 +1,110 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xtime_l.c +* +* This file contains low level functions to get/set time from the Global Timer +* register in the ARM Cortex R5 core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 5.00 	pkp  08/29/14 First release
+*
+* +* @note None. +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xtime_l.h" +#include "xpseudo_asm.h" +#include "xil_assert.h" +#include "xil_io.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/**************************************************************************** +* +* Set the time in the Global Timer Counter Register. +* +* @param Value to be written to the Global Timer Counter Register. +* +* @return None. +* +* @note In multiprocessor environment reference time will reset/lost for +* all processors, when this function called by any one processor. +* +****************************************************************************/ +void XTime_SetTime(XTime Xtime_Global) +{ + + +} + +/**************************************************************************** +* +* Get the time from the Global Timer Counter Register. +* +* @param Pointer to the location to be updated with the time. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void XTime_GetTime(XTime *Xtime_Global) +{ + *Xtime_Global = Xil_In32(TTC3_BASEADDR+0x00000018U); +} diff --git a/lib/bsp/standalone/src/cortexr5/xtime_l.h b/lib/bsp/standalone/src/cortexr5/xtime_l.h new file mode 100644 index 00000000..7e386126 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xtime_l.h @@ -0,0 +1,87 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xtime_l.h +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 5.00 	pkp	   05/29/14 First release
+*
+* +* @note None. +* +******************************************************************************/ + +#ifndef XTIME_H /* prevent circular inclusions */ +#define XTIME_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xparameters.h" +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Constant Definitions *****************************/ + +#define COUNTS_PER_SECOND 0x0005F5E1U + +#define TTC3_BASEADDR 0xFF140000U +/**************************** Type Definitions *******************************/ + +typedef u32 XTime; + +void XTime_SetTime(XTime Xtime_Global); +void XTime_GetTime(XTime *Xtime_Global); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XTIME_H */ diff --git a/lib/bsp/standalone/src/microblaze/Makefile b/lib/bsp/standalone/src/microblaze/Makefile old mode 100755 new mode 100644 index a352a2a6..6fedb27d --- a/lib/bsp/standalone/src/microblaze/Makefile +++ b/lib/bsp/standalone/src/microblaze/Makefile @@ -1,37 +1,49 @@ ############################################################################### # -# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: +# This file contains confidential and proprietary information of Xilinx, Inc. +# and is protected under U.S. and international copyright and other +# intellectual property laws. # -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. +# DISCLAIMER +# This disclaimer is not a license and does not grant any rights to the +# materials distributed herewith. Except as otherwise provided in a valid +# license issued to you by Xilinx, and to the maximum extent permitted by +# applicable law: +# (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +# XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +# OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +# NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +# and +# (2) Xilinx shall not be liable (whether in contract or tort, including +# negligence, or under any other theory of liability) for any loss or damage of +# any kind or nature related to, arising under or in connection with these +# materials, including for any direct, or any indirect, special, incidental, +# or consequential loss or damage (including loss of data, profits, goodwill, +# or any type of loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was reasonably foreseeable +# or Xilinx had been advised of the possibility of the same. # -# Use of the Software is limited solely to applications: -# (a) running on a Xilinx device, or -# (b) that interact with a Xilinx device through a bus or interconnect. +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail-safe, or for use in +# any application requiring fail-safe performance, such as life-support or +# safety devices or systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any other applications +# that could lead to death, personal injury, or severe property or environmental +# damage (individually and collectively, "Critical Applications"). +# Customer assumes the sole risk and liability of any use of Xilinx products in +# Critical Applications, subject only to applicable laws and regulations +# governing limitations on product liability. # -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -# SOFTWARE. +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +# AT ALL TIMES. # -# Except as contained in this notice, the name of the Xilinx shall not be used -# in advertising or otherwise to promote the sale, use or other dealings in -# this Software without prior written authorization from Xilinx. -###################################################################### +############################################################################### # The following are defined in config.make # LIBSOURCES - Based on if MicroBlaze support Exceptions -# LIBS - Do Build Profile Libraries +# LIBS - Do Build Profile Libraries include config.make AS=mb-as @@ -49,7 +61,7 @@ RELEASEDIR=../../../lib INCLUDEDIR=../../../include INCLUDES=-I./. -I${INCLUDEDIR} -OUTS = *.o +OUTS = *.o INCLUDEFILES=*.h @@ -58,7 +70,7 @@ libs: $(LIBS) standalone_libs: $(LIBSOURCES) echo "Compiling standalone"; $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^ - $(AR) -r ${RELEASEDIR}/${LIB} ${OUTS} + $(AR) -r ${RELEASEDIR}/${LIB} ${OUTS} profile_libs: $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" libs diff --git a/lib/bsp/standalone/src/microblaze/_exit.c b/lib/bsp/standalone/src/microblaze/_exit.c old mode 100755 new mode 100644 index 37673489..fc0ab8cc --- a/lib/bsp/standalone/src/microblaze/_exit.c +++ b/lib/bsp/standalone/src/microblaze/_exit.c @@ -1,41 +1,57 @@ /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ #include +#include "xil_types.h" +void _exit (sint32 status); /* _exit - Simple implementation. Does not return. */ -void _exit (int status) +void _exit (sint32 status) { (void) status; - while (1); + while (1) + { + ; + } } diff --git a/lib/bsp/standalone/src/microblaze/errno.c b/lib/bsp/standalone/src/microblaze/errno.c old mode 100755 new mode 100644 index 9fa8f6a3..3d6fb202 --- a/lib/bsp/standalone/src/microblaze/errno.c +++ b/lib/bsp/standalone/src/microblaze/errno.c @@ -4,9 +4,11 @@ #include #include +#include "xil_types.h" +sint32 * __errno (void); -int * -__errno () +sint32 * +__errno (void) { return &_REENT->_errno; } diff --git a/lib/bsp/standalone/src/microblaze/fcntl.c b/lib/bsp/standalone/src/microblaze/fcntl.c old mode 100755 new mode 100644 index 1ee9a86e..257cee56 --- a/lib/bsp/standalone/src/microblaze/fcntl.c +++ b/lib/bsp/standalone/src/microblaze/fcntl.c @@ -1,10 +1,12 @@ #include +#include "xil_types.h" +sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg); /* * fcntl -- Manipulate a file descriptor. * We don't have a filesystem, so we do nothing. */ -int fcntl (int fd, int cmd, long arg) +sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg) { (void) fd; (void) cmd; diff --git a/lib/bsp/standalone/src/microblaze/fsl.h b/lib/bsp/standalone/src/microblaze/fsl.h old mode 100755 new mode 100644 index 2215732c..0d84e7a3 --- a/lib/bsp/standalone/src/microblaze/fsl.h +++ b/lib/bsp/standalone/src/microblaze/fsl.h @@ -1,5 +1,5 @@ -#ifndef _FSL_H -#define _FSL_H +#ifndef FSL_H +#define FSL_H #include "mb_interface.h" /* Legacy reasons. We just have to include this guy who defines the FSL stuff */ @@ -8,7 +8,7 @@ extern "C" { #endif /* Extended FSL macros. These now replace all of the previous FSL macros */ -#define FSL_DEFAULT +#define FSL_DEFAULT #define FSL_NONBLOCKING n #define FSL_EXCEPTION e #define FSL_CONTROL c @@ -44,5 +44,5 @@ extern "C" { #ifdef __cplusplus } #endif -#endif /* _FSL_H */ +#endif /* FSL_H */ diff --git a/lib/bsp/standalone/src/microblaze/hw_exception_handler.S b/lib/bsp/standalone/src/microblaze/hw_exception_handler.S old mode 100755 new mode 100644 index a628ad33..9ce4ffc7 --- a/lib/bsp/standalone/src/microblaze/hw_exception_handler.S +++ b/lib/bsp/standalone/src/microblaze/hw_exception_handler.S @@ -1,35 +1,46 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ -/* +/****************************************************************************** * Microblaze HW Exception Handler * - Non self-modifying exception handler for the following exception conditions * - Unalignment @@ -38,7 +49,7 @@ * - Illegal instruction opcode * - Divide-by-zero * - Stack protection violation - */ + *******************************************************************************/ #include "microblaze_exceptions_g.h" #include "xparameters.h" @@ -46,129 +57,129 @@ /* Helpful Macros */ #define EX_HANDLER_STACK_SIZ (4*21) #define RMSR_OFFSET (20 * 4) -#define R17_OFFSET (0) +#define R17_OFFSET (0) #define REG_OFFSET(regnum) (4 * (regnum + 1)) #define NUM_TO_REG(num) r ## num #define R3_TO_STACK(regnum) swi r3, r1, REG_OFFSET(regnum) -#define R3_FROM_STACK(regnum) lwi r3, r1, REG_OFFSET(regnum) +#define R3_FROM_STACK(regnum) lwi r3, r1, REG_OFFSET(regnum) #define PUSH_REG(regnum) swi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum) #define POP_REG(regnum) lwi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum) - + /* Uses r5 */ #define PUSH_MSR \ mfs r5, rmsr; \ swi r5, r1, RMSR_OFFSET; - + #define PUSH_MSR_AND_ENABLE_EXC \ mfs r5, rmsr; \ swi r5, r1, RMSR_OFFSET; \ ori r5, r5, 0x100; /* Turn ON the EE bit*/ \ mts rmsr, r5; - + /* Uses r5 */ #define POP_MSR \ lwi r5, r1, RMSR_OFFSET; \ - mts rmsr, r5; + mts rmsr, r5; -/* Push r17 */ +/* Push r17 */ #define PUSH_R17 swi r17, r1, R17_OFFSET -/* Pop r17 */ +/* Pop r17 */ #define POP_R17 lwi r17, r1, R17_OFFSET - + #define LWREG_NOP \ bri ex_handler_unhandled; \ nop; #define SWREG_NOP \ bri ex_handler_unhandled; \ - nop; - + nop; + /* r3 is the source */ #define R3_TO_LWREG_V(regnum) \ R3_TO_STACK (regnum); \ - bri ex_handler_done; + bri ex_handler_done; /* r3 is the source */ #define R3_TO_LWREG(regnum) \ or NUM_TO_REG (regnum), r0, r3; \ - bri ex_handler_done; + bri ex_handler_done; -/* r3 is the target */ +/* r3 is the target */ #define SWREG_TO_R3_V(regnum) \ R3_FROM_STACK (regnum); \ - bri ex_sw_tail; - -/* r3 is the target */ + bri ex_sw_tail; + +/* r3 is the target */ #define SWREG_TO_R3(regnum) \ or r3, r0, NUM_TO_REG (regnum); \ - bri ex_sw_tail; + bri ex_sw_tail; -/* regnum is the source */ +/* regnum is the source */ #define FP_EX_OPB_SAVE(regnum) \ swi NUM_TO_REG (regnum), r0, mb_fpex_op_b; \ nop; \ - bri handle_fp_ex_opa; + bri handle_fp_ex_opa; -/* regnum is the source */ +/* regnum is the source */ #define FP_EX_OPB_SAVE_V(regnum) \ R3_FROM_STACK (regnum); \ swi r3, r0, mb_fpex_op_b; \ - bri handle_fp_ex_opa; - -/* regnum is the source */ + bri handle_fp_ex_opa; + +/* regnum is the source */ #define FP_EX_OPA_SAVE(regnum) \ swi NUM_TO_REG (regnum), r0, mb_fpex_op_a; \ nop; \ - bri handle_fp_ex_done; - -/* regnum is the source */ + bri handle_fp_ex_done; + +/* regnum is the source */ #define FP_EX_OPA_SAVE_V(regnum) \ R3_FROM_STACK (regnum); \ swi r3, r0, mb_fpex_op_a; \ - bri handle_fp_ex_done; + bri handle_fp_ex_done; #define FP_EX_UNHANDLED \ bri fp_ex_unhandled; \ nop; \ nop; -/* ESR masks */ +/* ESR masks */ #define ESR_EXC_MASK 0x0000001F #define ESR_REG_MASK 0x000003E0 #define ESR_LW_SW_MASK 0x00000400 #define ESR_WORD_MASK 0x00000800 #define ESR_DS_MASK 0x00001000 - + /* Extern declarations */ .extern XNullHandler #ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */ - -/* + +/* * hw_exception_handler - Handler for unaligned exceptions - * Exception handler notes: + * Exception handler notes: * - Does not handle exceptions other than unaligned exceptions * - Does not handle exceptions during load into r17, r1, r0. * - Does not handle exceptions during store from r17 (cannot be done) and r1 (slows down common case) * * Relevant register structures - * - * EAR - |----|----|----|----|----|----|----|----| - * - < ## 32 bit faulting address ## > - * - * ESR - |----|----|----|----|----| - | - |-----|-----| + * + * EAR - |----|----|----|----|----|----|----|----| + * - < ## 32 bit faulting address ## > + * + * ESR - |----|----|----|----|----| - | - |-----|-----| * - W S REG EXC * - * + * * STACK FRAME STRUCTURE * --------------------- * * +-------------+ + 0 * | r17 | - * +-------------+ + 4 + * +-------------+ + 4 * | Args for | * | next func | * +-------------+ + 8 @@ -179,19 +190,19 @@ * | . | * | r18 | * +-------------+ + 80 - * | MSR | - * +-------------+ + 84 - * | . | - * | . | - */ + * | MSR | + * +-------------+ + 84 + * | . | + * | . | + */ - -.global _hw_exception_handler -.section .text + +.global _hw_exception_handler +.section .text .align 2 .ent _hw_exception_handler -.type _hw_exception_handler, @function -_hw_exception_handler: +.type _hw_exception_handler, @function +_hw_exception_handler: #if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) /* Immediately halt for stack protection violation exception without using any stack */ @@ -207,33 +218,33 @@ ex_handler_not_sp_violation: #endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */ addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */ - PUSH_REG(3); - PUSH_REG(4); - PUSH_REG(5); + PUSH_REG(3); + PUSH_REG(4); + PUSH_REG(5); PUSH_REG(6); #ifdef MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS mfs r6, resr; andi r6, r6, ESR_DS_MASK; beqi r6, ex_handler_no_ds; mfs r17, rbtr; -ex_handler_no_ds: +ex_handler_no_ds: #endif - PUSH_R17; + PUSH_R17; PUSH_MSR_AND_ENABLE_EXC; /* Exceptions enabled here. This will allow nested exceptions */ - - mfs r3, resr; + + mfs r3, resr; andi r5, r3, ESR_EXC_MASK; /* Extract ESR[EXC] */ #ifndef NO_UNALIGNED_EXCEPTIONS - xori r6, r5, 1; /* 00001 = Unaligned Exception */ - bnei r6, handle_ex_regular; + xori r6, r5, 1; /* 00001 = Unaligned Exception */ + bnei r6, handle_ex_regular; la r4, r0, MB_ExceptionVectorTable; /* Check if user has registered an unaligned exception handler */ - lwi r4, r4, 8; + lwi r4, r4, 8; la r6, r0, XNullHandler; /* If exceptionvectortable entry is still XNullHandler, use */ xor r6, r4, r6; /* the default exception handler */ - beqi r6, handle_unaligned_ex ; - -handle_ex_regular: + beqi r6, handle_unaligned_ex ; + +handle_ex_regular: #endif /* ! NO_UNALIGNED_EXCEPTIONS */ #if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) @@ -241,29 +252,29 @@ handle_ex_regular: beqi r6, handle_fp_ex; /* Go and decode the FP exception */ #endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */ -handle_other_ex: /* Handle Other exceptions here */ - ori r6, r0, 20; +handle_other_ex: /* Handle Other exceptions here */ + ori r6, r0, 20; cmp r6, r5, r6; /* >= 20 are exceptions we do not handle. */ blei r6, ex_handler_unhandled; ori r6, r0, 7; cmp r6, r5, r6; /* Convert MMU exception indices into an ordinal of 7 */ bgti r6, handle_other_ex_tail; - ori r5, r0, 0x7; - -handle_other_ex_tail: + ori r5, r0, 0x7; + +handle_other_ex_tail: PUSH_REG(7); /* Save other volatiles before we make procedure calls below */ - PUSH_REG(8); - PUSH_REG(9); - PUSH_REG(10); - PUSH_REG(11); + PUSH_REG(8); + PUSH_REG(9); + PUSH_REG(10); + PUSH_REG(11); PUSH_REG(12); PUSH_REG(15); - PUSH_REG(18); + PUSH_REG(18); la r4, r0, MB_ExceptionVectorTable; /* Load the Exception vector table base address */ addk r7, r5, r5; /* Calculate exception vector offset = r5 * 8 */ - addk r7, r7, r7; + addk r7, r7, r7; addk r7, r7, r7; addk r7, r7, r4; /* Get pointer to exception vector */ lwi r5, r7, 4; /* Load argument to exception handler from table */ @@ -271,20 +282,20 @@ handle_other_ex_tail: brald r15, r7; /* Branch to handler */ nop; - + POP_REG(7); /* Restore other volatiles */ - POP_REG(8); - POP_REG(9); - POP_REG(10); - POP_REG(11); + POP_REG(8); + POP_REG(9); + POP_REG(10); + POP_REG(11); POP_REG(12); POP_REG(15); - POP_REG(18); + POP_REG(18); - bri ex_handler_done; /* Complete exception handling */ + bri ex_handler_done; /* Complete exception handling */ #ifndef NO_UNALIGNED_EXCEPTIONS -handle_unaligned_ex: +handle_unaligned_ex: andi r6, r3, ESR_REG_MASK; /* Mask and extract the register operand */ srl r6, r6; /* r6 >> 5 */ srl r6, r6; @@ -292,14 +303,14 @@ handle_unaligned_ex: srl r6, r6; srl r6, r6; sbi r6, r0, ex_reg_op; /* Store the register operand in a temporary location */ - mfs r4, rear; + mfs r4, rear; andi r6, r3, ESR_LW_SW_MASK; /* Extract ESR[S] */ bnei r6, ex_sw; -ex_lw: +ex_lw: andi r6, r3, ESR_WORD_MASK; /* Extract ESR[W] */ beqi r6, ex_lhw; lbui r5, r4, 0; /* Exception address in r4 */ - sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */ + sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */ lbui r5, r4, 1; sbi r5, r0, ex_tmp_data_loc_1; lbui r5, r4, 2; @@ -307,32 +318,32 @@ ex_lw: lbui r5, r4, 3; sbi r5, r0, ex_tmp_data_loc_3; lwi r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */ - bri ex_lw_tail; -ex_lhw: + bri ex_lw_tail; +ex_lhw: lbui r5, r4, 0; /* Exception address in r4 */ - sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */ - lbui r5, r4, 1; + sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */ + lbui r5, r4, 1; sbi r5, r0, ex_tmp_data_loc_1; lhui r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */ ex_lw_tail: lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */ la r6, r0, lw_table; /* Form load_word jump table offset (lw_table + (8 * regnum)) */ - addk r5, r5, r5; + addk r5, r5, r5; addk r5, r5, r5; addk r5, r5, r5; addk r5, r5, r6; bra r5; ex_lw_end: /* Exception handling of load word, ends */ -ex_sw: +ex_sw: lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */ la r6, r0, sw_table; /* Form store_word jump table offset (sw_table + (8 * regnum)) */ - add r5, r5, r5; + add r5, r5, r5; add r5, r5, r5; add r5, r5, r5; add r5, r5, r6; bra r5; -ex_sw_tail: - mfs r6, resr; +ex_sw_tail: + mfs r6, resr; andi r6, r6, ESR_WORD_MASK; /* Extract ESR[W] */ beqi r6, ex_shw; swi r3, r0, ex_tmp_data_loc_0; @@ -341,13 +352,13 @@ ex_sw_tail: lbui r3, r0, ex_tmp_data_loc_1; sbi r3, r4, 1; lbui r3, r0, ex_tmp_data_loc_2; - sbi r3, r4, 2; + sbi r3, r4, 2; lbui r3, r0, ex_tmp_data_loc_3; - sbi r3, r4, 3; + sbi r3, r4, 3; bri ex_handler_done; -ex_shw: +ex_shw: swi r3, r0, ex_tmp_data_loc_0; /* Store the lower half-word, byte-by-byte into destination address */ - + #ifdef __LITTLE_ENDIAN__ lbui r3, r0, ex_tmp_data_loc_0; #else @@ -361,7 +372,7 @@ ex_shw: #endif sbi r3, r4, 1; ex_sw_end: /* Exception handling of store word, ends. */ - bri ex_handler_done; + bri ex_handler_done; #endif /* !NO_UNALIGNED_EXCEPTIONS */ #if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) @@ -371,76 +382,76 @@ handle_fp_ex: handle_fp_ex_opb: la r6, r0, fp_table_opb; /* Decode opB and store its value in mb_fpex_op_b */ - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; andi r3, r4, 0x1F; add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */ add r3, r3, r3; add r5, r3, r3; add r5, r5, r3; add r5, r5, r6; - bra r5; + bra r5; handle_fp_ex_opa: la r6, r0, fp_table_opa; /* Decode opA and store its value in mb_fpex_op_a */ - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; - srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; andi r3, r4, 0x1F; add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */ add r3, r3, r3; add r5, r3, r3; add r5, r5, r3; add r5, r5, r6; - bra r5; + bra r5; handle_fp_ex_done: ori r5, r0, 6; /* Set exception number back to 6 */ - bri handle_other_ex_tail; - -fp_ex_unhandled: - bri 0; + bri handle_other_ex_tail; + +fp_ex_unhandled: + bri 0; #endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */ - + ex_handler_done: POP_R17; POP_MSR; - POP_REG(3); - POP_REG(4); - POP_REG(5); - POP_REG(6); + POP_REG(3); + POP_REG(4); + POP_REG(5); + POP_REG(6); rted r17, 0 - addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */ -ex_handler_unhandled: - bri 0 /* UNHANDLED. TRAP HERE */ -.end _hw_exception_handler + addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */ +ex_handler_unhandled: + bri 0 /* UNHANDLED. TRAP HERE */ +.end _hw_exception_handler -#ifndef NO_UNALIGNED_EXCEPTIONS +#ifndef NO_UNALIGNED_EXCEPTIONS -/* +/* * hw_exception_handler Jump Table * - Contains code snippets for each register that caused the unaligned exception. * - Hence exception handler is NOT self-modifying * - Separate table for load exceptions and store exceptions. * - Each table is of size: (8 * 32) = 256 bytes */ - + .section .text .align 4 lw_table: -lw_r0: R3_TO_LWREG (0); +lw_r0: R3_TO_LWREG (0); lw_r1: LWREG_NOP; lw_r2: R3_TO_LWREG (2); lw_r3: R3_TO_LWREG_V (3); @@ -451,30 +462,30 @@ lw_r7: R3_TO_LWREG (7); lw_r8: R3_TO_LWREG (8); lw_r9: R3_TO_LWREG (9); lw_r10: R3_TO_LWREG (10); -lw_r11: R3_TO_LWREG (11); +lw_r11: R3_TO_LWREG (11); lw_r12: R3_TO_LWREG (12); lw_r13: R3_TO_LWREG (13); -lw_r14: R3_TO_LWREG (14); -lw_r15: R3_TO_LWREG (15); -lw_r16: R3_TO_LWREG (16); +lw_r14: R3_TO_LWREG (14); +lw_r15: R3_TO_LWREG (15); +lw_r16: R3_TO_LWREG (16); lw_r17: LWREG_NOP; -lw_r18: R3_TO_LWREG (18); -lw_r19: R3_TO_LWREG (19); -lw_r20: R3_TO_LWREG (20); +lw_r18: R3_TO_LWREG (18); +lw_r19: R3_TO_LWREG (19); +lw_r20: R3_TO_LWREG (20); lw_r21: R3_TO_LWREG (21); lw_r22: R3_TO_LWREG (22); -lw_r23: R3_TO_LWREG (23); -lw_r24: R3_TO_LWREG (24); -lw_r25: R3_TO_LWREG (25); -lw_r26: R3_TO_LWREG (26); -lw_r27: R3_TO_LWREG (27); -lw_r28: R3_TO_LWREG (28); -lw_r29: R3_TO_LWREG (29); +lw_r23: R3_TO_LWREG (23); +lw_r24: R3_TO_LWREG (24); +lw_r25: R3_TO_LWREG (25); +lw_r26: R3_TO_LWREG (26); +lw_r27: R3_TO_LWREG (27); +lw_r28: R3_TO_LWREG (28); +lw_r29: R3_TO_LWREG (29); lw_r30: R3_TO_LWREG (30); lw_r31: R3_TO_LWREG (31); sw_table: -sw_r0: SWREG_TO_R3 (0); +sw_r0: SWREG_TO_R3 (0); sw_r1: SWREG_NOP; sw_r2: SWREG_TO_R3 (2); sw_r3: SWREG_TO_R3_V (3); @@ -485,128 +496,128 @@ sw_r7: SWREG_TO_R3 (7); sw_r8: SWREG_TO_R3 (8); sw_r9: SWREG_TO_R3 (9); sw_r10: SWREG_TO_R3 (10); -sw_r11: SWREG_TO_R3 (11); +sw_r11: SWREG_TO_R3 (11); sw_r12: SWREG_TO_R3 (12); sw_r13: SWREG_TO_R3 (13); -sw_r14: SWREG_TO_R3 (14); -sw_r15: SWREG_TO_R3 (15); -sw_r16: SWREG_TO_R3 (16); -sw_r17: SWREG_NOP; -sw_r18: SWREG_TO_R3 (18); -sw_r19: SWREG_TO_R3 (19); -sw_r20: SWREG_TO_R3 (20); +sw_r14: SWREG_TO_R3 (14); +sw_r15: SWREG_TO_R3 (15); +sw_r16: SWREG_TO_R3 (16); +sw_r17: SWREG_NOP; +sw_r18: SWREG_TO_R3 (18); +sw_r19: SWREG_TO_R3 (19); +sw_r20: SWREG_TO_R3 (20); sw_r21: SWREG_TO_R3 (21); sw_r22: SWREG_TO_R3 (22); -sw_r23: SWREG_TO_R3 (23); -sw_r24: SWREG_TO_R3 (24); -sw_r25: SWREG_TO_R3 (25); -sw_r26: SWREG_TO_R3 (26); -sw_r27: SWREG_TO_R3 (27); -sw_r28: SWREG_TO_R3 (28); -sw_r29: SWREG_TO_R3 (29); +sw_r23: SWREG_TO_R3 (23); +sw_r24: SWREG_TO_R3 (24); +sw_r25: SWREG_TO_R3 (25); +sw_r26: SWREG_TO_R3 (26); +sw_r27: SWREG_TO_R3 (27); +sw_r28: SWREG_TO_R3 (28); +sw_r29: SWREG_TO_R3 (29); sw_r30: SWREG_TO_R3 (30); sw_r31: SWREG_TO_R3 (31); /* Temporary data structures used in the handler */ .section .data .align 2 -ex_tmp_data_loc_0: +ex_tmp_data_loc_0: .byte 0 -ex_tmp_data_loc_1: +ex_tmp_data_loc_1: .byte 0 -ex_tmp_data_loc_2: +ex_tmp_data_loc_2: + .byte 0 +ex_tmp_data_loc_3: .byte 0 -ex_tmp_data_loc_3: - .byte 0 ex_reg_op: .byte 0 - + #endif /* ! NO_UNALIGNED_EXCEPTIONS */ - + #if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) -/* +/* * FP exception decode jump table. * - Contains code snippets for each register that could have been a source operand for an excepting FP instruction * - Hence exception handler is NOT self-modifying * - Separate table for opA and opB * - Each table is of size: (12 * 32) = 384 bytes */ - + .section .text .align 4 fp_table_opa: -opa_r0: FP_EX_OPA_SAVE (0); -opa_r1: FP_EX_UNHANDLED; -opa_r2: FP_EX_OPA_SAVE (2); -opa_r3: FP_EX_OPA_SAVE_V (3); -opa_r4: FP_EX_OPA_SAVE_V (4); -opa_r5: FP_EX_OPA_SAVE_V (5); -opa_r6: FP_EX_OPA_SAVE_V (6); -opa_r7: FP_EX_OPA_SAVE (7); -opa_r8: FP_EX_OPA_SAVE (8); -opa_r9: FP_EX_OPA_SAVE (9); -opa_r10: FP_EX_OPA_SAVE (10); -opa_r11: FP_EX_OPA_SAVE (11); -opa_r12: FP_EX_OPA_SAVE (12); -opa_r13: FP_EX_OPA_SAVE (13); -opa_r14: FP_EX_UNHANDLED; -opa_r15: FP_EX_UNHANDLED; -opa_r16: FP_EX_UNHANDLED; -opa_r17: FP_EX_UNHANDLED; -opa_r18: FP_EX_OPA_SAVE (18); -opa_r19: FP_EX_OPA_SAVE (19); -opa_r20: FP_EX_OPA_SAVE (20); -opa_r21: FP_EX_OPA_SAVE (21); -opa_r22: FP_EX_OPA_SAVE (22); -opa_r23: FP_EX_OPA_SAVE (23); -opa_r24: FP_EX_OPA_SAVE (24); -opa_r25: FP_EX_OPA_SAVE (25); -opa_r26: FP_EX_OPA_SAVE (26); -opa_r27: FP_EX_OPA_SAVE (27); -opa_r28: FP_EX_OPA_SAVE (28); -opa_r29: FP_EX_OPA_SAVE (29); -opa_r30: FP_EX_OPA_SAVE (30); -opa_r31: FP_EX_OPA_SAVE (31); +opa_r0: FP_EX_OPA_SAVE (0); +opa_r1: FP_EX_UNHANDLED; +opa_r2: FP_EX_OPA_SAVE (2); +opa_r3: FP_EX_OPA_SAVE_V (3); +opa_r4: FP_EX_OPA_SAVE_V (4); +opa_r5: FP_EX_OPA_SAVE_V (5); +opa_r6: FP_EX_OPA_SAVE_V (6); +opa_r7: FP_EX_OPA_SAVE (7); +opa_r8: FP_EX_OPA_SAVE (8); +opa_r9: FP_EX_OPA_SAVE (9); +opa_r10: FP_EX_OPA_SAVE (10); +opa_r11: FP_EX_OPA_SAVE (11); +opa_r12: FP_EX_OPA_SAVE (12); +opa_r13: FP_EX_OPA_SAVE (13); +opa_r14: FP_EX_UNHANDLED; +opa_r15: FP_EX_UNHANDLED; +opa_r16: FP_EX_UNHANDLED; +opa_r17: FP_EX_UNHANDLED; +opa_r18: FP_EX_OPA_SAVE (18); +opa_r19: FP_EX_OPA_SAVE (19); +opa_r20: FP_EX_OPA_SAVE (20); +opa_r21: FP_EX_OPA_SAVE (21); +opa_r22: FP_EX_OPA_SAVE (22); +opa_r23: FP_EX_OPA_SAVE (23); +opa_r24: FP_EX_OPA_SAVE (24); +opa_r25: FP_EX_OPA_SAVE (25); +opa_r26: FP_EX_OPA_SAVE (26); +opa_r27: FP_EX_OPA_SAVE (27); +opa_r28: FP_EX_OPA_SAVE (28); +opa_r29: FP_EX_OPA_SAVE (29); +opa_r30: FP_EX_OPA_SAVE (30); +opa_r31: FP_EX_OPA_SAVE (31); + +fp_table_opb: +opb_r0: FP_EX_OPB_SAVE (0); +opb_r1: FP_EX_UNHANDLED; +opb_r2: FP_EX_OPB_SAVE (2); +opb_r3: FP_EX_OPB_SAVE_V (3); +opb_r4: FP_EX_OPB_SAVE_V (4); +opb_r5: FP_EX_OPB_SAVE_V (5); +opb_r6: FP_EX_OPB_SAVE_V (6); +opb_r7: FP_EX_OPB_SAVE (7); +opb_r8: FP_EX_OPB_SAVE (8); +opb_r9: FP_EX_OPB_SAVE (9); +opb_r10: FP_EX_OPB_SAVE (10); +opb_r11: FP_EX_OPB_SAVE (11); +opb_r12: FP_EX_OPB_SAVE (12); +opb_r13: FP_EX_OPB_SAVE (13); +opb_r14: FP_EX_UNHANDLED; +opb_r15: FP_EX_UNHANDLED; +opb_r16: FP_EX_UNHANDLED; +opb_r17: FP_EX_UNHANDLED; +opb_r18: FP_EX_OPB_SAVE (18); +opb_r19: FP_EX_OPB_SAVE (19); +opb_r20: FP_EX_OPB_SAVE (20); +opb_r21: FP_EX_OPB_SAVE (21); +opb_r22: FP_EX_OPB_SAVE (22); +opb_r23: FP_EX_OPB_SAVE (23); +opb_r24: FP_EX_OPB_SAVE (24); +opb_r25: FP_EX_OPB_SAVE (25); +opb_r26: FP_EX_OPB_SAVE (26); +opb_r27: FP_EX_OPB_SAVE (27); +opb_r28: FP_EX_OPB_SAVE (28); +opb_r29: FP_EX_OPB_SAVE (29); +opb_r30: FP_EX_OPB_SAVE (30); +opb_r31: FP_EX_OPB_SAVE (31); -fp_table_opb: -opb_r0: FP_EX_OPB_SAVE (0); -opb_r1: FP_EX_UNHANDLED; -opb_r2: FP_EX_OPB_SAVE (2); -opb_r3: FP_EX_OPB_SAVE_V (3); -opb_r4: FP_EX_OPB_SAVE_V (4); -opb_r5: FP_EX_OPB_SAVE_V (5); -opb_r6: FP_EX_OPB_SAVE_V (6); -opb_r7: FP_EX_OPB_SAVE (7); -opb_r8: FP_EX_OPB_SAVE (8); -opb_r9: FP_EX_OPB_SAVE (9); -opb_r10: FP_EX_OPB_SAVE (10); -opb_r11: FP_EX_OPB_SAVE (11); -opb_r12: FP_EX_OPB_SAVE (12); -opb_r13: FP_EX_OPB_SAVE (13); -opb_r14: FP_EX_UNHANDLED; -opb_r15: FP_EX_UNHANDLED; -opb_r16: FP_EX_UNHANDLED; -opb_r17: FP_EX_UNHANDLED; -opb_r18: FP_EX_OPB_SAVE (18); -opb_r19: FP_EX_OPB_SAVE (19); -opb_r20: FP_EX_OPB_SAVE (20); -opb_r21: FP_EX_OPB_SAVE (21); -opb_r22: FP_EX_OPB_SAVE (22); -opb_r23: FP_EX_OPB_SAVE (23); -opb_r24: FP_EX_OPB_SAVE (24); -opb_r25: FP_EX_OPB_SAVE (25); -opb_r26: FP_EX_OPB_SAVE (26); -opb_r27: FP_EX_OPB_SAVE (27); -opb_r28: FP_EX_OPB_SAVE (28); -opb_r29: FP_EX_OPB_SAVE (29); -opb_r30: FP_EX_OPB_SAVE (30); -opb_r31: FP_EX_OPB_SAVE (31); - #endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */ - + #if defined(MICROBLAZE_FP_EXCEPTION_ENABLED) && defined(MICROBLAZE_FP_EXCEPTION_DECODE) /* This is where we store the opA and opB of the last excepting FP instruction */ -.section .data +.section .data .align 2 .global mb_fpex_op_a .global mb_fpex_op_b @@ -644,19 +655,18 @@ MB_ExceptionVectorTable: .long XNullHandler .long 6 /* -- FPU Exception -- */ .long XNullHandler - .long 7 /* -- MMU Exceptions -- */ + .long 7 /* -- MMU Exceptions -- */ #else /* Dummy exception handler, in case exceptions are not present in the processor */ -.global _hw_exception_handler -.section .text +.global _hw_exception_handler +.section .text .align 2 .ent _hw_exception_handler _hw_exception_handler: - bri 0; -.end _hw_exception_handler - + bri 0; +.end _hw_exception_handler + #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */ - diff --git a/lib/bsp/standalone/src/microblaze/mb_interface.h b/lib/bsp/standalone/src/microblaze/mb_interface.h old mode 100755 new mode 100644 index efc98aaa..d452ad10 --- a/lib/bsp/standalone/src/microblaze/mb_interface.h +++ b/lib/bsp/standalone/src/microblaze/mb_interface.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ @@ -54,22 +65,22 @@ extern void microblaze_register_exception_handler(u32 ExceptionId, Xil_Exception extern void microblaze_invalidate_icache(void); /* Invalidate the entire icache */ extern void microblaze_invalidate_dcache(void); /* Invalidate the entire dcache */ extern void microblaze_flush_dcache(void); /* Flush the whole dcache */ -extern void microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the icache */ -extern void microblaze_invalidate_dcache_range(unsigned int cacheaddr, unsigned int len); /* Invalidate a part of the dcache */ -extern void microblaze_flush_dcache_range(unsigned int cacheaddr, unsigned int len); /* Flush a part of the dcache */ +extern void microblaze_invalidate_icache_range(u32 cacheaddr, u32 len); /* Invalidate a part of the icache */ +extern void microblaze_invalidate_dcache_range(u32 cacheaddr, u32 len); /* Invalidate a part of the dcache */ +extern void microblaze_flush_dcache_range(u32 cacheaddr, u32 len); /* Flush a part of the dcache */ extern void microblaze_scrub(void); /* Scrub LMB and internal BRAM */ extern void microblaze_invalidate_cache_ext(void); /* Invalidate cache ext */ extern void microblaze_flush_cache_ext(void); /* Flush cache ext */ -extern void microblaze_flush_cache_ext_range(unsigned int cacheaddr, - unsigned int len); /* Flush cache ext range */ -extern void microblaze_invalidate_cache_ext_range(unsigned int cacheaddr, - unsigned int len); /* Invalidate cache ext range */ +extern void microblaze_flush_cache_ext_range(u32 cacheaddr, + u32 len); /* Flush cache ext range */ +extern void microblaze_invalidate_cache_ext_range(u32 cacheaddr, + u32 len); /* Invalidate cache ext range */ /* Deprecated */ -extern void microblaze_update_icache (int , int , int ) __attribute__((deprecated)); -extern void microblaze_init_icache_range (int , int ) __attribute__((deprecated)); -extern void microblaze_update_dcache (int , int , int ) __attribute__((deprecated)); -extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated)); +extern void microblaze_update_icache (s32 , s32 , s32 ) __attribute__((deprecated)); +extern void microblaze_init_icache_range (s32 , s32 ) __attribute__((deprecated)); +extern void microblaze_update_dcache (s32 , s32 , s32 ) __attribute__((deprecated)); +extern void microblaze_init_dcache_range (s32 , s32 ) __attribute__((deprecated)); /* necessary for pre-processor */ #define stringify(s) tostring(s) @@ -119,7 +130,7 @@ extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated "andi\t%0,%0,0x10" : "=d" (error)) /* Pseudo assembler instructions */ -#define clz(v) ({ unsigned int _rval; \ +#define clz(v) ({ u32 _rval; \ __asm__ __volatile__ ( \ "clz\t%0,%1\n" : "=d"(_rval): "d" (v) \ ); \ @@ -129,119 +140,119 @@ extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated #define mbar(mask) ({ __asm__ __volatile__ ("mbar\t" stringify(mask) ); }) #define mb_sleep() ({ __asm__ __volatile__ ("sleep\t"); }) -#define mb_swapb(v) ({ unsigned int _rval; \ +#define mb_swapb(v) ({ u32 _rval; \ __asm__ __volatile__ ( \ "swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \ ); \ _rval; \ }) -#define mb_swaph(v) ({ unsigned int _rval; \ +#define mb_swaph(v) ({ u32 _rval; \ __asm__ __volatile__ ( \ "swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \ ); \ _rval; \ }) -#define mfgpr(rn) ({ unsigned int _rval; \ +#define mfgpr(rn) ({ u32 _rval; \ __asm__ __volatile__ ( \ "or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfmsr() ({ unsigned int _rval; \ +#define mfmsr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rmsr\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfear() ({ unsigned int _rval; \ +#define mfear() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rear\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfesr() ({ unsigned int _rval; \ +#define mfesr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,resr\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mffsr() ({ unsigned int _rval; \ +#define mffsr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rfsr\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfpvr(rn) ({ unsigned int _rval; \ +#define mfpvr(rn) ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfbtr() ({ unsigned int _rval; \ +#define mfbtr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rbtr\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfedr() ({ unsigned int _rval; \ +#define mfedr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,redr\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfpid() ({ unsigned int _rval; \ +#define mfpid() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rpid\n" : "=d"(_rval)\ ); \ _rval; \ }) -#define mfzpr() ({ unsigned int _rval; \ +#define mfzpr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rzpr\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mftlbx() ({ unsigned int _rval; \ +#define mftlbx() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rtlbx\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mftlblo() ({ unsigned int _rval; \ +#define mftlblo() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rtlblo\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mftlbhi() ({ unsigned int _rval; \ +#define mftlbhi() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rtlbhi\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfslr() ({ unsigned int _rval; \ +#define mfslr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rslr\n" : "=d"(_rval) \ ); \ _rval; \ }) -#define mfshr() ({ unsigned int _rval; \ +#define mfshr() ({ u32 _rval; \ __asm__ __volatile__ ( \ "mfs\t%0,rshr\n" : "=d"(_rval) \ ); \ @@ -304,28 +315,28 @@ extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated ); \ }) -#define lwx(address) ({ unsigned int _rval; \ +#define lwx(address) ({ u32 _rval; \ __asm__ __volatile__ ( \ "lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \ ); \ _rval; \ }) -#define lwr(address) ({ unsigned int _rval; \ +#define lwr(address) ({ u32 _rval; \ __asm__ __volatile__ ( \ "lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \ ); \ _rval; \ }) -#define lhur(address) ({ unsigned int _rval; \ +#define lhur(address) ({ u32 _rval; \ __asm__ __volatile__ ( \ "lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \ ); \ _rval; \ }) -#define lbur(address) ({ unsigned int _rval; \ +#define lbur(address) ({ u32 _rval; \ __asm__ __volatile__ ( \ "lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \ ); \ @@ -353,12 +364,12 @@ extern void microblaze_init_dcache_range (int , int ) __attribute__((deprecated }) #define microblaze_getfpex_operand_a() ({ \ - extern unsigned int mb_fpex_op_a; \ + extern u32 mb_fpex_op_a; \ mb_fpex_op_a; \ }) #define microblaze_getfpex_operand_b() ({ \ - extern unsigned int mb_fpex_op_b; \ + extern u32 mb_fpex_op_b; \ mb_fpex_op_b; \ }) diff --git a/lib/bsp/standalone/src/microblaze/microblaze_disable_dcache.S b/lib/bsp/standalone/src/microblaze/microblaze_disable_dcache.S old mode 100755 new mode 100644 index e47160be..2699af05 --- a/lib/bsp/standalone/src/microblaze/microblaze_disable_dcache.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_disable_dcache.S @@ -1,19 +1,46 @@ /****************************************************************************** -* Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved. -* -* Xilinx, Inc. -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -* AND FITNESS FOR A PARTICULAR PURPOSE. -* +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************** * File : microblaze_disable_dcache.s * Date : 2002, March 20. * Company: Xilinx @@ -25,7 +52,7 @@ *******************************************************************************/ #include "xparameters.h" - + .text .globl microblaze_disable_dcache .ent microblaze_disable_dcache @@ -57,7 +84,7 @@ microblaze_disable_dcache: andi r11, r11, ~(0x80) mts rmsr, r11 -#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 +#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 lwi r15, r1, 0 #endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */ diff --git a/lib/bsp/standalone/src/microblaze/microblaze_disable_exceptions.S b/lib/bsp/standalone/src/microblaze/microblaze_disable_exceptions.S old mode 100755 new mode 100644 index d6d67125..4a4b96c8 --- a/lib/bsp/standalone/src/microblaze/microblaze_disable_exceptions.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_disable_exceptions.S @@ -1,39 +1,51 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************** +* +* Disable exceptions on microblaze. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. * ******************************************************************************/ -# -# Disable exceptions on microblaze. -# -# -#################################################################### #include "xparameters.h" @@ -45,14 +57,12 @@ microblaze_disable_exceptions: #if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 rtsd r15, 8 msrclr r0, 0x100 -#else +#else mfs r4, rmsr; andi r4, r4, ~(0x100); /* Turn OFF the EE bit */ mts rmsr, r4; rtsd r15, 8; - nop; + nop; #endif .end microblaze_disable_exceptions - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_disable_icache.S b/lib/bsp/standalone/src/microblaze/microblaze_disable_icache.S old mode 100755 new mode 100644 index 0f227038..67099563 --- a/lib/bsp/standalone/src/microblaze/microblaze_disable_icache.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_disable_icache.S @@ -1,45 +1,57 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************** +* +* File : microblaze_disable_icache.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Disable L1 icache on the microblaze. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. * ******************************************************************************/ -# -# File : microblaze_disable_icache.s -# Date : 2002, March 20. -# Company: Xilinx -# Group : Emerging Software Technologies -# -# Summary: -# Disable L1 icache on the microblaze. -# -# -#################################################################### #include "xparameters.h" @@ -47,7 +59,7 @@ .globl microblaze_disable_icache .ent microblaze_disable_icache .align 2 -microblaze_disable_icache: +microblaze_disable_icache: #if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 rtsd r15, 8 msrclr r0, 0x20 @@ -64,5 +76,3 @@ microblaze_disable_icache: #endif .end microblaze_disable_icache - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_disable_interrupts.S b/lib/bsp/standalone/src/microblaze/microblaze_disable_interrupts.S old mode 100755 new mode 100644 index e5f32562..e1c4a96f --- a/lib/bsp/standalone/src/microblaze/microblaze_disable_interrupts.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_disable_interrupts.S @@ -1,45 +1,57 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************** +* +* File : microblaze_disable_interrupts.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Disable interrupts on the microblaze. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. * ******************************************************************************/ -# -# File : microblaze_disable_interrupts.s -# Date : 2002, March 20. -# Company: Xilinx -# Group : Emerging Software Technologies -# -# Summary: -# Disable interrupts on the microblaze. -# -# -#################################################################### #include "xparameters.h" @@ -47,7 +59,7 @@ .globl microblaze_disable_interrupts .ent microblaze_disable_interrupts .align 2 -microblaze_disable_interrupts: +microblaze_disable_interrupts: #if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 rtsd r15, 8 msrclr r0, 0x2 @@ -64,5 +76,3 @@ microblaze_disable_interrupts: #endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ .end microblaze_disable_interrupts - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_enable_dcache.S b/lib/bsp/standalone/src/microblaze/microblaze_enable_dcache.S old mode 100755 new mode 100644 index 5c6e6d8f..5e3e4abd --- a/lib/bsp/standalone/src/microblaze/microblaze_enable_dcache.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_enable_dcache.S @@ -1,53 +1,65 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************** +* +* File : microblaze_enable_dcache.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Enable L1 dcache on the microblaze. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. * ******************************************************************************/ -# -# File : microblaze_enable_dcache.s -# Date : 2002, March 20. -# Company: Xilinx -# Group : Emerging Software Technologies -# -# Summary: -# Enable L1 dcache on the microblaze. -# -# -#################################################################### -#include "xparameters.h" +#include "xparameters.h" .text .globl microblaze_enable_dcache .ent microblaze_enable_dcache .align 2 -microblaze_enable_dcache: +microblaze_enable_dcache: #if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 rtsd r15, 8 @@ -65,5 +77,3 @@ microblaze_enable_dcache: #endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ .end microblaze_enable_dcache - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_enable_exceptions.S b/lib/bsp/standalone/src/microblaze/microblaze_enable_exceptions.S old mode 100755 new mode 100644 index 1a7cb099..ecbacb34 --- a/lib/bsp/standalone/src/microblaze/microblaze_enable_exceptions.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_enable_exceptions.S @@ -1,39 +1,51 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************** +* +* Enable exceptions on microblaze. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. * ******************************************************************************/ -# -# Enable exceptions on microblaze. -# -# -#################################################################### #include "xparameters.h" @@ -50,9 +62,7 @@ microblaze_enable_exceptions: ori r4, r4, 0x100; /* Turn ON the EE bit */ mts rmsr, r4; rtsd r15, 8; - nop; + nop; #endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ .end microblaze_enable_exceptions - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_enable_icache.S b/lib/bsp/standalone/src/microblaze/microblaze_enable_icache.S old mode 100755 new mode 100644 index 5675842e..4b3681af --- a/lib/bsp/standalone/src/microblaze/microblaze_enable_icache.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_enable_icache.S @@ -1,46 +1,57 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************** +* +* File : microblaze_enable_icache.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Enable icache on the microblaze. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. * ******************************************************************************/ -# -# File : microblaze_enable_icache.s -# Date : 2002, March 20. -# Company: Xilinx -# Group : Emerging Software Technologies -# -# Summary: -# Enable icache on the microblaze. -# -# -#################################################################### - #include "xparameters.h" .text @@ -64,5 +75,3 @@ microblaze_enable_icache: #endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ .end microblaze_enable_icache - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_enable_interrupts.S b/lib/bsp/standalone/src/microblaze/microblaze_enable_interrupts.S old mode 100755 new mode 100644 index feac4eb2..f37afc3c --- a/lib/bsp/standalone/src/microblaze/microblaze_enable_interrupts.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_enable_interrupts.S @@ -1,53 +1,65 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************** +* +* File : microblaze_enable_interrupts.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Enable interrupts on the microblaze. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. * ******************************************************************************/ -# -# File : microblaze_enable_interrupts.s -# Date : 2002, March 20. -# Company: Xilinx -# Group : Emerging Software Technologies -# -# Summary: -# Enable interrupts on the microblaze. -# -# -#################################################################### -#include "xparameters.h" +#include "xparameters.h" .text .globl microblaze_enable_interrupts .ent microblaze_enable_interrupts .align 2 -microblaze_enable_interrupts: +microblaze_enable_interrupts: #if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 rtsd r15, 8 msrset r0, 0x2 @@ -64,5 +76,3 @@ microblaze_enable_interrupts: #endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ .end microblaze_enable_interrupts - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_exception_handler.c b/lib/bsp/standalone/src/microblaze/microblaze_exception_handler.c old mode 100755 new mode 100644 index 6c433799..69afc622 --- a/lib/bsp/standalone/src/microblaze/microblaze_exception_handler.c +++ b/lib/bsp/standalone/src/microblaze/microblaze_exception_handler.c @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ diff --git a/lib/bsp/standalone/src/microblaze/microblaze_exceptions_g.h b/lib/bsp/standalone/src/microblaze/microblaze_exceptions_g.h old mode 100755 new mode 100644 index 1ba9ce29..97adb0d1 --- a/lib/bsp/standalone/src/microblaze/microblaze_exceptions_g.h +++ b/lib/bsp/standalone/src/microblaze/microblaze_exceptions_g.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -46,4 +57,9 @@ * * ******************************************************************************/ +#ifndef MICROBLAZE_EXCEPTIONS_G_H /* prevent circular inclusions */ +#define MICROBLAZE_EXCEPTIONS_G_H /* by using protection macros */ + #define MICROBLAZE_EXCEPTIONS_ENABLED 1 + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/microblaze/microblaze_exceptions_i.h b/lib/bsp/standalone/src/microblaze/microblaze_exceptions_i.h old mode 100755 new mode 100644 index c9cd039a..7fc4de9d --- a/lib/bsp/standalone/src/microblaze/microblaze_exceptions_i.h +++ b/lib/bsp/standalone/src/microblaze/microblaze_exceptions_i.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -67,17 +78,17 @@ typedef struct } MB_ExceptionVectorTableEntry; /* Exception IDs */ -#define XEXC_ID_FSL 0 -#define XEXC_ID_UNALIGNED_ACCESS 1 -#define XEXC_ID_ILLEGAL_OPCODE 2 -#define XEXC_ID_M_AXI_I_EXCEPTION 3 -#define XEXC_ID_IPLB_EXCEPTION 3 -#define XEXC_ID_M_AXI_D_EXCEPTION 4 -#define XEXC_ID_DPLB_EXCEPTION 4 -#define XEXC_ID_DIV_BY_ZERO 5 -#define XEXC_ID_FPU 6 -#define XEXC_ID_STACK_VIOLATION 7 -#define XEXC_ID_MMU 7 +#define XEXC_ID_FSL 0U +#define XEXC_ID_UNALIGNED_ACCESS 1U +#define XEXC_ID_ILLEGAL_OPCODE 2U +#define XEXC_ID_M_AXI_I_EXCEPTION 3U +#define XEXC_ID_IPLB_EXCEPTION 3U +#define XEXC_ID_M_AXI_D_EXCEPTION 4U +#define XEXC_ID_DPLB_EXCEPTION 4U +#define XEXC_ID_DIV_BY_ZERO 5U +#define XEXC_ID_FPU 6U +#define XEXC_ID_STACK_VIOLATION 7U +#define XEXC_ID_MMU 7U void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr); diff --git a/lib/bsp/standalone/src/microblaze/microblaze_flush_cache_ext.S b/lib/bsp/standalone/src/microblaze/microblaze_flush_cache_ext.S old mode 100755 new mode 100644 index 0b2fc0f1..3d26cba8 --- a/lib/bsp/standalone/src/microblaze/microblaze_flush_cache_ext.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_flush_cache_ext.S @@ -1,36 +1,50 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +******************************************************************************/ +/****************************************************************************** * * microblaze_flush_cache_ext() * -* Flush the entire L2 Cache +* Flush the entire L2 Cache * * *******************************************************************************/ @@ -48,7 +62,7 @@ microblaze_flush_cache_ext: #if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1)) addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) - + addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) @@ -61,5 +75,3 @@ Loop_start: nop .end microblaze_flush_cache_ext - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_flush_cache_ext_range.S b/lib/bsp/standalone/src/microblaze/microblaze_flush_cache_ext_range.S old mode 100755 new mode 100644 index 22f722d0..ceab0fdb --- a/lib/bsp/standalone/src/microblaze/microblaze_flush_cache_ext_range.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_flush_cache_ext_range.S @@ -1,38 +1,52 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +******************************************************************************/ +/****************************************************************************** * * microblaze_flush_cache_ext_range (unsigned int cacheaddr, unsigned int len) * *Flush a L2 Cache range * -*Parameters: +*Parameters: * 'cacheaddr' - address in the L2 cache where the flush begins * 'len ' - length (in bytes) worth of L2 cache to be flushed * @@ -63,12 +77,11 @@ Loop_start: bneid r6, Loop_start addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) -Loop_done: +Loop_done: #endif rtsd r15, 8 nop .end microblaze_flush_cache_ext_range - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_flush_dcache.S b/lib/bsp/standalone/src/microblaze/microblaze_flush_dcache.S old mode 100755 new mode 100644 index c455ede1..b4275f69 --- a/lib/bsp/standalone/src/microblaze/microblaze_flush_dcache.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_flush_dcache.S @@ -1,36 +1,51 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************** * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. * * microblaze_flush_dcache() -* -* Flush the L1 DCache +* +* Flush the L1 DCache * *******************************************************************************/ @@ -38,11 +53,11 @@ #define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 #endif - + .text .globl microblaze_flush_dcache .ent microblaze_flush_dcache @@ -50,21 +65,19 @@ microblaze_flush_dcache: addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Align to cache line */ - addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */ - + addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */ + L_start: wdc.flush r5, r0 /* Flush the Cache */ - - cmpu r18, r5, r6 /* Are we at the end? */ - blei r18, L_done - brid L_start /* Branch to the beginning of the loop */ + cmpu r18, r5, r6 /* Are we at the end? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ -L_done: +L_done: rtsd r15, 8 /* Return */ nop .end microblaze_flush_dcache - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_flush_dcache_range.S b/lib/bsp/standalone/src/microblaze/microblaze_flush_dcache_range.S old mode 100755 new mode 100644 index c820d6eb..2bd45b4e --- a/lib/bsp/standalone/src/microblaze/microblaze_flush_dcache_range.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_flush_dcache_range.S @@ -1,38 +1,52 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +******************************************************************************/ +/****************************************************************************** * * microblaze_flush_dcache_range (unsigned int cacheaddr, unsigned int len) -* +* * Flush a L1 DCache range -* -* Parameters: +* +* Parameters: * 'cacheaddr' - address in the Dcache where the flush begins * 'len ' - length (in bytes) worth of Dcache to be flushed * @@ -42,7 +56,7 @@ #define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 #endif @@ -61,32 +75,32 @@ microblaze_flush_dcache_range: -#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ - mfs r9, rmsr +#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ + mfs r9, rmsr andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) mts rmsr, r10 #endif beqi r6, L_done /* Skip loop if size is zero */ - + add r6, r5, r6 /* Compute end address */ addik r6, r6, -1 - - andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */ + + andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */ andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */ #if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */ - + L_start: - cmpu r18, r5, r6 /* Are we at the end? */ - blti r18, L_done - + cmpu r18, r5, r6 /* Are we at the end? */ + blti r18, L_done + wdc r5, r0 /* Invalidate the cache line */ - - brid L_start /* Branch to the beginning of the loop */ + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ #else - rsubk r6, r5, r6 + rsubk r6, r5, r6 /* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */ L_start: wdc.flush r5, r6 /* Flush the cache line */ @@ -94,9 +108,9 @@ L_start: addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) #endif - -L_done: - rtsd r15, 8 + +L_done: + rtsd r15, 8 #ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */ mts rmsr, r9 #else @@ -104,5 +118,3 @@ L_done: #endif .end microblaze_flush_dcache_range - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_init_dcache_range.S b/lib/bsp/standalone/src/microblaze/microblaze_init_dcache_range.S old mode 100755 new mode 100644 index d6a8494d..8e5cf932 --- a/lib/bsp/standalone/src/microblaze/microblaze_init_dcache_range.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_init_dcache_range.S @@ -1,38 +1,52 @@ /****************************************************************************** * -* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +******************************************************************************/ +/****************************************************************************** * * microblaze_init_dcache_range (unsigned int cache_start, unsigned int cache_len) -* +* * Invalidate dcache on the microblaze -* -* Parameters: +* +* Parameters: * 'cache_start' - address in the Dcache where invalidation begins * 'cache_len' - length (in bytes) worth of Dcache to be invalidated * @@ -43,11 +57,11 @@ #define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 #endif - + .text .globl microblaze_init_dcache_range .ent microblaze_init_dcache_range @@ -61,22 +75,20 @@ microblaze_init_dcache_range: andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */ - add r6, r5, r6 /* Compute end */ + add r6, r5, r6 /* Compute end */ andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */ - + L_start: wdc r5, r0 /* Invalidate the Cache (delay slot) */ - - cmpu r18, r5, r6 /* Are we at the end ? */ - blei r18, L_done - brid L_start /* Branch to the beginning of the loop */ + cmpu r18, r5, r6 /* Are we at the end ? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ -L_done: +L_done: rtsd r15, 8 /* Return */ mts rmsr, r9 .end microblaze_init_dcache_range - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_init_icache_range.S b/lib/bsp/standalone/src/microblaze/microblaze_init_icache_range.S old mode 100755 new mode 100644 index 5a66f12a..2bc6f501 --- a/lib/bsp/standalone/src/microblaze/microblaze_init_icache_range.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_init_icache_range.S @@ -1,39 +1,53 @@ /****************************************************************************** * -* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +******************************************************************************/ +/****************************************************************************** * * * microblaze_init_icache_range (unsigned int cache_start, unsigned int cache_len) -* +* * Invalidate icache on the microblaze -* -* Parameters: +* +* Parameters: * 'cache_start' - address in the Icache where invalidation begins * 'cache_len' - length (in bytes) worth of Icache to be invalidated * @@ -44,11 +58,11 @@ #define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1 #endif - + .text .globl microblaze_init_icache_range .ent microblaze_init_icache_range @@ -62,22 +76,20 @@ microblaze_init_icache_range: andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */ - add r6, r5, r6 /* Compute end */ + add r6, r5, r6 /* Compute end */ andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */ - + L_start: wic r5, r0 /* Invalidate the Cache (delay slot) */ - - cmpu r18, r5, r6 /* Are we at the end ? */ - blei r18, L_done - brid L_start /* Branch to the beginning of the loop */ + cmpu r18, r5, r6 /* Are we at the end ? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ -L_done: +L_done: rtsd r15, 8 /* Return */ mts rmsr, r9 .end microblaze_init_icache_range - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_interrupt_handler.c b/lib/bsp/standalone/src/microblaze/microblaze_interrupt_handler.c old mode 100755 new mode 100644 index 1724e300..85aed573 --- a/lib/bsp/standalone/src/microblaze/microblaze_interrupt_handler.c +++ b/lib/bsp/standalone/src/microblaze/microblaze_interrupt_handler.c @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -64,6 +75,7 @@ /************************** Function Prototypes ******************************/ void __interrupt_handler (void) __attribute__ ((interrupt_handler)); +void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); /************************** Variable Definitions *****************************/ @@ -91,7 +103,7 @@ extern MB_InterruptVectorTableEntry MB_InterruptVectorTable; void __interrupt_handler(void) { /* The compiler saves all volatiles and the MSR */ - MB_InterruptVectorTable.Handler(MB_InterruptVectorTable.CallBackRef); + (void)MB_InterruptVectorTable.Handler(MB_InterruptVectorTable.CallBackRef); /* The compiler restores all volatiles and MSR, and returns from interrupt */ } diff --git a/lib/bsp/standalone/src/microblaze/microblaze_interrupts_g.c b/lib/bsp/standalone/src/microblaze/microblaze_interrupts_g.c old mode 100755 new mode 100644 index e24a049c..1cb9f98e --- a/lib/bsp/standalone/src/microblaze/microblaze_interrupts_g.c +++ b/lib/bsp/standalone/src/microblaze/microblaze_interrupts_g.c @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -51,7 +62,7 @@ #include "xparameters.h" -extern void XNullHandler (void *); +/* extern void XNullHandler (void *NullParameter) */ /* * The interrupt handler table for microblaze processor @@ -59,6 +70,6 @@ extern void XNullHandler (void *); MB_InterruptVectorTableEntry MB_InterruptVectorTable[] = { - XNullHandler, - (void*) XNULL + {XNullHandler, + (void)XNULL} }; diff --git a/lib/bsp/standalone/src/microblaze/microblaze_interrupts_i.h b/lib/bsp/standalone/src/microblaze/microblaze_interrupts_i.h old mode 100755 new mode 100644 index d77fc6fe..34cf6b2c --- a/lib/bsp/standalone/src/microblaze/microblaze_interrupts_i.h +++ b/lib/bsp/standalone/src/microblaze/microblaze_interrupts_i.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ diff --git a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_cache_ext.S b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_cache_ext.S old mode 100755 new mode 100644 index 8cc2cb64..9ebda38e --- a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_cache_ext.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_cache_ext.S @@ -1,36 +1,50 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +******************************************************************************/ +/****************************************************************************** * * microblaze_invalidate_cache_ext() * -*Invalidate the entire L2 Cache +*Invalidate the entire L2 Cache * * *******************************************************************************/ @@ -48,19 +62,17 @@ microblaze_invalidate_cache_ext: #if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1)) addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)) - + addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) - andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) + andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) Loop_start: wdc.ext.clear r5, r6 bgtid r6,Loop_start addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) -#endif +#endif rtsd r15, 8 nop .end microblaze_invalidate_cache_ext - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_cache_ext_range.S b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_cache_ext_range.S old mode 100755 new mode 100644 index b3d32208..02542573 --- a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_cache_ext_range.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_cache_ext_range.S @@ -1,32 +1,46 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +******************************************************************************/ +/****************************************************************************** * * microblaze_invalidate_cache_ext_range (unsigned int cacheaddr, unsigned int len) * @@ -64,12 +78,10 @@ Loop_start: bneid r6, Loop_start addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) -Loop_done: +Loop_done: #endif rtsd r15, 8 nop .end microblaze_invalidate_cache_ext_range - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_dcache.S b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_dcache.S old mode 100755 new mode 100644 index 2016b0dd..60c8a07c --- a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_dcache.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_dcache.S @@ -1,36 +1,50 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +******************************************************************************/ +/****************************************************************************** * * microblaze_invalidate_dcache() -* -* Invalidate the entire L1 DCache +* +* Invalidate the entire L1 DCache * * *******************************************************************************/ @@ -39,7 +53,7 @@ #define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 #endif @@ -47,7 +61,7 @@ #ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK #define MB_VERSION_LT_v720 #endif - + .text .globl microblaze_invalidate_dcache .ent microblaze_invalidate_dcache @@ -55,24 +69,24 @@ microblaze_invalidate_dcache: -#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ - mfs r9, rmsr +#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ + mfs r9, rmsr andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) mts rmsr, r10 #endif - addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) - addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */ - + addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) + addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */ + L_start: wdc r5, r0 /* Invalidate the Cache */ - - cmpu r18, r5, r6 /* Are we at the end? */ - blei r18, L_done - brid L_start /* Branch to the beginning of the loop */ + cmpu r18, r5, r6 /* Are we at the end? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ -L_done: +L_done: rtsd r15, 8 /* Return */ #ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */ mts rmsr, r9 @@ -82,5 +96,3 @@ L_done: .end microblaze_invalidate_dcache - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_dcache_range.S b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_dcache_range.S old mode 100755 new mode 100644 index d72e55b0..21f3ab98 --- a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_dcache_range.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_dcache_range.S @@ -1,39 +1,53 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +******************************************************************************/ +/****************************************************************************** * * * microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len) -* +* * Invalidate a Dcache range -* -* Parameters: +* +* Parameters: * 'cacheaddr' - address in the Dcache where invalidation begins * 'len ' - length (in bytes) worth of Dcache to be invalidated * @@ -44,7 +58,7 @@ #define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 #endif @@ -55,7 +69,7 @@ #else #define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK #endif - + .text .globl microblaze_invalidate_dcache_range .ent microblaze_invalidate_dcache_range @@ -63,34 +77,34 @@ microblaze_invalidate_dcache_range: - -#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ - mfs r9, rmsr + +#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ + mfs r9, rmsr andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) mts rmsr, r10 #endif beqi r6, L_done /* Skip loop if size is zero */ - + add r6, r5, r6 /* Compute end address */ addik r6, r6, -1 - - andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */ + + andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */ andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */ - + #if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */ - + L_start: - cmpu r18, r5, r6 /* Are we at the end? */ - blti r18, L_done - - wdc r5, r0 - - brid L_start /* Branch to the beginning of the loop */ + cmpu r18, r5, r6 /* Are we at the end? */ + blti r18, L_done + + wdc r5, r0 + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ #else - rsubk r6, r5, r6 + rsubk r6, r5, r6 /* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */ L_start: wdc.clear r5, r6 /* Invalidate the cache line only if the address matches */ @@ -98,9 +112,9 @@ L_start: addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) #endif - -L_done: - rtsd r15, 8 + +L_done: + rtsd r15, 8 #ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */ mts rmsr, r9 #else @@ -108,5 +122,3 @@ L_done: #endif .end microblaze_invalidate_dcache_range - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_icache.S b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_icache.S old mode 100755 new mode 100644 index f0f679ee..cd566a2b --- a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_icache.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_icache.S @@ -1,36 +1,50 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +******************************************************************************/ +/****************************************************************************** * * * microblaze_invalidate_icache() -* +* * Invalidate the entire ICache * * @@ -40,7 +54,7 @@ #define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1 #endif @@ -48,7 +62,7 @@ #ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK #define MB_VERSION_LT_v720 #endif - + .text .globl microblaze_invalidate_icache .ent microblaze_invalidate_icache @@ -56,23 +70,23 @@ microblaze_invalidate_icache: -#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */ +#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */ mfs r9, rmsr andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) mts rmsr, r10 #endif - addik r5, r0, XPAR_MICROBLAZE_ICACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Align to cache line */ - addik r6, r5, XPAR_MICROBLAZE_CACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Compute end */ + addik r5, r0, XPAR_MICROBLAZE_ICACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Align to cache line */ + addik r6, r5, XPAR_MICROBLAZE_CACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Compute end */ L_start: wic r5, r0 /* Invalidate the Cache */ - - cmpu r18, r5, r6 /* Are we at the end? */ - blei r18, L_done - brid L_start /* Branch to the beginning of the loop */ + cmpu r18, r5, r6 /* Are we at the end? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ -L_done: +L_done: rtsd r15, 8 /* Return */ #ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */ @@ -82,5 +96,3 @@ L_done: #endif .end microblaze_invalidate_icache - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_icache_range.S b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_icache_range.S old mode 100755 new mode 100644 index 8f90d3eb..61adacc5 --- a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_icache_range.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_icache_range.S @@ -1,39 +1,53 @@ /****************************************************************************** * -* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +******************************************************************************/ +/****************************************************************************** * * * microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len) -* +* * Invalidate an ICache range -* -* Parameters: +* +* Parameters: * 'cacheaddr' - address in the Icache where invalidation begins * 'len' - length (in bytes) worth of Icache to be invalidated * @@ -44,7 +58,7 @@ #define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020 #define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 - + #ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1 #endif @@ -52,7 +66,7 @@ #ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK #define MB_VERSION_LT_v720 #endif - + .text .globl microblaze_invalidate_icache_range .ent microblaze_invalidate_icache_range @@ -60,27 +74,27 @@ microblaze_invalidate_icache_range: -#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */ - mfs r9, rmsr +#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */ + mfs r9, rmsr andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) mts rmsr, r10 #endif beqi r6, L_done /* Skip loop if size is zero */ - + add r6, r5, r6 /* Compute end address */ addik r6, r6, -1 - - andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align end down to cache line */ + + andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align end down to cache line */ andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align start down to cache line */ L_start: - cmpu r18, r5, r6 /* Are we at the end? */ - blti r18, L_done + cmpu r18, r5, r6 /* Are we at the end? */ + blti r18, L_done wic r5, r0 /* Invalidate the cache line */ - - brid L_start /* Branch to the beginning of the loop */ + + brid L_start /* Branch to the beginning of the loop */ addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ L_done: @@ -92,5 +106,3 @@ L_done: #endif .end microblaze_invalidate_icache_range - - diff --git a/lib/bsp/standalone/src/microblaze/microblaze_scrub.S b/lib/bsp/standalone/src/microblaze/microblaze_scrub.S old mode 100755 new mode 100644 index 5b0fc897..078b8a5c --- a/lib/bsp/standalone/src/microblaze/microblaze_scrub.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_scrub.S @@ -1,32 +1,46 @@ /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +******************************************************************************/ +/****************************************************************************** * * microblaze_scrub () * diff --git a/lib/bsp/standalone/src/microblaze/microblaze_sleep.c b/lib/bsp/standalone/src/microblaze/microblaze_sleep.c index 24dd6407..6e26e8a9 100644 --- a/lib/bsp/standalone/src/microblaze/microblaze_sleep.c +++ b/lib/bsp/standalone/src/microblaze/microblaze_sleep.c @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -80,9 +91,9 @@ * @note Instruction cache should be enabled for this to work. * ******************************************************************************/ -void MB_Sleep(unsigned int MilliSeconds) +void MB_Sleep(u32 MilliSeconds) { - if (((mfmsr() & 0x20) == 0)) { + if (((mfmsr() & 0x20U) == 0U)) { /* * Instruction cache not enabled. * Delay will be much higher than expected. diff --git a/lib/bsp/standalone/src/microblaze/microblaze_sleep.h b/lib/bsp/standalone/src/microblaze/microblaze_sleep.h index d9105b75..1fc56d1a 100644 --- a/lib/bsp/standalone/src/microblaze/microblaze_sleep.h +++ b/lib/bsp/standalone/src/microblaze/microblaze_sleep.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -74,7 +85,7 @@ extern "C" { /************************** Function Prototypes ******************************/ -void MB_Sleep(unsigned int MilliSeconds); +void MB_Sleep(u32 MilliSeconds); #ifdef __cplusplus } diff --git a/lib/bsp/standalone/src/microblaze/microblaze_update_dcache.S b/lib/bsp/standalone/src/microblaze/microblaze_update_dcache.S old mode 100755 new mode 100644 index 286b7891..1adaf461 --- a/lib/bsp/standalone/src/microblaze/microblaze_update_dcache.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_update_dcache.S @@ -1,34 +1,48 @@ /****************************************************************************** * -* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************** * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. * -* * File : microblaze_update_dcache.s * Date : 2003, September 24 * Company: Xilinx @@ -49,14 +63,14 @@ * | 0 | 0 | Invalidate Cache * | 0 | 1 | Valid, but unlocked cacheline * | 1 | 0 | Invalidate Cache, No effect of lock -* | 1 | 1 | Valid cache. Locked to a +* | 1 | 1 | Valid cache. Locked to a * | | | particular addrees * -------------------------------------------------------------- * * **********************************************************************************/ #include "xparameters.h" - + #ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 #endif @@ -97,7 +111,7 @@ microblaze_update_dcache: addik r6, r0, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* We don't have a return instruction here. This is tail call optimization :) */ - + #endif /* XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1 */ .end microblaze_update_dcache diff --git a/lib/bsp/standalone/src/microblaze/microblaze_update_icache.S b/lib/bsp/standalone/src/microblaze/microblaze_update_icache.S old mode 100755 new mode 100644 index f35c6aef..caf7b74a --- a/lib/bsp/standalone/src/microblaze/microblaze_update_icache.S +++ b/lib/bsp/standalone/src/microblaze/microblaze_update_icache.S @@ -1,32 +1,46 @@ /****************************************************************************** * -* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +******************************************************************************/ +/****************************************************************************** * * File : microblaze_update_icache.s * Date : 2003, September 24 @@ -48,14 +62,14 @@ * | 0 | 0 | Invalidate Cache * | 0 | 1 | Valid, but unlocked cacheline * | 1 | 0 | Invalidate Cache, No effect of lock -* | 1 | 1 | Valid cache. Locked to a +* | 1 | 1 | Valid cache. Locked to a * | | | particular addrees * -------------------------------------------------------------- * * **********************************************************************************/ #include "xparameters.h" - + #ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1 #endif @@ -67,7 +81,7 @@ microblaze_update_icache: #if XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1 - + /* Read the MSR register into a temp register */ mfs r18, rmsr @@ -96,8 +110,7 @@ microblaze_update_icache: addik r6, r0, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* We don't have a return instruction here. This is tail call optimization :) */ - + #endif /* XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1 */ - .end microblaze_update_icache - + .end microblaze_update_icache diff --git a/lib/bsp/standalone/src/microblaze/pvr.c b/lib/bsp/standalone/src/microblaze/pvr.c old mode 100755 new mode 100644 index f6b8ae17..de8e29de --- a/lib/bsp/standalone/src/microblaze/pvr.c +++ b/lib/bsp/standalone/src/microblaze/pvr.c @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ diff --git a/lib/bsp/standalone/src/microblaze/pvr.h b/lib/bsp/standalone/src/microblaze/pvr.h old mode 100755 new mode 100644 index da8a038d..e96078a2 --- a/lib/bsp/standalone/src/microblaze/pvr.h +++ b/lib/bsp/standalone/src/microblaze/pvr.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ diff --git a/lib/bsp/standalone/src/microblaze/xil_cache.c b/lib/bsp/standalone/src/microblaze/xil_cache.c old mode 100755 new mode 100644 index f575c5ed..d48d836d --- a/lib/bsp/standalone/src/microblaze/xil_cache.c +++ b/lib/bsp/standalone/src/microblaze/xil_cache.c @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -93,4 +104,3 @@ void Xil_ICacheDisable(void) Xil_L1ICacheDisable(); } - diff --git a/lib/bsp/standalone/src/microblaze/xil_cache.h b/lib/bsp/standalone/src/microblaze/xil_cache.h old mode 100755 new mode 100644 index 91a442cd..40c9b82f --- a/lib/bsp/standalone/src/microblaze/xil_cache.h +++ b/lib/bsp/standalone/src/microblaze/xil_cache.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -133,7 +144,7 @@ extern "C" { * Processor must be in real mode. ****************************************************************************/ #define Xil_L1DCacheInvalidateRange(Addr, Len) \ - microblaze_invalidate_dcache_range(Addr, Len) + microblaze_invalidate_dcache_range((Addr), (Len)) /****************************************************************************/ /** @@ -153,7 +164,7 @@ extern "C" { * Processor must be in real mode. ****************************************************************************/ #define Xil_L2CacheInvalidateRange(Addr, Len) \ - microblaze_invalidate_cache_ext_range(Addr, Len) + microblaze_invalidate_cache_ext_range((Addr), (Len)) /****************************************************************************/ /** @@ -170,10 +181,10 @@ extern "C" { ****************************************************************************/ #if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) # define Xil_L1DCacheFlushRange(Addr, Len) \ - microblaze_flush_dcache_range(Addr, Len) + microblaze_flush_dcache_range((Addr), (Len)) #else # define Xil_L1DCacheFlushRange(Addr, Len) \ - microblaze_invalidate_dcache_range(Addr, Len) + microblaze_invalidate_dcache_range((Addr), (Len)) #endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */ /****************************************************************************/ @@ -190,7 +201,7 @@ extern "C" { * ****************************************************************************/ #define Xil_L2CacheFlushRange(Addr, Len) \ - microblaze_flush_cache_ext_range(Addr, Len) + microblaze_flush_cache_ext_range((Addr), (Len)) /****************************************************************************/ /** @@ -232,7 +243,7 @@ extern "C" { * ****************************************************************************/ #define Xil_L1ICacheInvalidateRange(Addr, Len) \ - microblaze_invalidate_icache_range(Addr, Len) + microblaze_invalidate_icache_range((Addr), (Len)) /****************************************************************************/ /** @@ -360,8 +371,8 @@ extern "C" { * ****************************************************************************/ #define Xil_DCacheInvalidateRange(Addr, Len) \ - Xil_L2CacheInvalidateRange(Addr, Len); \ - Xil_L1DCacheInvalidateRange(Addr, Len); + Xil_L2CacheInvalidateRange((Addr), (Len)); \ + Xil_L1DCacheInvalidateRange((Addr), (Len)); /**************************************************************************** @@ -395,8 +406,8 @@ extern "C" { * ****************************************************************************/ #define Xil_DCacheFlushRange(Addr, Len) \ - Xil_L2CacheFlushRange(Addr, Len); \ - Xil_L1DCacheFlushRange(Addr, Len); + Xil_L2CacheFlushRange((Addr), (Len)); \ + Xil_L1DCacheFlushRange((Addr), (Len)); /**************************************************************************** @@ -432,8 +443,8 @@ extern "C" { * ****************************************************************************/ #define Xil_ICacheInvalidateRange(Addr, Len) \ - Xil_L2CacheInvalidateRange(Addr, Len); \ - Xil_L1ICacheInvalidateRange(Addr, Len); + Xil_L2CacheInvalidateRange((Addr), (Len)); \ + Xil_L1ICacheInvalidateRange((Addr), (Len)); void Xil_DCacheDisable(void); void Xil_ICacheDisable(void); diff --git a/lib/bsp/standalone/src/microblaze/xil_exception.c b/lib/bsp/standalone/src/microblaze/xil_exception.c old mode 100755 new mode 100644 index 837eac77..4bb96d82 --- a/lib/bsp/standalone/src/microblaze/xil_exception.c +++ b/lib/bsp/standalone/src/microblaze/xil_exception.c @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -55,6 +66,7 @@ #include "xil_exception.h" #include "microblaze_exceptions_g.h" +#include "microblaze_interrupts_i.h" #ifdef __cplusplus extern "C" { @@ -75,10 +87,10 @@ typedef struct { void *CallBackRef; } MB_ExceptionVectorTableEntry; -typedef struct { - Xil_ExceptionHandler Handler; - void *CallBackRef; -} MB_InterruptVectorTableEntry; +/*typedef struct { + Xil_ExceptionHandler Handler, + void *CallBackRef, +} MB_InterruptVectorTableEntry, */ #ifdef __cplusplus } @@ -86,7 +98,7 @@ typedef struct { /************************** Variable Definitions *****************************/ -extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[]; +extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[XIL_EXCEPTION_ID_INT]; extern MB_InterruptVectorTableEntry MB_InterruptVectorTable; /** @@ -109,7 +121,7 @@ extern MB_InterruptVectorTableEntry MB_InterruptVectorTable; *****************************************************************************/ static void Xil_ExceptionNullHandler(void *Data) { - (void) Data; + (void *) Data; } /****************************************************************************/ diff --git a/lib/bsp/standalone/src/microblaze/xil_exception.h b/lib/bsp/standalone/src/microblaze/xil_exception.h old mode 100755 new mode 100644 index f589cb68..05aa5056 --- a/lib/bsp/standalone/src/microblaze/xil_exception.h +++ b/lib/bsp/standalone/src/microblaze/xil_exception.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -68,24 +79,24 @@ extern "C" { * These constants are specific to Microblaze processor. */ -#define XIL_EXCEPTION_ID_FIRST 0 -#define XIL_EXCEPTION_ID_FSL 0 -#define XIL_EXCEPTION_ID_UNALIGNED_ACCESS 1 -#define XIL_EXCEPTION_ID_ILLEGAL_OPCODE 2 -#define XIL_EXCEPTION_ID_M_AXI_I_EXCEPTION 3 -#define XIL_EXCEPTION_ID_IPLB_EXCEPTION 3 -#define XIL_EXCEPTION_ID_M_AXI_D_EXCEPTION 4 -#define XIL_EXCEPTION_ID_DPLB_EXCEPTION 4 -#define XIL_EXCEPTION_ID_DIV_BY_ZERO 5 -#define XIL_EXCEPTION_ID_FPU 6 -#define XIL_EXCEPTION_ID_STACK_VIOLATION 7 -#define XIL_EXCEPTION_ID_MMU 7 +#define XIL_EXCEPTION_ID_FIRST 0U +#define XIL_EXCEPTION_ID_FSL 0U +#define XIL_EXCEPTION_ID_UNALIGNED_ACCESS 1U +#define XIL_EXCEPTION_ID_ILLEGAL_OPCODE 2U +#define XIL_EXCEPTION_ID_M_AXI_I_EXCEPTION 3U +#define XIL_EXCEPTION_ID_IPLB_EXCEPTION 3U +#define XIL_EXCEPTION_ID_M_AXI_D_EXCEPTION 4U +#define XIL_EXCEPTION_ID_DPLB_EXCEPTION 4U +#define XIL_EXCEPTION_ID_DIV_BY_ZERO 5U +#define XIL_EXCEPTION_ID_FPU 6U +#define XIL_EXCEPTION_ID_STACK_VIOLATION 7U +#define XIL_EXCEPTION_ID_MMU 7U #define XIL_EXCEPTION_ID_LAST XIL_EXCEPTION_ID_MMU /* * XIL_EXCEPTION_ID_INT is defined for all processors, but with different value. */ -#define XIL_EXCEPTION_ID_INT 16 /** +#define XIL_EXCEPTION_ID_INT 16U /** * exception ID for interrupt */ diff --git a/lib/bsp/standalone/src/microblaze/xil_io.c b/lib/bsp/standalone/src/microblaze/xil_io.c old mode 100755 new mode 100644 index aef0207d..295abc06 --- a/lib/bsp/standalone/src/microblaze/xil_io.c +++ b/lib/bsp/standalone/src/microblaze/xil_io.c @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -70,6 +81,116 @@ /************************** Function Prototypes ******************************/ +/***************** Macros (Inline Functions) and Functions Definitions *******/ + +/*****************************************************************************/ +/** +* +* Perform an input operation for an 8-bit memory location by reading from the +* specified address and returning the value read from that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u8 Xil_In8(u32 Addr) { + return *(volatile u8 *)Addr; +} + +/*****************************************************************************/ +/** +* +* Perform an input operation for a 16-bit memory location by reading from the +* specified address and returning the value read from that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u16 Xil_In16(u32 Addr) { + return *(volatile u16 *)Addr; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 32-bit memory location by reading from the +* specified address and returning the Value read from that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u32 Xil_In32(u32 Addr) { + return *(volatile u32 *)Addr; +} + + +/*****************************************************************************/ +/** +* +* Perform an output operation for an 8-bit memory location by writing the +* specified value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param value contains the value to be output at the specified address. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void Xil_Out8(u32 Addr, u8 Value) { + u8 *LocalAddr = (u8 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Perform an output operation for a 16-bit memory location by writing the +* specified value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param value contains the value to be output at the specified address. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void Xil_Out16(u32 Addr, u16 Value) { + u16 *LocalAddr = (u16 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Perform an output operation for a 32-bit memory location by writing the +* specified value to the specified address. +* +* @param addr contains the address to perform the output operation at. +* @param value contains the value to be output at the specified address. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void Xil_Out32(u32 Addr, u32 Value) { + u32 *LocalAddr = (u32 *)Addr; + *LocalAddr = Value; +} /*****************************************************************************/ /** @@ -85,7 +206,7 @@ ******************************************************************************/ u16 Xil_EndianSwap16(u16 Data) { - return (u16) (((Data & 0xFF00) >> 8) | ((Data & 0x00FF) << 8)); + return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U)); } /*****************************************************************************/ @@ -107,17 +228,17 @@ u32 Xil_EndianSwap32(u32 Data) /* get each of the half words from the 32 bit word */ - LoWord = (u16) (Data & 0x0000FFFF); - HiWord = (u16) ((Data & 0xFFFF0000) >> 16); + LoWord = (u16) (Data & 0x0000FFFFU); + HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U); /* byte swap each of the 16 bit half words */ - LoWord = (((LoWord & 0xFF00) >> 8) | ((LoWord & 0x00FF) << 8)); - HiWord = (((HiWord & 0xFF00) >> 8) | ((HiWord & 0x00FF) << 8)); + LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U)); + HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U)); /* swap the half words before returning the value */ - return (u32) ((LoWord << 16) | HiWord); + return ((((u32)LoWord) << (u32)16U) | (u32)HiWord); } /*****************************************************************************/ diff --git a/lib/bsp/standalone/src/microblaze/xil_io.h b/lib/bsp/standalone/src/microblaze/xil_io.h old mode 100755 new mode 100644 index 2bfb2ac1..4935d897 --- a/lib/bsp/standalone/src/microblaze/xil_io.h +++ b/lib/bsp/standalone/src/microblaze/xil_io.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -71,7 +82,15 @@ extern "C" { /************************** Constant Definitions *****************************/ -/**************************** Type Definitions *******************************/ +/**************************** Function Prototypes ****************************/ + +u8 Xil_In8(u32 Addr); +u16 Xil_In16(u32 Addr); +u32 Xil_In32(u32 Addr); + +void Xil_Out8(u32 Addr, u8 Value); +void Xil_Out16(u32 Addr, u16 Value); +void Xil_Out32(u32 Addr, u32 Value); /***************** Macros (Inline Functions) Definitions *********************/ @@ -89,102 +108,6 @@ extern "C" { * operation is needed as it will likely break some code. */ -/*****************************************************************************/ -/** -* -* Perform an input operation for an 8-bit memory location by reading from the -* specified address and returning the value read from that address. -* -* @param Addr contains the address to perform the input operation at. -* -* @return The value read from the specified input address. -* -* @note None. -* -******************************************************************************/ -#define Xil_In8(Addr) (*(volatile u8 *)(Addr)) - -/*****************************************************************************/ -/** -* -* Perform an input operation for a 16-bit memory location by reading from the -* specified address and returning the value read from that address. -* -* @param Addr contains the address to perform the input operation at. -* -* @return The value read from the specified input address. -* -* @note None. -* -******************************************************************************/ -#define Xil_In16(Addr) (*(volatile u16 *)(Addr)) - -/*****************************************************************************/ -/** -* -* Perform an input operation for a 32-bit memory location by reading from the -* specified address and returning the value read from that address. -* -* @param Addr contains the address to perform the input operation at. -* -* @return The value read from the specified input address. -* -* @note None. -* -******************************************************************************/ -#define Xil_In32(Addr) (*(volatile u32 *)(Addr)) - - -/*****************************************************************************/ -/** -* -* Perform an output operation for an 8-bit memory location by writing the -* specified value to the specified address. -* -* @param Addr contains the address to perform the output operation at. -* @param value contains the value to be output at the specified address. -* -* @return None -* -* @note None. -* -******************************************************************************/ -#define Xil_Out8(Addr, Value) \ - (*(volatile u8 *)((Addr)) = (Value)) - -/*****************************************************************************/ -/** -* -* Perform an output operation for a 16-bit memory location by writing the -* specified value to the specified address. -* -* @param Addr contains the address to perform the output operation at. -* @param value contains the value to be output at the specified address. -* -* @return None -* -* @note None. -* -******************************************************************************/ -#define Xil_Out16(Addr, Value) \ - (*(volatile u16 *)((Addr)) = (Value)) - -/*****************************************************************************/ -/** -* -* Perform an output operation for a 32-bit memory location by writing the -* specified value to the specified address. -* -* @param addr contains the address to perform the output operation at. -* @param value contains the value to be output at the specified address. -* -* @return None -* -* @note None. -* -******************************************************************************/ -#define Xil_Out32(Addr, Value) \ - (*(volatile u32 *)((Addr)) = (Value)) extern u16 Xil_EndianSwap16(u16 Data); @@ -213,7 +136,7 @@ extern void Xil_Out32LE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_In16BE(Addr) Xil_In16(Addr) +#define Xil_In16BE(Addr) Xil_In16((Addr)) /** * @@ -233,7 +156,7 @@ extern void Xil_Out32LE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_In32BE(Addr) Xil_In32(Addr) +#define Xil_In32BE(Addr) Xil_In32((Addr)) /*****************************************************************************/ /** @@ -253,7 +176,7 @@ extern void Xil_Out32LE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_Out16BE(Addr, Value) Xil_Out16(Addr, Value) +#define Xil_Out16BE(Addr, Value) Xil_Out16((Addr), (Value)) /*****************************************************************************/ /** @@ -272,7 +195,7 @@ extern void Xil_Out32LE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_Out32BE(Addr, Value) Xil_Out32(Addr, Value) +#define Xil_Out32BE(Addr, Value) Xil_Out32((Addr), (Value)) #define Xil_Htonl(Data) (Data) #define Xil_Htons(Data) (Data) @@ -286,10 +209,10 @@ extern u32 Xil_In32BE(u32 Addr); extern void Xil_Out16BE(u32 Addr, u16 Value); extern void Xil_Out32BE(u32 Addr, u32 Value); -#define Xil_In16LE(Addr) Xil_In16(Addr) -#define Xil_In32LE(Addr) Xil_In32(Addr) -#define Xil_Out16LE(Addr, Value) Xil_Out16(Addr, Value) -#define Xil_Out32LE(Addr, Value) Xil_Out32(Addr, Value) +#define Xil_In16LE(Addr) Xil_In16((Addr)) +#define Xil_In32LE(Addr) Xil_In32((Addr)) +#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value)) +#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value)) /*****************************************************************************/ @@ -304,7 +227,7 @@ extern void Xil_Out32BE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_Htonl(Data) Xil_EndianSwap32(Data) +#define Xil_Htonl(Data) Xil_EndianSwap32((Data)) /*****************************************************************************/ /** @@ -318,7 +241,7 @@ extern void Xil_Out32BE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_Htons(Data) Xil_EndianSwap16(Data) +#define Xil_Htons(Data) Xil_EndianSwap16((Data)) /*****************************************************************************/ /** @@ -332,7 +255,7 @@ extern void Xil_Out32BE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_Ntohl(Data) Xil_EndianSwap32(Data) +#define Xil_Ntohl(Data) Xil_EndianSwap32((Data)) /*****************************************************************************/ /** @@ -346,7 +269,7 @@ extern void Xil_Out32BE(u32 Addr, u32 Value); * @note None. * ******************************************************************************/ -#define Xil_Ntohs(Data) Xil_EndianSwap16(Data) +#define Xil_Ntohs(Data) Xil_EndianSwap16((Data)) #endif diff --git a/lib/bsp/standalone/src/microblaze/xil_misc_psreset_api.c b/lib/bsp/standalone/src/microblaze/xil_misc_psreset_api.c old mode 100755 new mode 100644 index 1546da39..6c86948e --- a/lib/bsp/standalone/src/microblaze/xil_misc_psreset_api.c +++ b/lib/bsp/standalone/src/microblaze/xil_misc_psreset_api.c @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -76,15 +87,15 @@ * @note None. * ******************************************************************************/ -void XDdr_ResetHw() +void XDdr_ResetHw(void) { u32 RegVal; - /* Unlock the slcr register access lock */ + /* Unlock the slcr register access lock */ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert and deassert the ddr softreset bit */ RegVal = Xil_In32(XDDRC_CTRL_BASEADDR); - RegVal &= ~XDDRPS_CTRL_RESET_MASK; + RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK); Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); RegVal |= XDDRPS_CTRL_RESET_MASK; Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); @@ -102,7 +113,7 @@ void XDdr_ResetHw() * @note None. * ******************************************************************************/ -void XOcm_Remap() +void XOcm_Remap(void) { u32 RegVal; @@ -110,7 +121,7 @@ void XOcm_Remap() Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Map the ocm region to postbootrom state */ RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR); - RegVal = (RegVal & ~XSLCR_OCM_CFG_HIADDR_MASK) | XSLCR_OCM_CFG_RESETVAL; + RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL; Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal); } @@ -131,11 +142,11 @@ void XSmc_ResetHw(u32 BaseAddress) /* Clear the interuupts */ RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET); - RegVal = RegVal | XSMC_MEMC_CLR_CONFIG_MASK; + RegVal |= XSMC_MEMC_CLR_CONFIG_MASK; Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal); /* Clear the idle counter registers */ - Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0); - Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0); + Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U); + Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U); /* Update the ecc registers with reset values */ Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET, XSMC_ECC_MEMCFG1_RESET_VAL); @@ -157,26 +168,26 @@ void XSmc_ResetHw(u32 BaseAddress) * @note None. * ******************************************************************************/ -void XSlcr_MioWriteResetValues() +void XSlcr_MioWriteResetValues(void) { u32 i; /* Unlock the slcr register access lock */ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Update all the MIO registers with reset values */ - for (i=0; i<=1;i++); + for (i=0U; i<=1U;i++) { - Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)), + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), XSLCR_MIO_PIN_00_RESET_VAL); } - for (; i<=8;i++); + for (; i<=8U;i++) { - Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)), + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), XSLCR_MIO_PIN_02_RESET_VAL); } - for (; i<=53 ;i++); + for (; i<=53U ;i++) { - Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)), + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), XSLCR_MIO_PIN_00_RESET_VAL); } @@ -194,7 +205,7 @@ void XSlcr_MioWriteResetValues() * @note None. * ******************************************************************************/ -void XSlcr_PllWriteResetValues() +void XSlcr_PllWriteResetValues(void) { /* Unlock the slcr register access lock */ @@ -224,14 +235,14 @@ void XSlcr_PllWriteResetValues() * @note None. * ******************************************************************************/ -void XSlcr_DisableLevelShifters() +void XSlcr_DisableLevelShifters(void) { u32 RegVal; /* Unlock the slcr register access lock */ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Disable the level shifters */ RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR); - RegVal = RegVal & ~XSLCR_LVL_SHFTR_EN_MASK; + RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK); Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal); } @@ -254,11 +265,11 @@ void XSlcr_OcmReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_OCM_RST_CTRL_VAL; + RegVal |= XSLCR_OCM_RST_CTRL_VAL; Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_OCM_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL); Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); } @@ -280,11 +291,11 @@ void XSlcr_EmacPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_GEM_RST_CTRL_VAL; + RegVal |= XSLCR_GEM_RST_CTRL_VAL; Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_GEM_RST_CTRL_VAL; + RegVal &= (u32)(~XSLCR_GEM_RST_CTRL_VAL); Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); } @@ -307,11 +318,11 @@ void XSlcr_UsbPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_USB_RST_CTRL_VAL; + RegVal |= XSLCR_USB_RST_CTRL_VAL; Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_USB_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL); Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -333,11 +344,11 @@ void XSlcr_QspiPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_QSPI_RST_CTRL_VAL; + RegVal |= XSLCR_QSPI_RST_CTRL_VAL; Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_QSPI_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL); Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -359,11 +370,11 @@ void XSlcr_SpiPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_SPI_RST_CTRL_VAL; + RegVal |= XSLCR_SPI_RST_CTRL_VAL; Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_SPI_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL); Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -384,11 +395,11 @@ void XSlcr_I2cPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_I2C_RST_CTRL_VAL; + RegVal |= XSLCR_I2C_RST_CTRL_VAL; Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_I2C_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL); Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -410,11 +421,11 @@ void XSlcr_UartPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_UART_RST_CTRL_VAL; + RegVal |= XSLCR_UART_RST_CTRL_VAL; Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_UART_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL); Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -436,11 +447,11 @@ void XSlcr_CanPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_CAN_RST_CTRL_VAL; + RegVal |= XSLCR_CAN_RST_CTRL_VAL; Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_CAN_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL); Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -461,11 +472,11 @@ void XSlcr_SmcPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_SMC_RST_CTRL_VAL; + RegVal |= XSLCR_SMC_RST_CTRL_VAL; Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_SMC_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL); Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -487,11 +498,11 @@ void XSlcr_DmaPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_DMAC_RST_CTRL_VAL; + RegVal |= XSLCR_DMAC_RST_CTRL_VAL; Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_DMAC_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL); Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); } /*****************************************************************************/ @@ -513,10 +524,10 @@ void XSlcr_GpioPsReset(void) Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Assert the reset */ RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_GPIO_RST_CTRL_VAL; + RegVal |= XSLCR_GPIO_RST_CTRL_VAL; Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); /* Release the reset */ RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_GPIO_RST_CTRL_VAL; + RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL); Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); -} \ No newline at end of file +} diff --git a/lib/bsp/standalone/src/microblaze/xil_misc_psreset_api.h b/lib/bsp/standalone/src/microblaze/xil_misc_psreset_api.h old mode 100755 new mode 100644 index 223fb587..5d69d746 --- a/lib/bsp/standalone/src/microblaze/xil_misc_psreset_api.h +++ b/lib/bsp/standalone/src/microblaze/xil_misc_psreset_api.h @@ -1,32 +1,43 @@ /****************************************************************************** * -* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ /*****************************************************************************/ @@ -58,137 +69,137 @@ extern "C" { #include "xil_io.h" /************************** Constant Definitions *****************************/ -#define XDDRC_CTRL_BASEADDR 0xF8006000 -#define XSLCR_BASEADDR 0xF8000000 +#define XDDRC_CTRL_BASEADDR 0xF8006000U +#define XSLCR_BASEADDR 0xF8000000U /**< OCM configuration register */ -#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x910) +#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U) /**< SLCR unlock register */ -#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x8) +#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U) /**< SLCR GEM0 rx clock control register */ -#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x138) +#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U) /**< SLCR GEM1 rx clock control register */ -#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x13C) +#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU) /**< SLCR GEM0 clock control register */ -#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x140) +#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U) /**< SLCR GEM1 clock control register */ -#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x144) +#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U) /**< SLCR SMC clock control register */ -#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x148) +#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U) /**< SLCR GEM reset control register */ -#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214) +#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U) /**< SLCR USB0 clock control register */ -#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x130) +#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U) /**< SLCR USB1 clock control register */ -#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x134) +#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U) /**< SLCR USB1 reset control register */ -#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210) +#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U) /**< SLCR SMC reset control register */ -#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234) +#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U) /**< SLCR Level shifter enable register */ -#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x900) +#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U) /**< SLCR ARM pll control register */ -#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x100) +#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U) /**< SLCR DDR pll control register */ -#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x104) +#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U) /**< SLCR IO pll control register */ -#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x108) +#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U) /**< SLCR ARM pll configuration register */ -#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x110) +#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U) /**< SLCR DDR pll configuration register */ -#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x114) +#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U) /**< SLCR IO pll configuration register */ -#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x118) +#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U) /**< SLCR ARM clock control register */ -#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x120) +#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U) /**< SLCR DDR clock control register */ -#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x124) +#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U) /**< SLCR MIO pin address register */ -#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x700) +#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U) /**< SLCR DMAC reset control address register */ -#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x20C) +#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU) /**< SLCR USB reset control address register */ -#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210) +/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/ /**< SLCR GEM reset control address register */ -#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214) +/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/ /**< SLCR SDIO reset control address register */ -#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x218) +#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U) /**< SLCR SPI reset control address register */ -#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x21C) +#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU) /**< SLCR CAN reset control address register */ -#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x220) +#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U) /**< SLCR I2C reset control address register */ -#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x224) +#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U) /**< SLCR UART reset control address register */ -#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x228) +#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U) /**< SLCR GPIO reset control address register */ -#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x22C) +#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU) /**< SLCR LQSPI reset control address register */ -#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x230) +#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U) /**< SLCR SMC reset control address register */ -#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234) +/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/ /**< SLCR OCM reset control address register */ -#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x238) +#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U) /**< SMC mem controller clear config register */ -#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0C +#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU /**< SMC idlecount configuration register */ -#define XSMC_REFRESH_PERIOD_0_OFFSET 0x20 -#define XSMC_REFRESH_PERIOD_1_OFFSET 0x24 +#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U +#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U /**< SMC ECC configuration register */ -#define XSMC_ECC_MEMCFG1_OFFSET 0x404 +#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U /**< SMC ECC command 1 register */ -#define XSMC_ECC_MEMCMD1_OFFSET 0x404 +#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U /**< SMC ECC command 2 register */ -#define XSMC_ECC_MEMCMD2_OFFSET 0x404 +#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U /**< SLCR unlock code */ -#define XSLCR_UNLOCK_CODE 0x0000DF0D +#define XSLCR_UNLOCK_CODE 0x0000DF0DU /**< SMC mem clear configuration mask */ -#define XSMC_MEMC_CLR_CONFIG_MASK 0x5F +#define XSMC_MEMC_CLR_CONFIG_MASK 0x0000005FU /**< SMC ECC memconfig 1 reset value */ -#define XSMC_ECC_MEMCFG1_RESET_VAL 0x43 +#define XSMC_ECC_MEMCFG1_RESET_VAL 0x00000043U /**< SMC ECC memcommand 1 reset value */ -#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080 +#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U /**< SMC ECC memcommand 2 reset value */ -#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585 +#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U /**< DDR controller reset bit mask */ -#define XDDRPS_CTRL_RESET_MASK 0x1 +#define XDDRPS_CTRL_RESET_MASK 0x00000001U /**< SLCR OCM configuration reset value*/ -#define XSLCR_OCM_CFG_RESETVAL 0x8 +#define XSLCR_OCM_CFG_RESETVAL 0x00000008U /**< SLCR OCM bank selection mask*/ -#define XSLCR_OCM_CFG_HIADDR_MASK 0xF +#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU /**< SLCR level shifter enable mask*/ -#define XSLCR_LVL_SHFTR_EN_MASK 0xF +#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU /**< SLCR PLL register reset values */ -#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008 -#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008 -#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008 -#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0 -#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0 -#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0 -#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400 -#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003 +#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U +#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U /**< SLCR MIO register default values */ -#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601 -#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601 +#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U +#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U /**< SLCR Reset control registers default values */ -#define XSLCR_DMAC_RST_CTRL_VAL 0x1 -#define XSLCR_GEM_RST_CTRL_VAL 0xF3 -#define XSLCR_USB_RST_CTRL_VAL 0x3 -#define XSLCR_I2C_RST_CTRL_VAL 0x3 -#define XSLCR_SPI_RST_CTRL_VAL 0xF -#define XSLCR_UART_RST_CTRL_VAL 0xF -#define XSLCR_QSPI_RST_CTRL_VAL 0x3 -#define XSLCR_GPIO_RST_CTRL_VAL 0x1 -#define XSLCR_SMC_RST_CTRL_VAL 0x3 -#define XSLCR_OCM_RST_CTRL_VAL 0x1 -#define XSLCR_SDIO_RST_CTRL_VAL 0x33 -#define XSLCR_CAN_RST_CTRL_VAL 0x3 +#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U +#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U +#define XSLCR_USB_RST_CTRL_VAL 0x00000003U +#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U +#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU +#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU +#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U +#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U +#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U +#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U +#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U +#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U /**************************** Type Definitions *******************************/ /* the following data type is used to hold a null terminated version string @@ -203,11 +214,11 @@ extern "C" { /* * Performs reset operation to the ddr interface */ -void XDdr_ResetHw(); +void XDdr_ResetHw(void); /* * Map the ocm region to post bootrom state */ -void XOcm_Remap(); +void XOcm_Remap(void); /* * Performs the smc interface reset */ @@ -215,15 +226,15 @@ void XSmc_ResetHw(u32 BaseAddress); /* * updates the MIO registers with reset values */ -void XSlcr_MioWriteResetValues(); +void XSlcr_MioWriteResetValues(void); /* * updates the PLL and clock registers with reset values */ -void XSlcr_PllWriteResetValues(); +void XSlcr_PllWriteResetValues(void); /* * Disables the level shifters */ -void XSlcr_DisableLevelShifters(); +void XSlcr_DisableLevelShifters(void); /* * provides softreset to the GPIO interface */ diff --git a/lib/bsp/standalone/src/microblaze/xil_printf.h b/lib/bsp/standalone/src/microblaze/xil_printf.h old mode 100755 new mode 100644 index f82f9c97..5d689e77 --- a/lib/bsp/standalone/src/microblaze/xil_printf.h +++ b/lib/bsp/standalone/src/microblaze/xil_printf.h @@ -1,42 +1,55 @@ /****************************************************************************** * -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ #ifndef XIL_PRINTF_H #define XIL_PRINTF_H +#include "xil_types.h" + #ifdef __cplusplus extern "C" { #endif -void xil_printf(const char *ctrl1, ...); +void xil_printf(const char8 *ctrl1, ...); void print(char *ptr); #ifdef __cplusplus diff --git a/lib/bsp/standalone/src/profile/Makefile b/lib/bsp/standalone/src/profile/Makefile old mode 100755 new mode 100644 index 0162ad7b..df115b5e --- a/lib/bsp/standalone/src/profile/Makefile +++ b/lib/bsp/standalone/src/profile/Makefile @@ -1,48 +1,58 @@ -#$Id: Makefile,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $ ############################################################################### # -# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: +# This file contains confidential and proprietary information of Xilinx, Inc. +# and is protected under U.S. and international copyright and other +# intellectual property laws. # -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. +# DISCLAIMER +# This disclaimer is not a license and does not grant any rights to the +# materials distributed herewith. Except as otherwise provided in a valid +# license issued to you by Xilinx, and to the maximum extent permitted by +# applicable law: +# (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +# XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +# OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +# NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +# and +# (2) Xilinx shall not be liable (whether in contract or tort, including +# negligence, or under any other theory of liability) for any loss or damage of +# any kind or nature related to, arising under or in connection with these +# materials, including for any direct, or any indirect, special, incidental, +# or consequential loss or damage (including loss of data, profits, goodwill, +# or any type of loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was reasonably foreseeable +# or Xilinx had been advised of the possibility of the same. # -# Use of the Software is limited solely to applications: -# (a) running on a Xilinx device, or -# (b) that interact with a Xilinx device through a bus or interconnect. +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail-safe, or for use in +# any application requiring fail-safe performance, such as life-support or +# safety devices or systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any other applications +# that could lead to death, personal injury, or severe property or environmental +# damage (individually and collectively, "Critical Applications"). +# Customer assumes the sole risk and liability of any use of Xilinx products in +# Critical Applications, subject only to applicable laws and regulations +# governing limitations on product liability. # -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -# SOFTWARE. -# -# Except as contained in this notice, the name of the Xilinx shall not be used -# in advertising or otherwise to promote the sale, use or other dealings in -# this Software without prior written authorization from Xilinx. +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +# AT ALL TIMES. # ############################################################################### # # Makefile for profiler -# +# ####################################################################### # PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here include ../config.make AS=mb-as -COMPILER = mb-gcc +COMPILER = mb-gcc ARCHIVER = mb-ar CP = cp -COMPILER_FLAGS=-O2 +COMPILER_FLAGS=-O2 EXTRA_COMPILER_FLAGS= LIB = libxil.a DUMMYLIB = libxilprofile.a @@ -54,7 +64,7 @@ RELEASEDIR = ../../../../lib INCLUDEDIR = ../../../../include INCLUDES = -I./. -I${INCLUDEDIR} -OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o +OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o DUMMYOBJ = dummy.o INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h @@ -72,7 +82,7 @@ dummylibs : $(DUMMYOBJ) %.o:%.S $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES) -include: +include: $(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR) clean: diff --git a/lib/bsp/standalone/src/profile/_profile_clean.c b/lib/bsp/standalone/src/profile/_profile_clean.c old mode 100755 new mode 100644 index a5d6f1aa..8a540273 --- a/lib/bsp/standalone/src/profile/_profile_clean.c +++ b/lib/bsp/standalone/src/profile/_profile_clean.c @@ -1,33 +1,43 @@ -// $Id: _profile_clean.c,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE. +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ @@ -35,6 +45,8 @@ #include "_profile_timer_hw.h" #include "xil_exception.h" +void _profile_clean( void ); + /* * This function is the exit routine and is called by the crtinit, when the * program terminates. The name needs to be changed later.. diff --git a/lib/bsp/standalone/src/profile/_profile_init.c b/lib/bsp/standalone/src/profile/_profile_init.c old mode 100755 new mode 100644 index 7a732ef0..f2b084da --- a/lib/bsp/standalone/src/profile/_profile_init.c +++ b/lib/bsp/standalone/src/profile/_profile_init.c @@ -1,33 +1,43 @@ -// $Id: _profile_init.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ****************************************************************************** * @@ -38,57 +48,55 @@ #include "profile.h" -// XMD Initializes the following Global Variables Value during Program -// Download with appropriate values. +/* XMD Initializes the following Global Variables Value during Program + * Download with appropriate values. */ #ifdef PROC_MICROBLAZE -extern int microblaze_init(void); +extern s32 microblaze_init(void); #elif defined PROC_PPC -extern int powerpc405_init(void); +extern s32 powerpc405_init(void); #else -extern int cortexa9_init(void); +extern s32 cortexa9_init(void); #endif +s32 profile_version = 1; /* Version of S/W Intrusive Profiling library */ +u32 binsize = (u32)BINSIZE; /* Histogram Bin Size */ +u32 cpu_clk_freq = (u32)CPU_FREQ_HZ ; /* CPU Clock Frequency */ +u32 sample_freq_hz = (u32)SAMPLE_FREQ_HZ ; /* Histogram Sampling Frequency */ +u32 timer_clk_ticks = (u32)TIMER_CLK_TICKS ;/* Timer Clock Ticks for the Timer */ -int profile_version = 1; // Version of S/W Intrusive Profiling library +/* Structure for Storing the Profiling Data */ +struct gmonparam *_gmonparam = (struct gmonparam *)(0xffffffffU); +s32 n_gmon_sections = 1; -int binsize = BINSIZE; // Histogram Bin Size -unsigned int cpu_clk_freq = CPU_FREQ_HZ ; // CPU Clock Frequency -unsigned int sample_freq_hz = SAMPLE_FREQ_HZ ; // Histogram Sampling Frequency -unsigned int timer_clk_ticks = TIMER_CLK_TICKS ;// Timer Clock Ticks for the Timer +/* This is the initialization code, which is called from the crtinit. */ -// Structure for Storing the Profiling Data -struct gmonparam *_gmonparam = (struct gmonparam *)0xffffffff; -int n_gmon_sections = 1; - -// This is the initialization code, which is called from the crtinit. -// void _profile_init( void ) { -/* print("Gmon Init called....\r\n") ; */ -/* putnum(n_gmon_sections) ; print("\r\n") ; */ +/* print("Gmon Init called....\r\n") */ +/* putnum(n_gmon_sections) , print("\r\n") */ /* if( _gmonparam == 0xffffffff ) */ -/* printf("Gmonparam is NULL !!\r\n"); */ -/* for( i = 0; i < n_gmon_sections; i++ ){ */ -/* putnum(_gmonparam[i].lowpc) ; print("\t") ; */ -/* putnum(_gmonparam[i].highpc) ; print("\r\n") ; */ -/* putnum( _gmonparam[i].textsize ); print("\r\n") ; */ -/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short));print("\r\n"); */ -/* } */ +/* printf("Gmonparam is NULL !!\r\n") */ +/* for( i = 0, i < n_gmon_sections, i++ )[ */ +/* putnum( _gmonparam[i].lowpc) , print("\t") */ +/* putnum( _gmonparam[i].highpc) , print("\r\n") */ +/* putnum( _gmonparam[i].textsize ), print("\r\n") */ +/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short)), print("\r\n") */ +/* ] */ #ifdef PROC_MICROBLAZE - microblaze_init(); + (void)microblaze_init(); #elif defined PROC_PPC powerpc405_init(); #else - cortexa9_init (); + (void)cortexa9_init(); #endif } diff --git a/lib/bsp/standalone/src/profile/_profile_timer_hw.c b/lib/bsp/standalone/src/profile/_profile_timer_hw.c old mode 100755 new mode 100644 index 83d5a1ab..6585d029 --- a/lib/bsp/standalone/src/profile/_profile_timer_hw.c +++ b/lib/bsp/standalone/src/profile/_profile_timer_hw.c @@ -1,33 +1,43 @@ -// $Id: _profile_timer_hw.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ****************************************************************************** * @@ -49,33 +59,61 @@ #ifdef TIMER_CONNECT_INTC #include "xintc_l.h" #include "xintc.h" -#endif // TIMER_CONNECT_INTC +#endif /* TIMER_CONNECT_INTC */ -//#ifndef PPC_PIT_INTERRUPT +/* #ifndef PPC_PIT_INTERRUPT */ #if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) #include "xtmrctr_l.h" #endif -extern unsigned int timer_clk_ticks ; +/* extern u32 timer_clk_ticks, */ -//-------------------------------------------------------------------- -// PowerPC Target - Timer related functions -//-------------------------------------------------------------------- +#ifdef PROC_PPC405 +#ifdef PPC_PIT_INTERRUPT +s32 ppc_pit_init( void ); +#endif +s32 powerpc405_init() +#endif /* PROC_CORTEXA9 */ + +#ifdef PROC_PPC440 +#ifdef PPC_PIT_INTERRUPT +s32 ppc_dec_init( void ); +#endif +s32 powerpc405_init(void); +#endif /* PROC_PPC440 */ + +#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) +s32 opb_timer_init( void ); +#endif + +#ifdef PROC_MICROBLAZE +s32 microblaze_init(void); +#endif /* PROC_MICROBLAZE */ + +#ifdef PROC_CORTEXA9 +s32 scu_timer_init( void ); +s32 cortexa9_init(void); +#endif /* PROC_CORTEXA9 */ + + +/*-------------------------------------------------------------------- + * PowerPC Target - Timer related functions + *-------------------------------------------------------------------- */ #ifdef PROC_PPC405 -//-------------------------------------------------------------------- -// PowerPC PIT Timer Init. -// Defined only if PIT Timer is used for Profiling -// -//-------------------------------------------------------------------- +/*-------------------------------------------------------------------- +* PowerPC PIT Timer Init. +* Defined only if PIT Timer is used for Profiling +* +*-------------------------------------------------------------------- */ #ifdef PPC_PIT_INTERRUPT int ppc_pit_init( void ) { - // 1. Register Profile_intr_handler as Interrupt handler - // 2. Set PIT Timer Interrupt and Enable it. + /* 1. Register Profile_intr_handler as Interrupt handler */ + /* 2. Set PIT Timer Interrupt and Enable it. */ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT, - (Xil_ExceptionHandler)profile_intr_handler,(void *)0); + (Xil_ExceptionHandler)profile_intr_handler,NULL); XTime_PITSetInterval( timer_clk_ticks ) ; XTime_PITEnableAutoReload() ; return 0; @@ -83,38 +121,38 @@ int ppc_pit_init( void ) #endif -//-------------------------------------------------------------------- -// PowerPC Timer Initialization functions. -// For PowerPC, PIT and opb_timer can be used for Profiling. This -// is selected by the user in standalone BSP -// -//-------------------------------------------------------------------- -int powerpc405_init() +/* -------------------------------------------------------------------- +* PowerPC Timer Initialization functions. +* For PowerPC, PIT and opb_timer can be used for Profiling. This +* is selected by the user in standalone BSP +* +*-------------------------------------------------------------------- */ +s32 powerpc405_init() { Xil_ExceptionInit() ; Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ; - // Initialize the Timer. - // 1. If PowerPC PIT Timer has to be used, initialize PIT timer. - // 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC + /* Initialize the Timer. + * 1. If PowerPC PIT Timer has to be used, initialize PIT timer. + * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */ #ifdef PPC_PIT_INTERRUPT ppc_pit_init(); #else #ifdef TIMER_CONNECT_INTC Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, - (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0); + (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL); XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID, - (XInterruptHandler)profile_intr_handler,(void*)0); + (XInterruptHandler)profile_intr_handler,NULL); #else Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, - (Xil_ExceptionHandler)profile_intr_handler,(void *)0); + (Xil_ExceptionHandler)profile_intr_handler,NULL); #endif - // Initialize the timer with Timer Ticks + /* Initialize the timer with Timer Ticks */ opb_timer_init() ; #endif - // Enable Interrupts in the System, if Profile Timer is the only Interrupt - // in the System. + /* Enable Interrupts in the System, if Profile Timer is the only Interrupt + * in the System. */ #ifdef ENABLE_SYS_INTR #ifdef PPC_PIT_INTERRUPT XTime_PITEnableInterrupt() ; @@ -128,28 +166,28 @@ int powerpc405_init() return 0; } -#endif // PROC_PPC +#endif /* PROC_PPC */ -//-------------------------------------------------------------------- -// PowerPC440 Target - Timer related functions -//-------------------------------------------------------------------- +/*-------------------------------------------------------------------- + * PowerPC440 Target - Timer related functions + * -------------------------------------------------------------------- */ #ifdef PROC_PPC440 -//-------------------------------------------------------------------- -// PowerPC DEC Timer Init. -// Defined only if DEC Timer is used for Profiling -// -//-------------------------------------------------------------------- +/*-------------------------------------------------------------------- + * PowerPC DEC Timer Init. + * Defined only if DEC Timer is used for Profiling + * + *-------------------------------------------------------------------- */ #ifdef PPC_PIT_INTERRUPT -int ppc_dec_init( void ) +s32 ppc_dec_init( void ) { - // 1. Register Profile_intr_handler as Interrupt handler - // 2. Set DEC Timer Interrupt and Enable it. + /* 1. Register Profile_intr_handler as Interrupt handler */ + /* 2. Set DEC Timer Interrupt and Enable it. */ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT, - (Xil_ExceptionHandler)profile_intr_handler,(void *)0); + (Xil_ExceptionHandler)profile_intr_handler,NULL); XTime_DECSetInterval( timer_clk_ticks ) ; XTime_DECEnableAutoReload() ; return 0; @@ -157,41 +195,41 @@ int ppc_dec_init( void ) #endif -//-------------------------------------------------------------------- -// PowerPC Timer Initialization functions. -// For PowerPC, DEC and opb_timer can be used for Profiling. This -// is selected by the user in standalone BSP -// -//-------------------------------------------------------------------- -int powerpc405_init(void) +/*-------------------------------------------------------------------- + * PowerPC Timer Initialization functions. + * For PowerPC, DEC and opb_timer can be used for Profiling. This + * is selected by the user in standalone BSP + * + *-------------------------------------------------------------------- */ +s32 powerpc405_init(void) { Xil_ExceptionInit(); Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ; - // Initialize the Timer. - // 1. If PowerPC DEC Timer has to be used, initialize DEC timer. - // 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC + /* Initialize the Timer. + * 1. If PowerPC DEC Timer has to be used, initialize DEC timer. + * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */ #ifdef PPC_PIT_INTERRUPT ppc_dec_init(); #else #ifdef TIMER_CONNECT_INTC Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT, - (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0); + (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL); XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID, - (XInterruptHandler)profile_intr_handler,(void*)0); + (XInterruptHandler)profile_intr_handler,NULL); #else Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, - (Xil_ExceptionHandler)profile_intr_handler,(void *)0); + (Xil_ExceptionHandler)profile_intr_handler,NULL); Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, - (Xil_ExceptionHandler)profile_intr_handler,(void *)0); + (Xil_ExceptionHandler)profile_intr_handler,NULL); #endif - // Initialize the timer with Timer Ticks + /* Initialize the timer with Timer Ticks */ opb_timer_init() ; #endif - // Enable Interrupts in the System, if Profile Timer is the only Interrupt - // in the System. + /* Enable Interrupts in the System, if Profile Timer is the only Interrupt + * in the System. */ #ifdef ENABLE_SYS_INTR #ifdef PPC_PIT_INTERRUPT XTime_DECEnableInterrupt() ; @@ -205,73 +243,73 @@ int powerpc405_init(void) return 0; } -#endif // PROC_PPC440 +#endif /* PROC_PPC440 */ -//-------------------------------------------------------------------- -// opb_timer Initialization for PowerPC and MicroBlaze. This function -// is not needed if DEC timer is used in PowerPC -// -//-------------------------------------------------------------------- -//#ifndef PPC_PIT_INTERRUPT +/* -------------------------------------------------------------------- + * opb_timer Initialization for PowerPC and MicroBlaze. This function + * is not needed if DEC timer is used in PowerPC + * + *-------------------------------------------------------------------- */ +/* #ifndef PPC_PIT_INTERRUPT */ #if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) -int opb_timer_init( void ) +s32 opb_timer_init( void ) { - // set the number of cycles the timer counts before interrupting - XTmrCtr_SetLoadReg(PROFILE_TIMER_BASEADDR, 0, timer_clk_ticks); + /* set the number of cycles the timer counts before interrupting */ + XTmrCtr_SetLoadReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)timer_clk_ticks); - // reset the timers, and clear interrupts - XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, - XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK ); + /* reset the timers, and clear interrupts */ + XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, + (u32)XTC_CSR_INT_OCCURED_MASK | (u32)XTC_CSR_LOAD_MASK ); - // start the timers - XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK - | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK); + /* start the timers */ + XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)XTC_CSR_ENABLE_TMR_MASK + | (u32)XTC_CSR_ENABLE_INT_MASK | (u32)XTC_CSR_AUTO_RELOAD_MASK | (u32)XTC_CSR_DOWN_COUNT_MASK); return 0; } #endif -//-------------------------------------------------------------------- -// MicroBlaze Target - Timer related functions -//-------------------------------------------------------------------- +/*-------------------------------------------------------------------- + * MicroBlaze Target - Timer related functions + *-------------------------------------------------------------------- */ #ifdef PROC_MICROBLAZE -//-------------------------------------------------------------------- -// Initialize the Profile Timer for MicroBlaze Target. -// For MicroBlaze, opb_timer is used. The opb_timer can be directly -// connected to MicroBlaze or connected through Interrupt Controller. -// -//-------------------------------------------------------------------- -int microblaze_init(void) +/* -------------------------------------------------------------------- + * Initialize the Profile Timer for MicroBlaze Target. + * For MicroBlaze, opb_timer is used. The opb_timer can be directly + * connected to MicroBlaze or connected through Interrupt Controller. + * + *-------------------------------------------------------------------- */ +s32 microblaze_init(void) { - // Register profile_intr_handler - // 1. If timer is connected to Interrupt Controller, register the handler - // to Interrupt Controllers vector table. - // 2. If timer is directly connected to MicroBlaze, register the handler - // as Interrupt handler + /* Register profile_intr_handler + * 1. If timer is connected to Interrupt Controller, register the handler + * to Interrupt Controllers vector table. + * 2. If timer is directly connected to MicroBlaze, register the handler + * as Interrupt handler */ Xil_ExceptionInit(); #ifdef TIMER_CONNECT_INTC XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID, - (XInterruptHandler)profile_intr_handler,(void*)0); + (XInterruptHandler)profile_intr_handler,NULL); #else Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)profile_intr_handler, - (void *)0) ; + NULL) ; #endif - // Initialize the timer with Timer Ticks - opb_timer_init() ; + /* Initialize the timer with Timer Ticks */ + (void)opb_timer_init() ; - // Enable Interrupts in the System, if Profile Timer is the only Interrupt - // in the System. + /* Enable Interrupts in the System, if Profile Timer is the only Interrupt + * in the System. */ #ifdef ENABLE_SYS_INTR #ifdef TIMER_CONNECT_INTC - XIntc_MasterEnable( INTC_BASEADDR ); + XIntc_MasterEnable((u32)INTC_BASEADDR ); XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION); - XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK ); + XIntc_EnableIntr( (u32)INTC_BASEADDR, PROFILE_TIMER_INTR_MASK ); Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, - (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0); + (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL); #endif #endif @@ -282,37 +320,37 @@ int microblaze_init(void) } -#endif // PROC_MICROBLAZE +#endif /* PROC_MICROBLAZE */ -//-------------------------------------------------------------------- -// Cortex A9 Target - Timer related functions -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Cortex A9 Target - Timer related functions + *-------------------------------------------------------------------- */ #ifdef PROC_CORTEXA9 -//-------------------------------------------------------------------- -// Initialize the Profile Timer for Cortex A9 Target. -// The scu private timer is connected to the Scu GIC controller. -// -//-------------------------------------------------------------------- -int scu_timer_init( void ) +/* -------------------------------------------------------------------- + * Initialize the Profile Timer for Cortex A9 Target. + * The scu private timer is connected to the Scu GIC controller. + * + *-------------------------------------------------------------------- */ +s32 scu_timer_init( void ) { - // set the number of cycles the timer counts before interrupting - // scu timer runs at half the cpu clock - XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2); + /* set the number of cycles the timer counts before interrupting + * scu timer runs at half the cpu clock */ + XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2U); - // clear any pending interrupts - XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1); + /* clear any pending interrupts */ + XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1U); - // enable interrupts, auto-reload mode and start the timer + /* enable interrupts, auto-reload mode and start the timer */ XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK | XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK); return 0; } -int cortexa9_init(void) +s32 cortexa9_init(void) { Xil_ExceptionInit(); @@ -325,7 +363,7 @@ int cortexa9_init(void) */ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, (Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler, - (void *)0); + NULL); /* * Connect the device driver handler that will be called when an @@ -335,7 +373,7 @@ int cortexa9_init(void) XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR, PROFILE_TIMER_INTR_ID, (Xil_ExceptionHandler)profile_intr_handler, - (void *)0); + NULL); /* * Enable the interrupt for scu timer. @@ -350,11 +388,11 @@ int cortexa9_init(void) /* * Initialize the timer with Timer Ticks */ - scu_timer_init() ; + (void)scu_timer_init() ; Xil_ExceptionEnable(); return 0; } -#endif // PROC_CORTEXA9 +#endif /* PROC_CORTEXA9 */ diff --git a/lib/bsp/standalone/src/profile/_profile_timer_hw.h b/lib/bsp/standalone/src/profile/_profile_timer_hw.h old mode 100755 new mode 100644 index 650afb23..efca4721 --- a/lib/bsp/standalone/src/profile/_profile_timer_hw.h +++ b/lib/bsp/standalone/src/profile/_profile_timer_hw.h @@ -1,33 +1,43 @@ -// $Id: _profile_timer_hw.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ /****************************************************************************** * -* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ****************************************************************************** * @@ -36,8 +46,8 @@ * ******************************************************************************/ -#ifndef _PROFILE_TIMER_HW_H -#define _PROFILE_TIMER_HW_H +#ifndef PROFILE_TIMER_HW_H +#define PROFILE_TIMER_HW_H #include "profile.h" @@ -52,26 +62,26 @@ #endif #ifdef PROC_PPC -#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; +#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; } #define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; } #else #define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); -#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); } +#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); } #endif #define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\ - ProfIo_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \ - (RegOffset)), (ValueToWrite)) + ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \ + (u32)(RegOffset)), (u32)(ValueToWrite)) #define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \ - ProfIo_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + (RegOffset)) + ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset)) #define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\ ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ (RegisterValue)) #define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \ - ProfTimerCtr_mReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET) + ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET) @@ -88,7 +98,7 @@ extern "C" { #ifdef TIMER_CONNECT_INTC #include "xintc_l.h" #include "xintc.h" -#endif // TIMER_CONNECT_INTC +#endif /* TIMER_CONNECT_INTC */ #if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) #include "xtmrctr_l.h" @@ -99,15 +109,15 @@ extern "C" { #include "xscugic.h" #endif -extern unsigned int timer_clk_ticks ; +extern u32 timer_clk_ticks ; -//-------------------------------------------------------------------- -// PowerPC Target - Timer related functions -//-------------------------------------------------------------------- +/*-------------------------------------------------------------------- + * PowerPC Target - Timer related functions + *-------------------------------------------------------------------- */ #ifdef PROC_PPC #ifdef PPC_PIT_INTERRUPT -unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG +u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */ #endif #ifdef PROC_PPC440 @@ -117,21 +127,21 @@ unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG #define XEXC_ID_PIT_INT XEXC_ID_DEC_INT #endif -//-------------------------------------------------------------------- -// Disable the Timer - During Profiling -// -// For PIT Timer - -// 1. XTime_PITDisableInterrupt() ; -// 2. Store the remaining timer clk tick -// 3. Stop the PIT Timer -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Disable the Timer - During Profiling + * + * For PIT Timer - + * 1. XTime_PITDisableInterrupt() ; + * 2. Store the remaining timer clk tick + * 3. Stop the PIT Timer + *-------------------------------------------------------------------- */ #ifdef PPC_PIT_INTERRUPT #define disable_timer() \ { \ - unsigned long val; \ + u32 val; \ val=mfspr(XREG_SPR_TCR); \ - mtspr(XREG_SPR_TCR, val & ~XREG_TCR_PIT_INTERRUPT_ENABLE); \ + mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \ timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \ mtspr(XREG_SPR_PIT, 0); \ } @@ -140,24 +150,24 @@ unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG { \ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ u32 tmp_v = ProfIo_In32(addr); \ - tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \ + tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ } #endif -//-------------------------------------------------------------------- -// Enable the Timer -// -// For PIT Timer - -// 1. Load the remaining timer clk ticks -// 2. XTime_PITEnableInterrupt() ; -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Enable the Timer + * + * For PIT Timer - + * 1. Load the remaining timer clk ticks + * 2. XTime_PITEnableInterrupt() ; + *-------------------------------------------------------------------- */ #ifdef PPC_PIT_INTERRUPT #define enable_timer() \ { \ - unsigned long val; \ + u32 val; \ val=mfspr(XREG_SPR_TCR); \ mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \ mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \ @@ -174,18 +184,18 @@ unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG -//-------------------------------------------------------------------- -// Send Ack to Timer Interrupt -// -// For PIT Timer - -// 1. Load the timer clk ticks -// 2. Enable AutoReload and Interrupt -// 3. Clear PIT Timer Status bits -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + * For PIT Timer - + * 1. Load the timer clk ticks + * 2. Enable AutoReload and Interrupt + * 3. Clear PIT Timer Status bits + *-------------------------------------------------------------------- */ #ifdef PPC_PIT_INTERRUPT #define timer_ack() \ { \ - unsigned long val; \ + u32 val; \ mtspr(XREG_SPR_PIT, timer_clk_ticks); \ mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \ val=mfspr(XREG_SPR_TCR); \ @@ -194,109 +204,116 @@ unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG #else #define timer_ack() \ { \ - unsigned int csr; \ + u32 csr; \ csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \ ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \ } #endif -//-------------------------------------------------------------------- -#endif // PROC_PPC -//-------------------------------------------------------------------- +/*-------------------------------------------------------------------- */ +#endif /* PROC_PPC */ +/* -------------------------------------------------------------------- */ -//-------------------------------------------------------------------- -// MicroBlaze Target - Timer related functions -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * MicroBlaze Target - Timer related functions + *-------------------------------------------------------------------- */ #ifdef PROC_MICROBLAZE -//-------------------------------------------------------------------- -// Disable the Timer during Call-Graph Data collection -// -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Disable the Timer during Call-Graph Data collection + * + *-------------------------------------------------------------------- */ #define disable_timer() \ { \ - u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ - u32 tmp_v = ProfIo_In32(addr); \ - tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \ - ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \ + Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + Addr += (u32)XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(Addr); \ + tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \ + u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \ + OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + OutAddr += (u32)XTC_TCSR_OFFSET; \ + ProfIo_Out32(OutAddr, (u32)tmp_v); \ } -//-------------------------------------------------------------------- -// Enable the Timer after Call-Graph Data collection -// -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Enable the Timer after Call-Graph Data collection + * + *-------------------------------------------------------------------- */ #define enable_timer() \ { \ - u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ - u32 tmp_v = ProfIo_In32(addr); \ - tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \ - ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \ + Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + Addr += (u32)XTC_TCSR_OFFSET; \ + u32 tmp_v = (u32)ProfIo_In32(Addr); \ + tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \ + ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \ } -//-------------------------------------------------------------------- -// Send Ack to Timer Interrupt -// -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + *-------------------------------------------------------------------- */ #define timer_ack() \ { \ - unsigned int csr; \ - csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \ - ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \ + u32 csr; \ + csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \ + ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \ } -//-------------------------------------------------------------------- -#endif // PROC_MICROBLAZE -//-------------------------------------------------------------------- +/*-------------------------------------------------------------------- */ +#endif /* PROC_MICROBLAZE */ +/*-------------------------------------------------------------------- */ -//-------------------------------------------------------------------- -// Cortex A9 Target - Timer related functions -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Cortex A9 Target - Timer related functions + *-------------------------------------------------------------------- */ #ifdef PROC_CORTEXA9 -//-------------------------------------------------------------------- -// Disable the Timer during Call-Graph Data collection -// -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Disable the Timer during Call-Graph Data collection + * + *-------------------------------------------------------------------- */ #define disable_timer() \ { \ u32 Reg; \ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ - Reg &= ~XSCUTIMER_CONTROL_ENABLE_MASK;\ + Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ -} \ +} -//-------------------------------------------------------------------- -// Enable the Timer after Call-Graph Data collection -// -//-------------------------------------------------------------------- +/* -------------------------------------------------------------------- + * Enable the Timer after Call-Graph Data collection + * + *-------------------------------------------------------------------- */ #define enable_timer() \ { \ u32 Reg; \ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ -} \ - - -//-------------------------------------------------------------------- -// Send Ack to Timer Interrupt -// -//-------------------------------------------------------------------- -#define timer_ack() \ -{ \ - Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_ISR_OFFSET, \ - XSCUTIMER_ISR_EVENT_FLAG_MASK);\ } -//-------------------------------------------------------------------- -#endif // PROC_CORTEXA9 -//-------------------------------------------------------------------- + +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + *-------------------------------------------------------------------- */ +#define timer_ack() \ +{ \ + Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \ + (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\ +} + +/*-------------------------------------------------------------------- */ +#endif /* PROC_CORTEXA9 */ +/*-------------------------------------------------------------------- */ #ifdef __cplusplus diff --git a/lib/bsp/standalone/src/profile/dummy.S b/lib/bsp/standalone/src/profile/dummy.S old mode 100755 new mode 100644 index 78f31ab0..cb4e1e68 --- a/lib/bsp/standalone/src/profile/dummy.S +++ b/lib/bsp/standalone/src/profile/dummy.S @@ -1,65 +1,75 @@ -// $Id: dummy.S,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ .globl dummy_f #ifdef PROC_MICROBLAZE - .text + .text .align 2 .ent dummy_f dummy_f: nop - .end dummy_f + .end dummy_f #endif -#ifdef PROC_PPC +#ifdef PROC_PPC .section .text .align 2 .type dummy_f@function - -dummy_f: + +dummy_f: b dummy_f - + #endif -#ifdef PROC_CORTEXA9 +#ifdef PROC_CORTEXA9 .section .text .align 2 .type dummy_f, %function - -dummy_f: + +dummy_f: b dummy_f - + #endif diff --git a/lib/bsp/standalone/src/profile/mblaze_nt_types.h b/lib/bsp/standalone/src/profile/mblaze_nt_types.h old mode 100755 new mode 100644 index 467c33da..0722dad1 --- a/lib/bsp/standalone/src/profile/mblaze_nt_types.h +++ b/lib/bsp/standalone/src/profile/mblaze_nt_types.h @@ -1,33 +1,43 @@ -// $Id: mblaze_nt_types.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ diff --git a/lib/bsp/standalone/src/profile/profile.h b/lib/bsp/standalone/src/profile/profile.h old mode 100755 new mode 100644 index 1296a771..50d6ca12 --- a/lib/bsp/standalone/src/profile/profile.h +++ b/lib/bsp/standalone/src/profile/profile.h @@ -1,40 +1,51 @@ -// $Id: profile.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ -#ifndef _PROFILE_H -#define _PROFILE_H 1 +#ifndef PROFILE_H +#define PROFILE_H 1 #include +#include "xil_types.h" #include "profile_config.h" #ifdef PROC_MICROBLAZE @@ -47,8 +58,9 @@ extern "C" { void _system_init( void ) ; void _system_clean( void ) ; -void mcount(unsigned long frompc, unsigned long selfpc); +void mcount(u32 frompc, u32 selfpc); void profile_intr_handler( void ) ; +void _profile_init( void ); @@ -59,19 +71,19 @@ void profile_intr_handler( void ) ; /* * histogram counters are unsigned shorts (according to the kernel). */ -#define HISTCOUNTER unsigned short +#define HISTCOUNTER u16 struct tostruct { - unsigned long selfpc; - long count; - short link; - unsigned short pad; + u32 selfpc; + s32 count; + s16 link; + u16 pad; }; struct fromstruct { - unsigned long frompc ; - short link ; - unsigned short pad ; + u32 frompc ; + s16 link ; + u16 pad ; } ; /* @@ -84,27 +96,27 @@ struct fromstruct { * The profiling data structures are housed in this structure. */ struct gmonparam { - long int state; + s32 state; - // Histogram Information - unsigned short *kcount; /* No. of bins in histogram */ - unsigned long kcountsize; /* Histogram samples */ + /* Histogram Information */ + u16 *kcount; /* No. of bins in histogram */ + u32 kcountsize; /* Histogram samples */ - // Call-graph Information + /* Call-graph Information */ struct fromstruct *froms; - unsigned long fromssize; + u32 fromssize; struct tostruct *tos; - unsigned long tossize; + u32 tossize; - // Initialization I/Ps - unsigned long lowpc; - unsigned long highpc; - unsigned long textsize; - //unsigned long cg_froms; - //unsigned long cg_tos; + /* Initialization I/Ps */ + u32 lowpc; + u32 highpc; + u32 textsize; + /* u32 cg_froms, */ + /* u32 cg_tos, */ }; extern struct gmonparam *_gmonparam; -extern int n_gmon_sections; +extern s32 n_gmon_sections; /* * Possible states of profiling. @@ -127,16 +139,5 @@ extern int n_gmon_sections; } #endif -#endif /* _PROFILE_H */ - - - - - - - - - - - +#endif /* PROFILE_H */ diff --git a/lib/bsp/standalone/src/profile/profile_cg.c b/lib/bsp/standalone/src/profile/profile_cg.c old mode 100755 new mode 100644 index 5c3cf891..883c62be --- a/lib/bsp/standalone/src/profile/profile_cg.c +++ b/lib/bsp/standalone/src/profile/profile_cg.c @@ -1,33 +1,43 @@ -// $Id: profile_cg.c,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ @@ -47,58 +57,69 @@ #include #include -extern struct gmonparam *_gmonparam; +#ifdef PROFILE_NO_FUNCPTR +s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc ); +#else +s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc ); +#endif + +/*extern struct gmonparam *_gmonparam, */ #ifdef PROFILE_NO_FUNCPTR -int searchpc( struct fromto_struct *cgtable, int cgtable_size, unsigned long frompc ) +s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc ) { - int index = 0 ; + s32 index = 0 ; while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){ index++ ; } - if( index == cgtable_size ) + if( index == cgtable_size ) { return -1 ; - else + } else { return index ; + } } #else -int searchpc( struct fromstruct *froms, int fromssize, unsigned long frompc ) +s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc ) { - int index = 0 ; + s32 index = 0 ; + s32 Status; while( (index < fromssize) && (froms[index].frompc != frompc) ){ index++ ; } - if( index == fromssize ) - return -1 ; - else - return index ; + if( index == fromssize ) { + Status = -1 ; + } else { + Status = index ; + } + return Status; } #endif /* PROFILE_NO_FUNCPTR */ -void mcount( unsigned long frompc, unsigned long selfpc ) +void mcount( u32 frompc, u32 selfpc ) { register struct gmonparam *p = NULL; - register long toindex, fromindex; - int j; + register s32 toindex, fromindex; + s32 j; disable_timer(); - //print("CG: "); putnum(frompc); print("->"); putnum(selfpc); print("\r\n"); - // check that frompcindex is a reasonable pc value. - // for example: signal catchers get called from the stack, - // not from text space. too bad. - // + /*print("CG: "), putnum(frompc), print("->"), putnum(selfpc), print("\r\n") , + * check that frompcindex is a reasonable pc value. + * for example: signal catchers get called from the stack, + * not from text space. too bad. + */ for(j = 0; j < n_gmon_sections; j++ ){ if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) { p = &_gmonparam[j]; break; } } - if( j == n_gmon_sections ) + if( j == n_gmon_sections ) { goto done; + } #ifdef PROFILE_NO_FUNCPTR fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ; @@ -112,47 +133,47 @@ void mcount( unsigned long frompc, unsigned long selfpc ) } p->cgtable[fromindex].count++ ; #else - fromindex = searchpc( p->froms, p->fromssize, frompc ) ; + fromindex = (s32)searchpc( p->froms, ((s32)p->fromssize), frompc ) ; if( fromindex == -1 ) { - fromindex = p->fromssize ; + fromindex = (s32)p->fromssize ; p->fromssize++ ; - //if( fromindex >= N_FROMS ) { - //print("Error : From PC table overflow\r\n") ; - //goto overflow ; - //} + /*if( fromindex >= N_FROMS ) { + * print("Error : From PC table overflow\r\n") + * goto overflow + *}*/ p->froms[fromindex].frompc = frompc ; p->froms[fromindex].link = -1 ; }else { - toindex = p->froms[fromindex].link ; + toindex = ((s32)(p->froms[fromindex].link)); while(toindex != -1) { - toindex = (p->tossize - toindex)-1 ; + toindex = (((s32)p->tossize) - toindex)-1 ; if( p->tos[toindex].selfpc == selfpc ) { p->tos[toindex].count++ ; goto done ; } - toindex = p->tos[toindex].link ; + toindex = ((s32)(p->tos[toindex].link)) ; } } - //if( toindex == -1 ) { + /*if( toindex == -1 ) { */ p->tos-- ; p->tossize++ ; - //if( toindex >= N_TOS ) { - //print("Error : To PC table overflow\r\n") ; - //goto overflow ; - //} + /* if( toindex >= N_TOS ) { + * print("Error : To PC table overflow\r\n") + * goto overflow + *} */ p->tos[0].selfpc = selfpc ; p->tos[0].count = 1 ; p->tos[0].link = p->froms[fromindex].link ; - p->froms[fromindex].link = p->tossize-1 ; + p->froms[fromindex].link = ((s32)(p->tossize))-((s32)1); #endif done: p->state = GMON_PROF_ON; - goto enable_timer ; - //overflow: - p->state = GMON_PROF_ERROR; - enable_timer: + goto enable_timer_label ; + /* overflow: */ + /*p->state = GMON_PROF_ERROR */ + enable_timer_label: enable_timer(); return ; } diff --git a/lib/bsp/standalone/src/profile/profile_config.h b/lib/bsp/standalone/src/profile/profile_config.h old mode 100755 new mode 100644 index eaad2d65..47c756f8 --- a/lib/bsp/standalone/src/profile/profile_config.h +++ b/lib/bsp/standalone/src/profile/profile_config.h @@ -1,33 +1,43 @@ -// $Id: profile_config.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ @@ -35,14 +45,14 @@ #ifndef _PROFILE_CONFIG_H #define _PROFILE_CONFIG_H -#define BINSIZE 4 -#define SAMPLE_FREQ_HZ 100000 -#define TIMER_CLK_TICKS 1000 +#define BINSIZE 4U +#define SAMPLE_FREQ_HZ 100000U +#define TIMER_CLK_TICKS 1000U #define PROFILE_NO_FUNCPTR_FLAG 0 -#define PROFILE_TIMER_BASEADDR 0x00608000 -#define PROFILE_TIMER_INTR_ID 0 +#define PROFILE_TIMER_BASEADDR 0x00608000U +#define PROFILE_TIMER_INTR_ID 0U #define TIMER_CONNECT_INTC diff --git a/lib/bsp/standalone/src/profile/profile_hist.c b/lib/bsp/standalone/src/profile/profile_hist.c old mode 100755 new mode 100644 index 14e7fe2d..e9b5260d --- a/lib/bsp/standalone/src/profile/profile_hist.c +++ b/lib/bsp/standalone/src/profile/profile_hist.c @@ -1,33 +1,43 @@ -// $Id: profile_hist.c,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ @@ -45,29 +55,29 @@ #include "xil_types.h" -extern int binsize ; +extern u32 binsize ; u32 prof_pc ; void profile_intr_handler( void ) { - int j; + s32 j; #ifdef PROC_MICROBLAZE asm( "swi r14, r0, prof_pc" ) ; #elif defined PROC_PPC prof_pc = mfspr(SPR_SRR0); #else - // for cortexa9, lr is saved in asm interrupt handler + /* for cortexa9, lr is saved in asm interrupt handler */ #endif - //print("PC: "); putnum(prof_pc); print("\r\n"); + /* print("PC: "), putnum(prof_pc), print("\r\n"), */ for(j = 0; j < n_gmon_sections; j++ ){ - if((prof_pc >= _gmonparam[j].lowpc) && (prof_pc < _gmonparam[j].highpc)) { - _gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/(4 * binsize)]++; + if((prof_pc >= ((u32)_gmonparam[j].lowpc)) && (prof_pc < ((u32)_gmonparam[j].highpc))) { + _gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/((u32)4 * binsize)]++; break; } } - // Ack the Timer Interrupt + /* Ack the Timer Interrupt */ timer_ack(); } diff --git a/lib/bsp/standalone/src/profile/profile_mcount_arm.S b/lib/bsp/standalone/src/profile/profile_mcount_arm.S old mode 100755 new mode 100644 index fb4b2769..3149a9a4 --- a/lib/bsp/standalone/src/profile/profile_mcount_arm.S +++ b/lib/bsp/standalone/src/profile/profile_mcount_arm.S @@ -1,33 +1,43 @@ -// $Id: profile_mcount_arm.S,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ // based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI diff --git a/lib/bsp/standalone/src/profile/profile_mcount_mb.S b/lib/bsp/standalone/src/profile/profile_mcount_mb.S old mode 100755 new mode 100644 index f4ec7557..7d8c883a --- a/lib/bsp/standalone/src/profile/profile_mcount_mb.S +++ b/lib/bsp/standalone/src/profile/profile_mcount_mb.S @@ -1,43 +1,53 @@ -// $Id: profile_mcount_mb.S,v 1.1.2.1 2011/05/17 04:37:58 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ - .globl _mcount - .text + .globl _mcount + .text .align 2 .ent _mcount #ifndef PROFILE_NO_GRAPH - + _mcount: addi r1, r1, -48 swi r11, r1, 44 @@ -49,12 +59,12 @@ _mcount: swi r9, r1, 20 swi r10, r1, 16 swi r15, r1, 12 - add r6, r0, r15 + add r5, r0, r15 brlid r15, mcount - lwi r5, r1, 48 + add r6, r0, r16 lwi r11, r1, 44 - lwi r12, r1, 40 + lwi r12, r1, 40 lwi r5, r1, 36 lwi r6, r1, 32 lwi r7, r1, 28 @@ -66,5 +76,5 @@ _mcount: addi r1, r1, 48 #endif /* PROFILE_NO_GRAPH */ - - .end _mcount + + .end _mcount diff --git a/lib/bsp/standalone/src/profile/profile_mcount_ppc.S b/lib/bsp/standalone/src/profile/profile_mcount_ppc.S old mode 100755 new mode 100644 index 2c1dfd3a..69b9a238 --- a/lib/bsp/standalone/src/profile/profile_mcount_ppc.S +++ b/lib/bsp/standalone/src/profile/profile_mcount_ppc.S @@ -1,40 +1,50 @@ -// $Id: profile_mcount_ppc.S,v 1.1.2.1 2011/05/17 04:37:58 sadanan Exp $ /****************************************************************************** * -* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. * -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. * -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: +* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND +* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE +* and +* (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage of +* any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought +* by a third party) even if such damage or loss was reasonably foreseeable +* or Xilinx had been advised of the possibility of the same. * -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or environmental +* damage (individually and collectively, "Critical Applications"). +* Customer assumes the sole risk and liability of any use of Xilinx products in +* Critical Applications, subject only to applicable laws and regulations +* governing limitations on product liability. * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. * ******************************************************************************/ .globl _mcount - - #define _MCOUNT_STACK_FRAME 48 - .section .text + + #define _MCOUNT_STACK_FRAME 48 + .section .text .align 2 .type _mcount@function @@ -54,7 +64,7 @@ _mcount: mflr 4 stw 4, (_MCOUNT_STACK_FRAME+4)(1) lwz 3, (_MCOUNT_STACK_FRAME)(1) - lwz 3, 4(3) + lwz 3, 4(3) bl mcount lwz 4, (_MCOUNT_STACK_FRAME+4)(1) mtlr 4 @@ -67,7 +77,6 @@ _mcount: lwz 6, 20(1) lwz 5, 16(1) lwz 4, 12(1) - lwz 3, 8(1) + lwz 3, 8(1) addi 1,1, _MCOUNT_STACK_FRAME blr -